DevPCI.cpp@ 50125

Last change on this file since 50125 was 48947, checked in by vboxsync, 11 years ago
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1	/* $Id: DevPCI.cpp 48947 2013-10-07 21:41:00Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU PCI bus manager
21	*
22	* Copyright (c) 2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43	/*******************************************************************************
44	* Header Files *
45	*******************************************************************************/
46	#define LOG_GROUP LOG_GROUP_DEV_PCI
47	/* Hack to get PCIDEVICEINT declared at the right point - include "PCIInternal.h". */
48	#define PCI_INCLUDE_PRIVATE
49	#include <VBox/pci.h>
50	#include <VBox/vmm/pdmdev.h>
51	#include <iprt/asm.h>
52	#include <iprt/assert.h>
53	#include <iprt/string.h>
54
55	#include "VBoxDD.h"
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* PIIX3 ISA Bridge state.
63	*/
64	typedef struct PIIX3State
65	{
66	/** The PCI device of the bridge. */
67	PCIDEVICE dev;
68	} PIIX3State, PIIX3, *PPIIX3;
69
70	/**
71	* PCI Bus instance.
72	*/
73	typedef struct PCIBus
74	{
75	/** Bus number. */
76	int32_t iBus;
77	/** Start device number. */
78	int32_t iDevSearch;
79	/** Number of bridges attached to the bus. */
80	uint32_t cBridges;
81
82	uint32_t Alignment0;
83
84	/** Array of PCI devices. */
85	R3PTRTYPE(PPCIDEVICE) devices[256];
86	/** Array of bridges attached to the bus. */
87	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
88
89	/** R3 pointer to the device instance. */
90	PPDMDEVINSR3 pDevInsR3;
91	/** Pointer to the PCI R3 helpers. */
92	PCPDMPCIHLPR3 pPciHlpR3;
93
94	/** R0 pointer to the device instance. */
95	PPDMDEVINSR0 pDevInsR0;
96	/** Pointer to the PCI R0 helpers. */
97	PCPDMPCIHLPR0 pPciHlpR0;
98
99	/** RC pointer to the device instance. */
100	PPDMDEVINSRC pDevInsRC;
101	/** Pointer to the PCI RC helpers. */
102	PCPDMPCIHLPRC pPciHlpRC;
103
104	/** The PCI device for the PCI bridge. */
105	PCIDEVICE PciDev;
106
107	} PCIBUS;
108	/** Pointer to a PCIBUS instance. */
109	typedef PCIBUS *PPCIBUS;
110	typedef PCIBUS PCIBus;
111
112	/** @def PCI_IRQ_PINS
113	* Number of pins for interrupts (PIRQ#0...PIRQ#3)
114	*/
115	#define PCI_IRQ_PINS 4
116
117	/** @def PCI_APIC_IRQ_PINS
118	* Number of pins for interrupts if the APIC is used.
119	*/
120	#define PCI_APIC_IRQ_PINS 8
121
122	/**
123	* PCI Globals - This is the host-to-pci bridge and the root bus.
124	*/
125	typedef struct PCIGLOBALS
126	{
127	/** Irq levels for the four PCI Irqs.
128	* These count how many devices asserted
129	* the IRQ line. If greater 0 an IRQ is sent to the guest.
130	* If it drops to 0 the IRQ is deasserted.
131	*/
132	volatile uint32_t pci_irq_levels[PCI_IRQ_PINS];
133
134	#if 1 /* Will be moved into the BIOS soon. */
135	/** The next I/O port address which the PCI BIOS will use. */
136	uint32_t pci_bios_io_addr;
137	/** The next MMIO address which the PCI BIOS will use. */
138	uint32_t pci_bios_mem_addr;
139	/** Actual bus number. */
140	uint8_t uBus;
141	#endif
142
143	/** I/O APIC usage flag */
144	bool fUseIoApic;
145	/** I/O APIC irq levels */
146	volatile uint32_t pci_apic_irq_levels[PCI_APIC_IRQ_PINS];
147	/** ACPI IRQ level */
148	uint32_t acpi_irq_level;
149	/** ACPI PIC IRQ */
150	int acpi_irq;
151	/** Config register. */
152	uint32_t uConfigReg;
153
154	/** R3 pointer to the device instance. */
155	PPDMDEVINSR3 pDevInsR3;
156	/** R0 pointer to the device instance. */
157	PPDMDEVINSR0 pDevInsR0;
158	/** RC pointer to the device instance. */
159	PPDMDEVINSRC pDevInsRC;
160
161	#if HC_ARCH_BITS == 64
162	uint32_t Alignment0;
163	#endif
164
165	/** ISA bridge state. */
166	PIIX3 PIIX3State;
167	/** PCI bus which is attached to the host-to-PCI bridge. */
168	PCIBUS PciBus;
169
170	} PCIGLOBALS;
171	/** Pointer to per VM data. */
172	typedef PCIGLOBALS *PPCIGLOBALS;
173
174
175	/*******************************************************************************
176	* Defined Constants And Macros *
177	*******************************************************************************/
178
179	/** Converts a bus instance pointer to a device instance pointer. */
180	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
181	/** Converts a PCI bus device instance pointer to a PCIGLOBALS pointer. */
182	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
183	/** Converts a PCI bus device instance pointer to a PCIBUS pointer. */
184	#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->PciBus))
185
186	/** Converts a pointer to a PCI bus instance to a PCIGLOBALS pointer.
187	* @note This works only if the bus number is 0!!!
188	*/
189	#define PCIBUS_2_PCIGLOBALS(pPciBus) RT_FROM_MEMBER(pPciBus, PCIGLOBALS, PciBus)
190
191	/** @def PCI_LOCK
192	* Acquires the PDM lock. This is a NOP if locking is disabled. */
193	/** @def PCI_UNLOCK
194	* Releases the PDM lock. This is a NOP if locking is disabled. */
195	#define PCI_LOCK(pDevIns, rc) \
196	do { \
197	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
198	if (rc2 != VINF_SUCCESS) \
199	return rc2; \
200	} while (0)
201	#define PCI_UNLOCK(pDevIns) \
202	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
203
204	/** @def VBOX_PCI_SAVED_STATE_VERSION
205	* Saved state version of the PCI bus device.
206	*/
207	#define VBOX_PCI_SAVED_STATE_VERSION 3
208
209
210	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
211	/*******************************************************************************
212	* Internal Functions *
213	*******************************************************************************/
214	RT_C_DECLS_BEGIN
215
216	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTag);
217	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTag);
218	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
219	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
220	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
221	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
222
223	#ifdef IN_RING3
224	DECLINLINE(PPCIDEVICE) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus);
225	#endif
226
227	RT_C_DECLS_END
228
229	#define DEBUG_PCI
230
231	#define PCI_VENDOR_ID 0x00 /* 16 bits */
232	#define PCI_DEVICE_ID 0x02 /* 16 bits */
233	#define PCI_COMMAND 0x04 /* 16 bits */
234	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
235	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
236	#define PCI_CLASS_DEVICE 0x0a /* Device class */
237	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
238	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
239	#define PCI_MIN_GNT 0x3e /* 8 bits */
240	#define PCI_MAX_LAT 0x3f /* 8 bits */
241
242
243	#ifdef IN_RING3
244
245	static void pci_update_mappings(PCIDevice *d)
246	{
247	PPCIBUS pBus = d->Int.s.CTX_SUFF(pBus);
248	PCIIORegion *r;
249	int cmd, i;
250	uint32_t last_addr, new_addr, config_ofs;
251
252	cmd = RT_LE2H_U16((uint16_t )(d->config + PCI_COMMAND));
253	for(i = 0; i < PCI_NUM_REGIONS; i++) {
254	r = &d->Int.s.aIORegions[i];
255	if (i == PCI_ROM_SLOT) {
256	config_ofs = 0x30;
257	} else {
258	config_ofs = 0x10 + i * 4;
259	}
260	if (r->size != 0) {
261	if (r->type & PCI_ADDRESS_SPACE_IO) {
262	if (cmd & PCI_COMMAND_IO) {
263	new_addr = RT_LE2H_U32((uint32_t )(d->config +
264	config_ofs));
265	new_addr = new_addr & ~(r->size - 1);
266	last_addr = new_addr + r->size - 1;
267	/* NOTE: we have only 64K ioports on PC */
268	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
269	last_addr >= 0x10000) {
270	new_addr = ~0U;
271	}
272	} else {
273	new_addr = ~0U;
274	}
275	} else {
276	if (cmd & PCI_COMMAND_MEMORY) {
277	new_addr = RT_LE2H_U32((uint32_t )(d->config +
278	config_ofs));
279	/* the ROM slot has a specific enable bit */
280	if (i == PCI_ROM_SLOT && !(new_addr & 1))
281	goto no_mem_map;
282	new_addr = new_addr & ~(r->size - 1);
283	last_addr = new_addr + r->size - 1;
284	/* NOTE: we do not support wrapping */
285	/* XXX: as we cannot support really dynamic
286	mappings, we handle specific values as invalid
287	mappings. */
288	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
289	last_addr == ~0U) {
290	new_addr = ~0U;
291	}
292	} else {
293	no_mem_map:
294	new_addr = ~0U;
295	}
296	}
297	/* now do the real mapping */
298	if (new_addr != r->addr) {
299	if (r->addr != ~0U) {
300	if (r->type & PCI_ADDRESS_SPACE_IO) {
301	int devclass;
302	/* NOTE: specific hack for IDE in PC case:
303	only one byte must be mapped. */
304	devclass = d->config[0x0a] \| (d->config[0x0b] << 8);
305	if (devclass == 0x0101 && r->size == 4) {
306	int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr + 2, 1);
307	AssertRC(rc);
308	} else {
309	int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr, r->size);
310	AssertRC(rc);
311	}
312	} else {
313	RTGCPHYS GCPhysBase = r->addr;
314	int rc;
315	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, d->pDevIns, GCPhysBase))
316	{
317	/* unmap it. */
318	rc = r->map_func(d, i, NIL_RTGCPHYS, r->size, (PCIADDRESSSPACE)(r->type));
319	AssertRC(rc);
320	rc = PDMDevHlpMMIO2Unmap(d->pDevIns, i, GCPhysBase);
321	}
322	else
323	rc = PDMDevHlpMMIODeregister(d->pDevIns, GCPhysBase, r->size);
324	AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, d->name, i, GCPhysBase, r->size));
325	}
326	}
327	r->addr = new_addr;
328	if (r->addr != ~0U) {
329	int rc = r->map_func(d, i,
330	r->addr + (r->type & PCI_ADDRESS_SPACE_IO ? 0 : 0),
331	r->size, (PCIADDRESSSPACE)(r->type));
332	AssertRC(rc);
333	}
334	}
335	}
336	}
337	}
338
339
340	static DECLCALLBACK(uint32_t) pci_default_read_config(PCIDevice *d, uint32_t address, unsigned len)
341	{
342	uint32_t val;
343	switch(len) {
344	case 1:
345	val = d->config[address];
346	break;
347	case 2:
348	val = RT_LE2H_U16((uint16_t )(d->config + address));
349	break;
350	default:
351	case 4:
352	val = RT_LE2H_U32((uint32_t )(d->config + address));
353	break;
354	}
355	return val;
356	}
357
358	static DECLCALLBACK(void) pci_default_write_config(PCIDevice *d, uint32_t address, uint32_t val, unsigned len)
359	{
360	int can_write;
361	unsigned i;
362	uint32_t end, addr;
363
364	if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) \|\|
365	(address >= 0x30 && address < 0x34))) {
366	PCIIORegion *r;
367	int reg;
368
369	if ( address >= 0x30 ) {
370	reg = PCI_ROM_SLOT;
371	}else{
372	reg = (address - 0x10) >> 2;
373	}
374	r = &d->Int.s.aIORegions[reg];
375	if (r->size == 0)
376	goto default_config;
377	/* compute the stored value */
378	if (reg == PCI_ROM_SLOT) {
379	/* keep ROM enable bit */
380	val &= (~(r->size - 1)) \| 1;
381	} else {
382	val &= ~(r->size - 1);
383	val \|= r->type;
384	}
385	(uint32_t )(d->config + address) = RT_H2LE_U32(val);
386	pci_update_mappings(d);
387	return;
388	}
389	default_config:
390	/* not efficient, but simple */
391	addr = address;
392	for(i = 0; i < len; i++) {
393	/* default read/write accesses */
394	switch(d->config[0x0e]) {
395	case 0x00: /* normal device */
396	case 0x80: /* multi-function device */
397	switch(addr) {
398	case 0x00:
399	case 0x01:
400	case 0x02:
401	case 0x03:
402	case 0x08:
403	case 0x09:
404	case 0x0a:
405	case 0x0b:
406	case 0x0e:
407	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: /* base */
408	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
409	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
410	case 0x2c: case 0x2d: /* subsystem ID */
411	case 0x2e: case 0x2f: /* vendor ID */
412	case 0x30: case 0x31: case 0x32: case 0x33: /* rom */
413	case 0x34: /* Capabilities pointer. */
414	case 0x3d: /* Interrupt pin. */
415	can_write = 0;
416	break;
417	default:
418	can_write = 1;
419	break;
420	}
421	break;
422	default:
423	case 0x01: /* bridge */
424	switch(addr) {
425	case 0x00:
426	case 0x01:
427	case 0x02:
428	case 0x03:
429	case 0x08:
430	case 0x09:
431	case 0x0a:
432	case 0x0b:
433	case 0x0e:
434	case 0x38: case 0x39: case 0x3a: case 0x3b: /* rom */
435	case 0x3d:
436	can_write = 0;
437	break;
438	default:
439	can_write = 1;
440	break;
441	}
442	break;
443	}
444	#ifdef VBOX
445	if (addr == 0x05) /* Command register, bits 8-15. */
446	{
447	/* don't change reserved bits (11-15) */
448	val &= UINT32_C(~0xf8);
449	d->config[addr] = val;
450	}
451	else if (addr == 0x06) /* Status register, bits 0-7. */
452	{
453	/* don't change read-only bits => actually all lower bits are read-only */
454	val &= UINT32_C(~0xff);
455	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
456	d->config[addr] &= ~val;
457	}
458	else if (addr == 0x07) /* Status register, bits 8-15. */
459	{
460	/* don't change read-only bits */
461	val &= UINT32_C(~0x06);
462	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
463	d->config[addr] &= ~val;
464	}
465	else
466	#endif
467	if (can_write) {
468	d->config[addr] = val;
469	}
470	addr++;
471	val >>= 8;
472	}
473
474	end = address + len;
475	if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
476	/* if the command register is modified, we must modify the mappings */
477	pci_update_mappings(d);
478	}
479	}
480
481	#endif /* IN_RING3 */
482
483	static int pci_data_write(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
484	{
485	uint8_t iBus, iDevice;
486	uint32_t config_addr;
487
488	Log(("pci_data_write: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
489
490	if (!(pGlobals->uConfigReg & (1 << 31))) {
491	return VINF_SUCCESS;
492	}
493	if ((pGlobals->uConfigReg & 0x3) != 0) {
494	return VINF_SUCCESS;
495	}
496	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
497	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
498	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
499	if (iBus != 0)
500	{
501	if (pGlobals->PciBus.cBridges)
502	{
503	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
504	PPCIDEVICE pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
505	if (pBridgeDevice)
506	{
507	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
508	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, val, len);
509	}
510	#else
511	return VINF_IOM_R3_IOPORT_WRITE;
512	#endif
513	}
514	}
515	else
516	{
517	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
518	if (pci_dev)
519	{
520	#ifdef IN_RING3
521	Log(("pci_config_write: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, val, len));
522	pci_dev->Int.s.pfnConfigWrite(pci_dev, config_addr, val, len);
523	#else
524	return VINF_IOM_R3_IOPORT_WRITE;
525	#endif
526	}
527	}
528	return VINF_SUCCESS;
529	}
530
531	static int pci_data_read(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
532	{
533	uint8_t iBus, iDevice;
534	uint32_t config_addr;
535
536	*pu32 = 0xffffffff;
537
538	if (!(pGlobals->uConfigReg & (1 << 31)))
539	return VINF_SUCCESS;
540	if ((pGlobals->uConfigReg & 0x3) != 0)
541	return VINF_SUCCESS;
542	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
543	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
544	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
545	if (iBus != 0)
546	{
547	if (pGlobals->PciBus.cBridges)
548	{
549	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
550	PPCIDEVICE pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
551	if (pBridgeDevice)
552	{
553	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
554	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, len);
555	}
556	#else
557	NOREF(len);
558	return VINF_IOM_R3_IOPORT_READ;
559	#endif
560	}
561	}
562	else
563	{
564	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
565	if (pci_dev)
566	{
567	#ifdef IN_RING3
568	*pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev, config_addr, len);
569	Log(("pci_config_read: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, *pu32, len));
570	#else
571	NOREF(len);
572	return VINF_IOM_R3_IOPORT_READ;
573	#endif
574	}
575	}
576
577	return VINF_SUCCESS;
578	}
579
580
581
582	/* return the global irq number corresponding to a given device irq
583	pin. We could also use the bus number to have a more precise
584	mapping.
585	This is the implementation note described in the PCI spec chapter 2.2.6 */
586	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
587	{
588	int slot_addend;
589	slot_addend = (uDevFn >> 3) - 1;
590	return (irq_num + slot_addend) & 3;
591	}
592
593	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
594	{
595	return (irq_num + (uDevFn >> 3)) & 7;
596	}
597
598	static inline int get_pci_irq_apic_level(PPCIGLOBALS pGlobals, int irq_num)
599	{
600	return (pGlobals->pci_apic_irq_levels[irq_num] != 0);
601	}
602
603	static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int acpi_irq, uint32_t uTagSrc)
604	{
605	/* This is only allowed to be called with a pointer to the host bus. */
606	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
607
608	if (acpi_irq == -1) {
609	int apic_irq, apic_level;
610	PPCIGLOBALS pGlobals = PCIBUS_2_PCIGLOBALS(pBus);
611	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
612
613	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
614	ASMAtomicIncU32(&pGlobals->pci_apic_irq_levels[irq_num]);
615	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
616	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
617
618	apic_irq = irq_num + 0x10;
619	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
620	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
621	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
622	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
623
624	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
625	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
626	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
627	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
628	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
629	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
630	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
631	}
632	} else {
633	Log3(("apic_set_irq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
634	R3STRING(pPciDev->name), irq_num1, iLevel, acpi_irq));
635	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), acpi_irq, iLevel, uTagSrc);
636	}
637	}
638
639	DECLINLINE(int) get_pci_irq_level(PPCIGLOBALS pGlobals, int irq_num)
640	{
641	return (pGlobals->pci_irq_levels[irq_num] != 0);
642	}
643
644	/**
645	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
646	*
647	* @param pDevIns Device instance of the host PCI Bus.
648	* @param uDevFn The device number on the host bus which will raise the IRQ
649	* @param pPciDev The PCI device structure which raised the interrupt.
650	* @param iIrq IRQ number to set.
651	* @param iLevel IRQ level.
652	* @param uTagSrc The IRQ tag and source ID (for tracing).
653	* @remark uDevFn and pPciDev->devfn are not the same if the device is behind a bridge.
654	* In that case uDevFn will be the slot of the bridge which is needed to calculate the
655	* PIRQ value.
656	*/
657	static void pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
658	{
659	PPCIBUS pBus = &pGlobals->PciBus;
660	uint8_t *pbCfg = pGlobals->PIIX3State.dev.config;
661	const bool fIsAcpiDevice = pPciDev->config[2] == 0x13 && pPciDev->config[3] == 0x71;
662	/* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
663	* is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
664	* See the \_SB_.PCI0._PRT method in vbox.dsl.
665	*/
666	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
667	int pic_irq, pic_level;
668
669	/* Check if the state changed. */
670	if (pPciDev->Int.s.uIrqPinState != iLevel)
671	{
672	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
673
674	/* Send interrupt to I/O APIC only. */
675	if (fIsApicEnabled)
676	{
677	if (fIsAcpiDevice)
678	/*
679	* ACPI needs special treatment since SCI is hardwired and
680	* should not be affected by PCI IRQ routing tables at the
681	* same time SCI IRQ is shared in PCI sense hence this
682	* kludge (i.e. we fetch the hardwired value from ACPIs
683	* PCI device configuration space).
684	*/
685	apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->config[PCI_INTERRUPT_LINE], uTagSrc);
686	else
687	apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
688	return;
689	}
690
691	if (fIsAcpiDevice)
692	{
693	/* As per above treat ACPI in a special way */
694	pic_irq = pPciDev->config[PCI_INTERRUPT_LINE];
695	pGlobals->acpi_irq = pic_irq;
696	pGlobals->acpi_irq_level = iLevel & PDM_IRQ_LEVEL_HIGH;
697	}
698	else
699	{
700	int irq_num;
701	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
702
703	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
704	ASMAtomicIncU32(&pGlobals->pci_irq_levels[irq_num]);
705	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
706	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
707
708	/* now we change the pic irq level according to the piix irq mappings */
709	pic_irq = pbCfg[0x60 + irq_num];
710	if (pic_irq >= 16)
711	{
712	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
713	{
714	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
715	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
716	}
717
718	return;
719	}
720	}
721
722	/* the pic level is the logical OR of all the PCI irqs mapped to it */
723	pic_level = 0;
724	if (pic_irq == pbCfg[0x60])
725	pic_level \|= get_pci_irq_level(pGlobals, 0);
726	if (pic_irq == pbCfg[0x61])
727	pic_level \|= get_pci_irq_level(pGlobals, 1);
728	if (pic_irq == pbCfg[0x62])
729	pic_level \|= get_pci_irq_level(pGlobals, 2);
730	if (pic_irq == pbCfg[0x63])
731	pic_level \|= get_pci_irq_level(pGlobals, 3);
732	if (pic_irq == pGlobals->acpi_irq)
733	pic_level \|= pGlobals->acpi_irq_level;
734
735	Log3(("pciSetIrq: %s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
736	R3STRING(pPciDev->name), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
737	pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level, uTagSrc);
738
739	/** @todo optimize pci irq flip-flop some rainy day. */
740	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
741	pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
742	}
743	}
744
745
746	/**
747	* @interface_method_impl{PDMPCIBUSREG,pfnSetIrq}
748	*/
749	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
750	{
751	pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel, uTagSrc);
752	}
753
754	#ifdef IN_RING3
755
756	/**
757	* Finds a bridge on the bus which contains the destination bus.
758	*
759	* @return Pointer to the device instance data of the bus or
760	* NULL if no bridge was found.
761	* @param pBus Pointer to the bus to search on.
762	* @param iBus Destination bus number.
763	*/
764	DECLINLINE(PPCIDEVICE) pciR3FindBridge(PPCIBUS pBus, uint8_t iBus)
765	{
766	/* Search for a fitting bridge. */
767	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
768	{
769	/*
770	* Examine secondary and subordinate bus number.
771	* If the target bus is in the range we pass the request on to the bridge.
772	*/
773	PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
774	AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
775	("Device is not a PCI bridge but on the list of PCI bridges\n"));
776
777	if ( iBus >= pBridgeTemp->config[VBOX_PCI_SECONDARY_BUS]
778	&& iBus <= pBridgeTemp->config[VBOX_PCI_SUBORDINATE_BUS])
779	return pBridgeTemp;
780	}
781
782	/* Nothing found. */
783	return NULL;
784	}
785
786	static void pciR3Piix3Reset(PIIX3State *d)
787	{
788	uint8_t *pci_conf = d->dev.config;
789
790	pci_conf[0x04] = 0x07; /* master, memory and I/O */
791	pci_conf[0x05] = 0x00;
792	pci_conf[0x06] = 0x00;
793	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
794	pci_conf[0x4c] = 0x4d;
795	pci_conf[0x4e] = 0x03;
796	pci_conf[0x4f] = 0x00;
797	pci_conf[0x60] = 0x80;
798	pci_conf[0x69] = 0x02;
799	pci_conf[0x70] = 0x80;
800	pci_conf[0x76] = 0x0c;
801	pci_conf[0x77] = 0x0c;
802	pci_conf[0x78] = 0x02;
803	pci_conf[0x79] = 0x00;
804	pci_conf[0x80] = 0x00;
805	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
806	pci_conf[0xa0] = 0x08;
807	pci_conf[0xa0] = 0x08;
808	pci_conf[0xa2] = 0x00;
809	pci_conf[0xa3] = 0x00;
810	pci_conf[0xa4] = 0x00;
811	pci_conf[0xa5] = 0x00;
812	pci_conf[0xa6] = 0x00;
813	pci_conf[0xa7] = 0x00;
814	pci_conf[0xa8] = 0x0f;
815	pci_conf[0xaa] = 0x00;
816	pci_conf[0xab] = 0x00;
817	pci_conf[0xac] = 0x00;
818	pci_conf[0xae] = 0x00;
819	}
820
821	static void pci_config_writel(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
822	{
823	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
824	(uDevFn << 8) \| addr;
825	pci_data_write(pGlobals, 0, val, 4);
826	}
827
828	static void pci_config_writew(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
829	{
830	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
831	(uDevFn << 8) \| (addr & ~3);
832	pci_data_write(pGlobals, addr & 3, val, 2);
833	}
834
835	static void pci_config_writeb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
836	{
837	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
838	(uDevFn << 8) \| (addr & ~3);
839	pci_data_write(pGlobals, addr & 3, val, 1);
840	}
841
842	static uint32_t pci_config_readl(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
843	{
844	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
845	(uDevFn << 8) \| addr;
846	uint32_t u32Val;
847	int rc = pci_data_read(pGlobals, 0, 4, &u32Val);
848	AssertRC(rc);
849	return u32Val;
850	}
851
852	static uint32_t pci_config_readw(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
853	{
854	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
855	(uDevFn << 8) \| (addr & ~3);
856	uint32_t u32Val;
857	int rc = pci_data_read(pGlobals, addr & 3, 2, &u32Val);
858	AssertRC(rc);
859	return u32Val;
860	}
861
862	static uint32_t pci_config_readb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
863	{
864	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
865	(uDevFn << 8) \| (addr & ~3);
866	uint32_t u32Val;
867	int rc = pci_data_read(pGlobals, addr & 3, 1, &u32Val);
868	AssertRC(rc);
869	return u32Val;
870	}
871
872	/* host irqs corresponding to PCI irqs A-D */
873	static const uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; /* bird: added const */
874
875	static void pci_set_io_region_addr(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int region_num, uint32_t addr)
876	{
877	uint16_t cmd;
878	uint32_t ofs;
879
880	if ( region_num == PCI_ROM_SLOT )
881	ofs = 0x30;
882	else
883	ofs = 0x10 + region_num * 4;
884
885	/* Read memory type first. */
886	uint8_t uRessourceType = pci_config_readb(pGlobals, uBus, uDevFn, ofs);
887
888	/* Read command register. */
889	cmd = pci_config_readw(pGlobals, uBus, uDevFn, PCI_COMMAND);
890	if ( region_num == PCI_ROM_SLOT )
891	cmd \|= 2;
892	else if ((uRessourceType & 0x01) == 1) /* Test if region is I/O space. */
893	cmd \|= 1; /* Enable I/O space access. */
894	else /* The region is MMIO. */
895	cmd \|= 2; /* Enable MMIO access. */
896
897	/* Write address of the device. */
898	pci_config_writel(pGlobals, uBus, uDevFn, ofs, addr);
899
900	/* enable memory mappings */
901	pci_config_writew(pGlobals, uBus, uDevFn, PCI_COMMAND, cmd);
902	}
903
904	static void pci_bios_init_device(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
905	{
906	uint32_t *paddr;
907	int i, pin, pic_irq;
908	uint16_t devclass, vendor_id, device_id;
909
910	devclass = pci_config_readw(pGlobals, uBus, uDevFn, PCI_CLASS_DEVICE);
911	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
912	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
913
914	/* Check if device is present. */
915	if (vendor_id != 0xffff)
916	{
917	switch(devclass)
918	{
919	case 0x0101:
920	if ( (vendor_id == 0x8086)
921	&& (device_id == 0x7010 \|\| device_id == 0x7111 \|\| device_id == 0x269e))
922	{
923	/* PIIX3, PIIX4 or ICH6 IDE */
924	pci_config_writew(pGlobals, uBus, uDevFn, 0x40, 0x8000); /* enable IDE0 */
925	pci_config_writew(pGlobals, uBus, uDevFn, 0x42, 0x8000); /* enable IDE1 */
926	goto default_map;
927	}
928	else
929	{
930	/* IDE: we map it as in ISA mode */
931	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x1f0);
932	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 1, 0x3f4);
933	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 2, 0x170);
934	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 3, 0x374);
935	}
936	break;
937	case 0x0300:
938	if (vendor_id != 0x80ee)
939	goto default_map;
940	/* VGA: map frame buffer to default Bochs VBE address */
941	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0xE0000000);
942	/*
943	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
944	* only the framebuffer (i.e., a memory region) is explicitly registered via
945	* pci_set_io_region_addr, so I/O decoding must be enabled manually.
946	*/
947	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
948	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
949	\| 1 /* Enable I/O space access. */);
950	break;
951	case 0x0800:
952	/* PIC */
953	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
954	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
955	if (vendor_id == 0x1014)
956	{
957	/* IBM */
958	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
959	{
960	/* MPIC & MPIC2 */
961	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
962	}
963	}
964	break;
965	case 0xff00:
966	if ( (vendor_id == 0x0106b)
967	&& (device_id == 0x0017 \|\| device_id == 0x0022))
968	{
969	/* macio bridge */
970	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000);
971	}
972	break;
973	case 0x0604:
974	{
975	/* Init PCI-to-PCI bridge. */
976	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus);
977
978	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
979	pGlobals->uBus++;
980	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
981	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
982
983	/* Add position of this bridge into the array. */
984	paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
985
986	/*
987	* The I/O range for the bridge must be aligned to a 4KB boundary.
988	* This does not change anything really as the access to the device is not going
989	* through the bridge but we want to be compliant to the spec.
990	*/
991	if ((pGlobals->pci_bios_io_addr % 4096) != 0)
992	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
993	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_io_addr));
994	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->pci_bios_io_addr >> 8) & 0xf0);
995
996	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
997	if ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0)
998	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
999	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_mem_addr));
1000	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xffff0));
1001
1002	/* Save values to compare later to. */
1003	uint32_t u32IoAddressBase = pGlobals->pci_bios_io_addr;
1004	uint32_t u32MMIOAddressBase = pGlobals->pci_bios_mem_addr;
1005
1006	/* Init devices behind the bridge and possibly other bridges as well. */
1007	for (int iDev = 0; iDev <= 255; iDev++)
1008	pci_bios_init_device(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1009
1010	/* The number of bridges behind the this one is now available. */
1011	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1012
1013	/*
1014	* Set I/O limit register. If there is no device with I/O space behind the bridge
1015	* we set a lower value than in the base register.
1016	* The result with a real bridge is that no I/O transactions are passed to the secondary
1017	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1018	*/
1019	if ((u32IoAddressBase != pGlobals->pci_bios_io_addr) && ((pGlobals->pci_bios_io_addr % 4096) != 0))
1020	{
1021	/* The upper boundary must be one byte less than a 4KB boundary. */
1022	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
1023	}
1024	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->pci_bios_io_addr >> 8) & 0xf0) - 1);
1025
1026	/* Same with the MMIO limit register but with 1MB boundary here. */
1027	if ((u32MMIOAddressBase != pGlobals->pci_bios_mem_addr) && ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0))
1028	{
1029	/* The upper boundary must be one byte less than a 1MB boundary. */
1030	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
1031	}
1032	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xfff0)) - 1);
1033
1034	/*
1035	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1036	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1037	* the base register than in the limit register.
1038	*/
1039	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
1040	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
1041	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
1042	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
1043	break;
1044	}
1045	default:
1046	default_map:
1047	{
1048	/* default memory mappings */
1049	/*
1050	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
1051	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
1052	*/
1053	for(i = 0; i < (PCI_NUM_REGIONS-1); i++)
1054	{
1055	uint32_t u32Size;
1056	uint8_t u8RessourceType;
1057	uint32_t u32Address = 0x10 + i * 4;
1058
1059	/* Calculate size. */
1060	u8RessourceType = pci_config_readb(pGlobals, uBus, uDevFn, u32Address);
1061	pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff));
1062	u32Size = pci_config_readl(pGlobals, uBus, uDevFn, u32Address);
1063	/* Clear resource information depending on resource type. */
1064	if ((u8RessourceType & 0x01) == 1) /* I/O */
1065	u32Size &= ~(0x01);
1066	else /* MMIO */
1067	u32Size &= ~(0x0f);
1068
1069	/*
1070	* Invert all bits and add 1 to get size of the region.
1071	* (From PCI implementation note)
1072	*/
1073	if (((u8RessourceType & 0x01) == 1) && (u32Size & UINT32_C(0xffff0000)) == 0)
1074	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
1075	else
1076	u32Size = (~u32Size) + 1;
1077
1078	Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, i, uDevFn, uBus, u32Size));
1079
1080	if (u32Size)
1081	{
1082	if ((u8RessourceType & 0x01) == 1)
1083	paddr = &pGlobals->pci_bios_io_addr;
1084	else
1085	paddr = &pGlobals->pci_bios_mem_addr;
1086	paddr = (paddr + u32Size - 1) & ~(u32Size - 1);
1087	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, ((u8RessourceType & 0x01) == 1 ? "I/O" : "MMIO"), i, *paddr));
1088	pci_set_io_region_addr(pGlobals, uBus, uDevFn, i, *paddr);
1089	*paddr += u32Size;
1090	Log(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1091	}
1092	}
1093	break;
1094	}
1095	}
1096
1097	/* map the interrupt */
1098	pin = pci_config_readb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_PIN);
1099	if (pin != 0)
1100	{
1101	uint8_t uBridgeDevFn = uDevFn;
1102	pin--;
1103
1104	/* We need to go up to the host bus to see which irq this device will assert there. */
1105	while (cBridgeDepth != 0)
1106	{
1107	/* Get the pin the device would assert on the bridge. */
1108	pin = ((uBridgeDevFn >> 3) + pin) & 3;
1109	uBridgeDevFn = paBridgePositions[cBridgeDepth];
1110	cBridgeDepth--;
1111	}
1112
1113	pin = pci_slot_get_pirq(uDevFn, pin);
1114	pic_irq = pci_irqs[pin];
1115	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);
1116	}
1117	}
1118	}
1119
1120	#endif /* IN_RING3 */
1121
1122
1123	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
1124
1125	/**
1126	* @callback_method_impl{FNIOMIOPORTOUT, PCI address}
1127	*/
1128	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1129	{
1130	Log(("pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1131	NOREF(pvUser);
1132	if (cb == 4)
1133	{
1134	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1135	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
1136	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
1137	PCI_UNLOCK(pDevIns);
1138	}
1139	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1140	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1141	return VINF_SUCCESS;
1142	}
1143
1144
1145	/**
1146	* @callback_method_impl{FNIOMIOPORTIN, PCI address}
1147	*/
1148	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1149	{
1150	NOREF(pvUser);
1151	if (cb == 4)
1152	{
1153	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1154	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
1155	*pu32 = pThis->uConfigReg;
1156	PCI_UNLOCK(pDevIns);
1157	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
1158	return VINF_SUCCESS;
1159	}
1160	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1161	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1162	Log(("pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
1163	return VERR_IOM_IOPORT_UNUSED;
1164	}
1165
1166
1167	/**
1168	* @callback_method_impl{FNIOMIOPORTOUT, PCI data}
1169	*/
1170	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1171	{
1172	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1173	NOREF(pvUser);
1174	int rc = VINF_SUCCESS;
1175	if (!(Port % cb))
1176	{
1177	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
1178	rc = pci_data_write(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
1179	PCI_UNLOCK(pDevIns);
1180	}
1181	else
1182	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
1183	return rc;
1184	}
1185
1186
1187	/**
1188	* @callback_method_impl{FNIOMIOPORTIN, PCI data}
1189	*/
1190	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1191	{
1192	NOREF(pvUser);
1193	if (!(Port % cb))
1194	{
1195	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
1196	int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
1197	PCI_UNLOCK(pDevIns);
1198	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
1199	return rc;
1200	}
1201	AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
1202	return VERR_IOM_IOPORT_UNUSED;
1203	}
1204
1205	#ifdef IN_RING3
1206
1207	/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
1208
1209	/**
1210	* Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
1211	*
1212	* @returns VBox status code.
1213	* @param pBus The bus to save.
1214	* @param pSSM The saved state handle.
1215	*/
1216	static int pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
1217	{
1218	/*
1219	* Iterate thru all the devices.
1220	*/
1221	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1222	{
1223	PPCIDEVICE pDev = pBus->devices[i];
1224	if (pDev)
1225	{
1226	SSMR3PutU32(pSSM, i);
1227	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1228
1229	int rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1230	if (RT_FAILURE(rc))
1231	return rc;
1232	}
1233	}
1234	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1235	}
1236
1237
1238	/**
1239	* @callback_method_impl{FNSSMDEVSAVEEXEC}
1240	*/
1241	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1242	{
1243	uint32_t i;
1244	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1245
1246	/*
1247	* Bus state data.
1248	*/
1249	SSMR3PutU32(pSSM, pThis->uConfigReg);
1250	SSMR3PutBool(pSSM, pThis->fUseIoApic);
1251
1252	/*
1253	* Save IRQ states.
1254	*/
1255	for (i = 0; i < PCI_IRQ_PINS; i++)
1256	SSMR3PutU32(pSSM, pThis->pci_irq_levels[i]);
1257	for (i = 0; i < PCI_APIC_IRQ_PINS; i++)
1258	SSMR3PutU32(pSSM, pThis->pci_apic_irq_levels[i]);
1259
1260	SSMR3PutU32(pSSM, pThis->acpi_irq_level);
1261	SSMR3PutS32(pSSM, pThis->acpi_irq);
1262
1263	SSMR3PutU32(pSSM, ~0); /* separator */
1264
1265	/*
1266	* Join paths with pcibridgeR3SaveExec.
1267	*/
1268	return pciR3CommonSaveExec(&pThis->PciBus, pSSM);
1269	}
1270
1271
1272	/**
1273	* Common routine for restoring the config registers of a PCI device.
1274	*
1275	* @param pDev The PCI device.
1276	* @param pbSrcConfig The configuration register values to be loaded.
1277	* @param fIsBridge Whether this is a bridge device or not.
1278	*/
1279	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1280	{
1281	/*
1282	* This table defines the fields for normal devices and bridge devices, and
1283	* the order in which they need to be restored.
1284	*/
1285	static const struct PciField
1286	{
1287	uint8_t off;
1288	uint8_t cb;
1289	uint8_t fWritable;
1290	uint8_t fBridge;
1291	const char *pszName;
1292	} s_aFields[] =
1293	{
1294	/* off,cb,fW,fB, pszName */
1295	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1296	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1297	{ 0x06, 2, 1, 3, "STATUS" },
1298	{ 0x08, 1, 0, 3, "REVISION_ID" },
1299	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1300	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1301	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1302	{ 0x0c, 1, 1, 3, "CACHE_LINE_SIZE" },
1303	{ 0x0d, 1, 1, 3, "LATENCY_TIMER" },
1304	{ 0x0e, 1, 0, 3, "HEADER_TYPE" },
1305	{ 0x0f, 1, 1, 3, "BIST" },
1306	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1307	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1308	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1309	{ 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1310	{ 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1311	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1312	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1313	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1314	{ 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1315	{ 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1316	{ 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1317	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1318	{ 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1319	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1320	{ 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1321	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1322	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1323	{ 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1324	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1325	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1326	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1327	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1328	{ 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1329	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1330	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1331	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1332	{ 0x38, 4, 1, 1, "RESERVED_38" }, // ???
1333	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1334	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1335	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1336	{ 0x3e, 1, 0, 1, "MIN_GNT" },
1337	{ 0x3e, 2, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !?
1338	{ 0x3f, 1, 0, 1, "MAX_LAT" },
1339	/* The COMMAND register must come last as it requires the ADDRESS
1340	registers to be restored before we pretent to change it from 0 to
1341	whatever value the guest assigned it. */
1342	{ 0x04, 2, 1, 3, "COMMAND" },
1343	};
1344
1345	#ifdef RT_STRICT
1346	/* Check that we've got full register coverage. */
1347	uint32_t bmDevice[0x40 / 32];
1348	uint32_t bmBridge[0x40 / 32];
1349	RT_ZERO(bmDevice);
1350	RT_ZERO(bmBridge);
1351	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1352	{
1353	uint8_t off = s_aFields[i].off;
1354	uint8_t cb = s_aFields[i].cb;
1355	uint8_t f = s_aFields[i].fBridge;
1356	while (cb-- > 0)
1357	{
1358	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1359	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1360	if (f & 1) ASMBitSet(bmDevice, off);
1361	if (f & 2) ASMBitSet(bmBridge, off);
1362	off++;
1363	}
1364	}
1365	for (uint32_t off = 0; off < 0x40; off++)
1366	{
1367	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1368	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1369	}
1370	#endif
1371
1372	/*
1373	* Loop thru the fields covering the 64 bytes of standard registers.
1374	*/
1375	uint8_t const fBridge = fIsBridge ? 2 : 1;
1376	uint8_t *pbDstConfig = &pDev->config[0];
1377	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1378	if (s_aFields[i].fBridge & fBridge)
1379	{
1380	uint8_t const off = s_aFields[i].off;
1381	uint8_t const cb = s_aFields[i].cb;
1382	uint32_t u32Src;
1383	uint32_t u32Dst;
1384	switch (cb)
1385	{
1386	case 1:
1387	u32Src = pbSrcConfig[off];
1388	u32Dst = pbDstConfig[off];
1389	break;
1390	case 2:
1391	u32Src = (uint16_t const )&pbSrcConfig[off];
1392	u32Dst = (uint16_t const )&pbDstConfig[off];
1393	break;
1394	case 4:
1395	u32Src = (uint32_t const )&pbSrcConfig[off];
1396	u32Dst = (uint32_t const )&pbDstConfig[off];
1397	break;
1398	default:
1399	AssertFailed();
1400	continue;
1401	}
1402
1403	if ( u32Src != u32Dst
1404	\|\| off == VBOX_PCI_COMMAND)
1405	{
1406	if (u32Src != u32Dst)
1407	{
1408	if (!s_aFields[i].fWritable)
1409	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1410	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1411	else
1412	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1413	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1414	}
1415	if (off == VBOX_PCI_COMMAND)
1416	PCIDevSetCommand(pDev, 0); /* For remapping, see pciR3CommonLoadExec. */
1417	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1418	}
1419	}
1420
1421	/*
1422	* The device dependent registers.
1423	*
1424	* We will not use ConfigWrite here as we have no clue about the size
1425	* of the registers, so the device is responsible for correctly
1426	* restoring functionality governed by these registers.
1427	*/
1428	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1429	if (pbDstConfig[off] != pbSrcConfig[off])
1430	{
1431	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1432	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1433	pbDstConfig[off] = pbSrcConfig[off];
1434	}
1435	}
1436
1437
1438	/**
1439	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
1440	*
1441	* @returns VBox status code.
1442	* @param pBus The bus which data is being loaded.
1443	* @param pSSM The saved state handle.
1444	* @param uVersion The data version.
1445	* @param uPass The pass.
1446	*/
1447	static DECLCALLBACK(int) pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1448	{
1449	uint32_t u32;
1450	uint32_t i;
1451	int rc;
1452
1453	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1454
1455	/*
1456	* Iterate thru all the devices and write 0 to the COMMAND register so
1457	* that all the memory is unmapped before we start restoring the saved
1458	* mapping locations.
1459	*
1460	* The register value is restored afterwards so we can do proper
1461	* LogRels in pciR3CommonRestoreConfig.
1462	*/
1463	for (i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1464	{
1465	PPCIDEVICE pDev = pBus->devices[i];
1466	if (pDev)
1467	{
1468	uint16_t u16 = PCIDevGetCommand(pDev);
1469	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1470	PCIDevSetCommand(pDev, u16);
1471	Assert(PCIDevGetCommand(pDev) == u16);
1472	}
1473	}
1474
1475	/*
1476	* Iterate all the devices.
1477	*/
1478	for (i = 0;; i++)
1479	{
1480	PCIDEVICE DevTmp;
1481	PPCIDEVICE pDev;
1482
1483	/* index / terminator */
1484	rc = SSMR3GetU32(pSSM, &u32);
1485	if (RT_FAILURE(rc))
1486	return rc;
1487	if (u32 == (uint32_t)~0)
1488	break;
1489	if ( u32 >= RT_ELEMENTS(pBus->devices)
1490	\|\| u32 < i)
1491	{
1492	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1493	return rc;
1494	}
1495
1496	/* skip forward to the device checking that no new devices are present. */
1497	for (; i < u32; i++)
1498	{
1499	if (pBus->devices[i])
1500	{
1501	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pBus->devices[i]->name,
1502	PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i])));
1503	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1504	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1505	i, pBus->devices[i]->name, PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i]));
1506	}
1507	}
1508
1509	/* get the data */
1510	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1511	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1512	if (uVersion < 3)
1513	{
1514	int32_t i32Temp;
1515	/* Irq value not needed anymore. */
1516	rc = SSMR3GetS32(pSSM, &i32Temp);
1517	if (RT_FAILURE(rc))
1518	return rc;
1519	}
1520	else
1521	{
1522	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1523	if (RT_FAILURE(rc))
1524	return rc;
1525	}
1526
1527	/* check that it's still around. */
1528	pDev = pBus->devices[i];
1529	if (!pDev)
1530	{
1531	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1532	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1533	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1534	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1535	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1536	continue;
1537	}
1538
1539	/* match the vendor id assuming that this will never be changed. */
1540	if ( DevTmp.config[0] != pDev->config[0]
1541	\|\| DevTmp.config[1] != pDev->config[1])
1542	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1543	i, pDev->name, DevTmp.config, pDev->config);
1544
1545	/* commit the loaded device config. */
1546	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1547
1548	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1549	}
1550
1551	return VINF_SUCCESS;
1552	}
1553
1554
1555	/**
1556	* @callback_method_impl{FNSSMDEVLOADEXEC}
1557	*/
1558	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1559	{
1560	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1561	PPCIBUS pBus = &pThis->PciBus;
1562	uint32_t u32;
1563	int rc;
1564
1565	/*
1566	* Check the version.
1567	*/
1568	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1569	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1570	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1571
1572	/*
1573	* Bus state data.
1574	*/
1575	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1576	if (uVersion > 1)
1577	SSMR3GetBool(pSSM, &pThis->fUseIoApic);
1578
1579	/* Load IRQ states. */
1580	if (uVersion > 2)
1581	{
1582	for (uint8_t i = 0; i < PCI_IRQ_PINS; i++)
1583	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_irq_levels[i]);
1584	for (uint8_t i = 0; i < PCI_APIC_IRQ_PINS; i++)
1585	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_apic_irq_levels[i]);
1586
1587	SSMR3GetU32(pSSM, &pThis->acpi_irq_level);
1588	SSMR3GetS32(pSSM, &pThis->acpi_irq);
1589	}
1590
1591	/* separator */
1592	rc = SSMR3GetU32(pSSM, &u32);
1593	if (RT_FAILURE(rc))
1594	return rc;
1595	if (u32 != (uint32_t)~0)
1596	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1597
1598	/*
1599	* The devices.
1600	*/
1601	return pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1602	}
1603
1604
1605	/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
1606
1607	/**
1608	* Registers the device with the specified PCI bus.
1609	*
1610	* @returns VBox status code.
1611	* @param pBus The bus to register with.
1612	* @param iDev The PCI device ordinal.
1613	* @param pPciDev The PCI device structure.
1614	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1615	*/
1616	static int pciR3RegisterDeviceInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1617	{
1618	/*
1619	* Find device slot.
1620	*/
1621	if (iDev < 0)
1622	{
1623	/*
1624	* Special check for the IDE controller which is our function 1 device
1625	* before searching.
1626	*/
1627	if ( !strcmp(pszName, "piix3ide")
1628	&& !pBus->devices[9])
1629	iDev = 9;
1630	/* LPC bus expected to be there by some guests, better make an additional argument to PDM
1631	device helpers, but requires significant rewrite */
1632	else if (!strcmp(pszName, "lpc")
1633	&& !pBus->devices[0xf8])
1634	iDev = 0xf8;
1635	else
1636	{
1637	Assert(!(pBus->iDevSearch % 8));
1638	for (iDev = pBus->iDevSearch; iDev < (int)RT_ELEMENTS(pBus->devices); iDev += 8)
1639	if ( !pBus->devices[iDev]
1640	&& !pBus->devices[iDev + 1]
1641	&& !pBus->devices[iDev + 2]
1642	&& !pBus->devices[iDev + 3]
1643	&& !pBus->devices[iDev + 4]
1644	&& !pBus->devices[iDev + 5]
1645	&& !pBus->devices[iDev + 6]
1646	&& !pBus->devices[iDev + 7])
1647	break;
1648	if (iDev >= (int)RT_ELEMENTS(pBus->devices))
1649	{
1650	AssertMsgFailed(("Couldn't find free spot!\n"));
1651	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1652	}
1653	}
1654	pciDevClearRequestedDevfunc(pPciDev);
1655	}
1656	else
1657	{
1658	/*
1659	* An explicit request.
1660	*
1661	* If the slot is occupied we'll have to relocate the device
1662	* currently occupying it first. This can only be done if the
1663	* existing device wasn't explicitly assigned. Also we limit
1664	* ourselves to function 0 devices.
1665	*
1666	* If you start setting devices + function in the
1667	* config, do it for all pci devices!
1668	*/
1669	//AssertReleaseMsg(iDev > 8 \|\| pBus->iBus != 0, ("iDev=%d pszName=%s\n", iDev, pszName));
1670	if (pBus->devices[iDev])
1671	{
1672	int iDevRel;
1673	AssertReleaseMsg(!(iDev % 8), ("PCI Configuration Conflict! iDev=%d pszName=%s clashes with %s\n",
1674	iDev, pszName, pBus->devices[iDev]->name));
1675	if ( pciDevIsRequestedDevfunc(pBus->devices[iDev])
1676	\|\| (pBus->devices[iDev + 1] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 1]))
1677	\|\| (pBus->devices[iDev + 2] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 2]))
1678	\|\| (pBus->devices[iDev + 3] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 3]))
1679	\|\| (pBus->devices[iDev + 4] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 4]))
1680	\|\| (pBus->devices[iDev + 5] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 5]))
1681	\|\| (pBus->devices[iDev + 6] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 6]))
1682	\|\| (pBus->devices[iDev + 7] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 7])))
1683	{
1684	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1685	pszName, pBus->devices[iDev]->name, iDev));
1686	return VERR_INTERNAL_ERROR;
1687	}
1688
1689	/* Find free slot for the device(s) we're moving and move them. */
1690	for (iDevRel = pBus->iDevSearch; iDevRel < (int)RT_ELEMENTS(pBus->devices); iDevRel += 8)
1691	{
1692	if ( !pBus->devices[iDevRel]
1693	&& !pBus->devices[iDevRel + 1]
1694	&& !pBus->devices[iDevRel + 2]
1695	&& !pBus->devices[iDevRel + 3]
1696	&& !pBus->devices[iDevRel + 4]
1697	&& !pBus->devices[iDevRel + 5]
1698	&& !pBus->devices[iDevRel + 6]
1699	&& !pBus->devices[iDevRel + 7])
1700	{
1701	int i = 0;
1702	for (i = 0; i < 8; i++)
1703	{
1704	if (!pBus->devices[iDev + i])
1705	continue;
1706	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->devices[iDev + i]->name, iDev + i, iDevRel + i));
1707	pBus->devices[iDevRel + i] = pBus->devices[iDev + i];
1708	pBus->devices[iDevRel + i]->devfn = iDevRel + i;
1709	pBus->devices[iDev + i] = NULL;
1710	}
1711	}
1712	}
1713	if (pBus->devices[iDev])
1714	{
1715	AssertMsgFailed(("Couldn't find free spot!\n"));
1716	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1717	}
1718	} /* if conflict */
1719	pciDevSetRequestedDevfunc(pPciDev);
1720	}
1721
1722	Assert(!pBus->devices[iDev]);
1723	pPciDev->devfn = iDev;
1724	pPciDev->name = pszName;
1725	pPciDev->Int.s.pBusR3 = pBus;
1726	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1727	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1728	pPciDev->Int.s.pfnConfigRead = pci_default_read_config;
1729	pPciDev->Int.s.pfnConfigWrite = pci_default_write_config;
1730	pBus->devices[iDev] = pPciDev;
1731	if (pciDevIsPci2PciBridge(pPciDev))
1732	{
1733	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->devices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
1734	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
1735	("device is a bridge but does not implement read/write functions\n"));
1736	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
1737	pBus->cBridges++;
1738	}
1739
1740	Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
1741	iDev >> 3, iDev & 7, 0x80000000 \| (iDev << 8), pszName));
1742
1743	return VINF_SUCCESS;
1744	}
1745
1746
1747	/**
1748	* @interface_method_impl{PDMPCIBUSREG,pfnRegister}
1749	*/
1750	static DECLCALLBACK(int) pciR3Register(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
1751	{
1752	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
1753
1754	/*
1755	* Check input.
1756	*/
1757	if ( !pszName
1758	\|\| !pPciDev
1759	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices)
1760	\|\| (iDev >= 0 && iDev <= 8))
1761	{
1762	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1763	return VERR_INVALID_PARAMETER;
1764	}
1765
1766	/*
1767	* Register the device.
1768	*/
1769	return pciR3RegisterDeviceInternal(pBus, iDev, pPciDev, pszName);
1770	}
1771
1772
1773	/**
1774	* @interface_method_impl{PDMPCIBUSREG,pfnIORegionRegisterR3}
1775	*/
1776	static DECLCALLBACK(int) pciR3CommonIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion,
1777	PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1778	{
1779	NOREF(pDevIns);
1780
1781	/*
1782	* Validate.
1783	*/
1784	AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
1785	\|\| enmType == PCI_ADDRESS_SPACE_IO
1786	\|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
1787	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
1788	VERR_INVALID_PARAMETER);
1789	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
1790	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
1791	VERR_INVALID_PARAMETER);
1792	int iLastSet = ASMBitLastSetU32(cbRegion);
1793	AssertMsgReturn( iLastSet != 0
1794	&& RT_BIT_32(iLastSet - 1) == cbRegion,
1795	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1796	VERR_INVALID_PARAMETER);
1797
1798	/*
1799	* Register the I/O region.
1800	*/
1801	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1802	pRegion->addr = ~0U;
1803	pRegion->size = cbRegion;
1804	pRegion->type = enmType;
1805	pRegion->map_func = pfnCallback;
1806
1807	/* Set type in the config space. */
1808	uint32_t u32Address = 0x10 + iRegion * 4;
1809	uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
1810	\| (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
1811	(uint32_t )(pPciDev->config + u32Address) = RT_H2LE_U32(u32Value);
1812
1813	return VINF_SUCCESS;
1814	}
1815
1816
1817	/**
1818	* @interface_method_impl{PDMPCIBUSREG,pfnSetConfigCallbacksR3}
1819	*/
1820	static DECLCALLBACK(void)
1821	pciR3CommonSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1822	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1823	{
1824	NOREF(pDevIns);
1825
1826	if (ppfnReadOld)
1827	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1828	pPciDev->Int.s.pfnConfigRead = pfnRead;
1829
1830	if (ppfnWriteOld)
1831	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1832	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1833	}
1834
1835
1836	/**
1837	* @interface_method_impl{PDMPCIBUSREG,pfnFakePCIBIOSR3}
1838	*/
1839	static DECLCALLBACK(int) pciR3FakePCIBIOS(PPDMDEVINS pDevIns)
1840	{
1841	unsigned i;
1842	uint8_t elcr[2] = {0, 0};
1843	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1844	PVM pVM = PDMDevHlpGetVM(pDevIns); Assert(pVM);
1845	PVMCPU pVCpu = PDMDevHlpGetVMCPU(pDevIns); Assert(pVM);
1846
1847	/*
1848	* Set the start addresses.
1849	*/
1850	pGlobals->pci_bios_io_addr = 0xd000;
1851	pGlobals->pci_bios_mem_addr = UINT32_C(0xf0000000);
1852	pGlobals->uBus = 0;
1853
1854	/*
1855	* Activate IRQ mappings.
1856	*/
1857	for (i = 0; i < 4; i++)
1858	{
1859	uint8_t irq = pci_irqs[i];
1860	/* Set to trigger level. */
1861	elcr[irq >> 3] \|= (1 << (irq & 7));
1862	/* Activate irq remapping in PIIX3. */
1863	pci_config_writeb(pGlobals, 0, pGlobals->PIIX3State.dev.devfn, 0x60 + i, irq);
1864	}
1865
1866	/* Tell to the PIC. */
1867	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d0, elcr[0], sizeof(uint8_t));
1868	if (rcStrict == VINF_SUCCESS)
1869	rcStrict = IOMIOPortWrite(pVM, pVCpu, 0x4d1, elcr[1], sizeof(uint8_t));
1870	if (rcStrict != VINF_SUCCESS)
1871	{
1872	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1873	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
1874	}
1875
1876	/*
1877	* Init the devices.
1878	*/
1879	for (i = 0; i < 256; i++)
1880	{
1881	uint8_t aBridgePositions[256];
1882
1883	memset(aBridgePositions, 0, sizeof(aBridgePositions));
1884	Log2(("PCI: Initializing device %d (%#x)\n",
1885	i, 0x80000000 \| (i << 8)));
1886	pci_bios_init_device(pGlobals, 0, i, 0, aBridgePositions);
1887	}
1888
1889	return VINF_SUCCESS;
1890	}
1891
1892
1893	/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
1894
1895	/**
1896	* @callback_method_impl{FNDBGFHANDLERDEV}
1897	*/
1898	static DECLCALLBACK(void) pciR3IrqInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1899	{
1900	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1901	NOREF(pszArgs);
1902
1903	uint16_t router = pGlobals->PIIX3State.dev.devfn;
1904	pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
1905	router >> 8, (router >> 3) & 0x1f, router & 0x7);
1906
1907	for (int i = 0; i < 4; ++i)
1908	{
1909	uint8_t irq_map = pci_config_readb(pGlobals, 0, router, 0x60 + i);
1910	if (irq_map & 0x80)
1911	pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
1912	else
1913	pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
1914	}
1915	}
1916
1917	/**
1918	* Outputs indent.
1919	*
1920	* @param pHlp Output helpers.
1921	* @param iIndent Indentation level.
1922	*/
1923	static void pciR3PrintIndent(PCDBGFINFOHLP pHlp, int iIndent)
1924	{
1925	while (iIndent-- > 0)
1926	pHlp->pfnPrintf(pHlp, " ");
1927	}
1928
1929	/**
1930	* Recursive worker for pciR3Info.
1931	*
1932	* @param pBus The bus to display.
1933	* @param pHlp Output helpers.
1934	* @param iIndent Indentation level.
1935	* @param fRegisters Whether to also display the PCI configuration registers
1936	* of each device on the bus.
1937	*/
1938	static void pciR3BusInfo(PPCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
1939	{
1940	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->devices); iDev++)
1941	{
1942	PPCIDEVICE pPciDev = pBus->devices[iDev];
1943	if (pPciDev != NULL)
1944	{
1945	pciR3PrintIndent(pHlp, iIndent);
1946
1947	/*
1948	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
1949	* as host driver handles real devices interrupts.
1950	*/
1951	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x%s%s",
1952	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
1953	pPciDev->name,
1954	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
1955	PCIDevGetWord(pPciDev, VBOX_PCI_VENDOR_ID), PCIDevGetWord(pPciDev, VBOX_PCI_DEVICE_ID),
1956	pciDevIsMsiCapable(pPciDev) ? " MSI" : "",
1957	pciDevIsMsixCapable(pPciDev) ? " MSI-X" : ""
1958	);
1959	if (PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
1960	pHlp->pfnPrintf(pHlp, " IRQ%d", PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
1961
1962	pHlp->pfnPrintf(pHlp, "\n");
1963
1964	uint16_t iCmd = PCIDevGetWord(pPciDev, VBOX_PCI_COMMAND);
1965	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
1966	{
1967	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
1968	{
1969	PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1970	uint64_t iRegionSize = pRegion->size;
1971
1972	if (iRegionSize == 0)
1973	continue;
1974
1975	uint32_t u32Addr = PCIDevGetDWord(pPciDev, PCIDevGetRegionReg(iRegion));
1976	const char * pszDesc;
1977	char szDescBuf[128];
1978
1979	bool f64Bit = !!(pRegion->type & PCI_ADDRESS_SPACE_BAR64);
1980	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
1981	{
1982	pszDesc = "IO";
1983	u32Addr &= ~0x3;
1984	}
1985	else
1986	{
1987	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
1988	f64Bit ? "64" : "32",
1989	(pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) ? " PREFETCH" : "");
1990	pszDesc = szDescBuf;
1991	u32Addr &= ~0xf;
1992	}
1993
1994	pciR3PrintIndent(pHlp, iIndent + 2);
1995	pHlp->pfnPrintf(pHlp, "%s region #%d: %x..%x\n",
1996	pszDesc, iRegion, u32Addr, u32Addr+iRegionSize);
1997	if (f64Bit)
1998	iRegion++;
1999	}
2000	}
2001
2002	pciR3PrintIndent(pHlp, iIndent + 2);
2003	uint16_t iStatus = PCIDevGetWord(pPciDev, VBOX_PCI_STATUS);
2004	pHlp->pfnPrintf(pHlp, "Command: %.Rhxs, Status: %.Rhxs\n",
2005	sizeof(uint16_t), &iCmd, sizeof(uint16_t), &iStatus);
2006	pciR3PrintIndent(pHlp, iIndent + 2);
2007	pHlp->pfnPrintf(pHlp, "Bus master: %s\n",
2008	iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
2009
2010	if (fRegisters)
2011	{
2012	pciR3PrintIndent(pHlp, iIndent + 2);
2013	pHlp->pfnPrintf(pHlp, "PCI registers:\n");
2014	for (int iReg = 0; iReg < 0x100; )
2015	{
2016	int iPerLine = 0x10;
2017	Assert (0x100 % iPerLine == 0);
2018	pciR3PrintIndent(pHlp, iIndent + 3);
2019
2020	while (iPerLine-- > 0)
2021	{
2022	pHlp->pfnPrintf(pHlp, "%02x ", PCIDevGetByte(pPciDev, iReg++));
2023	}
2024	pHlp->pfnPrintf(pHlp, "\n");
2025	}
2026	}
2027	}
2028	}
2029
2030	if (pBus->cBridges > 0)
2031	{
2032	pciR3PrintIndent(pHlp, iIndent);
2033	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2034	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2035	{
2036	PPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PPCIBUS);
2037	pciR3BusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2038	}
2039	}
2040	}
2041
2042
2043	/**
2044	* @callback_method_impl{FNDBGFHANDLERDEV}
2045	*/
2046	static DECLCALLBACK(void) pciR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2047	{
2048	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2049
2050	if (pszArgs == NULL \|\| !*pszArgs \|\| !strcmp(pszArgs, "basic"))
2051	pciR3BusInfo(pBus, pHlp, 0, false);
2052	else if (!strcmp(pszArgs, "verbose"))
2053	pciR3BusInfo(pBus, pHlp, 0, true);
2054	else
2055	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2056	}
2057
2058
2059	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
2060
2061	/**
2062	* @interface_method_impl{PDMDEVREG,pfnRelocate}
2063	*/
2064	static DECLCALLBACK(void) pciR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2065	{
2066	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2067	PPCIBUS pBus = &pGlobals->PciBus;
2068	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2069
2070	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2071	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2072
2073	/* Relocate RC pointers for the attached pci devices. */
2074	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2075	{
2076	if (pBus->devices[i])
2077	pBus->devices[i]->Int.s.pBusRC += offDelta;
2078	}
2079	}
2080
2081
2082	/**
2083	* @interface_method_impl{PDMDEVREG,pfnReset}
2084	*/
2085	static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
2086	{
2087	pciR3FakePCIBIOS(pDevIns);
2088	}
2089
2090
2091	/**
2092	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2093	*/
2094	static DECLCALLBACK(int) pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2095	{
2096	Assert(iInstance == 0);
2097	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2098
2099	/*
2100	* Validate and read configuration.
2101	*/
2102	if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
2103	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2104
2105	/* query whether we got an IOAPIC */
2106	bool fUseIoApic;
2107	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2108	if (RT_FAILURE(rc))
2109	return PDMDEV_SET_ERROR(pDevIns, rc,
2110	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2111
2112	/* check if RC code is enabled. */
2113	bool fGCEnabled;
2114	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2115	if (RT_FAILURE(rc))
2116	return PDMDEV_SET_ERROR(pDevIns, rc,
2117	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2118
2119	/* check if R0 code is enabled. */
2120	bool fR0Enabled;
2121	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2122	if (RT_FAILURE(rc))
2123	return PDMDEV_SET_ERROR(pDevIns, rc,
2124	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2125	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2126
2127	/*
2128	* Init data and register the PCI bus.
2129	*/
2130	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2131	pGlobals->pci_bios_io_addr = 0xc000;
2132	pGlobals->pci_bios_mem_addr = 0xf0000000;
2133	memset((void *)&pGlobals->pci_irq_levels, 0, sizeof(pGlobals->pci_irq_levels));
2134	pGlobals->fUseIoApic = fUseIoApic;
2135	memset((void *)&pGlobals->pci_apic_irq_levels, 0, sizeof(pGlobals->pci_apic_irq_levels));
2136
2137	pGlobals->pDevInsR3 = pDevIns;
2138	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2139	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2140
2141	pGlobals->PciBus.pDevInsR3 = pDevIns;
2142	pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2143	pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2144	pGlobals->PciBus.papBridgesR3 = (PPCIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE)
2145	* RT_ELEMENTS(pGlobals->PciBus.devices));
2146
2147	PDMPCIBUSREG PciBusReg;
2148	PPCIBUS pBus = &pGlobals->PciBus;
2149	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2150	PciBusReg.pfnRegisterR3 = pciR3Register;
2151	PciBusReg.pfnRegisterMsiR3 = NULL;
2152	PciBusReg.pfnIORegionRegisterR3 = pciR3CommonIORegionRegister;
2153	PciBusReg.pfnSetConfigCallbacksR3 = pciR3CommonSetConfigCallbacks;
2154	PciBusReg.pfnSetIrqR3 = pciSetIrq;
2155	PciBusReg.pfnFakePCIBIOSR3 = pciR3FakePCIBIOS;
2156	PciBusReg.pszSetIrqRC = fGCEnabled ? "pciSetIrq" : NULL;
2157	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
2158	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2159	if (RT_FAILURE(rc))
2160	return PDMDEV_SET_ERROR(pDevIns, rc,
2161	N_("Failed to register ourselves as a PCI Bus"));
2162	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2163	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2164	N_("PCI helper version mismatch; got %#x expected %#x"),
2165	pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION);
2166
2167	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2168	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2169
2170	/* Disable default device locking. */
2171	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2172	AssertRCReturn(rc, rc);
2173
2174	/*
2175	* Fill in PCI configs and add them to the bus.
2176	*/
2177	/* i440FX */
2178	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2179	PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
2180	PCIDevSetRevisionId(&pBus->PciDev, 0x02);
2181	PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
2182	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2183	PCIDevSetHeaderType(&pBus->PciDev, 0x00);
2184
2185	pBus->PciDev.pDevIns = pDevIns;
2186	pciDevSetRequestedDevfunc(&pBus->PciDev);
2187	pciR3RegisterDeviceInternal(pBus, 0, &pBus->PciDev, "i440FX");
2188
2189	/* PIIX3 */
2190	PCIDevSetVendorId( &pGlobals->PIIX3State.dev, 0x8086); /* Intel */
2191	PCIDevSetDeviceId( &pGlobals->PIIX3State.dev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
2192	PCIDevSetClassSub( &pGlobals->PIIX3State.dev, 0x01); /* PCI_ISA */
2193	PCIDevSetClassBase( &pGlobals->PIIX3State.dev, 0x06); /* PCI_bridge */
2194	PCIDevSetHeaderType(&pGlobals->PIIX3State.dev, 0x80); /* PCI_multifunction, generic */
2195
2196	pGlobals->PIIX3State.dev.pDevIns = pDevIns;
2197	pciDevSetRequestedDevfunc(&pGlobals->PIIX3State.dev);
2198	pciR3RegisterDeviceInternal(pBus, 8, &pGlobals->PIIX3State.dev, "PIIX3");
2199	pciR3Piix3Reset(&pGlobals->PIIX3State);
2200
2201	pBus->iDevSearch = 16;
2202
2203	/*
2204	* Register I/O ports and save state.
2205	*/
2206	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
2207	if (RT_FAILURE(rc))
2208	return rc;
2209	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
2210	if (RT_FAILURE(rc))
2211	return rc;
2212	if (fGCEnabled)
2213	{
2214	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2215	if (RT_FAILURE(rc))
2216	return rc;
2217	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2218	if (RT_FAILURE(rc))
2219	return rc;
2220	}
2221	if (fR0Enabled)
2222	{
2223	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2224	if (RT_FAILURE(rc))
2225	return rc;
2226	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2227	if (RT_FAILURE(rc))
2228	return rc;
2229	}
2230
2231	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2232	NULL, NULL, NULL,
2233	NULL, pciR3SaveExec, NULL,
2234	NULL, pciR3LoadExec, NULL);
2235	if (RT_FAILURE(rc))
2236	return rc;
2237
2238	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
2239	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
2240	pciR3Info);
2241	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ routing state. (no arguments)", pciR3IrqInfo);
2242
2243	return VINF_SUCCESS;
2244	}
2245
2246
2247	/**
2248	* The device registration structure.
2249	*/
2250	const PDMDEVREG g_DevicePCI =
2251	{
2252	/* u32Version */
2253	PDM_DEVREG_VERSION,
2254	/* szName */
2255	"pci",
2256	/* szRCMod */
2257	"VBoxDDGC.gc",
2258	/* szR0Mod */
2259	"VBoxDDR0.r0",
2260	/* pszDescription */
2261	"i440FX PCI bridge and PIIX3 ISA bridge.",
2262	/* fFlags */
2263	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2264	/* fClass */
2265	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2266	/* cMaxInstances */
2267	1,
2268	/* cbInstance */
2269	sizeof(PCIGLOBALS),
2270	/* pfnConstruct */
2271	pciR3Construct,
2272	/* pfnDestruct */
2273	NULL,
2274	/* pfnRelocate */
2275	pciR3Relocate,
2276	/* pfnMemSetup */
2277	NULL,
2278	/* pfnPowerOn */
2279	NULL,
2280	/* pfnReset */
2281	pciR3Reset,
2282	/* pfnSuspend */
2283	NULL,
2284	/* pfnResume */
2285	NULL,
2286	/* pfnAttach */
2287	NULL,
2288	/* pfnDetach */
2289	NULL,
2290	/* pfnQueryInterface */
2291	NULL,
2292	/* pfnInitComplete */
2293	NULL,
2294	/* pfnPowerOff */
2295	NULL,
2296	/* pfnSoftReset */
2297	NULL,
2298	/* u32VersionEnd */
2299	PDM_DEVREG_VERSION
2300
2301	};
2302	#endif /* IN_RING3 */
2303
2304
2305
2306	/* -=-=-=-=-=- The PCI bridge specific bits -=-=-=-=-=- */
2307
2308	/**
2309	* @interface_method_impl{PDMPCIBUSREG,pfnSetIrq}
2310	*/
2311	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
2312	{
2313	/*
2314	* The PCI-to-PCI bridge specification defines how the interrupt pins
2315	* are routed from the secondary to the primary bus (see chapter 9).
2316	* iIrq gives the interrupt pin the pci device asserted.
2317	* We change iIrq here according to the spec and call the SetIrq function
2318	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
2319	*/
2320	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2321	PPCIDEVICE pPciDevBus = pPciDev;
2322	int iIrqPinBridge = iIrq;
2323	uint8_t uDevFnBridge = 0;
2324
2325	/* Walk the chain until we reach the host bus. */
2326	do
2327	{
2328	uDevFnBridge = pBus->PciDev.devfn;
2329	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
2330
2331	/* Get the parent. */
2332	pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
2333	pPciDevBus = &pBus->PciDev;
2334	} while (pBus->iBus != 0);
2335
2336	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
2337	pciSetIrqInternal(PCIBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
2338	}
2339
2340	#ifdef IN_RING3
2341
2342	/**
2343	* @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
2344	*/
2345	static void pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
2346	{
2347	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2348
2349	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
2350
2351	/* If the current bus is not the target bus search for the bus which contains the device. */
2352	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2353	{
2354	PPCIDEVICE pBridgeDevice = pciR3FindBridge(pBus, iBus);
2355	if (pBridgeDevice)
2356	{
2357	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
2358	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
2359	}
2360	}
2361	else
2362	{
2363	/* This is the target bus, pass the write to the device. */
2364	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2365	if (pPciDev)
2366	{
2367	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2368	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
2369	}
2370	}
2371	}
2372
2373
2374	/**
2375	* @callback_method_impl{FNPCIBRIDGECONFIGREAD}
2376	*/
2377	static uint32_t pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
2378	{
2379	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2380	uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
2381
2382	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
2383
2384	/* If the current bus is not the target bus search for the bus which contains the device. */
2385	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2386	{
2387	PPCIDEVICE pBridgeDevice = pciR3FindBridge(pBus, iBus);
2388	if (pBridgeDevice)
2389	{
2390	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
2391	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
2392	}
2393	}
2394	else
2395	{
2396	/* This is the target bus, pass the read to the device. */
2397	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2398	if (pPciDev)
2399	{
2400	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
2401	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2402	}
2403	}
2404
2405	return u32Value;
2406	}
2407
2408
2409	/**
2410	* @callback_method_impl{FNSSMDEVSAVEEXEC}
2411	*/
2412	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2413	{
2414	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2415	return pciR3CommonSaveExec(pThis, pSSM);
2416	}
2417
2418
2419	/**
2420	* @callback_method_impl{FNSSMDEVLOADEXEC}
2421	*/
2422	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2423	{
2424	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2425	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
2426	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2427	return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
2428	}
2429
2430
2431	/**
2432	* @interface_method_impl{PDMPCIBUSREG,pfnRegister}
2433	*/
2434	static DECLCALLBACK(int) pcibridgeR3RegisterDevice(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
2435	{
2436	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2437
2438	/*
2439	* Check input.
2440	*/
2441	if ( !pszName
2442	\|\| !pPciDev
2443	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices))
2444	{
2445	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
2446	return VERR_INVALID_PARAMETER;
2447	}
2448
2449	/*
2450	* Register the device.
2451	*/
2452	return pciR3RegisterDeviceInternal(pBus, iDev, pPciDev, pszName);
2453	}
2454
2455
2456	/**
2457	* @interface_method_impl{PDMDEVREG, pfnReset}
2458	*/
2459	static DECLCALLBACK(void) pcibridgeR3Reset(PPDMDEVINS pDevIns)
2460	{
2461	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2462
2463	/* Reset config space to default values. */
2464	pBus->PciDev.config[VBOX_PCI_PRIMARY_BUS] = 0;
2465	pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS] = 0;
2466	pBus->PciDev.config[VBOX_PCI_SUBORDINATE_BUS] = 0;
2467	}
2468
2469
2470	/**
2471	* @interface_method_impl{PDMDEVREG, pfnRelocate}
2472	*/
2473	static DECLCALLBACK(void) pcibridgeR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2474	{
2475	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2476	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2477
2478	/* Relocate RC pointers for the attached pci devices. */
2479	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2480	{
2481	if (pBus->devices[i])
2482	pBus->devices[i]->Int.s.pBusRC += offDelta;
2483	}
2484	}
2485
2486
2487	/**
2488	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2489	*/
2490	static DECLCALLBACK(int) pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2491	{
2492	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2493
2494	/*
2495	* Validate and read configuration.
2496	*/
2497	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2498	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2499
2500	/* check if RC code is enabled. */
2501	bool fGCEnabled;
2502	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2503	if (RT_FAILURE(rc))
2504	return PDMDEV_SET_ERROR(pDevIns, rc,
2505	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2506
2507	/* check if R0 code is enabled. */
2508	bool fR0Enabled;
2509	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2510	if (RT_FAILURE(rc))
2511	return PDMDEV_SET_ERROR(pDevIns, rc,
2512	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2513	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2514
2515	/*
2516	* Init data and register the PCI bus.
2517	*/
2518	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2519	pBus->pDevInsR3 = pDevIns;
2520	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2521	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2522	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->devices));
2523
2524	PDMPCIBUSREG PciBusReg;
2525	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2526	PciBusReg.pfnRegisterR3 = pcibridgeR3RegisterDevice;
2527	PciBusReg.pfnRegisterMsiR3 = NULL;
2528	PciBusReg.pfnIORegionRegisterR3 = pciR3CommonIORegionRegister;
2529	PciBusReg.pfnSetConfigCallbacksR3 = pciR3CommonSetConfigCallbacks;
2530	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
2531	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2532	PciBusReg.pszSetIrqRC = fGCEnabled ? "pcibridgeSetIrq" : NULL;
2533	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pcibridgeSetIrq" : NULL;
2534	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2535	if (RT_FAILURE(rc))
2536	return PDMDEV_SET_ERROR(pDevIns, rc,
2537	N_("Failed to register ourselves as a PCI Bus"));
2538	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2539	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2540	N_("PCI helper version mismatch; got %#x expected %#x"),
2541	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2542
2543	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2544	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2545
2546	/*
2547	* Fill in PCI configs and add them to the bus.
2548	*/
2549	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2550	PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2551	PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
2552	PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
2553	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2554	PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
2555	PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2556	PCIDevSetCommand( &pBus->PciDev, 0x00);
2557	PCIDevSetStatus( &pBus->PciDev, 0x20); /* 66MHz Capable. */
2558	PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
2559
2560	/*
2561	* This device does not generate interrupts. Interrupt delivery from
2562	* devices attached to the bus is unaffected.
2563	*/
2564	PCIDevSetInterruptPin(&pBus->PciDev, 0x00);
2565
2566	pBus->PciDev.pDevIns = pDevIns;
2567
2568	/* Bridge-specific data */
2569	pciDevSetPci2PciBridge(&pBus->PciDev);
2570	pBus->PciDev.Int.s.pfnBridgeConfigRead = pcibridgeR3ConfigRead;
2571	pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;
2572
2573	/*
2574	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2575	*/
2576	rc = PDMDevHlpPCIRegister(pDevIns, &pBus->PciDev);
2577	if (RT_FAILURE(rc))
2578	return rc;
2579
2580	pBus->iDevSearch = 0;
2581	/*
2582	* The iBus property doesn't really represent the bus number
2583	* because the guest and the BIOS can choose different bus numbers
2584	* for them.
2585	* The bus number is mainly for the setIrq function to indicate
2586	* when the host bus is reached which will have iBus = 0.
2587	* That's why the + 1.
2588	*/
2589	pBus->iBus = iInstance + 1;
2590
2591	/*
2592	* Register SSM handlers. We use the same saved state version as for the host bridge
2593	* to make changes easier.
2594	*/
2595	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2596	NULL, NULL, NULL,
2597	NULL, pcibridgeR3SaveExec, NULL,
2598	NULL, pcibridgeR3LoadExec, NULL);
2599	if (RT_FAILURE(rc))
2600	return rc;
2601
2602	return VINF_SUCCESS;
2603	}
2604
2605
2606	/**
2607	* The device registration structure
2608	* for the PCI-to-PCI bridge.
2609	*/
2610	const PDMDEVREG g_DevicePCIBridge =
2611	{
2612	/* u32Version */
2613	PDM_DEVREG_VERSION,
2614	/* szName */
2615	"pcibridge",
2616	/* szRCMod */
2617	"VBoxDDGC.gc",
2618	/* szR0Mod */
2619	"VBoxDDR0.r0",
2620	/* pszDescription */
2621	"82801 Mobile PCI to PCI bridge",
2622	/* fFlags */
2623	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2624	/* fClass */
2625	PDM_DEVREG_CLASS_BUS_PCI,
2626	/* cMaxInstances */
2627	~0U,
2628	/* cbInstance */
2629	sizeof(PCIBUS),
2630	/* pfnConstruct */
2631	pcibridgeR3Construct,
2632	/* pfnDestruct */
2633	NULL,
2634	/* pfnRelocate */
2635	pcibridgeR3Relocate,
2636	/* pfnMemSetup */
2637	NULL,
2638	/* pfnPowerOn */
2639	NULL,
2640	/* pfnReset */
2641	pcibridgeR3Reset,
2642	/* pfnSuspend */
2643	NULL,
2644	/* pfnResume */
2645	NULL,
2646	/* pfnAttach */
2647	NULL,
2648	/* pfnDetach */
2649	NULL,
2650	/* pfnQueryInterface */
2651	NULL,
2652	/* pfnInitComplete */
2653	NULL,
2654	/* pfnPowerOff */
2655	NULL,
2656	/* pfnSoftReset */
2657	NULL,
2658	/* u32VersionEnd */
2659	PDM_DEVREG_VERSION
2660	};
2661
2662	#endif /* IN_RING3 */
2663	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 50125

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