DevPCI.cpp@ 43831

Last change on this file since 43831 was 41825, checked in by vboxsync, 12 years ago
PCI/DevATA: Put PCIDevPhysRead/Write into PDMDevHlpPCIDevPhysRead/Write, introduced VINF_PGM_PCI_PHYS_READ/WRITE_BM_DISABLED codes.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 101.6 KB

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1	/* $Id: DevPCI.cpp 41825 2012-06-19 14:14:28Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU PCI bus manager
21	*
22	* Copyright (c) 2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43	/*******************************************************************************
44	* Header Files *
45	*******************************************************************************/
46	#define LOG_GROUP LOG_GROUP_DEV_PCI
47	/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
48	#define PCI_INCLUDE_PRIVATE
49	#include <VBox/pci.h>
50	#include <VBox/vmm/pdmdev.h>
51	#include <iprt/asm.h>
52	#include <iprt/assert.h>
53	#include <iprt/string.h>
54
55	#include "VBoxDD.h"
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* PIIX3 ISA Bridge state.
63	*/
64	typedef struct PIIX3State
65	{
66	/** The PCI device of the bridge. */
67	PCIDEVICE dev;
68	} PIIX3State, PIIX3, *PPIIX3;
69
70	/**
71	* PCI Bus instance.
72	*/
73	typedef struct PCIBus
74	{
75	/** Bus number. */
76	int32_t iBus;
77	/** Start device number. */
78	int32_t iDevSearch;
79	/** Number of bridges attached to the bus. */
80	uint32_t cBridges;
81
82	uint32_t Alignment0;
83
84	/** Array of PCI devices. */
85	R3PTRTYPE(PPCIDEVICE) devices[256];
86	/** Array of bridges attached to the bus. */
87	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
88
89	/** R3 pointer to the device instance. */
90	PPDMDEVINSR3 pDevInsR3;
91	/** Pointer to the PCI R3 helpers. */
92	PCPDMPCIHLPR3 pPciHlpR3;
93
94	/** R0 pointer to the device instance. */
95	PPDMDEVINSR0 pDevInsR0;
96	/** Pointer to the PCI R0 helpers. */
97	PCPDMPCIHLPR0 pPciHlpR0;
98
99	/** RC pointer to the device instance. */
100	PPDMDEVINSRC pDevInsRC;
101	/** Pointer to the PCI RC helpers. */
102	PCPDMPCIHLPRC pPciHlpRC;
103
104	/** The PCI device for the PCI bridge. */
105	PCIDEVICE PciDev;
106
107	} PCIBUS;
108	/** Pointer to a PCIBUS instance. */
109	typedef PCIBUS *PPCIBUS;
110	typedef PCIBUS PCIBus;
111
112	/** @def PCI_IRQ_PINS
113	* Number of pins for interrupts (PIRQ#0...PIRQ#3)
114	*/
115	#define PCI_IRQ_PINS 4
116
117	/** @def PCI_APIC_IRQ_PINS
118	* Number of pins for interrupts if the APIC is used.
119	*/
120	#define PCI_APIC_IRQ_PINS 8
121
122	/**
123	* PCI Globals - This is the host-to-pci bridge and the root bus.
124	*/
125	typedef struct PCIGLOBALS
126	{
127	/** Irq levels for the four PCI Irqs.
128	* These count how many devices asserted
129	* the IRQ line. If greater 0 an IRQ is sent to the guest.
130	* If it drops to 0 the IRQ is deasserted.
131	*/
132	volatile uint32_t pci_irq_levels[PCI_IRQ_PINS];
133
134	#if 1 /* Will be moved into the BIOS soon. */
135	/** The next I/O port address which the PCI BIOS will use. */
136	uint32_t pci_bios_io_addr;
137	/** The next MMIO address which the PCI BIOS will use. */
138	uint32_t pci_bios_mem_addr;
139	/** Actual bus number. */
140	uint8_t uBus;
141	#endif
142
143	/** I/O APIC usage flag */
144	bool fUseIoApic;
145	/** I/O APIC irq levels */
146	volatile uint32_t pci_apic_irq_levels[PCI_APIC_IRQ_PINS];
147	/** ACPI IRQ level */
148	uint32_t acpi_irq_level;
149	/** ACPI PIC IRQ */
150	int acpi_irq;
151	/** Config register. */
152	uint32_t uConfigReg;
153
154	/** R3 pointer to the device instance. */
155	PPDMDEVINSR3 pDevInsR3;
156	/** R0 pointer to the device instance. */
157	PPDMDEVINSR0 pDevInsR0;
158	/** RC pointer to the device instance. */
159	PPDMDEVINSRC pDevInsRC;
160
161	#if HC_ARCH_BITS == 64
162	uint32_t Alignment0;
163	#endif
164
165	/** ISA bridge state. */
166	PIIX3 PIIX3State;
167	/** PCI bus which is attached to the host-to-PCI bridge. */
168	PCIBUS PciBus;
169
170	} PCIGLOBALS;
171	/** Pointer to per VM data. */
172	typedef PCIGLOBALS *PPCIGLOBALS;
173
174
175	/*******************************************************************************
176	* Defined Constants And Macros *
177	*******************************************************************************/
178
179	/** Converts a bus instance pointer to a device instance pointer. */
180	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
181	/** Converts a device instance pointer to a PCIGLOBALS pointer. */
182	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
183	/** Converts a device instance pointer to a PCIBUS pointer. */
184	#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->PciBus))
185
186	/** Converts a pointer to a PCI bus instance to a PCIGLOBALS pointer.
187	* @note This works only if the bus number is 0!!!
188	*/
189	#define PCIBUS_2_PCIGLOBALS(pPciBus) ( (PPCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(PCIGLOBALS, PciBus)) )
190
191	/** @def PCI_LOCK
192	* Acquires the PDM lock. This is a NOP if locking is disabled. */
193	/** @def PCI_UNLOCK
194	* Releases the PDM lock. This is a NOP if locking is disabled. */
195	#define PCI_LOCK(pDevIns, rc) \
196	do { \
197	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
198	if (rc2 != VINF_SUCCESS) \
199	return rc2; \
200	} while (0)
201	#define PCI_UNLOCK(pDevIns) \
202	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
203
204	/** @def VBOX_PCI_SAVED_STATE_VERSION
205	* Saved state version of the PCI bus device.
206	*/
207	#define VBOX_PCI_SAVED_STATE_VERSION 3
208
209
210	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
211	/*******************************************************************************
212	* Internal Functions *
213	*******************************************************************************/
214	RT_C_DECLS_BEGIN
215
216	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTag);
217	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTag);
218	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
219	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
220	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
221	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
222
223	#ifdef IN_RING3
224	DECLINLINE(PPCIDEVICE) pciFindBridge(PPCIBUS pBus, uint8_t iBus);
225	#endif
226
227	RT_C_DECLS_END
228
229	#define DEBUG_PCI
230
231	#define PCI_VENDOR_ID 0x00 /* 16 bits */
232	#define PCI_DEVICE_ID 0x02 /* 16 bits */
233	#define PCI_COMMAND 0x04 /* 16 bits */
234	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
235	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
236	#define PCI_CLASS_DEVICE 0x0a /* Device class */
237	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
238	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
239	#define PCI_MIN_GNT 0x3e /* 8 bits */
240	#define PCI_MAX_LAT 0x3f /* 8 bits */
241
242
243	#ifdef IN_RING3
244	static void pci_update_mappings(PCIDevice *d)
245	{
246	PPCIBUS pBus = d->Int.s.CTX_SUFF(pBus);
247	PCIIORegion *r;
248	int cmd, i;
249	uint32_t last_addr, new_addr, config_ofs;
250
251	cmd = RT_LE2H_U16((uint16_t )(d->config + PCI_COMMAND));
252	for(i = 0; i < PCI_NUM_REGIONS; i++) {
253	r = &d->Int.s.aIORegions[i];
254	if (i == PCI_ROM_SLOT) {
255	config_ofs = 0x30;
256	} else {
257	config_ofs = 0x10 + i * 4;
258	}
259	if (r->size != 0) {
260	if (r->type & PCI_ADDRESS_SPACE_IO) {
261	if (cmd & PCI_COMMAND_IO) {
262	new_addr = RT_LE2H_U32((uint32_t )(d->config +
263	config_ofs));
264	new_addr = new_addr & ~(r->size - 1);
265	last_addr = new_addr + r->size - 1;
266	/* NOTE: we have only 64K ioports on PC */
267	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
268	last_addr >= 0x10000) {
269	new_addr = ~0U;
270	}
271	} else {
272	new_addr = ~0U;
273	}
274	} else {
275	if (cmd & PCI_COMMAND_MEMORY) {
276	new_addr = RT_LE2H_U32((uint32_t )(d->config +
277	config_ofs));
278	/* the ROM slot has a specific enable bit */
279	if (i == PCI_ROM_SLOT && !(new_addr & 1))
280	goto no_mem_map;
281	new_addr = new_addr & ~(r->size - 1);
282	last_addr = new_addr + r->size - 1;
283	/* NOTE: we do not support wrapping */
284	/* XXX: as we cannot support really dynamic
285	mappings, we handle specific values as invalid
286	mappings. */
287	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
288	last_addr == ~0U) {
289	new_addr = ~0U;
290	}
291	} else {
292	no_mem_map:
293	new_addr = ~0U;
294	}
295	}
296	/* now do the real mapping */
297	if (new_addr != r->addr) {
298	if (r->addr != ~0U) {
299	if (r->type & PCI_ADDRESS_SPACE_IO) {
300	int devclass;
301	/* NOTE: specific hack for IDE in PC case:
302	only one byte must be mapped. */
303	devclass = d->config[0x0a] \| (d->config[0x0b] << 8);
304	if (devclass == 0x0101 && r->size == 4) {
305	int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr + 2, 1);
306	AssertRC(rc);
307	} else {
308	int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr, r->size);
309	AssertRC(rc);
310	}
311	} else {
312	RTGCPHYS GCPhysBase = r->addr;
313	int rc;
314	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, d->pDevIns, GCPhysBase))
315	{
316	/* unmap it. */
317	rc = r->map_func(d, i, NIL_RTGCPHYS, r->size, (PCIADDRESSSPACE)(r->type));
318	AssertRC(rc);
319	rc = PDMDevHlpMMIO2Unmap(d->pDevIns, i, GCPhysBase);
320	}
321	else
322	rc = PDMDevHlpMMIODeregister(d->pDevIns, GCPhysBase, r->size);
323	AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, d->name, i, GCPhysBase, r->size));
324	}
325	}
326	r->addr = new_addr;
327	if (r->addr != ~0U) {
328	int rc = r->map_func(d, i,
329	r->addr + (r->type & PCI_ADDRESS_SPACE_IO ? 0 : 0),
330	r->size, (PCIADDRESSSPACE)(r->type));
331	AssertRC(rc);
332	}
333	}
334	}
335	}
336	}
337
338
339	static DECLCALLBACK(uint32_t) pci_default_read_config(PCIDevice *d, uint32_t address, unsigned len)
340	{
341	uint32_t val;
342	switch(len) {
343	case 1:
344	val = d->config[address];
345	break;
346	case 2:
347	val = RT_LE2H_U16((uint16_t )(d->config + address));
348	break;
349	default:
350	case 4:
351	val = RT_LE2H_U32((uint32_t )(d->config + address));
352	break;
353	}
354	return val;
355	}
356
357	static DECLCALLBACK(void) pci_default_write_config(PCIDevice *d, uint32_t address, uint32_t val, unsigned len)
358	{
359	int can_write;
360	unsigned i;
361	uint32_t end, addr;
362
363	if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) \|\|
364	(address >= 0x30 && address < 0x34))) {
365	PCIIORegion *r;
366	int reg;
367
368	if ( address >= 0x30 ) {
369	reg = PCI_ROM_SLOT;
370	}else{
371	reg = (address - 0x10) >> 2;
372	}
373	r = &d->Int.s.aIORegions[reg];
374	if (r->size == 0)
375	goto default_config;
376	/* compute the stored value */
377	if (reg == PCI_ROM_SLOT) {
378	/* keep ROM enable bit */
379	val &= (~(r->size - 1)) \| 1;
380	} else {
381	val &= ~(r->size - 1);
382	val \|= r->type;
383	}
384	(uint32_t )(d->config + address) = RT_H2LE_U32(val);
385	pci_update_mappings(d);
386	return;
387	}
388	default_config:
389	/* not efficient, but simple */
390	addr = address;
391	for(i = 0; i < len; i++) {
392	/* default read/write accesses */
393	switch(d->config[0x0e]) {
394	case 0x00: /* normal device */
395	case 0x80: /* multi-function device */
396	switch(addr) {
397	case 0x00:
398	case 0x01:
399	case 0x02:
400	case 0x03:
401	case 0x08:
402	case 0x09:
403	case 0x0a:
404	case 0x0b:
405	case 0x0e:
406	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: /* base */
407	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
408	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
409	case 0x2c: case 0x2d: /* subsystem ID */
410	case 0x2e: case 0x2f: /* vendor ID */
411	case 0x30: case 0x31: case 0x32: case 0x33: /* rom */
412	case 0x34: /* Capabilities pointer. */
413	case 0x3d: /* Interrupt pin. */
414	can_write = 0;
415	break;
416	default:
417	can_write = 1;
418	break;
419	}
420	break;
421	default:
422	case 0x01: /* bridge */
423	switch(addr) {
424	case 0x00:
425	case 0x01:
426	case 0x02:
427	case 0x03:
428	case 0x08:
429	case 0x09:
430	case 0x0a:
431	case 0x0b:
432	case 0x0e:
433	case 0x38: case 0x39: case 0x3a: case 0x3b: /* rom */
434	case 0x3d:
435	can_write = 0;
436	break;
437	default:
438	can_write = 1;
439	break;
440	}
441	break;
442	}
443	#ifdef VBOX
444	if (addr == 0x05) /* Command register, bits 8-15. */
445	{
446	/* don't change reserved bits (11-15) */
447	val &= UINT32_C(~0xf8);
448	d->config[addr] = val;
449	}
450	else if (addr == 0x06) /* Status register, bits 0-7. */
451	{
452	/* don't change read-only bits => actually all lower bits are read-only */
453	val &= UINT32_C(~0xff);
454	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
455	d->config[addr] &= ~val;
456	}
457	else if (addr == 0x07) /* Status register, bits 8-15. */
458	{
459	/* don't change read-only bits */
460	val &= UINT32_C(~0x06);
461	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
462	d->config[addr] &= ~val;
463	}
464	else
465	#endif
466	if (can_write) {
467	d->config[addr] = val;
468	}
469	addr++;
470	val >>= 8;
471	}
472
473	end = address + len;
474	if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
475	/* if the command register is modified, we must modify the mappings */
476	pci_update_mappings(d);
477	}
478	}
479
480	#endif /* IN_RING3 */
481
482	static int pci_data_write(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
483	{
484	uint8_t iBus, iDevice;
485	uint32_t config_addr;
486
487	Log(("pci_data_write: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
488
489	if (!(pGlobals->uConfigReg & (1 << 31))) {
490	return VINF_SUCCESS;
491	}
492	if ((pGlobals->uConfigReg & 0x3) != 0) {
493	return VINF_SUCCESS;
494	}
495	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
496	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
497	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
498	if (iBus != 0)
499	{
500	if (pGlobals->PciBus.cBridges)
501	{
502	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
503	PPCIDEVICE pBridgeDevice = pciFindBridge(&pGlobals->PciBus, iBus);
504	if (pBridgeDevice)
505	{
506	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
507	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, val, len);
508	}
509	#else
510	return VINF_IOM_R3_IOPORT_WRITE;
511	#endif
512	}
513	}
514	else
515	{
516	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
517	if (pci_dev)
518	{
519	#ifdef IN_RING3
520	Log(("pci_config_write: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, val, len));
521	pci_dev->Int.s.pfnConfigWrite(pci_dev, config_addr, val, len);
522	#else
523	return VINF_IOM_R3_IOPORT_WRITE;
524	#endif
525	}
526	}
527	return VINF_SUCCESS;
528	}
529
530	static int pci_data_read(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
531	{
532	uint8_t iBus, iDevice;
533	uint32_t config_addr;
534
535	*pu32 = 0xffffffff;
536
537	if (!(pGlobals->uConfigReg & (1 << 31)))
538	return VINF_SUCCESS;
539	if ((pGlobals->uConfigReg & 0x3) != 0)
540	return VINF_SUCCESS;
541	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
542	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
543	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
544	if (iBus != 0)
545	{
546	if (pGlobals->PciBus.cBridges)
547	{
548	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
549	PPCIDEVICE pBridgeDevice = pciFindBridge(&pGlobals->PciBus, iBus);
550	if (pBridgeDevice)
551	{
552	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
553	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, len);
554	}
555	#else
556	NOREF(len);
557	return VINF_IOM_R3_IOPORT_READ;
558	#endif
559	}
560	}
561	else
562	{
563	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
564	if (pci_dev)
565	{
566	#ifdef IN_RING3
567	*pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev, config_addr, len);
568	Log(("pci_config_read: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, *pu32, len));
569	#else
570	NOREF(len);
571	return VINF_IOM_R3_IOPORT_READ;
572	#endif
573	}
574	}
575
576	return VINF_SUCCESS;
577	}
578
579
580
581	/* return the global irq number corresponding to a given device irq
582	pin. We could also use the bus number to have a more precise
583	mapping.
584	This is the implementation note described in the PCI spec chapter 2.2.6 */
585	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
586	{
587	int slot_addend;
588	slot_addend = (uDevFn >> 3) - 1;
589	return (irq_num + slot_addend) & 3;
590	}
591
592	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
593	{
594	return (irq_num + (uDevFn >> 3)) & 7;
595	}
596
597	static inline int get_pci_irq_apic_level(PPCIGLOBALS pGlobals, int irq_num)
598	{
599	return (pGlobals->pci_apic_irq_levels[irq_num] != 0);
600	}
601
602	static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int acpi_irq, uint32_t uTagSrc)
603	{
604	/* This is only allowed to be called with a pointer to the host bus. */
605	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
606
607	if (acpi_irq == -1) {
608	int apic_irq, apic_level;
609	PPCIGLOBALS pGlobals = PCIBUS_2_PCIGLOBALS(pBus);
610	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
611
612	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
613	ASMAtomicIncU32(&pGlobals->pci_apic_irq_levels[irq_num]);
614	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
615	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
616
617	apic_irq = irq_num + 0x10;
618	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
619	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
620	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
621	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
622
623	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
624	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
625	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
626	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
627	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
628	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
629	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
630	}
631	} else {
632	Log3(("apic_set_irq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
633	R3STRING(pPciDev->name), irq_num1, iLevel, acpi_irq));
634	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), acpi_irq, iLevel, uTagSrc);
635	}
636	}
637
638	DECLINLINE(int) get_pci_irq_level(PPCIGLOBALS pGlobals, int irq_num)
639	{
640	return (pGlobals->pci_irq_levels[irq_num] != 0);
641	}
642
643	/**
644	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
645	*
646	* @param pDevIns Device instance of the host PCI Bus.
647	* @param uDevFn The device number on the host bus which will raise the IRQ
648	* @param pPciDev The PCI device structure which raised the interrupt.
649	* @param iIrq IRQ number to set.
650	* @param iLevel IRQ level.
651	* @param uTagSrc The IRQ tag and source ID (for tracing).
652	* @remark uDevFn and pPciDev->devfn are not the same if the device is behind a bridge.
653	* In that case uDevFn will be the slot of the bridge which is needed to calculate the
654	* PIRQ value.
655	*/
656	static void pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
657	{
658	PPCIBUS pBus = &pGlobals->PciBus;
659	uint8_t *pbCfg = pGlobals->PIIX3State.dev.config;
660	const bool fIsAcpiDevice = pPciDev->config[2] == 0x13 && pPciDev->config[3] == 0x71;
661	/* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
662	* is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
663	* See the \_SB_.PCI0._PRT method in vbox.dsl.
664	*/
665	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
666	int pic_irq, pic_level;
667
668	/* Check if the state changed. */
669	if (pPciDev->Int.s.uIrqPinState != iLevel)
670	{
671	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
672
673	/* Send interrupt to I/O APIC only. */
674	if (fIsApicEnabled)
675	{
676	if (fIsAcpiDevice)
677	/*
678	* ACPI needs special treatment since SCI is hardwired and
679	* should not be affected by PCI IRQ routing tables at the
680	* same time SCI IRQ is shared in PCI sense hence this
681	* kludge (i.e. we fetch the hardwired value from ACPIs
682	* PCI device configuration space).
683	*/
684	apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->config[PCI_INTERRUPT_LINE], uTagSrc);
685	else
686	apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
687	return;
688	}
689
690	if (fIsAcpiDevice)
691	{
692	/* As per above treat ACPI in a special way */
693	pic_irq = pPciDev->config[PCI_INTERRUPT_LINE];
694	pGlobals->acpi_irq = pic_irq;
695	pGlobals->acpi_irq_level = iLevel & PDM_IRQ_LEVEL_HIGH;
696	}
697	else
698	{
699	int irq_num;
700	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
701
702	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
703	ASMAtomicIncU32(&pGlobals->pci_irq_levels[irq_num]);
704	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
705	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
706
707	/* now we change the pic irq level according to the piix irq mappings */
708	pic_irq = pbCfg[0x60 + irq_num];
709	if (pic_irq >= 16)
710	{
711	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
712	{
713	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
714	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
715	}
716
717	return;
718	}
719	}
720
721	/* the pic level is the logical OR of all the PCI irqs mapped to it */
722	pic_level = 0;
723	if (pic_irq == pbCfg[0x60])
724	pic_level \|= get_pci_irq_level(pGlobals, 0);
725	if (pic_irq == pbCfg[0x61])
726	pic_level \|= get_pci_irq_level(pGlobals, 1);
727	if (pic_irq == pbCfg[0x62])
728	pic_level \|= get_pci_irq_level(pGlobals, 2);
729	if (pic_irq == pbCfg[0x63])
730	pic_level \|= get_pci_irq_level(pGlobals, 3);
731	if (pic_irq == pGlobals->acpi_irq)
732	pic_level \|= pGlobals->acpi_irq_level;
733
734	Log3(("pciSetIrq: %s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
735	R3STRING(pPciDev->name), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
736	pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level, uTagSrc);
737
738	/** @todo optimize pci irq flip-flop some rainy day. */
739	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
740	pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
741	}
742	}
743
744	/**
745	* Set the IRQ for a PCI device on the host bus.
746	*
747	* @param pDevIns Device instance of the PCI Bus.
748	* @param pPciDev The PCI device structure.
749	* @param iIrq IRQ number to set.
750	* @param iLevel IRQ level.
751	* @param uTagSrc The IRQ tag and source ID (for tracing).
752	*/
753	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
754	{
755	pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel, uTagSrc);
756	}
757
758	#ifdef IN_RING3
759	/**
760	* Finds a bridge on the bus which contains the destination bus.
761	*
762	* @return Pointer to the device instance data of the bus or
763	* NULL if no bridge was found.
764	* @param pBus Pointer to the bus to search on.
765	* @param iBus Destination bus number.
766	*/
767	DECLINLINE(PPCIDEVICE) pciFindBridge(PPCIBUS pBus, uint8_t iBus)
768	{
769	/* Search for a fitting bridge. */
770	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
771	{
772	/*
773	* Examine secondary and subordinate bus number.
774	* If the target bus is in the range we pass the request on to the bridge.
775	*/
776	PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
777	AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
778	("Device is not a PCI bridge but on the list of PCI bridges\n"));
779
780	if ( iBus >= pBridgeTemp->config[VBOX_PCI_SECONDARY_BUS]
781	&& iBus <= pBridgeTemp->config[VBOX_PCI_SUBORDINATE_BUS])
782	return pBridgeTemp;
783	}
784
785	/* Nothing found. */
786	return NULL;
787	}
788
789	static void piix3_reset(PIIX3State *d)
790	{
791	uint8_t *pci_conf = d->dev.config;
792
793	pci_conf[0x04] = 0x07; /* master, memory and I/O */
794	pci_conf[0x05] = 0x00;
795	pci_conf[0x06] = 0x00;
796	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
797	pci_conf[0x4c] = 0x4d;
798	pci_conf[0x4e] = 0x03;
799	pci_conf[0x4f] = 0x00;
800	pci_conf[0x60] = 0x80;
801	pci_conf[0x69] = 0x02;
802	pci_conf[0x70] = 0x80;
803	pci_conf[0x76] = 0x0c;
804	pci_conf[0x77] = 0x0c;
805	pci_conf[0x78] = 0x02;
806	pci_conf[0x79] = 0x00;
807	pci_conf[0x80] = 0x00;
808	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
809	pci_conf[0xa0] = 0x08;
810	pci_conf[0xa0] = 0x08;
811	pci_conf[0xa2] = 0x00;
812	pci_conf[0xa3] = 0x00;
813	pci_conf[0xa4] = 0x00;
814	pci_conf[0xa5] = 0x00;
815	pci_conf[0xa6] = 0x00;
816	pci_conf[0xa7] = 0x00;
817	pci_conf[0xa8] = 0x0f;
818	pci_conf[0xaa] = 0x00;
819	pci_conf[0xab] = 0x00;
820	pci_conf[0xac] = 0x00;
821	pci_conf[0xae] = 0x00;
822	}
823
824	static void pci_config_writel(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
825	{
826	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
827	(uDevFn << 8) \| addr;
828	pci_data_write(pGlobals, 0, val, 4);
829	}
830
831	static void pci_config_writew(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
832	{
833	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
834	(uDevFn << 8) \| (addr & ~3);
835	pci_data_write(pGlobals, addr & 3, val, 2);
836	}
837
838	static void pci_config_writeb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
839	{
840	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
841	(uDevFn << 8) \| (addr & ~3);
842	pci_data_write(pGlobals, addr & 3, val, 1);
843	}
844
845	static uint32_t pci_config_readl(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
846	{
847	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
848	(uDevFn << 8) \| addr;
849	uint32_t u32Val;
850	int rc = pci_data_read(pGlobals, 0, 4, &u32Val);
851	AssertRC(rc);
852	return u32Val;
853	}
854
855	static uint32_t pci_config_readw(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
856	{
857	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
858	(uDevFn << 8) \| (addr & ~3);
859	uint32_t u32Val;
860	int rc = pci_data_read(pGlobals, addr & 3, 2, &u32Val);
861	AssertRC(rc);
862	return u32Val;
863	}
864
865	static uint32_t pci_config_readb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
866	{
867	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
868	(uDevFn << 8) \| (addr & ~3);
869	uint32_t u32Val;
870	int rc = pci_data_read(pGlobals, addr & 3, 1, &u32Val);
871	AssertRC(rc);
872	return u32Val;
873	}
874
875	/* host irqs corresponding to PCI irqs A-D */
876	static const uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; /* bird: added const */
877
878	static void pci_set_io_region_addr(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int region_num, uint32_t addr)
879	{
880	uint16_t cmd;
881	uint32_t ofs;
882
883	if ( region_num == PCI_ROM_SLOT )
884	ofs = 0x30;
885	else
886	ofs = 0x10 + region_num * 4;
887
888	/* Read memory type first. */
889	uint8_t uRessourceType = pci_config_readb(pGlobals, uBus, uDevFn, ofs);
890
891	/* Read command register. */
892	cmd = pci_config_readw(pGlobals, uBus, uDevFn, PCI_COMMAND);
893	if ( region_num == PCI_ROM_SLOT )
894	cmd \|= 2;
895	else if ((uRessourceType & 0x01) == 1) /* Test if region is I/O space. */
896	cmd \|= 1; /* Enable I/O space access. */
897	else /* The region is MMIO. */
898	cmd \|= 2; /* Enable MMIO access. */
899
900	/* Write address of the device. */
901	pci_config_writel(pGlobals, uBus, uDevFn, ofs, addr);
902
903	/* enable memory mappings */
904	pci_config_writew(pGlobals, uBus, uDevFn, PCI_COMMAND, cmd);
905	}
906
907	static void pci_bios_init_device(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
908	{
909	uint32_t *paddr;
910	int i, pin, pic_irq;
911	uint16_t devclass, vendor_id, device_id;
912
913	devclass = pci_config_readw(pGlobals, uBus, uDevFn, PCI_CLASS_DEVICE);
914	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
915	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
916
917	/* Check if device is present. */
918	if (vendor_id != 0xffff)
919	{
920	switch(devclass)
921	{
922	case 0x0101:
923	if ( (vendor_id == 0x8086)
924	&& (device_id == 0x7010 \|\| device_id == 0x7111 \|\| device_id == 0x269e))
925	{
926	/* PIIX3, PIIX4 or ICH6 IDE */
927	pci_config_writew(pGlobals, uBus, uDevFn, 0x40, 0x8000); /* enable IDE0 */
928	pci_config_writew(pGlobals, uBus, uDevFn, 0x42, 0x8000); /* enable IDE1 */
929	goto default_map;
930	}
931	else
932	{
933	/* IDE: we map it as in ISA mode */
934	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x1f0);
935	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 1, 0x3f4);
936	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 2, 0x170);
937	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 3, 0x374);
938	}
939	break;
940	case 0x0300:
941	if (vendor_id != 0x80ee)
942	goto default_map;
943	/* VGA: map frame buffer to default Bochs VBE address */
944	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0xE0000000);
945	/*
946	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
947	* only the framebuffer (i.e., a memory region) is explicitly registered via
948	* pci_set_io_region_addr, so I/O decoding must be enabled manually.
949	*/
950	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
951	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
952	\| 1 /* Enable I/O space access. */);
953	break;
954	case 0x0800:
955	/* PIC */
956	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
957	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
958	if (vendor_id == 0x1014)
959	{
960	/* IBM */
961	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
962	{
963	/* MPIC & MPIC2 */
964	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
965	}
966	}
967	break;
968	case 0xff00:
969	if ( (vendor_id == 0x0106b)
970	&& (device_id == 0x0017 \|\| device_id == 0x0022))
971	{
972	/* macio bridge */
973	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000);
974	}
975	break;
976	case 0x0604:
977	{
978	/* Init PCI-to-PCI bridge. */
979	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus);
980
981	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
982	pGlobals->uBus++;
983	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
984	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
985
986	/* Add position of this bridge into the array. */
987	paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
988
989	/*
990	* The I/O range for the bridge must be aligned to a 4KB boundary.
991	* This does not change anything really as the access to the device is not going
992	* through the bridge but we want to be compliant to the spec.
993	*/
994	if ((pGlobals->pci_bios_io_addr % 4096) != 0)
995	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
996	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_io_addr));
997	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->pci_bios_io_addr >> 8) & 0xf0);
998
999	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1000	if ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0)
1001	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
1002	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_mem_addr));
1003	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xffff0));
1004
1005	/* Save values to compare later to. */
1006	uint32_t u32IoAddressBase = pGlobals->pci_bios_io_addr;
1007	uint32_t u32MMIOAddressBase = pGlobals->pci_bios_mem_addr;
1008
1009	/* Init devices behind the bridge and possibly other bridges as well. */
1010	for (int iDev = 0; iDev <= 255; iDev++)
1011	pci_bios_init_device(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1012
1013	/* The number of bridges behind the this one is now available. */
1014	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1015
1016	/*
1017	* Set I/O limit register. If there is no device with I/O space behind the bridge
1018	* we set a lower value than in the base register.
1019	* The result with a real bridge is that no I/O transactions are passed to the secondary
1020	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1021	*/
1022	if ((u32IoAddressBase != pGlobals->pci_bios_io_addr) && ((pGlobals->pci_bios_io_addr % 4096) != 0))
1023	{
1024	/* The upper boundary must be one byte less than a 4KB boundary. */
1025	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
1026	}
1027	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->pci_bios_io_addr >> 8) & 0xf0) - 1);
1028
1029	/* Same with the MMIO limit register but with 1MB boundary here. */
1030	if ((u32MMIOAddressBase != pGlobals->pci_bios_mem_addr) && ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0))
1031	{
1032	/* The upper boundary must be one byte less than a 1MB boundary. */
1033	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
1034	}
1035	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xfff0)) - 1);
1036
1037	/*
1038	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1039	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1040	* the base register than in the limit register.
1041	*/
1042	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
1043	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
1044	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
1045	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
1046	break;
1047	}
1048	default:
1049	default_map:
1050	{
1051	/* default memory mappings */
1052	/*
1053	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
1054	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
1055	*/
1056	for(i = 0; i < (PCI_NUM_REGIONS-1); i++)
1057	{
1058	uint32_t u32Size;
1059	uint8_t u8RessourceType;
1060	uint32_t u32Address = 0x10 + i * 4;
1061
1062	/* Calculate size. */
1063	u8RessourceType = pci_config_readb(pGlobals, uBus, uDevFn, u32Address);
1064	pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff));
1065	u32Size = pci_config_readl(pGlobals, uBus, uDevFn, u32Address);
1066	/* Clear resource information depending on resource type. */
1067	if ((u8RessourceType & 0x01) == 1) /* I/O */
1068	u32Size &= ~(0x01);
1069	else /* MMIO */
1070	u32Size &= ~(0x0f);
1071
1072	/*
1073	* Invert all bits and add 1 to get size of the region.
1074	* (From PCI implementation note)
1075	*/
1076	if (((u8RessourceType & 0x01) == 1) && (u32Size & UINT32_C(0xffff0000)) == 0)
1077	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
1078	else
1079	u32Size = (~u32Size) + 1;
1080
1081	Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, i, uDevFn, uBus, u32Size));
1082
1083	if (u32Size)
1084	{
1085	if ((u8RessourceType & 0x01) == 1)
1086	paddr = &pGlobals->pci_bios_io_addr;
1087	else
1088	paddr = &pGlobals->pci_bios_mem_addr;
1089	paddr = (paddr + u32Size - 1) & ~(u32Size - 1);
1090	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, ((u8RessourceType & 0x01) == 1 ? "I/O" : "MMIO"), i, *paddr));
1091	pci_set_io_region_addr(pGlobals, uBus, uDevFn, i, *paddr);
1092	*paddr += u32Size;
1093	Log(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1094	}
1095	}
1096	break;
1097	}
1098	}
1099
1100	/* map the interrupt */
1101	pin = pci_config_readb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_PIN);
1102	if (pin != 0)
1103	{
1104	uint8_t uBridgeDevFn = uDevFn;
1105	pin--;
1106
1107	/* We need to go up to the host bus to see which irq this device will assert there. */
1108	while (cBridgeDepth != 0)
1109	{
1110	/* Get the pin the device would assert on the bridge. */
1111	pin = ((uBridgeDevFn >> 3) + pin) & 3;
1112	uBridgeDevFn = paBridgePositions[cBridgeDepth];
1113	cBridgeDepth--;
1114	}
1115
1116	pin = pci_slot_get_pirq(uDevFn, pin);
1117	pic_irq = pci_irqs[pin];
1118	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);
1119	}
1120	}
1121	}
1122
1123	#endif /* IN_RING3 */
1124
1125	/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
1126
1127	/**
1128	* Port I/O Handler for PCI address OUT operations.
1129	*
1130	* @returns VBox status code.
1131	*
1132	* @param pDevIns The device instance.
1133	* @param pvUser User argument - ignored.
1134	* @param uPort Port number used for the IN operation.
1135	* @param u32 The value to output.
1136	* @param cb The value size in bytes.
1137	*/
1138	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1139	{
1140	Log(("pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1141	NOREF(pvUser);
1142	if (cb == 4)
1143	{
1144	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1145	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
1146	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
1147	PCI_UNLOCK(pDevIns);
1148	}
1149	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1150	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1151	return VINF_SUCCESS;
1152	}
1153
1154
1155	/**
1156	* Port I/O Handler for PCI address IN operations.
1157	*
1158	* @returns VBox status code.
1159	*
1160	* @param pDevIns The device instance.
1161	* @param pvUser User argument - ignored.
1162	* @param uPort Port number used for the IN operation.
1163	* @param pu32 Where to store the result.
1164	* @param cb Number of bytes read.
1165	*/
1166	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1167	{
1168	NOREF(pvUser);
1169	if (cb == 4)
1170	{
1171	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1172	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
1173	*pu32 = pThis->uConfigReg;
1174	PCI_UNLOCK(pDevIns);
1175	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
1176	return VINF_SUCCESS;
1177	}
1178	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1179	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1180	Log(("pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
1181	return VERR_IOM_IOPORT_UNUSED;
1182	}
1183
1184
1185	/**
1186	* Port I/O Handler for PCI data OUT operations.
1187	*
1188	* @returns VBox status code.
1189	*
1190	* @param pDevIns The device instance.
1191	* @param pvUser User argument - ignored.
1192	* @param uPort Port number used for the IN operation.
1193	* @param u32 The value to output.
1194	* @param cb The value size in bytes.
1195	*/
1196	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1197	{
1198	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1199	NOREF(pvUser);
1200	int rc = VINF_SUCCESS;
1201	if (!(Port % cb))
1202	{
1203	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
1204	rc = pci_data_write(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
1205	PCI_UNLOCK(pDevIns);
1206	}
1207	else
1208	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
1209	return rc;
1210	}
1211
1212
1213	/**
1214	* Port I/O Handler for PCI data IN operations.
1215	*
1216	* @returns VBox status code.
1217	*
1218	* @param pDevIns The device instance.
1219	* @param pvUser User argument - ignored.
1220	* @param uPort Port number used for the IN operation.
1221	* @param pu32 Where to store the result.
1222	* @param cb Number of bytes read.
1223	*/
1224	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1225	{
1226	NOREF(pvUser);
1227	if (!(Port % cb))
1228	{
1229	PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
1230	int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
1231	PCI_UNLOCK(pDevIns);
1232	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
1233	return rc;
1234	}
1235	AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
1236	return VERR_IOM_IOPORT_UNUSED;
1237	}
1238
1239	#ifdef IN_RING3
1240
1241	/**
1242	* Saves a state of the PCI device.
1243	*
1244	* @returns VBox status code.
1245	* @param pDevIns Device instance of the PCI Bus.
1246	* @param pPciDev Pointer to PCI device.
1247	* @param pSSM The handle to save the state to.
1248	*/
1249	static DECLCALLBACK(int) pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1250	{
1251	NOREF(pDevIns);
1252	return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1253	}
1254
1255
1256	/**
1257	* Loads a saved PCI device state.
1258	*
1259	* @returns VBox status code.
1260	* @param pDevIns Device instance of the PCI Bus.
1261	* @param pPciDev Pointer to PCI device.
1262	* @param pSSM The handle to the saved state.
1263	*/
1264	static DECLCALLBACK(int) pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1265	{
1266	NOREF(pDevIns);
1267	return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1268	}
1269
1270
1271	/**
1272	* Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
1273	*
1274	* @returns VBox status code.
1275	* @param pBus The bus to save.
1276	* @param pSSM The saved state handle.
1277	*/
1278	static int pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
1279	{
1280	/*
1281	* Iterate thru all the devices.
1282	*/
1283	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1284	{
1285	PPCIDEVICE pDev = pBus->devices[i];
1286	if (pDev)
1287	{
1288	SSMR3PutU32(pSSM, i);
1289	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1290
1291	int rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1292	if (RT_FAILURE(rc))
1293	return rc;
1294	}
1295	}
1296	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1297	}
1298
1299
1300	/**
1301	* Saves a state of the PCI device.
1302	*
1303	* @returns VBox status code.
1304	* @param pDevIns The device instance.
1305	* @param pPciDev Pointer to PCI device.
1306	* @param pSSM The handle to save the state to.
1307	*/
1308	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1309	{
1310	uint32_t i;
1311	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1312
1313	/*
1314	* Bus state data.
1315	*/
1316	SSMR3PutU32(pSSM, pThis->uConfigReg);
1317	SSMR3PutBool(pSSM, pThis->fUseIoApic);
1318
1319	/*
1320	* Save IRQ states.
1321	*/
1322	for (i = 0; i < PCI_IRQ_PINS; i++)
1323	SSMR3PutU32(pSSM, pThis->pci_irq_levels[i]);
1324	for (i = 0; i < PCI_APIC_IRQ_PINS; i++)
1325	SSMR3PutU32(pSSM, pThis->pci_apic_irq_levels[i]);
1326
1327	SSMR3PutU32(pSSM, pThis->acpi_irq_level);
1328	SSMR3PutS32(pSSM, pThis->acpi_irq);
1329
1330	SSMR3PutU32(pSSM, ~0); /* separator */
1331
1332	/*
1333	* Join paths with pcibridgeR3SaveExec.
1334	*/
1335	return pciR3CommonSaveExec(&pThis->PciBus, pSSM);
1336	}
1337
1338
1339	/**
1340	* Common routine for restoring the config registers of a PCI device.
1341	*
1342	* @param pDev The PCI device.
1343	* @param pbSrcConfig The configuration register values to be loaded.
1344	* @param fIsBridge Whether this is a bridge device or not.
1345	*/
1346	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1347	{
1348	/*
1349	* This table defines the fields for normal devices and bridge devices, and
1350	* the order in which they need to be restored.
1351	*/
1352	static const struct PciField
1353	{
1354	uint8_t off;
1355	uint8_t cb;
1356	uint8_t fWritable;
1357	uint8_t fBridge;
1358	const char *pszName;
1359	} s_aFields[] =
1360	{
1361	/* off,cb,fW,fB, pszName */
1362	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1363	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1364	{ 0x06, 2, 1, 3, "STATUS" },
1365	{ 0x08, 1, 0, 3, "REVISION_ID" },
1366	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1367	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1368	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1369	{ 0x0c, 1, 0, 3, "CACHE_LINE_SIZE" }, // fWritable = ??
1370	{ 0x0d, 1, 0, 3, "LATENCY_TIMER" }, // fWritable = ??
1371	{ 0x0e, 1, 0, 3, "HEADER_TYPE" }, // fWritable = ??
1372	{ 0x0f, 1, 0, 3, "BIST" }, // fWritable = ??
1373	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1374	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1375	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1376	{ 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1377	{ 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1378	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1379	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1380	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1381	{ 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1382	{ 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1383	{ 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1384	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1385	{ 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1386	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1387	{ 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1388	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1389	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1390	{ 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1391	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1392	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1393	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1394	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1395	{ 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1396	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1397	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1398	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1399	{ 0x38, 4, 1, 1, "???" }, // ???
1400	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1401	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1402	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1403	{ 0x3e, 1, 0, 1, "MIN_GNT" }, // fWritable = !?
1404	{ 0x3e, 1, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !? cb=!?
1405	{ 0x3f, 1, 1, 3, "MAX_LAT" }, // fWritable = !? fBridge=!?
1406	/* The COMMAND register must come last as it requires the ADDRESS
1407	registers to be restored before we pretent to change it from 0 to
1408	whatever value the guest assigned it. */
1409	{ 0x04, 2, 1, 3, "COMMAND" },
1410	};
1411
1412	#ifdef RT_STRICT
1413	/* Check that we've got full register coverage. */
1414	uint32_t bmDevice[0x40 / 32];
1415	uint32_t bmBridge[0x40 / 32];
1416	RT_ZERO(bmDevice);
1417	RT_ZERO(bmBridge);
1418	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1419	{
1420	uint8_t off = s_aFields[i].off;
1421	uint8_t cb = s_aFields[i].cb;
1422	uint8_t f = s_aFields[i].fBridge;
1423	while (cb-- > 0)
1424	{
1425	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1426	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1427	if (f & 1) ASMBitSet(bmDevice, off);
1428	if (f & 2) ASMBitSet(bmBridge, off);
1429	off++;
1430	}
1431	}
1432	for (uint32_t off = 0; off < 0x40; off++)
1433	{
1434	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1435	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1436	}
1437	#endif
1438
1439	/*
1440	* Loop thru the fields covering the 64 bytes of standard registers.
1441	*/
1442	uint8_t const fBridge = fIsBridge ? 2 : 1;
1443	uint8_t *pbDstConfig = &pDev->config[0];
1444	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1445	if (s_aFields[i].fBridge & fBridge)
1446	{
1447	uint8_t const off = s_aFields[i].off;
1448	uint8_t const cb = s_aFields[i].cb;
1449	uint32_t u32Src;
1450	uint32_t u32Dst;
1451	switch (cb)
1452	{
1453	case 1:
1454	u32Src = pbSrcConfig[off];
1455	u32Dst = pbDstConfig[off];
1456	break;
1457	case 2:
1458	u32Src = (uint16_t const )&pbSrcConfig[off];
1459	u32Dst = (uint16_t const )&pbDstConfig[off];
1460	break;
1461	case 4:
1462	u32Src = (uint32_t const )&pbSrcConfig[off];
1463	u32Dst = (uint32_t const )&pbDstConfig[off];
1464	break;
1465	default:
1466	AssertFailed();
1467	continue;
1468	}
1469
1470	if ( u32Src != u32Dst
1471	\|\| off == VBOX_PCI_COMMAND)
1472	{
1473	if (u32Src != u32Dst)
1474	{
1475	if (!s_aFields[i].fWritable)
1476	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1477	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1478	else
1479	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1480	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1481	}
1482	if (off == VBOX_PCI_COMMAND)
1483	PCIDevSetCommand(pDev, 0); /* For remapping, see pciR3CommonLoadExec. */
1484	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1485	}
1486	}
1487
1488	/*
1489	* The device dependent registers.
1490	*
1491	* We will not use ConfigWrite here as we have no clue about the size
1492	* of the registers, so the device is responsible for correctly
1493	* restoring functionality governed by these registers.
1494	*/
1495	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1496	if (pbDstConfig[off] != pbSrcConfig[off])
1497	{
1498	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1499	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1500	pbDstConfig[off] = pbSrcConfig[off];
1501	}
1502	}
1503
1504
1505	/**
1506	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
1507	*
1508	* @returns VBox status code.
1509	* @param pBus The bus which data is being loaded.
1510	* @param pSSM The saved state handle.
1511	* @param uVersion The data version.
1512	* @param uPass The pass.
1513	*/
1514	static DECLCALLBACK(int) pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1515	{
1516	uint32_t u32;
1517	uint32_t i;
1518	int rc;
1519
1520	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1521
1522	/*
1523	* Iterate thru all the devices and write 0 to the COMMAND register so
1524	* that all the memory is unmapped before we start restoring the saved
1525	* mapping locations.
1526	*
1527	* The register value is restored afterwards so we can do proper
1528	* LogRels in pciR3CommonRestoreConfig.
1529	*/
1530	for (i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1531	{
1532	PPCIDEVICE pDev = pBus->devices[i];
1533	if (pDev)
1534	{
1535	uint16_t u16 = PCIDevGetCommand(pDev);
1536	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1537	PCIDevSetCommand(pDev, u16);
1538	Assert(PCIDevGetCommand(pDev) == u16);
1539	}
1540	}
1541
1542	/*
1543	* Iterate all the devices.
1544	*/
1545	for (i = 0;; i++)
1546	{
1547	PCIDEVICE DevTmp;
1548	PPCIDEVICE pDev;
1549
1550	/* index / terminator */
1551	rc = SSMR3GetU32(pSSM, &u32);
1552	if (RT_FAILURE(rc))
1553	return rc;
1554	if (u32 == (uint32_t)~0)
1555	break;
1556	if ( u32 >= RT_ELEMENTS(pBus->devices)
1557	\|\| u32 < i)
1558	{
1559	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1560	return rc;
1561	}
1562
1563	/* skip forward to the device checking that no new devices are present. */
1564	for (; i < u32; i++)
1565	{
1566	if (pBus->devices[i])
1567	{
1568	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pBus->devices[i]->name,
1569	PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i])));
1570	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1571	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1572	i, pBus->devices[i]->name, PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i]));
1573	}
1574	}
1575
1576	/* get the data */
1577	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1578	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1579	if (uVersion < 3)
1580	{
1581	int32_t i32Temp;
1582	/* Irq value not needed anymore. */
1583	rc = SSMR3GetS32(pSSM, &i32Temp);
1584	if (RT_FAILURE(rc))
1585	return rc;
1586	}
1587	else
1588	{
1589	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1590	if (RT_FAILURE(rc))
1591	return rc;
1592	}
1593
1594	/* check that it's still around. */
1595	pDev = pBus->devices[i];
1596	if (!pDev)
1597	{
1598	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1599	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1600	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1601	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1602	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1603	continue;
1604	}
1605
1606	/* match the vendor id assuming that this will never be changed. */
1607	if ( DevTmp.config[0] != pDev->config[0]
1608	\|\| DevTmp.config[1] != pDev->config[1])
1609	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1610	i, pDev->name, DevTmp.config, pDev->config);
1611
1612	/* commit the loaded device config. */
1613	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1614
1615	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1616	}
1617
1618	return VINF_SUCCESS;
1619	}
1620
1621
1622	/**
1623	* Loads a saved PCI device state.
1624	*
1625	* @returns VBox status code.
1626	* @param pDevIns The device instance.
1627	* @param pSSM The handle to the saved state.
1628	* @param uVersion The data unit version number.
1629	* @param uPass The data pass.
1630	*/
1631	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1632	{
1633	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1634	PPCIBUS pBus = &pThis->PciBus;
1635	uint32_t u32;
1636	int rc;
1637
1638	/*
1639	* Check the version.
1640	*/
1641	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1642	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1643	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1644
1645	/*
1646	* Bus state data.
1647	*/
1648	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1649	if (uVersion > 1)
1650	SSMR3GetBool(pSSM, &pThis->fUseIoApic);
1651
1652	/* Load IRQ states. */
1653	if (uVersion > 2)
1654	{
1655	for (uint8_t i = 0; i < PCI_IRQ_PINS; i++)
1656	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_irq_levels[i]);
1657	for (uint8_t i = 0; i < PCI_APIC_IRQ_PINS; i++)
1658	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_apic_irq_levels[i]);
1659
1660	SSMR3GetU32(pSSM, &pThis->acpi_irq_level);
1661	SSMR3GetS32(pSSM, &pThis->acpi_irq);
1662	}
1663
1664	/* separator */
1665	rc = SSMR3GetU32(pSSM, &u32);
1666	if (RT_FAILURE(rc))
1667	return rc;
1668	if (u32 != (uint32_t)~0)
1669	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1670
1671	/*
1672	* The devices.
1673	*/
1674	return pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1675	}
1676
1677
1678	/* -=-=-=-=-=- real code -=-=-=-=-=- */
1679
1680	/**
1681	* Registers the device with the specified PCI bus.
1682	*
1683	* @returns VBox status code.
1684	* @param pBus The bus to register with.
1685	* @param iDev The PCI device ordinal.
1686	* @param pPciDev The PCI device structure.
1687	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1688	*/
1689	static int pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1690	{
1691	/*
1692	* Find device slot.
1693	*/
1694	if (iDev < 0)
1695	{
1696	/*
1697	* Special check for the IDE controller which is our function 1 device
1698	* before searching.
1699	*/
1700	if ( !strcmp(pszName, "piix3ide")
1701	&& !pBus->devices[9])
1702	iDev = 9;
1703	/* LPC bus expected to be there by some guests, better make an additional argument to PDM
1704	device helpers, but requires significant rewrite */
1705	else if (!strcmp(pszName, "lpc")
1706	&& !pBus->devices[0xf8])
1707	iDev = 0xf8;
1708	else
1709	{
1710	Assert(!(pBus->iDevSearch % 8));
1711	for (iDev = pBus->iDevSearch; iDev < (int)RT_ELEMENTS(pBus->devices); iDev += 8)
1712	if ( !pBus->devices[iDev]
1713	&& !pBus->devices[iDev + 1]
1714	&& !pBus->devices[iDev + 2]
1715	&& !pBus->devices[iDev + 3]
1716	&& !pBus->devices[iDev + 4]
1717	&& !pBus->devices[iDev + 5]
1718	&& !pBus->devices[iDev + 6]
1719	&& !pBus->devices[iDev + 7])
1720	break;
1721	if (iDev >= (int)RT_ELEMENTS(pBus->devices))
1722	{
1723	AssertMsgFailed(("Couldn't find free spot!\n"));
1724	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1725	}
1726	}
1727	pciDevClearRequestedDevfunc(pPciDev);
1728	}
1729	else
1730	{
1731	/*
1732	* An explicit request.
1733	*
1734	* If the slot is occupied we'll have to relocate the device
1735	* currently occupying it first. This can only be done if the
1736	* existing device wasn't explicitly assigned. Also we limit
1737	* ourselves to function 0 devices.
1738	*
1739	* If you start setting devices + function in the
1740	* config, do it for all pci devices!
1741	*/
1742	//AssertReleaseMsg(iDev > 8 \|\| pBus->iBus != 0, ("iDev=%d pszName=%s\n", iDev, pszName));
1743	if (pBus->devices[iDev])
1744	{
1745	int iDevRel;
1746	AssertReleaseMsg(!(iDev % 8), ("PCI Configuration Conflict! iDev=%d pszName=%s clashes with %s\n",
1747	iDev, pszName, pBus->devices[iDev]->name));
1748	if ( pciDevIsRequestedDevfunc(pBus->devices[iDev])
1749	\|\| (pBus->devices[iDev + 1] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 1]))
1750	\|\| (pBus->devices[iDev + 2] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 2]))
1751	\|\| (pBus->devices[iDev + 3] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 3]))
1752	\|\| (pBus->devices[iDev + 4] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 4]))
1753	\|\| (pBus->devices[iDev + 5] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 5]))
1754	\|\| (pBus->devices[iDev + 6] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 6]))
1755	\|\| (pBus->devices[iDev + 7] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 7])))
1756	{
1757	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1758	pszName, pBus->devices[iDev]->name, iDev));
1759	return VERR_INTERNAL_ERROR;
1760	}
1761
1762	/* Find free slot for the device(s) we're moving and move them. */
1763	for (iDevRel = pBus->iDevSearch; iDevRel < (int)RT_ELEMENTS(pBus->devices); iDevRel += 8)
1764	{
1765	if ( !pBus->devices[iDevRel]
1766	&& !pBus->devices[iDevRel + 1]
1767	&& !pBus->devices[iDevRel + 2]
1768	&& !pBus->devices[iDevRel + 3]
1769	&& !pBus->devices[iDevRel + 4]
1770	&& !pBus->devices[iDevRel + 5]
1771	&& !pBus->devices[iDevRel + 6]
1772	&& !pBus->devices[iDevRel + 7])
1773	{
1774	int i = 0;
1775	for (i = 0; i < 8; i++)
1776	{
1777	if (!pBus->devices[iDev + i])
1778	continue;
1779	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->devices[iDev + i]->name, iDev + i, iDevRel + i));
1780	pBus->devices[iDevRel + i] = pBus->devices[iDev + i];
1781	pBus->devices[iDevRel + i]->devfn = iDevRel + i;
1782	pBus->devices[iDev + i] = NULL;
1783	}
1784	}
1785	}
1786	if (pBus->devices[iDev])
1787	{
1788	AssertMsgFailed(("Couldn't find free spot!\n"));
1789	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1790	}
1791	} /* if conflict */
1792	pciDevSetRequestedDevfunc(pPciDev);
1793	}
1794
1795	Assert(!pBus->devices[iDev]);
1796	pPciDev->devfn = iDev;
1797	pPciDev->name = pszName;
1798	pPciDev->Int.s.pBusR3 = pBus;
1799	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1800	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1801	pPciDev->Int.s.pfnConfigRead = pci_default_read_config;
1802	pPciDev->Int.s.pfnConfigWrite = pci_default_write_config;
1803	pBus->devices[iDev] = pPciDev;
1804	if (pciDevIsPci2PciBridge(pPciDev))
1805	{
1806	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->devices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
1807	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
1808	("device is a bridge but does not implement read/write functions\n"));
1809	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
1810	pBus->cBridges++;
1811	}
1812
1813	Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
1814	iDev >> 3, iDev & 7, 0x80000000 \| (iDev << 8), pszName));
1815
1816	return VINF_SUCCESS;
1817	}
1818
1819
1820	/**
1821	* Registers the device with the default PCI bus.
1822	*
1823	* @returns VBox status code.
1824	* @param pDevIns Device instance of the PCI Bus.
1825	* @param pPciDev The PCI device structure.
1826	* Any PCI enabled device must keep this in it's instance data!
1827	* Fill in the PCI data config before registration, please.
1828	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1829	* @param iDev The PCI device number. Use a negative value for auto assigning one.
1830	*/
1831	static DECLCALLBACK(int) pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
1832	{
1833	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
1834
1835	/*
1836	* Check input.
1837	*/
1838	if ( !pszName
1839	\|\| !pPciDev
1840	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices)
1841	\|\| (iDev >= 0 && iDev <= 8))
1842	{
1843	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1844	return VERR_INVALID_PARAMETER;
1845	}
1846
1847	/*
1848	* Register the device.
1849	*/
1850	return pciRegisterInternal(pBus, iDev, pPciDev, pszName);
1851	}
1852
1853
1854	static DECLCALLBACK(int) pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1855	{
1856	NOREF(pDevIns);
1857
1858	/*
1859	* Validate.
1860	*/
1861	AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
1862	\|\| enmType == PCI_ADDRESS_SPACE_IO
1863	\|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
1864	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
1865	VERR_INVALID_PARAMETER);
1866	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
1867	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
1868	VERR_INVALID_PARAMETER);
1869	int iLastSet = ASMBitLastSetU32(cbRegion);
1870	AssertMsgReturn( iLastSet != 0
1871	&& RT_BIT_32(iLastSet - 1) == cbRegion,
1872	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1873	VERR_INVALID_PARAMETER);
1874
1875	/*
1876	* Register the I/O region.
1877	*/
1878	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1879	pRegion->addr = ~0U;
1880	pRegion->size = cbRegion;
1881	pRegion->type = enmType;
1882	pRegion->map_func = pfnCallback;
1883
1884	/* Set type in the config space. */
1885	uint32_t u32Address = 0x10 + iRegion * 4;
1886	uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
1887	\| (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
1888	(uint32_t )(pPciDev->config + u32Address) = RT_H2LE_U32(u32Value);
1889
1890	return VINF_SUCCESS;
1891	}
1892
1893
1894	/**
1895	* @copydoc PDMPCIBUSREG::pfnSetConfigCallbacksR3
1896	*/
1897	static DECLCALLBACK(void) pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1898	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1899	{
1900	NOREF(pDevIns);
1901
1902	if (ppfnReadOld)
1903	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1904	pPciDev->Int.s.pfnConfigRead = pfnRead;
1905
1906	if (ppfnWriteOld)
1907	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1908	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1909	}
1910
1911
1912	/**
1913	* Called to perform the job of the bios.
1914	*
1915	* @returns VBox status.
1916	* @param pDevIns Device instance of the first bus.
1917	*/
1918	static DECLCALLBACK(int) pciFakePCIBIOS(PPDMDEVINS pDevIns)
1919	{
1920	unsigned i;
1921	uint8_t elcr[2] = {0, 0};
1922	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1923	PVM pVM = PDMDevHlpGetVM(pDevIns);
1924	Assert(pVM);
1925
1926	/*
1927	* Set the start addresses.
1928	*/
1929	pGlobals->pci_bios_io_addr = 0xd000;
1930	pGlobals->pci_bios_mem_addr = UINT32_C(0xf0000000);
1931	pGlobals->uBus = 0;
1932
1933	/*
1934	* Activate IRQ mappings.
1935	*/
1936	for (i = 0; i < 4; i++)
1937	{
1938	uint8_t irq = pci_irqs[i];
1939	/* Set to trigger level. */
1940	elcr[irq >> 3] \|= (1 << (irq & 7));
1941	/* Activate irq remapping in PIIX3. */
1942	pci_config_writeb(pGlobals, 0, pGlobals->PIIX3State.dev.devfn, 0x60 + i, irq);
1943	}
1944
1945	/* Tell to the PIC. */
1946	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, 0x4d0, elcr[0], sizeof(uint8_t));
1947	if (rcStrict == VINF_SUCCESS)
1948	rcStrict = IOMIOPortWrite(pVM, 0x4d1, elcr[1], sizeof(uint8_t));
1949	if (rcStrict != VINF_SUCCESS)
1950	{
1951	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1952	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
1953	}
1954
1955	/*
1956	* Init the devices.
1957	*/
1958	for (i = 0; i < 256; i++)
1959	{
1960	uint8_t aBridgePositions[256];
1961
1962	memset(aBridgePositions, 0, sizeof(aBridgePositions));
1963	Log2(("PCI: Initializing device %d (%#x)\n",
1964	i, 0x80000000 \| (i << 8)));
1965	pci_bios_init_device(pGlobals, 0, i, 0, aBridgePositions);
1966	}
1967
1968	return VINF_SUCCESS;
1969	}
1970
1971	/**
1972	* Info handler, device version.
1973	*
1974	* @param pDevIns Device instance which registered the info.
1975	* @param pHlp Callback functions for doing output.
1976	* @param pszArgs Argument string. Optional and specific to the handler.
1977	*/
1978	static DECLCALLBACK(void) pciIrqInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1979	{
1980	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1981	uint16_t router;
1982	uint8_t irq_map;
1983	int i;
1984	NOREF(pszArgs);
1985
1986	router = pGlobals->PIIX3State.dev.devfn;
1987	pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
1988	router >> 8, (router >> 3) & 0x1f, router & 0x7);
1989
1990	for (i = 0; i < 4; ++i)
1991	{
1992	irq_map = pci_config_readb(pGlobals, 0, router, 0x60 + i);
1993	if (irq_map & 0x80)
1994	pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
1995	else
1996	pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
1997	}
1998	}
1999
2000	static void printIndent(PCDBGFINFOHLP pHlp, int iIndent)
2001	{
2002	for (int i = 0; i < iIndent; i++)
2003	{
2004	pHlp->pfnPrintf(pHlp, " ");
2005	}
2006	}
2007
2008	static void pciBusInfo(PPCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
2009	{
2010	for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->devices); iDev++)
2011	{
2012	PPCIDEVICE pPciDev = pBus->devices[iDev];
2013	if (pPciDev != NULL)
2014	{
2015	printIndent(pHlp, iIndent);
2016
2017	/*
2018	* For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
2019	* as host driver handles real devices interrupts.
2020	*/
2021	pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x%s%s",
2022	pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2023	pPciDev->name,
2024	pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
2025	PCIDevGetWord(pPciDev, VBOX_PCI_VENDOR_ID), PCIDevGetWord(pPciDev, VBOX_PCI_DEVICE_ID),
2026	pciDevIsMsiCapable(pPciDev) ? " MSI" : "",
2027	pciDevIsMsixCapable(pPciDev) ? " MSI-X" : ""
2028	);
2029	if (PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
2030	pHlp->pfnPrintf(pHlp, " IRQ%d", PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
2031
2032	pHlp->pfnPrintf(pHlp, "\n");
2033
2034	uint16_t iCmd = PCIDevGetWord(pPciDev, VBOX_PCI_COMMAND);
2035	if ((iCmd & (VBOX_PCI_COMMAND_IO \| VBOX_PCI_COMMAND_MEMORY)) != 0)
2036	{
2037	for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2038	{
2039	PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2040	uint64_t iRegionSize = pRegion->size;
2041
2042	if (iRegionSize == 0)
2043	continue;
2044
2045	uint32_t u32Addr = PCIDevGetDWord(pPciDev, PCIDevGetRegionReg(iRegion));
2046	const char * pszDesc;
2047	char szDescBuf[128];
2048
2049	bool f64Bit = !!(pRegion->type & PCI_ADDRESS_SPACE_BAR64);
2050	if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2051	{
2052	pszDesc = "IO";
2053	u32Addr &= ~0x3;
2054	}
2055	else
2056	{
2057	RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2058	f64Bit ? "64" : "32",
2059	(pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) ? " PREFETCH" : "");
2060	pszDesc = szDescBuf;
2061	u32Addr &= ~0xf;
2062	}
2063
2064	printIndent(pHlp, iIndent + 2);
2065	pHlp->pfnPrintf(pHlp, "%s region #%d: %x..%x\n",
2066	pszDesc, iRegion, u32Addr, u32Addr+iRegionSize);
2067	if (f64Bit)
2068	iRegion++;
2069	}
2070	}
2071
2072	printIndent(pHlp, iIndent + 2);
2073	uint16_t iStatus = PCIDevGetWord(pPciDev, VBOX_PCI_STATUS);
2074	pHlp->pfnPrintf(pHlp, "Command: %.Rhxs, Status: %.Rhxs\n",
2075	sizeof(uint16_t), &iCmd, sizeof(uint16_t), &iStatus);
2076	printIndent(pHlp, iIndent + 2);
2077	pHlp->pfnPrintf(pHlp, "Bus master: %s\n",
2078	iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
2079
2080	if (fRegisters)
2081	{
2082	printIndent(pHlp, iIndent + 2);
2083	pHlp->pfnPrintf(pHlp, "PCI registers:\n");
2084	for (int iReg = 0; iReg < 0x100; )
2085	{
2086	int iPerLine = 0x10;
2087	Assert (0x100 % iPerLine == 0);
2088	printIndent(pHlp, iIndent + 3);
2089
2090	while (iPerLine-- > 0)
2091	{
2092	pHlp->pfnPrintf(pHlp, "%02x ", PCIDevGetByte(pPciDev, iReg++));
2093	}
2094	pHlp->pfnPrintf(pHlp, "\n");
2095	}
2096	}
2097	}
2098	}
2099
2100	if (pBus->cBridges > 0)
2101	{
2102	printIndent(pHlp, iIndent);
2103	pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2104	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2105	{
2106	PPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PPCIBUS);
2107	pciBusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2108	}
2109	}
2110	}
2111
2112	/**
2113	* Info handler, device version.
2114	*
2115	* @param pDevIns Device instance which registered the info.
2116	* @param pHlp Callback functions for doing output.
2117	* @param pszArgs Argument string. Optional and specific to the handler.
2118	*/
2119	static DECLCALLBACK(void) pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2120	{
2121	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2122
2123	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
2124	{
2125	pciBusInfo(pBus, pHlp, 0, false);
2126	}
2127	else if (!strcmp(pszArgs, "verbose"))
2128	{
2129	pciBusInfo(pBus, pHlp, 0, true);
2130	}
2131	else
2132	{
2133	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2134	}
2135	}
2136
2137	/**
2138	* @copydoc FNPDMDEVRELOCATE
2139	*/
2140	static DECLCALLBACK(void) pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2141	{
2142	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2143	PPCIBUS pBus = &pGlobals->PciBus;
2144	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2145
2146	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2147	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2148
2149	/* Relocate RC pointers for the attached pci devices. */
2150	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2151	{
2152	if (pBus->devices[i])
2153	pBus->devices[i]->Int.s.pBusRC += offDelta;
2154	}
2155	}
2156
2157
2158	/**
2159	* @copydoc FNPDMDEVRESET
2160	*/
2161	static DECLCALLBACK(void) pciReset(PPDMDEVINS pDevIns)
2162	{
2163	pciFakePCIBIOS(pDevIns);
2164	}
2165
2166	/**
2167	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2168	*/
2169	static DECLCALLBACK(int) pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2170	{
2171	Assert(iInstance == 0);
2172	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2173
2174	/*
2175	* Validate and read configuration.
2176	*/
2177	if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
2178	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2179
2180	/* query whether we got an IOAPIC */
2181	bool fUseIoApic;
2182	int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2183	if (RT_FAILURE(rc))
2184	return PDMDEV_SET_ERROR(pDevIns, rc,
2185	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2186
2187	/* check if RC code is enabled. */
2188	bool fGCEnabled;
2189	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2190	if (RT_FAILURE(rc))
2191	return PDMDEV_SET_ERROR(pDevIns, rc,
2192	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2193
2194	/* check if R0 code is enabled. */
2195	bool fR0Enabled;
2196	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2197	if (RT_FAILURE(rc))
2198	return PDMDEV_SET_ERROR(pDevIns, rc,
2199	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2200	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2201
2202	/*
2203	* Init data and register the PCI bus.
2204	*/
2205	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2206	pGlobals->pci_bios_io_addr = 0xc000;
2207	pGlobals->pci_bios_mem_addr = 0xf0000000;
2208	memset((void *)&pGlobals->pci_irq_levels, 0, sizeof(pGlobals->pci_irq_levels));
2209	pGlobals->fUseIoApic = fUseIoApic;
2210	memset((void *)&pGlobals->pci_apic_irq_levels, 0, sizeof(pGlobals->pci_apic_irq_levels));
2211
2212	pGlobals->pDevInsR3 = pDevIns;
2213	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2214	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2215
2216	pGlobals->PciBus.pDevInsR3 = pDevIns;
2217	pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2218	pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2219	pGlobals->PciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->PciBus.devices));
2220
2221	PDMPCIBUSREG PciBusReg;
2222	PPCIBUS pBus = &pGlobals->PciBus;
2223	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2224	PciBusReg.pfnRegisterR3 = pciRegister;
2225	PciBusReg.pfnRegisterMsiR3 = NULL;
2226	PciBusReg.pfnIORegionRegisterR3 = pciIORegionRegister;
2227	PciBusReg.pfnSetConfigCallbacksR3 = pciSetConfigCallbacks;
2228	PciBusReg.pfnSetIrqR3 = pciSetIrq;
2229	PciBusReg.pfnSaveExecR3 = pciGenericSaveExec;
2230	PciBusReg.pfnLoadExecR3 = pciGenericLoadExec;
2231	PciBusReg.pfnFakePCIBIOSR3 = pciFakePCIBIOS;
2232	PciBusReg.pszSetIrqRC = fGCEnabled ? "pciSetIrq" : NULL;
2233	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
2234	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2235	if (RT_FAILURE(rc))
2236	return PDMDEV_SET_ERROR(pDevIns, rc,
2237	N_("Failed to register ourselves as a PCI Bus"));
2238	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2239	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2240	N_("PCI helper version mismatch; got %#x expected %#x"),
2241	pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION);
2242
2243	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2244	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2245
2246	/* Disable default device locking. */
2247	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2248	AssertRCReturn(rc, rc);
2249
2250	/*
2251	* Fill in PCI configs and add them to the bus.
2252	*/
2253	/* i440FX */
2254	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2255	PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
2256	PCIDevSetRevisionId(&pBus->PciDev, 0x02);
2257	PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
2258	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2259	PCIDevSetHeaderType(&pBus->PciDev, 0x00);
2260
2261	pBus->PciDev.pDevIns = pDevIns;
2262	pciDevSetRequestedDevfunc(&pBus->PciDev);
2263	pciRegisterInternal(pBus, 0, &pBus->PciDev, "i440FX");
2264
2265	/* PIIX3 */
2266	PCIDevSetVendorId( &pGlobals->PIIX3State.dev, 0x8086); /* Intel */
2267	PCIDevSetDeviceId( &pGlobals->PIIX3State.dev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
2268	PCIDevSetClassSub( &pGlobals->PIIX3State.dev, 0x01); /* PCI_ISA */
2269	PCIDevSetClassBase( &pGlobals->PIIX3State.dev, 0x06); /* PCI_bridge */
2270	PCIDevSetHeaderType(&pGlobals->PIIX3State.dev, 0x80); /* PCI_multifunction, generic */
2271
2272	pGlobals->PIIX3State.dev.pDevIns = pDevIns;
2273	pciDevSetRequestedDevfunc(&pGlobals->PIIX3State.dev);
2274	pciRegisterInternal(pBus, 8, &pGlobals->PIIX3State.dev, "PIIX3");
2275	piix3_reset(&pGlobals->PIIX3State);
2276
2277	pBus->iDevSearch = 16;
2278
2279	/*
2280	* Register I/O ports and save state.
2281	*/
2282	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
2283	if (RT_FAILURE(rc))
2284	return rc;
2285	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
2286	if (RT_FAILURE(rc))
2287	return rc;
2288	if (fGCEnabled)
2289	{
2290	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2291	if (RT_FAILURE(rc))
2292	return rc;
2293	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2294	if (RT_FAILURE(rc))
2295	return rc;
2296	}
2297	if (fR0Enabled)
2298	{
2299	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2300	if (RT_FAILURE(rc))
2301	return rc;
2302	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2303	if (RT_FAILURE(rc))
2304	return rc;
2305	}
2306
2307	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2308	NULL, NULL, NULL,
2309	NULL, pciR3SaveExec, NULL,
2310	NULL, pciR3LoadExec, NULL);
2311	if (RT_FAILURE(rc))
2312	return rc;
2313
2314	PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. Recognizes 'basic' or 'verbose' "
2315	"as arguments, defaults to 'basic'.", pciInfo);
2316
2317	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ routing state. (no arguments)", pciIrqInfo);
2318
2319	return VINF_SUCCESS;
2320	}
2321
2322
2323	/**
2324	* The device registration structure.
2325	*/
2326	const PDMDEVREG g_DevicePCI =
2327	{
2328	/* u32Version */
2329	PDM_DEVREG_VERSION,
2330	/* szName */
2331	"pci",
2332	/* szRCMod */
2333	"VBoxDDGC.gc",
2334	/* szR0Mod */
2335	"VBoxDDR0.r0",
2336	/* pszDescription */
2337	"i440FX PCI bridge and PIIX3 ISA bridge.",
2338	/* fFlags */
2339	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2340	/* fClass */
2341	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2342	/* cMaxInstances */
2343	1,
2344	/* cbInstance */
2345	sizeof(PCIGLOBALS),
2346	/* pfnConstruct */
2347	pciConstruct,
2348	/* pfnDestruct */
2349	NULL,
2350	/* pfnRelocate */
2351	pciRelocate,
2352	/* pfnIOCtl */
2353	NULL,
2354	/* pfnPowerOn */
2355	NULL,
2356	/* pfnReset */
2357	pciReset,
2358	/* pfnSuspend */
2359	NULL,
2360	/* pfnResume */
2361	NULL,
2362	/* pfnAttach */
2363	NULL,
2364	/* pfnDetach */
2365	NULL,
2366	/* pfnQueryInterface */
2367	NULL,
2368	/* pfnInitComplete */
2369	NULL,
2370	/* pfnPowerOff */
2371	NULL,
2372	/* pfnSoftReset */
2373	NULL,
2374	/* u32VersionEnd */
2375	PDM_DEVREG_VERSION
2376
2377	};
2378	#endif /* IN_RING3 */
2379
2380
2381	/**
2382	* Set the IRQ for a PCI device on a secondary bus.
2383	*
2384	* @param pDevIns Device instance of the PCI Bus.
2385	* @param pPciDev The PCI device structure.
2386	* @param iIrq IRQ number to set.
2387	* @param iLevel IRQ level.
2388	* @param uTagSrc The IRQ tag and source ID (for tracing).
2389	*/
2390	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
2391	{
2392	/*
2393	* The PCI-to-PCI bridge specification defines how the interrupt pins
2394	* are routed from the secondary to the primary bus (see chapter 9).
2395	* iIrq gives the interrupt pin the pci device asserted.
2396	* We change iIrq here according to the spec and call the SetIrq function
2397	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
2398	*/
2399	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2400	PPCIDEVICE pPciDevBus = pPciDev;
2401	int iIrqPinBridge = iIrq;
2402	uint8_t uDevFnBridge = 0;
2403
2404	/* Walk the chain until we reach the host bus. */
2405	do
2406	{
2407	uDevFnBridge = pBus->PciDev.devfn;
2408	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
2409
2410	/* Get the parent. */
2411	pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
2412	pPciDevBus = &pBus->PciDev;
2413	} while (pBus->iBus != 0);
2414
2415	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
2416	pciSetIrqInternal(PCIBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
2417	}
2418
2419	#ifdef IN_RING3
2420
2421	static void pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
2422	{
2423	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2424
2425	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
2426
2427	/* If the current bus is not the target bus search for the bus which contains the device. */
2428	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2429	{
2430	PPCIDEVICE pBridgeDevice = pciFindBridge(pBus, iBus);
2431	if (pBridgeDevice)
2432	{
2433	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
2434	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
2435	}
2436	}
2437	else
2438	{
2439	/* This is the target bus, pass the write to the device. */
2440	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2441	if (pPciDev)
2442	{
2443	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2444	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
2445	}
2446	}
2447	}
2448
2449	static uint32_t pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
2450	{
2451	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2452	uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
2453
2454	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
2455
2456	/* If the current bus is not the target bus search for the bus which contains the device. */
2457	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2458	{
2459	PPCIDEVICE pBridgeDevice = pciFindBridge(pBus, iBus);
2460	if (pBridgeDevice)
2461	{
2462	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
2463	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
2464	}
2465	}
2466	else
2467	{
2468	/* This is the target bus, pass the read to the device. */
2469	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2470	if (pPciDev)
2471	{
2472	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
2473	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2474	}
2475	}
2476
2477	return u32Value;
2478	}
2479
2480
2481	/**
2482	* @copydoc FNSSMDEVSAVEEXEC
2483	*/
2484	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2485	{
2486	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2487	return pciR3CommonSaveExec(pThis, pSSM);
2488	}
2489
2490
2491	/**
2492	* @copydoc FNSSMDEVLOADEXEC
2493	*/
2494	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2495	{
2496	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2497	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
2498	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2499	return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
2500	}
2501
2502
2503	/**
2504	* Registers the device with the default PCI bus.
2505	*
2506	* @returns VBox status code.
2507	* @param pDevIns Device instance of the PCI Bus.
2508	* @param pPciDev The PCI device structure.
2509	* Any PCI enabled device must keep this in it's instance data!
2510	* Fill in the PCI data config before registration, please.
2511	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
2512	* @param iDev The PCI device number. Use a negative value for auto assigning one.
2513	*/
2514	static DECLCALLBACK(int) pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
2515	{
2516	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2517
2518	/*
2519	* Check input.
2520	*/
2521	if ( !pszName
2522	\|\| !pPciDev
2523	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices))
2524	{
2525	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
2526	return VERR_INVALID_PARAMETER;
2527	}
2528
2529	/*
2530	* Register the device.
2531	*/
2532	return pciRegisterInternal(pBus, iDev, pPciDev, pszName);
2533	}
2534
2535
2536	/**
2537	* @copydoc FNPDMDEVRESET
2538	*/
2539	static DECLCALLBACK(void) pcibridgeReset(PPDMDEVINS pDevIns)
2540	{
2541	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2542
2543	/* Reset config space to default values. */
2544	pBus->PciDev.config[VBOX_PCI_PRIMARY_BUS] = 0;
2545	pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS] = 0;
2546	pBus->PciDev.config[VBOX_PCI_SUBORDINATE_BUS] = 0;
2547	}
2548
2549
2550	/**
2551	* @copydoc FNPDMDEVRELOCATE
2552	*/
2553	static DECLCALLBACK(void) pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2554	{
2555	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2556	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2557
2558	/* Relocate RC pointers for the attached pci devices. */
2559	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2560	{
2561	if (pBus->devices[i])
2562	pBus->devices[i]->Int.s.pBusRC += offDelta;
2563	}
2564	}
2565
2566
2567	/**
2568	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2569	*/
2570	static DECLCALLBACK(int) pcibridgeConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2571	{
2572	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2573
2574	/*
2575	* Validate and read configuration.
2576	*/
2577	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2578	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2579
2580	/* check if RC code is enabled. */
2581	bool fGCEnabled;
2582	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2583	if (RT_FAILURE(rc))
2584	return PDMDEV_SET_ERROR(pDevIns, rc,
2585	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2586
2587	/* check if R0 code is enabled. */
2588	bool fR0Enabled;
2589	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2590	if (RT_FAILURE(rc))
2591	return PDMDEV_SET_ERROR(pDevIns, rc,
2592	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2593	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2594
2595	/*
2596	* Init data and register the PCI bus.
2597	*/
2598	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2599	pBus->pDevInsR3 = pDevIns;
2600	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2601	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2602	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->devices));
2603
2604	PDMPCIBUSREG PciBusReg;
2605	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2606	PciBusReg.pfnRegisterR3 = pcibridgeRegister;
2607	PciBusReg.pfnRegisterMsiR3 = NULL;
2608	PciBusReg.pfnIORegionRegisterR3 = pciIORegionRegister;
2609	PciBusReg.pfnSetConfigCallbacksR3 = pciSetConfigCallbacks;
2610	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
2611	PciBusReg.pfnSaveExecR3 = pciGenericSaveExec;
2612	PciBusReg.pfnLoadExecR3 = pciGenericLoadExec;
2613	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2614	PciBusReg.pszSetIrqRC = fGCEnabled ? "pcibridgeSetIrq" : NULL;
2615	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pcibridgeSetIrq" : NULL;
2616	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2617	if (RT_FAILURE(rc))
2618	return PDMDEV_SET_ERROR(pDevIns, rc,
2619	N_("Failed to register ourselves as a PCI Bus"));
2620	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2621	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2622	N_("PCI helper version mismatch; got %#x expected %#x"),
2623	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2624
2625	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2626	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2627
2628	/*
2629	* Fill in PCI configs and add them to the bus.
2630	*/
2631	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2632	PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2633	PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
2634	PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
2635	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2636	PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
2637	PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2638	PCIDevSetCommand( &pBus->PciDev, 0x00);
2639	PCIDevSetStatus( &pBus->PciDev, 0x20); /* 66MHz Capable. */
2640	PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
2641
2642	/*
2643	* This device does not generate interrupts. Interrupt delivery from
2644	* devices attached to the bus is unaffected.
2645	*/
2646	PCIDevSetInterruptPin (&pBus->PciDev, 0x00);
2647
2648	pBus->PciDev.pDevIns = pDevIns;
2649
2650	/* Bridge-specific data */
2651	pciDevSetPci2PciBridge(&pBus->PciDev);
2652	pBus->PciDev.Int.s.pfnBridgeConfigRead = pcibridgeConfigRead;
2653	pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeConfigWrite;
2654
2655	/*
2656	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2657	*/
2658	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->PciDev);
2659	if (RT_FAILURE(rc))
2660	return rc;
2661
2662	pBus->iDevSearch = 0;
2663	/*
2664	* The iBus property doesn't really represent the bus number
2665	* because the guest and the BIOS can choose different bus numbers
2666	* for them.
2667	* The bus number is mainly for the setIrq function to indicate
2668	* when the host bus is reached which will have iBus = 0.
2669	* That's why the + 1.
2670	*/
2671	pBus->iBus = iInstance + 1;
2672
2673	/*
2674	* Register SSM handlers. We use the same saved state version as for the host bridge
2675	* to make changes easier.
2676	*/
2677	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2678	NULL, NULL, NULL,
2679	NULL, pcibridgeR3SaveExec, NULL,
2680	NULL, pcibridgeR3LoadExec, NULL);
2681	if (RT_FAILURE(rc))
2682	return rc;
2683
2684	return VINF_SUCCESS;
2685	}
2686
2687
2688	/**
2689	* The device registration structure
2690	* for the PCI-to-PCI bridge.
2691	*/
2692	const PDMDEVREG g_DevicePCIBridge =
2693	{
2694	/* u32Version */
2695	PDM_DEVREG_VERSION,
2696	/* szName */
2697	"pcibridge",
2698	/* szRCMod */
2699	"VBoxDDGC.gc",
2700	/* szR0Mod */
2701	"VBoxDDR0.r0",
2702	/* pszDescription */
2703	"82801 Mobile PCI to PCI bridge",
2704	/* fFlags */
2705	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2706	/* fClass */
2707	PDM_DEVREG_CLASS_BUS_PCI,
2708	/* cMaxInstances */
2709	~0U,
2710	/* cbInstance */
2711	sizeof(PCIBUS),
2712	/* pfnConstruct */
2713	pcibridgeConstruct,
2714	/* pfnDestruct */
2715	NULL,
2716	/* pfnRelocate */
2717	pcibridgeRelocate,
2718	/* pfnIOCtl */
2719	NULL,
2720	/* pfnPowerOn */
2721	NULL,
2722	/* pfnReset */
2723	pcibridgeReset,
2724	/* pfnSuspend */
2725	NULL,
2726	/* pfnResume */
2727	NULL,
2728	/* pfnAttach */
2729	NULL,
2730	/* pfnDetach */
2731	NULL,
2732	/* pfnQueryInterface */
2733	NULL,
2734	/* pfnInitComplete */
2735	NULL,
2736	/* pfnPowerOff */
2737	NULL,
2738	/* pfnSoftReset */
2739	NULL,
2740	/* u32VersionEnd */
2741	PDM_DEVREG_VERSION
2742	};
2743
2744	#endif /* IN_RING3 */
2745	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 43831

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