DevPCI.cpp@ 15941

Last change on this file since 15941 was 15787, checked in by vboxsync, 16 years ago
PCI: don't allow to change subsystem ID and vendor ID; mask out read-only bits in the status register
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1	/* $Id: DevPCI.cpp 15787 2009-01-05 08:17:25Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	* --------------------------------------------------------------------
21	*
22	* This code is based on:
23	*
24	* QEMU PCI bus manager
25	*
26	* Copyright (c) 2004 Fabrice Bellard
27	*
28	* Permission is hereby granted, free of charge, to any person obtaining a copy
29	* of this software and associated documentation files (the "Software"), to deal
30	* in the Software without restriction, including without limitation the rights
31	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
32	* copies of the Software, and to permit persons to whom the Software is
33	* furnished to do so, subject to the following conditions:
34	*
35	* The above copyright notice and this permission notice shall be included in
36	* all copies or substantial portions of the Software.
37	*
38	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
39	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
40	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
41	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
42	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
43	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
44	* THE SOFTWARE.
45	*/
46
47	/*******************************************************************************
48	* Header Files *
49	*******************************************************************************/
50	#define LOG_GROUP LOG_GROUP_DEV_PCI
51	/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
52	#define PCI_INCLUDE_PRIVATE
53	#include <VBox/pci.h>
54	#include <VBox/pdmdev.h>
55	#include <iprt/assert.h>
56	#include <iprt/string.h>
57
58	#include "../Builtins.h"
59
60
61	/*******************************************************************************
62	* Structures and Typedefs *
63	*******************************************************************************/
64	/**
65	* PIIX3 ISA Bridge state.
66	*/
67	typedef struct PIIX3State
68	{
69	/** The PCI device of the bridge. */
70	PCIDEVICE dev;
71	} PIIX3State, PIIX3, *PPIIX3;
72
73	/**
74	* PCI Bus instance.
75	*/
76	typedef struct PCIBus
77	{
78	/** Bus number. */
79	int32_t iBus;
80	/** Start device number. */
81	int32_t iDevSearch;
82	/** Number of bridges attached to the bus. */
83	uint32_t cBridges;
84
85	uint32_t Alignment0;
86
87	/** Array of PCI devices. */
88	R3PTRTYPE(PPCIDEVICE) devices[256];
89	/** Array of bridges attached to the bus. */
90	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
91
92	/** R3 pointer to the device instance. */
93	PPDMDEVINSR3 pDevInsR3;
94	/** Pointer to the PCI R3 helpers. */
95	PCPDMPCIHLPR3 pPciHlpR3;
96
97	/** R0 pointer to the device instance. */
98	PPDMDEVINSR0 pDevInsR0;
99	/** Pointer to the PCI R0 helpers. */
100	PCPDMPCIHLPR0 pPciHlpR0;
101
102	/** RC pointer to the device instance. */
103	PPDMDEVINSRC pDevInsRC;
104	/** Pointer to the PCI RC helpers. */
105	PCPDMPCIHLPRC pPciHlpRC;
106
107	/** The PCI device for the PCI bridge. */
108	PCIDEVICE PciDev;
109
110	} PCIBUS;
111	/** Pointer to a PCIBUS instance. */
112	typedef PCIBUS *PPCIBUS;
113	typedef PCIBUS PCIBus;
114
115	/** @def PCI_IRQ_PINS
116	* Number of pins for interrupts (PIRQ#0...PIRQ#3)
117	*/
118	#define PCI_IRQ_PINS 4
119
120	/** @def PCI_APIC_IRQ_PINS
121	* Number of pins for interrupts if the APIC is used.
122	*/
123	#define PCI_APIC_IRQ_PINS 8
124
125	/**
126	* PCI Globals - This is the host-to-pci bridge and the root bus.
127	*/
128	typedef struct PCIGLOBALS
129	{
130	/** Irq levels for the four PCI Irqs.
131	* These count how many devices asserted
132	* the IRQ line. If greater 0 an IRQ is sent to the guest.
133	* If it drops to 0 the IRQ is deasserted.
134	*/
135	volatile uint32_t pci_irq_levels[PCI_IRQ_PINS];
136
137	#if 1 /* Will be moved into the BIOS soon. */
138	/** The next I/O port address which the PCI BIOS will use. */
139	uint32_t pci_bios_io_addr;
140	/** The next MMIO address which the PCI BIOS will use. */
141	uint32_t pci_bios_mem_addr;
142	/** Actual bus number. */
143	uint8_t uBus;
144	#endif
145
146	/** I/O APIC usage flag */
147	bool fUseIoApic;
148	/** I/O APIC irq levels */
149	volatile uint32_t pci_apic_irq_levels[PCI_APIC_IRQ_PINS];
150	/** ACPI IRQ level */
151	uint32_t acpi_irq_level;
152	/** ACPI PIC IRQ */
153	int acpi_irq;
154	/** Config register. */
155	uint32_t uConfigReg;
156
157	/** R3 pointer to the device instance. */
158	PPDMDEVINSR3 pDevInsR3;
159	/** R0 pointer to the device instance. */
160	PPDMDEVINSR0 pDevInsR0;
161	/** RC pointer to the device instance. */
162	PPDMDEVINSRC pDevInsRC;
163
164	#if HC_ARCH_BITS == 64
165	uint32_t Alignment0;
166	#endif
167
168	/** ISA bridge state. */
169	PIIX3 PIIX3State;
170	/** PCI bus which is attached to the host-to-PCI bridge. */
171	PCIBUS PciBus;
172
173	} PCIGLOBALS;
174	/** Pointer to per VM data. */
175	typedef PCIGLOBALS *PPCIGLOBALS;
176
177
178	/*******************************************************************************
179	* Defined Constants And Macros *
180	*******************************************************************************/
181
182	/** Converts a bus instance pointer to a device instance pointer. */
183	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
184	/** Converts a device instance pointer to a PCIGLOBALS pointer. */
185	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
186	/** Converts a device instance pointer to a PCIBUS pointer. */
187	#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->PciBus))
188
189	/** Converts a pointer to a PCI bus instance to a PCIGLOBALS pointer.
190	* @note This works only if the bus number is 0!!!
191	*/
192	#define PCIBUS_2_PCIGLOBALS(pPciBus) ( (PPCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(PCIGLOBALS, PciBus)) )
193
194	/** @def PCI_LOCK
195	* Acquires the PDM lock. This is a NOP if locking is disabled. */
196	/** @def PCI_UNLOCK
197	* Releases the PDM lock. This is a NOP if locking is disabled. */
198	#define PCI_LOCK(pDevIns, rc) \
199	do { \
200	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
201	if (rc2 != VINF_SUCCESS) \
202	return rc2; \
203	} while (0)
204	#define PCI_UNLOCK(pDevIns) \
205	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
206
207	/** @def VBOX_PCI_SAVED_STATE_VERSION
208	* Saved state version of the PCI bus device.
209	*/
210	#define VBOX_PCI_SAVED_STATE_VERSION 3
211
212
213	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
214	/*******************************************************************************
215	* Internal Functions *
216	*******************************************************************************/
217	__BEGIN_DECLS
218
219	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
220	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
221	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
222	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
223	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
224	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
225
226	#ifdef IN_RING3
227	DECLINLINE(PPCIDEVICE) pciFindBridge(PPCIBUS pBus, uint8_t iBus);
228	#endif
229
230	__END_DECLS
231
232	#define DEBUG_PCI
233
234	#define PCI_VENDOR_ID 0x00 /* 16 bits */
235	#define PCI_DEVICE_ID 0x02 /* 16 bits */
236	#define PCI_COMMAND 0x04 /* 16 bits */
237	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
238	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
239	#define PCI_CLASS_DEVICE 0x0a /* Device class */
240	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
241	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
242	#define PCI_MIN_GNT 0x3e /* 8 bits */
243	#define PCI_MAX_LAT 0x3f /* 8 bits */
244
245
246	#ifdef IN_RING3
247
248	static void pci_update_mappings(PCIDevice *d)
249	{
250	PPCIBUS pBus = d->Int.s.CTX_SUFF(pBus);
251	PCIIORegion *r;
252	int cmd, i;
253	uint32_t last_addr, new_addr, config_ofs;
254
255	cmd = RT_LE2H_U16((uint16_t )(d->config + PCI_COMMAND));
256	for(i = 0; i < PCI_NUM_REGIONS; i++) {
257	r = &d->Int.s.aIORegions[i];
258	if (i == PCI_ROM_SLOT) {
259	config_ofs = 0x30;
260	} else {
261	config_ofs = 0x10 + i * 4;
262	}
263	if (r->size != 0) {
264	if (r->type & PCI_ADDRESS_SPACE_IO) {
265	if (cmd & PCI_COMMAND_IO) {
266	new_addr = RT_LE2H_U32((uint32_t )(d->config +
267	config_ofs));
268	new_addr = new_addr & ~(r->size - 1);
269	last_addr = new_addr + r->size - 1;
270	/* NOTE: we have only 64K ioports on PC */
271	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
272	last_addr >= 0x10000) {
273	new_addr = ~0U;
274	}
275	} else {
276	new_addr = ~0U;
277	}
278	} else {
279	if (cmd & PCI_COMMAND_MEMORY) {
280	new_addr = RT_LE2H_U32((uint32_t )(d->config +
281	config_ofs));
282	/* the ROM slot has a specific enable bit */
283	if (i == PCI_ROM_SLOT && !(new_addr & 1))
284	goto no_mem_map;
285	new_addr = new_addr & ~(r->size - 1);
286	last_addr = new_addr + r->size - 1;
287	/* NOTE: we do not support wrapping */
288	/* XXX: as we cannot support really dynamic
289	mappings, we handle specific values as invalid
290	mappings. */
291	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
292	last_addr == ~0U) {
293	new_addr = ~0U;
294	}
295	} else {
296	no_mem_map:
297	new_addr = ~0U;
298	}
299	}
300	/* now do the real mapping */
301	if (new_addr != r->addr) {
302	if (r->addr != ~0U) {
303	if (r->type & PCI_ADDRESS_SPACE_IO) {
304	int devclass;
305	/* NOTE: specific hack for IDE in PC case:
306	only one byte must be mapped. */
307	devclass = d->config[0x0a] \| (d->config[0x0b] << 8);
308	if (devclass == 0x0101 && r->size == 4) {
309	int rc = d->pDevIns->pDevHlpR3->pfnIOPortDeregister(d->pDevIns, r->addr + 2, 1);
310	AssertRC(rc);
311	} else {
312	int rc = d->pDevIns->pDevHlpR3->pfnIOPortDeregister(d->pDevIns, r->addr, r->size);
313	AssertRC(rc);
314	}
315	} else {
316	RTGCPHYS GCPhysBase = r->addr;
317	int rc;
318	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, d->pDevIns, GCPhysBase))
319	{
320	/* unmap it. */
321	rc = r->map_func(d, i, NIL_RTGCPHYS, r->size, (PCIADDRESSSPACE)(r->type));
322	AssertRC(rc);
323	rc = PDMDevHlpMMIO2Unmap(d->pDevIns, i, GCPhysBase);
324	}
325	else
326	rc = d->pDevIns->pDevHlpR3->pfnMMIODeregister(d->pDevIns, GCPhysBase, r->size);
327	AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, d->name, i, GCPhysBase, r->size));
328	}
329	}
330	r->addr = new_addr;
331	if (r->addr != ~0U) {
332	int rc = r->map_func(d, i,
333	r->addr + (r->type & PCI_ADDRESS_SPACE_IO ? 0 : 0),
334	r->size, (PCIADDRESSSPACE)(r->type));
335	AssertRC(rc);
336	}
337	}
338	}
339	}
340	}
341
342
343	static DECLCALLBACK(uint32_t) pci_default_read_config(PCIDevice *d, uint32_t address, unsigned len)
344	{
345	uint32_t val;
346	switch(len) {
347	case 1:
348	val = d->config[address];
349	break;
350	case 2:
351	val = RT_LE2H_U16((uint16_t )(d->config + address));
352	break;
353	default:
354	case 4:
355	val = RT_LE2H_U32((uint32_t )(d->config + address));
356	break;
357	}
358	return val;
359	}
360
361	static DECLCALLBACK(void) pci_default_write_config(PCIDevice *d, uint32_t address, uint32_t val, unsigned len)
362	{
363	int can_write;
364	unsigned i;
365	uint32_t end, addr;
366
367	if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) \|\|
368	(address >= 0x30 && address < 0x34))) {
369	PCIIORegion *r;
370	int reg;
371
372	if ( address >= 0x30 ) {
373	reg = PCI_ROM_SLOT;
374	}else{
375	reg = (address - 0x10) >> 2;
376	}
377	r = &d->Int.s.aIORegions[reg];
378	if (r->size == 0)
379	goto default_config;
380	/* compute the stored value */
381	if (reg == PCI_ROM_SLOT) {
382	/* keep ROM enable bit */
383	val &= (~(r->size - 1)) \| 1;
384	} else {
385	val &= ~(r->size - 1);
386	val \|= r->type;
387	}
388	(uint32_t )(d->config + address) = RT_H2LE_U32(val);
389	pci_update_mappings(d);
390	return;
391	}
392	default_config:
393	/* not efficient, but simple */
394	addr = address;
395	for(i = 0; i < len; i++) {
396	/* default read/write accesses */
397	switch(d->config[0x0e]) {
398	case 0x00: /* normal device */
399	case 0x80: /* multi-function device */
400	switch(addr) {
401	case 0x00:
402	case 0x01:
403	case 0x02:
404	case 0x03:
405	case 0x08:
406	case 0x09:
407	case 0x0a:
408	case 0x0b:
409	case 0x0e:
410	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: /* base */
411	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
412	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
413	case 0x2c: case 0x2d: /* subsystem ID */
414	case 0x2e: case 0x2f: /* vendor ID */
415	case 0x30: case 0x31: case 0x32: case 0x33: /* rom */
416	case 0x3d:
417	can_write = 0;
418	break;
419	default:
420	can_write = 1;
421	break;
422	}
423	break;
424	default:
425	case 0x01: /* bridge */
426	switch(addr) {
427	case 0x00:
428	case 0x01:
429	case 0x02:
430	case 0x03:
431	case 0x08:
432	case 0x09:
433	case 0x0a:
434	case 0x0b:
435	case 0x0e:
436	case 0x38: case 0x39: case 0x3a: case 0x3b: /* rom */
437	case 0x3d:
438	can_write = 0;
439	break;
440	default:
441	can_write = 1;
442	break;
443	}
444	break;
445	}
446	#ifdef VBOX
447	if (addr == 0x06)
448	{
449	/* don't change read-only bits => actually all lower bits are read-only */
450	val &= UINT32_C(~0xff);
451	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
452	d->config[addr] &= ~val;
453	}
454	else if (addr == 0x07)
455	{
456	/* don't change read-only bits */
457	val &= UINT32_C(~0x06);
458	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
459	d->config[addr] &= ~val;
460	}
461	else
462	#endif
463	if (can_write) {
464	d->config[addr] = val;
465	}
466	addr++;
467	val >>= 8;
468	}
469
470	end = address + len;
471	if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
472	/* if the command register is modified, we must modify the mappings */
473	pci_update_mappings(d);
474	}
475	}
476
477	#endif /* IN_RING3 */
478
479	static int pci_data_write(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
480	{
481	uint8_t iBus, iDevice;
482	uint32_t config_addr;
483
484	Log(("pci_data_write: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
485
486	if (!(pGlobals->uConfigReg & (1 << 31))) {
487	return VINF_SUCCESS;
488	}
489	if ((pGlobals->uConfigReg & 0x3) != 0) {
490	return VINF_SUCCESS;
491	}
492	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
493	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
494	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
495	if (iBus != 0)
496	{
497	if (pGlobals->PciBus.cBridges)
498	{
499	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
500	PPCIDEVICE pBridgeDevice = pciFindBridge(&pGlobals->PciBus, iBus);
501	if (pBridgeDevice)
502	{
503	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
504	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, val, len);
505	}
506	#else
507	return VINF_IOM_HC_IOPORT_WRITE;
508	#endif
509	}
510	}
511	else
512	{
513	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
514	if (pci_dev)
515	{
516	#ifdef IN_RING3
517	Log(("pci_config_write: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, val, len));
518	pci_dev->Int.s.pfnConfigWrite(pci_dev, config_addr, val, len);
519	#else
520	return VINF_IOM_HC_IOPORT_WRITE;
521	#endif
522	}
523	}
524	return VINF_SUCCESS;
525	}
526
527	static int pci_data_read(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
528	{
529	uint8_t iBus, iDevice;
530	uint32_t config_addr;
531
532	*pu32 = 0xffffffff;
533
534	if (!(pGlobals->uConfigReg & (1 << 31)))
535	return VINF_SUCCESS;
536	if ((pGlobals->uConfigReg & 0x3) != 0)
537	return VINF_SUCCESS;
538	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
539	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
540	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
541	if (iBus != 0)
542	{
543	if (pGlobals->PciBus.cBridges)
544	{
545	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
546	PPCIDEVICE pBridgeDevice = pciFindBridge(&pGlobals->PciBus, iBus);
547	if (pBridgeDevice)
548	{
549	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
550	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, len);
551	}
552	#else
553	return VINF_IOM_HC_IOPORT_READ;
554	#endif
555	}
556	}
557	else
558	{
559	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
560	if (pci_dev)
561	{
562	#ifdef IN_RING3
563	*pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev, config_addr, len);
564	Log(("pci_config_read: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, *pu32, len));
565	#else
566	return VINF_IOM_HC_IOPORT_READ;
567	#endif
568	}
569	}
570
571	return VINF_SUCCESS;
572	}
573
574
575
576	/* return the global irq number corresponding to a given device irq
577	pin. We could also use the bus number to have a more precise
578	mapping.
579	This is the implementation note described in the PCI spec chapter 2.2.6 */
580	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
581	{
582	int slot_addend;
583	slot_addend = (uDevFn >> 3) - 1;
584	return (irq_num + slot_addend) & 3;
585	}
586
587	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
588	{
589	return (irq_num + (uDevFn >> 3)) & 7;
590	}
591
592	static inline int get_pci_irq_apic_level(PPCIGLOBALS pGlobals, int irq_num)
593	{
594	return (pGlobals->pci_apic_irq_levels[irq_num] != 0);
595	}
596
597	static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int acpi_irq)
598	{
599	/* This is only allowed to be called with a pointer to the host bus. */
600	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
601
602	if (acpi_irq == -1) {
603	int apic_irq, apic_level;
604	PPCIGLOBALS pGlobals = PCIBUS_2_PCIGLOBALS(pBus);
605	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
606
607	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
608	ASMAtomicIncU32(&pGlobals->pci_apic_irq_levels[irq_num]);
609	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
610	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
611
612	apic_irq = irq_num + 0x10;
613	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
614	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
615	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
616	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
617
618	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
619	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
620	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
621	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
622	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
623	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
624	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
625	}
626	} else {
627	Log3(("apic_set_irq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
628	R3STRING(pPciDev->name), irq_num1, iLevel, acpi_irq));
629	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), acpi_irq, iLevel);
630	}
631	}
632
633	DECLINLINE(int) get_pci_irq_level(PPCIGLOBALS pGlobals, int irq_num)
634	{
635	return (pGlobals->pci_irq_levels[irq_num] != 0);
636	}
637
638	/**
639	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
640	*
641	* @param pDevIns Device instance of the host PCI Bus.
642	* @param uDevFn The device number on the host bus which will raise the IRQ
643	* @param pPciDev The PCI device structure which raised the interrupt.
644	* @param iIrq IRQ number to set.
645	* @param iLevel IRQ level.
646	* @remark uDevFn and pPciDev->devfn are not the same if the device is behind a bridge.
647	* In that case uDevFn will be the slot of the bridge which is needed to calculate the
648	* PIRQ value.
649	*/
650	static void pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
651	{
652	PPCIBUS pBus = &pGlobals->PciBus;
653	uint8_t *pbCfg = pGlobals->PIIX3State.dev.config;
654	const bool fIsAcpiDevice = pPciDev->config[2] == 0x13 && pPciDev->config[3] == 0x71;
655	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
656	int pic_irq, pic_level;
657
658	/* Check if the state changed. */
659	if (pPciDev->Int.s.uIrqPinState != iLevel)
660	{
661	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
662
663	/* apic only */
664	if (fIsApicEnabled)
665	{
666	if (fIsAcpiDevice)
667	/*
668	* ACPI needs special treatment since SCI is hardwired and
669	* should not be affected by PCI IRQ routing tables at the
670	* same time SCI IRQ is shared in PCI sense hence this
671	* kludge (i.e. we fetch the hardwired value from ACPIs
672	* PCI device configuration space).
673	*/
674	apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->config[PCI_INTERRUPT_LINE]);
675	else
676	apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1);
677	return;
678	}
679
680	if (fIsAcpiDevice)
681	{
682	/* As per above treat ACPI in a special way */
683	pic_irq = pPciDev->config[PCI_INTERRUPT_LINE];
684	pGlobals->acpi_irq = pic_irq;
685	pGlobals->acpi_irq_level = iLevel & PDM_IRQ_LEVEL_HIGH;
686	}
687	else
688	{
689	int irq_num;
690	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
691
692	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
693	ASMAtomicIncU32(&pGlobals->pci_irq_levels[irq_num]);
694	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
695	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
696
697	/* now we change the pic irq level according to the piix irq mappings */
698	pic_irq = pbCfg[0x60 + irq_num];
699	if (pic_irq >= 16)
700	{
701	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
702	{
703	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
704	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
705	}
706
707	return;
708	}
709	}
710
711	/* the pic level is the logical OR of all the PCI irqs mapped to it */
712	pic_level = 0;
713	if (pic_irq == pbCfg[0x60])
714	pic_level \|= get_pci_irq_level(pGlobals, 0);
715	if (pic_irq == pbCfg[0x61])
716	pic_level \|= get_pci_irq_level(pGlobals, 1);
717	if (pic_irq == pbCfg[0x62])
718	pic_level \|= get_pci_irq_level(pGlobals, 2);
719	if (pic_irq == pbCfg[0x63])
720	pic_level \|= get_pci_irq_level(pGlobals, 3);
721	if (pic_irq == pGlobals->acpi_irq)
722	pic_level \|= pGlobals->acpi_irq_level;
723
724	Log3(("pciSetIrq: %s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d\n",
725	R3STRING(pPciDev->name), iLevel, iIrq, pic_irq, pic_level));
726	pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level);
727
728	/** @todo optimize pci irq flip-flop some rainy day. */
729	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
730	pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW);
731	}
732	}
733
734	/**
735	* Set the IRQ for a PCI device on the host bus.
736	*
737	* @param pDevIns Device instance of the PCI Bus.
738	* @param pPciDev The PCI device structure.
739	* @param iIrq IRQ number to set.
740	* @param iLevel IRQ level.
741	*/
742	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
743	{
744	pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
745	}
746
747	#ifdef IN_RING3
748
749	/**
750	* Finds a bridge on the bus which contains the destination bus.
751	*
752	* @return Pointer to the device instance data of the bus or
753	* NULL if no bridge was found.
754	* @param pBus Pointer to the bus to search on.
755	* @param iBus Destination bus number.
756	*/
757	DECLINLINE(PPCIDEVICE) pciFindBridge(PPCIBUS pBus, uint8_t iBus)
758	{
759	/* Search for a fitting bridge. */
760	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
761	{
762	/*
763	* Examine secondary and subordinate bus number.
764	* If the target bus is in the range we pass the request on to the bridge.
765	*/
766	PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
767	AssertMsg(pBridgeTemp && pBridgeTemp->Int.s.fPciToPciBridge,
768	("Device is not a PCI bridge but on the list of PCI bridges\n"));
769
770	if ( iBus >= pBridgeTemp->config[VBOX_PCI_SECONDARY_BUS]
771	&& iBus <= pBridgeTemp->config[VBOX_PCI_SUBORDINATE_BUS])
772	return pBridgeTemp;
773	}
774
775	/* Nothing found. */
776	return NULL;
777	}
778
779	static void piix3_reset(PIIX3State *d)
780	{
781	uint8_t *pci_conf = d->dev.config;
782
783	pci_conf[0x04] = 0x07; /* master, memory and I/O */
784	pci_conf[0x05] = 0x00;
785	pci_conf[0x06] = 0x00;
786	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
787	pci_conf[0x4c] = 0x4d;
788	pci_conf[0x4e] = 0x03;
789	pci_conf[0x4f] = 0x00;
790	pci_conf[0x60] = 0x80;
791	pci_conf[0x69] = 0x02;
792	pci_conf[0x70] = 0x80;
793	pci_conf[0x76] = 0x0c;
794	pci_conf[0x77] = 0x0c;
795	pci_conf[0x78] = 0x02;
796	pci_conf[0x79] = 0x00;
797	pci_conf[0x80] = 0x00;
798	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
799	pci_conf[0xa0] = 0x08;
800	pci_conf[0xa0] = 0x08;
801	pci_conf[0xa2] = 0x00;
802	pci_conf[0xa3] = 0x00;
803	pci_conf[0xa4] = 0x00;
804	pci_conf[0xa5] = 0x00;
805	pci_conf[0xa6] = 0x00;
806	pci_conf[0xa7] = 0x00;
807	pci_conf[0xa8] = 0x0f;
808	pci_conf[0xaa] = 0x00;
809	pci_conf[0xab] = 0x00;
810	pci_conf[0xac] = 0x00;
811	pci_conf[0xae] = 0x00;
812	}
813
814	static void pci_config_writel(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
815	{
816	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
817	(uDevFn << 8) \| addr;
818	pci_data_write(pGlobals, 0, val, 4);
819	}
820
821	static void pci_config_writew(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
822	{
823	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
824	(uDevFn << 8) \| (addr & ~3);
825	pci_data_write(pGlobals, addr & 3, val, 2);
826	}
827
828	static void pci_config_writeb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
829	{
830	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
831	(uDevFn << 8) \| (addr & ~3);
832	pci_data_write(pGlobals, addr & 3, val, 1);
833	}
834
835	static uint32_t pci_config_readl(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
836	{
837	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
838	(uDevFn << 8) \| addr;
839	uint32_t u32Val;
840	int rc = pci_data_read(pGlobals, 0, 4, &u32Val);
841	AssertRC(rc);
842	return u32Val;
843	}
844
845	static uint32_t pci_config_readw(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
846	{
847	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
848	(uDevFn << 8) \| (addr & ~3);
849	uint32_t u32Val;
850	int rc = pci_data_read(pGlobals, addr & 3, 2, &u32Val);
851	AssertRC(rc);
852	return u32Val;
853	}
854
855	static uint32_t pci_config_readb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
856	{
857	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
858	(uDevFn << 8) \| (addr & ~3);
859	uint32_t u32Val;
860	int rc = pci_data_read(pGlobals, addr & 3, 1, &u32Val);
861	AssertRC(rc);
862	return u32Val;
863	}
864
865	/* host irqs corresponding to PCI irqs A-D */
866	static const uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; /* bird: added const */
867
868	static void pci_set_io_region_addr(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int region_num, uint32_t addr)
869	{
870	uint16_t cmd;
871	uint32_t ofs;
872
873	if ( region_num == PCI_ROM_SLOT )
874	ofs = 0x30;
875	else
876	ofs = 0x10 + region_num * 4;
877
878	/* Read memory type first. */
879	uint8_t uRessourceType = pci_config_readb(pGlobals, uBus, uDevFn, ofs);
880
881	/* Read command register. */
882	cmd = pci_config_readw(pGlobals, uBus, uDevFn, PCI_COMMAND);
883	if ( region_num == PCI_ROM_SLOT )
884	cmd \|= 2;
885	else if ((uRessourceType & 0x01) == 1) /* Test if region is I/O space. */
886	cmd \|= 1; /* Enable I/O space access. */
887	else /* The region is MMIO. */
888	cmd \|= 2; /* Enable MMIO access. */
889
890	/* Write address of the device. */
891	pci_config_writel(pGlobals, uBus, uDevFn, ofs, addr);
892
893	/* enable memory mappings */
894	pci_config_writew(pGlobals, uBus, uDevFn, PCI_COMMAND, cmd);
895	}
896
897	static void pci_bios_init_device(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
898	{
899	uint32_t *paddr;
900	int i, pin, pic_irq;
901	uint16_t devclass, vendor_id, device_id;
902
903	devclass = pci_config_readw(pGlobals, uBus, uDevFn, PCI_CLASS_DEVICE);
904	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
905	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
906
907	/* Check if device is present. */
908	if (vendor_id != 0xffff)
909	{
910	switch(devclass)
911	{
912	case 0x0101:
913	if ( (vendor_id == 0x8086)
914	&& (device_id == 0x7010 \|\| device_id == 0x7111))
915	{
916	/* PIIX3 or PIIX4 IDE */
917	pci_config_writew(pGlobals, uBus, uDevFn, 0x40, 0x8000); /* enable IDE0 */
918	pci_config_writew(pGlobals, uBus, uDevFn, 0x42, 0x8000); /* enable IDE1 */
919	goto default_map;
920	}
921	else
922	{
923	/* IDE: we map it as in ISA mode */
924	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x1f0);
925	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 1, 0x3f4);
926	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 2, 0x170);
927	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 3, 0x374);
928	}
929	break;
930	case 0x0300:
931	if (vendor_id != 0x80ee)
932	goto default_map;
933	/* VGA: map frame buffer to default Bochs VBE address */
934	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0xE0000000);
935	break;
936	case 0x0800:
937	/* PIC */
938	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
939	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
940	if (vendor_id == 0x1014)
941	{
942	/* IBM */
943	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
944	{
945	/* MPIC & MPIC2 */
946	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
947	}
948	}
949	break;
950	case 0xff00:
951	if ( (vendor_id == 0x0106b)
952	&& (device_id == 0x0017 \|\| device_id == 0x0022))
953	{
954	/* macio bridge */
955	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000);
956	}
957	break;
958	case 0x0604:
959	{
960	/* Init PCI-to-PCI bridge. */
961	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus);
962
963	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
964	pGlobals->uBus++;
965	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
966	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
967
968	/* Add position of this bridge into the array. */
969	paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
970
971	/*
972	* The I/O range for the bridge must be aligned to a 4KB boundary.
973	* This does not change anything really as the access to the device is not going
974	* through the bridge but we want to be compliant to the spec.
975	*/
976	if ((pGlobals->pci_bios_io_addr % 4096) != 0)
977	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
978	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_io_addr));
979	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->pci_bios_io_addr >> 8) & 0xf0);
980
981	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
982	if ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0)
983	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
984	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_mem_addr));
985	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xffff0));
986
987	/* Save values to compare later to. */
988	uint32_t u32IoAddressBase = pGlobals->pci_bios_io_addr;
989	uint32_t u32MMIOAddressBase = pGlobals->pci_bios_mem_addr;
990
991	/* Init devices behind the bridge and possibly other bridges as well. */
992	for (int i = 0; i <= 255; i++)
993	pci_bios_init_device(pGlobals, uBus + 1, i, cBridgeDepth + 1, paBridgePositions);
994
995	/* The number of bridges behind the this one is now available. */
996	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
997
998	/*
999	* Set I/O limit register. If there is no device with I/O space behind the bridge
1000	* we set a lower value than in the base register.
1001	* The result with a real bridge is that no I/O transactions are passed to the secondary
1002	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1003	*/
1004	if ((u32IoAddressBase != pGlobals->pci_bios_io_addr) && ((pGlobals->pci_bios_io_addr % 4096) != 0))
1005	{
1006	/* The upper boundary must be one byte less than a 4KB boundary. */
1007	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
1008	}
1009	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->pci_bios_io_addr >> 8) & 0xf0) - 1);
1010
1011	/* Same with the MMIO limit register but with 1MB boundary here. */
1012	if ((u32MMIOAddressBase != pGlobals->pci_bios_mem_addr) && ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0))
1013	{
1014	/* The upper boundary must be one byte less than a 1MB boundary. */
1015	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
1016	}
1017	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xfff0)) - 1);
1018
1019	/*
1020	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1021	* which may be behind a bridge. Thatswhy it is unconditionally disabled here atm by writing a higher value into
1022	* the base register than in the limit register.
1023	*/
1024	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
1025	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
1026	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
1027	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
1028	break;
1029	}
1030	default:
1031	default_map:
1032	{
1033	/* default memory mappings */
1034	/*
1035	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
1036	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
1037	*/
1038	for(i = 0; i < (PCI_NUM_REGIONS-1); i++)
1039	{
1040	uint32_t u32Size;
1041	uint8_t u8RessourceType;
1042	uint32_t u32Address = 0x10 + i * 4;
1043
1044	/* Calculate size. */
1045	u8RessourceType = pci_config_readb(pGlobals, uBus, uDevFn, u32Address);
1046	pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff));
1047	u32Size = pci_config_readl(pGlobals, uBus, uDevFn, u32Address);
1048	/* Clear ressource information depending on ressource type. */
1049	if ((u8RessourceType & 0x01) == 1) /* I/O */
1050	u32Size &= ~(0x01);
1051	else /* MMIO */
1052	u32Size &= ~(0x0f);
1053
1054	/*
1055	* Invert all bits and add 1 to get size of the region.
1056	* (From PCI implementation note)
1057	*/
1058	if (((u8RessourceType & 0x01) == 1) && (u32Size & UINT32_C(0xffff0000)) == 0)
1059	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
1060	else
1061	u32Size = (~u32Size) + 1;
1062
1063	Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, i, uDevFn, uBus, u32Size));
1064
1065	if (u32Size)
1066	{
1067	if ((u8RessourceType & 0x01) == 1)
1068	paddr = &pGlobals->pci_bios_io_addr;
1069	else
1070	paddr = &pGlobals->pci_bios_mem_addr;
1071	paddr = (paddr + u32Size - 1) & ~(u32Size - 1);
1072	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, ((u8RessourceType & 0x01) == 1 ? "I/O" : "MMIO"), i, *paddr));
1073	pci_set_io_region_addr(pGlobals, uBus, uDevFn, i, *paddr);
1074	*paddr += u32Size;
1075	Log(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1076	}
1077	}
1078	break;
1079	}
1080	}
1081
1082	/* map the interrupt */
1083	pin = pci_config_readb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_PIN);
1084	if (pin != 0)
1085	{
1086	uint8_t uBridgeDevFn = uDevFn;
1087	pin--;
1088
1089	/* We need to go up to the host bus to see which irq this device will assert there. */
1090	while (cBridgeDepth != 0)
1091	{
1092	/* Get the pin the device would assert on the bridge. */
1093	pin = ((uBridgeDevFn >> 3) + pin) & 3;
1094	uBridgeDevFn = paBridgePositions[cBridgeDepth];
1095	cBridgeDepth--;
1096	}
1097
1098	pin = pci_slot_get_pirq(uDevFn, pin);
1099	pic_irq = pci_irqs[pin];
1100	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);
1101	}
1102	}
1103	}
1104
1105	#endif /* IN_RING3 */
1106
1107	/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
1108
1109	/**
1110	* Port I/O Handler for PCI address OUT operations.
1111	*
1112	* @returns VBox status code.
1113	*
1114	* @param pDevIns The device instance.
1115	* @param pvUser User argument - ignored.
1116	* @param uPort Port number used for the IN operation.
1117	* @param u32 The value to output.
1118	* @param cb The value size in bytes.
1119	*/
1120	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1121	{
1122	Log(("pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1123	NOREF(pvUser);
1124	if (cb == 4)
1125	{
1126	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1127	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
1128	pThis->uConfigReg = u32;
1129	PCI_UNLOCK(pDevIns);
1130	}
1131	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1132	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1133	return VINF_SUCCESS;
1134	}
1135
1136
1137	/**
1138	* Port I/O Handler for PCI address IN operations.
1139	*
1140	* @returns VBox status code.
1141	*
1142	* @param pDevIns The device instance.
1143	* @param pvUser User argument - ignored.
1144	* @param uPort Port number used for the IN operation.
1145	* @param pu32 Where to store the result.
1146	* @param cb Number of bytes read.
1147	*/
1148	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1149	{
1150	NOREF(pvUser);
1151	if (cb == 4)
1152	{
1153	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1154	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
1155	*pu32 = pThis->uConfigReg;
1156	PCI_UNLOCK(pDevIns);
1157	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
1158	return VINF_SUCCESS;
1159	}
1160	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1161	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1162	Log(("pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
1163	return VERR_IOM_IOPORT_UNUSED;
1164	}
1165
1166
1167	/**
1168	* Port I/O Handler for PCI data OUT operations.
1169	*
1170	* @returns VBox status code.
1171	*
1172	* @param pDevIns The device instance.
1173	* @param pvUser User argument - ignored.
1174	* @param uPort Port number used for the IN operation.
1175	* @param u32 The value to output.
1176	* @param cb The value size in bytes.
1177	*/
1178	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1179	{
1180	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1181	NOREF(pvUser);
1182	int rc = VINF_SUCCESS;
1183	if (!(Port % cb))
1184	{
1185	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
1186	rc = pci_data_write(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
1187	PCI_UNLOCK(pDevIns);
1188	}
1189	else
1190	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
1191	return rc;
1192	}
1193
1194
1195	/**
1196	* Port I/O Handler for PCI data IN operations.
1197	*
1198	* @returns VBox status code.
1199	*
1200	* @param pDevIns The device instance.
1201	* @param pvUser User argument - ignored.
1202	* @param uPort Port number used for the IN operation.
1203	* @param pu32 Where to store the result.
1204	* @param cb Number of bytes read.
1205	*/
1206	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1207	{
1208	NOREF(pvUser);
1209	if (!(Port % cb))
1210	{
1211	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
1212	int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
1213	PCI_UNLOCK(pDevIns);
1214	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
1215	return rc;
1216	}
1217	AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
1218	return VERR_IOM_IOPORT_UNUSED;
1219	}
1220
1221	#ifdef IN_RING3
1222
1223	/**
1224	* Saves a state of the PCI device.
1225	*
1226	* @returns VBox status code.
1227	* @param pDevIns Device instance of the PCI Bus.
1228	* @param pPciDev Pointer to PCI device.
1229	* @param pSSMHandle The handle to save the state to.
1230	*/
1231	static DECLCALLBACK(int) pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSMHandle)
1232	{
1233	return SSMR3PutMem(pSSMHandle, &pPciDev->config[0], sizeof(pPciDev->config));
1234	}
1235
1236
1237	/**
1238	* Loads a saved PCI device state.
1239	*
1240	* @returns VBox status code.
1241	* @param pDevIns Device instance of the PCI Bus.
1242	* @param pPciDev Pointer to PCI device.
1243	* @param pSSMHandle The handle to the saved state.
1244	*/
1245	static DECLCALLBACK(int) pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSMHandle)
1246	{
1247	return SSMR3GetMem(pSSMHandle, &pPciDev->config[0], sizeof(pPciDev->config));
1248	}
1249
1250
1251	/**
1252	* Saves a state of the PCI device.
1253	*
1254	* @returns VBox status code.
1255	* @param pDevIns The device instance.
1256	* @param pPciDev Pointer to PCI device.
1257	* @param pSSMHandle The handle to save the state to.
1258	*/
1259	static DECLCALLBACK(int) pciSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1260	{
1261	uint32_t i;
1262	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1263	PPCIBUS pBus = &pThis->PciBus;
1264
1265	/*
1266	* Bus state data.
1267	*/
1268	SSMR3PutU32(pSSMHandle, pThis->uConfigReg);
1269	SSMR3PutBool(pSSMHandle, pThis->fUseIoApic);
1270	/*
1271	* Save IRQ states.
1272	*/
1273	for (i = 0; i < PCI_IRQ_PINS; i++)
1274	SSMR3PutU32(pSSMHandle, pThis->pci_irq_levels[i]);
1275	for (i = 0; i < PCI_APIC_IRQ_PINS; i++)
1276	SSMR3PutU32(pSSMHandle, pThis->pci_apic_irq_levels[i]);
1277
1278	SSMR3PutU32(pSSMHandle, pThis->acpi_irq_level);
1279	SSMR3PutS32(pSSMHandle, pThis->acpi_irq);
1280
1281	SSMR3PutU32(pSSMHandle, ~0); /* separator */
1282
1283	/*
1284	* Iterate all the devices.
1285	*/
1286	for (i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1287	{
1288	PPCIDEVICE pDev = pBus->devices[i];
1289	if (pDev)
1290	{
1291	int rc;
1292	SSMR3PutU32(pSSMHandle, i);
1293	SSMR3PutMem(pSSMHandle, pDev->config, sizeof(pDev->config));
1294
1295	rc = SSMR3PutS32(pSSMHandle, pDev->Int.s.uIrqPinState);
1296	if (RT_FAILURE(rc))
1297	return rc;
1298	}
1299	}
1300	return SSMR3PutU32(pSSMHandle, ~0); /* terminator */
1301	}
1302
1303	/**
1304	* Loads a saved PCI device state.
1305	*
1306	* @returns VBox status code.
1307	* @param pDevIns The device instance.
1308	* @param pSSMHandle The handle to the saved state.
1309	* @param u32Version The data unit version number.
1310	*/
1311	static DECLCALLBACK(int) pciLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
1312	{
1313	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1314	PPCIBUS pBus = &pThis->PciBus;
1315	uint32_t u32;
1316	uint32_t i;
1317	int rc;
1318
1319	/*
1320	* Check the version.
1321	*/
1322	if (u32Version > VBOX_PCI_SAVED_STATE_VERSION)
1323	{
1324	AssertFailed();
1325	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1326	}
1327
1328	/*
1329	* Bus state data.
1330	*/
1331	SSMR3GetU32(pSSMHandle, &pThis->uConfigReg);
1332	if (u32Version > 1)
1333	SSMR3GetBool(pSSMHandle, &pThis->fUseIoApic);
1334
1335	/* Load IRQ states. */
1336	if (u32Version > 2)
1337	{
1338	for (uint8_t i = 0; i < PCI_IRQ_PINS; i++)
1339	SSMR3GetU32(pSSMHandle, (uint32_t *)&pThis->pci_irq_levels[i]);
1340	for (uint8_t i = 0; i < PCI_APIC_IRQ_PINS; i++)
1341	SSMR3GetU32(pSSMHandle, (uint32_t *)&pThis->pci_apic_irq_levels[i]);
1342
1343	SSMR3GetU32(pSSMHandle, &pThis->acpi_irq_level);
1344	SSMR3GetS32(pSSMHandle, &pThis->acpi_irq);
1345	}
1346
1347	/* separator */
1348	rc = SSMR3GetU32(pSSMHandle, &u32);
1349	if (RT_FAILURE(rc))
1350	return rc;
1351	if (u32 != (uint32_t)~0)
1352	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1353
1354	/*
1355	* Iterate all the devices.
1356	*/
1357	for (i = 0;; i++)
1358	{
1359	PCIDEVICE DevTmp;
1360	PPCIDEVICE pDev;
1361
1362	/* index / terminator */
1363	rc = SSMR3GetU32(pSSMHandle, &u32);
1364	if (RT_FAILURE(rc))
1365	return rc;
1366	if (u32 == (uint32_t)~0)
1367	break;
1368	if ( u32 >= RT_ELEMENTS(pBus->devices)
1369	\|\| u32 < i)
1370	{
1371	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1372	return rc;
1373	}
1374
1375	/* skip forward to the device checking that no new devices are present. */
1376	for (; i < u32; i++)
1377	{
1378	if (pBus->devices[i])
1379	{
1380	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pBus->devices[i]->name,
1381	PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i])));
1382	if (SSMR3HandleGetAfter(pSSMHandle) != SSMAFTER_DEBUG_IT)
1383	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
1384	}
1385	}
1386
1387	/* Get the data */
1388	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1389	SSMR3GetMem(pSSMHandle, DevTmp.config, sizeof(DevTmp.config));
1390	if (u32Version < 3)
1391	{
1392	int32_t i32Temp;
1393	/* Irq value not needed anymore. */
1394	rc = SSMR3GetS32(pSSMHandle, &i32Temp);
1395	if (RT_FAILURE(rc))
1396	return rc;
1397	}
1398	else
1399	{
1400	rc = SSMR3GetS32(pSSMHandle, &DevTmp.Int.s.uIrqPinState);
1401	if (RT_FAILURE(rc))
1402	return rc;
1403	}
1404
1405	/* check that it's still around. */
1406	pDev = pBus->devices[i];
1407	if (!pDev)
1408	{
1409	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1410	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1411	if (SSMR3HandleGetAfter(pSSMHandle) != SSMAFTER_DEBUG_IT)
1412	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
1413	continue;
1414	}
1415
1416	/* match the vendor id assuming that this will never be changed. */
1417	if ( DevTmp.config[0] != pDev->config[0]
1418	\|\| DevTmp.config[1] != pDev->config[1])
1419	{
1420	LogRel(("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs\n",
1421	i, pDev->name, DevTmp.config, pDev->config));
1422	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
1423	}
1424
1425	/* commit the loaded device config. */
1426	memcpy(pDev->config, DevTmp.config, sizeof(pDev->config));
1427
1428	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1429	}
1430
1431	return VINF_SUCCESS;
1432	}
1433
1434
1435	/* -=-=-=-=-=- real code -=-=-=-=-=- */
1436
1437	/**
1438	* Registers the device with the specified PCI bus.
1439	*
1440	* @returns VBox status code.
1441	* @param pBus The bus to register with.
1442	* @param iDev The PCI device ordinal.
1443	* @param pPciDev The PCI device structure.
1444	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1445	*/
1446	static int pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1447	{
1448	/*
1449	* Find device slot.
1450	*/
1451	if (iDev < 0)
1452	{
1453	/*
1454	* Special check for the IDE controller which is our function 1 device
1455	* before searching.
1456	*/
1457	if ( !strcmp(pszName, "piix3ide")
1458	&& !pBus->devices[9])
1459	iDev = 9;
1460	else
1461	{
1462	Assert(!(pBus->iDevSearch % 8));
1463	for (iDev = pBus->iDevSearch; iDev < (int)RT_ELEMENTS(pBus->devices); iDev += 8)
1464	if ( !pBus->devices[iDev]
1465	&& !pBus->devices[iDev + 1]
1466	&& !pBus->devices[iDev + 2]
1467	&& !pBus->devices[iDev + 3]
1468	&& !pBus->devices[iDev + 4]
1469	&& !pBus->devices[iDev + 5]
1470	&& !pBus->devices[iDev + 6]
1471	&& !pBus->devices[iDev + 7])
1472	break;
1473	if (iDev >= (int)RT_ELEMENTS(pBus->devices))
1474	{
1475	AssertMsgFailed(("Couldn't find free spot!\n"));
1476	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1477	}
1478	}
1479	pPciDev->Int.s.fRequestedDevFn = false;
1480	}
1481	else
1482	{
1483	/*
1484	* An explicit request.
1485	*
1486	* If the slot is occupied we'll have to relocate the device
1487	* currently occupying it first. This can only be done if the
1488	* existing device wasn't explicitly assigned. Also we limit
1489	* ourselves to function 0 devices.
1490	*
1491	* If you start setting devices + function in the
1492	* config, do it for all pci devices!
1493	*/
1494	//AssertReleaseMsg(iDev > 8 \|\| pBus->iBus != 0, ("iDev=%d pszName=%s\n", iDev, pszName));
1495	if (pBus->devices[iDev])
1496	{
1497	int iDevRel;
1498	AssertReleaseMsg(!(iDev % 8), ("PCI Configuration Conflict! iDev=%d pszName=%s clashes with %s\n",
1499	iDev, pszName, pBus->devices[iDev]->name));
1500	if ( pBus->devices[iDev]->Int.s.fRequestedDevFn
1501	\|\| (pBus->devices[iDev + 1] && pBus->devices[iDev + 1]->Int.s.fRequestedDevFn)
1502	\|\| (pBus->devices[iDev + 2] && pBus->devices[iDev + 2]->Int.s.fRequestedDevFn)
1503	\|\| (pBus->devices[iDev + 3] && pBus->devices[iDev + 3]->Int.s.fRequestedDevFn)
1504	\|\| (pBus->devices[iDev + 4] && pBus->devices[iDev + 4]->Int.s.fRequestedDevFn)
1505	\|\| (pBus->devices[iDev + 5] && pBus->devices[iDev + 5]->Int.s.fRequestedDevFn)
1506	\|\| (pBus->devices[iDev + 6] && pBus->devices[iDev + 6]->Int.s.fRequestedDevFn)
1507	\|\| (pBus->devices[iDev + 7] && pBus->devices[iDev + 7]->Int.s.fRequestedDevFn))
1508	{
1509	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1510	pszName, pBus->devices[iDev]->name, iDev));
1511	return VERR_INTERNAL_ERROR;
1512	}
1513
1514	/* Find free slot for the device(s) we're moving and move them. */
1515	for (iDevRel = pBus->iDevSearch; iDevRel < (int)RT_ELEMENTS(pBus->devices); iDevRel += 8)
1516	{
1517	if ( !pBus->devices[iDevRel]
1518	&& !pBus->devices[iDevRel + 1]
1519	&& !pBus->devices[iDevRel + 2]
1520	&& !pBus->devices[iDevRel + 3]
1521	&& !pBus->devices[iDevRel + 4]
1522	&& !pBus->devices[iDevRel + 5]
1523	&& !pBus->devices[iDevRel + 6]
1524	&& !pBus->devices[iDevRel + 7])
1525	{
1526	int i = 0;
1527	for (i = 0; i < 8; i++)
1528	{
1529	if (!pBus->devices[iDev + i])
1530	continue;
1531	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->devices[iDev + i]->name, iDev + i, iDevRel + i));
1532	pBus->devices[iDevRel + i] = pBus->devices[iDev + i];
1533	pBus->devices[iDevRel + i]->devfn = i;
1534	pBus->devices[iDev + i] = NULL;
1535	}
1536	}
1537	}
1538	if (pBus->devices[iDev])
1539	{
1540	AssertMsgFailed(("Couldn't find free spot!\n"));
1541	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1542	}
1543	} /* if conflict */
1544	pPciDev->Int.s.fRequestedDevFn = true;
1545	}
1546
1547	Assert(!pBus->devices[iDev]);
1548	pPciDev->devfn = iDev;
1549	pPciDev->name = pszName;
1550	pPciDev->Int.s.pBusR3 = pBus;
1551	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1552	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1553	pPciDev->Int.s.pfnConfigRead = pci_default_read_config;
1554	pPciDev->Int.s.pfnConfigWrite = pci_default_write_config;
1555	pBus->devices[iDev] = pPciDev;
1556	if (pPciDev->Int.s.fPciToPciBridge)
1557	{
1558	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->devices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
1559	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
1560	("device is a bridge but does not implement read/write functions\n"));
1561	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
1562	pBus->cBridges++;
1563	}
1564
1565	Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
1566	iDev >> 3, iDev & 7, 0x80000000 \| (iDev << 8), pszName));
1567
1568	return VINF_SUCCESS;
1569	}
1570
1571
1572	/**
1573	* Registers the device with the default PCI bus.
1574	*
1575	* @returns VBox status code.
1576	* @param pDevIns Device instance of the PCI Bus.
1577	* @param pPciDev The PCI device structure.
1578	* Any PCI enabled device must keep this in it's instance data!
1579	* Fill in the PCI data config before registration, please.
1580	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1581	* @param iDev The PCI device number. Use a negative value for auto assigning one.
1582	*/
1583	static DECLCALLBACK(int) pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
1584	{
1585	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
1586
1587	/*
1588	* Check input.
1589	*/
1590	if ( !pszName
1591	\|\| !pPciDev
1592	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices)
1593	\|\| (iDev >= 0 && iDev <= 8))
1594	{
1595	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1596	return VERR_INVALID_PARAMETER;
1597	}
1598
1599	/*
1600	* Register the device.
1601	*/
1602	return pciRegisterInternal(pBus, iDev, pPciDev, pszName);
1603	}
1604
1605
1606	static DECLCALLBACK(int) pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1607	{
1608	/*
1609	* Validate.
1610	*/
1611	AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
1612	\|\| enmType == PCI_ADDRESS_SPACE_IO
1613	\|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
1614	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
1615	VERR_INVALID_PARAMETER);
1616	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
1617	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
1618	VERR_INVALID_PARAMETER);
1619	int iLastSet = ASMBitLastSetU32(cbRegion);
1620	AssertMsgReturn( iLastSet != 0
1621	&& RT_BIT_32(iLastSet - 1) == cbRegion,
1622	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1623	VERR_INVALID_PARAMETER);
1624
1625	/*
1626	* Register the I/O region.
1627	*/
1628	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1629	pRegion->addr = ~0U;
1630	pRegion->size = cbRegion;
1631	pRegion->type = enmType;
1632	pRegion->map_func = pfnCallback;
1633
1634	/* Set type in the config space. */
1635	uint32_t u32Address = 0x10 + iRegion * 4;
1636	uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
1637	\| (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
1638	(uint32_t )(pPciDev->config + u32Address) = RT_H2LE_U32(u32Value);
1639
1640	return VINF_SUCCESS;
1641	}
1642
1643
1644	/**
1645	* @copydoc PDMPCIBUSREG::pfnSetConfigCallbacksR3
1646	*/
1647	static DECLCALLBACK(void) pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1648	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1649	{
1650	if (ppfnReadOld)
1651	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1652	pPciDev->Int.s.pfnConfigRead = pfnRead;
1653
1654	if (ppfnWriteOld)
1655	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1656	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1657	}
1658
1659
1660	/**
1661	* Called to perform the job of the bios.
1662	*
1663	* @returns VBox status.
1664	* @param pDevIns Device instance of the first bus.
1665	*/
1666	static DECLCALLBACK(int) pciFakePCIBIOS(PPDMDEVINS pDevIns)
1667	{
1668	int rc;
1669	unsigned i;
1670	uint8_t elcr[2] = {0, 0};
1671	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1672	PVM pVM = PDMDevHlpGetVM(pDevIns);
1673	Assert(pVM);
1674
1675	/*
1676	* Set the start addresses.
1677	*/
1678	pGlobals->pci_bios_io_addr = 0xc000;
1679	pGlobals->pci_bios_mem_addr = UINT32_C(0xf0000000);
1680	pGlobals->uBus = 0;
1681
1682	/*
1683	* Activate IRQ mappings.
1684	*/
1685	for (i = 0; i < 4; i++)
1686	{
1687	uint8_t irq = pci_irqs[i];
1688	/* Set to trigger level. */
1689	elcr[irq >> 3] \|= (1 << (irq & 7));
1690	/* Activate irq remapping in PIIX3. */
1691	pci_config_writeb(pGlobals, 0, pGlobals->PIIX3State.dev.devfn, 0x60 + i, irq);
1692	}
1693
1694	/* Tell to the PIC. */
1695	rc = IOMIOPortWrite(pVM, 0x4d0, elcr[0], sizeof(uint8_t));
1696	if (rc == VINF_SUCCESS)
1697	rc = IOMIOPortWrite(pVM, 0x4d1, elcr[1], sizeof(uint8_t));
1698	if (rc != VINF_SUCCESS)
1699	{
1700	AssertMsgFailed(("Writing to PIC failed!\n"));
1701	return RT_SUCCESS(rc) ? VERR_INTERNAL_ERROR : rc;
1702	}
1703
1704	/*
1705	* Init the devices.
1706	*/
1707	for (i = 0; i < 256; i++)
1708	{
1709	uint8_t aBridgePositions[256];
1710
1711	memset(aBridgePositions, 0, sizeof(aBridgePositions));
1712	Log2(("PCI: Initializing device %d (%#x)\n",
1713	i, 0x80000000 \| (i << 8)));
1714	pci_bios_init_device(pGlobals, 0, i, 0, aBridgePositions);
1715	}
1716
1717	return VINF_SUCCESS;
1718	}
1719
1720	/**
1721	* @copydoc FNPDMDEVRELOCATE
1722	*/
1723	static DECLCALLBACK(void) pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1724	{
1725	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1726	PPCIBUS pBus = &pGlobals->PciBus;
1727	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1728
1729	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
1730	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1731
1732	/* Relocate RC pointers for the attached pci devices. */
1733	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1734	{
1735	if (pBus->devices[i])
1736	pBus->devices[i]->Int.s.pBusRC += offDelta;
1737	}
1738	}
1739
1740
1741	/**
1742	* Construct a host to PCI Bus device instance for a VM.
1743	*
1744	* @returns VBox status.
1745	* @param pDevIns The device instance data.
1746	* If the registration structure is needed, pDevIns->pDevReg points to it.
1747	* @param iInstance Instance number. Use this to figure out which registers and such to use.
1748	* The device number is also found in pDevIns->iInstance, but since it's
1749	* likely to be freqently used PDM passes it as parameter.
1750	* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
1751	* of the device instance. It's also found in pDevIns->pCfgHandle, but like
1752	* iInstance it's expected to be used a bit in this function.
1753	*/
1754	static DECLCALLBACK(int) pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1755	{
1756	int rc;
1757	Assert(iInstance == 0);
1758
1759	/*
1760	* Validate and read configuration.
1761	*/
1762	if (!CFGMR3AreValuesValid(pCfgHandle, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
1763	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1764
1765	/* query whether we got an IOAPIC */
1766	bool fUseIoApic;
1767	rc = CFGMR3QueryBoolDef(pCfgHandle, "IOAPIC", &fUseIoApic, false);
1768	if (RT_FAILURE(rc))
1769	return PDMDEV_SET_ERROR(pDevIns, rc,
1770	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
1771
1772	/* check if RC code is enabled. */
1773	bool fGCEnabled;
1774	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
1775	if (RT_FAILURE(rc))
1776	return PDMDEV_SET_ERROR(pDevIns, rc,
1777	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
1778
1779	/* check if R0 code is enabled. */
1780	bool fR0Enabled;
1781	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
1782	if (RT_FAILURE(rc))
1783	return PDMDEV_SET_ERROR(pDevIns, rc,
1784	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
1785	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
1786
1787	/*
1788	* Init data and register the PCI bus.
1789	*/
1790	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1791	pGlobals->pci_bios_io_addr = 0xc000;
1792	pGlobals->pci_bios_mem_addr = 0xf0000000;
1793	memset((void *)&pGlobals->pci_irq_levels, 0, sizeof(pGlobals->pci_irq_levels));
1794	pGlobals->fUseIoApic = fUseIoApic;
1795	memset((void *)&pGlobals->pci_apic_irq_levels, 0, sizeof(pGlobals->pci_apic_irq_levels));
1796
1797	pGlobals->pDevInsR3 = pDevIns;
1798	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1799	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1800
1801	pGlobals->PciBus.pDevInsR3 = pDevIns;
1802	pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1803	pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1804	pGlobals->PciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->PciBus.devices));
1805
1806	PDMPCIBUSREG PciBusReg;
1807	PPCIBUS pBus = &pGlobals->PciBus;
1808	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
1809	PciBusReg.pfnRegisterR3 = pciRegister;
1810	PciBusReg.pfnIORegionRegisterR3 = pciIORegionRegister;
1811	PciBusReg.pfnSetConfigCallbacksR3 = pciSetConfigCallbacks;
1812	PciBusReg.pfnSetIrqR3 = pciSetIrq;
1813	PciBusReg.pfnSaveExecR3 = pciGenericSaveExec;
1814	PciBusReg.pfnLoadExecR3 = pciGenericLoadExec;
1815	PciBusReg.pfnFakePCIBIOSR3 = pciFakePCIBIOS;
1816	PciBusReg.pszSetIrqRC = fGCEnabled ? "pciSetIrq" : NULL;
1817	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
1818	rc = pDevIns->pDevHlpR3->pfnPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
1819	if (RT_FAILURE(rc))
1820	return PDMDEV_SET_ERROR(pDevIns, rc,
1821	N_("Failed to register ourselves as a PCI Bus"));
1822	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1823	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1824	N_("PCI helper version mismatch; got %#x expected %#x"),
1825	pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION);
1826
1827	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
1828	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
1829
1830	/*
1831	* Fill in PCI configs and add them to the bus.
1832	*/
1833	/* i440FX */
1834	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
1835	PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
1836	PCIDevSetRevisionId(&pBus->PciDev, 0x02);
1837	PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
1838	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
1839	PCIDevSetHeaderType(&pBus->PciDev, 0x00);
1840
1841	pBus->PciDev.pDevIns = pDevIns;
1842	pBus->PciDev.Int.s.fRequestedDevFn= true;
1843	pciRegisterInternal(pBus, 0, &pBus->PciDev, "i440FX");
1844
1845	/* PIIX3 */
1846	PCIDevSetVendorId( &pGlobals->PIIX3State.dev, 0x8086); /* Intel */
1847	PCIDevSetDeviceId( &pGlobals->PIIX3State.dev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
1848	PCIDevSetClassSub( &pGlobals->PIIX3State.dev, 0x01); /* PCI_ISA */
1849	PCIDevSetClassBase( &pGlobals->PIIX3State.dev, 0x06); /* PCI_bridge */
1850	PCIDevSetHeaderType(&pGlobals->PIIX3State.dev, 0x80); /* PCI_multifunction, generic */
1851
1852	pGlobals->PIIX3State.dev.pDevIns = pDevIns;
1853	pGlobals->PIIX3State.dev.Int.s.fRequestedDevFn= true;
1854	pciRegisterInternal(pBus, 8, &pGlobals->PIIX3State.dev, "PIIX3");
1855	piix3_reset(&pGlobals->PIIX3State);
1856
1857	pBus->iDevSearch = 16;
1858
1859	/*
1860	* Register I/O ports and save state.
1861	*/
1862	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
1863	if (RT_FAILURE(rc))
1864	return rc;
1865	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
1866	if (RT_FAILURE(rc))
1867	return rc;
1868	if (fGCEnabled)
1869	{
1870	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
1871	if (RT_FAILURE(rc))
1872	return rc;
1873	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
1874	if (RT_FAILURE(rc))
1875	return rc;
1876	}
1877	if (fR0Enabled)
1878	{
1879	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
1880	if (RT_FAILURE(rc))
1881	return rc;
1882	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
1883	if (RT_FAILURE(rc))
1884	return rc;
1885	}
1886
1887	rc = PDMDevHlpSSMRegister(pDevIns, "pci", iInstance, VBOX_PCI_SAVED_STATE_VERSION, sizeof(*pBus),
1888	NULL, pciSaveExec, NULL, NULL, pciLoadExec, NULL);
1889	if (RT_FAILURE(rc))
1890	return rc;
1891
1892	return VINF_SUCCESS;
1893	}
1894
1895
1896	/**
1897	* The device registration structure.
1898	*/
1899	const PDMDEVREG g_DevicePCI =
1900	{
1901	/* u32Version */
1902	PDM_DEVREG_VERSION,
1903	/* szDeviceName */
1904	"pci",
1905	/* szRCMod */
1906	"VBoxDDGC.gc",
1907	/* szR0Mod */
1908	"VBoxDDR0.r0",
1909	/* pszDescription */
1910	"i440FX PCI bridge and PIIX3 ISA bridge.",
1911	/* fFlags */
1912	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1913	/* fClass */
1914	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
1915	/* cMaxInstances */
1916	1,
1917	/* cbInstance */
1918	sizeof(PCIGLOBALS),
1919	/* pfnConstruct */
1920	pciConstruct,
1921	/* pfnDestruct */
1922	NULL,
1923	/* pfnRelocate */
1924	pciRelocate,
1925	/* pfnIOCtl */
1926	NULL,
1927	/* pfnPowerOn */
1928	NULL,
1929	/* pfnReset */
1930	NULL,
1931	/* pfnSuspend */
1932	NULL,
1933	/* pfnResume */
1934	NULL,
1935	/* pfnAttach */
1936	NULL,
1937	/* pfnDetach */
1938	NULL,
1939	/* pfnQueryInterface */
1940	NULL,
1941	/* pfnInitComplete */
1942	NULL,
1943	/* pfnPowerOff */
1944	NULL,
1945	/* pfnSoftReset */
1946	NULL,
1947	/* u32VersionEnd */
1948	PDM_DEVREG_VERSION
1949
1950	};
1951	#endif /* IN_RING3 */
1952
1953	/**
1954	* Set the IRQ for a PCI device on a secondary bus.
1955	*
1956	* @param pDevIns Device instance of the PCI Bus.
1957	* @param pPciDev The PCI device structure.
1958	* @param iIrq IRQ number to set.
1959	* @param iLevel IRQ level.
1960	*/
1961	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
1962	{
1963	/*
1964	* The PCI-to-PCI bridge specification defines how the interrupt pins
1965	* are routed from the secondary to the primary bus (see chapter 9).
1966	* iIrq gives the interrupt pin the pci device asserted.
1967	* We change iIrq here according to the spec and call the SetIrq function
1968	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
1969	*/
1970	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
1971	int iIrqPinBridge = 0;
1972	uint8_t uDevFnBridge = pPciDev->devfn;
1973
1974	/* Walk the chain until we reach the host bus. */
1975	while (pBus->iBus != 0)
1976	{
1977	uDevFnBridge = pBus->PciDev.devfn;
1978	iIrqPinBridge = ((uDevFnBridge >> 3) + iIrqPinBridge) & 3;
1979	/* Get the parent. */
1980	pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
1981	}
1982
1983	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
1984	pciSetIrqInternal(PCIBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel);
1985	}
1986
1987	#ifdef IN_RING3
1988
1989	static void pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
1990	{
1991	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
1992
1993	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
1994
1995	/* If the current bus is not the target bus search for the bus which contains the device. */
1996	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
1997	{
1998	PPCIDEVICE pBridgeDevice = pciFindBridge(pBus, iBus);
1999	if (pBridgeDevice)
2000	{
2001	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
2002	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
2003	}
2004	}
2005	else
2006	{
2007	/* This is the target bus, pass the write to the device. */
2008	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2009	if (pPciDev)
2010	{
2011	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2012	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
2013	}
2014	}
2015	}
2016
2017	static uint32_t pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
2018	{
2019	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2020	uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
2021
2022	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
2023
2024	/* If the current bus is not the target bus search for the bus which contains the device. */
2025	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2026	{
2027	PPCIDEVICE pBridgeDevice = pciFindBridge(pBus, iBus);
2028	if (pBridgeDevice)
2029	{
2030	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
2031	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
2032	}
2033	}
2034	else
2035	{
2036	/* This is the target bus, pass the read to the device. */
2037	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2038	if (pPciDev)
2039	{
2040	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
2041	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2042	}
2043	}
2044
2045	return u32Value;
2046	}
2047
2048	/**
2049	* Saves a state of a PCI bridge device.
2050	*
2051	* @returns VBox status code.
2052	* @param pDevIns The device instance.
2053	* @param pPciDev Pointer to PCI device.
2054	* @param pSSMHandle The handle to save the state to.
2055	*/
2056	static DECLCALLBACK(int) pcibridgeSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
2057	{
2058	uint32_t i;
2059	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2060
2061	/*
2062	* Iterate all the devices.
2063	*/
2064	for (i = 0; i < RT_ELEMENTS(pThis->devices); i++)
2065	{
2066	PPCIDEVICE pDev = pThis->devices[i];
2067	if (pDev)
2068	{
2069	int rc;
2070	SSMR3PutU32(pSSMHandle, i);
2071	SSMR3PutMem(pSSMHandle, pDev->config, sizeof(pDev->config));
2072
2073	rc = SSMR3PutS32(pSSMHandle, pDev->Int.s.uIrqPinState);
2074	if (RT_FAILURE(rc))
2075	return rc;
2076	}
2077	}
2078	return SSMR3PutU32(pSSMHandle, ~0); /* terminator */
2079	}
2080
2081	/**
2082	* Loads a saved PCI bridge device state.
2083	*
2084	* @returns VBox status code.
2085	* @param pDevIns The device instance.
2086	* @param pSSMHandle The handle to the saved state.
2087	* @param u32Version The data unit version number.
2088	*/
2089	static DECLCALLBACK(int) pcibridgeLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
2090	{
2091	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2092	uint32_t u32;
2093	uint32_t i;
2094	int rc;
2095
2096	/*
2097	* Check the version.
2098	*/
2099	if (u32Version > VBOX_PCI_SAVED_STATE_VERSION)
2100	{
2101	AssertFailed();
2102	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2103	}
2104
2105	/*
2106	* Iterate all the devices.
2107	*/
2108	for (i = 0;; i++)
2109	{
2110	PCIDEVICE DevTmp;
2111	PPCIDEVICE pDev;
2112
2113	/* index / terminator */
2114	rc = SSMR3GetU32(pSSMHandle, &u32);
2115	if (RT_FAILURE(rc))
2116	return rc;
2117	if (u32 == (uint32_t)~0)
2118	break;
2119	if ( u32 >= RT_ELEMENTS(pBus->devices)
2120	\|\| u32 < i)
2121	{
2122	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
2123	return rc;
2124	}
2125
2126	/* skip forward to the device checking that no new devices are present. */
2127	for (; i < u32; i++)
2128	{
2129	if (pBus->devices[i])
2130	{
2131	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pBus->devices[i]->name,
2132	PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i])));
2133	if (SSMR3HandleGetAfter(pSSMHandle) != SSMAFTER_DEBUG_IT)
2134	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2135	}
2136	}
2137
2138	/* get the data */
2139	DevTmp.Int.s.uIrqPinState = 0;
2140	SSMR3GetMem(pSSMHandle, DevTmp.config, sizeof(DevTmp.config));
2141	rc = SSMR3GetS32(pSSMHandle, &DevTmp.Int.s.uIrqPinState);
2142	if (RT_FAILURE(rc))
2143	return rc;
2144
2145	/* check that it's still around. */
2146	pDev = pBus->devices[i];
2147	if (!pDev)
2148	{
2149	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
2150	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
2151	if (SSMR3HandleGetAfter(pSSMHandle) != SSMAFTER_DEBUG_IT)
2152	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2153	continue;
2154	}
2155
2156	/* match the vendor id assuming that this will never be changed. */
2157	if ( DevTmp.config[0] != pDev->config[0]
2158	\|\| DevTmp.config[1] != pDev->config[1])
2159	{
2160	LogRel(("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs\n",
2161	i, pDev->name, DevTmp.config, pDev->config));
2162	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2163	}
2164
2165	/* commit the loaded device config. */
2166	memcpy(pDev->config, DevTmp.config, sizeof(pDev->config));
2167
2168	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
2169	}
2170
2171	return VINF_SUCCESS;
2172	}
2173
2174	/**
2175	* @copydoc FNPDMDEVRESET
2176	*/
2177	static DECLCALLBACK(void) pcibridgeReset(PPDMDEVINS pDevIns)
2178	{
2179	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2180
2181	/* Reset config space to default values. */
2182	pBus->PciDev.config[VBOX_PCI_PRIMARY_BUS] = 0;
2183	pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS] = 0;
2184	pBus->PciDev.config[VBOX_PCI_SUBORDINATE_BUS] = 0;
2185	}
2186
2187	/**
2188	* @copydoc FNPDMDEVRELOCATE
2189	*/
2190	static DECLCALLBACK(void) pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2191	{
2192	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2193	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2194
2195	/* Relocate RC pointers for the attached pci devices. */
2196	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2197	{
2198	if (pBus->devices[i])
2199	pBus->devices[i]->Int.s.pBusRC += offDelta;
2200	}
2201	}
2202
2203	/**
2204	* Registers the device with the default PCI bus.
2205	*
2206	* @returns VBox status code.
2207	* @param pDevIns Device instance of the PCI Bus.
2208	* @param pPciDev The PCI device structure.
2209	* Any PCI enabled device must keep this in it's instance data!
2210	* Fill in the PCI data config before registration, please.
2211	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
2212	* @param iDev The PCI device number. Use a negative value for auto assigning one.
2213	*/
2214	static DECLCALLBACK(int) pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
2215	{
2216	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2217
2218	/*
2219	* Check input.
2220	*/
2221	if ( !pszName
2222	\|\| !pPciDev
2223	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices))
2224	{
2225	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
2226	return VERR_INVALID_PARAMETER;
2227	}
2228
2229	/*
2230	* Register the device.
2231	*/
2232	return pciRegisterInternal(pBus, iDev, pPciDev, pszName);
2233	}
2234
2235	/**
2236	* Construct a PCI bridge device instance for a VM.
2237	*
2238	* @returns VBox status.
2239	* @param pDevIns The device instance data.
2240	* If the registration structure is needed, pDevIns->pDevReg points to it.
2241	* @param iInstance Instance number. Use this to figure out which registers and such to use.
2242	* The device number is also found in pDevIns->iInstance, but since it's
2243	* likely to be freqently used PDM passes it as parameter.
2244	* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
2245	* of the device instance. It's also found in pDevIns->pCfgHandle, but like
2246	* iInstance it's expected to be used a bit in this function.
2247	*/
2248	static DECLCALLBACK(int) pcibridgeConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2249	{
2250	int rc;
2251
2252	/*
2253	* Validate and read configuration.
2254	*/
2255	if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0" "R0Enabled\0"))
2256	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2257
2258	/* check if RC code is enabled. */
2259	bool fGCEnabled;
2260	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
2261	if (RT_FAILURE(rc))
2262	return PDMDEV_SET_ERROR(pDevIns, rc,
2263	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2264
2265	/* check if R0 code is enabled. */
2266	bool fR0Enabled;
2267	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
2268	if (RT_FAILURE(rc))
2269	return PDMDEV_SET_ERROR(pDevIns, rc,
2270	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2271	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2272
2273	/*
2274	* Init data and register the PCI bus.
2275	*/
2276	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2277	pBus->pDevInsR3 = pDevIns;
2278	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2279	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2280	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->devices));
2281
2282	PDMPCIBUSREG PciBusReg;
2283	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2284	PciBusReg.pfnRegisterR3 = pcibridgeRegister;
2285	PciBusReg.pfnIORegionRegisterR3 = pciIORegionRegister;
2286	PciBusReg.pfnSetConfigCallbacksR3 = pciSetConfigCallbacks;
2287	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
2288	PciBusReg.pfnSaveExecR3 = pciGenericSaveExec;
2289	PciBusReg.pfnLoadExecR3 = pciGenericLoadExec;
2290	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2291	PciBusReg.pszSetIrqRC = fGCEnabled ? "pcibridgeSetIrq" : NULL;
2292	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pcibridgeSetIrq" : NULL;
2293	rc = pDevIns->pDevHlpR3->pfnPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2294	if (RT_FAILURE(rc))
2295	return PDMDEV_SET_ERROR(pDevIns, rc,
2296	N_("Failed to register ourselves as a PCI Bus"));
2297	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2298	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2299	N_("PCI helper version mismatch; got %#x expected %#x"),
2300	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2301
2302	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2303	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2304
2305	/*
2306	* Fill in PCI configs and add them to the bus.
2307	*/
2308	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2309	PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2310	PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
2311	PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
2312	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2313	PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
2314	PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2315	PCIDevSetCommand( &pBus->PciDev, 0x00);
2316	PCIDevSetStatus( &pBus->PciDev, 0x20); /* 66MHz Capable. */
2317	PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
2318
2319	/*
2320	* This device does not generate interrupts. Interrupt delivery from
2321	* devices attached to the bus is unaffected.
2322	*/
2323	PCIDevSetInterruptPin (&pBus->PciDev, 0x00);
2324
2325	pBus->PciDev.pDevIns = pDevIns;
2326	pBus->PciDev.Int.s.fPciToPciBridge = true;
2327	pBus->PciDev.Int.s.pfnBridgeConfigRead = pcibridgeConfigRead;
2328	pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeConfigWrite;
2329
2330	/*
2331	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2332	*/
2333	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->PciDev);
2334	if (RT_FAILURE(rc))
2335	return rc;
2336
2337	pBus->iDevSearch = 0;
2338	/*
2339	* The iBus property doesn't really represent the bus number
2340	* because the guest and the BIOS can choose different bus numbers
2341	* for them.
2342	* The bus number is mainly for the setIrq function to indicate
2343	* when the host bus is reached which will have iBus = 0.
2344	* Thathswhy the + 1.
2345	*/
2346	pBus->iBus = iInstance + 1;
2347
2348	/*
2349	* Register SSM handlers. We use the same saved state version as for the host bridge
2350	* to make changes easier.
2351	*/
2352	rc = PDMDevHlpSSMRegister(pDevIns, "pcibridge", iInstance, VBOX_PCI_SAVED_STATE_VERSION, sizeof(*pBus),
2353	NULL, pcibridgeSaveExec, NULL, NULL, pcibridgeLoadExec, NULL);
2354	if (RT_FAILURE(rc))
2355	return rc;
2356
2357	return VINF_SUCCESS;
2358	}
2359
2360	/**
2361	* The device registration structure
2362	* for the PCI-to-PCI bridge.
2363	*/
2364	const PDMDEVREG g_DevicePCIBridge =
2365	{
2366	/* u32Version */
2367	PDM_DEVREG_VERSION,
2368	/* szDeviceName */
2369	"pcibridge",
2370	/* szRCMod */
2371	"VBoxDDGC.gc",
2372	/* szR0Mod */
2373	"VBoxDDR0.r0",
2374	/* pszDescription */
2375	"82801 Mobile PCI to PCI bridge",
2376	/* fFlags */
2377	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2378	/* fClass */
2379	PDM_DEVREG_CLASS_BUS_PCI,
2380	/* cMaxInstances */
2381	~0,
2382	/* cbInstance */
2383	sizeof(PCIBUS),
2384	/* pfnConstruct */
2385	pcibridgeConstruct,
2386	/* pfnDestruct */
2387	NULL,
2388	/* pfnRelocate */
2389	pcibridgeRelocate,
2390	/* pfnIOCtl */
2391	NULL,
2392	/* pfnPowerOn */
2393	NULL,
2394	/* pfnReset */
2395	pcibridgeReset,
2396	/* pfnSuspend */
2397	NULL,
2398	/* pfnResume */
2399	NULL,
2400	/* pfnAttach */
2401	NULL,
2402	/* pfnDetach */
2403	NULL,
2404	/* pfnQueryInterface */
2405	NULL,
2406	/* pfnInitComplete */
2407	NULL,
2408	/* pfnPowerOff */
2409	NULL,
2410	/* pfnSoftReset */
2411	NULL,
2412	/* u32VersionEnd */
2413	PDM_DEVREG_VERSION
2414	};
2415
2416	#endif /* IN_RING3 */
2417	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 15941

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