DevPCI.cpp@ 106054

Last change on this file since 106054 was 104842, checked in by vboxsync, 6 months ago
DevVGA,DevPCI,Main: Increased the max VRAM size to 1GB. Experimental. bugref:10687
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1	/* $Id: DevPCI.cpp 104842 2024-06-05 01:02:34Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*
5	* @remarks New code shall be added to DevPciIch9.cpp as that will become
6	* the common PCI bus code soon. Don't fix code in both DevPCI.cpp
7	* and DevPciIch9.cpp when it's possible to just make the latter
8	* version common. Common code uses the 'devpci' prefix, is
9	* prototyped in DevPciInternal.h, and is defined in DevPciIch9.cpp.
10	*/
11
12	/*
13	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
14	*
15	* This file is part of VirtualBox base platform packages, as
16	* available from https://www.virtualbox.org.
17	*
18	* This program is free software; you can redistribute it and/or
19	* modify it under the terms of the GNU General Public License
20	* as published by the Free Software Foundation, in version 3 of the
21	* License.
22	*
23	* This program is distributed in the hope that it will be useful, but
24	* WITHOUT ANY WARRANTY; without even the implied warranty of
25	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
26	* General Public License for more details.
27	*
28	* You should have received a copy of the GNU General Public License
29	* along with this program; if not, see <https://www.gnu.org/licenses>.
30	*
31	* SPDX-License-Identifier: GPL-3.0-only
32	* --------------------------------------------------------------------
33	*
34	* This code is based on:
35	*
36	* QEMU PCI bus manager
37	*
38	* Copyright (c) 2004 Fabrice Bellard
39	*
40	* Permission is hereby granted, free of charge, to any person obtaining a copy
41	* of this software and associated documentation files (the "Software"), to deal
42	* in the Software without restriction, including without limitation the rights
43	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
44	* copies of the Software, and to permit persons to whom the Software is
45	* furnished to do so, subject to the following conditions:
46	*
47	* The above copyright notice and this permission notice shall be included in
48	* all copies or substantial portions of the Software.
49	*
50	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
51	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
52	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
53	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
54	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
55	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
56	* THE SOFTWARE.
57	*/
58
59
60	/*********************************************************************************************************************************
61	* Header Files *
62	*********************************************************************************************************************************/
63	#define LOG_GROUP LOG_GROUP_DEV_PCI
64	#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
65	#include <VBox/vmm/pdmpcidev.h>
66	#include <VBox/vmm/pdmdev.h>
67	#include <VBox/vmm/mm.h>
68	#include <iprt/asm.h>
69	#include <iprt/assert.h>
70	#include <iprt/string.h>
71
72	#include "PciInline.h"
73	#include "VBoxDD.h"
74	#include "DevPciInternal.h"
75
76
77	/*********************************************************************************************************************************
78	* Defined Constants And Macros *
79	*********************************************************************************************************************************/
80	/** Saved state version of the PCI bus device. */
81	#define VBOX_PCI_SAVED_STATE_VERSION VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES
82	/** Adds I/O region types and sizes for dealing changes in resource regions. */
83	#define VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES 4
84	/** Before region sizes, the first named one.
85	* Looking at the code though, we support even older version. */
86	#define VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES 3
87	/** Notes whether we use the I/O APIC. */
88	#define VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC 2
89
90
91	/*********************************************************************************************************************************
92	* Internal Functions *
93	*********************************************************************************************************************************/
94	RT_C_DECLS_BEGIN
95
96	static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTag);
97
98	#ifdef IN_RING3
99	DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus);
100	#endif
101
102	RT_C_DECLS_END
103
104	#define DEBUG_PCI
105
106	#define PCI_VENDOR_ID 0x00 /* 16 bits */
107	#define PCI_DEVICE_ID 0x02 /* 16 bits */
108	#define PCI_COMMAND 0x04 /* 16 bits */
109	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
110	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
111	#define PCI_CLASS_DEVICE 0x0a /* Device class */
112	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
113	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
114	#define PCI_MIN_GNT 0x3e /* 8 bits */
115	#define PCI_MAX_LAT 0x3f /* 8 bits */
116
117
118	static VBOXSTRICTRC pci_data_write(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, uint32_t addr, uint32_t u32Value, int cb)
119	{
120	LogFunc(("addr=%08x u32Value=%08x cb=%d\n", pGlobals->uConfigReg, u32Value, cb));
121
122	if (!(pGlobals->uConfigReg & (1 << 31)))
123	return VINF_SUCCESS;
124	if ((pGlobals->uConfigReg & 0x3) != 0)
125	return VINF_SUCCESS;
126
127	uint8_t const iBus = (pGlobals->uConfigReg >> 16) & 0xff;
128	uint8_t const iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
129	#ifdef IN_RING3
130	uint32_t const config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
131	#endif
132	RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
133
134	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
135	if (iBus != 0)
136	{
137	if (pGlobals->PciBus.cBridges)
138	{
139	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
140	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
141	if (pBridgeDevice)
142	{
143	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
144	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus,
145	iDevice, config_addr, cb, u32Value);
146	}
147	#else
148	RT_NOREF(pDevIns, addr, u32Value, cb);
149	rcStrict = VINF_IOM_R3_IOPORT_WRITE;
150	#endif
151	}
152	}
153	else
154	{
155	R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[iDevice];
156	if (pPciDev)
157	{
158	#ifdef IN_RING3
159	LogFunc(("%s: addr=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, config_addr, u32Value, cb));
160	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
161	if (pPciDev->Int.s.pfnConfigWrite)
162	rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, config_addr, cb, u32Value);
163	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
164	rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
165	pPciDev, config_addr, cb, u32Value);
166	#else
167	rcStrict = VINF_IOM_R3_IOPORT_WRITE;
168	#endif
169	}
170	}
171	return rcStrict;
172	}
173
174	static VBOXSTRICTRC pci_data_read(PDEVPCIROOT pGlobals, uint32_t addr, int cb, uint32_t *pu32Value)
175	{
176	*pu32Value = UINT32_MAX;
177
178	if (!(pGlobals->uConfigReg & (1 << 31)))
179	return VINF_SUCCESS;
180	if ((pGlobals->uConfigReg & 0x3) != 0)
181	return VINF_SUCCESS;
182	uint8_t const iBus = (pGlobals->uConfigReg >> 16) & 0xff;
183	uint8_t const iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
184	#ifdef IN_RING3
185	uint32_t const config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
186	#endif
187	RT_UNTRUSTED_VALIDATED_FENCE();
188
189	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
190	if (iBus != 0)
191	{
192	if (pGlobals->PciBus.cBridges)
193	{
194	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
195	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(&pGlobals->PciBus, iBus);
196	if (pBridgeDevice)
197	{
198	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
199	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns),
200	iBus, iDevice, config_addr, cb, pu32Value);
201	}
202	#else
203	RT_NOREF(addr, cb);
204	rcStrict = VINF_IOM_R3_IOPORT_READ;
205	#endif
206	}
207	}
208	else
209	{
210	R3PTRTYPE(PDMPCIDEV *) pPciDev = pGlobals->PciBus.apDevices[iDevice];
211	if (pPciDev)
212	{
213	#ifdef IN_RING3
214	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
215	if (pPciDev->Int.s.pfnConfigRead)
216	rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, config_addr, cb, pu32Value);
217	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
218	rcStrict = devpciR3CommonConfigReadWorker(pPciDev, config_addr, cb, pu32Value);
219	LogFunc(("%s: addr=%02x val=%08x cb=%d\n", pPciDev->pszNameR3, config_addr, *pu32Value, cb));
220	#else
221	NOREF(cb);
222	rcStrict = VINF_IOM_R3_IOPORT_READ;
223	#endif
224	}
225	}
226
227	return rcStrict;
228	}
229
230
231
232	/* return the global irq number corresponding to a given device irq
233	pin. We could also use the bus number to have a more precise
234	mapping.
235	This is the implementation note described in the PCI spec chapter 2.2.6 */
236	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
237	{
238	int slot_addend;
239	slot_addend = (uDevFn >> 3) - 1;
240	return (irq_num + slot_addend) & 3;
241	}
242
243	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
244	{
245	return (irq_num + (uDevFn >> 3)) & 7;
246	}
247
248	static inline int get_pci_irq_apic_level(PDEVPCIROOT pGlobals, int irq_num)
249	{
250	return (pGlobals->auPciApicIrqLevels[irq_num] != 0);
251	}
252
253	static void apic_set_irq(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PDEVPCIBUSCC pBusCC,
254	uint8_t uDevFn, PDMPCIDEV *pPciDev, int irq_num1, int iLevel, int iAcpiIrq, uint32_t uTagSrc)
255	{
256	/* This is only allowed to be called with a pointer to the host bus. */
257	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
258	uint16_t const uBusDevFn = PCIBDF_MAKE(pBus->iBus, uDevFn);
259
260	if (iAcpiIrq == -1) {
261	int apic_irq, apic_level;
262	PDEVPCIROOT pGlobals = DEVPCIBUS_2_DEVPCIROOT(pBus);
263	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
264
265	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
266	ASMAtomicIncU32(&pGlobals->auPciApicIrqLevels[irq_num]);
267	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
268	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
269
270	apic_irq = irq_num + 0x10;
271	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
272	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
273	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
274	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, apic_irq, apic_level, uTagSrc);
275
276	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
277	ASMAtomicDecU32(&pGlobals->auPciApicIrqLevels[irq_num]);
278	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
279	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
280	Log3Func(("%s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
281	R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, apic_irq, apic_level, irq_num));
282	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, apic_irq, apic_level, uTagSrc);
283	}
284	} else {
285	Log3Func(("%s: irq_num1=%d level=%d iAcpiIrq=%d\n", R3STRING(pPciDev->pszNameR3), irq_num1, iLevel, iAcpiIrq));
286	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, iAcpiIrq, iLevel, uTagSrc);
287	}
288	}
289
290	DECLINLINE(int) get_pci_irq_level(PDEVPCIROOT pGlobals, int irq_num)
291	{
292	return (pGlobals->u.Piix3.auPciLegacyIrqLevels[irq_num] != 0);
293	}
294
295	/**
296	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
297	*
298	* @param pDevIns The PDM device instance for the PCI bus.
299	* @param pGlobals Device instance of the host PCI bus.
300	* @param pBusCC Context specific data for the PCI bus.
301	* @param uDevFn The device number on the host bus which will raise the IRQ
302	* @param pPciDev The PCI device structure which raised the interrupt.
303	* @param iIrq IRQ number to set.
304	* @param iLevel IRQ level.
305	* @param uTagSrc The IRQ tag and source ID (for tracing).
306	* @remark uDevFn and pPciDev->uDevFn are not the same if the device is behind
307	* a bridge. In that case uDevFn will be the slot of the bridge which
308	* is needed to calculate the PIRQ value.
309	*/
310	static void pciSetIrqInternal(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, PDEVPCIBUSCC pBusCC,
311	uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
312	{
313	PDEVPCIBUS pBus = &pGlobals->PciBus;
314	uint8_t *pbCfg = pDevIns->apPciDevs[1]->abConfig;
315	const bool fIsAcpiDevice = pPciDev->abConfig[2] == 0x13 && pPciDev->abConfig[3] == 0x71;
316	/* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
317	* is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
318	* See the \_SB_.PCI0._PRT method in vbox.dsl.
319	*/
320	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
321	int pic_irq, pic_level;
322
323	/* Check if the state changed. */
324	if (pPciDev->Int.s.uIrqPinState != iLevel)
325	{
326	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
327
328	/* Send interrupt to I/O APIC only. */
329	if (fIsApicEnabled)
330	{
331	if (fIsAcpiDevice)
332	/*
333	* ACPI needs special treatment since SCI is hardwired and
334	* should not be affected by PCI IRQ routing tables at the
335	* same time SCI IRQ is shared in PCI sense hence this
336	* kludge (i.e. we fetch the hardwired value from ACPIs
337	* PCI device configuration space).
338	*/
339	apic_set_irq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, -1, iLevel, pPciDev->abConfig[PCI_INTERRUPT_LINE], uTagSrc);
340	else
341	apic_set_irq(pDevIns, pBus, pBusCC, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
342	return;
343	}
344
345	if (fIsAcpiDevice)
346	{
347	/* As per above treat ACPI in a special way */
348	pic_irq = pPciDev->abConfig[PCI_INTERRUPT_LINE];
349	pGlobals->u.Piix3.iAcpiIrq = pic_irq;
350	pGlobals->u.Piix3.iAcpiIrqLevel = iLevel & PDM_IRQ_LEVEL_HIGH;
351	}
352	else
353	{
354	int irq_num;
355	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
356
357	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
358	ASMAtomicIncU32(&pGlobals->u.Piix3.auPciLegacyIrqLevels[irq_num]);
359	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
360	ASMAtomicDecU32(&pGlobals->u.Piix3.auPciLegacyIrqLevels[irq_num]);
361
362	/* now we change the pic irq level according to the piix irq mappings */
363	pic_irq = pbCfg[0x60 + irq_num];
364	if (pic_irq >= 16)
365	{
366	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
367	{
368	ASMAtomicDecU32(&pGlobals->u.Piix3.auPciLegacyIrqLevels[irq_num]);
369	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
370	}
371
372	return;
373	}
374	}
375
376	/* the pic level is the logical OR of all the PCI irqs mapped to it */
377	pic_level = 0;
378	if (pic_irq == pbCfg[0x60])
379	pic_level \|= get_pci_irq_level(pGlobals, 0); /* PIRQA */
380	if (pic_irq == pbCfg[0x61])
381	pic_level \|= get_pci_irq_level(pGlobals, 1); /* PIRQB */
382	if (pic_irq == pbCfg[0x62])
383	pic_level \|= get_pci_irq_level(pGlobals, 2); /* PIRQC */
384	if (pic_irq == pbCfg[0x63])
385	pic_level \|= get_pci_irq_level(pGlobals, 3); /* PIRQD */
386	if (pic_irq == pGlobals->u.Piix3.iAcpiIrq)
387	pic_level \|= pGlobals->u.Piix3.iAcpiIrqLevel;
388
389	Log3Func(("%s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
390	R3STRING(pPciDev->pszNameR3), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
391	pBusCC->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pDevIns, pic_irq, pic_level, uTagSrc);
392
393	/** @todo optimize pci irq flip-flop some rainy day. */
394	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
395	pciSetIrqInternal(pDevIns, pGlobals, pBusCC, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
396	}
397	}
398
399
400	/**
401	* @interface_method_impl{PDMPCIBUSREGR3,pfnSetIrqR3}
402	*/
403	static DECLCALLBACK(void) pciSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
404	{
405	PDEVPCIROOT pBus = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
406	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
407	LogFlow(("pciSetIrq: %p %u %u %#x\n", pPciDev, iIrq, iLevel, uTagSrc));
408	pciSetIrqInternal(pDevIns, pBus, pBusCC, pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
409	}
410
411	#ifdef IN_RING3
412
413	/**
414	* Finds a bridge on the bus which contains the destination bus.
415	*
416	* @return Pointer to the device instance data of the bus or
417	* NULL if no bridge was found.
418	* @param pBus Pointer to the bus to search on.
419	* @param iBus Destination bus number.
420	*/
421	DECLINLINE(PPDMPCIDEV) pciR3FindBridge(PDEVPCIBUS pBus, uint8_t iBus)
422	{
423	/* Search for a fitting bridge. */
424	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
425	{
426	/*
427	* Examine secondary and subordinate bus number.
428	* If the target bus is in the range we pass the request on to the bridge.
429	*/
430	PPDMPCIDEV pBridgeTemp = pBus->papBridgesR3[iBridge];
431	AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
432	("Device is not a PCI bridge but on the list of PCI bridges\n"));
433
434	if ( iBus >= pBridgeTemp->abConfig[VBOX_PCI_SECONDARY_BUS]
435	&& iBus <= pBridgeTemp->abConfig[VBOX_PCI_SUBORDINATE_BUS])
436	return pBridgeTemp;
437	}
438
439	/* Nothing found. */
440	return NULL;
441	}
442
443	static void pciR3Piix3Reset(PPDMPCIDEV pPiix3PciDev)
444	{
445	uint8_t *pci_conf = pPiix3PciDev->abConfig;
446
447	pci_conf[0x04] = 0x07; /* master, memory and I/O */
448	pci_conf[0x05] = 0x00;
449	pci_conf[0x06] = 0x00;
450	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
451	pci_conf[0x4c] = 0x4d;
452	pci_conf[0x4e] = 0x03;
453	pci_conf[0x4f] = 0x00;
454	pci_conf[0x60] = 0x80;
455	pci_conf[0x69] = 0x02;
456	pci_conf[0x70] = 0x80;
457	pci_conf[0x76] = 0x0c;
458	pci_conf[0x77] = 0x0c;
459	pci_conf[0x78] = 0x02;
460	pci_conf[0x79] = 0x00;
461	pci_conf[0x80] = 0x00;
462	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
463	pci_conf[0xa0] = 0x08;
464	pci_conf[0xa2] = 0x00;
465	pci_conf[0xa3] = 0x00;
466	pci_conf[0xa4] = 0x00;
467	pci_conf[0xa5] = 0x00;
468	pci_conf[0xa6] = 0x00;
469	pci_conf[0xa7] = 0x00;
470	pci_conf[0xa8] = 0x0f;
471	pci_conf[0xaa] = 0x00;
472	pci_conf[0xab] = 0x00;
473	pci_conf[0xac] = 0x00;
474	pci_conf[0xae] = 0x00;
475	}
476
477	/* host irqs corresponding to PCI irqs A-D */
478	static const uint8_t pci_irqs[4] = { 11, 10, 9, 11 }; /* bird: added const */
479
480	static void pci_bios_init_device(PPDMDEVINS pDevIns, PDEVPCIROOT pGlobals, PDEVPCIBUS pBus,
481	PPDMPCIDEV pPciDev, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
482	{
483	uint32_t uPciBiosSpecialVRAM = 0xe0000000;
484	uint32_t *paddr;
485	int pin, pic_irq;
486	uint16_t devclass, vendor_id, device_id;
487
488	devclass = devpciR3GetWord(pPciDev, PCI_CLASS_DEVICE);
489	vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
490	device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
491
492	/* Check if device is present. */
493	if (vendor_id != 0xffff)
494	{
495	switch (devclass)
496	{
497	case 0x0101:
498	if ( (vendor_id == 0x8086)
499	&& (device_id == 0x7010 \|\| device_id == 0x7111 \|\| device_id == 0x269e))
500	{
501	/* PIIX3, PIIX4 or ICH6 IDE */
502	devpciR3SetWord(pDevIns, pPciDev, 0x40, 0x8011); /* enable IDE0 + fast timing */
503	devpciR3SetWord(pDevIns, pPciDev, 0x42, 0x8011); /* enable IDE1 + fast timing */
504	goto default_map;
505	}
506	else
507	{
508	/* IDE: we map it as in ISA mode */
509	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x1f0);
510	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 1, 0x3f4);
511	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 2, 0x170);
512	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 3, 0x374);
513	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
514	devpciR3GetWord(pPciDev, PCI_COMMAND)
515	\| PCI_COMMAND_IOACCESS);
516	}
517	break;
518	case 0x0800:
519	/* PIC */
520	vendor_id = devpciR3GetWord(pPciDev, PCI_VENDOR_ID);
521	device_id = devpciR3GetWord(pPciDev, PCI_DEVICE_ID);
522	if (vendor_id == 0x1014)
523	{
524	/* IBM */
525	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
526	{
527	/* MPIC & MPIC2 */
528	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x80800000 + 0x00040000);
529	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
530	devpciR3GetWord(pPciDev, PCI_COMMAND)
531	\| PCI_COMMAND_MEMACCESS);
532	}
533	}
534	break;
535	case 0xff00:
536	if ( (vendor_id == 0x0106b)
537	&& (device_id == 0x0017 \|\| device_id == 0x0022))
538	{
539	/* macio bridge */
540	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, 0, 0x80800000);
541	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
542	devpciR3GetWord(pPciDev, PCI_COMMAND)
543	\| PCI_COMMAND_MEMACCESS);
544	}
545	break;
546	case 0x0604:
547	{
548	/* Init PCI-to-PCI bridge. */
549	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_PRIMARY_BUS, pBus->iBus);
550
551	AssertMsg(pGlobals->uPciBiosBus < 255, ("Too many bridges on the bus\n"));
552	pGlobals->uPciBiosBus++;
553	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SECONDARY_BUS, pGlobals->uPciBiosBus);
554	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
555
556	/* Add position of this bridge into the array. */
557	paBridgePositions[cBridgeDepth+1] = (pPciDev->uDevFn >> 3);
558
559	/*
560	* The I/O range for the bridge must be aligned to a 4KB boundary.
561	* This does not change anything really as the access to the device is not going
562	* through the bridge but we want to be compliant to the spec.
563	*/
564	if ((pGlobals->uPciBiosIo % _4K) != 0)
565	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
566	LogFunc(("Aligned I/O start address. New address %#x\n", pGlobals->uPciBiosIo));
567	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_IO_BASE, (pGlobals->uPciBiosIo >> 8) & 0xf0);
568
569	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
570	if ((pGlobals->uPciBiosMmio % _1M) != 0)
571	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
572	LogFunc(("Aligned MMIO start address. New address %#x\n", pGlobals->uPciBiosMmio));
573	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_MEMORY_BASE, (pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xffff0));
574
575	/* Save values to compare later to. */
576	uint32_t u32IoAddressBase = pGlobals->uPciBiosIo;
577	uint32_t u32MMIOAddressBase = pGlobals->uPciBiosMmio;
578
579	/* Init devices behind the bridge and possibly other bridges as well. */
580	PDEVPCIBUS pChildBus = PDMINS_2_DATA(pPciDev->Int.s.CTX_SUFF(pDevIns), PDEVPCIBUS);
581	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pChildBus->apDevices); uDevFn++)
582	{
583	PPDMPCIDEV pChildPciDev = pChildBus->apDevices[uDevFn];
584	if (pChildPciDev)
585	pci_bios_init_device(pDevIns, pGlobals, pChildBus, pChildPciDev, cBridgeDepth + 1, paBridgePositions);
586	}
587
588	/* The number of bridges behind the this one is now available. */
589	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uPciBiosBus);
590
591	/*
592	* Set I/O limit register. If there is no device with I/O space behind the bridge
593	* we set a lower value than in the base register.
594	* The result with a real bridge is that no I/O transactions are passed to the secondary
595	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
596	*/
597	if ((u32IoAddressBase != pGlobals->uPciBiosIo) && ((pGlobals->uPciBiosIo % _4K) != 0))
598	{
599	/* The upper boundary must be one byte less than a 4KB boundary. */
600	pGlobals->uPciBiosIo = RT_ALIGN_32(pGlobals->uPciBiosIo, _4K);
601	}
602	devpciR3SetByte(pDevIns, pPciDev, VBOX_PCI_IO_LIMIT, ((pGlobals->uPciBiosIo >> 8) & 0xf0) - 1);
603
604	/* Same with the MMIO limit register but with 1MB boundary here. */
605	if ((u32MMIOAddressBase != pGlobals->uPciBiosMmio) && ((pGlobals->uPciBiosMmio % _1M) != 0))
606	{
607	/* The upper boundary must be one byte less than a 1MB boundary. */
608	pGlobals->uPciBiosMmio = RT_ALIGN_32(pGlobals->uPciBiosMmio, _1M);
609	}
610	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->uPciBiosMmio >> 16) & UINT32_C(0xfff0)) - 1);
611
612	/*
613	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
614	* which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
615	* the base register than in the limit register.
616	*/
617	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
618	devpciR3SetWord(pDevIns, pPciDev, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
619	devpciR3SetDWord(pDevIns, pPciDev, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
620	devpciR3SetDWord(pDevIns, pPciDev, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
621	break;
622	}
623	default:
624	default_map:
625	{
626	/* default memory mappings */
627	bool fActiveMemRegion = false;
628	bool fActiveIORegion = false;
629	/*
630	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
631	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
632	*/
633	for (unsigned i = 0; i < (PCI_NUM_REGIONS-1); i++)
634	{
635	uint32_t u32Size;
636	uint8_t u8ResourceType;
637	uint32_t u32Address = 0x10 + i * 4;
638
639	/* Calculate size. */
640	u8ResourceType = devpciR3GetByte(pPciDev, u32Address);
641	devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0xffffffff));
642	u32Size = devpciR3GetDWord(pPciDev, u32Address);
643	bool fIsPio = ((u8ResourceType & PCI_COMMAND_IOACCESS) == PCI_COMMAND_IOACCESS);
644	/* Clear resource information depending on resource type. */
645	if (fIsPio) /* I/O */
646	u32Size &= ~(0x01);
647	else /* MMIO */
648	u32Size &= ~(0x0f);
649
650	/*
651	* Invert all bits and add 1 to get size of the region.
652	* (From PCI implementation note)
653	*/
654	if (fIsPio && (u32Size & UINT32_C(0xffff0000)) == 0)
655	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
656	else
657	u32Size = (~u32Size) + 1;
658
659	Log2Func(("Size of region %u for device %d on bus %d is %u\n", i, pPciDev->uDevFn, pBus->iBus, u32Size));
660
661	if (u32Size)
662	{
663	if (fIsPio)
664	paddr = &pGlobals->uPciBiosIo;
665	else
666	{
667	paddr = &pGlobals->uPciBiosMmio;
668	if (devclass == 0x0300)
669	{
670	/*
671	* Because legacy VGA I/O ports are implicitly decoded
672	* by a VGA class device without needing a BAR, we must
673	* enable I/O decoding for such devices.
674	*/
675	fActiveIORegion = true;
676
677	if (vendor_id == 0x80ee \|\| vendor_id == 0x15ad)
678	{
679	bool fPrefetch = (u8ResourceType & ((uint8_t)(PCI_ADDRESS_SPACE_MEM_PREFETCH \| PCI_ADDRESS_SPACE_IO)))
680	== PCI_ADDRESS_SPACE_MEM_PREFETCH;
681	/* VGA: map frame buffer to default Bochs VBE address. Only
682	* needed for legacy guest drivers. */
683	if (fPrefetch)
684	{
685	paddr = &uPciBiosSpecialVRAM;
686
687	/* Hack alert! Workaround for VRAM sizes higher than 256MB (absolute max is 1GB). */
688	if ( u32Size > 0x10000000 /* 256MB (what we can stuff at 0xe0000000) */
689	&& uPciBiosSpecialVRAM == 0xe0000000)
690	uPciBiosSpecialVRAM = u32Size > 0x20000000 /512MB/ ? 0x80000000 : 0xc0000000;
691	}
692	}
693	}
694	}
695	uint32_t uNew = *paddr;
696	uNew = (uNew + u32Size - 1) & ~(u32Size - 1);
697	if (fIsPio)
698	uNew &= UINT32_C(0xffff);
699	/* Unconditionally exclude I/O-APIC/HPET/ROM. Pessimistic, but better than causing a mess. */
700	if ( !uNew
701	\|\| uNew + u32Size - 1 >= UINT32_C(0xfec00000))
702	{
703	LogRel(("PCI: no space left for BAR%u (type=%#x size=%#RX32) of device %u/%u/%u (vendor=%#06x device=%#06x) - uNew=%#RX32 (*paddr=%#RX32)\n",
704	i, u8ResourceType, u32Size, pBus->iBus, pPciDev->uDevFn >> 3, pPciDev->uDevFn & 7,
705	vendor_id, device_id, uNew, paddr)); /* @todo make this a VM start failure later. */
706	/* Undo the mapping mess caused by the size probing. */
707	devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0));
708	}
709	else
710	{
711	LogFunc(("Start address of %s region %u is %#x\n", (fIsPio ? "I/O" : "MMIO"), i, uNew));
712	devpciR3BiosInitSetRegionAddress(pDevIns, pBus, pPciDev, i, uNew);
713	if (fIsPio)
714	fActiveIORegion = true;
715	else
716	fActiveMemRegion = true;
717	*paddr = uNew + u32Size;
718	Log2Func(("New address is %#x\n", *paddr));
719	}
720	}
721	}
722
723	/* Update the command word appropriately. */
724	devpciR3SetWord(pDevIns, pPciDev, PCI_COMMAND,
725	devpciR3GetWord(pPciDev, PCI_COMMAND)
726	\| (fActiveMemRegion ? PCI_COMMAND_MEMACCESS : 0)
727	\| (fActiveIORegion ? PCI_COMMAND_IOACCESS : 0));
728
729	break;
730	}
731	}
732
733	/* map the interrupt */
734	pin = devpciR3GetByte(pPciDev, PCI_INTERRUPT_PIN);
735	if (pin != 0)
736	{
737	uint8_t uBridgeDevFn = pPciDev->uDevFn;
738	pin--;
739
740	/* We need to go up to the host bus to see which irq this device will assert there. */
741	while (cBridgeDepth != 0)
742	{
743	/* Get the pin the device would assert on the bridge. */
744	pin = ((uBridgeDevFn >> 3) + pin) & 3;
745	uBridgeDevFn = paBridgePositions[cBridgeDepth];
746	cBridgeDepth--;
747	}
748
749	pin = pci_slot_get_pirq(pPciDev->uDevFn, pin);
750	pic_irq = pci_irqs[pin];
751	devpciR3SetByte(pDevIns, pPciDev, PCI_INTERRUPT_LINE, pic_irq);
752	}
753	}
754	}
755
756	/**
757	* Worker for Fake PCI BIOS config, triggered by magic port access by BIOS.
758	*
759	* @returns VBox status code.
760	*
761	* @param pDevIns i440FX device instance.
762	*/
763	static int pciR3FakePCIBIOS(PPDMDEVINS pDevIns)
764	{
765	uint8_t elcr[2] = {0, 0};
766	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
767
768	LogRel(("PCI: Setting up resources and interrupts\n"));
769
770	/*
771	* Set the start addresses.
772	*/
773	pGlobals->uPciBiosBus = 0;
774	pGlobals->uPciBiosIo = 0xd000;
775	pGlobals->uPciBiosMmio = UINT32_C(0xf0000000);
776
777	/*
778	* Activate IRQ mappings.
779	*/
780	PPDMPCIDEV pPIIX3 = pDevIns->apPciDevs[1];
781	for (unsigned i = 0; i < 4; i++)
782	{
783	uint8_t irq = pci_irqs[i];
784	/* Set to trigger level. */
785	elcr[irq >> 3] \|= (1 << (irq & 7));
786	/* Activate irq remapping in PIIX3. */
787	devpciR3SetByte(pDevIns, pPIIX3, 0x60 + i, irq);
788	}
789
790	/* Tell to the PIC. */
791	/** @todo r=aeichner We should really move this to the BIOS code and get rid of this fake PCI BIOS thing,
792	* DevPciIch9.cpp lacks this code and has a todo for this.
793	*/
794	VBOXSTRICTRC rcStrict = pDevIns->pHlpR3->pfnIoPortWrite(pDevIns, 0x4d0, elcr[0], sizeof(uint8_t));
795	if (rcStrict == VINF_SUCCESS)
796	rcStrict = pDevIns->pHlpR3->pfnIoPortWrite(pDevIns, 0x4d1, elcr[1], sizeof(uint8_t));
797	if (rcStrict != VINF_SUCCESS)
798	{
799	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
800	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
801	}
802
803	/*
804	* Init the devices.
805	*/
806	PDEVPCIBUS pBus = &pGlobals->PciBus;
807	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
808	{
809	PPDMPCIDEV pPciDev = pBus->apDevices[uDevFn];
810	if (pPciDev)
811	{
812	Log2(("PCI: Initializing device %d (%#x)\n", uDevFn, 0x80000000 \| (uDevFn << 8)));
813	uint8_t aBridgePositions[256];
814	RT_ZERO(aBridgePositions);
815	pci_bios_init_device(pDevIns, pGlobals, pBus, pPciDev, 0, aBridgePositions);
816	}
817	}
818
819	return VINF_SUCCESS;
820	}
821
822	#endif /* IN_RING3 */
823
824
825	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
826
827	/**
828	* @callback_method_impl{FNIOMIOPORTNEWOUT, PCI address}
829	*/
830	static DECLCALLBACK(VBOXSTRICTRC)
831	pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
832	{
833	LogFunc(("offPort=%#x u32=%#x cb=%d\n", offPort, u32, cb));
834	Assert(offPort == 0); RT_NOREF2(offPort, pvUser);
835	if (cb == 4)
836	{
837	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
838	PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
839	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
840	PCI_UNLOCK(pDevIns);
841	}
842	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
843	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
844	return VINF_SUCCESS;
845	}
846
847
848	/**
849	* @callback_method_impl{FNIOMIOPORTNEWIN, PCI address}
850	*/
851	static DECLCALLBACK(VBOXSTRICTRC)
852	pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
853	{
854	Assert(offPort == 0); RT_NOREF2(offPort, pvUser);
855	if (cb == 4)
856	{
857	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
858	PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_READ);
859	*pu32 = pThis->uConfigReg;
860	PCI_UNLOCK(pDevIns);
861	LogFunc(("offPort=%#x cb=%d -> %#x\n", offPort, cb, *pu32));
862	return VINF_SUCCESS;
863	}
864	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
865	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
866	LogFunc(("offPort=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", offPort, cb));
867	return VERR_IOM_IOPORT_UNUSED;
868	}
869
870
871	/**
872	* @callback_method_impl{FNIOMIOPORTNEWOUT, PCI data}
873	*/
874	static DECLCALLBACK(VBOXSTRICTRC)
875	pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
876	{
877	LogFunc(("offPort=%#x u32=%#x cb=%d\n", offPort, u32, cb));
878	Assert(offPort < 4); NOREF(pvUser);
879	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
880	if (!(offPort % cb))
881	{
882	PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
883	rcStrict = pci_data_write(pDevIns, PDMINS_2_DATA(pDevIns, PDEVPCIROOT), offPort, u32, cb);
884	PCI_UNLOCK(pDevIns);
885	}
886	else
887	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", offPort, u32, cb));
888	return rcStrict;
889	}
890
891
892	/**
893	* @callback_method_impl{FNIOMIOPORTNEWIN, PCI data}
894	*/
895	static DECLCALLBACK(VBOXSTRICTRC)
896	pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
897	{
898	Assert(offPort < 4); NOREF(pvUser);
899	if (!(offPort % cb))
900	{
901	PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_READ);
902	VBOXSTRICTRC rcStrict = pci_data_read(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), offPort, cb, pu32);
903	PCI_UNLOCK(pDevIns);
904	LogFunc(("offPort=%#x cb=%#x -> %#x (%Rrc)\n", offPort, cb, *pu32, VBOXSTRICTRC_VAL(rcStrict)));
905	return rcStrict;
906	}
907	AssertMsgFailed(("Read from port %#x cb=%d\n", offPort, cb));
908	return VERR_IOM_IOPORT_UNUSED;
909	}
910
911	#ifdef IN_RING3
912
913	/**
914	* @callback_method_impl{FNIOMIOPORTNEWOUT, PCI data}
915	*/
916	static DECLCALLBACK(VBOXSTRICTRC)
917	pciR3IOPortMagicPCIWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
918	{
919	Assert(offPort == 0); RT_NOREF2(pvUser, offPort);
920	LogFunc(("offPort=%#x u32=%#x cb=%d\n", offPort, u32, cb));
921	if (cb == 4)
922	{
923	if (u32 == UINT32_C(19200509)) // Richard Adams - Note! In decimal rather hex.
924	{
925	int rc = pciR3FakePCIBIOS(pDevIns);
926	AssertRC(rc);
927	}
928	}
929
930	return VINF_SUCCESS;
931	}
932
933	/**
934	* @callback_method_impl{FNIOMIOPORTNEWIN, PCI data}
935	*/
936	static DECLCALLBACK(VBOXSTRICTRC)
937	pciR3IOPortMagicPCIRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
938	{
939	Assert(offPort == 0); RT_NOREF5(pDevIns, pvUser, offPort, pu32, cb);
940	LogFunc(("offPort=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", offPort, cb));
941	return VERR_IOM_IOPORT_UNUSED;
942	}
943
944
945	/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
946
947	/**
948	* Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
949	*
950	* @returns VBox status code.
951	* @param pHlp The device helpers.
952	* @param pBus The bus to save.
953	* @param pSSM The saved state handle.
954	*/
955	static int pciR3CommonSaveExec(PCPDMDEVHLPR3 pHlp, PDEVPCIBUS pBus, PSSMHANDLE pSSM)
956	{
957	/*
958	* Iterate thru all the devices.
959	*/
960	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
961	{
962	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
963	if (pDev)
964	{
965	pHlp->pfnSSMPutU32(pSSM, uDevFn);
966	pHlp->pfnSSMPutMem(pSSM, pDev->abConfig, 256); /* Only save 256 bytes here! */
967
968	pHlp->pfnSSMPutS32(pSSM, pDev->Int.s.uIrqPinState);
969
970	/* Save the type an size of all the regions. */
971	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
972	{
973	pHlp->pfnSSMPutU8(pSSM, pDev->Int.s.aIORegions[iRegion].type);
974	pHlp->pfnSSMPutU64(pSSM, pDev->Int.s.aIORegions[iRegion].size);
975	}
976	}
977	}
978	return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); /* terminator */
979	}
980
981
982	/**
983	* @callback_method_impl{FNSSMDEVSAVEEXEC}
984	*/
985	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
986	{
987	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
988	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
989
990	/*
991	* Bus state data.
992	*/
993	pHlp->pfnSSMPutU32(pSSM, pThis->uConfigReg);
994	pHlp->pfnSSMPutBool(pSSM, pThis->fUseIoApic);
995
996	/*
997	* Save IRQ states.
998	*/
999	for (unsigned i = 0; i < RT_ELEMENTS(pThis->u.Piix3.auPciLegacyIrqLevels); i++)
1000	pHlp->pfnSSMPutU32(pSSM, pThis->u.Piix3.auPciLegacyIrqLevels[i]);
1001	for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
1002	pHlp->pfnSSMPutU32(pSSM, pThis->auPciApicIrqLevels[i]);
1003
1004	pHlp->pfnSSMPutU32(pSSM, pThis->u.Piix3.iAcpiIrqLevel);
1005	pHlp->pfnSSMPutS32(pSSM, pThis->u.Piix3.iAcpiIrq);
1006
1007	pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); /* separator */
1008
1009	/*
1010	* Join paths with pcibridgeR3SaveExec.
1011	*/
1012	return pciR3CommonSaveExec(pHlp, &pThis->PciBus, pSSM);
1013	}
1014
1015
1016	/**
1017	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
1018	*
1019	* @returns VBox status code.
1020	* @param pDevIns The device instance.
1021	* @param pBus The bus which data is being loaded.
1022	* @param pSSM The saved state handle.
1023	* @param uVersion The data version.
1024	* @param uPass The pass.
1025	*/
1026	static int pciR3CommonLoadExec(PPDMDEVINS pDevIns, PDEVPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1027	{
1028	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1029	uint32_t u32;
1030	int rc;
1031
1032	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1033
1034	/*
1035	* Iterate thru all the devices and write 0 to the COMMAND register so
1036	* that all the memory is unmapped before we start restoring the saved
1037	* mapping locations.
1038	*
1039	* The register value is restored afterwards so we can do proper
1040	* LogRels in devpciR3CommonRestoreConfig.
1041	*/
1042	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1043	{
1044	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1045	if (pDev)
1046	{
1047	uint16_t u16 = PCIDevGetCommand(pDev);
1048	devpciR3SetCfg(pDevIns, pDev, VBOX_PCI_COMMAND, 0 /u32Value/, 2 /cb/);
1049	PCIDevSetCommand(pDev, u16);
1050	Assert(PCIDevGetCommand(pDev) == u16);
1051	}
1052	}
1053
1054	/*
1055	* Iterate all the devices.
1056	*/
1057	for (uint32_t uDevFn = 0;; uDevFn++)
1058	{
1059	/* index / terminator */
1060	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
1061	if (RT_FAILURE(rc))
1062	return rc;
1063	if (u32 == UINT32_MAX)
1064	break;
1065	if ( u32 >= RT_ELEMENTS(pBus->apDevices)
1066	\|\| u32 < uDevFn)
1067	{
1068	AssertMsgFailed(("u32=%#x uDevFn=%#x\n", u32, uDevFn));
1069	return rc;
1070	}
1071
1072	/* skip forward to the device checking that no new devices are present. */
1073	for (; uDevFn < u32; uDevFn++)
1074	{
1075	if (pBus->apDevices[uDevFn])
1076	{
1077	LogRel(("PCI: New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", uDevFn, pBus->apDevices[uDevFn]->pszNameR3,
1078	PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn])));
1079	if (pHlp->pfnSSMHandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1080	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1081	uDevFn, pBus->apDevices[uDevFn]->pszNameR3, PCIDevGetVendorId(pBus->apDevices[uDevFn]), PCIDevGetDeviceId(pBus->apDevices[uDevFn]));
1082	}
1083	}
1084
1085	/* get the data */
1086	union
1087	{
1088	PDMPCIDEV DevTmp;
1089	uint8_t abDevTmpPadding[RT_UOFFSETOF(PDMPCIDEV, abMsixState)];
1090	} u;
1091	RT_ZERO(u.DevTmp);
1092	u.DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1093	pHlp->pfnSSMGetMem(pSSM, u.DevTmp.abConfig, 256);
1094	if (uVersion < VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1095	{
1096	int32_t i32Temp;
1097	/* Irq value not needed anymore. */
1098	rc = pHlp->pfnSSMGetS32(pSSM, &i32Temp);
1099	if (RT_FAILURE(rc))
1100	return rc;
1101	}
1102	else
1103	{
1104	rc = pHlp->pfnSSMGetS32(pSSM, &u.DevTmp.Int.s.uIrqPinState);
1105	if (RT_FAILURE(rc))
1106	return rc;
1107	}
1108
1109	/* Load the region types and sizes. */
1110	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES)
1111	{
1112	for (uint32_t iRegion = 0; iRegion < VBOX_PCI_NUM_REGIONS; iRegion++)
1113	{
1114	pHlp->pfnSSMGetU8(pSSM, &u.DevTmp.Int.s.aIORegions[iRegion].type);
1115	rc = pHlp->pfnSSMGetU64(pSSM, &u.DevTmp.Int.s.aIORegions[iRegion].size);
1116	AssertLogRelRCReturn(rc, rc);
1117	}
1118	}
1119
1120	/* check that it's still around. */
1121	PPDMPCIDEV pDev = pBus->apDevices[uDevFn];
1122	if (!pDev)
1123	{
1124	LogRel(("PCI: Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", uDevFn,
1125	PCIDevGetVendorId(&u.DevTmp), PCIDevGetDeviceId(&u.DevTmp)));
1126	if (pHlp->pfnSSMHandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1127	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1128	uDevFn, PCIDevGetVendorId(&u.DevTmp), PCIDevGetDeviceId(&u.DevTmp));
1129	continue;
1130	}
1131
1132	/* match the vendor id assuming that this will never be changed. */
1133	if ( u.DevTmp.abConfig[0] != pDev->abConfig[0]
1134	\|\| u.DevTmp.abConfig[1] != pDev->abConfig[1])
1135	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1136	N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1137	uDevFn, pDev->pszNameR3, u.DevTmp.abConfig, pDev->abConfig);
1138
1139	/* commit the loaded device config. */
1140	rc = devpciR3CommonRestoreRegions(pHlp, pSSM, pDev, u.DevTmp.Int.s.aIORegions,
1141	uVersion >= VBOX_PCI_SAVED_STATE_VERSION_REGION_SIZES);
1142	if (RT_FAILURE(rc))
1143	break;
1144	devpciR3CommonRestoreConfig(pDevIns, pDev, &u.DevTmp.abConfig[0]);
1145
1146	pDev->Int.s.uIrqPinState = u.DevTmp.Int.s.uIrqPinState;
1147	}
1148
1149	return VINF_SUCCESS;
1150	}
1151
1152
1153	/**
1154	* @callback_method_impl{FNSSMDEVLOADEXEC}
1155	*/
1156	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1157	{
1158	PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1159	PDEVPCIBUS pBus = &pThis->PciBus;
1160	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1161	uint32_t u32;
1162	int rc;
1163
1164	/*
1165	* Check the version.
1166	*/
1167	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1168	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1169	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1170
1171	/*
1172	* Bus state data.
1173	*/
1174	pHlp->pfnSSMGetU32(pSSM, &pThis->uConfigReg);
1175	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_USE_IO_APIC)
1176	pHlp->pfnSSMGetBool(pSSM, &pThis->fUseIoApic);
1177
1178	/* Load IRQ states. */
1179	if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
1180	{
1181	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->u.Piix3.auPciLegacyIrqLevels); i++)
1182	pHlp->pfnSSMGetU32V(pSSM, &pThis->u.Piix3.auPciLegacyIrqLevels[i]);
1183	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
1184	pHlp->pfnSSMGetU32V(pSSM, &pThis->auPciApicIrqLevels[i]);
1185
1186	pHlp->pfnSSMGetU32(pSSM, &pThis->u.Piix3.iAcpiIrqLevel);
1187	pHlp->pfnSSMGetS32(pSSM, &pThis->u.Piix3.iAcpiIrq);
1188	}
1189
1190	/* separator */
1191	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
1192	if (RT_FAILURE(rc))
1193	return rc;
1194	if (u32 != UINT32_MAX)
1195	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1196
1197	/*
1198	* The devices.
1199	*/
1200	return pciR3CommonLoadExec(pDevIns, pBus, pSSM, uVersion, uPass);
1201	}
1202
1203
1204	/* -=-=-=-=-=- PCI Bus Interface Methods (PDMPCIBUSREG) -=-=-=-=-=- */
1205
1206
1207	/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
1208
1209	/**
1210	* @callback_method_impl{FNDBGFHANDLERDEV}
1211	*/
1212	static DECLCALLBACK(void) pciR3IrqRouteInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1213	{
1214	PPDMPCIDEV pPIIX3 = pDevIns->apPciDevs[1];
1215	NOREF(pszArgs);
1216
1217	uint16_t router = pPIIX3->uDevFn;
1218	pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
1219	router >> 8, (router >> 3) & 0x1f, router & 0x7);
1220
1221	for (int i = 0; i < 4; ++i)
1222	{
1223	uint8_t irq_map = devpciR3GetByte(pPIIX3, 0x60 + i);
1224	if (irq_map & 0x80)
1225	pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
1226	else
1227	pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
1228	}
1229	}
1230
1231	/**
1232	* @callback_method_impl{FNDBGFHANDLERDEV, 'pirq'}
1233	*/
1234	static DECLCALLBACK(void) devpciR3InfoPIRQ(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1235	{
1236	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1237	NOREF(pszArgs);
1238
1239	pHlp->pfnPrintf(pHlp, "PCI IRQ levels:\n");
1240	for (int i = 0; i < DEVPCI_LEGACY_IRQ_PINS; ++i)
1241	pHlp->pfnPrintf(pHlp, " IRQ%c: %u\n", 'A' + i, pGlobals->u.Piix3.auPciLegacyIrqLevels[i]);
1242	}
1243
1244
1245	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1246
1247	/**
1248	* @interface_method_impl{PDMDEVREG,pfnReset}
1249	*/
1250	static DECLCALLBACK(void) pciR3Reset(PPDMDEVINS pDevIns)
1251	{
1252	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1253	PDEVPCIBUS pBus = &pGlobals->PciBus;
1254
1255	/* PCI-specific reset for each device. */
1256	for (uint32_t uDevFn = 0; uDevFn < RT_ELEMENTS(pBus->apDevices); uDevFn++)
1257	{
1258	if (pBus->apDevices[uDevFn])
1259	devpciR3ResetDevice(pDevIns, pBus->apDevices[uDevFn]);
1260	}
1261
1262	pciR3Piix3Reset(pDevIns->apPciDevs[1]);
1263	}
1264
1265
1266	/**
1267	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1268	*/
1269	static DECLCALLBACK(int) pciR3Destruct(PPDMDEVINS pDevIns)
1270	{
1271	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1272	if (pGlobals->PciBus.papBridgesR3)
1273	{
1274	PDMDevHlpMMHeapFree(pDevIns, pGlobals->PciBus.papBridgesR3);
1275	pGlobals->PciBus.papBridgesR3 = NULL;
1276	}
1277	return VINF_SUCCESS;
1278	}
1279
1280
1281	/**
1282	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1283	*/
1284	static DECLCALLBACK(int) pciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1285	{
1286	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1287	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1288	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1289	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1290	RT_NOREF(iInstance);
1291	Assert(iInstance == 0);
1292
1293	/*
1294	* Validate and read configuration.
1295	*/
1296	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "IOAPIC", "");
1297
1298	/* query whether we got an IOAPIC */
1299	bool fUseIoApic;
1300	int rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
1301	if (RT_FAILURE(rc))
1302	return PDMDEV_SET_ERROR(pDevIns, rc,
1303	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
1304
1305	Log(("PCI: fUseIoApic=%RTbool fR0Enabled=%RTbool fRCEnabled=%RTbool\n", fUseIoApic, pDevIns->fR0Enabled, pDevIns->fRCEnabled));
1306
1307	/*
1308	* Init data and register the PCI bus.
1309	*/
1310	pGlobals->uPciBiosIo = 0xc000;
1311	pGlobals->uPciBiosMmio = 0xf0000000;
1312	memset((void *)&pGlobals->u.Piix3.auPciLegacyIrqLevels, 0, sizeof(pGlobals->u.Piix3.auPciLegacyIrqLevels));
1313	pGlobals->fUseIoApic = fUseIoApic;
1314	memset((void *)&pGlobals->auPciApicIrqLevels, 0, sizeof(pGlobals->auPciApicIrqLevels));
1315
1316	pGlobals->PciBus.enmType = DEVPCIBUSTYPE_PIIX3;
1317	pGlobals->PciBus.fPureBridge = false;
1318	pGlobals->PciBus.papBridgesR3 = (PPDMPCIDEV *)PDMDevHlpMMHeapAllocZ(pDevIns,
1319	sizeof(PPDMPCIDEV)
1320	* RT_ELEMENTS(pGlobals->PciBus.apDevices));
1321	AssertLogRelReturn(pGlobals->PciBus.papBridgesR3, VERR_NO_MEMORY);
1322
1323	PDEVPCIBUS pBus = &pGlobals->PciBus;
1324	PDMPCIBUSREGCC PciBusReg;
1325	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1326	PciBusReg.pfnRegisterR3 = devpciR3CommonRegisterDevice;
1327	PciBusReg.pfnRegisterMsiR3 = NULL;
1328	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1329	PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
1330	PciBusReg.pfnConfigRead = devpciR3CommonConfigRead;
1331	PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite;
1332	PciBusReg.pfnSetIrqR3 = pciSetIrq;
1333	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1334	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
1335	if (RT_FAILURE(rc))
1336	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
1337	Assert(pBus->iBus == 0);
1338	if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1339	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1340	N_("PCI helper version mismatch; got %#x expected %#x"),
1341	pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1342
1343	/* Disable default device locking. */
1344	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1345	AssertRCReturn(rc, rc);
1346
1347	/*
1348	* Fill in PCI configs and add them to the bus.
1349	*/
1350	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1351	AssertPtr(pPciDev);
1352
1353	/* i440FX */
1354	PCIDevSetVendorId( pPciDev, 0x8086); /* Intel */
1355	PCIDevSetDeviceId( pPciDev, 0x1237);
1356	PCIDevSetRevisionId(pPciDev, 0x02);
1357	PCIDevSetClassSub( pPciDev, 0x00); /* host2pci */
1358	PCIDevSetClassBase( pPciDev, 0x06); /* PCI_bridge */
1359	PCIDevSetHeaderType(pPciDev, 0x00);
1360	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, 0 /fFlags/, 0 /uPciDevNo/, 0 /uPciFunNo/, "i440FX");
1361	AssertLogRelRCReturn(rc, rc);
1362
1363	/* PIIX3 */
1364	PPDMPCIDEV pPiix3PciDev = pDevIns->apPciDevs[1];
1365	PCIDevSetVendorId( pPiix3PciDev, 0x8086); /* Intel */
1366	PCIDevSetDeviceId( pPiix3PciDev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
1367	PCIDevSetClassSub( pPiix3PciDev, 0x01); /* PCI_ISA */
1368	PCIDevSetClassBase( pPiix3PciDev, 0x06); /* PCI_bridge */
1369	PCIDevSetHeaderType(pPiix3PciDev, 0x80); /* PCI_multifunction, generic */
1370	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPiix3PciDev, 0 /fFlags/, 1 /uPciDevNo/, 0 /uPciFunNo/, "PIIX3");
1371	AssertLogRelRCReturn(rc, rc);
1372	pciR3Piix3Reset(pDevIns->apPciDevs[1]);
1373
1374	pBus->iDevSearch = 16;
1375
1376	/*
1377	* Register I/O ports and save state.
1378	*/
1379	static const IOMIOPORTDESC s_aAddrDesc[] = { { "PCI address", "PCI address", NULL, NULL }, { NULL, NULL, NULL, NULL } };
1380	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cf8, 1, pciIOPortAddressWrite, pciIOPortAddressRead, "i440FX (PCI)", s_aAddrDesc,
1381	&pGlobals->hIoPortAddress);
1382	AssertLogRelRCReturn(rc, rc);
1383
1384	static const IOMIOPORTDESC s_aDataDesc[] = { { "PCI data", "PCI data", NULL, NULL }, { NULL, NULL, NULL, NULL } };
1385	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0cfc, 4, pciIOPortDataWrite, pciIOPortDataRead, "i440FX (PCI)", s_aDataDesc,
1386	&pGlobals->hIoPortData);
1387	AssertLogRelRCReturn(rc, rc);
1388
1389	static const IOMIOPORTDESC s_aMagicDesc[] = { { "PCI magic", NULL, NULL, NULL }, { NULL, NULL, NULL, NULL } };
1390	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x0410, 1, pciR3IOPortMagicPCIWrite, pciR3IOPortMagicPCIRead,
1391	"i440FX (Fake PCI BIOS trigger)", s_aMagicDesc, &pGlobals->hIoPortMagic);
1392	AssertLogRelRCReturn(rc, rc);
1393
1394
1395	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
1396	NULL, NULL, NULL,
1397	NULL, pciR3SaveExec, NULL,
1398	NULL, pciR3LoadExec, NULL);
1399	AssertLogRelRCReturn(rc, rc);
1400
1401	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
1402	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
1403	devpciR3InfoPci);
1404	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", devpciR3InfoPciIrq);
1405	PDMDevHlpDBGFInfoRegister(pDevIns, "pirq", "Display PIRQ state. (no arguments)", devpciR3InfoPIRQ);
1406	PDMDevHlpDBGFInfoRegister(pDevIns, "irqroute", "Display PCI IRQ routing. (no arguments)", pciR3IrqRouteInfo);
1407
1408	return VINF_SUCCESS;
1409	}
1410
1411	#else /* !IN_RING3 */
1412
1413	/**
1414	* @interface_method_impl{PDMDEVREGR0,pfnConstruct}
1415	*/
1416	static DECLCALLBACK(int) pciRZRootConstruct(PPDMDEVINS pDevIns)
1417	{
1418	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1419	PDEVPCIROOT pGlobals = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
1420	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1421
1422	/* Mirror the ring-3 device lock disabling: */
1423	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1424	AssertRCReturn(rc, rc);
1425
1426	/* Set up the RZ PCI bus callbacks: */
1427	PDMPCIBUSREGCC PciBusReg;
1428	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1429	PciBusReg.iBus = pGlobals->PciBus.iBus;
1430	PciBusReg.pfnSetIrq = pciSetIrq;
1431	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1432	rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
1433	AssertRCReturn(rc, rc);
1434
1435	/* Set up I/O port callbacks, except for the magic port: */
1436	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pGlobals->hIoPortAddress, pciIOPortAddressWrite, pciIOPortAddressRead, NULL);
1437	AssertLogRelRCReturn(rc, rc);
1438
1439	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pGlobals->hIoPortData, pciIOPortDataWrite, pciIOPortDataRead, NULL);
1440	AssertLogRelRCReturn(rc, rc);
1441
1442	return rc;
1443	}
1444
1445	#endif /* !IN_RING3 */
1446
1447	/**
1448	* The device registration structure.
1449	*/
1450	const PDMDEVREG g_DevicePCI =
1451	{
1452	/* .u32Version = */ PDM_DEVREG_VERSION,
1453	/* .uReserved0 = */ 0,
1454	/* .szName = */ "pci",
1455	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1456	/* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI,
1457	/* .cMaxInstances = */ 1,
1458	/* .uSharedVersion = */ 42,
1459	/* .cbInstanceShared = */ sizeof(DEVPCIROOT),
1460	/* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)),
1461	/* .cbInstanceRC = */ sizeof(DEVPCIBUSRC),
1462	/* .cMaxPciDevices = */ 2,
1463	/* .cMaxMsixVectors = */ 0,
1464	/* .pszDescription = */ "i440FX PCI bridge and PIIX3 ISA bridge.",
1465	#if defined(IN_RING3)
1466	/* .pszRCMod = */ "VBoxDDRC.rc",
1467	/* .pszR0Mod = */ "VBoxDDR0.r0",
1468	/* .pfnConstruct = */ pciR3Construct,
1469	/* .pfnDestruct = */ pciR3Destruct,
1470	/* .pfnRelocate = */ NULL,
1471	/* .pfnMemSetup = */ NULL,
1472	/* .pfnPowerOn = */ NULL,
1473	/* .pfnReset = */ pciR3Reset,
1474	/* .pfnSuspend = */ NULL,
1475	/* .pfnResume = */ NULL,
1476	/* .pfnAttach = */ NULL,
1477	/* .pfnDetach = */ NULL,
1478	/* .pfnQueryInterface = */ NULL,
1479	/* .pfnInitComplete = */ NULL,
1480	/* .pfnPowerOff = */ NULL,
1481	/* .pfnSoftReset = */ NULL,
1482	/* .pfnReserved0 = */ NULL,
1483	/* .pfnReserved1 = */ NULL,
1484	/* .pfnReserved2 = */ NULL,
1485	/* .pfnReserved3 = */ NULL,
1486	/* .pfnReserved4 = */ NULL,
1487	/* .pfnReserved5 = */ NULL,
1488	/* .pfnReserved6 = */ NULL,
1489	/* .pfnReserved7 = */ NULL,
1490	#elif defined(IN_RING0)
1491	/* .pfnEarlyConstruct = */ NULL,
1492	/* .pfnConstruct = */ pciRZRootConstruct,
1493	/* .pfnDestruct = */ NULL,
1494	/* .pfnFinalDestruct = */ NULL,
1495	/* .pfnRequest = */ NULL,
1496	/* .pfnReserved0 = */ NULL,
1497	/* .pfnReserved1 = */ NULL,
1498	/* .pfnReserved2 = */ NULL,
1499	/* .pfnReserved3 = */ NULL,
1500	/* .pfnReserved4 = */ NULL,
1501	/* .pfnReserved5 = */ NULL,
1502	/* .pfnReserved6 = */ NULL,
1503	/* .pfnReserved7 = */ NULL,
1504	#elif defined(IN_RC)
1505	/* .pfnConstruct = */ pciRZRootConstruct,
1506	/* .pfnReserved0 = */ NULL,
1507	/* .pfnReserved1 = */ NULL,
1508	/* .pfnReserved2 = */ NULL,
1509	/* .pfnReserved3 = */ NULL,
1510	/* .pfnReserved4 = */ NULL,
1511	/* .pfnReserved5 = */ NULL,
1512	/* .pfnReserved6 = */ NULL,
1513	/* .pfnReserved7 = */ NULL,
1514	#else
1515	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1516	#endif
1517	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1518
1519	};
1520
1521
1522
1523	/* -=-=-=-=-=- The PCI bridge specific bits -=-=-=-=-=- */
1524
1525	/**
1526	* @interface_method_impl{PDMPCIBUSREGR3,pfnSetIrqR3}
1527	*/
1528	static DECLCALLBACK(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
1529	{
1530	LogFlow(("pcibridgeSetIrq: %p %u %u %#x\n", pPciDev, iIrq, iLevel, uTagSrc));
1531
1532	/*
1533	* The PCI-to-PCI bridge specification defines how the interrupt pins
1534	* are routed from the secondary to the primary bus (see chapter 9).
1535	* iIrq gives the interrupt pin the pci device asserted.
1536	* We change iIrq here according to the spec and call the SetIrq function
1537	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
1538	*/
1539	PDEVPCIBUS pBus;
1540	uint8_t uDevFnBridge;
1541	int iIrqPinBridge;
1542	PPDMDEVINS pDevInsBus = devpcibridgeCommonSetIrqRootWalk(pDevIns, pPciDev, iIrq, &pBus, &uDevFnBridge, &iIrqPinBridge);
1543	AssertReturnVoid(pDevInsBus);
1544	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
1545	Assert(pDevInsBus->pReg == &g_DevicePCI);
1546
1547	pciSetIrqInternal(pDevInsBus, DEVPCIBUS_2_DEVPCIROOT(pBus), PDMINS_2_DATA_CC(pDevInsBus, PDEVPCIBUSCC),
1548	uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
1549	}
1550
1551	#ifdef IN_RING3
1552
1553	/**
1554	* @callback_method_impl{FNPCIBRIDGECONFIGWRITE}
1555	*/
1556	static DECLCALLBACK(VBOXSTRICTRC) pcibridgeR3ConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
1557	uint32_t u32Address, unsigned cb, uint32_t u32Value)
1558	{
1559	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d u32Value=%u\n", pDevIns, iBus, iDevice, u32Address, cb, u32Value));
1560	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1561	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1562
1563	/* If the current bus is not the target bus search for the bus which contains the device. */
1564	if (iBus != pDevIns->apPciDevs[0]->abConfig[VBOX_PCI_SECONDARY_BUS])
1565	{
1566	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1567	if (pBridgeDevice)
1568	{
1569	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
1570	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->Int.s.CTX_SUFF(pDevIns), iBus, iDevice,
1571	u32Address, cb, u32Value);
1572	}
1573	}
1574	else
1575	{
1576	/* This is the target bus, pass the write to the device. */
1577	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1578	if (pPciDev)
1579	{
1580	LogFunc(("%s: addr=%02x val=%08x len=%d\n", pPciDev->pszNameR3, u32Address, u32Value, cb));
1581	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
1582	if (pPciDev->Int.s.pfnConfigWrite)
1583	rcStrict = pPciDev->Int.s.pfnConfigWrite(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, u32Value);
1584	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
1585	rcStrict = devpciR3CommonConfigWriteWorker(pDevIns, PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
1586	pPciDev, u32Address, cb, u32Value);
1587	}
1588	}
1589	return rcStrict;
1590	}
1591
1592
1593	/**
1594	* @callback_method_impl{FNPCIBRIDGECONFIGREAD}
1595	*/
1596	static DECLCALLBACK(VBOXSTRICTRC) pcibridgeR3ConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice,
1597	uint32_t u32Address, unsigned cb, uint32_t *pu32Value)
1598	{
1599	LogFlowFunc(("pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
1600	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1601	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1602
1603	/* If the current bus is not the target bus search for the bus which contains the device. */
1604	if (iBus != pDevIns->apPciDevs[0]->abConfig[VBOX_PCI_SECONDARY_BUS])
1605	{
1606	PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus);
1607	if (pBridgeDevice)
1608	{
1609	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
1610	rcStrict = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->Int.s.CTX_SUFF(pDevIns),
1611	iBus, iDevice, u32Address, cb, pu32Value);
1612	}
1613	else
1614	*pu32Value = UINT32_MAX;
1615	}
1616	else
1617	{
1618	/* This is the target bus, pass the read to the device. */
1619	PPDMPCIDEV pPciDev = pBus->apDevices[iDevice];
1620	if (pPciDev)
1621	{
1622	rcStrict = VINF_PDM_PCI_DO_DEFAULT;
1623	if (pPciDev->Int.s.pfnConfigRead)
1624	rcStrict = pPciDev->Int.s.pfnConfigRead(pPciDev->Int.s.CTX_SUFF(pDevIns), pPciDev, u32Address, cb, pu32Value);
1625	if (rcStrict == VINF_PDM_PCI_DO_DEFAULT)
1626	rcStrict = devpciR3CommonConfigReadWorker(pPciDev, u32Address, cb, pu32Value);
1627
1628	LogFunc(("%s: u32Address=%02x u32Value=%08x cb=%d\n", pPciDev->pszNameR3, u32Address, *pu32Value, cb));
1629	}
1630	else
1631	*pu32Value = UINT32_MAX;
1632	}
1633
1634	return rcStrict;
1635	}
1636
1637
1638	/**
1639	* @callback_method_impl{FNSSMDEVSAVEEXEC}
1640	*/
1641	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1642	{
1643	return pciR3CommonSaveExec(pDevIns->pHlpR3, PDMINS_2_DATA(pDevIns, PDEVPCIBUS), pSSM);
1644	}
1645
1646
1647	/**
1648	* @callback_method_impl{FNSSMDEVLOADEXEC}
1649	*/
1650	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1651	{
1652	PDEVPCIBUS pThis = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1653	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1654	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1655	return pciR3CommonLoadExec(pDevIns, pThis, pSSM, uVersion, uPass);
1656	}
1657
1658
1659	/**
1660	* @interface_method_impl{PDMDEVREG,pfnReset}
1661	*/
1662	static DECLCALLBACK(void) pcibridgeR3Reset(PPDMDEVINS pDevIns)
1663	{
1664	/* Reset config space to default values. */
1665	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1666	pPciDev->abConfig[VBOX_PCI_PRIMARY_BUS] = 0;
1667	pPciDev->abConfig[VBOX_PCI_SECONDARY_BUS] = 0;
1668	pPciDev->abConfig[VBOX_PCI_SUBORDINATE_BUS] = 0;
1669	}
1670
1671
1672	/**
1673	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1674	*/
1675	static DECLCALLBACK(int) pcibridgeR3Destruct(PPDMDEVINS pDevIns)
1676	{
1677	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1678	if (pBus->papBridgesR3)
1679	{
1680	PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
1681	pBus->papBridgesR3 = NULL;
1682	}
1683	return VINF_SUCCESS;
1684	}
1685
1686
1687	/**
1688	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1689	*/
1690	static DECLCALLBACK(int) pcibridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1691	{
1692	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1693	RT_NOREF(iInstance, pCfg);
1694	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1695	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1696
1697	/*
1698	* Validate and read configuration (none left).
1699	*/
1700	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "", "");
1701	Log(("PCI: fRCEnabled=%RTbool fR0Enabled=%RTbool\n", pDevIns->fRCEnabled, pDevIns->fR0Enabled));
1702
1703	/*
1704	* Init data and register the PCI bus.
1705	*/
1706	pBus->enmType = DEVPCIBUSTYPE_PIIX3;
1707	pBus->fPureBridge = true;
1708	pBus->papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pBus->apDevices));
1709	AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
1710
1711	PDMPCIBUSREGCC PciBusReg;
1712	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1713	PciBusReg.pfnRegisterR3 = devpcibridgeR3CommonRegisterDevice;
1714	PciBusReg.pfnRegisterMsiR3 = NULL;
1715	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
1716	PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
1717	PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite;
1718	PciBusReg.pfnConfigRead = devpciR3CommonConfigRead;
1719	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
1720	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1721	int rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
1722	if (RT_FAILURE(rc))
1723	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
1724	Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
1725	if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
1726	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1727	N_("PCI helper version mismatch; got %#x expected %#x"),
1728	pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
1729
1730	/*
1731	* Fill in PCI configs and add them to the bus.
1732	*/
1733	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1734	PCIDevSetVendorId( pPciDev, 0x8086); /* Intel */
1735	PCIDevSetDeviceId( pPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
1736	PCIDevSetRevisionId(pPciDev, 0xf2);
1737	PCIDevSetClassSub( pPciDev, 0x04); /* pci2pci */
1738	PCIDevSetClassBase( pPciDev, 0x06); /* PCI_bridge */
1739	PCIDevSetClassProg( pPciDev, 0x01); /* Supports subtractive decoding. */
1740	PCIDevSetHeaderType(pPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
1741	PCIDevSetCommand( pPciDev, 0x0000);
1742	PCIDevSetStatus( pPciDev, 0x0020); /* 66MHz Capable. */
1743	PCIDevSetInterruptLine(pPciDev, 0x00); /* This device does not assert interrupts. */
1744
1745	/*
1746	* This device does not generate interrupts. Interrupt delivery from
1747	* devices attached to the bus is unaffected.
1748	*/
1749	PCIDevSetInterruptPin(pPciDev, 0x00);
1750
1751	/*
1752	* Register this PCI bridge. The called function will take care on which bus we will get registered.
1753	*/
1754	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, PDMPCIDEVREG_F_PCI_BRIDGE, PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
1755	PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "pcibridge");
1756	if (RT_FAILURE(rc))
1757	return rc;
1758	pPciDev->Int.s.pfnBridgeConfigRead = pcibridgeR3ConfigRead;
1759	pPciDev->Int.s.pfnBridgeConfigWrite = pcibridgeR3ConfigWrite;
1760
1761	pBus->iDevSearch = 0;
1762
1763	/*
1764	* Register SSM handlers. We use the same saved state version as for the host bridge
1765	* to make changes easier.
1766	*/
1767	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
1768	NULL, NULL, NULL,
1769	NULL, pcibridgeR3SaveExec, NULL,
1770	NULL, pcibridgeR3LoadExec, NULL);
1771	if (RT_FAILURE(rc))
1772	return rc;
1773
1774	return VINF_SUCCESS;
1775	}
1776
1777	#else /* !IN_RING3 */
1778
1779	/**
1780	* @interface_method_impl{PDMDEVREGR0,pfnConstruct}
1781	*/
1782	static DECLCALLBACK(int) pcibridgeRZConstruct(PPDMDEVINS pDevIns)
1783	{
1784	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1785	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
1786	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
1787
1788	PDMPCIBUSREGCC PciBusReg;
1789	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
1790	PciBusReg.iBus = pBus->iBus;
1791	PciBusReg.pfnSetIrq = pcibridgeSetIrq;
1792	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
1793	int rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
1794	AssertRC(rc);
1795
1796	return rc;
1797	}
1798
1799	#endif /* !IN_RING3 */
1800
1801	/**
1802	* The device registration structure
1803	* for the PCI-to-PCI bridge.
1804	*/
1805	const PDMDEVREG g_DevicePCIBridge =
1806	{
1807	/* .u32Version = */ PDM_DEVREG_VERSION,
1808	/* .uReserved0 = */ 0,
1809	/* .szName = */ "pcibridge",
1810	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1811	/* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI,
1812	/* .cMaxInstances = */ ~0U,
1813	/* .uSharedVersion = */ 42,
1814	/* .cbInstanceShared = */ sizeof(DEVPCIBUS),
1815	/* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)),
1816	/* .cbInstanceRC = */ 0,
1817	/* .cMaxPciDevices = */ 1,
1818	/* .cMaxMsixVectors = */ 0,
1819	/* .pszDescription = */ "82801 Mobile PCI to PCI bridge",
1820	#if defined(IN_RING3)
1821	/* .pszRCMod = */ "VBoxDDRC.rc",
1822	/* .pszR0Mod = */ "VBoxDDR0.r0",
1823	/* .pfnConstruct = */ pcibridgeR3Construct,
1824	/* .pfnDestruct = */ pcibridgeR3Destruct,
1825	/* .pfnRelocate = */ NULL,
1826	/* .pfnMemSetup = */ NULL,
1827	/* .pfnPowerOn = */ NULL,
1828	/* .pfnReset = */ pcibridgeR3Reset,
1829	/* .pfnSuspend = */ NULL,
1830	/* .pfnResume = */ NULL,
1831	/* .pfnAttach = */ NULL,
1832	/* .pfnDetach = */ NULL,
1833	/* .pfnQueryInterface = */ NULL,
1834	/* .pfnInitComplete = */ NULL,
1835	/* .pfnPowerOff = */ NULL,
1836	/* .pfnSoftReset = */ NULL,
1837	/* .pfnReserved0 = */ NULL,
1838	/* .pfnReserved1 = */ NULL,
1839	/* .pfnReserved2 = */ NULL,
1840	/* .pfnReserved3 = */ NULL,
1841	/* .pfnReserved4 = */ NULL,
1842	/* .pfnReserved5 = */ NULL,
1843	/* .pfnReserved6 = */ NULL,
1844	/* .pfnReserved7 = */ NULL,
1845	#elif defined(IN_RING0)
1846	/* .pfnEarlyConstruct = */ NULL,
1847	/* .pfnConstruct = */ pcibridgeRZConstruct,
1848	/* .pfnDestruct = */ NULL,
1849	/* .pfnFinalDestruct = */ NULL,
1850	/* .pfnRequest = */ NULL,
1851	/* .pfnReserved0 = */ NULL,
1852	/* .pfnReserved1 = */ NULL,
1853	/* .pfnReserved2 = */ NULL,
1854	/* .pfnReserved3 = */ NULL,
1855	/* .pfnReserved4 = */ NULL,
1856	/* .pfnReserved5 = */ NULL,
1857	/* .pfnReserved6 = */ NULL,
1858	/* .pfnReserved7 = */ NULL,
1859	#elif defined(IN_RC)
1860	/* .pfnConstruct = */ pcibridgeRZConstruct,
1861	/* .pfnReserved0 = */ NULL,
1862	/* .pfnReserved1 = */ NULL,
1863	/* .pfnReserved2 = */ NULL,
1864	/* .pfnReserved3 = */ NULL,
1865	/* .pfnReserved4 = */ NULL,
1866	/* .pfnReserved5 = */ NULL,
1867	/* .pfnReserved6 = */ NULL,
1868	/* .pfnReserved7 = */ NULL,
1869	#else
1870	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1871	#endif
1872	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1873	};
1874

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 106054

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