DevPCI.cpp@ 30714

Last change on this file since 30714 was 30130, checked in by vboxsync, 15 years ago
PCI: make LPC placement on the bus unconditional (fixes older OSX guests)
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1	/* $Id: DevPCI.cpp 30130 2010-06-09 16:22:21Z vboxsync $ */
2	/** @file
3	* DevPCI - PCI BUS Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU PCI bus manager
21	*
22	* Copyright (c) 2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43	/*******************************************************************************
44	* Header Files *
45	*******************************************************************************/
46	#define LOG_GROUP LOG_GROUP_DEV_PCI
47	/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
48	#define PCI_INCLUDE_PRIVATE
49	#include <VBox/pci.h>
50	#include <VBox/pdmdev.h>
51	#include <iprt/asm.h>
52	#include <iprt/assert.h>
53	#include <iprt/string.h>
54
55	#include "../Builtins.h"
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* PIIX3 ISA Bridge state.
63	*/
64	typedef struct PIIX3State
65	{
66	/** The PCI device of the bridge. */
67	PCIDEVICE dev;
68	} PIIX3State, PIIX3, *PPIIX3;
69
70	/**
71	* PCI Bus instance.
72	*/
73	typedef struct PCIBus
74	{
75	/** Bus number. */
76	int32_t iBus;
77	/** Start device number. */
78	int32_t iDevSearch;
79	/** Number of bridges attached to the bus. */
80	uint32_t cBridges;
81
82	uint32_t Alignment0;
83
84	/** Array of PCI devices. */
85	R3PTRTYPE(PPCIDEVICE) devices[256];
86	/** Array of bridges attached to the bus. */
87	R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
88
89	/** R3 pointer to the device instance. */
90	PPDMDEVINSR3 pDevInsR3;
91	/** Pointer to the PCI R3 helpers. */
92	PCPDMPCIHLPR3 pPciHlpR3;
93
94	/** R0 pointer to the device instance. */
95	PPDMDEVINSR0 pDevInsR0;
96	/** Pointer to the PCI R0 helpers. */
97	PCPDMPCIHLPR0 pPciHlpR0;
98
99	/** RC pointer to the device instance. */
100	PPDMDEVINSRC pDevInsRC;
101	/** Pointer to the PCI RC helpers. */
102	PCPDMPCIHLPRC pPciHlpRC;
103
104	/** The PCI device for the PCI bridge. */
105	PCIDEVICE PciDev;
106
107	} PCIBUS;
108	/** Pointer to a PCIBUS instance. */
109	typedef PCIBUS *PPCIBUS;
110	typedef PCIBUS PCIBus;
111
112	/** @def PCI_IRQ_PINS
113	* Number of pins for interrupts (PIRQ#0...PIRQ#3)
114	*/
115	#define PCI_IRQ_PINS 4
116
117	/** @def PCI_APIC_IRQ_PINS
118	* Number of pins for interrupts if the APIC is used.
119	*/
120	#define PCI_APIC_IRQ_PINS 8
121
122	/**
123	* PCI Globals - This is the host-to-pci bridge and the root bus.
124	*/
125	typedef struct PCIGLOBALS
126	{
127	/** Irq levels for the four PCI Irqs.
128	* These count how many devices asserted
129	* the IRQ line. If greater 0 an IRQ is sent to the guest.
130	* If it drops to 0 the IRQ is deasserted.
131	*/
132	volatile uint32_t pci_irq_levels[PCI_IRQ_PINS];
133
134	#if 1 /* Will be moved into the BIOS soon. */
135	/** The next I/O port address which the PCI BIOS will use. */
136	uint32_t pci_bios_io_addr;
137	/** The next MMIO address which the PCI BIOS will use. */
138	uint32_t pci_bios_mem_addr;
139	/** Actual bus number. */
140	uint8_t uBus;
141	#endif
142
143	/** I/O APIC usage flag */
144	bool fUseIoApic;
145	/** I/O APIC irq levels */
146	volatile uint32_t pci_apic_irq_levels[PCI_APIC_IRQ_PINS];
147	/** ACPI IRQ level */
148	uint32_t acpi_irq_level;
149	/** ACPI PIC IRQ */
150	int acpi_irq;
151	/** Config register. */
152	uint32_t uConfigReg;
153
154	/** R3 pointer to the device instance. */
155	PPDMDEVINSR3 pDevInsR3;
156	/** R0 pointer to the device instance. */
157	PPDMDEVINSR0 pDevInsR0;
158	/** RC pointer to the device instance. */
159	PPDMDEVINSRC pDevInsRC;
160
161	#if HC_ARCH_BITS == 64
162	uint32_t Alignment0;
163	#endif
164
165	/** ISA bridge state. */
166	PIIX3 PIIX3State;
167	/** PCI bus which is attached to the host-to-PCI bridge. */
168	PCIBUS PciBus;
169
170	} PCIGLOBALS;
171	/** Pointer to per VM data. */
172	typedef PCIGLOBALS *PPCIGLOBALS;
173
174
175	/*******************************************************************************
176	* Defined Constants And Macros *
177	*******************************************************************************/
178
179	/** Converts a bus instance pointer to a device instance pointer. */
180	#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
181	/** Converts a device instance pointer to a PCIGLOBALS pointer. */
182	#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
183	/** Converts a device instance pointer to a PCIBUS pointer. */
184	#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->PciBus))
185
186	/** Converts a pointer to a PCI bus instance to a PCIGLOBALS pointer.
187	* @note This works only if the bus number is 0!!!
188	*/
189	#define PCIBUS_2_PCIGLOBALS(pPciBus) ( (PPCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(PCIGLOBALS, PciBus)) )
190
191	/** @def PCI_LOCK
192	* Acquires the PDM lock. This is a NOP if locking is disabled. */
193	/** @def PCI_UNLOCK
194	* Releases the PDM lock. This is a NOP if locking is disabled. */
195	#define PCI_LOCK(pDevIns, rc) \
196	do { \
197	int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
198	if (rc2 != VINF_SUCCESS) \
199	return rc2; \
200	} while (0)
201	#define PCI_UNLOCK(pDevIns) \
202	DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
203
204	/** @def VBOX_PCI_SAVED_STATE_VERSION
205	* Saved state version of the PCI bus device.
206	*/
207	#define VBOX_PCI_SAVED_STATE_VERSION 3
208
209
210	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
211	/*******************************************************************************
212	* Internal Functions *
213	*******************************************************************************/
214	RT_C_DECLS_BEGIN
215
216	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
217	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel);
218	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
219	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
220	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
221	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
222
223	#ifdef IN_RING3
224	DECLINLINE(PPCIDEVICE) pciFindBridge(PPCIBUS pBus, uint8_t iBus);
225	#endif
226
227	RT_C_DECLS_END
228
229	#define DEBUG_PCI
230
231	#define PCI_VENDOR_ID 0x00 /* 16 bits */
232	#define PCI_DEVICE_ID 0x02 /* 16 bits */
233	#define PCI_COMMAND 0x04 /* 16 bits */
234	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
235	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
236	#define PCI_CLASS_DEVICE 0x0a /* Device class */
237	#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
238	#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
239	#define PCI_MIN_GNT 0x3e /* 8 bits */
240	#define PCI_MAX_LAT 0x3f /* 8 bits */
241
242
243	#ifdef IN_RING3
244
245	static void pci_update_mappings(PCIDevice *d)
246	{
247	PPCIBUS pBus = d->Int.s.CTX_SUFF(pBus);
248	PCIIORegion *r;
249	int cmd, i;
250	uint32_t last_addr, new_addr, config_ofs;
251
252	cmd = RT_LE2H_U16((uint16_t )(d->config + PCI_COMMAND));
253	for(i = 0; i < PCI_NUM_REGIONS; i++) {
254	r = &d->Int.s.aIORegions[i];
255	if (i == PCI_ROM_SLOT) {
256	config_ofs = 0x30;
257	} else {
258	config_ofs = 0x10 + i * 4;
259	}
260	if (r->size != 0) {
261	if (r->type & PCI_ADDRESS_SPACE_IO) {
262	if (cmd & PCI_COMMAND_IO) {
263	new_addr = RT_LE2H_U32((uint32_t )(d->config +
264	config_ofs));
265	new_addr = new_addr & ~(r->size - 1);
266	last_addr = new_addr + r->size - 1;
267	/* NOTE: we have only 64K ioports on PC */
268	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
269	last_addr >= 0x10000) {
270	new_addr = ~0U;
271	}
272	} else {
273	new_addr = ~0U;
274	}
275	} else {
276	if (cmd & PCI_COMMAND_MEMORY) {
277	new_addr = RT_LE2H_U32((uint32_t )(d->config +
278	config_ofs));
279	/* the ROM slot has a specific enable bit */
280	if (i == PCI_ROM_SLOT && !(new_addr & 1))
281	goto no_mem_map;
282	new_addr = new_addr & ~(r->size - 1);
283	last_addr = new_addr + r->size - 1;
284	/* NOTE: we do not support wrapping */
285	/* XXX: as we cannot support really dynamic
286	mappings, we handle specific values as invalid
287	mappings. */
288	if (last_addr <= new_addr \|\| new_addr == 0 \|\|
289	last_addr == ~0U) {
290	new_addr = ~0U;
291	}
292	} else {
293	no_mem_map:
294	new_addr = ~0U;
295	}
296	}
297	/* now do the real mapping */
298	if (new_addr != r->addr) {
299	if (r->addr != ~0U) {
300	if (r->type & PCI_ADDRESS_SPACE_IO) {
301	int devclass;
302	/* NOTE: specific hack for IDE in PC case:
303	only one byte must be mapped. */
304	devclass = d->config[0x0a] \| (d->config[0x0b] << 8);
305	if (devclass == 0x0101 && r->size == 4) {
306	int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr + 2, 1);
307	AssertRC(rc);
308	} else {
309	int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr, r->size);
310	AssertRC(rc);
311	}
312	} else {
313	RTGCPHYS GCPhysBase = r->addr;
314	int rc;
315	if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, d->pDevIns, GCPhysBase))
316	{
317	/* unmap it. */
318	rc = r->map_func(d, i, NIL_RTGCPHYS, r->size, (PCIADDRESSSPACE)(r->type));
319	AssertRC(rc);
320	rc = PDMDevHlpMMIO2Unmap(d->pDevIns, i, GCPhysBase);
321	}
322	else
323	rc = PDMDevHlpMMIODeregister(d->pDevIns, GCPhysBase, r->size);
324	AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, d->name, i, GCPhysBase, r->size));
325	}
326	}
327	r->addr = new_addr;
328	if (r->addr != ~0U) {
329	int rc = r->map_func(d, i,
330	r->addr + (r->type & PCI_ADDRESS_SPACE_IO ? 0 : 0),
331	r->size, (PCIADDRESSSPACE)(r->type));
332	AssertRC(rc);
333	}
334	}
335	}
336	}
337	}
338
339
340	static DECLCALLBACK(uint32_t) pci_default_read_config(PCIDevice *d, uint32_t address, unsigned len)
341	{
342	uint32_t val;
343	switch(len) {
344	case 1:
345	val = d->config[address];
346	break;
347	case 2:
348	val = RT_LE2H_U16((uint16_t )(d->config + address));
349	break;
350	default:
351	case 4:
352	val = RT_LE2H_U32((uint32_t )(d->config + address));
353	break;
354	}
355	return val;
356	}
357
358	static DECLCALLBACK(void) pci_default_write_config(PCIDevice *d, uint32_t address, uint32_t val, unsigned len)
359	{
360	int can_write;
361	unsigned i;
362	uint32_t end, addr;
363
364	if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) \|\|
365	(address >= 0x30 && address < 0x34))) {
366	PCIIORegion *r;
367	int reg;
368
369	if ( address >= 0x30 ) {
370	reg = PCI_ROM_SLOT;
371	}else{
372	reg = (address - 0x10) >> 2;
373	}
374	r = &d->Int.s.aIORegions[reg];
375	if (r->size == 0)
376	goto default_config;
377	/* compute the stored value */
378	if (reg == PCI_ROM_SLOT) {
379	/* keep ROM enable bit */
380	val &= (~(r->size - 1)) \| 1;
381	} else {
382	val &= ~(r->size - 1);
383	val \|= r->type;
384	}
385	(uint32_t )(d->config + address) = RT_H2LE_U32(val);
386	pci_update_mappings(d);
387	return;
388	}
389	default_config:
390	/* not efficient, but simple */
391	addr = address;
392	for(i = 0; i < len; i++) {
393	/* default read/write accesses */
394	switch(d->config[0x0e]) {
395	case 0x00: /* normal device */
396	case 0x80: /* multi-function device */
397	switch(addr) {
398	case 0x00:
399	case 0x01:
400	case 0x02:
401	case 0x03:
402	case 0x08:
403	case 0x09:
404	case 0x0a:
405	case 0x0b:
406	case 0x0e:
407	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: /* base */
408	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
409	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
410	case 0x2c: case 0x2d: /* subsystem ID */
411	case 0x2e: case 0x2f: /* vendor ID */
412	case 0x30: case 0x31: case 0x32: case 0x33: /* rom */
413	case 0x3d:
414	can_write = 0;
415	break;
416	default:
417	can_write = 1;
418	break;
419	}
420	break;
421	default:
422	case 0x01: /* bridge */
423	switch(addr) {
424	case 0x00:
425	case 0x01:
426	case 0x02:
427	case 0x03:
428	case 0x08:
429	case 0x09:
430	case 0x0a:
431	case 0x0b:
432	case 0x0e:
433	case 0x38: case 0x39: case 0x3a: case 0x3b: /* rom */
434	case 0x3d:
435	can_write = 0;
436	break;
437	default:
438	can_write = 1;
439	break;
440	}
441	break;
442	}
443	#ifdef VBOX
444	if (addr == 0x06)
445	{
446	/* don't change read-only bits => actually all lower bits are read-only */
447	val &= UINT32_C(~0xff);
448	/* status register, low part: clear bits by writing a '1' to the corresponding bit */
449	d->config[addr] &= ~val;
450	}
451	else if (addr == 0x07)
452	{
453	/* don't change read-only bits */
454	val &= UINT32_C(~0x06);
455	/* status register, high part: clear bits by writing a '1' to the corresponding bit */
456	d->config[addr] &= ~val;
457	}
458	else
459	#endif
460	if (can_write) {
461	d->config[addr] = val;
462	}
463	addr++;
464	val >>= 8;
465	}
466
467	end = address + len;
468	if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
469	/* if the command register is modified, we must modify the mappings */
470	pci_update_mappings(d);
471	}
472	}
473
474	#endif /* IN_RING3 */
475
476	static int pci_data_write(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
477	{
478	uint8_t iBus, iDevice;
479	uint32_t config_addr;
480
481	Log(("pci_data_write: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
482
483	if (!(pGlobals->uConfigReg & (1 << 31))) {
484	return VINF_SUCCESS;
485	}
486	if ((pGlobals->uConfigReg & 0x3) != 0) {
487	return VINF_SUCCESS;
488	}
489	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
490	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
491	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
492	if (iBus != 0)
493	{
494	if (pGlobals->PciBus.cBridges)
495	{
496	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
497	PPCIDEVICE pBridgeDevice = pciFindBridge(&pGlobals->PciBus, iBus);
498	if (pBridgeDevice)
499	{
500	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
501	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, val, len);
502	}
503	#else
504	return VINF_IOM_HC_IOPORT_WRITE;
505	#endif
506	}
507	}
508	else
509	{
510	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
511	if (pci_dev)
512	{
513	#ifdef IN_RING3
514	Log(("pci_config_write: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, val, len));
515	pci_dev->Int.s.pfnConfigWrite(pci_dev, config_addr, val, len);
516	#else
517	return VINF_IOM_HC_IOPORT_WRITE;
518	#endif
519	}
520	}
521	return VINF_SUCCESS;
522	}
523
524	static int pci_data_read(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
525	{
526	uint8_t iBus, iDevice;
527	uint32_t config_addr;
528
529	*pu32 = 0xffffffff;
530
531	if (!(pGlobals->uConfigReg & (1 << 31)))
532	return VINF_SUCCESS;
533	if ((pGlobals->uConfigReg & 0x3) != 0)
534	return VINF_SUCCESS;
535	iBus = (pGlobals->uConfigReg >> 16) & 0xff;
536	iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
537	config_addr = (pGlobals->uConfigReg & 0xfc) \| (addr & 3);
538	if (iBus != 0)
539	{
540	if (pGlobals->PciBus.cBridges)
541	{
542	#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
543	PPCIDEVICE pBridgeDevice = pciFindBridge(&pGlobals->PciBus, iBus);
544	if (pBridgeDevice)
545	{
546	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
547	*pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, len);
548	}
549	#else
550	return VINF_IOM_HC_IOPORT_READ;
551	#endif
552	}
553	}
554	else
555	{
556	R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
557	if (pci_dev)
558	{
559	#ifdef IN_RING3
560	*pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev, config_addr, len);
561	Log(("pci_config_read: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, *pu32, len));
562	#else
563	return VINF_IOM_HC_IOPORT_READ;
564	#endif
565	}
566	}
567
568	return VINF_SUCCESS;
569	}
570
571
572
573	/* return the global irq number corresponding to a given device irq
574	pin. We could also use the bus number to have a more precise
575	mapping.
576	This is the implementation note described in the PCI spec chapter 2.2.6 */
577	static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
578	{
579	int slot_addend;
580	slot_addend = (uDevFn >> 3) - 1;
581	return (irq_num + slot_addend) & 3;
582	}
583
584	static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
585	{
586	return (irq_num + (uDevFn >> 3)) & 7;
587	}
588
589	static inline int get_pci_irq_apic_level(PPCIGLOBALS pGlobals, int irq_num)
590	{
591	return (pGlobals->pci_apic_irq_levels[irq_num] != 0);
592	}
593
594	static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int acpi_irq)
595	{
596	/* This is only allowed to be called with a pointer to the host bus. */
597	AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
598
599	if (acpi_irq == -1) {
600	int apic_irq, apic_level;
601	PPCIGLOBALS pGlobals = PCIBUS_2_PCIGLOBALS(pBus);
602	int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
603
604	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
605	ASMAtomicIncU32(&pGlobals->pci_apic_irq_levels[irq_num]);
606	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
607	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
608
609	apic_irq = irq_num + 0x10;
610	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
611	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
612	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
613	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
614
615	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
616	ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
617	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
618	apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
619	Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
620	R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
621	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level);
622	}
623	} else {
624	Log3(("apic_set_irq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
625	R3STRING(pPciDev->name), irq_num1, iLevel, acpi_irq));
626	pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), acpi_irq, iLevel);
627	}
628	}
629
630	DECLINLINE(int) get_pci_irq_level(PPCIGLOBALS pGlobals, int irq_num)
631	{
632	return (pGlobals->pci_irq_levels[irq_num] != 0);
633	}
634
635	/**
636	* Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
637	*
638	* @param pDevIns Device instance of the host PCI Bus.
639	* @param uDevFn The device number on the host bus which will raise the IRQ
640	* @param pPciDev The PCI device structure which raised the interrupt.
641	* @param iIrq IRQ number to set.
642	* @param iLevel IRQ level.
643	* @remark uDevFn and pPciDev->devfn are not the same if the device is behind a bridge.
644	* In that case uDevFn will be the slot of the bridge which is needed to calculate the
645	* PIRQ value.
646	*/
647	static void pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel)
648	{
649	PPCIBUS pBus = &pGlobals->PciBus;
650	uint8_t *pbCfg = pGlobals->PIIX3State.dev.config;
651	const bool fIsAcpiDevice = pPciDev->config[2] == 0x13 && pPciDev->config[3] == 0x71;
652	/* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
653	* is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
654	* See the \_SB_.PCI0._PRT method in vbox.dsl.
655	*/
656	const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
657	int pic_irq, pic_level;
658
659	/* Check if the state changed. */
660	if (pPciDev->Int.s.uIrqPinState != iLevel)
661	{
662	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
663
664	/* Send interrupt to I/O APIC only. */
665	if (fIsApicEnabled)
666	{
667	if (fIsAcpiDevice)
668	/*
669	* ACPI needs special treatment since SCI is hardwired and
670	* should not be affected by PCI IRQ routing tables at the
671	* same time SCI IRQ is shared in PCI sense hence this
672	* kludge (i.e. we fetch the hardwired value from ACPIs
673	* PCI device configuration space).
674	*/
675	apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->config[PCI_INTERRUPT_LINE]);
676	else
677	apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1);
678	return;
679	}
680
681	if (fIsAcpiDevice)
682	{
683	/* As per above treat ACPI in a special way */
684	pic_irq = pPciDev->config[PCI_INTERRUPT_LINE];
685	pGlobals->acpi_irq = pic_irq;
686	pGlobals->acpi_irq_level = iLevel & PDM_IRQ_LEVEL_HIGH;
687	}
688	else
689	{
690	int irq_num;
691	irq_num = pci_slot_get_pirq(uDevFn, iIrq);
692
693	if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
694	ASMAtomicIncU32(&pGlobals->pci_irq_levels[irq_num]);
695	else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
696	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
697
698	/* now we change the pic irq level according to the piix irq mappings */
699	pic_irq = pbCfg[0x60 + irq_num];
700	if (pic_irq >= 16)
701	{
702	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
703	{
704	ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
705	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
706	}
707
708	return;
709	}
710	}
711
712	/* the pic level is the logical OR of all the PCI irqs mapped to it */
713	pic_level = 0;
714	if (pic_irq == pbCfg[0x60])
715	pic_level \|= get_pci_irq_level(pGlobals, 0);
716	if (pic_irq == pbCfg[0x61])
717	pic_level \|= get_pci_irq_level(pGlobals, 1);
718	if (pic_irq == pbCfg[0x62])
719	pic_level \|= get_pci_irq_level(pGlobals, 2);
720	if (pic_irq == pbCfg[0x63])
721	pic_level \|= get_pci_irq_level(pGlobals, 3);
722	if (pic_irq == pGlobals->acpi_irq)
723	pic_level \|= pGlobals->acpi_irq_level;
724
725	Log3(("pciSetIrq: %s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d\n",
726	R3STRING(pPciDev->name), iLevel, iIrq, pic_irq, pic_level));
727	pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level);
728
729	/** @todo optimize pci irq flip-flop some rainy day. */
730	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
731	pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW);
732	}
733	}
734
735	/**
736	* Set the IRQ for a PCI device on the host bus.
737	*
738	* @param pDevIns Device instance of the PCI Bus.
739	* @param pPciDev The PCI device structure.
740	* @param iIrq IRQ number to set.
741	* @param iLevel IRQ level.
742	*/
743	PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
744	{
745	pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel);
746	}
747
748	#ifdef IN_RING3
749
750	/**
751	* Finds a bridge on the bus which contains the destination bus.
752	*
753	* @return Pointer to the device instance data of the bus or
754	* NULL if no bridge was found.
755	* @param pBus Pointer to the bus to search on.
756	* @param iBus Destination bus number.
757	*/
758	DECLINLINE(PPCIDEVICE) pciFindBridge(PPCIBUS pBus, uint8_t iBus)
759	{
760	/* Search for a fitting bridge. */
761	for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
762	{
763	/*
764	* Examine secondary and subordinate bus number.
765	* If the target bus is in the range we pass the request on to the bridge.
766	*/
767	PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
768	AssertMsg(pBridgeTemp && pBridgeTemp->Int.s.fPciToPciBridge,
769	("Device is not a PCI bridge but on the list of PCI bridges\n"));
770
771	if ( iBus >= pBridgeTemp->config[VBOX_PCI_SECONDARY_BUS]
772	&& iBus <= pBridgeTemp->config[VBOX_PCI_SUBORDINATE_BUS])
773	return pBridgeTemp;
774	}
775
776	/* Nothing found. */
777	return NULL;
778	}
779
780	static void piix3_reset(PIIX3State *d)
781	{
782	uint8_t *pci_conf = d->dev.config;
783
784	pci_conf[0x04] = 0x07; /* master, memory and I/O */
785	pci_conf[0x05] = 0x00;
786	pci_conf[0x06] = 0x00;
787	pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
788	pci_conf[0x4c] = 0x4d;
789	pci_conf[0x4e] = 0x03;
790	pci_conf[0x4f] = 0x00;
791	pci_conf[0x60] = 0x80;
792	pci_conf[0x69] = 0x02;
793	pci_conf[0x70] = 0x80;
794	pci_conf[0x76] = 0x0c;
795	pci_conf[0x77] = 0x0c;
796	pci_conf[0x78] = 0x02;
797	pci_conf[0x79] = 0x00;
798	pci_conf[0x80] = 0x00;
799	pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
800	pci_conf[0xa0] = 0x08;
801	pci_conf[0xa0] = 0x08;
802	pci_conf[0xa2] = 0x00;
803	pci_conf[0xa3] = 0x00;
804	pci_conf[0xa4] = 0x00;
805	pci_conf[0xa5] = 0x00;
806	pci_conf[0xa6] = 0x00;
807	pci_conf[0xa7] = 0x00;
808	pci_conf[0xa8] = 0x0f;
809	pci_conf[0xaa] = 0x00;
810	pci_conf[0xab] = 0x00;
811	pci_conf[0xac] = 0x00;
812	pci_conf[0xae] = 0x00;
813	}
814
815	static void pci_config_writel(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
816	{
817	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
818	(uDevFn << 8) \| addr;
819	pci_data_write(pGlobals, 0, val, 4);
820	}
821
822	static void pci_config_writew(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
823	{
824	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
825	(uDevFn << 8) \| (addr & ~3);
826	pci_data_write(pGlobals, addr & 3, val, 2);
827	}
828
829	static void pci_config_writeb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
830	{
831	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
832	(uDevFn << 8) \| (addr & ~3);
833	pci_data_write(pGlobals, addr & 3, val, 1);
834	}
835
836	static uint32_t pci_config_readl(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
837	{
838	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
839	(uDevFn << 8) \| addr;
840	uint32_t u32Val;
841	int rc = pci_data_read(pGlobals, 0, 4, &u32Val);
842	AssertRC(rc);
843	return u32Val;
844	}
845
846	static uint32_t pci_config_readw(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
847	{
848	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
849	(uDevFn << 8) \| (addr & ~3);
850	uint32_t u32Val;
851	int rc = pci_data_read(pGlobals, addr & 3, 2, &u32Val);
852	AssertRC(rc);
853	return u32Val;
854	}
855
856	static uint32_t pci_config_readb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
857	{
858	pGlobals->uConfigReg = 0x80000000 \| (uBus << 16) \|
859	(uDevFn << 8) \| (addr & ~3);
860	uint32_t u32Val;
861	int rc = pci_data_read(pGlobals, addr & 3, 1, &u32Val);
862	AssertRC(rc);
863	return u32Val;
864	}
865
866	/* host irqs corresponding to PCI irqs A-D */
867	static const uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; /* bird: added const */
868
869	static void pci_set_io_region_addr(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int region_num, uint32_t addr)
870	{
871	uint16_t cmd;
872	uint32_t ofs;
873
874	if ( region_num == PCI_ROM_SLOT )
875	ofs = 0x30;
876	else
877	ofs = 0x10 + region_num * 4;
878
879	/* Read memory type first. */
880	uint8_t uRessourceType = pci_config_readb(pGlobals, uBus, uDevFn, ofs);
881
882	/* Read command register. */
883	cmd = pci_config_readw(pGlobals, uBus, uDevFn, PCI_COMMAND);
884	if ( region_num == PCI_ROM_SLOT )
885	cmd \|= 2;
886	else if ((uRessourceType & 0x01) == 1) /* Test if region is I/O space. */
887	cmd \|= 1; /* Enable I/O space access. */
888	else /* The region is MMIO. */
889	cmd \|= 2; /* Enable MMIO access. */
890
891	/* Write address of the device. */
892	pci_config_writel(pGlobals, uBus, uDevFn, ofs, addr);
893
894	/* enable memory mappings */
895	pci_config_writew(pGlobals, uBus, uDevFn, PCI_COMMAND, cmd);
896	}
897
898	static void pci_bios_init_device(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
899	{
900	uint32_t *paddr;
901	int i, pin, pic_irq;
902	uint16_t devclass, vendor_id, device_id;
903
904	devclass = pci_config_readw(pGlobals, uBus, uDevFn, PCI_CLASS_DEVICE);
905	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
906	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
907
908	/* Check if device is present. */
909	if (vendor_id != 0xffff)
910	{
911	switch(devclass)
912	{
913	case 0x0101:
914	if ( (vendor_id == 0x8086)
915	&& (device_id == 0x7010 \|\| device_id == 0x7111 \|\| device_id == 0x269e))
916	{
917	/* PIIX3, PIIX4 or ICH6 IDE */
918	pci_config_writew(pGlobals, uBus, uDevFn, 0x40, 0x8000); /* enable IDE0 */
919	pci_config_writew(pGlobals, uBus, uDevFn, 0x42, 0x8000); /* enable IDE1 */
920	goto default_map;
921	}
922	else
923	{
924	/* IDE: we map it as in ISA mode */
925	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x1f0);
926	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 1, 0x3f4);
927	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 2, 0x170);
928	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 3, 0x374);
929	}
930	break;
931	case 0x0300:
932	if (vendor_id != 0x80ee)
933	goto default_map;
934	/* VGA: map frame buffer to default Bochs VBE address */
935	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0xE0000000);
936	/*
937	* Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
938	* only the framebuffer (i.e., a memory region) is explicitly registered via
939	* pci_set_io_region_addr, so I/O decoding must be enabled manually.
940	*/
941	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
942	pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
943	\| 1 /* Enable I/O space access. */);
944	break;
945	case 0x0800:
946	/* PIC */
947	vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
948	device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
949	if (vendor_id == 0x1014)
950	{
951	/* IBM */
952	if (device_id == 0x0046 \|\| device_id == 0xFFFF)
953	{
954	/* MPIC & MPIC2 */
955	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
956	}
957	}
958	break;
959	case 0xff00:
960	if ( (vendor_id == 0x0106b)
961	&& (device_id == 0x0017 \|\| device_id == 0x0022))
962	{
963	/* macio bridge */
964	pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000);
965	}
966	break;
967	case 0x0604:
968	{
969	/* Init PCI-to-PCI bridge. */
970	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus);
971
972	AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
973	pGlobals->uBus++;
974	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
975	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
976
977	/* Add position of this bridge into the array. */
978	paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
979
980	/*
981	* The I/O range for the bridge must be aligned to a 4KB boundary.
982	* This does not change anything really as the access to the device is not going
983	* through the bridge but we want to be compliant to the spec.
984	*/
985	if ((pGlobals->pci_bios_io_addr % 4096) != 0)
986	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
987	Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_io_addr));
988	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->pci_bios_io_addr >> 8) & 0xf0);
989
990	/* The MMIO range for the bridge must be aligned to a 1MB boundary. */
991	if ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0)
992	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
993	Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_mem_addr));
994	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xffff0));
995
996	/* Save values to compare later to. */
997	uint32_t u32IoAddressBase = pGlobals->pci_bios_io_addr;
998	uint32_t u32MMIOAddressBase = pGlobals->pci_bios_mem_addr;
999
1000	/* Init devices behind the bridge and possibly other bridges as well. */
1001	for (int iDev = 0; iDev <= 255; iDev++)
1002	pci_bios_init_device(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1003
1004	/* The number of bridges behind the this one is now available. */
1005	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1006
1007	/*
1008	* Set I/O limit register. If there is no device with I/O space behind the bridge
1009	* we set a lower value than in the base register.
1010	* The result with a real bridge is that no I/O transactions are passed to the secondary
1011	* interface. Again this doesn't really matter here but we want to be compliant to the spec.
1012	*/
1013	if ((u32IoAddressBase != pGlobals->pci_bios_io_addr) && ((pGlobals->pci_bios_io_addr % 4096) != 0))
1014	{
1015	/* The upper boundary must be one byte less than a 4KB boundary. */
1016	pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
1017	}
1018	pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->pci_bios_io_addr >> 8) & 0xf0) - 1);
1019
1020	/* Same with the MMIO limit register but with 1MB boundary here. */
1021	if ((u32MMIOAddressBase != pGlobals->pci_bios_mem_addr) && ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0))
1022	{
1023	/* The upper boundary must be one byte less than a 1MB boundary. */
1024	pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
1025	}
1026	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xfff0)) - 1);
1027
1028	/*
1029	* Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1030	* which may be behind a bridge. Thatswhy it is unconditionally disabled here atm by writing a higher value into
1031	* the base register than in the limit register.
1032	*/
1033	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
1034	pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
1035	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
1036	pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
1037	break;
1038	}
1039	default:
1040	default_map:
1041	{
1042	/* default memory mappings */
1043	/*
1044	* PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
1045	* Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
1046	*/
1047	for(i = 0; i < (PCI_NUM_REGIONS-1); i++)
1048	{
1049	uint32_t u32Size;
1050	uint8_t u8RessourceType;
1051	uint32_t u32Address = 0x10 + i * 4;
1052
1053	/* Calculate size. */
1054	u8RessourceType = pci_config_readb(pGlobals, uBus, uDevFn, u32Address);
1055	pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff));
1056	u32Size = pci_config_readl(pGlobals, uBus, uDevFn, u32Address);
1057	/* Clear ressource information depending on ressource type. */
1058	if ((u8RessourceType & 0x01) == 1) /* I/O */
1059	u32Size &= ~(0x01);
1060	else /* MMIO */
1061	u32Size &= ~(0x0f);
1062
1063	/*
1064	* Invert all bits and add 1 to get size of the region.
1065	* (From PCI implementation note)
1066	*/
1067	if (((u8RessourceType & 0x01) == 1) && (u32Size & UINT32_C(0xffff0000)) == 0)
1068	u32Size = (~(u32Size \| UINT32_C(0xffff0000))) + 1;
1069	else
1070	u32Size = (~u32Size) + 1;
1071
1072	Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, i, uDevFn, uBus, u32Size));
1073
1074	if (u32Size)
1075	{
1076	if ((u8RessourceType & 0x01) == 1)
1077	paddr = &pGlobals->pci_bios_io_addr;
1078	else
1079	paddr = &pGlobals->pci_bios_mem_addr;
1080	paddr = (paddr + u32Size - 1) & ~(u32Size - 1);
1081	Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, ((u8RessourceType & 0x01) == 1 ? "I/O" : "MMIO"), i, *paddr));
1082	pci_set_io_region_addr(pGlobals, uBus, uDevFn, i, *paddr);
1083	*paddr += u32Size;
1084	Log(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1085	}
1086	}
1087	break;
1088	}
1089	}
1090
1091	/* map the interrupt */
1092	pin = pci_config_readb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_PIN);
1093	if (pin != 0)
1094	{
1095	uint8_t uBridgeDevFn = uDevFn;
1096	pin--;
1097
1098	/* We need to go up to the host bus to see which irq this device will assert there. */
1099	while (cBridgeDepth != 0)
1100	{
1101	/* Get the pin the device would assert on the bridge. */
1102	pin = ((uBridgeDevFn >> 3) + pin) & 3;
1103	uBridgeDevFn = paBridgePositions[cBridgeDepth];
1104	cBridgeDepth--;
1105	}
1106
1107	pin = pci_slot_get_pirq(uDevFn, pin);
1108	pic_irq = pci_irqs[pin];
1109	pci_config_writeb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);
1110	}
1111	}
1112	}
1113
1114	#endif /* IN_RING3 */
1115
1116	/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
1117
1118	/**
1119	* Port I/O Handler for PCI address OUT operations.
1120	*
1121	* @returns VBox status code.
1122	*
1123	* @param pDevIns The device instance.
1124	* @param pvUser User argument - ignored.
1125	* @param uPort Port number used for the IN operation.
1126	* @param u32 The value to output.
1127	* @param cb The value size in bytes.
1128	*/
1129	PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1130	{
1131	Log(("pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1132	NOREF(pvUser);
1133	if (cb == 4)
1134	{
1135	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1136	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
1137	pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
1138	PCI_UNLOCK(pDevIns);
1139	}
1140	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1141	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1142	return VINF_SUCCESS;
1143	}
1144
1145
1146	/**
1147	* Port I/O Handler for PCI address IN operations.
1148	*
1149	* @returns VBox status code.
1150	*
1151	* @param pDevIns The device instance.
1152	* @param pvUser User argument - ignored.
1153	* @param uPort Port number used for the IN operation.
1154	* @param pu32 Where to store the result.
1155	* @param cb Number of bytes read.
1156	*/
1157	PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1158	{
1159	NOREF(pvUser);
1160	if (cb == 4)
1161	{
1162	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1163	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
1164	*pu32 = pThis->uConfigReg;
1165	PCI_UNLOCK(pDevIns);
1166	Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
1167	return VINF_SUCCESS;
1168	}
1169	/* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1170	* Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1171	Log(("pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
1172	return VERR_IOM_IOPORT_UNUSED;
1173	}
1174
1175
1176	/**
1177	* Port I/O Handler for PCI data OUT operations.
1178	*
1179	* @returns VBox status code.
1180	*
1181	* @param pDevIns The device instance.
1182	* @param pvUser User argument - ignored.
1183	* @param uPort Port number used for the IN operation.
1184	* @param u32 The value to output.
1185	* @param cb The value size in bytes.
1186	*/
1187	PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1188	{
1189	Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1190	NOREF(pvUser);
1191	int rc = VINF_SUCCESS;
1192	if (!(Port % cb))
1193	{
1194	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_WRITE);
1195	rc = pci_data_write(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
1196	PCI_UNLOCK(pDevIns);
1197	}
1198	else
1199	AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
1200	return rc;
1201	}
1202
1203
1204	/**
1205	* Port I/O Handler for PCI data IN operations.
1206	*
1207	* @returns VBox status code.
1208	*
1209	* @param pDevIns The device instance.
1210	* @param pvUser User argument - ignored.
1211	* @param uPort Port number used for the IN operation.
1212	* @param pu32 Where to store the result.
1213	* @param cb Number of bytes read.
1214	*/
1215	PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1216	{
1217	NOREF(pvUser);
1218	if (!(Port % cb))
1219	{
1220	PCI_LOCK(pDevIns, VINF_IOM_HC_IOPORT_READ);
1221	int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
1222	PCI_UNLOCK(pDevIns);
1223	Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
1224	return rc;
1225	}
1226	AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
1227	return VERR_IOM_IOPORT_UNUSED;
1228	}
1229
1230	#ifdef IN_RING3
1231
1232	/**
1233	* Saves a state of the PCI device.
1234	*
1235	* @returns VBox status code.
1236	* @param pDevIns Device instance of the PCI Bus.
1237	* @param pPciDev Pointer to PCI device.
1238	* @param pSSM The handle to save the state to.
1239	*/
1240	static DECLCALLBACK(int) pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1241	{
1242	return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1243	}
1244
1245
1246	/**
1247	* Loads a saved PCI device state.
1248	*
1249	* @returns VBox status code.
1250	* @param pDevIns Device instance of the PCI Bus.
1251	* @param pPciDev Pointer to PCI device.
1252	* @param pSSM The handle to the saved state.
1253	*/
1254	static DECLCALLBACK(int) pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1255	{
1256	return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1257	}
1258
1259
1260	/**
1261	* Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
1262	*
1263	* @returns VBox status code.
1264	* @param pBus The bus to save.
1265	* @param pSSM The saved state handle.
1266	*/
1267	static int pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
1268	{
1269	/*
1270	* Iterate thru all the devices.
1271	*/
1272	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1273	{
1274	PPCIDEVICE pDev = pBus->devices[i];
1275	if (pDev)
1276	{
1277	SSMR3PutU32(pSSM, i);
1278	SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1279
1280	int rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1281	if (RT_FAILURE(rc))
1282	return rc;
1283	}
1284	}
1285	return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1286	}
1287
1288
1289	/**
1290	* Saves a state of the PCI device.
1291	*
1292	* @returns VBox status code.
1293	* @param pDevIns The device instance.
1294	* @param pPciDev Pointer to PCI device.
1295	* @param pSSM The handle to save the state to.
1296	*/
1297	static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1298	{
1299	uint32_t i;
1300	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1301
1302	/*
1303	* Bus state data.
1304	*/
1305	SSMR3PutU32(pSSM, pThis->uConfigReg);
1306	SSMR3PutBool(pSSM, pThis->fUseIoApic);
1307
1308	/*
1309	* Save IRQ states.
1310	*/
1311	for (i = 0; i < PCI_IRQ_PINS; i++)
1312	SSMR3PutU32(pSSM, pThis->pci_irq_levels[i]);
1313	for (i = 0; i < PCI_APIC_IRQ_PINS; i++)
1314	SSMR3PutU32(pSSM, pThis->pci_apic_irq_levels[i]);
1315
1316	SSMR3PutU32(pSSM, pThis->acpi_irq_level);
1317	SSMR3PutS32(pSSM, pThis->acpi_irq);
1318
1319	SSMR3PutU32(pSSM, ~0); /* separator */
1320
1321	/*
1322	* Join paths with pcibridgeR3SaveExec.
1323	*/
1324	return pciR3CommonSaveExec(&pThis->PciBus, pSSM);
1325	}
1326
1327
1328	/**
1329	* Common routine for restoring the config registers of a PCI device.
1330	*
1331	* @param pDev The PCI device.
1332	* @param pbSrcConfig The configuration register values to be loaded.
1333	* @param fIsBridge Whether this is a bridge device or not.
1334	*/
1335	static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1336	{
1337	/*
1338	* This table defines the fields for normal devices and bridge devices, and
1339	* the order in which they need to be restored.
1340	*/
1341	static const struct PciField
1342	{
1343	uint8_t off;
1344	uint8_t cb;
1345	uint8_t fWritable;
1346	uint8_t fBridge;
1347	const char *pszName;
1348	} s_aFields[] =
1349	{
1350	/* off,cb,fW,fB, pszName */
1351	{ 0x00, 2, 0, 3, "VENDOR_ID" },
1352	{ 0x02, 2, 0, 3, "DEVICE_ID" },
1353	{ 0x06, 2, 1, 3, "STATUS" },
1354	{ 0x08, 1, 0, 3, "REVISION_ID" },
1355	{ 0x09, 1, 0, 3, "CLASS_PROG" },
1356	{ 0x0a, 1, 0, 3, "CLASS_SUB" },
1357	{ 0x0b, 1, 0, 3, "CLASS_BASE" },
1358	{ 0x0c, 1, 0, 3, "CACHE_LINE_SIZE" }, // fWritable = ??
1359	{ 0x0d, 1, 0, 3, "LATENCY_TIMER" }, // fWritable = ??
1360	{ 0x0e, 1, 0, 3, "HEADER_TYPE" }, // fWritable = ??
1361	{ 0x0f, 1, 0, 3, "BIST" }, // fWritable = ??
1362	{ 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1363	{ 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1364	{ 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1365	{ 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1366	{ 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1367	{ 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1368	{ 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1369	{ 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1370	{ 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1371	{ 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1372	{ 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1373	{ 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1374	{ 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1375	{ 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1376	{ 0x24, 4, 1, 1, "BASE_ADDRESS_4" },
1377	{ 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1378	{ 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1379	{ 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1380	{ 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1381	{ 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1382	{ 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1383	{ 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1384	{ 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1385	{ 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1386	{ 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1387	{ 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1388	{ 0x38, 4, 1, 1, "???" }, // ???
1389	{ 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1390	{ 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1391	{ 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1392	{ 0x3e, 1, 0, 1, "MIN_GNT" }, // fWritable = !?
1393	{ 0x3e, 1, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !? cb=!?
1394	{ 0x3f, 1, 1, 3, "MAX_LAT" }, // fWritable = !? fBridge=!?
1395	/* The COMMAND register must come last as it requires the ADDRESS
1396	registers to be restored before we pretent to change it from 0 to
1397	whatever value the guest assigned it. */
1398	{ 0x04, 2, 1, 3, "COMMAND" },
1399	};
1400
1401	#ifdef RT_STRICT
1402	/* Check that we've got full register coverage. */
1403	uint32_t bmDevice[0x40 / 32];
1404	uint32_t bmBridge[0x40 / 32];
1405	RT_ZERO(bmDevice);
1406	RT_ZERO(bmBridge);
1407	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1408	{
1409	uint8_t off = s_aFields[i].off;
1410	uint8_t cb = s_aFields[i].cb;
1411	uint8_t f = s_aFields[i].fBridge;
1412	while (cb-- > 0)
1413	{
1414	if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1415	if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1416	if (f & 1) ASMBitSet(bmDevice, off);
1417	if (f & 2) ASMBitSet(bmBridge, off);
1418	off++;
1419	}
1420	}
1421	for (uint32_t off = 0; off < 0x40; off++)
1422	{
1423	AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1424	AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1425	}
1426	#endif
1427
1428	/*
1429	* Loop thru the fields covering the 64 bytes of standard registers.
1430	*/
1431	uint8_t const fBridge = fIsBridge ? 2 : 1;
1432	uint8_t *pbDstConfig = &pDev->config[0];
1433	for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1434	if (s_aFields[i].fBridge & fBridge)
1435	{
1436	uint8_t const off = s_aFields[i].off;
1437	uint8_t const cb = s_aFields[i].cb;
1438	uint32_t u32Src;
1439	uint32_t u32Dst;
1440	switch (cb)
1441	{
1442	case 1:
1443	u32Src = pbSrcConfig[off];
1444	u32Dst = pbDstConfig[off];
1445	break;
1446	case 2:
1447	u32Src = (uint16_t const )&pbSrcConfig[off];
1448	u32Dst = (uint16_t const )&pbDstConfig[off];
1449	break;
1450	case 4:
1451	u32Src = (uint32_t const )&pbSrcConfig[off];
1452	u32Dst = (uint32_t const )&pbDstConfig[off];
1453	break;
1454	default:
1455	AssertFailed();
1456	continue;
1457	}
1458
1459	if ( u32Src != u32Dst
1460	\|\| off == VBOX_PCI_COMMAND)
1461	{
1462	if (u32Src != u32Dst)
1463	{
1464	if (!s_aFields[i].fWritable)
1465	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1466	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1467	else
1468	LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1469	pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1470	}
1471	if (off == VBOX_PCI_COMMAND)
1472	PCIDevSetCommand(pDev, 0); /* For remapping, see pciR3CommonLoadExec. */
1473	pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1474	}
1475	}
1476
1477	/*
1478	* The device dependent registers.
1479	*
1480	* We will not use ConfigWrite here as we have no clue about the size
1481	* of the registers, so the device is responsible for correctly
1482	* restoring functionality governed by these registers.
1483	*/
1484	for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1485	if (pbDstConfig[off] != pbSrcConfig[off])
1486	{
1487	LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1488	pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1489	pbDstConfig[off] = pbSrcConfig[off];
1490	}
1491	}
1492
1493
1494	/**
1495	* Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
1496	*
1497	* @returns VBox status code.
1498	* @param pBus The bus which data is being loaded.
1499	* @param pSSM The saved state handle.
1500	* @param uVersion The data version.
1501	* @param uPass The pass.
1502	*/
1503	static DECLCALLBACK(int) pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1504	{
1505	uint32_t u32;
1506	uint32_t i;
1507	int rc;
1508
1509	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1510
1511	/*
1512	* Iterate thru all the devices and write 0 to the COMMAND register so
1513	* that all the memory is unmapped before we start restoring the saved
1514	* mapping locations.
1515	*
1516	* The register value is restored afterwards so we can do proper
1517	* LogRels in pciR3CommonRestoreConfig.
1518	*/
1519	for (i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1520	{
1521	PPCIDEVICE pDev = pBus->devices[i];
1522	if (pDev)
1523	{
1524	uint16_t u16 = PCIDevGetCommand(pDev);
1525	pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1526	PCIDevSetCommand(pDev, u16);
1527	Assert(PCIDevGetCommand(pDev) == u16);
1528	}
1529	}
1530
1531	/*
1532	* Iterate all the devices.
1533	*/
1534	for (i = 0;; i++)
1535	{
1536	PCIDEVICE DevTmp;
1537	PPCIDEVICE pDev;
1538
1539	/* index / terminator */
1540	rc = SSMR3GetU32(pSSM, &u32);
1541	if (RT_FAILURE(rc))
1542	return rc;
1543	if (u32 == (uint32_t)~0)
1544	break;
1545	if ( u32 >= RT_ELEMENTS(pBus->devices)
1546	\|\| u32 < i)
1547	{
1548	AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1549	return rc;
1550	}
1551
1552	/* skip forward to the device checking that no new devices are present. */
1553	for (; i < u32; i++)
1554	{
1555	if (pBus->devices[i])
1556	{
1557	LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pBus->devices[i]->name,
1558	PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i])));
1559	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1560	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1561	i, pBus->devices[i]->name, PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i]));
1562	}
1563	}
1564
1565	/* get the data */
1566	DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1567	SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1568	if (uVersion < 3)
1569	{
1570	int32_t i32Temp;
1571	/* Irq value not needed anymore. */
1572	rc = SSMR3GetS32(pSSM, &i32Temp);
1573	if (RT_FAILURE(rc))
1574	return rc;
1575	}
1576	else
1577	{
1578	rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1579	if (RT_FAILURE(rc))
1580	return rc;
1581	}
1582
1583	/* check that it's still around. */
1584	pDev = pBus->devices[i];
1585	if (!pDev)
1586	{
1587	LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1588	PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1589	if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1590	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1591	i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1592	continue;
1593	}
1594
1595	/* match the vendor id assuming that this will never be changed. */
1596	if ( DevTmp.config[0] != pDev->config[0]
1597	\|\| DevTmp.config[1] != pDev->config[1])
1598	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1599	i, pDev->name, DevTmp.config, pDev->config);
1600
1601	/* commit the loaded device config. */
1602	pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1603
1604	pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1605	}
1606
1607	return VINF_SUCCESS;
1608	}
1609
1610
1611	/**
1612	* Loads a saved PCI device state.
1613	*
1614	* @returns VBox status code.
1615	* @param pDevIns The device instance.
1616	* @param pSSM The handle to the saved state.
1617	* @param uVersion The data unit version number.
1618	* @param uPass The data pass.
1619	*/
1620	static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1621	{
1622	PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1623	PPCIBUS pBus = &pThis->PciBus;
1624	uint32_t u32;
1625	int rc;
1626
1627	/*
1628	* Check the version.
1629	*/
1630	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1631	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1632	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1633
1634	/*
1635	* Bus state data.
1636	*/
1637	SSMR3GetU32(pSSM, &pThis->uConfigReg);
1638	if (uVersion > 1)
1639	SSMR3GetBool(pSSM, &pThis->fUseIoApic);
1640
1641	/* Load IRQ states. */
1642	if (uVersion > 2)
1643	{
1644	for (uint8_t i = 0; i < PCI_IRQ_PINS; i++)
1645	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_irq_levels[i]);
1646	for (uint8_t i = 0; i < PCI_APIC_IRQ_PINS; i++)
1647	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_apic_irq_levels[i]);
1648
1649	SSMR3GetU32(pSSM, &pThis->acpi_irq_level);
1650	SSMR3GetS32(pSSM, &pThis->acpi_irq);
1651	}
1652
1653	/* separator */
1654	rc = SSMR3GetU32(pSSM, &u32);
1655	if (RT_FAILURE(rc))
1656	return rc;
1657	if (u32 != (uint32_t)~0)
1658	AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1659
1660	/*
1661	* The devices.
1662	*/
1663	return pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1664	}
1665
1666
1667	/* -=-=-=-=-=- real code -=-=-=-=-=- */
1668
1669	/**
1670	* Registers the device with the specified PCI bus.
1671	*
1672	* @returns VBox status code.
1673	* @param pBus The bus to register with.
1674	* @param iDev The PCI device ordinal.
1675	* @param pPciDev The PCI device structure.
1676	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1677	*/
1678	static int pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1679	{
1680	/*
1681	* Find device slot.
1682	*/
1683	if (iDev < 0)
1684	{
1685	/*
1686	* Special check for the IDE controller which is our function 1 device
1687	* before searching.
1688	*/
1689	if ( !strcmp(pszName, "piix3ide")
1690	&& !pBus->devices[9])
1691	iDev = 9;
1692	/* LPC bus expected to be there by some guests, better make an additional argument to PDM
1693	device helpers, but requires significant rewrite */
1694	else if (!strcmp(pszName, "lpc")
1695	&& !pBus->devices[0xf8])
1696	iDev = 0xf8;
1697	else
1698	{
1699	Assert(!(pBus->iDevSearch % 8));
1700	for (iDev = pBus->iDevSearch; iDev < (int)RT_ELEMENTS(pBus->devices); iDev += 8)
1701	if ( !pBus->devices[iDev]
1702	&& !pBus->devices[iDev + 1]
1703	&& !pBus->devices[iDev + 2]
1704	&& !pBus->devices[iDev + 3]
1705	&& !pBus->devices[iDev + 4]
1706	&& !pBus->devices[iDev + 5]
1707	&& !pBus->devices[iDev + 6]
1708	&& !pBus->devices[iDev + 7])
1709	break;
1710	if (iDev >= (int)RT_ELEMENTS(pBus->devices))
1711	{
1712	AssertMsgFailed(("Couldn't find free spot!\n"));
1713	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1714	}
1715	}
1716	pPciDev->Int.s.fRequestedDevFn = false;
1717	}
1718	else
1719	{
1720	/*
1721	* An explicit request.
1722	*
1723	* If the slot is occupied we'll have to relocate the device
1724	* currently occupying it first. This can only be done if the
1725	* existing device wasn't explicitly assigned. Also we limit
1726	* ourselves to function 0 devices.
1727	*
1728	* If you start setting devices + function in the
1729	* config, do it for all pci devices!
1730	*/
1731	//AssertReleaseMsg(iDev > 8 \|\| pBus->iBus != 0, ("iDev=%d pszName=%s\n", iDev, pszName));
1732	if (pBus->devices[iDev])
1733	{
1734	int iDevRel;
1735	AssertReleaseMsg(!(iDev % 8), ("PCI Configuration Conflict! iDev=%d pszName=%s clashes with %s\n",
1736	iDev, pszName, pBus->devices[iDev]->name));
1737	if ( pBus->devices[iDev]->Int.s.fRequestedDevFn
1738	\|\| (pBus->devices[iDev + 1] && pBus->devices[iDev + 1]->Int.s.fRequestedDevFn)
1739	\|\| (pBus->devices[iDev + 2] && pBus->devices[iDev + 2]->Int.s.fRequestedDevFn)
1740	\|\| (pBus->devices[iDev + 3] && pBus->devices[iDev + 3]->Int.s.fRequestedDevFn)
1741	\|\| (pBus->devices[iDev + 4] && pBus->devices[iDev + 4]->Int.s.fRequestedDevFn)
1742	\|\| (pBus->devices[iDev + 5] && pBus->devices[iDev + 5]->Int.s.fRequestedDevFn)
1743	\|\| (pBus->devices[iDev + 6] && pBus->devices[iDev + 6]->Int.s.fRequestedDevFn)
1744	\|\| (pBus->devices[iDev + 7] && pBus->devices[iDev + 7]->Int.s.fRequestedDevFn))
1745	{
1746	AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1747	pszName, pBus->devices[iDev]->name, iDev));
1748	return VERR_INTERNAL_ERROR;
1749	}
1750
1751	/* Find free slot for the device(s) we're moving and move them. */
1752	for (iDevRel = pBus->iDevSearch; iDevRel < (int)RT_ELEMENTS(pBus->devices); iDevRel += 8)
1753	{
1754	if ( !pBus->devices[iDevRel]
1755	&& !pBus->devices[iDevRel + 1]
1756	&& !pBus->devices[iDevRel + 2]
1757	&& !pBus->devices[iDevRel + 3]
1758	&& !pBus->devices[iDevRel + 4]
1759	&& !pBus->devices[iDevRel + 5]
1760	&& !pBus->devices[iDevRel + 6]
1761	&& !pBus->devices[iDevRel + 7])
1762	{
1763	int i = 0;
1764	for (i = 0; i < 8; i++)
1765	{
1766	if (!pBus->devices[iDev + i])
1767	continue;
1768	Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->devices[iDev + i]->name, iDev + i, iDevRel + i));
1769	pBus->devices[iDevRel + i] = pBus->devices[iDev + i];
1770	pBus->devices[iDevRel + i]->devfn = i;
1771	pBus->devices[iDev + i] = NULL;
1772	}
1773	}
1774	}
1775	if (pBus->devices[iDev])
1776	{
1777	AssertMsgFailed(("Couldn't find free spot!\n"));
1778	return VERR_PDM_TOO_PCI_MANY_DEVICES;
1779	}
1780	} /* if conflict */
1781	pPciDev->Int.s.fRequestedDevFn = true;
1782	}
1783
1784	Assert(!pBus->devices[iDev]);
1785	pPciDev->devfn = iDev;
1786	pPciDev->name = pszName;
1787	pPciDev->Int.s.pBusR3 = pBus;
1788	pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1789	pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1790	pPciDev->Int.s.pfnConfigRead = pci_default_read_config;
1791	pPciDev->Int.s.pfnConfigWrite = pci_default_write_config;
1792	pBus->devices[iDev] = pPciDev;
1793	if (pPciDev->Int.s.fPciToPciBridge)
1794	{
1795	AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->devices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
1796	AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
1797	("device is a bridge but does not implement read/write functions\n"));
1798	pBus->papBridgesR3[pBus->cBridges] = pPciDev;
1799	pBus->cBridges++;
1800	}
1801
1802	Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
1803	iDev >> 3, iDev & 7, 0x80000000 \| (iDev << 8), pszName));
1804
1805	return VINF_SUCCESS;
1806	}
1807
1808
1809	/**
1810	* Registers the device with the default PCI bus.
1811	*
1812	* @returns VBox status code.
1813	* @param pDevIns Device instance of the PCI Bus.
1814	* @param pPciDev The PCI device structure.
1815	* Any PCI enabled device must keep this in it's instance data!
1816	* Fill in the PCI data config before registration, please.
1817	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1818	* @param iDev The PCI device number. Use a negative value for auto assigning one.
1819	*/
1820	static DECLCALLBACK(int) pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
1821	{
1822	PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
1823
1824	/*
1825	* Check input.
1826	*/
1827	if ( !pszName
1828	\|\| !pPciDev
1829	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices)
1830	\|\| (iDev >= 0 && iDev <= 8))
1831	{
1832	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1833	return VERR_INVALID_PARAMETER;
1834	}
1835
1836	/*
1837	* Register the device.
1838	*/
1839	return pciRegisterInternal(pBus, iDev, pPciDev, pszName);
1840	}
1841
1842
1843	static DECLCALLBACK(int) pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1844	{
1845	/*
1846	* Validate.
1847	*/
1848	AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
1849	\|\| enmType == PCI_ADDRESS_SPACE_IO
1850	\|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
1851	("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
1852	VERR_INVALID_PARAMETER);
1853	AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
1854	("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
1855	VERR_INVALID_PARAMETER);
1856	int iLastSet = ASMBitLastSetU32(cbRegion);
1857	AssertMsgReturn( iLastSet != 0
1858	&& RT_BIT_32(iLastSet - 1) == cbRegion,
1859	("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1860	VERR_INVALID_PARAMETER);
1861
1862	/*
1863	* Register the I/O region.
1864	*/
1865	PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1866	pRegion->addr = ~0U;
1867	pRegion->size = cbRegion;
1868	pRegion->type = enmType;
1869	pRegion->map_func = pfnCallback;
1870
1871	/* Set type in the config space. */
1872	uint32_t u32Address = 0x10 + iRegion * 4;
1873	uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
1874	\| (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
1875	(uint32_t )(pPciDev->config + u32Address) = RT_H2LE_U32(u32Value);
1876
1877	return VINF_SUCCESS;
1878	}
1879
1880
1881	/**
1882	* @copydoc PDMPCIBUSREG::pfnSetConfigCallbacksR3
1883	*/
1884	static DECLCALLBACK(void) pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1885	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1886	{
1887	if (ppfnReadOld)
1888	*ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1889	pPciDev->Int.s.pfnConfigRead = pfnRead;
1890
1891	if (ppfnWriteOld)
1892	*ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1893	pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1894	}
1895
1896
1897	/**
1898	* Called to perform the job of the bios.
1899	*
1900	* @returns VBox status.
1901	* @param pDevIns Device instance of the first bus.
1902	*/
1903	static DECLCALLBACK(int) pciFakePCIBIOS(PPDMDEVINS pDevIns)
1904	{
1905	unsigned i;
1906	uint8_t elcr[2] = {0, 0};
1907	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1908	PVM pVM = PDMDevHlpGetVM(pDevIns);
1909	Assert(pVM);
1910
1911	/*
1912	* Set the start addresses.
1913	*/
1914	pGlobals->pci_bios_io_addr = 0xd000;
1915	pGlobals->pci_bios_mem_addr = UINT32_C(0xf0000000);
1916	pGlobals->uBus = 0;
1917
1918	/*
1919	* Activate IRQ mappings.
1920	*/
1921	for (i = 0; i < 4; i++)
1922	{
1923	uint8_t irq = pci_irqs[i];
1924	/* Set to trigger level. */
1925	elcr[irq >> 3] \|= (1 << (irq & 7));
1926	/* Activate irq remapping in PIIX3. */
1927	pci_config_writeb(pGlobals, 0, pGlobals->PIIX3State.dev.devfn, 0x60 + i, irq);
1928	}
1929
1930	/* Tell to the PIC. */
1931	VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, 0x4d0, elcr[0], sizeof(uint8_t));
1932	if (rcStrict == VINF_SUCCESS)
1933	rcStrict = IOMIOPortWrite(pVM, 0x4d1, elcr[1], sizeof(uint8_t));
1934	if (rcStrict != VINF_SUCCESS)
1935	{
1936	AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1937	return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
1938	}
1939
1940	/*
1941	* Init the devices.
1942	*/
1943	for (i = 0; i < 256; i++)
1944	{
1945	uint8_t aBridgePositions[256];
1946
1947	memset(aBridgePositions, 0, sizeof(aBridgePositions));
1948	Log2(("PCI: Initializing device %d (%#x)\n",
1949	i, 0x80000000 \| (i << 8)));
1950	pci_bios_init_device(pGlobals, 0, i, 0, aBridgePositions);
1951	}
1952
1953	return VINF_SUCCESS;
1954	}
1955
1956	/**
1957	* @copydoc FNPDMDEVRELOCATE
1958	*/
1959	static DECLCALLBACK(void) pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1960	{
1961	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1962	PPCIBUS pBus = &pGlobals->PciBus;
1963	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1964
1965	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
1966	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1967
1968	/* Relocate RC pointers for the attached pci devices. */
1969	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1970	{
1971	if (pBus->devices[i])
1972	pBus->devices[i]->Int.s.pBusRC += offDelta;
1973	}
1974	}
1975
1976
1977	/**
1978	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1979	*/
1980	static DECLCALLBACK(int) pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1981	{
1982	int rc;
1983	Assert(iInstance == 0);
1984
1985	/*
1986	* Validate and read configuration.
1987	*/
1988	if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
1989	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1990
1991	/* query whether we got an IOAPIC */
1992	bool fUseIoApic;
1993	rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
1994	if (RT_FAILURE(rc))
1995	return PDMDEV_SET_ERROR(pDevIns, rc,
1996	N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
1997
1998	/* check if RC code is enabled. */
1999	bool fGCEnabled;
2000	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2001	if (RT_FAILURE(rc))
2002	return PDMDEV_SET_ERROR(pDevIns, rc,
2003	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2004
2005	/* check if R0 code is enabled. */
2006	bool fR0Enabled;
2007	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2008	if (RT_FAILURE(rc))
2009	return PDMDEV_SET_ERROR(pDevIns, rc,
2010	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2011	Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2012
2013	/*
2014	* Init data and register the PCI bus.
2015	*/
2016	PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2017	pGlobals->pci_bios_io_addr = 0xc000;
2018	pGlobals->pci_bios_mem_addr = 0xf0000000;
2019	memset((void *)&pGlobals->pci_irq_levels, 0, sizeof(pGlobals->pci_irq_levels));
2020	pGlobals->fUseIoApic = fUseIoApic;
2021	memset((void *)&pGlobals->pci_apic_irq_levels, 0, sizeof(pGlobals->pci_apic_irq_levels));
2022
2023	pGlobals->pDevInsR3 = pDevIns;
2024	pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2025	pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2026
2027	pGlobals->PciBus.pDevInsR3 = pDevIns;
2028	pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2029	pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2030	pGlobals->PciBus.papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pGlobals->PciBus.devices));
2031
2032	PDMPCIBUSREG PciBusReg;
2033	PPCIBUS pBus = &pGlobals->PciBus;
2034	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2035	PciBusReg.pfnRegisterR3 = pciRegister;
2036	PciBusReg.pfnIORegionRegisterR3 = pciIORegionRegister;
2037	PciBusReg.pfnSetConfigCallbacksR3 = pciSetConfigCallbacks;
2038	PciBusReg.pfnSetIrqR3 = pciSetIrq;
2039	PciBusReg.pfnSaveExecR3 = pciGenericSaveExec;
2040	PciBusReg.pfnLoadExecR3 = pciGenericLoadExec;
2041	PciBusReg.pfnFakePCIBIOSR3 = pciFakePCIBIOS;
2042	PciBusReg.pszSetIrqRC = fGCEnabled ? "pciSetIrq" : NULL;
2043	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
2044	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2045	if (RT_FAILURE(rc))
2046	return PDMDEV_SET_ERROR(pDevIns, rc,
2047	N_("Failed to register ourselves as a PCI Bus"));
2048	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2049	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2050	N_("PCI helper version mismatch; got %#x expected %#x"),
2051	pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION);
2052
2053	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2054	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2055
2056	/*
2057	* Fill in PCI configs and add them to the bus.
2058	*/
2059	/* i440FX */
2060	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2061	PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
2062	PCIDevSetRevisionId(&pBus->PciDev, 0x02);
2063	PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
2064	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2065	PCIDevSetHeaderType(&pBus->PciDev, 0x00);
2066
2067	pBus->PciDev.pDevIns = pDevIns;
2068	pBus->PciDev.Int.s.fRequestedDevFn= true;
2069	pciRegisterInternal(pBus, 0, &pBus->PciDev, "i440FX");
2070
2071	/* PIIX3 */
2072	PCIDevSetVendorId( &pGlobals->PIIX3State.dev, 0x8086); /* Intel */
2073	PCIDevSetDeviceId( &pGlobals->PIIX3State.dev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
2074	PCIDevSetClassSub( &pGlobals->PIIX3State.dev, 0x01); /* PCI_ISA */
2075	PCIDevSetClassBase( &pGlobals->PIIX3State.dev, 0x06); /* PCI_bridge */
2076	PCIDevSetHeaderType(&pGlobals->PIIX3State.dev, 0x80); /* PCI_multifunction, generic */
2077
2078	pGlobals->PIIX3State.dev.pDevIns = pDevIns;
2079	pGlobals->PIIX3State.dev.Int.s.fRequestedDevFn= true;
2080	pciRegisterInternal(pBus, 8, &pGlobals->PIIX3State.dev, "PIIX3");
2081	piix3_reset(&pGlobals->PIIX3State);
2082
2083	pBus->iDevSearch = 16;
2084
2085	/*
2086	* Register I/O ports and save state.
2087	*/
2088	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
2089	if (RT_FAILURE(rc))
2090	return rc;
2091	rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
2092	if (RT_FAILURE(rc))
2093	return rc;
2094	if (fGCEnabled)
2095	{
2096	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2097	if (RT_FAILURE(rc))
2098	return rc;
2099	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2100	if (RT_FAILURE(rc))
2101	return rc;
2102	}
2103	if (fR0Enabled)
2104	{
2105	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2106	if (RT_FAILURE(rc))
2107	return rc;
2108	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2109	if (RT_FAILURE(rc))
2110	return rc;
2111	}
2112
2113	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2114	NULL, NULL, NULL,
2115	NULL, pciR3SaveExec, NULL,
2116	NULL, pciR3LoadExec, NULL);
2117	if (RT_FAILURE(rc))
2118	return rc;
2119
2120	return VINF_SUCCESS;
2121	}
2122
2123
2124	/**
2125	* The device registration structure.
2126	*/
2127	const PDMDEVREG g_DevicePCI =
2128	{
2129	/* u32Version */
2130	PDM_DEVREG_VERSION,
2131	/* szName */
2132	"pci",
2133	/* szRCMod */
2134	"VBoxDDGC.gc",
2135	/* szR0Mod */
2136	"VBoxDDR0.r0",
2137	/* pszDescription */
2138	"i440FX PCI bridge and PIIX3 ISA bridge.",
2139	/* fFlags */
2140	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2141	/* fClass */
2142	PDM_DEVREG_CLASS_BUS_PCI \| PDM_DEVREG_CLASS_BUS_ISA,
2143	/* cMaxInstances */
2144	1,
2145	/* cbInstance */
2146	sizeof(PCIGLOBALS),
2147	/* pfnConstruct */
2148	pciConstruct,
2149	/* pfnDestruct */
2150	NULL,
2151	/* pfnRelocate */
2152	pciRelocate,
2153	/* pfnIOCtl */
2154	NULL,
2155	/* pfnPowerOn */
2156	NULL,
2157	/* pfnReset */
2158	NULL,
2159	/* pfnSuspend */
2160	NULL,
2161	/* pfnResume */
2162	NULL,
2163	/* pfnAttach */
2164	NULL,
2165	/* pfnDetach */
2166	NULL,
2167	/* pfnQueryInterface */
2168	NULL,
2169	/* pfnInitComplete */
2170	NULL,
2171	/* pfnPowerOff */
2172	NULL,
2173	/* pfnSoftReset */
2174	NULL,
2175	/* u32VersionEnd */
2176	PDM_DEVREG_VERSION
2177
2178	};
2179	#endif /* IN_RING3 */
2180
2181
2182	/**
2183	* Set the IRQ for a PCI device on a secondary bus.
2184	*
2185	* @param pDevIns Device instance of the PCI Bus.
2186	* @param pPciDev The PCI device structure.
2187	* @param iIrq IRQ number to set.
2188	* @param iLevel IRQ level.
2189	*/
2190	PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel)
2191	{
2192	/*
2193	* The PCI-to-PCI bridge specification defines how the interrupt pins
2194	* are routed from the secondary to the primary bus (see chapter 9).
2195	* iIrq gives the interrupt pin the pci device asserted.
2196	* We change iIrq here according to the spec and call the SetIrq function
2197	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
2198	*/
2199	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2200	PPCIDEVICE pPciDevBus = pPciDev;
2201	int iIrqPinBridge = iIrq;
2202	uint8_t uDevFnBridge = 0;
2203
2204	/* Walk the chain until we reach the host bus. */
2205	do
2206	{
2207	uDevFnBridge = pBus->PciDev.devfn;
2208	iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
2209
2210	/* Get the parent. */
2211	pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
2212	pPciDevBus = &pBus->PciDev;
2213	} while (pBus->iBus != 0);
2214
2215	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
2216	pciSetIrqInternal(PCIBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel);
2217	}
2218
2219	#ifdef IN_RING3
2220
2221	static void pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
2222	{
2223	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2224
2225	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
2226
2227	/* If the current bus is not the target bus search for the bus which contains the device. */
2228	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2229	{
2230	PPCIDEVICE pBridgeDevice = pciFindBridge(pBus, iBus);
2231	if (pBridgeDevice)
2232	{
2233	AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
2234	pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
2235	}
2236	}
2237	else
2238	{
2239	/* This is the target bus, pass the write to the device. */
2240	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2241	if (pPciDev)
2242	{
2243	Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2244	pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
2245	}
2246	}
2247	}
2248
2249	static uint32_t pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
2250	{
2251	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2252	uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
2253
2254	LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
2255
2256	/* If the current bus is not the target bus search for the bus which contains the device. */
2257	if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2258	{
2259	PPCIDEVICE pBridgeDevice = pciFindBridge(pBus, iBus);
2260	if (pBridgeDevice)
2261	{
2262	AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
2263	u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
2264	}
2265	}
2266	else
2267	{
2268	/* This is the target bus, pass the read to the device. */
2269	PPCIDEVICE pPciDev = pBus->devices[iDevice];
2270	if (pPciDev)
2271	{
2272	u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
2273	Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2274	}
2275	}
2276
2277	return u32Value;
2278	}
2279
2280
2281	/**
2282	* @copydoc FNSSMDEVSAVEEXEC
2283	*/
2284	static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2285	{
2286	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2287	return pciR3CommonSaveExec(pThis, pSSM);
2288	}
2289
2290
2291	/**
2292	* @copydoc FNSSMDEVLOADEXEC
2293	*/
2294	static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2295	{
2296	PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2297	if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
2298	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2299	return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
2300	}
2301
2302
2303	/**
2304	* Registers the device with the default PCI bus.
2305	*
2306	* @returns VBox status code.
2307	* @param pDevIns Device instance of the PCI Bus.
2308	* @param pPciDev The PCI device structure.
2309	* Any PCI enabled device must keep this in it's instance data!
2310	* Fill in the PCI data config before registration, please.
2311	* @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
2312	* @param iDev The PCI device number. Use a negative value for auto assigning one.
2313	*/
2314	static DECLCALLBACK(int) pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
2315	{
2316	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2317
2318	/*
2319	* Check input.
2320	*/
2321	if ( !pszName
2322	\|\| !pPciDev
2323	\|\| iDev >= (int)RT_ELEMENTS(pBus->devices))
2324	{
2325	AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
2326	return VERR_INVALID_PARAMETER;
2327	}
2328
2329	/*
2330	* Register the device.
2331	*/
2332	return pciRegisterInternal(pBus, iDev, pPciDev, pszName);
2333	}
2334
2335
2336	/**
2337	* @copydoc FNPDMDEVRESET
2338	*/
2339	static DECLCALLBACK(void) pcibridgeReset(PPDMDEVINS pDevIns)
2340	{
2341	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2342
2343	/* Reset config space to default values. */
2344	pBus->PciDev.config[VBOX_PCI_PRIMARY_BUS] = 0;
2345	pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS] = 0;
2346	pBus->PciDev.config[VBOX_PCI_SUBORDINATE_BUS] = 0;
2347	}
2348
2349
2350	/**
2351	* @copydoc FNPDMDEVRELOCATE
2352	*/
2353	static DECLCALLBACK(void) pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2354	{
2355	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2356	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2357
2358	/* Relocate RC pointers for the attached pci devices. */
2359	for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2360	{
2361	if (pBus->devices[i])
2362	pBus->devices[i]->Int.s.pBusRC += offDelta;
2363	}
2364	}
2365
2366
2367	/**
2368	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2369	*/
2370	static DECLCALLBACK(int) pcibridgeConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2371	{
2372	int rc;
2373
2374	/*
2375	* Validate and read configuration.
2376	*/
2377	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2378	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2379
2380	/* check if RC code is enabled. */
2381	bool fGCEnabled;
2382	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2383	if (RT_FAILURE(rc))
2384	return PDMDEV_SET_ERROR(pDevIns, rc,
2385	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2386
2387	/* check if R0 code is enabled. */
2388	bool fR0Enabled;
2389	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2390	if (RT_FAILURE(rc))
2391	return PDMDEV_SET_ERROR(pDevIns, rc,
2392	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2393	Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2394
2395	/*
2396	* Init data and register the PCI bus.
2397	*/
2398	PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2399	pBus->pDevInsR3 = pDevIns;
2400	pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2401	pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2402	pBus->papBridgesR3 = (PPCIDEVICE )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) RT_ELEMENTS(pBus->devices));
2403
2404	PDMPCIBUSREG PciBusReg;
2405	PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2406	PciBusReg.pfnRegisterR3 = pcibridgeRegister;
2407	PciBusReg.pfnIORegionRegisterR3 = pciIORegionRegister;
2408	PciBusReg.pfnSetConfigCallbacksR3 = pciSetConfigCallbacks;
2409	PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
2410	PciBusReg.pfnSaveExecR3 = pciGenericSaveExec;
2411	PciBusReg.pfnLoadExecR3 = pciGenericLoadExec;
2412	PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2413	PciBusReg.pszSetIrqRC = fGCEnabled ? "pcibridgeSetIrq" : NULL;
2414	PciBusReg.pszSetIrqR0 = fR0Enabled ? "pcibridgeSetIrq" : NULL;
2415	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2416	if (RT_FAILURE(rc))
2417	return PDMDEV_SET_ERROR(pDevIns, rc,
2418	N_("Failed to register ourselves as a PCI Bus"));
2419	if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2420	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2421	N_("PCI helper version mismatch; got %#x expected %#x"),
2422	pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2423
2424	pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2425	pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2426
2427	/*
2428	* Fill in PCI configs and add them to the bus.
2429	*/
2430	PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2431	PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2432	PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
2433	PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
2434	PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2435	PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
2436	PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2437	PCIDevSetCommand( &pBus->PciDev, 0x00);
2438	PCIDevSetStatus( &pBus->PciDev, 0x20); /* 66MHz Capable. */
2439	PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
2440
2441	/*
2442	* This device does not generate interrupts. Interrupt delivery from
2443	* devices attached to the bus is unaffected.
2444	*/
2445	PCIDevSetInterruptPin (&pBus->PciDev, 0x00);
2446
2447	pBus->PciDev.pDevIns = pDevIns;
2448	pBus->PciDev.Int.s.fPciToPciBridge = true;
2449	pBus->PciDev.Int.s.pfnBridgeConfigRead = pcibridgeConfigRead;
2450	pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeConfigWrite;
2451
2452	/*
2453	* Register this PCI bridge. The called function will take care on which bus we will get registered.
2454	*/
2455	rc = PDMDevHlpPCIRegister (pDevIns, &pBus->PciDev);
2456	if (RT_FAILURE(rc))
2457	return rc;
2458
2459	pBus->iDevSearch = 0;
2460	/*
2461	* The iBus property doesn't really represent the bus number
2462	* because the guest and the BIOS can choose different bus numbers
2463	* for them.
2464	* The bus number is mainly for the setIrq function to indicate
2465	* when the host bus is reached which will have iBus = 0.
2466	* Thathswhy the + 1.
2467	*/
2468	pBus->iBus = iInstance + 1;
2469
2470	/*
2471	* Register SSM handlers. We use the same saved state version as for the host bridge
2472	* to make changes easier.
2473	*/
2474	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(pBus) + 16128, "pgm",
2475	NULL, NULL, NULL,
2476	NULL, pcibridgeR3SaveExec, NULL,
2477	NULL, pcibridgeR3LoadExec, NULL);
2478	if (RT_FAILURE(rc))
2479	return rc;
2480
2481	return VINF_SUCCESS;
2482	}
2483
2484
2485	/**
2486	* The device registration structure
2487	* for the PCI-to-PCI bridge.
2488	*/
2489	const PDMDEVREG g_DevicePCIBridge =
2490	{
2491	/* u32Version */
2492	PDM_DEVREG_VERSION,
2493	/* szName */
2494	"pcibridge",
2495	/* szRCMod */
2496	"VBoxDDGC.gc",
2497	/* szR0Mod */
2498	"VBoxDDR0.r0",
2499	/* pszDescription */
2500	"82801 Mobile PCI to PCI bridge",
2501	/* fFlags */
2502	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2503	/* fClass */
2504	PDM_DEVREG_CLASS_BUS_PCI,
2505	/* cMaxInstances */
2506	~0,
2507	/* cbInstance */
2508	sizeof(PCIBUS),
2509	/* pfnConstruct */
2510	pcibridgeConstruct,
2511	/* pfnDestruct */
2512	NULL,
2513	/* pfnRelocate */
2514	pcibridgeRelocate,
2515	/* pfnIOCtl */
2516	NULL,
2517	/* pfnPowerOn */
2518	NULL,
2519	/* pfnReset */
2520	pcibridgeReset,
2521	/* pfnSuspend */
2522	NULL,
2523	/* pfnResume */
2524	NULL,
2525	/* pfnAttach */
2526	NULL,
2527	/* pfnDetach */
2528	NULL,
2529	/* pfnQueryInterface */
2530	NULL,
2531	/* pfnInitComplete */
2532	NULL,
2533	/* pfnPowerOff */
2534	NULL,
2535	/* pfnSoftReset */
2536	NULL,
2537	/* u32VersionEnd */
2538	PDM_DEVREG_VERSION
2539	};
2540
2541	#endif /* IN_RING3 */
2542	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 30714

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