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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 94800

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1/* $Id: DevIommuAmd.cpp 93115 2022-01-01 11:31:46Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26
27#include <iprt/x86.h>
28#include <iprt/string.h>
29#include <iprt/avl.h>
30#ifdef IN_RING3
31# include <iprt/mem.h>
32#endif
33
34#include "VBoxDD.h"
35#include "DevIommuAmd.h"
36
37
38/*********************************************************************************************************************************
39* Defined Constants And Macros *
40*********************************************************************************************************************************/
41/** Release log prefix string. */
42#define IOMMU_LOG_PFX "AMD-IOMMU"
43/** The current saved state version. */
44#define IOMMU_SAVED_STATE_VERSION 1
45/** The IOMMU device instance magic. */
46#define IOMMU_MAGIC 0x10acce55
47
48/** Enable the IOTLBE cache only in ring-3 for now, see @bugref{9654#c95}. */
49#ifdef IN_RING3
50# define IOMMU_WITH_IOTLBE_CACHE
51#endif
52/** Enable the interrupt cache. */
53#define IOMMU_WITH_IRTE_CACHE
54
55/* The DTE cache is mandatory for the IOTLB or interrupt cache to work. */
56#if defined(IOMMU_WITH_IOTLBE_CACHE) || defined(IOMMU_WITH_IRTE_CACHE)
57# define IOMMU_WITH_DTE_CACHE
58/** The maximum number of device IDs in the cache. */
59# define IOMMU_DEV_CACHE_COUNT 16
60/** An empty device ID. */
61# define IOMMU_DTE_CACHE_KEY_NIL 0
62#endif
63
64#ifdef IOMMU_WITH_IRTE_CACHE
65/** The maximum number of IRTE cache entries. */
66# define IOMMU_IRTE_CACHE_COUNT 32
67/** A NIL IRTE cache entry key. */
68# define IOMMU_IRTE_CACHE_KEY_NIL (~(uint32_t)0U)
69/** Gets the device ID from an IRTE cache entry key. */
70#define IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(a_Key) RT_HIWORD(a_Key)
71/** Gets the IOVA from the IOTLB entry key. */
72# define IOMMU_IRTE_CACHE_KEY_GET_OFF(a_Key) RT_LOWORD(a_Key)
73/** Makes an IRTE cache entry key.
74 *
75 * Bits 31:16 is the device ID (Bus, Device, Function).
76 * Bits 15:0 is the the offset into the IRTE table.
77 */
78# define IOMMU_IRTE_CACHE_KEY_MAKE(a_DevId, a_off) RT_MAKE_U32(a_off, a_DevId)
79#endif /* IOMMU_WITH_IRTE_CACHE */
80
81#ifdef IOMMU_WITH_IOTLBE_CACHE
82/** The maximum number of IOTLB entries. */
83# define IOMMU_IOTLBE_MAX 64
84/** The mask of bits covering the domain ID in the IOTLBE key. */
85# define IOMMU_IOTLB_DOMAIN_ID_MASK UINT64_C(0xffffff0000000000)
86/** The mask of bits covering the IOVA in the IOTLBE key. */
87# define IOMMU_IOTLB_IOVA_MASK (~IOMMU_IOTLB_DOMAIN_ID_MASK)
88/** The number of bits to shift for the domain ID of the IOTLBE key. */
89# define IOMMU_IOTLB_DOMAIN_ID_SHIFT 40
90/** A NIL IOTLB key. */
91# define IOMMU_IOTLB_KEY_NIL UINT64_C(0)
92/** Gets the domain ID from an IOTLB entry key. */
93# define IOMMU_IOTLB_KEY_GET_DOMAIN_ID(a_Key) ((a_Key) >> IOMMU_IOTLB_DOMAIN_ID_SHIFT)
94/** Gets the IOVA from the IOTLB entry key. */
95# define IOMMU_IOTLB_KEY_GET_IOVA(a_Key) (((a_Key) & IOMMU_IOTLB_IOVA_MASK) << X86_PAGE_4K_SHIFT)
96/** Makes an IOTLB entry key.
97 *
98 * Address bits 63:52 of the IOVA are zero extended, so top 12 bits are free.
99 * Address bits 11:0 of the IOVA are offset into the minimum page size of 4K,
100 * so bottom 12 bits are free.
101 *
102 * Thus we use the top 24 bits of key to hold bits 15:0 of the domain ID.
103 * We use the bottom 40 bits of the key to hold bits 51:12 of the IOVA.
104 */
105# define IOMMU_IOTLB_KEY_MAKE(a_DomainId, a_uIova) ( ((uint64_t)(a_DomainId) << IOMMU_IOTLB_DOMAIN_ID_SHIFT) \
106 | (((a_uIova) >> X86_PAGE_4K_SHIFT) & IOMMU_IOTLB_IOVA_MASK))
107#endif /* IOMMU_WITH_IOTLBE_CACHE */
108
109#ifdef IOMMU_WITH_DTE_CACHE
110/** @name IOMMU_DTE_CACHE_F_XXX: DTE cache flags.
111 *
112 * Some of these flags are "basic" i.e. they correspond directly to their bits in
113 * the DTE. The rest of the flags are based on checks or operations on several DTE
114 * bits.
115 *
116 * The basic flags are:
117 * - VALID (DTE.V)
118 * - IO_PERM_READ (DTE.IR)
119 * - IO_PERM_WRITE (DTE.IW)
120 * - IO_PERM_RSVD (bit following DTW.IW reserved for future & to keep
121 * masking consistent)
122 * - SUPPRESS_ALL_IOPF (DTE.SA)
123 * - SUPPRESS_IOPF (DTE.SE)
124 * - INTR_MAP_VALID (DTE.IV)
125 * - IGNORE_UNMAPPED_INTR (DTE.IG)
126 *
127 * @see iommuAmdGetBasicDevFlags()
128 * @{ */
129/** The DTE is present. */
130# define IOMMU_DTE_CACHE_F_PRESENT RT_BIT(0)
131/** The DTE is valid. */
132# define IOMMU_DTE_CACHE_F_VALID RT_BIT(1)
133/** The DTE permissions apply for address translations. */
134# define IOMMU_DTE_CACHE_F_IO_PERM RT_BIT(2)
135/** DTE permission - I/O read allowed. */
136# define IOMMU_DTE_CACHE_F_IO_PERM_READ RT_BIT(3)
137/** DTE permission - I/O write allowed. */
138# define IOMMU_DTE_CACHE_F_IO_PERM_WRITE RT_BIT(4)
139/** DTE permission - reserved. */
140# define IOMMU_DTE_CACHE_F_IO_PERM_RSVD RT_BIT(5)
141/** Address translation required. */
142# define IOMMU_DTE_CACHE_F_ADDR_TRANSLATE RT_BIT(6)
143/** Suppress all I/O page faults. */
144# define IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF RT_BIT(7)
145/** Suppress I/O page faults. */
146# define IOMMU_DTE_CACHE_F_SUPPRESS_IOPF RT_BIT(8)
147/** Interrupt map valid. */
148# define IOMMU_DTE_CACHE_F_INTR_MAP_VALID RT_BIT(9)
149/** Ignore unmapped interrupts. */
150# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR RT_BIT(10)
151/** An I/O page fault has been raised for this device. */
152# define IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED RT_BIT(11)
153/** Fixed and arbitrary interrupt control: Target Abort. */
154# define IOMMU_DTE_CACHE_F_INTR_CTRL_TARGET_ABORT RT_BIT(12)
155/** Fixed and arbitrary interrupt control: Forward unmapped. */
156# define IOMMU_DTE_CACHE_F_INTR_CTRL_FWD_UNMAPPED RT_BIT(13)
157/** Fixed and arbitrary interrupt control: Remapped. */
158# define IOMMU_DTE_CACHE_F_INTR_CTRL_REMAPPED RT_BIT(14)
159/** Fixed and arbitrary interrupt control: Reserved. */
160# define IOMMU_DTE_CACHE_F_INTR_CTRL_RSVD RT_BIT(15)
161/** @} */
162
163/** The number of bits to shift I/O device flags for DTE permissions. */
164# define IOMMU_DTE_CACHE_F_IO_PERM_SHIFT 3
165/** The mask of DTE permissions in I/O device flags. */
166# define IOMMU_DTE_CACHE_F_IO_PERM_MASK 0x3
167/** The number of bits to shift I/O device flags for interrupt control bits. */
168# define IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT 12
169/** The mask of interrupt control bits in I/O device flags. */
170# define IOMMU_DTE_CACHE_F_INTR_CTRL_MASK 0x3
171/** The number of bits to shift for ignore-unmapped interrupts bit. */
172# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR_SHIFT 10
173
174/** Acquires the cache lock. */
175# define IOMMU_CACHE_LOCK(a_pDevIns, a_pThis) \
176 do { \
177 int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VINF_SUCCESS); \
178 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV((a_pDevIns), &(a_pThis)->CritSectCache, rcLock); \
179 } while (0)
180
181/** Releases the cache lock. */
182# define IOMMU_CACHE_UNLOCK(a_pDevIns, a_pThis) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSectCache)
183#endif /* IOMMU_WITH_DTE_CACHE */
184
185/** Acquires the IOMMU lock (returns a_rcBusy on contention). */
186#define IOMMU_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
187 do { \
188 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)); \
189 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
190 { /* likely */ } \
191 else \
192 return rcLock; \
193 } while (0)
194
195/** Acquires the IOMMU lock (can fail under extraordinary circumstance in ring-0). */
196#define IOMMU_LOCK(a_pDevIns, a_pThisCC) \
197 do { \
198 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
199 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV((a_pDevIns), NULL, rcLock); \
200 } while (0)
201
202/** Checks if the current thread owns the PDM lock. */
203# define IOMMU_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
204 do \
205 { \
206 Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner((a_pDevIns))); \
207 NOREF(a_pThisCC); \
208 } while (0)
209
210/** Releases the PDM lock. */
211# define IOMMU_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock((a_pDevIns))
212
213/** Gets the maximum valid IOVA for the given I/O page-table level. */
214#define IOMMU_GET_MAX_VALID_IOVA(a_Level) ((X86_PAGE_4K_SIZE << ((a_Level) * 9)) - 1)
215
216
217/*********************************************************************************************************************************
218* Structures and Typedefs *
219*********************************************************************************************************************************/
220/**
221 * IOMMU operation (transaction).
222 */
223typedef enum IOMMUOP
224{
225 /** Address translation request. */
226 IOMMUOP_TRANSLATE_REQ = 0,
227 /** Memory read request. */
228 IOMMUOP_MEM_READ,
229 /** Memory write request. */
230 IOMMUOP_MEM_WRITE,
231 /** Interrupt request. */
232 IOMMUOP_INTR_REQ,
233 /** Command. */
234 IOMMUOP_CMD
235} IOMMUOP;
236/** Pointer to a IOMMU operation. */
237typedef IOMMUOP *PIOMMUOP;
238
239/**
240 * I/O page lookup.
241 */
242typedef struct IOPAGELOOKUP
243{
244 /** The translated system physical address. */
245 RTGCPHYS GCPhysSpa;
246 /** The number of offset bits in the system physical address. */
247 uint8_t cShift;
248 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
249 uint8_t fPerm;
250} IOPAGELOOKUP;
251/** Pointer to an I/O page lookup. */
252typedef IOPAGELOOKUP *PIOPAGELOOKUP;
253/** Pointer to a const I/O page lookup. */
254typedef IOPAGELOOKUP const *PCIOPAGELOOKUP;
255
256/**
257 * I/O address range.
258 */
259typedef struct IOADDRRANGE
260{
261 /** The address (virtual or physical). */
262 uint64_t uAddr;
263 /** The size of the access in bytes. */
264 size_t cb;
265 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
266 uint8_t fPerm;
267} IOADDRRANGE;
268/** Pointer to an I/O address range. */
269typedef IOADDRRANGE *PIOADDRRANGE;
270/** Pointer to a const I/O address range. */
271typedef IOADDRRANGE const *PCIOADDRRANGE;
272
273#ifdef IOMMU_WITH_DTE_CACHE
274/**
275 * Device Table Entry Cache.
276 */
277typedef struct DTECACHE
278{
279 /** This device's flags, see IOMMU_DTE_CACHE_F_XXX. */
280 uint16_t fFlags;
281 /** The domain ID assigned for this device by software. */
282 uint16_t idDomain;
283} DTECACHE;
284/** Pointer to an I/O device struct. */
285typedef DTECACHE *PDTECACHE;
286/** Pointer to a const I/O device struct. */
287typedef DTECACHE *PCDTECACHE;
288AssertCompileSize(DTECACHE, 4);
289#endif /* IOMMU_WITH_DTE_CACHE */
290
291#ifdef IOMMU_WITH_IOTLBE_CACHE
292/**
293 * I/O TLB Entry.
294 * Keep this as small and aligned as possible.
295 */
296typedef struct IOTLBE
297{
298 /** The AVL tree node. */
299 AVLU64NODECORE Core;
300 /** The least recently used (LRU) list node. */
301 RTLISTNODE NdLru;
302 /** The I/O page lookup results of the translation. */
303 IOPAGELOOKUP PageLookup;
304 /** Whether the entry needs to be evicted from the cache. */
305 bool fEvictPending;
306} IOTLBE;
307/** Pointer to an IOMMU I/O TLB entry struct. */
308typedef IOTLBE *PIOTLBE;
309/** Pointer to a const IOMMU I/O TLB entry struct. */
310typedef IOTLBE const *PCIOTLBE;
311AssertCompileSizeAlignment(IOTLBE, 8);
312AssertCompileMemberOffset(IOTLBE, Core, 0);
313#endif /* IOMMU_WITH_IOTLBE_CACHE */
314
315#ifdef IOMMU_WITH_IRTE_CACHE
316/**
317 * Interrupt Remap Table Entry Cache.
318 */
319typedef struct IRTECACHE
320{
321 /** The key, see IOMMU_IRTE_CACHE_KEY_MAKE. */
322 uint32_t uKey;
323 /** The IRTE. */
324 IRTE_T Irte;
325} IRTECACHE;
326/** Pointer to an IRTE cache struct. */
327typedef IRTECACHE *PIRTECACHE;
328/** Pointer to a const IRTE cache struct. */
329typedef IRTECACHE const *PCIRTECACHE;
330AssertCompileSizeAlignment(IRTECACHE, 4);
331#endif /* IOMMU_WITH_IRTE_CACHE */
332
333/**
334 * The shared IOMMU device state.
335 */
336typedef struct IOMMU
337{
338 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
339 uint32_t idxIommu;
340 /** IOMMU magic. */
341 uint32_t u32Magic;
342
343 /** The MMIO handle. */
344 IOMMMIOHANDLE hMmio;
345 /** The event semaphore the command thread waits on. */
346 SUPSEMEVENT hEvtCmdThread;
347 /** Whether the command thread has been signaled for wake up. */
348 bool volatile fCmdThreadSignaled;
349 /** Padding. */
350 bool afPadding0[3];
351 /** The IOMMU PCI address. */
352 PCIBDF uPciAddress;
353
354#ifdef IOMMU_WITH_DTE_CACHE
355 /** The critsect that protects the cache from concurrent access. */
356 PDMCRITSECT CritSectCache;
357 /** Array of device IDs. */
358 uint16_t aDeviceIds[IOMMU_DEV_CACHE_COUNT];
359 /** Array of DTE cache entries. */
360 DTECACHE aDteCache[IOMMU_DEV_CACHE_COUNT];
361#endif
362#ifdef IOMMU_WITH_IRTE_CACHE
363 /** Array of IRTE cache entries. */
364 IRTECACHE aIrteCache[IOMMU_IRTE_CACHE_COUNT];
365#endif
366
367 /** @name PCI: Base capability block registers.
368 * @{ */
369 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
370 /** @} */
371
372 /** @name MMIO: Control and status registers.
373 * @{ */
374 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
375 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
376 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
377 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
378 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
379 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
380 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
381 /** @} */
382
383 /** @name MMIO: Peripheral Page Request (PPR) Log registers.
384 * @{ */
385 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
386 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
387 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
388 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
389 /** @} */
390
391 /** @todo IOMMU: SMI filter. */
392
393 /** @name MMIO: Guest Virtual-APIC Log registers.
394 * @{ */
395 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
396 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
397 /** @} */
398
399 /** @name MMIO: Alternate PPR and Event Log registers.
400 * @{ */
401 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
402 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
403 /** @} */
404
405 /** @name MMIO: Device-specific feature registers.
406 * @{ */
407 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
408 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
409 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
410 /** @} */
411
412 /** @name MMIO: MSI Capability Block registers.
413 * @{ */
414 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
415 /** @} */
416
417 /** @name MMIO: Performance Optimization Control registers.
418 * @{ */
419 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
420 /** @} */
421
422 /** @name MMIO: x2APIC Control registers.
423 * @{ */
424 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
425 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
426 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
427 /** @} */
428
429 /** @name MMIO: Memory Address Routing & Control (MARC) registers.
430 * @{ */
431 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
432 /** @} */
433
434 /** @name MMIO: Reserved register.
435 * @{ */
436 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
437 /** @} */
438
439 /** @name MMIO: Command and Event Log pointer registers.
440 * @{ */
441 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
442 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
443 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
444 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
445 /** @} */
446
447 /** @name MMIO: Command and Event Status register.
448 * @{ */
449 IOMMU_STATUS_T Status; /**< IOMMU status register. */
450 /** @} */
451
452 /** @name MMIO: PPR Log Head and Tail pointer registers.
453 * @{ */
454 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
455 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
456 /** @} */
457
458 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
459 * @{ */
460 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
461 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
462 /** @} */
463
464 /** @name MMIO: PPR Log B Head and Tail pointer registers.
465 * @{ */
466 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
467 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
468 /** @} */
469
470 /** @name MMIO: Event Log B Head and Tail pointer registers.
471 * @{ */
472 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
473 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
474 /** @} */
475
476 /** @name MMIO: PPR Log Overflow protection registers.
477 * @{ */
478 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
479 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
480 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
481 /** @} */
482
483 /** @todo IOMMU: IOMMU Event counter registers. */
484
485#ifdef VBOX_WITH_STATISTICS
486 /** @name IOMMU: Stat counters.
487 * @{ */
488 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
489 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
490 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
491 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
492
493 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
494 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
495
496 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
497 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
498 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
499 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
500
501 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
502 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
503 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
504 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
505
506 STAMCOUNTER StatCmd; /**< Number of commands processed in total. */
507 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
508 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
509 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
510 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
511 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
512 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
513 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
514 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
515
516 STAMCOUNTER StatIotlbeCached; /**< Number of IOTLB entries in the cache. */
517 STAMCOUNTER StatIotlbeLazyEvictReuse; /**< Number of IOTLB entries re-used after lazy eviction. */
518
519 STAMPROFILEADV StatProfDteLookup; /**< Profiling of I/O page walk (from memory). */
520 STAMPROFILEADV StatProfIotlbeLookup; /**< Profiling of IOTLB entry lookup (from cache). */
521
522 STAMPROFILEADV StatProfIrteLookup; /**< Profiling of IRTE entry lookup (from memory). */
523 STAMPROFILEADV StatProfIrteCacheLookup; /**< Profiling of IRTE entry lookup (from cache). */
524
525 STAMCOUNTER StatAccessCacheHit; /**< Number of IOTLB cache hits. */
526 STAMCOUNTER StatAccessCacheHitFull; /**< Number of accesses that were fully looked up from the cache. */
527 STAMCOUNTER StatAccessCacheMiss; /**< Number of cache misses (resulting in DTE lookups). */
528 STAMCOUNTER StatAccessCacheNonContig; /**< Number of cache accesses resulting in non-contiguous access. */
529 STAMCOUNTER StatAccessCachePermDenied; /**< Number of cache accesses resulting in insufficient permissions. */
530 STAMCOUNTER StatAccessDteNonContig; /**< Number of DTE accesses resulting in non-contiguous access. */
531 STAMCOUNTER StatAccessDtePermDenied; /**< Number of DTE accesses resulting in insufficient permissions. */
532
533 STAMCOUNTER StatIntrCacheHit; /**< Number of interrupt cache hits. */
534 STAMCOUNTER StatIntrCacheMiss; /**< Number of interrupt cache misses. */
535
536 STAMCOUNTER StatNonStdPageSize; /**< Number of non-standard page size translations. */
537 STAMCOUNTER StatIopfs; /**< Number of I/O page faults. */
538 /** @} */
539#endif
540} IOMMU;
541/** Pointer to the IOMMU device state. */
542typedef IOMMU *PIOMMU;
543/** Pointer to the const IOMMU device state. */
544typedef const IOMMU *PCIOMMU;
545AssertCompileMemberAlignment(IOMMU, hMmio, 8);
546#ifdef IOMMU_WITH_DTE_CACHE
547AssertCompileMemberAlignment(IOMMU, CritSectCache, 8);
548AssertCompileMemberAlignment(IOMMU, aDeviceIds, 8);
549AssertCompileMemberAlignment(IOMMU, aDteCache, 8);
550#endif
551#ifdef IOMMU_WITH_IRTE_CACHE
552AssertCompileMemberAlignment(IOMMU, aIrteCache, 8);
553#endif
554AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
555AssertCompileMemberAlignment(IOMMU, aDevTabBaseAddrs, 8);
556AssertCompileMemberAlignment(IOMMU, CmdBufHeadPtr, 8);
557AssertCompileMemberAlignment(IOMMU, Status, 8);
558
559/**
560 * The ring-3 IOMMU device state.
561 */
562typedef struct IOMMUR3
563{
564 /** Device instance. */
565 PPDMDEVINSR3 pDevInsR3;
566 /** The IOMMU helpers. */
567 R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
568 /** The command thread handle. */
569 R3PTRTYPE(PPDMTHREAD) pCmdThread;
570#ifdef IOMMU_WITH_IOTLBE_CACHE
571 /** Pointer to array of pre-allocated IOTLBEs. */
572 PIOTLBE paIotlbes;
573 /** Maps [DomainId,Iova] to [IOTLBE]. */
574 AVLU64TREE TreeIotlbe;
575 /** LRU list anchor for IOTLB entries. */
576 RTLISTANCHOR LstLruIotlbe;
577 /** Index of the next unused IOTLB. */
578 uint32_t idxUnusedIotlbe;
579 /** Number of cached IOTLB entries in the tree. */
580 uint32_t cCachedIotlbes;
581#endif
582} IOMMUR3;
583/** Pointer to the ring-3 IOMMU device state. */
584typedef IOMMUR3 *PIOMMUR3;
585/** Pointer to the const ring-3 IOMMU device state. */
586typedef const IOMMUR3 *PCIOMMUR3;
587#ifdef IOMMU_WITH_IOTLBE_CACHE
588AssertCompileMemberAlignment(IOMMUR3, paIotlbes, 8);
589AssertCompileMemberAlignment(IOMMUR3, TreeIotlbe, 8);
590AssertCompileMemberAlignment(IOMMUR3, LstLruIotlbe, 8);
591#endif
592
593/**
594 * The ring-0 IOMMU device state.
595 */
596typedef struct IOMMUR0
597{
598 /** Device instance. */
599 PPDMDEVINSR0 pDevInsR0;
600 /** The IOMMU helpers. */
601 R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
602} IOMMUR0;
603/** Pointer to the ring-0 IOMMU device state. */
604typedef IOMMUR0 *PIOMMUR0;
605
606/**
607 * The raw-mode IOMMU device state.
608 */
609typedef struct IOMMURC
610{
611 /** Device instance. */
612 PPDMDEVINSRC pDevInsRC;
613 /** The IOMMU helpers. */
614 RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
615} IOMMURC;
616/** Pointer to the raw-mode IOMMU device state. */
617typedef IOMMURC *PIOMMURC;
618
619/** The IOMMU device state for the current context. */
620typedef CTX_SUFF(IOMMU) IOMMUCC;
621/** Pointer to the IOMMU device state for the current context. */
622typedef CTX_SUFF(PIOMMU) PIOMMUCC;
623
624/**
625 * IOMMU register access.
626 */
627typedef struct IOMMUREGACC
628{
629 const char *pszName;
630 VBOXSTRICTRC (*pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value);
631 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
632} IOMMUREGACC;
633/** Pointer to an IOMMU register access. */
634typedef IOMMUREGACC *PIOMMUREGACC;
635/** Pointer to a const IOMMU register access. */
636typedef IOMMUREGACC const *PCIOMMUREGACC;
637
638#ifdef IOMMU_WITH_IOTLBE_CACHE
639/**
640 * IOTLBE flush argument.
641 */
642typedef struct IOTLBEFLUSHARG
643{
644 /** The ring-3 IOMMU device state. */
645 PIOMMUR3 pIommuR3;
646 /** The domain ID to flush. */
647 uint16_t idDomain;
648} IOTLBEFLUSHARG;
649/** Pointer to an IOTLBE flush argument. */
650typedef IOTLBEFLUSHARG *PIOTLBEFLUSHARG;
651/** Pointer to a const IOTLBE flush argument. */
652typedef IOTLBEFLUSHARG const *PCIOTLBEFLUSHARG;
653
654/**
655 * IOTLBE Info. argument.
656 */
657typedef struct IOTLBEINFOARG
658{
659 /** The ring-3 IOMMU device state. */
660 PIOMMUR3 pIommuR3;
661 /** The info helper. */
662 PCDBGFINFOHLP pHlp;
663 /** The domain ID to dump IOTLB entry. */
664 uint16_t idDomain;
665} IOTLBEINFOARG;
666/** Pointer to an IOTLBE flush argument. */
667typedef IOTLBEINFOARG *PIOTLBEINFOARG;
668/** Pointer to a const IOTLBE flush argument. */
669typedef IOTLBEINFOARG const *PCIOTLBEINFOARG;
670#endif
671
672/**
673 * IOMMU operation auxiliary info.
674 */
675typedef struct IOMMUOPAUX
676{
677 /** The IOMMU operation being performed. */
678 IOMMUOP enmOp;
679 /** The device table entry (can be NULL). */
680 PCDTE_T pDte;
681 /** The device ID (bus, device, function). */
682 uint16_t idDevice;
683 /** The domain ID (when the DTE isn't provided). */
684 uint16_t idDomain;
685} IOMMUOPAUX;
686/** Pointer to an I/O address lookup struct. */
687typedef IOMMUOPAUX *PIOMMUOPAUX;
688/** Pointer to a const I/O address lookup struct. */
689typedef IOMMUOPAUX const *PCIOMMUOPAUX;
690
691typedef DECLCALLBACKTYPE(int, FNIOPAGELOOKUP,(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
692 PIOPAGELOOKUP pPageLookup));
693typedef FNIOPAGELOOKUP *PFNIOPAGELOOKUP;
694
695
696/*********************************************************************************************************************************
697* Global Variables *
698*********************************************************************************************************************************/
699#ifdef IN_RING3
700/**
701 * An array of the number of device table segments supported.
702 * Indexed by u2DevTabSegSup.
703 */
704static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
705#endif
706
707#if (defined(IN_RING3) && defined(IOMMU_WITH_IOTLBE_CACHE)) || defined(LOG_ENABLED)
708/**
709 * The IOMMU I/O permission names.
710 */
711static const char * const g_aszPerm[] = { "none", "read", "write", "read+write" };
712#endif
713
714/**
715 * An array of the masks to select the device table segment index from a device ID.
716 */
717static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
718
719/**
720 * An array of the shift values to select the device table segment index from a
721 * device ID.
722 */
723static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
724
725/**
726 * The maximum size (inclusive) of each device table segment (0 to 7).
727 * Indexed by the device table segment index.
728 */
729static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
730
731
732#ifndef VBOX_DEVICE_STRUCT_TESTCASE
733/**
734 * Gets the maximum number of buffer entries for the given buffer length.
735 *
736 * @returns Number of buffer entries.
737 * @param uEncodedLen The length (power-of-2 encoded).
738 */
739DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
740{
741 Assert(uEncodedLen > 7);
742 Assert(uEncodedLen < 16);
743 return 2 << (uEncodedLen - 1);
744}
745
746
747/**
748 * Gets the total length of the buffer given a base register's encoded length.
749 *
750 * @returns The length of the buffer in bytes.
751 * @param uEncodedLen The length (power-of-2 encoded).
752 */
753DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
754{
755 Assert(uEncodedLen > 7);
756 Assert(uEncodedLen < 16);
757 return (2 << (uEncodedLen - 1)) << 4;
758}
759
760
761/**
762 * Gets the number of (unconsumed) entries in the event log.
763 *
764 * @returns The number of entries in the event log.
765 * @param pThis The shared IOMMU device state.
766 */
767static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
768{
769 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
770 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
771 if (idxTail >= idxHead)
772 return idxTail - idxHead;
773
774 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
775 return cMaxEvts - idxHead + idxTail;
776}
777
778
779#if (defined(IN_RING3) && defined(IOMMU_WITH_IOTLBE_CACHE)) || defined(LOG_ENABLED)
780/**
781 * Gets the descriptive I/O permission name for a memory access.
782 *
783 * @returns The I/O permission name.
784 * @param fPerm The I/O permissions for the access, see IOMMU_IO_PERM_XXX.
785 */
786static const char *iommuAmdMemAccessGetPermName(uint8_t fPerm)
787{
788 /* We shouldn't construct an access with "none" or "read+write" (must be read or write) permissions. */
789 Assert(fPerm > 0 && fPerm < RT_ELEMENTS(g_aszPerm));
790 return g_aszPerm[fPerm & IOMMU_IO_PERM_MASK];
791}
792#endif
793
794
795#ifdef IOMMU_WITH_DTE_CACHE
796/**
797 * Gets the basic I/O device flags for the given device table entry.
798 *
799 * @returns The basic I/O device flags.
800 * @param pDte The device table entry.
801 */
802static uint16_t iommuAmdGetBasicDevFlags(PCDTE_T pDte)
803{
804 /* Extract basic flags from bits 127:0 of the DTE. */
805 uint16_t fFlags = 0;
806 if (pDte->n.u1Valid)
807 {
808 fFlags |= IOMMU_DTE_CACHE_F_VALID;
809
810 /** @todo Skip the if checks here (shift/mask the relevant bits over). */
811 if (pDte->n.u1SuppressAllPfEvents)
812 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
813 if (pDte->n.u1SuppressPfEvents)
814 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_IOPF;
815
816 uint16_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
817 AssertCompile(IOMMU_DTE_CACHE_F_IO_PERM_MASK == IOMMU_IO_PERM_MASK);
818 fFlags |= fDtePerm << IOMMU_DTE_CACHE_F_IO_PERM_SHIFT;
819 }
820
821 /* Extract basic flags from bits 255:128 of the DTE. */
822 if (pDte->n.u1IntrMapValid)
823 {
824 fFlags |= IOMMU_DTE_CACHE_F_INTR_MAP_VALID;
825
826 /** @todo Skip the if check here (shift/mask the relevant bit over). */
827 if (pDte->n.u1IgnoreUnmappedIntrs)
828 fFlags |= IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
829
830 uint16_t const fIntrCtrl = IOMMU_DTE_GET_INTR_CTRL(pDte);
831 AssertCompile(IOMMU_DTE_CACHE_F_INTR_CTRL_MASK == IOMMU_DTE_INTR_CTRL_MASK);
832 fFlags |= fIntrCtrl << IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT;
833 }
834 return fFlags;
835}
836#endif
837
838
839/**
840 * Remaps the source MSI to the destination MSI given the IRTE.
841 *
842 * @param pMsiIn The source MSI.
843 * @param pMsiOut Where to store the remapped MSI.
844 * @param pIrte The IRTE used for the remapping.
845 */
846static void iommuAmdIrteRemapMsi(PCMSIMSG pMsiIn, PMSIMSG pMsiOut, PCIRTE_T pIrte)
847{
848 /* Preserve all bits from the source MSI address and data that don't map 1:1 from the IRTE. */
849 *pMsiOut = *pMsiIn;
850
851 pMsiOut->Addr.n.u1DestMode = pIrte->n.u1DestMode;
852 pMsiOut->Addr.n.u8DestId = pIrte->n.u8Dest;
853
854 pMsiOut->Data.n.u8Vector = pIrte->n.u8Vector;
855 pMsiOut->Data.n.u3DeliveryMode = pIrte->n.u3IntrType;
856}
857
858
859#ifdef IOMMU_WITH_DTE_CACHE
860/**
861 * Looks up an entry in the DTE cache for the given device ID.
862 *
863 * @returns The index of the entry, or the cache capacity if no entry was found.
864 * @param pThis The shared IOMMU device state.
865 * @param idDevice The device ID (bus, device, function).
866 */
867DECLINLINE(uint16_t) iommuAmdDteCacheEntryLookup(PIOMMU pThis, uint16_t idDevice)
868{
869 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
870 for (uint16_t i = 0; i < cDeviceIds; i++)
871 {
872 if (pThis->aDeviceIds[i] == idDevice)
873 return i;
874 }
875 return cDeviceIds;
876}
877
878
879/**
880 * Gets an free/unused DTE cache entry.
881 *
882 * @returns The index of an unused entry, or cache capacity if the cache is full.
883 * @param pThis The shared IOMMU device state.
884 */
885DECLINLINE(uint16_t) iommuAmdDteCacheEntryGetUnused(PCIOMMU pThis)
886{
887 /*
888 * ASSUMES device ID 0 is the PCI host bridge or the IOMMU itself
889 * (the latter being an ugly hack) and cannot be a valid device ID.
890 */
891 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
892 for (uint16_t i = 0; i < cDeviceIds; i++)
893 {
894 if (!pThis->aDeviceIds[i])
895 return i;
896 }
897 return cDeviceIds;
898}
899
900
901/**
902 * Adds a DTE cache entry at the given index.
903 *
904 * @param pThis The shared IOMMU device state.
905 * @param idxDte The index of the DTE cache entry.
906 * @param idDevice The device ID (bus, device, function).
907 * @param fFlags Device flags to set, see IOMMU_DTE_CACHE_F_XXX.
908 * @param idDomain The domain ID.
909 *
910 * @remarks Requires the cache lock to be taken.
911 */
912DECL_FORCE_INLINE(void) iommuAmdDteCacheAddAtIndex(PIOMMU pThis, uint16_t idxDte, uint16_t idDevice, uint16_t fFlags,
913 uint16_t idDomain)
914{
915 pThis->aDeviceIds[idxDte] = idDevice;
916 pThis->aDteCache[idxDte].fFlags = fFlags;
917 pThis->aDteCache[idxDte].idDomain = idDomain;
918}
919
920
921/**
922 * Adds a DTE cache entry.
923 *
924 * @param pDevIns The IOMMU instance data.
925 * @param idDevice The device ID (bus, device, function).
926 * @param pDte The device table entry.
927 */
928static void iommuAmdDteCacheAdd(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte)
929{
930 uint16_t const fFlags = iommuAmdGetBasicDevFlags(pDte) | IOMMU_DTE_CACHE_F_PRESENT;
931 uint16_t const idDomain = pDte->n.u16DomainId;
932
933 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
934 IOMMU_CACHE_LOCK(pDevIns, pThis);
935
936 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
937 uint16_t idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
938 if ( idxDte >= cDteCache /* Not found. */
939 && (idxDte = iommuAmdDteCacheEntryGetUnused(pThis)) < cDteCache) /* Get new/unused slot index. */
940 iommuAmdDteCacheAddAtIndex(pThis, idxDte, idDevice, fFlags, idDomain);
941
942 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
943}
944
945
946/**
947 * Updates flags for an existing DTE cache entry given its index.
948 *
949 * @param pThis The shared IOMMU device state.
950 * @param idxDte The index of the DTE cache entry.
951 * @param fOrMask Device flags to add to the existing flags, see
952 * IOMMU_DTE_CACHE_F_XXX.
953 * @param fAndMask Device flags to remove from the existing flags, see
954 * IOMMU_DTE_CACHE_F_XXX.
955 *
956 * @remarks Requires the cache lock to be taken.
957 */
958DECL_FORCE_INLINE(void) iommuAmdDteCacheUpdateFlagsForIndex(PIOMMU pThis, uint16_t idxDte, uint16_t fOrMask, uint16_t fAndMask)
959{
960 uint16_t const fOldFlags = pThis->aDteCache[idxDte].fFlags;
961 uint16_t const fNewFlags = (fOldFlags | fOrMask) & ~fAndMask;
962 Assert(fOldFlags & IOMMU_DTE_CACHE_F_PRESENT);
963 pThis->aDteCache[idxDte].fFlags = fNewFlags;
964}
965
966
967#ifdef IOMMU_WITH_IOTLBE_CACHE
968/**
969 * Adds a new DTE cache entry or updates flags for an existing DTE cache entry.
970 * If the cache is full, nothing happens.
971 *
972 * @param pDevIns The IOMMU instance data.
973 * @param pDte The device table entry.
974 * @param idDevice The device ID (bus, device, function).
975 * @param fOrMask Device flags to add to the existing flags, see
976 * IOMMU_DTE_CACHE_F_XXX.
977 * @param fAndMask Device flags to remove from the existing flags, see
978 * IOMMU_DTE_CACHE_F_XXX.
979 */
980static void iommuAmdDteCacheAddOrUpdateFlags(PPDMDEVINS pDevIns, PCDTE_T pDte, uint16_t idDevice, uint16_t fOrMask,
981 uint16_t fAndMask)
982{
983 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
984 IOMMU_CACHE_LOCK(pDevIns, pThis);
985
986 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
987 uint16_t idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
988 if (idxDte < cDteCache)
989 iommuAmdDteCacheUpdateFlagsForIndex(pThis, idxDte, fOrMask, fAndMask);
990 else if ((idxDte = iommuAmdDteCacheEntryGetUnused(pThis)) < cDteCache)
991 {
992 uint16_t const fFlags = (iommuAmdGetBasicDevFlags(pDte) | IOMMU_DTE_CACHE_F_PRESENT | fOrMask) & ~fAndMask;
993 iommuAmdDteCacheAddAtIndex(pThis, idxDte, idDevice, fFlags, pDte->n.u16DomainId);
994 }
995 /* else: cache is full, shouldn't really happen. */
996
997 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
998}
999#endif
1000
1001
1002/**
1003 * Updates flags for an existing DTE cache entry.
1004 *
1005 * @param pDevIns The IOMMU instance data.
1006 * @param idDevice The device ID (bus, device, function).
1007 * @param fOrMask Device flags to add to the existing flags, see
1008 * IOMMU_DTE_CACHE_F_XXX.
1009 * @param fAndMask Device flags to remove from the existing flags, see
1010 * IOMMU_DTE_CACHE_F_XXX.
1011 */
1012static void iommuAmdDteCacheUpdateFlags(PPDMDEVINS pDevIns, uint16_t idDevice, uint16_t fOrMask, uint16_t fAndMask)
1013{
1014 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1015 IOMMU_CACHE_LOCK(pDevIns, pThis);
1016
1017 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
1018 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
1019 if (idxDte < cDteCache)
1020 iommuAmdDteCacheUpdateFlagsForIndex(pThis, idxDte, fOrMask, fAndMask);
1021
1022 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1023}
1024
1025
1026# ifdef IN_RING3
1027/**
1028 * Removes a DTE cache entry.
1029 *
1030 * @param pDevIns The IOMMU instance data.
1031 * @param idDevice The device ID to remove cache entries for.
1032 */
1033static void iommuAmdDteCacheRemove(PPDMDEVINS pDevIns, uint16_t idDevice)
1034{
1035 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1036 IOMMU_CACHE_LOCK(pDevIns, pThis);
1037
1038 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
1039 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
1040 if (idxDte < cDteCache)
1041 {
1042 pThis->aDteCache[idxDte].fFlags = 0;
1043 pThis->aDteCache[idxDte].idDomain = 0;
1044 }
1045
1046 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1047}
1048
1049
1050/**
1051 * Removes all entries in the device table entry cache.
1052 *
1053 * @param pDevIns The IOMMU instance data.
1054 */
1055static void iommuAmdDteCacheRemoveAll(PPDMDEVINS pDevIns)
1056{
1057 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1058 IOMMU_CACHE_LOCK(pDevIns, pThis);
1059 RT_ZERO(pThis->aDeviceIds);
1060 RT_ZERO(pThis->aDteCache);
1061 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1062}
1063# endif /* IN_RING3 */
1064#endif /* IOMMU_WITH_DTE_CACHE */
1065
1066
1067#ifdef IOMMU_WITH_IOTLBE_CACHE
1068/**
1069 * Moves the IOTLB entry to the least recently used slot.
1070 *
1071 * @param pThisR3 The ring-3 IOMMU device state.
1072 * @param pIotlbe The IOTLB entry to move.
1073 */
1074DECLINLINE(void) iommuAmdIotlbEntryMoveToLru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1075{
1076 if (!RTListNodeIsFirst(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1077 {
1078 RTListNodeRemove(&pIotlbe->NdLru);
1079 RTListPrepend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1080 }
1081}
1082
1083
1084/**
1085 * Moves the IOTLB entry to the most recently used slot.
1086 *
1087 * @param pThisR3 The ring-3 IOMMU device state.
1088 * @param pIotlbe The IOTLB entry to move.
1089 */
1090DECLINLINE(void) iommuAmdIotlbEntryMoveToMru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1091{
1092 if (!RTListNodeIsLast(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1093 {
1094 RTListNodeRemove(&pIotlbe->NdLru);
1095 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1096 }
1097}
1098
1099
1100# ifdef IN_RING3
1101/**
1102 * Dumps the IOTLB entry via the debug info helper.
1103 *
1104 * @returns VINF_SUCCESS.
1105 * @param pNode Pointer to an IOTLB entry to dump info.
1106 * @param pvUser Pointer to an IOTLBEINFOARG.
1107 */
1108static DECLCALLBACK(int) iommuAmdR3IotlbEntryInfo(PAVLU64NODECORE pNode, void *pvUser)
1109{
1110 /* Validate. */
1111 PCIOTLBEINFOARG pArgs = (PCIOTLBEINFOARG)pvUser;
1112 AssertPtr(pArgs);
1113 AssertPtr(pArgs->pIommuR3);
1114 AssertPtr(pArgs->pHlp);
1115 //Assert(pArgs->pIommuR3->u32Magic == IOMMU_MAGIC);
1116
1117 uint16_t const idDomain = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1118 if (idDomain == pArgs->idDomain)
1119 {
1120 PCIOTLBE pIotlbe = (PCIOTLBE)pNode;
1121 AVLU64KEY const uKey = pIotlbe->Core.Key;
1122 uint64_t const uIova = IOMMU_IOTLB_KEY_GET_IOVA(uKey);
1123 RTGCPHYS const GCPhysSpa = pIotlbe->PageLookup.GCPhysSpa;
1124 uint8_t const cShift = pIotlbe->PageLookup.cShift;
1125 size_t const cbPage = RT_BIT_64(cShift);
1126 uint8_t const fPerm = pIotlbe->PageLookup.fPerm;
1127 const char *pszPerm = iommuAmdMemAccessGetPermName(fPerm);
1128 bool const fEvictPending = pIotlbe->fEvictPending;
1129
1130 PCDBGFINFOHLP pHlp = pArgs->pHlp;
1131 pHlp->pfnPrintf(pHlp, " Key = %#RX64 (%#RX64)\n", uKey, uIova);
1132 pHlp->pfnPrintf(pHlp, " GCPhys = %#RGp\n", GCPhysSpa);
1133 pHlp->pfnPrintf(pHlp, " cShift = %u (%zu bytes)\n", cShift, cbPage);
1134 pHlp->pfnPrintf(pHlp, " fPerm = %#x (%s)\n", fPerm, pszPerm);
1135 pHlp->pfnPrintf(pHlp, " fEvictPending = %RTbool\n", fEvictPending);
1136 }
1137
1138 return VINF_SUCCESS;
1139}
1140# endif /* IN_RING3 */
1141
1142
1143/**
1144 * Removes the IOTLB entry if it's associated with the specified domain ID.
1145 *
1146 * @returns VINF_SUCCESS.
1147 * @param pNode Pointer to an IOTLBE.
1148 * @param pvUser Pointer to an IOTLBEFLUSHARG containing the domain ID.
1149 */
1150static DECLCALLBACK(int) iommuAmdIotlbEntryRemoveDomainId(PAVLU64NODECORE pNode, void *pvUser)
1151{
1152 /* Validate. */
1153 PCIOTLBEFLUSHARG pArgs = (PCIOTLBEFLUSHARG)pvUser;
1154 AssertPtr(pArgs);
1155 AssertPtr(pArgs->pIommuR3);
1156 //Assert(pArgs->pIommuR3->u32Magic == IOMMU_MAGIC);
1157
1158 uint16_t const idDomain = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1159 if (idDomain == pArgs->idDomain)
1160 {
1161 /* Mark this entry is as invalidated and needs to be evicted later. */
1162 PIOTLBE pIotlbe = (PIOTLBE)pNode;
1163 pIotlbe->fEvictPending = true;
1164 iommuAmdIotlbEntryMoveToLru(pArgs->pIommuR3, (PIOTLBE)pNode);
1165 }
1166 return VINF_SUCCESS;
1167}
1168
1169
1170/**
1171 * Destroys an IOTLB entry that's in the tree.
1172 *
1173 * @returns VINF_SUCCESS.
1174 * @param pNode Pointer to an IOTLBE.
1175 * @param pvUser Opaque data. Currently not used, will be NULL.
1176 */
1177static DECLCALLBACK(int) iommuAmdIotlbEntryDestroy(PAVLU64NODECORE pNode, void *pvUser)
1178{
1179 RT_NOREF(pvUser);
1180 PIOTLBE pIotlbe = (PIOTLBE)pNode;
1181 Assert(pIotlbe);
1182 pIotlbe->NdLru.pNext = NULL;
1183 pIotlbe->NdLru.pPrev = NULL;
1184 RT_ZERO(pIotlbe->PageLookup);
1185 pIotlbe->fEvictPending = false;
1186 return VINF_SUCCESS;
1187}
1188
1189
1190/**
1191 * Inserts an IOTLB entry into the cache.
1192 *
1193 * @param pThis The shared IOMMU device state.
1194 * @param pThisR3 The ring-3 IOMMU device state.
1195 * @param pIotlbe The IOTLB entry to initialize and insert.
1196 * @param idDomain The domain ID.
1197 * @param uIova The I/O virtual address.
1198 * @param pPageLookup The I/O page lookup result of the access.
1199 */
1200static void iommuAmdIotlbEntryInsert(PIOMMU pThis, PIOMMUR3 pThisR3, PIOTLBE pIotlbe, uint16_t idDomain, uint64_t uIova,
1201 PCIOPAGELOOKUP pPageLookup)
1202{
1203 /* Initialize the IOTLB entry with results of the I/O page walk. */
1204 AVLU64KEY const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1205 Assert(uKey != IOMMU_IOTLB_KEY_NIL);
1206
1207 /* Check if the entry already exists. */
1208 PIOTLBE pFound = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, uKey);
1209 if (!pFound)
1210 {
1211 /* Insert the entry into the cache. */
1212 pIotlbe->Core.Key = uKey;
1213 pIotlbe->PageLookup = *pPageLookup;
1214 Assert(!pIotlbe->fEvictPending);
1215
1216 bool const fInserted = RTAvlU64Insert(&pThisR3->TreeIotlbe, &pIotlbe->Core);
1217 Assert(fInserted); NOREF(fInserted);
1218 Assert(pThisR3->cCachedIotlbes < IOMMU_IOTLBE_MAX);
1219 ++pThisR3->cCachedIotlbes;
1220 STAM_COUNTER_INC(&pThis->StatIotlbeCached); NOREF(pThis);
1221 }
1222 else
1223 {
1224 /* Update the existing entry. */
1225 Assert(pFound->Core.Key == uKey);
1226 if (pFound->fEvictPending)
1227 {
1228 pFound->fEvictPending = false;
1229 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse); NOREF(pThis);
1230 }
1231 pFound->PageLookup = *pPageLookup;
1232 }
1233}
1234
1235
1236/**
1237 * Removes an IOTLB entry from the cache for the given key.
1238 *
1239 * @returns Pointer to the removed IOTLB entry, NULL if the entry wasn't found in
1240 * the tree.
1241 * @param pThis The shared IOMMU device state.
1242 * @param pThisR3 The ring-3 IOMMU device state.
1243 * @param uKey The key of the IOTLB entry to remove.
1244 */
1245static PIOTLBE iommuAmdIotlbEntryRemove(PIOMMU pThis, PIOMMUR3 pThisR3, AVLU64KEY uKey)
1246{
1247 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Remove(&pThisR3->TreeIotlbe, uKey);
1248 if (pIotlbe)
1249 {
1250 if (pIotlbe->fEvictPending)
1251 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse);
1252
1253 RT_ZERO(pIotlbe->Core);
1254 RT_ZERO(pIotlbe->PageLookup);
1255 /* We must not erase the LRU node connections here! */
1256 pIotlbe->fEvictPending = false;
1257 Assert(pIotlbe->Core.Key == IOMMU_IOTLB_KEY_NIL);
1258
1259 Assert(pThisR3->cCachedIotlbes > 0);
1260 --pThisR3->cCachedIotlbes;
1261 STAM_COUNTER_DEC(&pThis->StatIotlbeCached); NOREF(pThis);
1262 }
1263 return pIotlbe;
1264}
1265
1266
1267/**
1268 * Looks up an IOTLB from the cache.
1269 *
1270 * @returns Pointer to IOTLB entry if found, NULL otherwise.
1271 * @param pThis The shared IOMMU device state.
1272 * @param pThisR3 The ring-3 IOMMU device state.
1273 * @param idDomain The domain ID.
1274 * @param uIova The I/O virtual address.
1275 */
1276static PIOTLBE iommuAmdIotlbLookup(PIOMMU pThis, PIOMMUR3 pThisR3, uint64_t idDomain, uint64_t uIova)
1277{
1278 RT_NOREF(pThis);
1279
1280 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1281 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, uKey);
1282 if ( pIotlbe
1283 && !pIotlbe->fEvictPending)
1284 return pIotlbe;
1285
1286 /*
1287 * Domain Id wildcard invalidations only marks entries for eviction later but doesn't remove
1288 * them from the cache immediately. We found an entry pending eviction, just return that
1289 * nothing was found (rather than evicting now).
1290 */
1291 return NULL;
1292}
1293
1294
1295/**
1296 * Adds an IOTLB entry to the cache.
1297 *
1298 * @param pThis The shared IOMMU device state.
1299 * @param pThisR3 The ring-3 IOMMU device state.
1300 * @param idDomain The domain ID.
1301 * @param uIovaPage The I/O virtual address (must be 4K aligned).
1302 * @param pPageLookup The I/O page lookup result of the access.
1303 */
1304static void iommuAmdIotlbAdd(PIOMMU pThis, PIOMMUR3 pThisR3, uint16_t idDomain, uint64_t uIovaPage, PCIOPAGELOOKUP pPageLookup)
1305{
1306 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
1307 Assert(pPageLookup);
1308 Assert(pPageLookup->cShift <= 51);
1309 Assert(pPageLookup->fPerm != IOMMU_IO_PERM_NONE);
1310
1311 /*
1312 * If there are no unused IOTLB entries, evict the LRU entry.
1313 * Otherwise, get a new IOTLB entry from the pre-allocated list.
1314 */
1315 if (pThisR3->idxUnusedIotlbe == IOMMU_IOTLBE_MAX)
1316 {
1317 /* Grab the least recently used entry. */
1318 PIOTLBE pIotlbe = RTListGetFirst(&pThisR3->LstLruIotlbe, IOTLBE, NdLru);
1319 Assert(pIotlbe);
1320
1321 /* If the entry is in the cache, remove it. */
1322 if (pIotlbe->Core.Key != IOMMU_IOTLB_KEY_NIL)
1323 iommuAmdIotlbEntryRemove(pThis, pThisR3, pIotlbe->Core.Key);
1324
1325 /* Initialize and insert the IOTLB entry into the cache. */
1326 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, idDomain, uIovaPage, pPageLookup);
1327
1328 /* Move the entry to the most recently used slot. */
1329 iommuAmdIotlbEntryMoveToMru(pThisR3, pIotlbe);
1330 }
1331 else
1332 {
1333 /* Grab an unused IOTLB entry from the pre-allocated list. */
1334 PIOTLBE pIotlbe = &pThisR3->paIotlbes[pThisR3->idxUnusedIotlbe];
1335 ++pThisR3->idxUnusedIotlbe;
1336
1337 /* Initialize and insert the IOTLB entry into the cache. */
1338 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, idDomain, uIovaPage, pPageLookup);
1339
1340 /* Add the entry to the most recently used slot. */
1341 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1342 }
1343}
1344
1345
1346/**
1347 * Removes all IOTLB entries from the cache.
1348 *
1349 * @param pDevIns The IOMMU instance data.
1350 */
1351static void iommuAmdIotlbRemoveAll(PPDMDEVINS pDevIns)
1352{
1353 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1354 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1355 IOMMU_CACHE_LOCK(pDevIns, pThis);
1356
1357 if (pThisR3->cCachedIotlbes > 0)
1358 {
1359 RTAvlU64Destroy(&pThisR3->TreeIotlbe, iommuAmdIotlbEntryDestroy, NULL /* pvParam */);
1360 RTListInit(&pThisR3->LstLruIotlbe);
1361 pThisR3->idxUnusedIotlbe = 0;
1362 pThisR3->cCachedIotlbes = 0;
1363 STAM_COUNTER_RESET(&pThis->StatIotlbeCached);
1364 }
1365
1366 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1367}
1368
1369
1370/**
1371 * Removes IOTLB entries for the range of I/O virtual addresses and the specified
1372 * domain ID from the cache.
1373 *
1374 * @param pDevIns The IOMMU instance data.
1375 * @param idDomain The domain ID.
1376 * @param uIova The I/O virtual address to invalidate.
1377 * @param cbInvalidate The size of the invalidation (must be 4K aligned).
1378 */
1379static void iommuAmdIotlbRemoveRange(PPDMDEVINS pDevIns, uint16_t idDomain, uint64_t uIova, size_t cbInvalidate)
1380{
1381 /* Validate. */
1382 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1383 Assert(!(cbInvalidate & X86_PAGE_4K_OFFSET_MASK));
1384 Assert(cbInvalidate >= X86_PAGE_4K_SIZE);
1385
1386 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1387 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1388 IOMMU_CACHE_LOCK(pDevIns, pThis);
1389
1390 do
1391 {
1392 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1393 PIOTLBE pIotlbe = iommuAmdIotlbEntryRemove(pThis, pThisR3, uKey);
1394 if (pIotlbe)
1395 iommuAmdIotlbEntryMoveToLru(pThisR3, pIotlbe);
1396 uIova += X86_PAGE_4K_SIZE;
1397 cbInvalidate -= X86_PAGE_4K_SIZE;
1398 } while (cbInvalidate > 0);
1399
1400 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1401}
1402
1403
1404/**
1405 * Removes all IOTLB entries for the specified domain ID.
1406 *
1407 * @param pDevIns The IOMMU instance data.
1408 * @param idDomain The domain ID.
1409 */
1410static void iommuAmdIotlbRemoveDomainId(PPDMDEVINS pDevIns, uint16_t idDomain)
1411{
1412 /*
1413 * We need to iterate the tree and search based on the domain ID.
1414 * But it seems we cannot remove items while iterating the tree.
1415 * Thus, we simply mark entries for eviction later but move them to the LRU
1416 * so they will eventually get evicted and re-cycled as the cache gets re-populated.
1417 */
1418 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1419 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1420 IOMMU_CACHE_LOCK(pDevIns, pThis);
1421
1422 IOTLBEFLUSHARG Args;
1423 Args.pIommuR3 = pThisR3;
1424 Args.idDomain = idDomain;
1425 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdIotlbEntryRemoveDomainId, &Args);
1426
1427 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1428}
1429
1430
1431/**
1432 * Adds or updates IOTLB entries for the given range of I/O virtual addresses.
1433 *
1434 * @param pDevIns The IOMMU instance data.
1435 * @param idDomain The domain ID.
1436 * @param uIovaPage The I/O virtual address (must be 4K aligned).
1437 * @param cbContiguous The size of the access.
1438 * @param pAddrOut The translated I/O address lookup.
1439 *
1440 * @remarks All pages in the range specified by @c cbContiguous must have identical
1441 * permissions and page sizes.
1442 */
1443static void iommuAmdIotlbAddRange(PPDMDEVINS pDevIns, uint16_t idDomain, uint64_t uIovaPage, size_t cbContiguous,
1444 PCIOPAGELOOKUP pAddrOut)
1445{
1446 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
1447
1448 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1449 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1450
1451 IOPAGELOOKUP PageLookup;
1452 PageLookup.GCPhysSpa = pAddrOut->GCPhysSpa & X86_PAGE_4K_BASE_MASK;
1453 PageLookup.cShift = pAddrOut->cShift;
1454 PageLookup.fPerm = pAddrOut->fPerm;
1455
1456 size_t const cbIova = RT_ALIGN_Z(cbContiguous, X86_PAGE_4K_SIZE);
1457 Assert(!(cbIova & X86_PAGE_4K_OFFSET_MASK));
1458 Assert(cbIova >= X86_PAGE_4K_SIZE);
1459
1460 size_t cPages = cbIova / X86_PAGE_4K_SIZE;
1461 cPages = RT_MIN(cPages, IOMMU_IOTLBE_MAX);
1462
1463 IOMMU_CACHE_LOCK(pDevIns, pThis);
1464 /** @todo Re-check DTE cache? */
1465 /*
1466 * Add IOTLB entries for every page in the access.
1467 * The page size and permissions are assumed to be identical to every
1468 * page in this access.
1469 */
1470 while (cPages > 0)
1471 {
1472 iommuAmdIotlbAdd(pThis, pThisR3, idDomain, uIovaPage, &PageLookup);
1473 uIovaPage += X86_PAGE_4K_SIZE;
1474 PageLookup.GCPhysSpa += X86_PAGE_4K_SIZE;
1475 --cPages;
1476 }
1477 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1478}
1479#endif /* IOMMU_WITH_IOTLBE_CACHE */
1480
1481
1482#ifdef IOMMU_WITH_IRTE_CACHE
1483/**
1484 * Looks up an IRTE cache entry.
1485 *
1486 * @returns Index of the found entry, or cache capacity if not found.
1487 * @param pThis The shared IOMMU device state.
1488 * @param idDevice The device ID (bus, device, function).
1489 * @param offIrte The offset into the interrupt remap table.
1490 */
1491static uint16_t iommuAmdIrteCacheEntryLookup(PCIOMMU pThis, uint16_t idDevice, uint16_t offIrte)
1492{
1493 /** @todo Consider sorting and binary search when the cache capacity grows.
1494 * For the IRTE cache this should be okay since typically guests do not alter the
1495 * interrupt remapping once programmed, so hopefully sorting shouldn't happen
1496 * often. */
1497 uint32_t const uKey = IOMMU_IRTE_CACHE_KEY_MAKE(idDevice, offIrte);
1498 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1499 for (uint16_t i = 0; i < cIrteCache; i++)
1500 if (pThis->aIrteCache[i].uKey == uKey)
1501 return i;
1502 return cIrteCache;
1503}
1504
1505
1506/**
1507 * Gets a free/unused IRTE cache entry.
1508 *
1509 * @returns The index of an unused entry, or cache capacity if the cache is full.
1510 * @param pThis The shared IOMMU device state.
1511 */
1512static uint16_t iommuAmdIrteCacheEntryGetUnused(PCIOMMU pThis)
1513{
1514 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1515 for (uint16_t i = 0; i < cIrteCache; i++)
1516 if (pThis->aIrteCache[i].uKey == IOMMU_IRTE_CACHE_KEY_NIL)
1517 {
1518 Assert(!pThis->aIrteCache[i].Irte.u32);
1519 return i;
1520 }
1521 return cIrteCache;
1522}
1523
1524
1525/**
1526 * Looks up the IRTE cache for the given MSI.
1527 *
1528 * @returns VBox status code.
1529 * @param pDevIns The IOMMU instance data.
1530 * @param idDevice The device ID (bus, device, function).
1531 * @param enmOp The IOMMU operation being performed.
1532 * @param pMsiIn The source MSI.
1533 * @param pMsiOut Where to store the remapped MSI.
1534 */
1535static int iommuAmdIrteCacheLookup(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1536{
1537 RT_NOREF(enmOp); /* May need it if we have to report errors (currently we fallback to the slower path to do that). */
1538
1539 int rc = VERR_NOT_FOUND;
1540 /* Deal with such cases in the slower/fallback path. */
1541 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
1542 { /* likely */ }
1543 else
1544 return rc;
1545
1546 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1547 IOMMU_CACHE_LOCK(pDevIns, pThis);
1548
1549 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, idDevice);
1550 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
1551 {
1552 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
1553 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1554 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1555 {
1556 Assert((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE); /* Paranoia. */
1557
1558 /* Currently, we only cache remapping of fixed and arbitrated interrupts. */
1559 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
1560 if (u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
1561 {
1562 uint8_t const uIntrCtrl = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT)
1563 & IOMMU_DTE_CACHE_F_INTR_CTRL_MASK;
1564 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
1565 {
1566 /* Interrupt table length has been verified prior to adding entries to the cache. */
1567 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(pMsiIn->Data.u32);
1568 uint16_t const idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, idDevice, offIrte);
1569 if (idxIrteCache < RT_ELEMENTS(pThis->aIrteCache))
1570 {
1571 PCIRTE_T pIrte = &pThis->aIrteCache[idxIrteCache].Irte;
1572 Assert(pIrte->n.u1RemapEnable);
1573 Assert(pIrte->n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO);
1574 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, pIrte);
1575 rc = VINF_SUCCESS;
1576 }
1577 }
1578 else if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
1579 {
1580 *pMsiOut = *pMsiIn;
1581 rc = VINF_SUCCESS;
1582 }
1583 }
1584 }
1585 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
1586 {
1587 *pMsiOut = *pMsiIn;
1588 rc = VINF_SUCCESS;
1589 }
1590 }
1591
1592 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1593 return rc;
1594}
1595
1596
1597/**
1598 * Adds or updates the IRTE cache for the given IRTE.
1599 *
1600 * @returns VBox status code.
1601 * @retval VERR_OUT_OF_RESOURCES if the cache is full.
1602 *
1603 * @param pDevIns The IOMMU instance data.
1604 * @param idDevice The device ID (bus, device, function).
1605 * @param offIrte The offset into the interrupt remap table.
1606 * @param pIrte The IRTE to cache.
1607 */
1608static int iommuAmdIrteCacheAdd(PPDMDEVINS pDevIns, uint16_t idDevice, uint16_t offIrte, PCIRTE_T pIrte)
1609{
1610 Assert(offIrte != 0xffff); /* Shouldn't be a valid IRTE table offset since sizeof(IRTE) is a multiple of 4. */
1611
1612 int rc = VINF_SUCCESS;
1613 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1614 Assert(idDevice != pThis->uPciAddress);
1615 IOMMU_CACHE_LOCK(pDevIns, pThis);
1616
1617 /* Find an existing entry or get an unused slot. */
1618 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1619 uint16_t idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, idDevice, offIrte);
1620 if ( idxIrteCache < cIrteCache
1621 || (idxIrteCache = iommuAmdIrteCacheEntryGetUnused(pThis)) < cIrteCache)
1622 {
1623 pThis->aIrteCache[idxIrteCache].uKey = IOMMU_IRTE_CACHE_KEY_MAKE(idDevice, offIrte);
1624 pThis->aIrteCache[idxIrteCache].Irte = *pIrte;
1625 }
1626 else
1627 rc = VERR_OUT_OF_RESOURCES;
1628
1629 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1630 return rc;
1631}
1632
1633
1634# ifdef IN_RING3
1635/**
1636 * Removes IRTE cache entries for the given device ID.
1637 *
1638 * @param pDevIns The IOMMU instance data.
1639 * @param idDevice The device ID (bus, device, function).
1640 */
1641static void iommuAmdIrteCacheRemove(PPDMDEVINS pDevIns, uint16_t idDevice)
1642{
1643 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1644 IOMMU_CACHE_LOCK(pDevIns, pThis);
1645 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1646 for (uint16_t i = 0; i < cIrteCache; i++)
1647 {
1648 PIRTECACHE pIrteCache = &pThis->aIrteCache[i];
1649 if (idDevice == IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(pIrteCache->uKey))
1650 {
1651 pIrteCache->uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1652 pIrteCache->Irte.u32 = 0;
1653 /* There could multiple IRTE entries for a device ID, continue searching. */
1654 }
1655 }
1656 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1657}
1658
1659
1660/**
1661 * Removes all IRTE cache entries.
1662 *
1663 * @param pDevIns The IOMMU instance data.
1664 */
1665static void iommuAmdIrteCacheRemoveAll(PPDMDEVINS pDevIns)
1666{
1667 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1668 IOMMU_CACHE_LOCK(pDevIns, pThis);
1669 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1670 for (uint16_t i = 0; i < cIrteCache; i++)
1671 {
1672 pThis->aIrteCache[i].uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1673 pThis->aIrteCache[i].Irte.u32 = 0;
1674 }
1675 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1676}
1677# endif /* IN_RING3 */
1678#endif /* IOMMU_WITH_IRTE_CACHE */
1679
1680
1681/**
1682 * Atomically reads the control register without locking the IOMMU device.
1683 *
1684 * @returns The control register.
1685 * @param pThis The shared IOMMU device state.
1686 */
1687DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrlUnlocked(PCIOMMU pThis)
1688{
1689 IOMMU_CTRL_T Ctrl;
1690 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
1691 return Ctrl;
1692}
1693
1694
1695/**
1696 * Returns whether MSI is enabled for the IOMMU.
1697 *
1698 * @returns Whether MSI is enabled.
1699 * @param pDevIns The IOMMU device instance.
1700 *
1701 * @note There should be a PCIDevXxx function for this.
1702 */
1703static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
1704{
1705 MSI_CAP_HDR_T MsiCapHdr;
1706 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
1707 return MsiCapHdr.n.u1MsiEnable;
1708}
1709
1710
1711/**
1712 * Signals a PCI target abort.
1713 *
1714 * @param pDevIns The IOMMU device instance.
1715 */
1716static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
1717{
1718 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1719 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
1720 PDMPciDevSetStatus(pPciDev, u16Status);
1721}
1722
1723
1724/**
1725 * Wakes up the command thread if there are commands to be processed.
1726 *
1727 * @param pDevIns The IOMMU device instance.
1728 *
1729 * @remarks The IOMMU lock must be held while calling this!
1730 */
1731static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1732{
1733 Log4Func(("\n"));
1734
1735 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1736 if ( pThis->Status.n.u1CmdBufRunning
1737 && pThis->CmdBufTailPtr.n.off != pThis->CmdBufHeadPtr.n.off
1738 && !ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, true))
1739 {
1740 Log4Func(("Signaling command thread\n"));
1741 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
1742 }
1743}
1744
1745
1746/**
1747 * Reads the Device Table Base Address Register.
1748 */
1749static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1750{
1751 RT_NOREF(pDevIns, offReg);
1752 *pu64Value = pThis->aDevTabBaseAddrs[0].u64;
1753 return VINF_SUCCESS;
1754}
1755
1756
1757/**
1758 * Reads the Command Buffer Base Address Register.
1759 */
1760static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1761{
1762 RT_NOREF(pDevIns, offReg);
1763 *pu64Value = pThis->CmdBufBaseAddr.u64;
1764 return VINF_SUCCESS;
1765}
1766
1767
1768/**
1769 * Reads the Event Log Base Address Register.
1770 */
1771static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1772{
1773 RT_NOREF(pDevIns, offReg);
1774 *pu64Value = pThis->EvtLogBaseAddr.u64;
1775 return VINF_SUCCESS;
1776}
1777
1778
1779/**
1780 * Reads the Control Register.
1781 */
1782static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1783{
1784 RT_NOREF(pDevIns, offReg);
1785 *pu64Value = pThis->Ctrl.u64;
1786 return VINF_SUCCESS;
1787}
1788
1789
1790/**
1791 * Reads the Exclusion Range Base Address Register.
1792 */
1793static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1794{
1795 RT_NOREF(pDevIns, offReg);
1796 *pu64Value = pThis->ExclRangeBaseAddr.u64;
1797 return VINF_SUCCESS;
1798}
1799
1800
1801/**
1802 * Reads to the Exclusion Range Limit Register.
1803 */
1804static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1805{
1806 RT_NOREF(pDevIns, offReg);
1807 *pu64Value = pThis->ExclRangeLimit.u64;
1808 return VINF_SUCCESS;
1809}
1810
1811
1812/**
1813 * Reads to the Extended Feature Register.
1814 */
1815static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1816{
1817 RT_NOREF(pDevIns, offReg);
1818 *pu64Value = pThis->ExtFeat.u64;
1819 return VINF_SUCCESS;
1820}
1821
1822
1823/**
1824 * Reads to the PPR Log Base Address Register.
1825 */
1826static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1827{
1828 RT_NOREF(pDevIns, offReg);
1829 *pu64Value = pThis->PprLogBaseAddr.u64;
1830 return VINF_SUCCESS;
1831}
1832
1833
1834/**
1835 * Writes the Hardware Event Register (Hi).
1836 */
1837static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1838{
1839 RT_NOREF(pDevIns, offReg);
1840 *pu64Value = pThis->HwEvtHi.u64;
1841 return VINF_SUCCESS;
1842}
1843
1844
1845/**
1846 * Reads the Hardware Event Register (Lo).
1847 */
1848static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1849{
1850 RT_NOREF(pDevIns, offReg);
1851 *pu64Value = pThis->HwEvtLo;
1852 return VINF_SUCCESS;
1853}
1854
1855
1856/**
1857 * Reads the Hardware Event Status Register.
1858 */
1859static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1860{
1861 RT_NOREF(pDevIns, offReg);
1862 *pu64Value = pThis->HwEvtStatus.u64;
1863 return VINF_SUCCESS;
1864}
1865
1866
1867/**
1868 * Reads to the GA Log Base Address Register.
1869 */
1870static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1871{
1872 RT_NOREF(pDevIns, offReg);
1873 *pu64Value = pThis->GALogBaseAddr.u64;
1874 return VINF_SUCCESS;
1875}
1876
1877
1878/**
1879 * Reads to the PPR Log B Base Address Register.
1880 */
1881static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1882{
1883 RT_NOREF(pDevIns, offReg);
1884 *pu64Value = pThis->PprLogBBaseAddr.u64;
1885 return VINF_SUCCESS;
1886}
1887
1888
1889/**
1890 * Reads to the Event Log B Base Address Register.
1891 */
1892static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1893{
1894 RT_NOREF(pDevIns, offReg);
1895 *pu64Value = pThis->EvtLogBBaseAddr.u64;
1896 return VINF_SUCCESS;
1897}
1898
1899
1900/**
1901 * Reads the Device Table Segment Base Address Register.
1902 */
1903static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1904{
1905 RT_NOREF(pDevIns);
1906
1907 /* Figure out which segment is being written. */
1908 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1909 uint8_t const idxSegment = offSegment + 1;
1910 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1911
1912 *pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
1913 return VINF_SUCCESS;
1914}
1915
1916
1917/**
1918 * Reads the Device Specific Feature Extension (DSFX) Register.
1919 */
1920static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1921{
1922 RT_NOREF(pDevIns, offReg);
1923 *pu64Value = pThis->DevSpecificFeat.u64;
1924 return VINF_SUCCESS;
1925}
1926
1927/**
1928 * Reads the Device Specific Control Extension (DSCX) Register.
1929 */
1930static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1931{
1932 RT_NOREF(pDevIns, offReg);
1933 *pu64Value = pThis->DevSpecificCtrl.u64;
1934 return VINF_SUCCESS;
1935}
1936
1937
1938/**
1939 * Reads the Device Specific Status Extension (DSSX) Register.
1940 */
1941static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1942{
1943 RT_NOREF(pDevIns, offReg);
1944 *pu64Value = pThis->DevSpecificStatus.u64;
1945 return VINF_SUCCESS;
1946}
1947
1948
1949/**
1950 * Reads the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1951 */
1952static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1953{
1954 RT_NOREF(pDevIns, offReg);
1955 uint32_t const uLo = pThis->MiscInfo.au32[0];
1956 uint32_t const uHi = pThis->MiscInfo.au32[1];
1957 *pu64Value = RT_MAKE_U64(uLo, uHi);
1958 return VINF_SUCCESS;
1959}
1960
1961
1962/**
1963 * Reads the MSI Capability Header Register (32-bit) and the MSI Address (Lo)
1964 * Register (32-bit).
1965 */
1966static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1967{
1968 RT_NOREF(pThis, offReg);
1969 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1970 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1971 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1972 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1973 *pu64Value = RT_MAKE_U64(uLo, uHi);
1974 return VINF_SUCCESS;
1975}
1976
1977
1978/**
1979 * Reads the MSI Address (Hi) Register (32-bit) and the MSI data register (32-bit).
1980 */
1981static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1982{
1983 RT_NOREF(pThis, offReg);
1984 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1985 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1986 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1987 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1988 *pu64Value = RT_MAKE_U64(uLo, uHi);
1989 return VINF_SUCCESS;
1990}
1991
1992
1993/**
1994 * Reads the Command Buffer Head Pointer Register.
1995 */
1996static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1997{
1998 RT_NOREF(pDevIns, offReg);
1999 *pu64Value = pThis->CmdBufHeadPtr.u64;
2000 return VINF_SUCCESS;
2001}
2002
2003
2004/**
2005 * Reads the Command Buffer Tail Pointer Register.
2006 */
2007static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
2008{
2009 RT_NOREF(pDevIns, offReg);
2010 *pu64Value = pThis->CmdBufTailPtr.u64;
2011 return VINF_SUCCESS;
2012}
2013
2014
2015/**
2016 * Reads the Event Log Head Pointer Register.
2017 */
2018static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
2019{
2020 RT_NOREF(pDevIns, offReg);
2021 *pu64Value = pThis->EvtLogHeadPtr.u64;
2022 return VINF_SUCCESS;
2023}
2024
2025
2026/**
2027 * Reads the Event Log Tail Pointer Register.
2028 */
2029static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
2030{
2031 RT_NOREF(pDevIns, offReg);
2032 *pu64Value = pThis->EvtLogTailPtr.u64;
2033 return VINF_SUCCESS;
2034}
2035
2036
2037/**
2038 * Reads the Status Register.
2039 */
2040static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
2041{
2042 RT_NOREF(pDevIns, offReg);
2043 *pu64Value = pThis->Status.u64;
2044 return VINF_SUCCESS;
2045}
2046
2047
2048/**
2049 * Writes the Device Table Base Address Register.
2050 */
2051static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2052{
2053 RT_NOREF(pDevIns, offReg);
2054
2055 /* Mask out all unrecognized bits. */
2056 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
2057
2058 /* Update the register. */
2059 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
2060
2061 /* Paranoia. */
2062 Assert(pThis->aDevTabBaseAddrs[0].n.u9Size <= g_auDevTabSegMaxSizes[0]);
2063 return VINF_SUCCESS;
2064}
2065
2066
2067/**
2068 * Writes the Command Buffer Base Address Register.
2069 */
2070static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2071{
2072 RT_NOREF(pDevIns, offReg);
2073
2074 /*
2075 * While this is not explicitly specified like the event log base address register,
2076 * the AMD IOMMU spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
2077 * Inconsistent specs :/
2078 */
2079 if (pThis->Status.n.u1CmdBufRunning)
2080 {
2081 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2082 return VINF_SUCCESS;
2083 }
2084
2085 /* Mask out all unrecognized bits. */
2086 CMD_BUF_BAR_T CmdBufBaseAddr;
2087 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
2088
2089 /* Validate the length. */
2090 if (CmdBufBaseAddr.n.u4Len >= 8)
2091 {
2092 /* Update the register. */
2093 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
2094
2095 /*
2096 * Writing the command buffer base address, clears the command buffer head and tail pointers.
2097 * See AMD IOMMU spec. 2.4 "Commands".
2098 */
2099 pThis->CmdBufHeadPtr.u64 = 0;
2100 pThis->CmdBufTailPtr.u64 = 0;
2101 }
2102 else
2103 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
2104
2105 return VINF_SUCCESS;
2106}
2107
2108
2109/**
2110 * Writes the Event Log Base Address Register.
2111 */
2112static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2113{
2114 RT_NOREF(pDevIns, offReg);
2115
2116 /*
2117 * IOMMU behavior is undefined when software writes this register when event logging is running.
2118 * In our emulation, we ignore the write entirely.
2119 * See AMD IOMMU spec. "Event Log Base Address Register".
2120 */
2121 if (pThis->Status.n.u1EvtLogRunning)
2122 {
2123 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
2124 return VINF_SUCCESS;
2125 }
2126
2127 /* Mask out all unrecognized bits. */
2128 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
2129 EVT_LOG_BAR_T EvtLogBaseAddr;
2130 EvtLogBaseAddr.u64 = u64Value;
2131
2132 /* Validate the length. */
2133 if (EvtLogBaseAddr.n.u4Len >= 8)
2134 {
2135 /* Update the register. */
2136 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
2137
2138 /*
2139 * Writing the event log base address, clears the event log head and tail pointers.
2140 * See AMD IOMMU spec. 2.5 "Event Logging".
2141 */
2142 pThis->EvtLogHeadPtr.u64 = 0;
2143 pThis->EvtLogTailPtr.u64 = 0;
2144 }
2145 else
2146 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
2147
2148 return VINF_SUCCESS;
2149}
2150
2151
2152/**
2153 * Writes the Control Register.
2154 */
2155static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2156{
2157 RT_NOREF(pDevIns, offReg);
2158
2159 /* Mask out all unrecognized bits. */
2160 u64Value &= IOMMU_CTRL_VALID_MASK;
2161 IOMMU_CTRL_T NewCtrl;
2162 NewCtrl.u64 = u64Value;
2163
2164 /* Ensure the device table segments are within limits. */
2165 if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
2166 {
2167 IOMMU_CTRL_T const OldCtrl = pThis->Ctrl;
2168
2169 /* Update the register. */
2170 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
2171
2172 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
2173 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
2174
2175 /* Enable or disable event logging when the bit transitions. */
2176 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
2177 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
2178 if ( fOldEvtLogEn != fNewEvtLogEn
2179 || fOldIommuEn != fNewIommuEn)
2180 {
2181 if ( fNewIommuEn
2182 && fNewEvtLogEn)
2183 {
2184 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
2185 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
2186 }
2187 else
2188 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
2189 }
2190
2191 /* Enable or disable command buffer processing when the bit transitions. */
2192 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
2193 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
2194 if ( fOldCmdBufEn != fNewCmdBufEn
2195 || fOldIommuEn != fNewIommuEn)
2196 {
2197 if ( fNewCmdBufEn
2198 && fNewIommuEn)
2199 {
2200 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
2201 LogFunc(("Command buffer enabled\n"));
2202
2203 /* Wake up the command thread to start processing commands if any. */
2204 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2205 }
2206 else
2207 {
2208 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2209 LogFunc(("Command buffer disabled\n"));
2210 }
2211 }
2212 }
2213 else
2214 {
2215 LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
2216 pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
2217 }
2218
2219 return VINF_SUCCESS;
2220}
2221
2222
2223/**
2224 * Writes to the Exclusion Range Base Address Register.
2225 */
2226static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2227{
2228 RT_NOREF(pDevIns, offReg);
2229 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
2230 return VINF_SUCCESS;
2231}
2232
2233
2234/**
2235 * Writes to the Exclusion Range Limit Register.
2236 */
2237static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2238{
2239 RT_NOREF(pDevIns, offReg);
2240 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
2241 u64Value |= UINT64_C(0xfff);
2242 pThis->ExclRangeLimit.u64 = u64Value;
2243 return VINF_SUCCESS;
2244}
2245
2246
2247/**
2248 * Writes the Hardware Event Register (Hi).
2249 */
2250static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2251{
2252 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2253 RT_NOREF(pDevIns, offReg);
2254 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
2255 pThis->HwEvtHi.u64 = u64Value;
2256 return VINF_SUCCESS;
2257}
2258
2259
2260/**
2261 * Writes the Hardware Event Register (Lo).
2262 */
2263static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2264{
2265 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2266 RT_NOREF(pDevIns, offReg);
2267 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
2268 pThis->HwEvtLo = u64Value;
2269 return VINF_SUCCESS;
2270}
2271
2272
2273/**
2274 * Writes the Hardware Event Status Register.
2275 */
2276static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2277{
2278 RT_NOREF(pDevIns, offReg);
2279
2280 /* Mask out all unrecognized bits. */
2281 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
2282
2283 /*
2284 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
2285 * If the current status bits or the bits being written are both 0, we've nothing to do.
2286 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
2287 */
2288 uint64_t HwStatus = pThis->HwEvtStatus.u64;
2289 if (!(HwStatus & RT_BIT(0)))
2290 return VINF_SUCCESS;
2291 if (u64Value & HwStatus & RT_BIT_64(0))
2292 HwStatus &= ~RT_BIT_64(0);
2293 if (u64Value & HwStatus & RT_BIT_64(1))
2294 HwStatus &= ~RT_BIT_64(1);
2295
2296 /* Update the register. */
2297 pThis->HwEvtStatus.u64 = HwStatus;
2298 return VINF_SUCCESS;
2299}
2300
2301
2302/**
2303 * Writes the Device Table Segment Base Address Register.
2304 */
2305static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2306{
2307 RT_NOREF(pDevIns);
2308
2309 /* Figure out which segment is being written. */
2310 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
2311 uint8_t const idxSegment = offSegment + 1;
2312 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2313
2314 /* Mask out all unrecognized bits. */
2315 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
2316 DEV_TAB_BAR_T DevTabSegBar;
2317 DevTabSegBar.u64 = u64Value;
2318
2319 /* Validate the size. */
2320 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
2321 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
2322 if (uSegSize <= uMaxSegSize)
2323 {
2324 /* Update the register. */
2325 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
2326 }
2327 else
2328 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
2329
2330 return VINF_SUCCESS;
2331}
2332
2333
2334/**
2335 * Writes the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
2336 */
2337static VBOXSTRICTRC iommuAmdDevMsiVector_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2338{
2339 RT_NOREF(pDevIns, offReg);
2340
2341 /* MSI Vector Register 0 is read-only. */
2342 /* MSI Vector Register 1. */
2343 uint32_t const uReg = u64Value >> 32;
2344 pThis->MiscInfo.au32[1] = uReg & IOMMU_MSI_VECTOR_1_VALID_MASK;
2345 return VINF_SUCCESS;
2346}
2347
2348
2349/**
2350 * Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
2351 * Register (32-bit).
2352 */
2353static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2354{
2355 RT_NOREF(pThis, offReg);
2356 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2357 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2358
2359 /* MSI capability header. */
2360 {
2361 uint32_t const uReg = u64Value;
2362 MSI_CAP_HDR_T MsiCapHdr;
2363 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
2364 MsiCapHdr.n.u1MsiEnable = RT_BOOL(uReg & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
2365 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
2366 }
2367
2368 /* MSI Address Lo. */
2369 {
2370 uint32_t const uReg = u64Value >> 32;
2371 uint32_t const uMsiAddrLo = uReg & VBOX_MSI_ADDR_VALID_MASK;
2372 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
2373 }
2374
2375 return VINF_SUCCESS;
2376}
2377
2378
2379/**
2380 * Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
2381 */
2382static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2383{
2384 RT_NOREF(pThis, offReg);
2385 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2386 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2387
2388 /* MSI Address Hi. */
2389 {
2390 uint32_t const uReg = u64Value;
2391 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, uReg);
2392 }
2393
2394 /* MSI Data. */
2395 {
2396 uint32_t const uReg = u64Value >> 32;
2397 uint32_t const uMsiData = uReg & VBOX_MSI_DATA_VALID_MASK;
2398 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
2399 }
2400
2401 return VINF_SUCCESS;
2402}
2403
2404
2405/**
2406 * Writes the Command Buffer Head Pointer Register.
2407 */
2408static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2409{
2410 RT_NOREF(pDevIns, offReg);
2411
2412 /*
2413 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
2414 * In our emulation, we ignore the write entirely.
2415 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2416 */
2417 if (pThis->Status.n.u1CmdBufRunning)
2418 {
2419 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2420 return VINF_SUCCESS;
2421 }
2422
2423 /*
2424 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2425 * In our emulation, we ignore the write entirely.
2426 */
2427 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
2428 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2429 Assert(cbBuf <= _512K);
2430 if (offBuf >= cbBuf)
2431 {
2432 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
2433 return VINF_SUCCESS;
2434 }
2435
2436 /* Update the register. */
2437 pThis->CmdBufHeadPtr.au32[0] = offBuf;
2438
2439 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2440
2441 Log4Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
2442 return VINF_SUCCESS;
2443}
2444
2445
2446/**
2447 * Writes the Command Buffer Tail Pointer Register.
2448 */
2449static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2450{
2451 RT_NOREF(pDevIns, offReg);
2452
2453 /*
2454 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2455 * In our emulation, we ignore the write entirely.
2456 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2457 */
2458 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
2459 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2460 Assert(cbBuf <= _512K);
2461 if (offBuf >= cbBuf)
2462 {
2463 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2464 return VINF_SUCCESS;
2465 }
2466
2467 /*
2468 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
2469 * head pointer after adding one or more commands to the buffer.
2470 *
2471 * However, we cannot enforce this strictly because it's legal for software to shrink the
2472 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
2473 * at 0). Software might even make the queue empty by making head and tail equal which is
2474 * allowed. I don't think we can or should try too hard to prevent software shooting itself
2475 * in the foot here. As long as we make sure the offset value is within the circular buffer
2476 * bounds (which we do by masking bits above) it should be sufficient.
2477 */
2478 pThis->CmdBufTailPtr.au32[0] = offBuf;
2479
2480 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2481
2482 Log4Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
2483 return VINF_SUCCESS;
2484}
2485
2486
2487/**
2488 * Writes the Event Log Head Pointer Register.
2489 */
2490static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2491{
2492 RT_NOREF(pDevIns, offReg);
2493
2494 /*
2495 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2496 * In our emulation, we ignore the write entirely.
2497 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2498 */
2499 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
2500 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2501 Assert(cbBuf <= _512K);
2502 if (offBuf >= cbBuf)
2503 {
2504 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2505 return VINF_SUCCESS;
2506 }
2507
2508 /* Update the register. */
2509 pThis->EvtLogHeadPtr.au32[0] = offBuf;
2510
2511 Log4Func(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
2512 return VINF_SUCCESS;
2513}
2514
2515
2516/**
2517 * Writes the Event Log Tail Pointer Register.
2518 */
2519static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2520{
2521 RT_NOREF(pDevIns, offReg);
2522 NOREF(pThis);
2523
2524 /*
2525 * IOMMU behavior is undefined when software writes this register when the event log is running.
2526 * In our emulation, we ignore the write entirely.
2527 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2528 */
2529 if (pThis->Status.n.u1EvtLogRunning)
2530 {
2531 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
2532 return VINF_SUCCESS;
2533 }
2534
2535 /*
2536 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2537 * In our emulation, we ignore the write entirely.
2538 */
2539 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
2540 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2541 Assert(cbBuf <= _512K);
2542 if (offBuf >= cbBuf)
2543 {
2544 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2545 return VINF_SUCCESS;
2546 }
2547
2548 /* Update the register. */
2549 pThis->EvtLogTailPtr.au32[0] = offBuf;
2550
2551 Log4Func(("Set EvtLogTailPtr to %#RX32\n", offBuf));
2552 return VINF_SUCCESS;
2553}
2554
2555
2556/**
2557 * Writes the Status Register.
2558 */
2559static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2560{
2561 RT_NOREF(pDevIns, offReg);
2562
2563 /* Mask out all unrecognized bits. */
2564 u64Value &= IOMMU_STATUS_VALID_MASK;
2565
2566 /*
2567 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
2568 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
2569 */
2570 IOMMU_STATUS_T const OldStatus = pThis->Status;
2571 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
2572 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
2573 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
2574
2575 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
2576
2577 /* Update the register. */
2578 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
2579 return VINF_SUCCESS;
2580}
2581
2582
2583/**
2584 * Register access table 0.
2585 * The MMIO offset of each entry must be a multiple of 8!
2586 */
2587static const IOMMUREGACC g_aRegAccess0[] =
2588{
2589 /* MMIO off. Register name Read function Write function */
2590 { /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w },
2591 { /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w },
2592 { /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w },
2593 { /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w },
2594 { /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w },
2595 { /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w },
2596 { /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL },
2597 { /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL },
2598 { /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w },
2599 { /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w },
2600 { /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w },
2601 { /* 0x58 */ NULL, NULL, NULL },
2602
2603 { /* 0x60 */ "SMI_FLT_0", NULL, NULL },
2604 { /* 0x68 */ "SMI_FLT_1", NULL, NULL },
2605 { /* 0x70 */ "SMI_FLT_2", NULL, NULL },
2606 { /* 0x78 */ "SMI_FLT_3", NULL, NULL },
2607 { /* 0x80 */ "SMI_FLT_4", NULL, NULL },
2608 { /* 0x88 */ "SMI_FLT_5", NULL, NULL },
2609 { /* 0x90 */ "SMI_FLT_6", NULL, NULL },
2610 { /* 0x98 */ "SMI_FLT_7", NULL, NULL },
2611 { /* 0xa0 */ "SMI_FLT_8", NULL, NULL },
2612 { /* 0xa8 */ "SMI_FLT_9", NULL, NULL },
2613 { /* 0xb0 */ "SMI_FLT_10", NULL, NULL },
2614 { /* 0xb8 */ "SMI_FLT_11", NULL, NULL },
2615 { /* 0xc0 */ "SMI_FLT_12", NULL, NULL },
2616 { /* 0xc8 */ "SMI_FLT_13", NULL, NULL },
2617 { /* 0xd0 */ "SMI_FLT_14", NULL, NULL },
2618 { /* 0xd8 */ "SMI_FLT_15", NULL, NULL },
2619
2620 { /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL },
2621 { /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL },
2622 { /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL },
2623 { /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL },
2624
2625 { /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2626 { /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2627 { /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2628 { /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2629 { /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2630 { /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2631 { /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2632
2633 { /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL },
2634 { /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL },
2635 { /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL },
2636
2637 { /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, iommuAmdDevMsiVector_w },
2638 { /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrAndAddrLo_r, iommuAmdMsiCapHdrAndAddrLo_w },
2639 { /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiAndData_r, iommuAmdMsiAddrHiAndData_w },
2640 { /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL },
2641
2642 { /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL },
2643 { /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL },
2644 { /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL },
2645};
2646AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
2647
2648/**
2649 * Register access table 1.
2650 * The MMIO offset of each entry must be a multiple of 8!
2651 */
2652static const IOMMUREGACC g_aRegAccess1[] =
2653{
2654 /* MMIO offset Register name Read function Write function */
2655 { /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL },
2656 { /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL },
2657 { /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL },
2658 { /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL },
2659 { /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL },
2660 { /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL },
2661 { /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL },
2662 { /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL },
2663 { /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL },
2664 { /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL },
2665 { /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL },
2666 { /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL }
2667};
2668AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
2669
2670/**
2671 * Register access table 2.
2672 * The MMIO offset of each entry must be a multiple of 8!
2673 */
2674static const IOMMUREGACC g_aRegAccess2[] =
2675{
2676 /* MMIO offset Register name Read Function Write function */
2677 { /* 0x1ff8 */ "RSVD_REG", NULL, NULL },
2678
2679 { /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w },
2680 { /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w },
2681 { /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w },
2682 { /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w },
2683
2684 { /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w },
2685 { /* 0x2028 */ NULL, NULL, NULL },
2686
2687 { /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL },
2688 { /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL },
2689
2690 { /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL },
2691 { /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL },
2692
2693 { /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL },
2694 { /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL },
2695
2696 { /* 0x2060 */ NULL, NULL, NULL },
2697 { /* 0x2068 */ NULL, NULL, NULL },
2698
2699 { /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL },
2700 { /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL },
2701
2702 { /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL },
2703 { /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL },
2704 { /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL }
2705};
2706AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
2707
2708
2709/**
2710 * Gets the register access structure given its MMIO offset.
2711 *
2712 * @returns The register access structure, or NULL if the offset is invalid.
2713 * @param off The MMIO offset of the register being accessed.
2714 */
2715static PCIOMMUREGACC iommuAmdGetRegAccess(uint32_t off)
2716{
2717 /* Figure out which table the register belongs to and validate its index. */
2718 PCIOMMUREGACC pReg;
2719 if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
2720 {
2721 uint32_t const idxReg = off >> 3;
2722 Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
2723 pReg = &g_aRegAccess0[idxReg];
2724 }
2725 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
2726 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
2727 {
2728 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
2729 Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
2730 pReg = &g_aRegAccess1[idxReg];
2731 }
2732 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
2733 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
2734 {
2735 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
2736 Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
2737 pReg = &g_aRegAccess2[idxReg];
2738 }
2739 else
2740 pReg = NULL;
2741 return pReg;
2742}
2743
2744
2745/**
2746 * Writes an IOMMU register (32-bit and 64-bit).
2747 *
2748 * @returns Strict VBox status code.
2749 * @param pDevIns The IOMMU device instance.
2750 * @param off MMIO byte offset to the register.
2751 * @param cb The size of the write access.
2752 * @param uValue The value being written.
2753 *
2754 * @thread EMT.
2755 */
2756static VBOXSTRICTRC iommuAmdRegisterWrite(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
2757{
2758 /*
2759 * Validate the access in case of IOM bug or incorrect assumption.
2760 */
2761 Assert(off < IOMMU_MMIO_REGION_SIZE);
2762 AssertMsgReturn(cb == 4 || cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
2763 AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
2764
2765 Log4Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
2766
2767 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2768 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2769 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2770 if (pReg)
2771 { /* likely */ }
2772 else
2773 {
2774 LogFunc(("Writing unknown register %#x with %#RX64 -> Ignored\n", off, uValue));
2775 return VINF_SUCCESS;
2776 }
2777
2778 /* If a write handler doesn't exist, it's either a reserved or read-only register. */
2779 if (pReg->pfnWrite)
2780 { /* likely */ }
2781 else
2782 {
2783 LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2784 return VINF_SUCCESS;
2785 }
2786
2787 /*
2788 * If the write access is 64-bits and aligned on a 64-bit boundary, dispatch right away.
2789 * This handles writes to 64-bit registers as well as aligned, 64-bit writes to two
2790 * consecutive 32-bit registers.
2791 */
2792 if (cb == 8)
2793 {
2794 if (!(off & 7))
2795 {
2796 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2797 VBOXSTRICTRC rcStrict = pReg->pfnWrite(pDevIns, pThis, off, uValue);
2798 IOMMU_UNLOCK(pDevIns, pThisCC);
2799 return rcStrict;
2800 }
2801
2802 LogFunc(("Misaligned access while writing register at off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2803 return VINF_SUCCESS;
2804 }
2805
2806 /* We shouldn't get sizes other than 32 bits here as we've specified so with IOM. */
2807 Assert(cb == 4);
2808 if (!(off & 7))
2809 {
2810 VBOXSTRICTRC rcStrict;
2811 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2812
2813 /*
2814 * Lower 32 bits of a 64-bit register or a 32-bit register is being written.
2815 * Merge with higher 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2816 */
2817 uint64_t u64Read;
2818 if (pReg->pfnRead)
2819 rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
2820 else
2821 {
2822 rcStrict = VINF_SUCCESS;
2823 u64Read = 0;
2824 }
2825
2826 if (RT_SUCCESS(rcStrict))
2827 {
2828 uValue = (u64Read & UINT64_C(0xffffffff00000000)) | uValue;
2829 rcStrict = pReg->pfnWrite(pDevIns, pThis, off, uValue);
2830 }
2831 else
2832 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2833
2834 IOMMU_UNLOCK(pDevIns, pThisCC);
2835 return rcStrict;
2836 }
2837
2838 /*
2839 * Higher 32 bits of a 64-bit register or a 32-bit register at a 32-bit boundary is being written.
2840 * Merge with lower 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2841 */
2842 VBOXSTRICTRC rcStrict;
2843 Assert(!(off & 3));
2844 Assert(off & 7);
2845 Assert(off >= 4);
2846 uint64_t u64Read;
2847 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2848 if (pReg->pfnRead)
2849 rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
2850 else
2851 {
2852 rcStrict = VINF_SUCCESS;
2853 u64Read = 0;
2854 }
2855
2856 if (RT_SUCCESS(rcStrict))
2857 {
2858 uValue = (uValue << 32) | (u64Read & UINT64_C(0xffffffff));
2859 rcStrict = pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
2860 }
2861 else
2862 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2863
2864 IOMMU_UNLOCK(pDevIns, pThisCC);
2865 return rcStrict;
2866}
2867
2868
2869/**
2870 * Reads an IOMMU register (64-bit) given its MMIO offset.
2871 *
2872 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
2873 * boundary include the lower half of the subsequent register.
2874 *
2875 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
2876 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
2877 * software will only perform 32-bit reads on those 32-bit registers that are
2878 * aligned on 8-byte boundaries.
2879 *
2880 * @returns Strict VBox status code.
2881 * @param pDevIns The IOMMU device instance.
2882 * @param off The MMIO offset of the register in bytes.
2883 * @param puResult Where to store the value being read.
2884 *
2885 * @thread EMT.
2886 */
2887static VBOXSTRICTRC iommuAmdRegisterRead(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
2888{
2889 Assert(off < IOMMU_MMIO_REGION_SIZE);
2890 Assert(!(off & 7) || !(off & 3));
2891
2892 Log4Func(("off=%#x\n", off));
2893
2894 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2895 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2896 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2897 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); NOREF(pPciDev);
2898
2899 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2900 if (pReg)
2901 { /* likely */ }
2902 else
2903 {
2904 LogFunc(("Reading unknown register %#x -> Ignored\n", off));
2905 return VINF_IOM_MMIO_UNUSED_FF;
2906 }
2907
2908 /* If a read handler doesn't exist, it's a reserved or unknown register. */
2909 if (pReg->pfnRead)
2910 { /* likely */ }
2911 else
2912 {
2913 LogFunc(("Reading reserved or unknown register off=%#x -> returning 0s\n", off));
2914 return VINF_IOM_MMIO_UNUSED_00;
2915 }
2916
2917 /*
2918 * If the read access is aligned on a 64-bit boundary, read the full 64-bits and return.
2919 * The caller takes care of truncating upper 32 bits for 32-bit reads.
2920 */
2921 if (!(off & 7))
2922 {
2923 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
2924 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, puResult);
2925 IOMMU_UNLOCK(pDevIns, pThisCC);
2926 return rcStrict;
2927 }
2928
2929 /*
2930 * High 32 bits of a 64-bit register or a 32-bit register at a non 64-bit boundary is being read.
2931 * Read full 64 bits at the previous 64-bit boundary but return only the high 32 bits.
2932 */
2933 Assert(!(off & 3));
2934 Assert(off & 7);
2935 Assert(off >= 4);
2936 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
2937 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, puResult);
2938 IOMMU_UNLOCK(pDevIns, pThisCC);
2939 if (RT_SUCCESS(rcStrict))
2940 *puResult >>= 32;
2941 else
2942 {
2943 *puResult = 0;
2944 LogFunc(("Reading off %#x during split read failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2945 }
2946
2947 return rcStrict;
2948}
2949
2950
2951/**
2952 * Raises the MSI interrupt for the IOMMU device.
2953 *
2954 * @param pDevIns The IOMMU device instance.
2955 *
2956 * @thread Any.
2957 * @remarks The IOMMU lock may or may not be held.
2958 */
2959static void iommuAmdMsiInterruptRaise(PPDMDEVINS pDevIns)
2960{
2961 LogFlowFunc(("\n"));
2962 if (iommuAmdIsMsiEnabled(pDevIns))
2963 {
2964 LogFunc(("Raising MSI\n"));
2965 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
2966 }
2967}
2968
2969#if 0
2970/**
2971 * Clears the MSI interrupt for the IOMMU device.
2972 *
2973 * @param pDevIns The IOMMU device instance.
2974 *
2975 * @thread Any.
2976 * @remarks The IOMMU lock may or may not be held.
2977 */
2978static void iommuAmdMsiInterruptClear(PPDMDEVINS pDevIns)
2979{
2980 if (iommuAmdIsMsiEnabled(pDevIns))
2981 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
2982}
2983#endif
2984
2985/**
2986 * Writes an entry to the event log in memory.
2987 *
2988 * @returns VBox status code.
2989 * @param pDevIns The IOMMU device instance.
2990 * @param pEvent The event to log.
2991 *
2992 * @thread Any.
2993 * @remarks The IOMMU lock must be held while calling this function.
2994 */
2995static int iommuAmdEvtLogEntryWrite(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2996{
2997 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2998 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2999
3000 IOMMU_LOCK(pDevIns, pThisCC);
3001
3002 /* Check if event logging is active and the log has not overflowed. */
3003 IOMMU_STATUS_T const Status = pThis->Status;
3004 if ( Status.n.u1EvtLogRunning
3005 && !Status.n.u1EvtOverflow)
3006 {
3007 uint32_t const cbEvt = sizeof(*pEvent);
3008
3009 /* Get the offset we need to write the event to in memory (circular buffer offset). */
3010 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
3011 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
3012
3013 /* Ensure we have space in the event log. */
3014 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
3015 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
3016 if (cEvts + 1 < cMaxEvts)
3017 {
3018 /* Write the event log entry to memory. */
3019 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
3020 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
3021 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
3022 if (RT_FAILURE(rc))
3023 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
3024
3025 /* Increment the event log tail pointer. */
3026 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3027 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
3028
3029 /* Indicate that an event log entry was written. */
3030 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
3031
3032 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
3033 if (pThis->Ctrl.n.u1EvtIntrEn)
3034 iommuAmdMsiInterruptRaise(pDevIns);
3035 }
3036 else
3037 {
3038 /* Indicate that the event log has overflowed. */
3039 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
3040
3041 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
3042 if (pThis->Ctrl.n.u1EvtIntrEn)
3043 iommuAmdMsiInterruptRaise(pDevIns);
3044 }
3045 }
3046
3047 IOMMU_UNLOCK(pDevIns, pThisCC);
3048
3049 return VINF_SUCCESS;
3050}
3051
3052
3053/**
3054 * Sets an event in the hardware error registers.
3055 *
3056 * @param pDevIns The IOMMU device instance.
3057 * @param pEvent The event.
3058 *
3059 * @thread Any.
3060 */
3061static void iommuAmdHwErrorSet(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3062{
3063 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3064 if (pThis->ExtFeat.n.u1HwErrorSup)
3065 {
3066 if (pThis->HwEvtStatus.n.u1Valid)
3067 pThis->HwEvtStatus.n.u1Overflow = 1;
3068 pThis->HwEvtStatus.n.u1Valid = 1;
3069 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
3070 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
3071 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
3072 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
3073 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
3074 }
3075}
3076
3077
3078/**
3079 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
3080 *
3081 * @param idDevice The device ID (bus, device, function).
3082 * @param idDomain The domain ID.
3083 * @param GCPhysPtEntity The system physical address of the page table
3084 * entity.
3085 * @param enmOp The IOMMU operation being performed.
3086 * @param pEvtPageTabHwErr Where to store the initialized event.
3087 */
3088static void iommuAmdPageTabHwErrorEventInit(uint16_t idDevice, uint16_t idDomain, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
3089 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3090{
3091 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
3092 pEvtPageTabHwErr->n.u16DevId = idDevice;
3093 pEvtPageTabHwErr->n.u16DomainOrPasidLo = idDomain;
3094 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
3095 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3096 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3097 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3098 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3099 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
3100 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
3101}
3102
3103
3104/**
3105 * Raises a PAGE_TAB_HARDWARE_ERROR event.
3106 *
3107 * @param pDevIns The IOMMU device instance.
3108 * @param enmOp The IOMMU operation being performed.
3109 * @param pEvtPageTabHwErr The page table hardware error event.
3110 *
3111 * @thread Any.
3112 */
3113static void iommuAmdPageTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3114{
3115 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
3116 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
3117
3118 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3119 IOMMU_LOCK(pDevIns, pThisCC);
3120
3121 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3122 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3123 if (enmOp != IOMMUOP_CMD)
3124 iommuAmdSetPciTargetAbort(pDevIns);
3125
3126 IOMMU_UNLOCK(pDevIns, pThisCC);
3127
3128 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. idDevice=%#x idDomain=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
3129 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
3130 pEvtPageTabHwErr->n.u2Type));
3131}
3132
3133
3134#ifdef IN_RING3
3135/**
3136 * Initializes a COMMAND_HARDWARE_ERROR event.
3137 *
3138 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
3139 * @param pEvtCmdHwErr Where to store the initialized event.
3140 */
3141static void iommuAmdCmdHwErrorEventInit(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3142{
3143 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
3144 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
3145 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
3146 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
3147}
3148
3149
3150/**
3151 * Raises a COMMAND_HARDWARE_ERROR event.
3152 *
3153 * @param pDevIns The IOMMU device instance.
3154 * @param pEvtCmdHwErr The command hardware error event.
3155 *
3156 * @thread Any.
3157 */
3158static void iommuAmdCmdHwErrorEventRaise(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3159{
3160 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
3161 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
3162 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3163
3164 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3165 IOMMU_LOCK(pDevIns, pThisCC);
3166
3167 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3168 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3169 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3170
3171 IOMMU_UNLOCK(pDevIns, pThisCC);
3172
3173 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
3174}
3175#endif /* IN_RING3 */
3176
3177
3178/**
3179 * Initializes a DEV_TAB_HARDWARE_ERROR event.
3180 *
3181 * @param idDevice The device ID (bus, device, function).
3182 * @param GCPhysDte The system physical address of the failed device table
3183 * access.
3184 * @param enmOp The IOMMU operation being performed.
3185 * @param pEvtDevTabHwErr Where to store the initialized event.
3186 */
3187static void iommuAmdDevTabHwErrorEventInit(uint16_t idDevice, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
3188 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3189{
3190 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
3191 pEvtDevTabHwErr->n.u16DevId = idDevice;
3192 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3193 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
3194 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3195 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3196 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3197 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
3198 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
3199}
3200
3201
3202/**
3203 * Raises a DEV_TAB_HARDWARE_ERROR event.
3204 *
3205 * @param pDevIns The IOMMU device instance.
3206 * @param enmOp The IOMMU operation being performed.
3207 * @param pEvtDevTabHwErr The device table hardware error event.
3208 *
3209 * @thread Any.
3210 */
3211static void iommuAmdDevTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3212{
3213 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
3214 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
3215
3216 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3217 IOMMU_LOCK(pDevIns, pThisCC);
3218
3219 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3220 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3221 if (enmOp != IOMMUOP_CMD)
3222 iommuAmdSetPciTargetAbort(pDevIns);
3223
3224 IOMMU_UNLOCK(pDevIns, pThisCC);
3225
3226 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. idDevice=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
3227 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
3228}
3229
3230
3231#ifdef IN_RING3
3232/**
3233 * Initializes an ILLEGAL_COMMAND_ERROR event.
3234 *
3235 * @param GCPhysCmd The system physical address of the failed command
3236 * access.
3237 * @param pEvtIllegalCmd Where to store the initialized event.
3238 */
3239static void iommuAmdIllegalCmdEventInit(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3240{
3241 Assert(!(GCPhysCmd & UINT64_C(0xf)));
3242 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
3243 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
3244 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
3245}
3246
3247
3248/**
3249 * Raises an ILLEGAL_COMMAND_ERROR event.
3250 *
3251 * @param pDevIns The IOMMU device instance.
3252 * @param pEvtIllegalCmd The illegal command error event.
3253 */
3254static void iommuAmdIllegalCmdEventRaise(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3255{
3256 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3257 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
3258 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3259
3260 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3261 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3262
3263 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
3264}
3265#endif /* IN_RING3 */
3266
3267
3268/**
3269 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
3270 *
3271 * @param idDevice The device ID (bus, device, function).
3272 * @param uIova The I/O virtual address.
3273 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
3274 * event was caused by an invalid level encoding in the
3275 * DTE.
3276 * @param enmOp The IOMMU operation being performed.
3277 * @param pEvtIllegalDte Where to store the initialized event.
3278 */
3279static void iommuAmdIllegalDteEventInit(uint16_t idDevice, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
3280 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
3281{
3282 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
3283 pEvtIllegalDte->n.u16DevId = idDevice;
3284 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3285 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3286 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
3287 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3288 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
3289 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
3290 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
3291 * IOMMU spec here but not for this field for I/O page fault event. */
3292 Assert(!(uIova & UINT64_C(0x3)));
3293}
3294
3295
3296/**
3297 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
3298 *
3299 * @param pDevIns The IOMMU instance data.
3300 * @param enmOp The IOMMU operation being performed.
3301 * @param pEvtIllegalDte The illegal device table entry event.
3302 * @param enmEvtType The illegal device table entry event type.
3303 *
3304 * @thread Any.
3305 */
3306static void iommuAmdIllegalDteEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
3307 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
3308{
3309 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3310 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
3311
3312 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3313 if (enmOp != IOMMUOP_CMD)
3314 iommuAmdSetPciTargetAbort(pDevIns);
3315
3316 LogFunc(("Raised ILLEGAL_DTE_EVENT. idDevice=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
3317 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
3318 NOREF(enmEvtType);
3319}
3320
3321
3322/**
3323 * Initializes an IO_PAGE_FAULT event.
3324 *
3325 * @param idDevice The device ID (bus, device, function).
3326 * @param idDomain The domain ID.
3327 * @param uIova The I/O virtual address being accessed.
3328 * @param fPresent Transaction to a page marked as present (including
3329 * DTE.V=1) or interrupt marked as remapped
3330 * (IRTE.RemapEn=1).
3331 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
3332 * the I/O page fault was caused by invalid level
3333 * encoding.
3334 * @param fPermDenied Permission denied for the address being accessed.
3335 * @param enmOp The IOMMU operation being performed.
3336 * @param pEvtIoPageFault Where to store the initialized event.
3337 */
3338static void iommuAmdIoPageFaultEventInit(uint16_t idDevice, uint16_t idDomain, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
3339 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
3340{
3341 Assert(!fPermDenied || fPresent);
3342 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
3343 pEvtIoPageFault->n.u16DevId = idDevice;
3344 //pEvtIoPageFault->n.u4PasidHi = 0;
3345 pEvtIoPageFault->n.u16DomainOrPasidLo = idDomain;
3346 //pEvtIoPageFault->n.u1GuestOrNested = 0;
3347 //pEvtIoPageFault->n.u1NoExecute = 0;
3348 //pEvtIoPageFault->n.u1User = 0;
3349 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3350 pEvtIoPageFault->n.u1Present = fPresent;
3351 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3352 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
3353 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
3354 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3355 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
3356 pEvtIoPageFault->n.u64Addr = uIova;
3357}
3358
3359
3360/**
3361 * Raises an IO_PAGE_FAULT event.
3362 *
3363 * @param pDevIns The IOMMU instance data.
3364 * @param fIoDevFlags The I/O device flags, see IOMMU_DTE_CACHE_F_XXX.
3365 * @param pIrte The interrupt remapping table entry, can be NULL.
3366 * @param enmOp The IOMMU operation being performed.
3367 * @param pEvtIoPageFault The I/O page fault event.
3368 * @param enmEvtType The I/O page fault event type.
3369 *
3370 * @thread Any.
3371 */
3372static void iommuAmdIoPageFaultEventRaise(PPDMDEVINS pDevIns, uint16_t fIoDevFlags, PCIRTE_T pIrte, IOMMUOP enmOp,
3373 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3374{
3375 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
3376 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
3377 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3378 STAM_COUNTER_INC(&pThis->StatIopfs); NOREF(pThis);
3379
3380#ifdef IOMMU_WITH_DTE_CACHE
3381# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) iommuAmdDteCacheUpdateFlags((a_pDevIns), (a_DevId), \
3382 IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED, \
3383 0 /* fAndMask */)
3384#else
3385# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) do { } while (0)
3386#endif
3387
3388 bool fSuppressEvtLogging = false;
3389 if ( enmOp == IOMMUOP_MEM_READ
3390 || enmOp == IOMMUOP_MEM_WRITE)
3391 {
3392 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_VALID
3393 | IOMMU_DTE_CACHE_F_SUPPRESS_IOPF | IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED;
3394 uint16_t const fSuppressAllIopf = IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
3395 if ( (fIoDevFlags & fSuppressAllIopf) == fSuppressAllIopf
3396 || (fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3397 {
3398 fSuppressEvtLogging = true;
3399 }
3400 }
3401 else if (enmOp == IOMMUOP_INTR_REQ)
3402 {
3403 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_INTR_MAP_VALID | IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
3404 if ((fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3405 fSuppressEvtLogging = true;
3406 else if (pIrte) /** @todo Make this compulsary and assert if it isn't provided. */
3407 fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
3408 }
3409 /* else: Events are never suppressed for commands. */
3410
3411 switch (enmEvtType)
3412 {
3413 case kIoPageFaultType_PermDenied:
3414 {
3415 /* Cannot be triggered by a command. */
3416 Assert(enmOp != IOMMUOP_CMD);
3417 RT_FALL_THRU();
3418 }
3419 case kIoPageFaultType_DteRsvdPagingMode:
3420 case kIoPageFaultType_PteInvalidPageSize:
3421 case kIoPageFaultType_PteInvalidLvlEncoding:
3422 case kIoPageFaultType_SkippedLevelIovaNotZero:
3423 case kIoPageFaultType_PteRsvdNotZero:
3424 case kIoPageFaultType_PteValidNotSet:
3425 case kIoPageFaultType_DteTranslationDisabled:
3426 case kIoPageFaultType_PasidInvalidRange:
3427 {
3428 /*
3429 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
3430 * create an event log entry. See AMD IOMMU spec. 2.1.3.2 "I/O Page Faults".
3431 */
3432 if (enmOp != IOMMUOP_TRANSLATE_REQ)
3433 {
3434 if (!fSuppressEvtLogging)
3435 {
3436 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3437 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3438 }
3439 if (enmOp != IOMMUOP_CMD)
3440 iommuAmdSetPciTargetAbort(pDevIns);
3441 }
3442 break;
3443 }
3444
3445 case kIoPageFaultType_UserSupervisor:
3446 {
3447 /* Access is blocked and only creates an event log entry. */
3448 if (!fSuppressEvtLogging)
3449 {
3450 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3451 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3452 }
3453 break;
3454 }
3455
3456 case kIoPageFaultType_IrteAddrInvalid:
3457 case kIoPageFaultType_IrteRsvdNotZero:
3458 case kIoPageFaultType_IrteRemapEn:
3459 case kIoPageFaultType_IrteRsvdIntType:
3460 case kIoPageFaultType_IntrReqAborted:
3461 case kIoPageFaultType_IntrWithPasid:
3462 {
3463 /* Only trigerred by interrupt requests. */
3464 Assert(enmOp == IOMMUOP_INTR_REQ);
3465 if (!fSuppressEvtLogging)
3466 {
3467 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3468 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3469 }
3470 iommuAmdSetPciTargetAbort(pDevIns);
3471 break;
3472 }
3473
3474 case kIoPageFaultType_SmiFilterMismatch:
3475 {
3476 /* Not supported and probably will never be, assert. */
3477 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
3478 break;
3479 }
3480
3481 case kIoPageFaultType_DevId_Invalid:
3482 {
3483 /* Cannot be triggered by a command. */
3484 Assert(enmOp != IOMMUOP_CMD);
3485 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
3486 if (!fSuppressEvtLogging)
3487 {
3488 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3489 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3490 }
3491 if ( enmOp == IOMMUOP_MEM_READ
3492 || enmOp == IOMMUOP_MEM_WRITE)
3493 iommuAmdSetPciTargetAbort(pDevIns);
3494 break;
3495 }
3496 }
3497
3498#undef IOMMU_DTE_CACHE_SET_PF_RAISED
3499}
3500
3501
3502/**
3503 * Raises an IO_PAGE_FAULT event given the DTE.
3504 *
3505 * @param pDevIns The IOMMU instance data.
3506 * @param pDte The device table entry.
3507 * @param pIrte The interrupt remapping table entry, can be NULL.
3508 * @param enmOp The IOMMU operation being performed.
3509 * @param pEvtIoPageFault The I/O page fault event.
3510 * @param enmEvtType The I/O page fault event type.
3511 *
3512 * @thread Any.
3513 */
3514static void iommuAmdIoPageFaultEventRaiseWithDte(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
3515 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3516{
3517 Assert(pDte);
3518 uint16_t const fIoDevFlags = iommuAmdGetBasicDevFlags(pDte);
3519 return iommuAmdIoPageFaultEventRaise(pDevIns, fIoDevFlags, pIrte, enmOp, pEvtIoPageFault, enmEvtType);
3520}
3521
3522
3523/**
3524 * Reads a device table entry for the given the device ID.
3525 *
3526 * @returns VBox status code.
3527 * @param pDevIns The IOMMU device instance.
3528 * @param idDevice The device ID (bus, device, function).
3529 * @param enmOp The IOMMU operation being performed.
3530 * @param pDte Where to store the device table entry.
3531 *
3532 * @thread Any.
3533 */
3534static int iommuAmdDteRead(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PDTE_T pDte)
3535{
3536 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3537 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3538
3539 IOMMU_LOCK(pDevIns, pThisCC);
3540
3541 /* Figure out which device table segment is being accessed. */
3542 uint8_t const idxSegsEn = pThis->Ctrl.n.u3DevTabSegEn;
3543 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
3544
3545 uint8_t const idxSeg = (idDevice & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
3546 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3547 AssertCompile(RT_ELEMENTS(g_auDevTabSegShifts) == RT_ELEMENTS(g_auDevTabSegMasks));
3548
3549 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
3550 uint32_t const offDte = (idDevice & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
3551 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
3552
3553 /* Ensure the DTE falls completely within the device table segment. */
3554 uint32_t const cbDevTabSeg = (pThis->aDevTabBaseAddrs[idxSeg].n.u9Size + 1) << X86_PAGE_4K_SHIFT;
3555
3556 IOMMU_UNLOCK(pDevIns, pThisCC);
3557
3558 if (offDte + sizeof(DTE_T) <= cbDevTabSeg)
3559 {
3560 /* Read the device table entry from guest memory. */
3561 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
3562 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
3563 if (RT_SUCCESS(rc))
3564 return VINF_SUCCESS;
3565
3566 /* Raise a device table hardware error. */
3567 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
3568
3569 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
3570 iommuAmdDevTabHwErrorEventInit(idDevice, GCPhysDte, enmOp, &EvtDevTabHwErr);
3571 iommuAmdDevTabHwErrorEventRaise(pDevIns, enmOp, &EvtDevTabHwErr);
3572 return VERR_IOMMU_DTE_READ_FAILED;
3573 }
3574
3575 /* Raise an I/O page fault for out-of-bounds acccess. */
3576 LogFunc(("Out-of-bounds device table entry. idDevice=%#x offDte=%u cbDevTabSeg=%u -> IOPF\n", idDevice, offDte, cbDevTabSeg));
3577 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3578 iommuAmdIoPageFaultEventInit(idDevice, 0 /* idDomain */, 0 /* uIova */, false /* fPresent */, false /* fRsvdNotZero */,
3579 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3580 iommuAmdIoPageFaultEventRaise(pDevIns, 0 /* fIoDevFlags */, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3581 kIoPageFaultType_DevId_Invalid);
3582 return VERR_IOMMU_DTE_BAD_OFFSET;
3583}
3584
3585
3586/**
3587 * Performs pre-translation checks for the given device table entry.
3588 *
3589 * @returns VBox status code.
3590 * @retval VINF_SUCCESS if the DTE is valid and supports address translation.
3591 * @retval VINF_IOMMU_ADDR_TRANSLATION_DISABLED if the DTE is valid but address
3592 * translation is disabled.
3593 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED if an error occurred and any
3594 * corresponding event was raised.
3595 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the DTE denies the requested
3596 * permissions.
3597 *
3598 * @param pDevIns The IOMMU device instance.
3599 * @param uIova The I/O virtual address to translate.
3600 * @param idDevice The device ID (bus, device, function).
3601 * @param fPerm The I/O permissions for this access, see
3602 * IOMMU_IO_PERM_XXX.
3603 * @param pDte The device table entry.
3604 * @param enmOp The IOMMU operation being performed.
3605 *
3606 * @thread Any.
3607 */
3608static int iommuAmdPreTranslateChecks(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, uint8_t fPerm, PCDTE_T pDte,
3609 IOMMUOP enmOp)
3610{
3611 /*
3612 * Check if the translation is valid, otherwise raise an I/O page fault.
3613 */
3614 if (pDte->n.u1TranslationValid)
3615 { /* likely */ }
3616 else
3617 {
3618 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
3619 * doesn't explicitly say whether an I/O page fault is raised. From other
3620 * places in the spec. it seems early page walk terminations (starting with
3621 * the DTE) return the state computed so far and raises an I/O page fault. So
3622 * returning an invalid translation rather than skipping translation. */
3623 LogFunc(("Translation valid bit not set -> IOPF\n"));
3624 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3625 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3626 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3627 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3628 kIoPageFaultType_DteTranslationDisabled);
3629 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3630 }
3631
3632 /*
3633 * Check permissions bits in the DTE.
3634 * Note: This MUST be checked prior to checking the root page table level below!
3635 */
3636 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3637 if ((fPerm & fDtePerm) == fPerm)
3638 { /* likely */ }
3639 else
3640 {
3641 LogFunc(("Permission denied by DTE (fPerm=%#x fDtePerm=%#x) -> IOPF\n", fPerm, fDtePerm));
3642 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3643 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3644 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3645 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3646 kIoPageFaultType_PermDenied);
3647 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3648 }
3649
3650 /*
3651 * If the root page table level is 0, translation is disabled and GPA=SPA and
3652 * the DTE.IR and DTE.IW bits control permissions (verified above).
3653 */
3654 uint8_t const uMaxLevel = pDte->n.u3Mode;
3655 if (uMaxLevel != 0)
3656 { /* likely */ }
3657 else
3658 {
3659 Assert((fPerm & fDtePerm) == fPerm); /* Verify we've checked permissions. */
3660 return VINF_IOMMU_ADDR_TRANSLATION_DISABLED;
3661 }
3662
3663 /*
3664 * If the root page table level exceeds the allowed host-address translation level,
3665 * page walk is terminated and translation fails.
3666 */
3667 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3668 { /* likely */ }
3669 else
3670 {
3671 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
3672 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
3673 * I'm just going with I/O page fault. */
3674 LogFunc(("Invalid root page table level %#x (idDevice=%#x) -> IOPF\n", uMaxLevel, idDevice));
3675 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3676 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3677 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3678 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3679 kIoPageFaultType_PteInvalidLvlEncoding);
3680 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3681 }
3682
3683 /* The DTE allows translations for this device. */
3684 return VINF_SUCCESS;
3685}
3686
3687
3688/**
3689 * Walks the I/O page table to translate the I/O virtual address to a system
3690 * physical address.
3691 *
3692 * @returns VBox status code.
3693 * @param pDevIns The IOMMU device instance.
3694 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
3695 * @param fPerm The I/O permissions for this access, see
3696 * IOMMU_IO_PERM_XXX.
3697 * @param idDevice The device ID (bus, device, function).
3698 * @param pDte The device table entry.
3699 * @param enmOp The IOMMU operation being performed.
3700 * @param pPageLookup Where to store the results of the I/O page lookup. This
3701 * is only updated when VINF_SUCCESS is returned.
3702 *
3703 * @thread Any.
3704 */
3705static int iommuAmdIoPageTableWalk(PPDMDEVINS pDevIns, uint64_t uIova, uint8_t fPerm, uint16_t idDevice, PCDTE_T pDte,
3706 IOMMUOP enmOp, PIOPAGELOOKUP pPageLookup)
3707{
3708 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3709 Assert(pDte->n.u1Valid);
3710 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
3711
3712 /* The virtual address bits indexing table. */
3713 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
3714 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
3715
3716 /*
3717 * Traverse the I/O page table starting with the page directory in the DTE.
3718 *
3719 * The Valid (Present bit), Translation Valid and Mode (Next-Level bits) in
3720 * the DTE have been validated already, see iommuAmdPreTranslateChecks.
3721 */
3722 IOPTENTITY_T PtEntity;
3723 PtEntity.u64 = pDte->au64[0];
3724 for (;;)
3725 {
3726 uint8_t const uLevel = PtEntity.n.u3NextLevel;
3727
3728 /* Read the page table entity at the current level. */
3729 {
3730 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
3731 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
3732 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
3733 uint64_t const offPte = idxPte << 3;
3734 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
3735 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
3736 if (RT_FAILURE(rc))
3737 {
3738 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
3739 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
3740 iommuAmdPageTabHwErrorEventInit(idDevice, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
3741 iommuAmdPageTabHwErrorEventRaise(pDevIns, enmOp, &EvtPageTabHwErr);
3742 return VERR_IOMMU_IPE_2;
3743 }
3744 }
3745
3746 /* Check present bit. */
3747 if (PtEntity.n.u1Present)
3748 { /* likely */ }
3749 else
3750 {
3751 LogFunc(("Page table entry not present. idDevice=%#x uIova=%#RX64 -> IOPF\n", idDevice, uIova));
3752 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3753 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3754 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3755 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3756 kIoPageFaultType_PermDenied);
3757 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3758 }
3759
3760 /* Validate the encoding of the next level. */
3761 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
3762#if IOMMU_MAX_HOST_PT_LEVEL < 6
3763 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3764 { /* likely */ }
3765 else
3766 {
3767 LogFunc(("Next-level/paging-mode field of the paging entity invalid. uNextLevel=%#x -> IOPF\n", uNextLevel));
3768 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3769 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, true /* fRsvdNotZero */,
3770 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3771 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3772 kIoPageFaultType_PteInvalidLvlEncoding);
3773 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3774 }
3775#endif
3776
3777 /* Check reserved bits. */
3778 uint64_t const fRsvdMask = uNextLevel == 0 || uNextLevel == 7 ? IOMMU_PTE_RSVD_MASK : IOMMU_PDE_RSVD_MASK;
3779 if (!(PtEntity.u64 & fRsvdMask))
3780 { /* likely */ }
3781 else
3782 {
3783 LogFunc(("Page table entity (%#RX64 level=%u) reserved bits set -> IOPF\n", PtEntity.u64, uNextLevel));
3784 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3785 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, true /* fRsvdNotZero */,
3786 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3787 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3788 kIoPageFaultType_PteRsvdNotZero);
3789 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3790 }
3791
3792 /* Check permission bits. */
3793 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3794 if ((fPerm & fPtePerm) == fPerm)
3795 { /* likely */ }
3796 else
3797 {
3798 LogFunc(("Page table entry access denied. idDevice=%#x fPerm=%#x fPtePerm=%#x -> IOPF\n", idDevice, fPerm, fPtePerm));
3799 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3800 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3801 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3802 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3803 kIoPageFaultType_PermDenied);
3804 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3805 }
3806
3807 /* If the next level is 0 or 7, this is the final level PTE. */
3808 if (uNextLevel == 0)
3809 {
3810 /* The page size of the translation is the default size for the level. */
3811 uint8_t const cShift = s_acIovaLevelShifts[uLevel];
3812 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3813 pPageLookup->GCPhysSpa = GCPhysPte & X86_GET_PAGE_BASE_MASK(cShift);
3814 pPageLookup->cShift = cShift;
3815 pPageLookup->fPerm = fPtePerm;
3816 return VINF_SUCCESS;
3817 }
3818 if (uNextLevel == 7)
3819 {
3820 /* The default page size of the translation is overridden. */
3821 uint8_t cShift = X86_PAGE_4K_SHIFT;
3822 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3823 while (GCPhysPte & RT_BIT_64(cShift++))
3824 ;
3825
3826 /* The page size must be larger than the default size and lower than the default size of the higher level. */
3827 if ( cShift > s_acIovaLevelShifts[uLevel]
3828 && cShift < s_acIovaLevelShifts[uLevel + 1])
3829 {
3830 pPageLookup->GCPhysSpa = GCPhysPte & X86_GET_PAGE_BASE_MASK(cShift);
3831 pPageLookup->cShift = cShift;
3832 pPageLookup->fPerm = fPtePerm;
3833 STAM_COUNTER_INC(&pThis->StatNonStdPageSize); NOREF(pThis);
3834 return VINF_SUCCESS;
3835 }
3836
3837 LogFunc(("Page size invalid. idDevice=%#x cShift=%u -> IOPF\n", idDevice, cShift));
3838 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3839 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3840 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3841 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3842 kIoPageFaultType_PteInvalidPageSize);
3843 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3844 }
3845
3846 /* Validate level transition. */
3847 if (uNextLevel < uLevel)
3848 { /* likely */ }
3849 else
3850 {
3851 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
3852 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3853 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3854 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3855 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3856 kIoPageFaultType_PteInvalidLvlEncoding);
3857 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3858 }
3859
3860 /* Ensure IOVA bits of skipped levels (if any) are zero. */
3861 uint64_t const fIovaSkipMask = IOMMU_GET_MAX_VALID_IOVA(uLevel - 1) - IOMMU_GET_MAX_VALID_IOVA(uNextLevel);
3862 if (!(uIova & fIovaSkipMask))
3863 { /* likely */ }
3864 else
3865 {
3866 LogFunc(("IOVA of skipped levels are not zero. uIova=%#RX64 fSkipMask=%#RX64 -> IOPF\n", uIova, fIovaSkipMask));
3867 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3868 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3869 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3870 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3871 kIoPageFaultType_SkippedLevelIovaNotZero);
3872 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3873 }
3874
3875 /* Traverse to the next level. */
3876 }
3877}
3878
3879
3880/**
3881 * Page lookup callback for finding an I/O page from guest memory.
3882 *
3883 * @returns VBox status code.
3884 * @retval VINF_SUCCESS when the page is found and has the right permissions.
3885 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED when address translation fails.
3886 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
3887 * insufficient to what is requested.
3888 *
3889 * @param pDevIns The IOMMU instance data.
3890 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
3891 * 4K aligned).
3892 * @param fPerm The I/O permissions for this access, see
3893 * IOMMU_IO_PERM_XXX.
3894 * @param pAux The auxiliary information required during lookup.
3895 * @param pPageLookup Where to store the looked up I/O page.
3896 */
3897static DECLCALLBACK(int) iommuAmdDteLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
3898 PIOPAGELOOKUP pPageLookup)
3899{
3900 AssertPtr(pAux);
3901 AssertPtr(pPageLookup);
3902 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
3903
3904 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3905 STAM_PROFILE_ADV_START(&pThis->StatProfDteLookup, a);
3906 int rc = iommuAmdIoPageTableWalk(pDevIns, uIovaPage, fPerm, pAux->idDevice, pAux->pDte, pAux->enmOp, pPageLookup);
3907 STAM_PROFILE_ADV_STOP(&pThis->StatProfDteLookup, a); NOREF(pThis);
3908 return rc;
3909}
3910
3911
3912/**
3913 * Looks up a range of I/O virtual addresses.
3914 *
3915 * @returns VBox status code.
3916 * @param pDevIns The IOMMU instance data.
3917 * @param pfnIoPageLookup The lookup function to use.
3918 * @param pAddrIn The I/O address range to lookup.
3919 * @param pAux The auxiliary information required by the lookup
3920 * function.
3921 * @param pAddrOut Where to store the translated I/O address page
3922 * lookup.
3923 * @param pcbContiguous Where to store the size of the access.
3924 */
3925static int iommuAmdLookupIoAddrRange(PPDMDEVINS pDevIns, PFNIOPAGELOOKUP pfnIoPageLookup, PCIOADDRRANGE pAddrIn,
3926 PCIOMMUOPAUX pAux, PIOPAGELOOKUP pAddrOut, size_t *pcbContiguous)
3927{
3928 int rc;
3929 size_t const cbIova = pAddrIn->cb;
3930 uint8_t const fPerm = pAddrIn->fPerm;
3931 uint64_t const uIova = pAddrIn->uAddr;
3932 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3933 size_t cbRemaining = cbIova;
3934 uint64_t uIovaPage = pAddrIn->uAddr & X86_PAGE_4K_BASE_MASK;
3935 uint64_t offIova = pAddrIn->uAddr & X86_PAGE_4K_OFFSET_MASK;
3936 size_t const cbPage = X86_PAGE_4K_SIZE;
3937
3938 IOPAGELOOKUP PageLookupPrev;
3939 RT_ZERO(PageLookupPrev);
3940 for (;;)
3941 {
3942 /* Lookup the physical page corresponding to the I/O virtual address. */
3943 IOPAGELOOKUP PageLookup;
3944 rc = pfnIoPageLookup(pDevIns, uIovaPage, fPerm, pAux, &PageLookup);
3945 if (RT_SUCCESS(rc))
3946 {
3947 /*
3948 * Validate results of the translation.
3949 */
3950 /* The IOTLB cache preserves the original page sizes even though the IOVAs are split into 4K pages. */
3951 Assert(PageLookup.cShift >= X86_PAGE_4K_SHIFT && PageLookup.cShift <= 51);
3952 Assert( pfnIoPageLookup != iommuAmdDteLookupPage
3953 || !(PageLookup.GCPhysSpa & X86_GET_PAGE_OFFSET_MASK(PageLookup.cShift)));
3954 Assert((PageLookup.fPerm & fPerm) == fPerm);
3955
3956 /* Store the translated address before continuing to access more pages. */
3957 if (cbRemaining == cbIova)
3958 {
3959 uint64_t const offSpa = uIova & X86_GET_PAGE_OFFSET_MASK(PageLookup.cShift);
3960 GCPhysSpa = PageLookup.GCPhysSpa | offSpa;
3961 }
3962 /*
3963 * Check if translated address results in a physically contiguous region.
3964 *
3965 * Also ensure that the permissions for all pages in this range are identical
3966 * because we specify a common permission while adding pages in this range
3967 * to the IOTLB cache.
3968 *
3969 * The page size must also be identical since we need to know how many offset
3970 * bits to copy into the final translated address (while retrieving 4K sized
3971 * pages from the IOTLB cache).
3972 */
3973 else if ( PageLookup.GCPhysSpa == PageLookupPrev.GCPhysSpa + cbPage
3974 && PageLookup.fPerm == PageLookupPrev.fPerm
3975 && PageLookup.cShift == PageLookupPrev.cShift)
3976 { /* likely */ }
3977 else
3978 {
3979 Assert(cbRemaining > 0);
3980 rc = VERR_OUT_OF_RANGE;
3981 break;
3982 }
3983
3984 /* Store the page lookup result from the first/previous page. */
3985 PageLookupPrev = PageLookup;
3986
3987 /* Check if we need to access more pages. */
3988 if (cbRemaining > cbPage - offIova)
3989 {
3990 cbRemaining -= (cbPage - offIova); /* Calculate how much more we need to access. */
3991 uIovaPage += cbPage; /* Update address of the next access. */
3992 offIova = 0; /* After the first page, remaining pages are accessed from offset 0. */
3993 }
3994 else
3995 {
3996 /* Caller (PDM) doesn't expect more data accessed than what was requested. */
3997 cbRemaining = 0;
3998 break;
3999 }
4000 }
4001 else
4002 break;
4003 }
4004
4005 pAddrOut->GCPhysSpa = GCPhysSpa; /* Update the translated address. */
4006 pAddrOut->cShift = PageLookupPrev.cShift; /* Update the page size of the lookup. */
4007 pAddrOut->fPerm = PageLookupPrev.fPerm; /* Update the allowed permissions for this access. */
4008 *pcbContiguous = cbIova - cbRemaining; /* Update the size of the contiguous memory region. */
4009 return rc;
4010}
4011
4012
4013/**
4014 * Looks up an I/O virtual address from the device table.
4015 *
4016 * @returns VBox status code.
4017 * @param pDevIns The IOMMU instance data.
4018 * @param idDevice The device ID (bus, device, function).
4019 * @param uIova The I/O virtual address to lookup.
4020 * @param cbIova The size of the access.
4021 * @param fPerm The I/O permissions for this access, see
4022 * IOMMU_IO_PERM_XXX.
4023 * @param enmOp The IOMMU operation being performed.
4024 * @param pGCPhysSpa Where to store the translated system physical address.
4025 * @param pcbContiguous Where to store the number of contiguous bytes translated
4026 * and permission-checked.
4027 *
4028 * @thread Any.
4029 */
4030static int iommuAmdDteLookup(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova, uint8_t fPerm, IOMMUOP enmOp,
4031 PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4032{
4033 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4034 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
4035 size_t cbContiguous = 0;
4036
4037 /* Read the device table entry from memory. */
4038 DTE_T Dte;
4039 int rc = iommuAmdDteRead(pDevIns, idDevice, enmOp, &Dte);
4040 if (RT_SUCCESS(rc))
4041 {
4042 if (Dte.n.u1Valid)
4043 {
4044 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
4045 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
4046 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
4047 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
4048 {
4049 /*
4050 * Check if the DTE is configured for translating addresses.
4051 * Note: Addresses cannot be subject to exclusion as we do -not- support remote IOTLBs,
4052 * so there's no need to check the address exclusion base/limit here.
4053 */
4054 rc = iommuAmdPreTranslateChecks(pDevIns, idDevice, uIova, fPerm, &Dte, enmOp);
4055 if (rc == VINF_SUCCESS)
4056 {
4057 IOADDRRANGE AddrIn;
4058 AddrIn.uAddr = uIova;
4059 AddrIn.cb = cbIova;
4060 AddrIn.fPerm = fPerm;
4061
4062 IOMMUOPAUX Aux;
4063 Aux.enmOp = enmOp;
4064 Aux.pDte = &Dte;
4065 Aux.idDevice = idDevice;
4066 Aux.idDomain = Dte.n.u16DomainId;
4067
4068 /* Lookup the address from the DTE and I/O page tables.*/
4069 IOPAGELOOKUP AddrOut;
4070 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdDteLookupPage, &AddrIn, &Aux, &AddrOut, &cbContiguous);
4071 GCPhysSpa = AddrOut.GCPhysSpa;
4072
4073 /*
4074 * If we stopped since translation resulted in non-contiguous physical addresses
4075 * or permissions aren't identical for all pages in the access, what we translated
4076 * thus far is still valid.
4077 */
4078 if (rc == VERR_OUT_OF_RANGE)
4079 {
4080 Assert(cbContiguous > 0 && cbContiguous < cbIova);
4081 rc = VINF_SUCCESS;
4082 STAM_COUNTER_INC(&pThis->StatAccessDteNonContig); NOREF(pThis);
4083 }
4084 else if (rc == VERR_IOMMU_ADDR_ACCESS_DENIED)
4085 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
4086
4087#ifdef IOMMU_WITH_IOTLBE_CACHE
4088 if (RT_SUCCESS(rc))
4089 {
4090 /* Update that addresses requires translation (cumulative permissions of DTE and I/O page tables). */
4091 iommuAmdDteCacheAddOrUpdateFlags(pDevIns, &Dte, idDevice, IOMMU_DTE_CACHE_F_ADDR_TRANSLATE,
4092 0 /* fAndMask */);
4093 /* Update IOTLB for the contiguous range of I/O virtual addresses. */
4094 iommuAmdIotlbAddRange(pDevIns, Aux.idDomain, uIova & X86_PAGE_4K_BASE_MASK, cbContiguous, &AddrOut);
4095 }
4096#endif
4097 }
4098 else if (rc == VINF_IOMMU_ADDR_TRANSLATION_DISABLED)
4099 {
4100 /*
4101 * Translation is disabled for this device (root paging mode is 0).
4102 * GPA=SPA, but the permission bits are important and controls accesses.
4103 */
4104 GCPhysSpa = uIova;
4105 cbContiguous = cbIova;
4106 rc = VINF_SUCCESS;
4107
4108#ifdef IOMMU_WITH_IOTLBE_CACHE
4109 /* Update that addresses permissions of DTE apply (but omit address translation). */
4110 iommuAmdDteCacheAddOrUpdateFlags(pDevIns, &Dte, idDevice, IOMMU_DTE_CACHE_F_IO_PERM,
4111 IOMMU_DTE_CACHE_F_ADDR_TRANSLATE);
4112#endif
4113 }
4114 else
4115 {
4116 /* Address translation failed or access is denied. */
4117 Assert(rc == VERR_IOMMU_ADDR_ACCESS_DENIED || rc == VERR_IOMMU_ADDR_TRANSLATION_FAILED);
4118 GCPhysSpa = NIL_RTGCPHYS;
4119 cbContiguous = 0;
4120 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
4121 }
4122 }
4123 else
4124 {
4125 /* Invalid reserved bits in the DTE, raise an error event. */
4126 LogFunc(("Invalid DTE reserved bits (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4127 EVT_ILLEGAL_DTE_T Event;
4128 iommuAmdIllegalDteEventInit(idDevice, uIova, true /* fRsvdNotZero */, enmOp, &Event);
4129 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4130 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4131 }
4132 }
4133 else
4134 {
4135 /*
4136 * The DTE is not valid, forward addresses untranslated.
4137 * See AMD IOMMU spec. "Table 5: Feature Enablement for Address Translation".
4138 */
4139 GCPhysSpa = uIova;
4140 cbContiguous = cbIova;
4141 }
4142 }
4143 else
4144 {
4145 LogFunc(("Failed to read device table entry. idDevice=%#x rc=%Rrc\n", idDevice, rc));
4146 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4147 }
4148
4149 *pGCPhysSpa = GCPhysSpa;
4150 *pcbContiguous = cbContiguous;
4151 AssertMsg(rc != VINF_SUCCESS || cbContiguous > 0, ("cbContiguous=%zu\n", cbContiguous));
4152 return rc;
4153}
4154
4155
4156#ifdef IOMMU_WITH_IOTLBE_CACHE
4157/**
4158 * I/O page lookup callback for finding an I/O page from the IOTLB.
4159 *
4160 * @returns VBox status code.
4161 * @retval VINF_SUCCESS when the page is found and has the right permissions.
4162 * @retval VERR_NOT_FOUND when the page is not found.
4163 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
4164 * insufficient to what is requested.
4165 *
4166 * @param pDevIns The IOMMU instance data.
4167 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
4168 * 4K aligned).
4169 * @param fPerm The I/O permissions for this access, see
4170 * IOMMU_IO_PERM_XXX.
4171 * @param pAux The auxiliary information required during lookup.
4172 * @param pPageLookup Where to store the looked up I/O page.
4173 */
4174static DECLCALLBACK(int) iommuAmdCacheLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
4175 PIOPAGELOOKUP pPageLookup)
4176{
4177 Assert(pAux);
4178 Assert(pPageLookup);
4179 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
4180
4181 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4182 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4183
4184 STAM_PROFILE_ADV_START(&pThis->StatProfIotlbeLookup, a);
4185 PCIOTLBE pIotlbe = iommuAmdIotlbLookup(pThis, pThisR3, pAux->idDomain, uIovaPage);
4186 STAM_PROFILE_ADV_STOP(&pThis->StatProfIotlbeLookup, a);
4187 if (pIotlbe)
4188 {
4189 *pPageLookup = pIotlbe->PageLookup;
4190 if ((pPageLookup->fPerm & fPerm) == fPerm)
4191 {
4192 STAM_COUNTER_INC(&pThis->StatAccessCacheHit);
4193 return VINF_SUCCESS;
4194 }
4195 return VERR_IOMMU_ADDR_ACCESS_DENIED;
4196 }
4197 return VERR_NOT_FOUND;
4198}
4199
4200
4201/**
4202 * Lookups a memory access from the IOTLB cache.
4203 *
4204 * @returns VBox status code.
4205 * @retval VINF_SUCCESS if the access was cached and permissions are verified.
4206 * @retval VERR_OUT_OF_RANGE if the access resulted in a non-contiguous physical
4207 * address region.
4208 * @retval VERR_NOT_FOUND if the access was not cached.
4209 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the access was cached but permissions
4210 * are insufficient.
4211 *
4212 * @param pDevIns The IOMMU instance data.
4213 * @param idDevice The device ID (bus, device, function).
4214 * @param uIova The I/O virtual address to lookup.
4215 * @param cbIova The size of the access.
4216 * @param fPerm The I/O permissions for this access, see
4217 * IOMMU_IO_PERM_XXX.
4218 * @param enmOp The IOMMU operation being performed.
4219 * @param pGCPhysSpa Where to store the translated system physical address.
4220 * @param pcbContiguous Where to store the number of contiguous bytes translated
4221 * and permission-checked.
4222 */
4223static int iommuAmdIotlbCacheLookup(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova, uint8_t fPerm,
4224 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4225{
4226 int rc;
4227 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4228
4229#define IOMMU_IOTLB_LOOKUP_FAILED(a_rc) \
4230 do { \
4231 *pGCPhysSpa = NIL_RTGCPHYS; \
4232 *pcbContiguous = 0; \
4233 rc = (a_rc); \
4234 } while (0)
4235
4236 /*
4237 * We hold the cache lock across both the DTE and the IOTLB lookups (if any) because
4238 * we don't want the DTE cache to be invalidate while we perform IOTBL lookups.
4239 */
4240 IOMMU_CACHE_LOCK(pDevIns, pThis);
4241
4242 /* Lookup the DTE cache entry. */
4243 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, idDevice);
4244 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
4245 {
4246 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
4247 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4248 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4249 {
4250 /* Lookup IOTLB entries. */
4251 IOADDRRANGE AddrIn;
4252 AddrIn.uAddr = uIova;
4253 AddrIn.cb = cbIova;
4254 AddrIn.fPerm = fPerm;
4255
4256 IOMMUOPAUX Aux;
4257 Aux.enmOp = enmOp;
4258 Aux.pDte = NULL;
4259 Aux.idDevice = idDevice;
4260 Aux.idDomain = pDteCache->idDomain;
4261
4262 IOPAGELOOKUP AddrOut;
4263 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdCacheLookupPage, &AddrIn, &Aux, &AddrOut, pcbContiguous);
4264 *pGCPhysSpa = AddrOut.GCPhysSpa;
4265 Assert(*pcbContiguous <= cbIova);
4266 }
4267 else if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4268 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4269 {
4270 /* Address translation is disabled, but DTE permissions apply. */
4271 Assert(!(pDteCache->fFlags & IOMMU_DTE_CACHE_F_ADDR_TRANSLATE));
4272 uint8_t const fDtePerm = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_IO_PERM_SHIFT) & IOMMU_DTE_CACHE_F_IO_PERM_MASK;
4273 if ((fDtePerm & fPerm) == fPerm)
4274 {
4275 *pGCPhysSpa = uIova;
4276 *pcbContiguous = cbIova;
4277 rc = VINF_SUCCESS;
4278 }
4279 else
4280 IOMMU_IOTLB_LOOKUP_FAILED(VERR_IOMMU_ADDR_ACCESS_DENIED);
4281 }
4282 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
4283 {
4284 /* Forward addresses untranslated, without checking permissions. */
4285 *pGCPhysSpa = uIova;
4286 *pcbContiguous = cbIova;
4287 rc = VINF_SUCCESS;
4288 }
4289 else
4290 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4291 }
4292 else
4293 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4294
4295 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
4296
4297 return rc;
4298
4299#undef IOMMU_IOTLB_LOOKUP_FAILED
4300}
4301#endif /* IOMMU_WITH_IOTLBE_CACHE */
4302
4303
4304/**
4305 * Gets the I/O permission and IOMMU operation type for the given access flags.
4306 *
4307 * @param pThis The shared IOMMU device state.
4308 * @param fFlags The PDM IOMMU flags, PDMIOMMU_MEM_F_XXX.
4309 * @param penmOp Where to store the IOMMU operation.
4310 * @param pfPerm Where to store the IOMMU I/O permission.
4311 * @param fBulk Whether this is a bulk read or write.
4312 */
4313DECLINLINE(void) iommuAmdMemAccessGetPermAndOp(PIOMMU pThis, uint32_t fFlags, PIOMMUOP penmOp, uint8_t *pfPerm, bool fBulk)
4314{
4315 if (fFlags & PDMIOMMU_MEM_F_WRITE)
4316 {
4317 *penmOp = IOMMUOP_MEM_WRITE;
4318 *pfPerm = IOMMU_IO_PERM_WRITE;
4319#ifdef VBOX_WITH_STATISTICS
4320 if (!fBulk)
4321 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
4322 else
4323 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
4324#else
4325 RT_NOREF2(pThis, fBulk);
4326#endif
4327 }
4328 else
4329 {
4330 Assert(fFlags & PDMIOMMU_MEM_F_READ);
4331 *penmOp = IOMMUOP_MEM_READ;
4332 *pfPerm = IOMMU_IO_PERM_READ;
4333#ifdef VBOX_WITH_STATISTICS
4334 if (!fBulk)
4335 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
4336 else
4337 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
4338#else
4339 RT_NOREF2(pThis, fBulk);
4340#endif
4341 }
4342}
4343
4344
4345/**
4346 * Memory access transaction from a device.
4347 *
4348 * @returns VBox status code.
4349 * @param pDevIns The IOMMU device instance.
4350 * @param idDevice The device ID (bus, device, function).
4351 * @param uIova The I/O virtual address being accessed.
4352 * @param cbIova The size of the access.
4353 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4354 * @param pGCPhysSpa Where to store the translated system physical address.
4355 * @param pcbContiguous Where to store the number of contiguous bytes translated
4356 * and permission-checked.
4357 *
4358 * @thread Any.
4359 */
4360static DECLCALLBACK(int) iommuAmdMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
4361 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4362{
4363 /* Validate. */
4364 AssertPtr(pDevIns);
4365 AssertPtr(pGCPhysSpa);
4366 Assert(cbIova > 0);
4367 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4368
4369 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4370 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4371 if (Ctrl.n.u1IommuEn)
4372 {
4373 IOMMUOP enmOp;
4374 uint8_t fPerm;
4375 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, false /* fBulk */);
4376 LogFlowFunc(("%s: idDevice=%#x uIova=%#RX64 cb=%zu\n", iommuAmdMemAccessGetPermName(fPerm), idDevice, uIova, cbIova));
4377
4378 int rc;
4379#ifdef IOMMU_WITH_IOTLBE_CACHE
4380 /* Lookup the IOVA from the cache. */
4381 rc = iommuAmdIotlbCacheLookup(pDevIns, idDevice, uIova, cbIova, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4382 if (rc == VINF_SUCCESS)
4383 {
4384 /* All pages in the access were found in the cache with sufficient permissions. */
4385 Assert(*pcbContiguous == cbIova);
4386 Assert(*pGCPhysSpa != NIL_RTGCPHYS);
4387 STAM_COUNTER_INC(&pThis->StatAccessCacheHitFull);
4388 return VINF_SUCCESS;
4389 }
4390 if (rc != VERR_OUT_OF_RANGE)
4391 { /* likely */ }
4392 else
4393 {
4394 /* Access stopped since translations resulted in non-contiguous memory, let caller resume access. */
4395 Assert(*pcbContiguous > 0 && *pcbContiguous < cbIova);
4396 STAM_COUNTER_INC(&pThis->StatAccessCacheNonContig);
4397 return VINF_SUCCESS;
4398 }
4399
4400 /*
4401 * Access incomplete as not all pages were in the cache.
4402 * Or permissions were denied for the access (which typically doesn't happen)
4403 * so go through the slower path and raise the required event.
4404 */
4405 AssertMsg(*pcbContiguous < cbIova, ("Invalid size: cbContiguous=%zu cbIova=%zu\n", *pcbContiguous, cbIova));
4406 uIova += *pcbContiguous;
4407 cbIova -= *pcbContiguous;
4408 /* We currently are including any permission denied pages as cache misses too.*/
4409 STAM_COUNTER_INC(&pThis->StatAccessCacheMiss);
4410#endif
4411
4412 /* Lookup the IOVA from the device table. */
4413 rc = iommuAmdDteLookup(pDevIns, idDevice, uIova, cbIova, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4414 if (RT_SUCCESS(rc))
4415 { /* likely */ }
4416 else
4417 {
4418 Assert(rc != VERR_OUT_OF_RANGE);
4419 LogFunc(("DTE lookup failed! idDevice=%#x uIova=%#RX64 fPerm=%u cbIova=%zu rc=%#Rrc\n", idDevice, uIova, fPerm,
4420 cbIova, rc));
4421 }
4422
4423 return rc;
4424 }
4425
4426 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4427 *pGCPhysSpa = uIova;
4428 *pcbContiguous = cbIova;
4429 return VINF_SUCCESS;
4430}
4431
4432
4433/**
4434 * Memory access bulk (one or more 4K pages) request from a device.
4435 *
4436 * @returns VBox status code.
4437 * @param pDevIns The IOMMU device instance.
4438 * @param idDevice The device ID (bus, device, function).
4439 * @param cIovas The number of addresses being accessed.
4440 * @param pauIovas The I/O virtual addresses for each page being accessed.
4441 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4442 * @param paGCPhysSpa Where to store the translated physical addresses.
4443 *
4444 * @thread Any.
4445 */
4446static DECLCALLBACK(int) iommuAmdMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
4447 uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
4448{
4449 /* Validate. */
4450 AssertPtr(pDevIns);
4451 Assert(cIovas > 0);
4452 AssertPtr(pauIovas);
4453 AssertPtr(paGCPhysSpa);
4454 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4455
4456 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4457 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4458 if (Ctrl.n.u1IommuEn)
4459 {
4460 IOMMUOP enmOp;
4461 uint8_t fPerm;
4462 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, true /* fBulk */);
4463 LogFlowFunc(("%s: idDevice=%#x cIovas=%zu\n", iommuAmdMemAccessGetPermName(fPerm), idDevice, cIovas));
4464
4465 for (size_t i = 0; i < cIovas; i++)
4466 {
4467 int rc;
4468 size_t cbContig;
4469
4470#ifdef IOMMU_WITH_IOTLBE_CACHE
4471 /* Lookup the IOVA from the IOTLB cache. */
4472 rc = iommuAmdIotlbCacheLookup(pDevIns, idDevice, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i],
4473 &cbContig);
4474 if (rc == VINF_SUCCESS)
4475 {
4476 Assert(cbContig == X86_PAGE_SIZE);
4477 Assert(paGCPhysSpa[i] != NIL_RTGCPHYS);
4478 STAM_COUNTER_INC(&pThis->StatAccessCacheHitFull);
4479 continue;
4480 }
4481 Assert(rc == VERR_NOT_FOUND || rc == VERR_IOMMU_ADDR_ACCESS_DENIED);
4482 STAM_COUNTER_INC(&pThis->StatAccessCacheMiss);
4483#endif
4484
4485 /* Lookup the IOVA from the device table. */
4486 rc = iommuAmdDteLookup(pDevIns, idDevice, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i], &cbContig);
4487 if (RT_SUCCESS(rc))
4488 { /* likely */ }
4489 else
4490 {
4491 LogFunc(("Failed! idDevice=%#x uIova=%#RX64 fPerm=%u rc=%Rrc\n", idDevice, pauIovas[i], fPerm, rc));
4492 return rc;
4493 }
4494 Assert(cbContig == X86_PAGE_SIZE);
4495 }
4496 }
4497 else
4498 {
4499 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4500 for (size_t i = 0; i < cIovas; i++)
4501 paGCPhysSpa[i] = pauIovas[i];
4502 }
4503
4504 return VINF_SUCCESS;
4505}
4506
4507
4508/**
4509 * Reads an interrupt remapping table entry from guest memory given its DTE.
4510 *
4511 * @returns VBox status code.
4512 * @param pDevIns The IOMMU device instance.
4513 * @param idDevice The device ID (bus, device, function).
4514 * @param pDte The device table entry.
4515 * @param GCPhysIn The source MSI address (used for reporting errors).
4516 * @param uDataIn The source MSI data.
4517 * @param enmOp The IOMMU operation being performed.
4518 * @param pIrte Where to store the interrupt remapping table entry.
4519 *
4520 * @thread Any.
4521 */
4522static int iommuAmdIrteRead(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
4523 IOMMUOP enmOp, PIRTE_T pIrte)
4524{
4525 /* Ensure the IRTE length is valid. */
4526 Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
4527
4528 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
4529 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
4530 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(uDataIn);
4531 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
4532
4533 /* Ensure the IRTE falls completely within the interrupt table. */
4534 if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
4535 { /* likely */ }
4536 else
4537 {
4538 LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
4539 GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
4540
4541 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4542 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
4543 false /* fPermDenied */, enmOp, &EvtIoPageFault);
4544 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4545 kIoPageFaultType_IrteAddrInvalid);
4546 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4547 }
4548
4549 /* Read the IRTE from memory. */
4550 Assert(!(GCPhysIrte & 3));
4551 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
4552 if (RT_SUCCESS(rc))
4553 return VINF_SUCCESS;
4554
4555 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
4556 * situation. Is it an I/O page fault or a device table hardware error?
4557 * There's no interrupt table hardware error event, but it's unclear what
4558 * we should do here. */
4559 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
4560 return VERR_IOMMU_IPE_4;
4561}
4562
4563
4564/**
4565 * Remaps the interrupt using the interrupt remapping table.
4566 *
4567 * @returns VBox status code.
4568 * @param pDevIns The IOMMU instance data.
4569 * @param idDevice The device ID (bus, device, function).
4570 * @param pDte The device table entry.
4571 * @param enmOp The IOMMU operation being performed.
4572 * @param pMsiIn The source MSI.
4573 * @param pMsiOut Where to store the remapped MSI.
4574 *
4575 * @thread Any.
4576 */
4577static int iommuAmdIntrRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
4578 PMSIMSG pMsiOut)
4579{
4580 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
4581
4582 IRTE_T Irte;
4583 uint32_t const uMsiInData = pMsiIn->Data.u32;
4584 int rc = iommuAmdIrteRead(pDevIns, idDevice, pDte, pMsiIn->Addr.u64, uMsiInData, enmOp, &Irte);
4585 if (RT_SUCCESS(rc))
4586 {
4587 if (Irte.n.u1RemapEnable)
4588 {
4589 if (!Irte.n.u1GuestMode)
4590 {
4591 if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
4592 {
4593 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, &Irte);
4594#ifdef IOMMU_WITH_IRTE_CACHE
4595 iommuAmdIrteCacheAdd(pDevIns, idDevice, IOMMU_GET_IRTE_OFF(uMsiInData), &Irte);
4596#endif
4597 return VINF_SUCCESS;
4598 }
4599
4600 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
4601 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4602 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4603 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4604 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault,
4605 kIoPageFaultType_IrteRsvdIntType);
4606 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4607 }
4608
4609 LogFunc(("Guest mode not supported -> IOPF\n"));
4610 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4611 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4612 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4613 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
4614 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4615 }
4616
4617 LogFunc(("Remapping disabled -> IOPF\n"));
4618 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4619 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4620 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4621 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
4622 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4623 }
4624
4625 return rc;
4626}
4627
4628
4629/**
4630 * Looks up an MSI interrupt from the interrupt remapping table.
4631 *
4632 * @returns VBox status code.
4633 * @param pDevIns The IOMMU instance data.
4634 * @param idDevice The device ID (bus, device, function).
4635 * @param enmOp The IOMMU operation being performed.
4636 * @param pMsiIn The source MSI.
4637 * @param pMsiOut Where to store the remapped MSI.
4638 *
4639 * @thread Any.
4640 */
4641static int iommuAmdIntrTableLookup(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4642{
4643 LogFlowFunc(("idDevice=%#x (%#x:%#x:%#x) enmOp=%u\n", idDevice, ((idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK),
4644 ((idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK), (idDevice & VBOX_PCI_DEVFN_FUN_MASK),
4645 enmOp));
4646
4647 /* Read the device table entry from memory. */
4648 DTE_T Dte;
4649 int rc = iommuAmdDteRead(pDevIns, idDevice, enmOp, &Dte);
4650 if (RT_SUCCESS(rc))
4651 {
4652#ifdef IOMMU_WITH_IRTE_CACHE
4653 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte);
4654#endif
4655 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
4656 if (Dte.n.u1IntrMapValid)
4657 {
4658 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
4659 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
4660 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
4661 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
4662 { /* likely */ }
4663 else
4664 {
4665 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4666 EVT_ILLEGAL_DTE_T Event;
4667 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4668 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4669 return VERR_IOMMU_INTR_REMAP_FAILED;
4670 }
4671
4672 /*
4673 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
4674 * that's connected through HyperTransport it might be possible; but for us, it
4675 * doesn't seem we need to specially handle these pins.
4676 */
4677
4678 /*
4679 * Validate the MSI source address.
4680 *
4681 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
4682 * CPU is concerned, the MSI region is fixed and we must ensure no other device
4683 * claims the region as I/O space.
4684 *
4685 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
4686 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
4687 * See Intel spec. 10.11.1 "Message Address Register Format".
4688 */
4689 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
4690 {
4691 /*
4692 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
4693 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
4694 */
4695 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
4696 bool fPassThru = false;
4697 switch (u8DeliveryMode)
4698 {
4699 case VBOX_MSI_DELIVERY_MODE_FIXED:
4700 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
4701 {
4702 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
4703 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
4704 {
4705 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
4706 uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
4707 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4708 {
4709 /*
4710 * We don't support guest interrupt remapping yet. When we do, we'll need to
4711 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
4712 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
4713 * already reads the control register, add that as a parameter when we eventually
4714 * support guest interrupt remapping. For now, just assert.
4715 */
4716 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4717 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
4718 NOREF(pThis);
4719
4720 return iommuAmdIntrRemap(pDevIns, idDevice, &Dte, enmOp, pMsiIn, pMsiOut);
4721 }
4722
4723 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
4724 EVT_ILLEGAL_DTE_T Event;
4725 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
4726 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
4727 return VERR_IOMMU_INTR_REMAP_FAILED;
4728 }
4729
4730 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
4731 {
4732 fPassThru = true;
4733 break;
4734 }
4735
4736 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
4737 {
4738 LogRelMax(10, ("%s: Remapping disallowed for fixed/arbitrated interrupt %#x -> Target abort\n",
4739 IOMMU_LOG_PFX, pMsiIn->Data.n.u8Vector));
4740 iommuAmdSetPciTargetAbort(pDevIns);
4741 return VERR_IOMMU_INTR_REMAP_DENIED;
4742 }
4743
4744 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD); /* Paranoia. */
4745 LogRelMax(10, ("%s: IntCtl mode invalid %#x -> Illegal DTE\n", IOMMU_LOG_PFX, uIntrCtrl));
4746 EVT_ILLEGAL_DTE_T Event;
4747 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4748 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
4749 return VERR_IOMMU_INTR_REMAP_FAILED;
4750 }
4751
4752 /* SMIs are passed through unmapped. We don't implement SMI filters. */
4753 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
4754 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
4755 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
4756 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
4757 default:
4758 {
4759 LogRelMax(10, ("%s: MSI data delivery mode invalid %#x -> Target abort\n", IOMMU_LOG_PFX,
4760 u8DeliveryMode));
4761 iommuAmdSetPciTargetAbort(pDevIns);
4762 return VERR_IOMMU_INTR_REMAP_FAILED;
4763 }
4764 }
4765
4766 /*
4767 * For those other than fixed and arbitrated interrupts, destination mode must be 0 (physical).
4768 * See AMD IOMMU spec. The note below Table 19: "IOMMU Controls and Actions for Upstream Interrupts".
4769 */
4770 if ( u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO
4771 || !pMsiIn->Addr.n.u1DestMode)
4772 {
4773 if (fPassThru)
4774 {
4775 *pMsiOut = *pMsiIn;
4776 return VINF_SUCCESS;
4777 }
4778 LogRelMax(10, ("%s: Remapping/passthru disallowed for interrupt %#x -> Target abort\n", IOMMU_LOG_PFX,
4779 pMsiIn->Data.n.u8Vector));
4780 }
4781 else
4782 LogRelMax(10, ("%s: Logical destination mode invalid for delivery mode %#x\n -> Target abort\n",
4783 IOMMU_LOG_PFX, u8DeliveryMode));
4784
4785 iommuAmdSetPciTargetAbort(pDevIns);
4786 return VERR_IOMMU_INTR_REMAP_DENIED;
4787 }
4788 else
4789 {
4790 /** @todo should be cause a PCI target abort here? */
4791 LogRelMax(10, ("%s: MSI address region invalid %#RX64\n", IOMMU_LOG_PFX, pMsiIn->Addr.u64));
4792 return VERR_IOMMU_INTR_REMAP_FAILED;
4793 }
4794 }
4795 else
4796 {
4797 LogFlowFunc(("DTE interrupt map not valid\n"));
4798 *pMsiOut = *pMsiIn;
4799 return VINF_SUCCESS;
4800 }
4801 }
4802
4803 LogFunc(("Failed to read device table entry. idDevice=%#x rc=%Rrc\n", idDevice, rc));
4804 return VERR_IOMMU_INTR_REMAP_FAILED;
4805}
4806
4807
4808/**
4809 * Interrupt remap request from a device.
4810 *
4811 * @returns VBox status code.
4812 * @param pDevIns The IOMMU device instance.
4813 * @param idDevice The device ID (bus, device, function).
4814 * @param pMsiIn The source MSI.
4815 * @param pMsiOut Where to store the remapped MSI.
4816 */
4817static DECLCALLBACK(int) iommuAmdMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4818{
4819 /* Validate. */
4820 Assert(pDevIns);
4821 Assert(pMsiIn);
4822 Assert(pMsiOut);
4823
4824 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4825
4826 /* If this MSI was generated by the IOMMU itself, it's not subject to remapping, see @bugref{9654#c104}. */
4827 if (idDevice == pThis->uPciAddress)
4828 return VERR_IOMMU_CANNOT_CALL_SELF;
4829
4830 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
4831 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4832 if (Ctrl.n.u1IommuEn)
4833 {
4834 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
4835
4836 int rc;
4837#ifdef IOMMU_WITH_IRTE_CACHE
4838 STAM_PROFILE_ADV_START(&pThis->StatProfIrteCacheLookup, a);
4839 rc = iommuAmdIrteCacheLookup(pDevIns, idDevice, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4840 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteCacheLookup, a);
4841 if (RT_SUCCESS(rc))
4842 {
4843 STAM_COUNTER_INC(&pThis->StatIntrCacheHit);
4844 return VINF_SUCCESS;
4845 }
4846 STAM_COUNTER_INC(&pThis->StatIntrCacheMiss);
4847#endif
4848
4849 STAM_PROFILE_ADV_START(&pThis->StatProfIrteLookup, a);
4850 rc = iommuAmdIntrTableLookup(pDevIns, idDevice, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4851 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteLookup, a);
4852 return rc;
4853 }
4854
4855 *pMsiOut = *pMsiIn;
4856 return VINF_SUCCESS;
4857}
4858
4859
4860/**
4861 * @callback_method_impl{FNIOMMMIONEWWRITE}
4862 */
4863static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
4864{
4865 NOREF(pvUser);
4866 Assert(cb == 4 || cb == 8);
4867 Assert(!(off & (cb - 1)));
4868
4869 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4870 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
4871
4872 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
4873 return iommuAmdRegisterWrite(pDevIns, off, cb, uValue);
4874}
4875
4876
4877/**
4878 * @callback_method_impl{FNIOMMMIONEWREAD}
4879 */
4880static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
4881{
4882 NOREF(pvUser);
4883 Assert(cb == 4 || cb == 8);
4884 Assert(!(off & (cb - 1)));
4885
4886 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4887 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
4888
4889 uint64_t uResult;
4890 VBOXSTRICTRC rcStrict = iommuAmdRegisterRead(pDevIns, off, &uResult);
4891 if (rcStrict == VINF_SUCCESS)
4892 {
4893 if (cb == 8)
4894 *(uint64_t *)pv = uResult;
4895 else
4896 *(uint32_t *)pv = (uint32_t)uResult;
4897 }
4898
4899 return rcStrict;
4900}
4901
4902
4903#ifdef IN_RING3
4904/**
4905 * Processes an IOMMU command.
4906 *
4907 * @returns VBox status code.
4908 * @param pDevIns The IOMMU device instance.
4909 * @param pCmd The command to process.
4910 * @param GCPhysCmd The system physical address of the command.
4911 * @param pEvtError Where to store the error event in case of failures.
4912 *
4913 * @thread Command thread.
4914 */
4915static int iommuAmdR3CmdProcess(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
4916{
4917 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4918 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4919
4920 STAM_COUNTER_INC(&pThis->StatCmd);
4921
4922 uint8_t const bCmd = pCmd->n.u4Opcode;
4923 switch (bCmd)
4924 {
4925 case IOMMU_CMD_COMPLETION_WAIT:
4926 {
4927 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
4928
4929 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
4930 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
4931
4932 /* Validate reserved bits in the command. */
4933 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
4934 {
4935 /* If Completion Store is requested, write the StoreData to the specified address. */
4936 if (pCmdComWait->n.u1Store)
4937 {
4938 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
4939 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
4940 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
4941 if (RT_FAILURE(rc))
4942 {
4943 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
4944 GCPhysStore, rc));
4945 iommuAmdCmdHwErrorEventInit(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
4946 return VERR_IOMMU_CMD_HW_ERROR;
4947 }
4948 }
4949
4950 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
4951 if (pCmdComWait->n.u1Interrupt)
4952 {
4953 IOMMU_LOCK(pDevIns, pThisR3);
4954 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
4955 bool const fRaiseInt = pThis->Ctrl.n.u1CompWaitIntrEn;
4956 IOMMU_UNLOCK(pDevIns, pThisR3);
4957 if (fRaiseInt)
4958 iommuAmdMsiInterruptRaise(pDevIns);
4959 }
4960 return VINF_SUCCESS;
4961 }
4962 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4963 return VERR_IOMMU_CMD_INVALID_FORMAT;
4964 }
4965
4966 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
4967 {
4968 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
4969 PCCMD_INV_DTE_T pCmdInvDte = (PCCMD_INV_DTE_T)pCmd;
4970 AssertCompile(sizeof(*pCmdInvDte) == sizeof(*pCmd));
4971
4972 /* Validate reserved bits in the command. */
4973 if ( !(pCmdInvDte->au64[0] & ~IOMMU_CMD_INV_DTE_QWORD_0_VALID_MASK)
4974 && !(pCmdInvDte->au64[1] & ~IOMMU_CMD_INV_DTE_QWORD_1_VALID_MASK))
4975 {
4976#ifdef IOMMU_WITH_DTE_CACHE
4977 iommuAmdDteCacheRemove(pDevIns, pCmdInvDte->n.u16DevId);
4978#endif
4979 return VINF_SUCCESS;
4980 }
4981 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4982 return VERR_IOMMU_CMD_INVALID_FORMAT;
4983 }
4984
4985 case IOMMU_CMD_INV_IOMMU_PAGES:
4986 {
4987 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
4988 PCCMD_INV_IOMMU_PAGES_T pCmdInvPages = (PCCMD_INV_IOMMU_PAGES_T)pCmd;
4989 AssertCompile(sizeof(*pCmdInvPages) == sizeof(*pCmd));
4990
4991 /* Validate reserved bits in the command. */
4992 if ( !(pCmdInvPages->au64[0] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_0_VALID_MASK)
4993 && !(pCmdInvPages->au64[1] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_1_VALID_MASK))
4994 {
4995#ifdef IOMMU_WITH_IOTLBE_CACHE
4996 uint64_t const uIova = RT_MAKE_U64(pCmdInvPages->n.u20AddrLo << X86_PAGE_4K_SHIFT, pCmdInvPages->n.u32AddrHi);
4997 uint16_t const idDomain = pCmdInvPages->n.u16DomainId;
4998 uint8_t cShift;
4999 if (!pCmdInvPages->n.u1Size)
5000 cShift = X86_PAGE_4K_SHIFT;
5001 else
5002 {
5003 /* Find the first clear bit starting from bit 12 to 64 of the I/O virtual address. */
5004 unsigned const uFirstZeroBit = ASMBitLastSetU64(~(uIova >> X86_PAGE_4K_SHIFT));
5005 cShift = X86_PAGE_4K_SHIFT + uFirstZeroBit;
5006
5007 /*
5008 * For the address 0x7ffffffffffff000, cShift would be 76 (12+64) and the code below
5009 * would do the right thing by clearing the entire cache for the specified domain ID.
5010 *
5011 * However, for the address 0xfffffffffffff000, cShift would be computed as 12.
5012 * IOMMU behavior is undefined in this case, so it's safe to invalidate just one page.
5013 * A debug-time assert is in place here to let us know if any software tries this.
5014 *
5015 * See AMD IOMMU spec. 2.4.3 "INVALIDATE_IOMMU_PAGES".
5016 * See AMD IOMMU spec. Table 14: "Example Page Size Encodings".
5017 */
5018 Assert(uIova != UINT64_C(0xfffffffffffff000));
5019 }
5020
5021 /*
5022 * Validate invalidation size.
5023 * See AMD IOMMU spec. 2.2.3 "I/O Page Tables for Host Translations".
5024 */
5025 if ( cShift >= 12 /* 4 KB */
5026 && cShift <= 51 /* 2 PB */)
5027 {
5028 /* Remove the range of I/O virtual addresses requesting to be invalidated. */
5029 size_t const cbIova = RT_BIT_64(cShift);
5030 iommuAmdIotlbRemoveRange(pDevIns, idDomain, uIova, cbIova);
5031 }
5032 else
5033 {
5034 /*
5035 * The guest provided size is invalid or exceeds the largest, meaningful page size.
5036 * In such situations we must remove all ranges for the specified domain ID.
5037 */
5038 iommuAmdIotlbRemoveDomainId(pDevIns, idDomain);
5039 }
5040#endif
5041 return VINF_SUCCESS;
5042 }
5043 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5044 return VERR_IOMMU_CMD_INVALID_FORMAT;
5045 }
5046
5047 case IOMMU_CMD_INV_IOTLB_PAGES:
5048 {
5049 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
5050
5051 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
5052 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
5053 {
5054 /** @todo IOMMU: Implement remote IOTLB invalidation. */
5055 return VERR_NOT_IMPLEMENTED;
5056 }
5057 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5058 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5059 }
5060
5061 case IOMMU_CMD_INV_INTR_TABLE:
5062 {
5063 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
5064
5065 PCCMD_INV_INTR_TABLE_T pCmdInvIntrTable = (PCCMD_INV_INTR_TABLE_T)pCmd;
5066 AssertCompile(sizeof(*pCmdInvIntrTable) == sizeof(*pCmd));
5067
5068 /* Validate reserved bits in the command. */
5069 if ( !(pCmdInvIntrTable->au64[0] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_0_VALID_MASK)
5070 && !(pCmdInvIntrTable->au64[1] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_1_VALID_MASK))
5071 {
5072#ifdef IOMMU_WITH_IRTE_CACHE
5073 iommuAmdIrteCacheRemove(pDevIns, pCmdInvIntrTable->u.u16DevId);
5074#endif
5075 return VINF_SUCCESS;
5076 }
5077 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5078 return VERR_IOMMU_CMD_INVALID_FORMAT;
5079 }
5080
5081 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
5082 {
5083 /* Linux doesn't use prefetching of IOMMU pages, so we don't bother for now. */
5084 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
5085 Assert(!pThis->ExtFeat.n.u1PrefetchSup);
5086 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5087 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5088 }
5089
5090 case IOMMU_CMD_COMPLETE_PPR_REQ:
5091 {
5092 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
5093
5094 /* We don't support PPR requests yet. */
5095 Assert(!pThis->ExtFeat.n.u1PprSup);
5096 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5097 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5098 }
5099
5100 case IOMMU_CMD_INV_IOMMU_ALL:
5101 {
5102 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
5103 if (pThis->ExtFeat.n.u1InvAllSup)
5104 {
5105 PCCMD_INV_IOMMU_ALL_T pCmdInvAll = (PCCMD_INV_IOMMU_ALL_T)pCmd;
5106 AssertCompile(sizeof(*pCmdInvAll) == sizeof(*pCmd));
5107
5108 /* Validate reserved bits in the command. */
5109 if ( !(pCmdInvAll->au64[0] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_0_VALID_MASK)
5110 && !(pCmdInvAll->au64[1] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_1_VALID_MASK))
5111 {
5112#ifdef IOMMU_WITH_DTE_CACHE
5113 iommuAmdDteCacheRemoveAll(pDevIns);
5114#endif
5115#ifdef IOMMU_WITH_IOTLBE_CACHE
5116 iommuAmdIotlbRemoveAll(pDevIns);
5117#endif
5118 return VINF_SUCCESS;
5119 }
5120 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5121 return VERR_IOMMU_CMD_INVALID_FORMAT;
5122 }
5123 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5124 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5125 }
5126 }
5127
5128 STAM_COUNTER_DEC(&pThis->StatCmd);
5129 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
5130 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5131 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5132}
5133
5134
5135/**
5136 * The IOMMU command thread.
5137 *
5138 * @returns VBox status code.
5139 * @param pDevIns The IOMMU device instance.
5140 * @param pThread The command thread.
5141 */
5142static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5143{
5144 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5145 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5146
5147 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
5148 return VINF_SUCCESS;
5149
5150 /*
5151 * Pre-allocate the maximum command buffer size supported by the IOMMU.
5152 * This avoid trashing the heap as well as not wasting time allocating
5153 * and freeing buffers while processing commands.
5154 */
5155 size_t const cbMaxCmdBuf = sizeof(CMD_GENERIC_T) * iommuAmdGetBufMaxEntries(15);
5156 void *pvCmds = RTMemAllocZ(cbMaxCmdBuf);
5157 AssertPtrReturn(pvCmds, VERR_NO_MEMORY);
5158
5159 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
5160 {
5161 /*
5162 * Sleep perpetually until we are woken up to process commands.
5163 */
5164 bool const fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
5165 if (!fSignaled)
5166 {
5167 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
5168 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
5169 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
5170 break;
5171 Log4Func(("Woken up with rc=%Rrc\n", rc));
5172 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
5173 }
5174
5175 /*
5176 * Fetch and process IOMMU commands.
5177 */
5178 /** @todo r=ramshankar: We currently copy all commands from guest memory into a
5179 * temporary host buffer before processing them as a batch. If we want to
5180 * save on host memory a bit, we could (once PGM has the necessary APIs)
5181 * lock the page mappings page mappings and access them directly. */
5182 IOMMU_LOCK(pDevIns, pThisR3);
5183
5184 if (pThis->Status.n.u1CmdBufRunning)
5185 {
5186 /* Get the offsets we need to read commands from memory (circular buffer offset). */
5187 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
5188 uint32_t const offTail = pThis->CmdBufTailPtr.n.off;
5189 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
5190
5191 /* Validate. */
5192 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
5193 Assert(offHead < cbCmdBuf);
5194 Assert(cbCmdBuf <= cbMaxCmdBuf);
5195
5196 if (offHead != offTail)
5197 {
5198 /* Read the entire command buffer from memory (avoids multiple PGM calls). */
5199 RTGCPHYS const GCPhysCmdBufBase = pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
5200
5201 IOMMU_UNLOCK(pDevIns, pThisR3);
5202 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmdBufBase, pvCmds, cbCmdBuf);
5203 IOMMU_LOCK(pDevIns, pThisR3);
5204
5205 if (RT_SUCCESS(rc))
5206 {
5207 /* Indicate to software we've fetched all commands from the buffer. */
5208 pThis->CmdBufHeadPtr.n.off = offTail;
5209
5210 /* Allow IOMMU to do other work while we process commands. */
5211 IOMMU_UNLOCK(pDevIns, pThisR3);
5212
5213 /* Process the fetched commands. */
5214 EVT_GENERIC_T EvtError;
5215 do
5216 {
5217 PCCMD_GENERIC_T pCmd = (PCCMD_GENERIC_T)((uintptr_t)pvCmds + offHead);
5218 rc = iommuAmdR3CmdProcess(pDevIns, pCmd, GCPhysCmdBufBase + offHead, &EvtError);
5219 if (RT_FAILURE(rc))
5220 {
5221 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
5222 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
5223 {
5224 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
5225 iommuAmdIllegalCmdEventRaise(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
5226 }
5227 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
5228 {
5229 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
5230 LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", pCmd->n.u4Opcode));
5231 iommuAmdCmdHwErrorEventRaise(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
5232 }
5233 break;
5234 }
5235
5236 /* Move to the next command in the circular buffer. */
5237 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
5238 } while (offHead != offTail);
5239 }
5240 else
5241 {
5242 LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmdBufBase, rc));
5243 EVT_CMD_HW_ERR_T EvtCmdHwErr;
5244 iommuAmdCmdHwErrorEventInit(GCPhysCmdBufBase, &EvtCmdHwErr);
5245 iommuAmdCmdHwErrorEventRaise(pDevIns, &EvtCmdHwErr);
5246
5247 IOMMU_UNLOCK(pDevIns, pThisR3);
5248 }
5249 }
5250 else
5251 IOMMU_UNLOCK(pDevIns, pThisR3);
5252 }
5253 else
5254 IOMMU_UNLOCK(pDevIns, pThisR3);
5255 }
5256
5257 RTMemFree(pvCmds);
5258 LogFlowFunc(("Command thread terminating\n"));
5259 return VINF_SUCCESS;
5260}
5261
5262
5263/**
5264 * Wakes up the command thread so it can respond to a state change.
5265 *
5266 * @returns VBox status code.
5267 * @param pDevIns The IOMMU device instance.
5268 * @param pThread The command thread.
5269 */
5270static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5271{
5272 RT_NOREF(pThread);
5273 Log4Func(("\n"));
5274 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5275 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
5276}
5277
5278
5279/**
5280 * @callback_method_impl{FNPCICONFIGREAD}
5281 */
5282static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5283 unsigned cb, uint32_t *pu32Value)
5284{
5285 /** @todo IOMMU: PCI config read stat counter. */
5286 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
5287 Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
5288 return rcStrict;
5289}
5290
5291
5292/**
5293 * Sets up the IOMMU MMIO region (usually in response to an IOMMU base address
5294 * register write).
5295 *
5296 * @returns VBox status code.
5297 * @param pDevIns The IOMMU instance data.
5298 *
5299 * @remarks Call this function only when the IOMMU BAR is enabled.
5300 */
5301static int iommuAmdR3MmioSetup(PPDMDEVINS pDevIns)
5302{
5303 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5304 Assert(pThis->IommuBar.n.u1Enable);
5305 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
5306 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
5307 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
5308 RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
5309
5310 /* If the MMIO region is already mapped at the specified address, we're done. */
5311 Assert(GCPhysMmioBase != NIL_RTGCPHYS);
5312 if (GCPhysMmioBasePrev == GCPhysMmioBase)
5313 return VINF_SUCCESS;
5314
5315 /* Unmap the previous MMIO region (which is at a different address). */
5316 if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
5317 {
5318 LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
5319 int rc = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
5320 if (RT_FAILURE(rc))
5321 {
5322 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBasePrev, rc));
5323 return rc;
5324 }
5325 }
5326
5327 /* Map the newly specified MMIO region. */
5328 LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
5329 int rc = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
5330 if (RT_FAILURE(rc))
5331 {
5332 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rc));
5333 return rc;
5334 }
5335
5336 return VINF_SUCCESS;
5337}
5338
5339
5340/**
5341 * @callback_method_impl{FNPCICONFIGWRITE}
5342 */
5343static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5344 unsigned cb, uint32_t u32Value)
5345{
5346 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5347
5348 /*
5349 * Discard writes to read-only registers that are specific to the IOMMU.
5350 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
5351 * See PCI spec. 6.1. "Configuration Space Organization".
5352 */
5353 switch (uAddress)
5354 {
5355 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
5356 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
5357 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
5358 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
5359 {
5360 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
5361 return VINF_SUCCESS;
5362 }
5363 }
5364
5365 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5366 IOMMU_LOCK(pDevIns, pThisR3);
5367
5368 VBOXSTRICTRC rcStrict;
5369 switch (uAddress)
5370 {
5371 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
5372 {
5373 if (!pThis->IommuBar.n.u1Enable)
5374 {
5375 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
5376 if (pThis->IommuBar.n.u1Enable)
5377 rcStrict = iommuAmdR3MmioSetup(pDevIns);
5378 else
5379 rcStrict = VINF_SUCCESS;
5380 }
5381 else
5382 {
5383 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
5384 rcStrict = VINF_SUCCESS;
5385 }
5386 break;
5387 }
5388
5389 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
5390 {
5391 if (!pThis->IommuBar.n.u1Enable)
5392 {
5393 AssertCompile((IOMMU_BAR_VALID_MASK >> 32) == 0xffffffff);
5394 pThis->IommuBar.au32[1] = u32Value;
5395 }
5396 else
5397 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
5398 rcStrict = VINF_SUCCESS;
5399 break;
5400 }
5401
5402 case IOMMU_PCI_OFF_MSI_CAP_HDR:
5403 {
5404 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
5405 RT_FALL_THRU();
5406 }
5407 default:
5408 {
5409 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
5410 break;
5411 }
5412 }
5413
5414 IOMMU_UNLOCK(pDevIns, pThisR3);
5415
5416 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
5417 return rcStrict;
5418}
5419
5420
5421/**
5422 * @callback_method_impl{FNDBGFHANDLERDEV}
5423 */
5424static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5425{
5426 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5427 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5428 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5429
5430 bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
5431
5432 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
5433 /* Device Table Base Addresses (all segments). */
5434 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
5435 {
5436 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
5437 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
5438 if (fVerbose)
5439 {
5440 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
5441 IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
5442 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5443 DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
5444 }
5445 }
5446 /* Command Buffer Base Address Register. */
5447 {
5448 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
5449 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
5450 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5451 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5452 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
5453 if (fVerbose)
5454 {
5455 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5456 CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
5457 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5458 cEntries, cbBuffer);
5459 }
5460 }
5461 /* Event Log Base Address Register. */
5462 {
5463 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
5464 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
5465 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5466 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5467 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
5468 if (fVerbose)
5469 {
5470 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5471 EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5472 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5473 cEntries, cbBuffer);
5474 }
5475 }
5476 /* IOMMU Control Register. */
5477 {
5478 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
5479 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
5480 if (fVerbose)
5481 {
5482 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
5483 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
5484 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
5485 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5486 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5487 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
5488 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
5489 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
5490 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
5491 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
5492 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
5493 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
5494 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
5495 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
5496 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
5497 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
5498 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
5499 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
5500 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
5501 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
5502 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
5503 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
5504 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
5505 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
5506 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
5507 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
5508 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
5509 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
5510 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
5511 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
5512 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
5513 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
5514 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
5515 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
5516 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
5517 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
5518 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
5519 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
5520 }
5521 }
5522 /* Exclusion Base Address Register. */
5523 {
5524 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
5525 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
5526 if (fVerbose)
5527 {
5528 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
5529 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
5530 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5531 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
5532 }
5533 }
5534 /* Exclusion Range Limit Register. */
5535 {
5536 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
5537 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
5538 if (fVerbose)
5539 {
5540 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n",
5541 (ExclRangeLimit.n.u40ExclRangeLimit << X86_PAGE_4K_SHIFT) | X86_PAGE_4K_OFFSET_MASK);
5542 }
5543 }
5544 /* Extended Feature Register. */
5545 {
5546 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
5547 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
5548 if (fVerbose)
5549 {
5550 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
5551 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
5552 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
5553 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
5554 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
5555 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
5556 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
5557 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
5558 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
5559 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
5560 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
5561 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
5562 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
5563 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
5564 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
5565 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
5566 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
5567 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
5568 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
5569 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
5570 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
5571 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
5572 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
5573 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
5574 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
5575 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
5576 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
5577 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
5578 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
5579 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
5580 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
5581 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
5582 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
5583 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
5584 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
5585 }
5586 }
5587 /* PPR Log Base Address Register. */
5588 {
5589 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
5590 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
5591 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5592 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5593 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
5594 if (fVerbose)
5595 {
5596 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5597 PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5598 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5599 cEntries, cbBuffer);
5600 }
5601 }
5602 /* Hardware Event (Hi) Register. */
5603 {
5604 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
5605 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
5606 if (fVerbose)
5607 {
5608 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
5609 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
5610 }
5611 }
5612 /* Hardware Event (Lo) Register. */
5613 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
5614 /* Hardware Event Status. */
5615 {
5616 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
5617 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
5618 if (fVerbose)
5619 {
5620 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
5621 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
5622 }
5623 }
5624 /* Guest Virtual-APIC Log Base Address Register. */
5625 {
5626 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
5627 uint8_t const uEncodedLen = GALogBar.n.u4Len;
5628 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5629 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5630 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
5631 if (fVerbose)
5632 {
5633 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5634 GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5635 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5636 cEntries, cbBuffer);
5637 }
5638 }
5639 /* Guest Virtual-APIC Log Tail Address Register. */
5640 {
5641 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
5642 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
5643 if (fVerbose)
5644 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
5645 }
5646 /* PPR Log B Base Address Register. */
5647 {
5648 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
5649 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
5650 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5651 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5652 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
5653 if (fVerbose)
5654 {
5655 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5656 PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5657 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5658 cEntries, cbBuffer);
5659 }
5660 }
5661 /* Event Log B Base Address Register. */
5662 {
5663 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
5664 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
5665 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5666 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5667 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
5668 if (fVerbose)
5669 {
5670 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5671 EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5672 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5673 cEntries, cbBuffer);
5674 }
5675 }
5676 /* Device-Specific Feature Extension Register. */
5677 {
5678 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
5679 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
5680 if (fVerbose)
5681 {
5682 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
5683 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
5684 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
5685 }
5686 }
5687 /* Device-Specific Control Extension Register. */
5688 {
5689 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
5690 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
5691 if (fVerbose)
5692 {
5693 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
5694 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
5695 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
5696 }
5697 }
5698 /* Device-Specific Status Extension Register. */
5699 {
5700 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
5701 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
5702 if (fVerbose)
5703 {
5704 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
5705 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
5706 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
5707 }
5708 }
5709 /* Miscellaneous Information Register (Lo and Hi). */
5710 {
5711 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
5712 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
5713 if (fVerbose)
5714 {
5715 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
5716 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
5717 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
5718 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
5719 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
5720 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
5721 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
5722 }
5723 }
5724 /* MSI Capability Header. */
5725 {
5726 MSI_CAP_HDR_T MsiCapHdr;
5727 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
5728 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
5729 if (fVerbose)
5730 {
5731 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
5732 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
5733 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
5734 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
5735 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
5736 }
5737 }
5738 /* MSI Address Register (Lo and Hi). */
5739 {
5740 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
5741 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
5742 MSIADDR MsiAddr;
5743 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
5744 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
5745 if (fVerbose)
5746 {
5747 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
5748 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
5749 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
5750 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
5751 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
5752 }
5753 }
5754 /* MSI Data. */
5755 {
5756 MSIDATA MsiData;
5757 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
5758 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
5759 if (fVerbose)
5760 {
5761 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
5762 MsiData.n.u8Vector);
5763 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
5764 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
5765 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
5766 "level" : "edge");
5767 }
5768 }
5769 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
5770 {
5771 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
5772 MsiMapCapHdr.u32 = 0;
5773 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
5774 if (fVerbose)
5775 {
5776 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
5777 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
5778 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
5779 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
5780 }
5781 }
5782 /* Performance Optimization Control Register. */
5783 {
5784 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
5785 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
5786 if (fVerbose)
5787 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
5788 }
5789 /* XT (x2APIC) General Interrupt Control Register. */
5790 {
5791 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
5792 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
5793 if (fVerbose)
5794 {
5795 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5796 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5797 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5798 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
5799 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
5800 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5801 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5802 }
5803 }
5804 /* XT (x2APIC) PPR Interrupt Control Register. */
5805 {
5806 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
5807 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
5808 if (fVerbose)
5809 {
5810 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5811 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5812 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5813 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
5814 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
5815 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5816 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5817 }
5818 }
5819 /* XT (X2APIC) GA Log Interrupt Control Register. */
5820 {
5821 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
5822 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
5823 if (fVerbose)
5824 {
5825 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5826 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5827 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5828 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
5829 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
5830 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5831 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5832 }
5833 }
5834 /* MARC Registers. */
5835 {
5836 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
5837 {
5838 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
5839 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
5840 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
5841
5842 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
5843 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
5844 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
5845 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
5846
5847 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
5848 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
5849 }
5850 }
5851 /* Reserved Register. */
5852 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
5853 /* Command Buffer Head Pointer Register. */
5854 {
5855 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
5856 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
5857 CmdBufHeadPtr.n.off);
5858 }
5859 /* Command Buffer Tail Pointer Register. */
5860 {
5861 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
5862 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
5863 CmdBufTailPtr.n.off);
5864 }
5865 /* Event Log Head Pointer Register. */
5866 {
5867 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
5868 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
5869 EvtLogHeadPtr.n.off);
5870 }
5871 /* Event Log Tail Pointer Register. */
5872 {
5873 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
5874 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
5875 EvtLogTailPtr.n.off);
5876 }
5877 /* Status Register. */
5878 {
5879 IOMMU_STATUS_T const Status = pThis->Status;
5880 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
5881 if (fVerbose)
5882 {
5883 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
5884 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
5885 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
5886 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
5887 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
5888 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
5889 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
5890 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
5891 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
5892 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
5893 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
5894 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
5895 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
5896 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
5897 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
5898 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
5899 }
5900 }
5901 /* PPR Log Head Pointer. */
5902 {
5903 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
5904 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
5905 PprLogHeadPtr.n.off);
5906 }
5907 /* PPR Log Tail Pointer. */
5908 {
5909 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
5910 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
5911 PprLogTailPtr.n.off);
5912 }
5913 /* Guest Virtual-APIC Log Head Pointer. */
5914 {
5915 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
5916 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
5917 GALogHeadPtr.n.u12GALogPtr);
5918 }
5919 /* Guest Virtual-APIC Log Tail Pointer. */
5920 {
5921 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
5922 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
5923 GALogTailPtr.n.u12GALogPtr);
5924 }
5925 /* PPR Log B Head Pointer. */
5926 {
5927 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
5928 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
5929 PprLogBHeadPtr.n.off);
5930 }
5931 /* PPR Log B Tail Pointer. */
5932 {
5933 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
5934 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
5935 PprLogBTailPtr.n.off);
5936 }
5937 /* Event Log B Head Pointer. */
5938 {
5939 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
5940 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
5941 EvtLogBHeadPtr.n.off);
5942 }
5943 /* Event Log B Tail Pointer. */
5944 {
5945 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
5946 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
5947 EvtLogBTailPtr.n.off);
5948 }
5949 /* PPR Log Auto Response Register. */
5950 {
5951 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
5952 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
5953 if (fVerbose)
5954 {
5955 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
5956 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
5957 }
5958 }
5959 /* PPR Log Overflow Early Warning Indicator Register. */
5960 {
5961 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
5962 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
5963 if (fVerbose)
5964 {
5965 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
5966 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
5967 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
5968 }
5969 }
5970 /* PPR Log Overflow Early Warning Indicator Register. */
5971 {
5972 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
5973 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
5974 if (fVerbose)
5975 {
5976 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
5977 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
5978 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
5979 }
5980 }
5981}
5982
5983
5984/**
5985 * Dumps the DTE via the info callback helper.
5986 *
5987 * @param pHlp The info helper.
5988 * @param pDte The device table entry.
5989 * @param pszPrefix The string prefix.
5990 */
5991static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
5992{
5993 AssertReturnVoid(pHlp);
5994 AssertReturnVoid(pDte);
5995 AssertReturnVoid(pszPrefix);
5996
5997 pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
5998 pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
5999 pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
6000 pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
6001 pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
6002 pDte->n.u40PageTableRootPtrLo << 12);
6003 pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
6004 pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
6005 pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
6006 pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
6007 pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
6008 pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
6009 pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
6010 (pDte->n.u21GstCr3TableRootPtrHi << 31)
6011 | (pDte->n.u16GstCr3TableRootPtrMid << 15)
6012 | (pDte->n.u3GstCr3TableRootPtrLo << 12));
6013 pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
6014 pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
6015 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
6016 pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
6017 pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
6018 pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
6019 pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
6020 pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
6021 pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
6022 pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
6023 pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
6024 pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
6025 pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
6026 uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
6027 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
6028 {
6029 uint16_t const cEntries = IOMMU_DTE_GET_INTR_TAB_ENTRIES(pDte);
6030 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
6031 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
6032 cbIntrTable);
6033 }
6034 else
6035 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
6036 pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
6037 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
6038 pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
6039 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
6040 pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
6041 pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
6042 pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
6043 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
6044 pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
6045 pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
6046 pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
6047 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
6048 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
6049 pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
6050 pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
6051 pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
6052 pHlp->pfnPrintf(pHlp, "\n");
6053}
6054
6055
6056/**
6057 * @callback_method_impl{FNDBGFHANDLERDEV}
6058 */
6059static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6060{
6061 if (pszArgs)
6062 {
6063 uint16_t idDevice = 0;
6064 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &idDevice);
6065 if (RT_SUCCESS(rc))
6066 {
6067 DTE_T Dte;
6068 rc = iommuAmdDteRead(pDevIns, idDevice, IOMMUOP_TRANSLATE_REQ, &Dte);
6069 if (RT_SUCCESS(rc))
6070 {
6071 pHlp->pfnPrintf(pHlp, "DTE for device %#x\n", idDevice);
6072 iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
6073 return;
6074 }
6075 pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", idDevice, idDevice, rc);
6076 }
6077 else
6078 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
6079 }
6080 else
6081 pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
6082}
6083
6084
6085# ifdef IOMMU_WITH_DTE_CACHE
6086/**
6087 * @callback_method_impl{FNDBGFHANDLERDEV}
6088 */
6089static DECLCALLBACK(void) iommuAmdR3DbgInfoDteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6090{
6091 RT_NOREF(pszArgs);
6092 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6093 IOMMU_CACHE_LOCK(pDevIns, pThis);
6094
6095 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDeviceIds);
6096 pHlp->pfnPrintf(pHlp, "DTE Cache: Capacity=%u entries\n", cDteCache);
6097 for (uint16_t i = 0; i < cDteCache; i++)
6098 {
6099 uint16_t const idDevice = pThis->aDeviceIds[i];
6100 if (idDevice)
6101 {
6102 pHlp->pfnPrintf(pHlp, " Entry[%u]: Device=%#x (BDF %02x:%02x.%d)\n", i, idDevice,
6103 (idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6104 (idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6105 idDevice & VBOX_PCI_DEVFN_FUN_MASK);
6106
6107 PCDTECACHE pDteCache = &pThis->aDteCache[i];
6108 pHlp->pfnPrintf(pHlp, " Flags = %#x\n", pDteCache->fFlags);
6109 pHlp->pfnPrintf(pHlp, " Domain Id = %u\n", pDteCache->idDomain);
6110 pHlp->pfnPrintf(pHlp, "\n");
6111 }
6112 }
6113 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
6114}
6115# endif /* IOMMU_WITH_DTE_CACHE */
6116
6117
6118# ifdef IOMMU_WITH_IOTLBE_CACHE
6119/**
6120 * @callback_method_impl{FNDBGFHANDLERDEV}
6121 */
6122static DECLCALLBACK(void) iommuAmdR3DbgInfoIotlb(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6123{
6124 if (pszArgs)
6125 {
6126 uint16_t idDomain = 0;
6127 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &idDomain);
6128 if (RT_SUCCESS(rc))
6129 {
6130 pHlp->pfnPrintf(pHlp, "IOTLBEs for domain %u (%#x):\n", idDomain, idDomain);
6131 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6132 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6133 IOTLBEINFOARG Args;
6134 Args.pIommuR3 = pThisR3;
6135 Args.pHlp = pHlp;
6136 Args.idDomain = idDomain;
6137
6138 IOMMU_CACHE_LOCK(pDevIns, pThis);
6139 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdR3IotlbEntryInfo, &Args);
6140 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
6141 }
6142 else
6143 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit domain ID. rc=%Rrc\n", rc);
6144 }
6145 else
6146 pHlp->pfnPrintf(pHlp, "Missing domain ID.\n");
6147}
6148# endif /* IOMMU_WITH_IOTLBE_CACHE */
6149
6150
6151# ifdef IOMMU_WITH_IRTE_CACHE
6152/**
6153 * Gets the interrupt type name for an interrupt type in the IRTE.
6154 *
6155 * @returns The interrupt type name.
6156 * @param uIntrType The interrupt type (as specified in the IRTE).
6157 */
6158static const char *iommuAmdIrteGetIntrTypeName(uint8_t uIntrType)
6159{
6160 switch (uIntrType)
6161 {
6162 case VBOX_MSI_DELIVERY_MODE_FIXED: return "Fixed";
6163 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO: return "Arbitrated";
6164 default: return "<Reserved>";
6165 }
6166}
6167
6168
6169/**
6170 * @callback_method_impl{FNDBGFHANDLERDEV}
6171 */
6172static DECLCALLBACK(void) iommuAmdR3DbgInfoIrteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6173{
6174 RT_NOREF(pszArgs);
6175
6176 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6177 IOMMU_CACHE_LOCK(pDevIns, pThis);
6178
6179 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
6180 pHlp->pfnPrintf(pHlp, "IRTE Cache: Capacity=%u entries\n", cIrteCache);
6181 for (uint16_t idxIrte = 0; idxIrte < cIrteCache; idxIrte++)
6182 {
6183 PCIRTECACHE pIrteCache = &pThis->aIrteCache[idxIrte];
6184 uint32_t const uKey = pIrteCache->uKey;
6185 if (uKey != IOMMU_IRTE_CACHE_KEY_NIL)
6186 {
6187 uint16_t const idDevice = IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(uKey);
6188 uint16_t const offIrte = IOMMU_IRTE_CACHE_KEY_GET_OFF(uKey);
6189 pHlp->pfnPrintf(pHlp, " Entry[%u]: Offset=%#x Device=%#x (BDF %02x:%02x.%d)\n",
6190 idxIrte, offIrte, idDevice,
6191 (idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6192 (idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6193 idDevice & VBOX_PCI_DEVFN_FUN_MASK);
6194
6195 PCIRTE_T pIrte = &pIrteCache->Irte;
6196 pHlp->pfnPrintf(pHlp, " Remap Enable = %RTbool\n", pIrte->n.u1RemapEnable);
6197 pHlp->pfnPrintf(pHlp, " Suppress IOPF = %RTbool\n", pIrte->n.u1SuppressIoPf);
6198 pHlp->pfnPrintf(pHlp, " Interrupt Type = %#x (%s)\n", pIrte->n.u3IntrType,
6199 iommuAmdIrteGetIntrTypeName(pIrte->n.u3IntrType));
6200 pHlp->pfnPrintf(pHlp, " Request EOI = %RTbool\n", pIrte->n.u1ReqEoi);
6201 pHlp->pfnPrintf(pHlp, " Destination mode = %s\n", pIrte->n.u1DestMode ? "Logical" : "Physical");
6202 pHlp->pfnPrintf(pHlp, " Destination Id = %u\n", pIrte->n.u8Dest);
6203 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", pIrte->n.u8Vector, pIrte->n.u8Vector);
6204 pHlp->pfnPrintf(pHlp, "\n");
6205 }
6206 }
6207 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
6208}
6209# endif /* IOMMU_WITH_IRTE_CACHE */
6210
6211
6212/**
6213 * @callback_method_impl{FNDBGFHANDLERDEV}
6214 */
6215static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6216{
6217 RT_NOREF(pszArgs);
6218
6219 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6220 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6221 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6222 NOREF(pPciDev);
6223
6224 uint8_t cSegments = 0;
6225 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6226 {
6227 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6228 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6229 if (GCPhysDevTab)
6230 ++cSegments;
6231 }
6232
6233 pHlp->pfnPrintf(pHlp, "AMD-IOMMU device tables with address translations enabled:\n");
6234 pHlp->pfnPrintf(pHlp, " DTE Segments=%u\n", cSegments);
6235 if (!cSegments)
6236 return;
6237
6238 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6239 {
6240 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6241 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6242 if (GCPhysDevTab)
6243 {
6244 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
6245 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
6246
6247 void *pvDevTab = RTMemAllocZ(cbDevTab);
6248 if (RT_LIKELY(pvDevTab))
6249 {
6250 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
6251 if (RT_SUCCESS(rc))
6252 {
6253 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
6254 {
6255 PCDTE_T pDte = (PCDTE_T)((uintptr_t)pvDevTab + idxDte * sizeof(DTE_T));
6256 if ( pDte->n.u1Valid
6257 && pDte->n.u1TranslationValid
6258 && pDte->n.u3Mode != 0)
6259 {
6260 pHlp->pfnPrintf(pHlp, " DTE %u (BDF %02x:%02x.%d)\n", idxDte,
6261 (idxDte >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6262 (idxDte >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6263 idxDte & VBOX_PCI_DEVFN_FUN_MASK);
6264 iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
6265 pHlp->pfnPrintf(pHlp, "\n");
6266 }
6267 }
6268 pHlp->pfnPrintf(pHlp, "\n");
6269 }
6270 else
6271 {
6272 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %zu bytes. rc=%Rrc!\n", GCPhysDevTab,
6273 cbDevTab, rc);
6274 }
6275
6276 RTMemFree(pvDevTab);
6277 }
6278 else
6279 {
6280 pHlp->pfnPrintf(pHlp, " Allocating %zu bytes for reading the device table failed!\n", cbDevTab);
6281 return;
6282 }
6283 }
6284 }
6285}
6286
6287
6288/**
6289 * @callback_method_impl{FNSSMDEVSAVEEXEC}
6290 */
6291static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6292{
6293 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6294 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6295 LogFlowFunc(("\n"));
6296
6297 /* First, save ExtFeat and other registers that cannot be modified by the guest. */
6298 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64);
6299 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64);
6300 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64);
6301 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64);
6302 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64);
6303 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg);
6304
6305 /* Next, save all registers that can be modified by the guest. */
6306 pHlp->pfnSSMPutU64(pSSM, pThis->IommuBar.u64);
6307
6308 uint8_t const cDevTabBaseAddrs = RT_ELEMENTS(pThis->aDevTabBaseAddrs);
6309 pHlp->pfnSSMPutU8(pSSM, cDevTabBaseAddrs);
6310 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6311 pHlp->pfnSSMPutU64(pSSM, pThis->aDevTabBaseAddrs[i].u64);
6312
6313 AssertReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8, VERR_IOMMU_IPE_4);
6314 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufBaseAddr.u64);
6315 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBaseAddr.u64);
6316 pHlp->pfnSSMPutU64(pSSM, pThis->Ctrl.u64);
6317 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeBaseAddr.u64);
6318 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeLimit.u64);
6319#if 0
6320 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64); /* read-only, done already (above). */
6321#endif
6322
6323 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBaseAddr.u64);
6324 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtHi.u64);
6325 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtLo);
6326 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtStatus.u64);
6327
6328 pHlp->pfnSSMPutU64(pSSM, pThis->GALogBaseAddr.u64);
6329 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailAddr.u64);
6330
6331 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBBaseAddr.u64);
6332 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBBaseAddr.u64);
6333
6334#if 0
6335 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6336 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6337 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6338
6339 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64); /* read-only, done already (above). */
6340#endif
6341 pHlp->pfnSSMPutU32(pSSM, pThis->PerfOptCtrl.u32);
6342
6343 pHlp->pfnSSMPutU64(pSSM, pThis->XtGenIntrCtrl.u64);
6344 pHlp->pfnSSMPutU64(pSSM, pThis->XtPprIntrCtrl.u64);
6345 pHlp->pfnSSMPutU64(pSSM, pThis->XtGALogIntrCtrl.u64);
6346
6347 size_t const cMarcApers = RT_ELEMENTS(pThis->aMarcApers);
6348 pHlp->pfnSSMPutU8(pSSM, cMarcApers);
6349 for (size_t i = 0; i < cMarcApers; i++)
6350 {
6351 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Base.u64);
6352 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Reloc.u64);
6353 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Length.u64);
6354 }
6355
6356#if 0
6357 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg); /* read-only, done already (above). */
6358#endif
6359
6360 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufHeadPtr.u64);
6361 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufTailPtr.u64);
6362 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogHeadPtr.u64);
6363 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogTailPtr.u64);
6364
6365 pHlp->pfnSSMPutU64(pSSM, pThis->Status.u64);
6366
6367 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogHeadPtr.u64);
6368 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogTailPtr.u64);
6369
6370 pHlp->pfnSSMPutU64(pSSM, pThis->GALogHeadPtr.u64);
6371 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailPtr.u64);
6372
6373 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBHeadPtr.u64);
6374 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBTailPtr.u64);
6375
6376 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBHeadPtr.u64);
6377 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBTailPtr.u64);
6378
6379 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogAutoResp.u64);
6380 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogOverflowEarly.u64);
6381 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBOverflowEarly.u64);
6382
6383 return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
6384}
6385
6386
6387/**
6388 * @callback_method_impl{FNSSMDEVLOADEXEC}
6389 */
6390static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6391{
6392 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6393 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6394 int const rcErr = VERR_SSM_UNEXPECTED_DATA;
6395 LogFlowFunc(("\n"));
6396
6397 /* Validate. */
6398 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
6399 if (uVersion != IOMMU_SAVED_STATE_VERSION)
6400 {
6401 LogRel(("%s: Invalid saved-state version %#x\n", IOMMU_LOG_PFX, uVersion));
6402 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
6403 }
6404
6405 /* Load ExtFeat and other read-only registers first. */
6406 int rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64);
6407 AssertRCReturn(rc, rc);
6408 AssertLogRelMsgReturn(pThis->ExtFeat.n.u2HostAddrTranslateSize < 0x3,
6409 ("ExtFeat.HATS register invalid %#RX64\n", pThis->ExtFeat.u64), rcErr);
6410 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64);
6411 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64);
6412 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64);
6413 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64);
6414 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg);
6415
6416 /* IOMMU base address register. */
6417 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->IommuBar.u64);
6418 AssertRCReturn(rc, rc);
6419 pThis->IommuBar.u64 &= IOMMU_BAR_VALID_MASK;
6420
6421 /* Device table base address registers. */
6422 uint8_t cDevTabBaseAddrs;
6423 rc = pHlp->pfnSSMGetU8(pSSM, &cDevTabBaseAddrs);
6424 AssertRCReturn(rc, rc);
6425 AssertLogRelMsgReturn(cDevTabBaseAddrs > 0 && cDevTabBaseAddrs <= RT_ELEMENTS(pThis->aDevTabBaseAddrs),
6426 ("Device table segment count invalid %#x\n", cDevTabBaseAddrs), rcErr);
6427 AssertCompile(RT_ELEMENTS(pThis->aDevTabBaseAddrs) == RT_ELEMENTS(g_auDevTabSegMaxSizes));
6428 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6429 {
6430 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aDevTabBaseAddrs[i].u64);
6431 AssertRCReturn(rc, rc);
6432 pThis->aDevTabBaseAddrs[i].u64 &= IOMMU_DEV_TAB_BAR_VALID_MASK;
6433 uint16_t const uSegSize = pThis->aDevTabBaseAddrs[i].n.u9Size;
6434 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[i];
6435 AssertLogRelMsgReturn(uSegSize <= uMaxSegSize,
6436 ("Device table [%u] segment size invalid %u (max %u)\n", i, uSegSize, uMaxSegSize), rcErr);
6437 }
6438
6439 /* Command buffer base address register. */
6440 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufBaseAddr.u64);
6441 AssertRCReturn(rc, rc);
6442 pThis->CmdBufBaseAddr.u64 &= IOMMU_CMD_BUF_BAR_VALID_MASK;
6443 AssertLogRelMsgReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8,
6444 ("Command buffer base address invalid %#RX64\n", pThis->CmdBufBaseAddr.u64), rcErr);
6445
6446 /* Event log base address register. */
6447 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBaseAddr.u64);
6448 AssertRCReturn(rc, rc);
6449 pThis->EvtLogBaseAddr.u64 &= IOMMU_EVT_LOG_BAR_VALID_MASK;
6450 AssertLogRelMsgReturn(pThis->EvtLogBaseAddr.n.u4Len >= 8,
6451 ("Event log base address invalid %#RX64\n", pThis->EvtLogBaseAddr.u64), rcErr);
6452
6453 /* Control register. */
6454 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Ctrl.u64);
6455 AssertRCReturn(rc, rc);
6456 pThis->Ctrl.u64 &= IOMMU_CTRL_VALID_MASK;
6457 AssertLogRelMsgReturn(pThis->Ctrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup,
6458 ("Control register invalid %#RX64\n", pThis->Ctrl.u64), rcErr);
6459
6460 /* Exclusion range base address register. */
6461 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeBaseAddr.u64);
6462 AssertRCReturn(rc, rc);
6463 pThis->ExclRangeBaseAddr.u64 &= IOMMU_EXCL_RANGE_BAR_VALID_MASK;
6464
6465 /* Exclusion range limit register. */
6466 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeLimit.u64);
6467 AssertRCReturn(rc, rc);
6468 pThis->ExclRangeLimit.u64 &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
6469 pThis->ExclRangeLimit.u64 |= UINT64_C(0xfff);
6470
6471#if 0
6472 pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64); /* read-only, done already (above). */
6473#endif
6474
6475 /* PPR log base address register. */
6476 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBaseAddr.u64);
6477 AssertRCReturn(rc, rc);
6478 Assert(!pThis->ExtFeat.n.u1PprSup);
6479
6480 /* Hardware event (Hi) register. */
6481 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtHi.u64);
6482 AssertRCReturn(rc, rc);
6483
6484 /* Hardware event (Lo) register. */
6485 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtLo);
6486 AssertRCReturn(rc, rc);
6487
6488 /* Hardware event status register. */
6489 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtStatus.u64);
6490 AssertRCReturn(rc, rc);
6491 pThis->HwEvtStatus.u64 &= IOMMU_HW_EVT_STATUS_VALID_MASK;
6492
6493 /* Guest Virtual-APIC log base address register. */
6494 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogBaseAddr.u64);
6495 AssertRCReturn(rc, rc);
6496 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6497
6498 /* Guest Virtual-APIC log tail address register. */
6499 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailAddr.u64);
6500 AssertRCReturn(rc, rc);
6501 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6502
6503 /* PPR log-B base address register. */
6504 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBBaseAddr.u64);
6505 AssertRCReturn(rc, rc);
6506 Assert(!pThis->ExtFeat.n.u1PprSup);
6507
6508 /* Event log-B base address register. */
6509 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBBaseAddr.u64);
6510 AssertRCReturn(rc, rc);
6511 Assert(!pThis->ExtFeat.n.u2DualPprLogSup);
6512
6513#if 0
6514 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6515 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6516 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6517
6518 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64); /* read-only, done already (above). */
6519#endif
6520
6521 /* Performance optimization control register. */
6522 rc = pHlp->pfnSSMGetU32(pSSM, &pThis->PerfOptCtrl.u32);
6523 AssertRCReturn(rc, rc);
6524 Assert(!pThis->ExtFeat.n.u1PerfOptSup);
6525
6526 /* x2APIC registers. */
6527 {
6528 Assert(!pThis->ExtFeat.n.u1X2ApicSup);
6529
6530 /* x2APIC general interrupt control register. */
6531 pHlp->pfnSSMGetU64(pSSM, &pThis->XtGenIntrCtrl.u64);
6532 AssertRCReturn(rc, rc);
6533
6534 /* x2APIC PPR interrupt control register. */
6535 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtPprIntrCtrl.u64);
6536 AssertRCReturn(rc, rc);
6537
6538 /* x2APIC GA log interrupt control register. */
6539 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtGALogIntrCtrl.u64);
6540 AssertRCReturn(rc, rc);
6541 }
6542
6543 /* MARC (Memory Access and Routing) registers. */
6544 {
6545 uint8_t cMarcApers;
6546 rc = pHlp->pfnSSMGetU8(pSSM, &cMarcApers);
6547 AssertRCReturn(rc, rc);
6548 AssertLogRelMsgReturn(cMarcApers > 0 && cMarcApers <= RT_ELEMENTS(pThis->aMarcApers),
6549 ("MARC register count invalid %#x\n", cMarcApers), rcErr);
6550 for (uint8_t i = 0; i < cMarcApers; i++)
6551 {
6552 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Base.u64);
6553 AssertRCReturn(rc, rc);
6554
6555 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Reloc.u64);
6556 AssertRCReturn(rc, rc);
6557
6558 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Length.u64);
6559 AssertRCReturn(rc, rc);
6560 }
6561 Assert(!pThis->ExtFeat.n.u2MarcSup);
6562 }
6563
6564#if 0
6565 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg); /* read-only, done already (above). */
6566#endif
6567
6568 /* Command buffer head pointer register. */
6569 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufHeadPtr.u64);
6570 AssertRCReturn(rc, rc);
6571 {
6572 /*
6573 * IOMMU behavior is undefined when software writes a value outside the buffer length.
6574 * In our emulation, since we ignore the write entirely (see iommuAmdCmdBufHeadPtr_w)
6575 * we shouldn't see such values in the saved state.
6576 */
6577 uint32_t const offBuf = pThis->CmdBufHeadPtr.u64 & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
6578 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6579 Assert(cbBuf <= _512K);
6580 AssertLogRelMsgReturn(offBuf < cbBuf,
6581 ("Command buffer head pointer invalid %#x\n", pThis->CmdBufHeadPtr.u64), rcErr);
6582 }
6583
6584 /* Command buffer tail pointer register. */
6585 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufTailPtr.u64);
6586 AssertRCReturn(rc, rc);
6587 {
6588 uint32_t const offBuf = pThis->CmdBufTailPtr.u64 & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
6589 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6590 Assert(cbBuf <= _512K);
6591 AssertLogRelMsgReturn(offBuf < cbBuf,
6592 ("Command buffer tail pointer invalid %#x\n", pThis->CmdBufTailPtr.u64), rcErr);
6593 }
6594
6595 /* Event log head pointer register. */
6596 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogHeadPtr.u64);
6597 AssertRCReturn(rc, rc);
6598 {
6599 uint32_t const offBuf = pThis->EvtLogHeadPtr.u64 & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
6600 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6601 Assert(cbBuf <= _512K);
6602 AssertLogRelMsgReturn(offBuf < cbBuf,
6603 ("Event log head pointer invalid %#x\n", pThis->EvtLogHeadPtr.u64), rcErr);
6604 }
6605
6606 /* Event log tail pointer register. */
6607 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogTailPtr.u64);
6608 AssertRCReturn(rc, rc);
6609 {
6610 uint32_t const offBuf = pThis->EvtLogTailPtr.u64 & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
6611 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6612 Assert(cbBuf <= _512K);
6613 AssertLogRelMsgReturn(offBuf < cbBuf,
6614 ("Event log tail pointer invalid %#x\n", pThis->EvtLogTailPtr.u64), rcErr);
6615 }
6616
6617 /* Status register. */
6618 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Status.u64);
6619 AssertRCReturn(rc, rc);
6620 pThis->Status.u64 &= IOMMU_STATUS_VALID_MASK;
6621
6622 /* PPR log head pointer register. */
6623 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogHeadPtr.u64);
6624 AssertRCReturn(rc, rc);
6625 Assert(!pThis->ExtFeat.n.u1PprSup);
6626
6627 /* PPR log tail pointer register. */
6628 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogTailPtr.u64);
6629 AssertRCReturn(rc, rc);
6630 Assert(!pThis->ExtFeat.n.u1PprSup);
6631
6632 /* Guest Virtual-APIC log head pointer register. */
6633 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogHeadPtr.u64);
6634 AssertRCReturn(rc, rc);
6635 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6636
6637 /* Guest Virtual-APIC log tail pointer register. */
6638 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailPtr.u64);
6639 AssertRCReturn(rc, rc);
6640 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6641
6642 /* PPR log-B head pointer register. */
6643 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBHeadPtr.u64);
6644 AssertRCReturn(rc, rc);
6645 Assert(!pThis->ExtFeat.n.u1PprSup);
6646
6647 /* PPR log-B head pointer register. */
6648 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBTailPtr.u64);
6649 AssertRCReturn(rc, rc);
6650 Assert(!pThis->ExtFeat.n.u1PprSup);
6651
6652 /* Event log-B head pointer register. */
6653 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBHeadPtr.u64);
6654 AssertRCReturn(rc, rc);
6655 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6656
6657 /* Event log-B tail pointer register. */
6658 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBTailPtr.u64);
6659 AssertRCReturn(rc, rc);
6660 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6661
6662 /* PPR log auto response register. */
6663 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogAutoResp.u64);
6664 AssertRCReturn(rc, rc);
6665 Assert(!pThis->ExtFeat.n.u1PprAutoRespSup);
6666
6667 /* PPR log overflow early indicator register. */
6668 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogOverflowEarly.u64);
6669 AssertRCReturn(rc, rc);
6670 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6671
6672 /* PPR log-B overflow early indicator register. */
6673 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBOverflowEarly.u64);
6674 AssertRCReturn(rc, rc);
6675 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6676
6677 /* End marker. */
6678 {
6679 uint32_t uEndMarker;
6680 rc = pHlp->pfnSSMGetU32(pSSM, &uEndMarker);
6681 AssertLogRelMsgRCReturn(rc, ("Failed to read end marker. rc=%Rrc\n", rc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6682 AssertLogRelMsgReturn(uEndMarker == UINT32_MAX, ("End marker invalid (%#x expected %#x)\n", uEndMarker, UINT32_MAX),
6683 rcErr);
6684 }
6685
6686 return rc;
6687}
6688
6689
6690/**
6691 * @callback_method_impl{FNSSMDEVLOADDONE}
6692 */
6693static DECLCALLBACK(int) iommuAmdR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6694{
6695 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6696 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6697 RT_NOREF(pSSM);
6698 LogFlowFunc(("\n"));
6699
6700 /* Sanity. */
6701 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
6702 AssertPtrReturn(pThisR3, VERR_INVALID_POINTER);
6703
6704 int rc;
6705 IOMMU_LOCK(pDevIns, pThisR3);
6706
6707 /* Map MMIO regions if the IOMMU BAR is enabled. */
6708 if (pThis->IommuBar.n.u1Enable)
6709 rc = iommuAmdR3MmioSetup(pDevIns);
6710 else
6711 rc = VINF_SUCCESS;
6712
6713 /* Wake up the command thread if commands need processing. */
6714 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
6715
6716 IOMMU_UNLOCK(pDevIns, pThisR3);
6717
6718 LogRel(("%s: Restored: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
6719 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
6720 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
6721 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
6722 pThis->ExtFeat.u64));
6723 return rc;
6724}
6725
6726
6727/**
6728 * @interface_method_impl{PDMDEVREG,pfnReset}
6729 */
6730static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
6731{
6732 /*
6733 * Resets read-write portion of the IOMMU state.
6734 *
6735 * NOTE! State not initialized here is expected to be initialized during
6736 * device construction and remain read-only through the lifetime of the VM.
6737 */
6738 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6739 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6740 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6741 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6742 LogFlowFunc(("\n"));
6743
6744 IOMMU_LOCK(pDevIns, pThisR3);
6745
6746 RT_ZERO(pThis->aDevTabBaseAddrs);
6747
6748 pThis->CmdBufBaseAddr.u64 = 0;
6749 pThis->CmdBufBaseAddr.n.u4Len = 8;
6750
6751 pThis->EvtLogBaseAddr.u64 = 0;
6752 pThis->EvtLogBaseAddr.n.u4Len = 8;
6753
6754 pThis->Ctrl.u64 = 0;
6755 pThis->Ctrl.n.u1Coherent = 1;
6756 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
6757
6758 pThis->ExclRangeBaseAddr.u64 = 0;
6759 pThis->ExclRangeLimit.u64 = 0;
6760
6761 pThis->PprLogBaseAddr.u64 = 0;
6762 pThis->PprLogBaseAddr.n.u4Len = 8;
6763
6764 pThis->HwEvtHi.u64 = 0;
6765 pThis->HwEvtLo = 0;
6766 pThis->HwEvtStatus.u64 = 0;
6767
6768 pThis->GALogBaseAddr.u64 = 0;
6769 pThis->GALogBaseAddr.n.u4Len = 8;
6770 pThis->GALogTailAddr.u64 = 0;
6771
6772 pThis->PprLogBBaseAddr.u64 = 0;
6773 pThis->PprLogBBaseAddr.n.u4Len = 8;
6774
6775 pThis->EvtLogBBaseAddr.u64 = 0;
6776 pThis->EvtLogBBaseAddr.n.u4Len = 8;
6777
6778 pThis->PerfOptCtrl.u32 = 0;
6779
6780 pThis->XtGenIntrCtrl.u64 = 0;
6781 pThis->XtPprIntrCtrl.u64 = 0;
6782 pThis->XtGALogIntrCtrl.u64 = 0;
6783
6784 RT_ZERO(pThis->aMarcApers);
6785
6786 pThis->CmdBufHeadPtr.u64 = 0;
6787 pThis->CmdBufTailPtr.u64 = 0;
6788 pThis->EvtLogHeadPtr.u64 = 0;
6789 pThis->EvtLogTailPtr.u64 = 0;
6790
6791 pThis->Status.u64 = 0;
6792
6793 pThis->PprLogHeadPtr.u64 = 0;
6794 pThis->PprLogTailPtr.u64 = 0;
6795
6796 pThis->GALogHeadPtr.u64 = 0;
6797 pThis->GALogTailPtr.u64 = 0;
6798
6799 pThis->PprLogBHeadPtr.u64 = 0;
6800 pThis->PprLogBTailPtr.u64 = 0;
6801
6802 pThis->EvtLogBHeadPtr.u64 = 0;
6803 pThis->EvtLogBTailPtr.u64 = 0;
6804
6805 pThis->PprLogAutoResp.u64 = 0;
6806 pThis->PprLogOverflowEarly.u64 = 0;
6807 pThis->PprLogBOverflowEarly.u64 = 0;
6808
6809 pThis->IommuBar.u64 = 0;
6810 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
6811 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
6812
6813 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
6814
6815 IOMMU_UNLOCK(pDevIns, pThisR3);
6816
6817#ifdef IOMMU_WITH_DTE_CACHE
6818 iommuAmdDteCacheRemoveAll(pDevIns);
6819#endif
6820#ifdef IOMMU_WITH_IOTLBE_CACHE
6821 iommuAmdIotlbRemoveAll(pDevIns);
6822#endif
6823#ifdef IOMMU_WITH_IRTE_CACHE
6824 iommuAmdIrteCacheRemoveAll(pDevIns);
6825#endif
6826}
6827
6828
6829/**
6830 * @interface_method_impl{PDMDEVREG,pfnDestruct}
6831 */
6832static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
6833{
6834 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
6835 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6836 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6837 LogFlowFunc(("\n"));
6838
6839 IOMMU_LOCK(pDevIns, pThisR3);
6840
6841 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
6842 {
6843 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
6844 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
6845 }
6846
6847#ifdef IOMMU_WITH_IOTLBE_CACHE
6848 if (pThisR3->paIotlbes)
6849 {
6850 PDMDevHlpMMHeapFree(pDevIns, pThisR3->paIotlbes);
6851 pThisR3->paIotlbes = NULL;
6852 pThisR3->idxUnusedIotlbe = 0;
6853 }
6854#endif
6855
6856 IOMMU_UNLOCK(pDevIns, pThisR3);
6857 return VINF_SUCCESS;
6858}
6859
6860
6861/**
6862 * @interface_method_impl{PDMDEVREG,pfnConstruct}
6863 */
6864static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
6865{
6866 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6867
6868 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6869 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6870 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6871
6872 pThis->u32Magic = IOMMU_MAGIC;
6873 pThisR3->pDevInsR3 = pDevIns;
6874
6875 LogFlowFunc(("iInstance=%d\n", iInstance));
6876
6877 /*
6878 * Validate and read the configuration.
6879 */
6880 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "PCIAddress", "");
6881 int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "PCIAddress", &pThis->uPciAddress, NIL_PCIBDF);
6882 if (RT_FAILURE(rc))
6883 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query 32-bit integer \"PCIAddress\""));
6884 if (!PCIBDF_IS_VALID(pThis->uPciAddress))
6885 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed \"PCIAddress\" of the AMD IOMMU cannot be invalid"));
6886
6887 /*
6888 * Register the IOMMU with PDM.
6889 */
6890 PDMIOMMUREGR3 IommuReg;
6891 RT_ZERO(IommuReg);
6892 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
6893 IommuReg.pfnMemAccess = iommuAmdMemAccess;
6894 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
6895 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
6896 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
6897 rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
6898 if (RT_FAILURE(rc))
6899 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
6900 if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
6901 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6902 N_("IOMMU helper version mismatch; got %#x expected %#x"),
6903 pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
6904 if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
6905 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6906 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
6907 pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
6908 AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
6909 AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
6910 AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
6911 AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
6912
6913 /*
6914 * We will use PDM's critical section (via helpers) for the IOMMU device.
6915 */
6916 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
6917 AssertRCReturn(rc, rc);
6918
6919 /*
6920 * Initialize read-only PCI configuration space.
6921 */
6922 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6923 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6924
6925 /* Header. */
6926 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
6927 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
6928 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
6929 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
6930 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
6931 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
6932 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
6933 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
6934 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
6935 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
6936 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
6937 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
6938 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
6939 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
6940
6941 /* Capability Header. */
6942 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
6943 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
6944 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
6945 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Next capability offset */
6946 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
6947 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
6948 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
6949 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
6950 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
6951 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
6952 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
6953
6954 /* Base Address Register. */
6955 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
6956 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
6957
6958 /* IOMMU Range Register. */
6959 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
6960
6961 /* Misc. Information Register. */
6962 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
6963 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
6964 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
6965 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
6966 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
6967 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
6968 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
6969 uint32_t const uMiscInfoReg1 = 0;
6970 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
6971 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
6972
6973 /* MSI Capability Header register. */
6974 PDMMSIREG MsiReg;
6975 RT_ZERO(MsiReg);
6976 MsiReg.cMsiVectors = 1;
6977 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
6978 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
6979 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support". */
6980
6981 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
6982#if 0
6983 /* MSI Address Lo. */
6984 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
6985 /* MSI Address Hi. */
6986 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
6987 /* MSI Data. */
6988 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
6989#endif
6990
6991#if 0
6992 /** @todo IOMMU: I don't know if we need to support this, enable later if
6993 * required. */
6994 /* MSI Mapping Capability Header register. */
6995 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
6996 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
6997 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
6998 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
6999 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
7000 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
7001 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
7002#endif
7003
7004 /*
7005 * Register the PCI function with PDM.
7006 */
7007 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
7008 AssertLogRelRCReturn(rc, rc);
7009
7010 /*
7011 * Register MSI support for the PCI device.
7012 * This must be done -after- registering it as a PCI device!
7013 */
7014 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
7015 AssertRCReturn(rc, rc);
7016
7017 /*
7018 * Intercept PCI config. space accesses.
7019 */
7020 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
7021 AssertLogRelRCReturn(rc, rc);
7022
7023 /*
7024 * Create the MMIO region.
7025 * Mapping of the region is done when software configures it via PCI config space.
7026 */
7027 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
7028 NULL /* pvUser */,
7029 IOMMMIO_FLAGS_READ_DWORD_QWORD
7030 | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING
7031 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
7032 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
7033 "AMD-IOMMU", &pThis->hMmio);
7034 AssertLogRelRCReturn(rc, rc);
7035
7036 /*
7037 * Register saved state handlers.
7038 */
7039 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL /* pszBefore */,
7040 NULL /* pfnLivePrep */, NULL /* pfnLiveExec */, NULL /* pfnLiveVote */,
7041 NULL /* pfnSavePrep */, iommuAmdR3SaveExec, NULL /* pfnSaveDone */,
7042 NULL /* pfnLoadPrep */, iommuAmdR3LoadExec, iommuAmdR3LoadDone);
7043 AssertLogRelRCReturn(rc, rc);
7044
7045 /*
7046 * Register debugger info items.
7047 */
7048 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
7049 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device (from memory). Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
7050 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display I/O device tables with translation enabled.", iommuAmdR3DbgInfoDevTabs);
7051#ifdef IOMMU_WITH_IOTLBE_CACHE
7052 PDMDevHlpDBGFInfoRegister(pDevIns, "iommutlb", "Display IOTLBs for a domain. Arguments: DomainID.", iommuAmdR3DbgInfoIotlb);
7053#endif
7054#ifdef IOMMU_WITH_DTE_CACHE
7055 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudtecache", "Display the DTE cache.", iommuAmdR3DbgInfoDteCache);
7056#endif
7057#ifdef IOMMU_WITH_IRTE_CACHE
7058 PDMDevHlpDBGFInfoRegister(pDevIns, "iommuirtecache", "Display the IRTE cache.", iommuAmdR3DbgInfoIrteCache);
7059#endif
7060
7061# ifdef VBOX_WITH_STATISTICS
7062 /*
7063 * Statistics.
7064 */
7065 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
7066 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
7067
7068 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
7069 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
7070
7071 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
7072 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
7073
7074 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
7075 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
7076
7077 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
7078 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
7079
7080 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
7081 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
7082
7083 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
7084 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
7085
7086 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
7087 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
7088 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
7089 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
7090 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
7091 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
7092 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
7093 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
7094 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
7095
7096
7097 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeCached, STAMTYPE_COUNTER, "IOTLB/Cached", STAMUNIT_OCCURENCES, "Number of IOTLB entries in the cache.");
7098 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeLazyEvictReuse, STAMTYPE_COUNTER, "IOTLB/LazyEvictReuse", STAMUNIT_OCCURENCES, "Number of IOTLB entries reused after lazy eviction.");
7099
7100 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfDteLookup, STAMTYPE_PROFILE, "Profile/DteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling DTE lookup.");
7101 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIotlbeLookup, STAMTYPE_PROFILE, "Profile/IotlbeLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IOTLBE lookup.");
7102
7103 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteLookup, STAMTYPE_PROFILE, "Profile/IrteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE lookup.");
7104 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteCacheLookup, STAMTYPE_PROFILE, "Profile/IrteCacheLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE cache lookup.");
7105
7106 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHit, STAMTYPE_COUNTER, "MemAccess/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
7107 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheMiss, STAMTYPE_COUNTER, "MemAccess/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
7108 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHitFull, STAMTYPE_COUNTER, "MemAccess/CacheHitFull", STAMUNIT_OCCURENCES, "Number of accesses that was entirely in the cache.");
7109 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheNonContig, STAMTYPE_COUNTER, "MemAccess/CacheNonContig", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in non-contiguous translated regions.");
7110 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCachePermDenied, STAMTYPE_COUNTER, "MemAccess/CacheAddrDenied", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in denied permissions.");
7111 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDteNonContig, STAMTYPE_COUNTER, "MemAccess/DteNonContig", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in non-contiguous translated regions.");
7112 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDtePermDenied, STAMTYPE_COUNTER, "MemAccess/DtePermDenied", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in denied permissions.");
7113
7114 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheHit, STAMTYPE_COUNTER, "Interrupt/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
7115 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheMiss, STAMTYPE_COUNTER, "Interrupt/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
7116
7117 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatNonStdPageSize, STAMTYPE_COUNTER, "MemAccess/NonStdPageSize", STAMUNIT_OCCURENCES, "Number of non-standard page size translations.");
7118 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIopfs, STAMTYPE_COUNTER, "MemAccess/IOPFs", STAMUNIT_OCCURENCES, "Number of I/O page faults.");
7119# endif
7120
7121 /*
7122 * Create the command thread and its event semaphore.
7123 */
7124 char szDevIommu[64];
7125 RT_ZERO(szDevIommu);
7126 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
7127 rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
7128 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
7129 AssertLogRelRCReturn(rc, rc);
7130
7131 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
7132 AssertLogRelRCReturn(rc, rc);
7133
7134#ifdef IOMMU_WITH_DTE_CACHE
7135 /*
7136 * Initialize the critsect of the cache.
7137 */
7138 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSectCache, RT_SRC_POS, "IOMMUCache-#%u", pDevIns->iInstance);
7139 AssertLogRelRCReturn(rc, rc);
7140
7141 /* Several places in this code relies on this basic assumption - assert it! */
7142 AssertCompile(RT_ELEMENTS(pThis->aDeviceIds) == RT_ELEMENTS(pThis->aDteCache));
7143#endif
7144
7145#ifdef IOMMU_WITH_IOTLBE_CACHE
7146 /*
7147 * Allocate IOTLB entries.
7148 * This is allocated upfront since we expect a relatively small number of entries,
7149 * is more cache-line efficient and easier to track least recently used entries for
7150 * eviction when the cache is full. This also avoids unpredictable behavior during
7151 * the lifetime of the VM if the hyperheap gets full.
7152 */
7153 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
7154 pThisR3->paIotlbes = (PIOTLBE)PDMDevHlpMMHeapAllocZ(pDevIns, cbIotlbes);
7155 if (!pThisR3->paIotlbes)
7156 return PDMDevHlpVMSetError(pDevIns, VERR_NO_MEMORY, RT_SRC_POS,
7157 N_("Failed to allocate %zu bytes from the hyperheap for the IOTLB cache."), cbIotlbes);
7158 RTListInit(&pThisR3->LstLruIotlbe);
7159 LogRel(("%s: Allocated %zu bytes from the hyperheap for the IOTLB cache\n", IOMMU_LOG_PFX, cbIotlbes));
7160#endif
7161
7162 /*
7163 * Initialize read-only registers.
7164 * NOTE! Fields here must match their corresponding field in the ACPI tables.
7165 */
7166 /* Don't remove the commented lines below as it lets us see all features at a glance. */
7167 pThis->ExtFeat.u64 = 0;
7168 //pThis->ExtFeat.n.u1PrefetchSup = 0;
7169 //pThis->ExtFeat.n.u1PprSup = 0;
7170 //pThis->ExtFeat.n.u1X2ApicSup = 0;
7171 //pThis->ExtFeat.n.u1NoExecuteSup = 0;
7172 //pThis->ExtFeat.n.u1GstTranslateSup = 0;
7173 pThis->ExtFeat.n.u1InvAllSup = 1;
7174 //pThis->ExtFeat.n.u1GstVirtApicSup = 0;
7175 pThis->ExtFeat.n.u1HwErrorSup = 1;
7176 //pThis->ExtFeat.n.u1PerfCounterSup = 0;
7177 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
7178 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
7179 //pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
7180 //pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
7181 //pThis->ExtFeat.n.u2SmiFilterSup = 0;
7182 //pThis->ExtFeat.n.u3SmiFilterCount = 0;
7183 //pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
7184 //pThis->ExtFeat.n.u2DualPprLogSup = 0;
7185 //pThis->ExtFeat.n.u2DualEvtLogSup = 0;
7186 //pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
7187 //pThis->ExtFeat.n.u1UserSupervisorSup = 0;
7188 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
7189 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
7190 //pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
7191 //pThis->ExtFeat.n.u1PprAutoRespSup = 0;
7192 //pThis->ExtFeat.n.u2MarcSup = 0;
7193 //pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
7194 //pThis->ExtFeat.n.u1PerfOptSup = 0;
7195 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
7196 //pThis->ExtFeat.n.u1GstIoSup = 0;
7197 //pThis->ExtFeat.n.u1HostAccessSup = 0;
7198 //pThis->ExtFeat.n.u1EnhancedPprSup = 0;
7199 //pThis->ExtFeat.n.u1AttrForwardSup = 0;
7200 //pThis->ExtFeat.n.u1HostDirtySup = 0;
7201 //pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
7202 //pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
7203 //pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
7204
7205 pThis->DevSpecificFeat.u64 = 0;
7206 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
7207 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
7208
7209 pThis->DevSpecificCtrl.u64 = 0;
7210 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
7211 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
7212
7213 pThis->DevSpecificStatus.u64 = 0;
7214 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
7215 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
7216
7217 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
7218
7219 pThis->RsvdReg = 0;
7220
7221 /*
7222 * Initialize parts of the IOMMU state as it would during reset.
7223 * Also initializes non-zero initial values like IRTE cache keys.
7224 * Must be called -after- initializing PCI config. space registers.
7225 */
7226 iommuAmdR3Reset(pDevIns);
7227
7228 LogRel(("%s: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
7229 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
7230 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
7231 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
7232 pThis->ExtFeat.u64));
7233 return VINF_SUCCESS;
7234}
7235
7236#else
7237
7238/**
7239 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
7240 */
7241static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
7242{
7243 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7244 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
7245 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
7246 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
7247
7248 /* We will use PDM's critical section (via helpers) for the IOMMU device. */
7249 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7250 AssertRCReturn(rc, rc);
7251
7252 /* Set up the MMIO RZ handlers. */
7253 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
7254 AssertRCReturn(rc, rc);
7255
7256 /* Set up the IOMMU RZ callbacks. */
7257 PDMIOMMUREGCC IommuReg;
7258 RT_ZERO(IommuReg);
7259 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
7260 IommuReg.idxIommu = pThis->idxIommu;
7261 IommuReg.pfnMemAccess = iommuAmdMemAccess;
7262 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
7263 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
7264 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
7265 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
7266 AssertRCReturn(rc, rc);
7267 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
7268 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
7269 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
7270 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
7271 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
7272 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
7273 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
7274 return VINF_SUCCESS;
7275}
7276#endif
7277
7278
7279/**
7280 * The device registration structure.
7281 */
7282const PDMDEVREG g_DeviceIommuAmd =
7283{
7284 /* .u32Version = */ PDM_DEVREG_VERSION,
7285 /* .uReserved0 = */ 0,
7286 /* .szName = */ "iommu-amd",
7287 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
7288 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
7289 /* .cMaxInstances = */ 1,
7290 /* .uSharedVersion = */ 42,
7291 /* .cbInstanceShared = */ sizeof(IOMMU),
7292 /* .cbInstanceCC = */ sizeof(IOMMUCC),
7293 /* .cbInstanceRC = */ sizeof(IOMMURC),
7294 /* .cMaxPciDevices = */ 1,
7295 /* .cMaxMsixVectors = */ 0,
7296 /* .pszDescription = */ "IOMMU (AMD)",
7297#if defined(IN_RING3)
7298 /* .pszRCMod = */ "VBoxDDRC.rc",
7299 /* .pszR0Mod = */ "VBoxDDR0.r0",
7300 /* .pfnConstruct = */ iommuAmdR3Construct,
7301 /* .pfnDestruct = */ iommuAmdR3Destruct,
7302 /* .pfnRelocate = */ NULL,
7303 /* .pfnMemSetup = */ NULL,
7304 /* .pfnPowerOn = */ NULL,
7305 /* .pfnReset = */ iommuAmdR3Reset,
7306 /* .pfnSuspend = */ NULL,
7307 /* .pfnResume = */ NULL,
7308 /* .pfnAttach = */ NULL,
7309 /* .pfnDetach = */ NULL,
7310 /* .pfnQueryInterface = */ NULL,
7311 /* .pfnInitComplete = */ NULL,
7312 /* .pfnPowerOff = */ NULL,
7313 /* .pfnSoftReset = */ NULL,
7314 /* .pfnReserved0 = */ NULL,
7315 /* .pfnReserved1 = */ NULL,
7316 /* .pfnReserved2 = */ NULL,
7317 /* .pfnReserved3 = */ NULL,
7318 /* .pfnReserved4 = */ NULL,
7319 /* .pfnReserved5 = */ NULL,
7320 /* .pfnReserved6 = */ NULL,
7321 /* .pfnReserved7 = */ NULL,
7322#elif defined(IN_RING0)
7323 /* .pfnEarlyConstruct = */ NULL,
7324 /* .pfnConstruct = */ iommuAmdRZConstruct,
7325 /* .pfnDestruct = */ NULL,
7326 /* .pfnFinalDestruct = */ NULL,
7327 /* .pfnRequest = */ NULL,
7328 /* .pfnReserved0 = */ NULL,
7329 /* .pfnReserved1 = */ NULL,
7330 /* .pfnReserved2 = */ NULL,
7331 /* .pfnReserved3 = */ NULL,
7332 /* .pfnReserved4 = */ NULL,
7333 /* .pfnReserved5 = */ NULL,
7334 /* .pfnReserved6 = */ NULL,
7335 /* .pfnReserved7 = */ NULL,
7336#elif defined(IN_RC)
7337 /* .pfnConstruct = */ iommuAmdRZConstruct,
7338 /* .pfnReserved0 = */ NULL,
7339 /* .pfnReserved1 = */ NULL,
7340 /* .pfnReserved2 = */ NULL,
7341 /* .pfnReserved3 = */ NULL,
7342 /* .pfnReserved4 = */ NULL,
7343 /* .pfnReserved5 = */ NULL,
7344 /* .pfnReserved6 = */ NULL,
7345 /* .pfnReserved7 = */ NULL,
7346#else
7347# error "Not in IN_RING3, IN_RING0 or IN_RC!"
7348#endif
7349 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
7350};
7351
7352#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
7353
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