VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 90447

Last change on this file since 90447 was 90445, checked in by vboxsync, 3 years ago

Dev*: Check PDMDevHlpCritSectEnter return status better. bugref:6695
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1/* $Id: DevIommuAmd.cpp 90445 2021-07-30 22:18:24Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26
27#include <iprt/x86.h>
28#include <iprt/string.h>
29#include <iprt/avl.h>
30#ifdef IN_RING3
31# include <iprt/mem.h>
32#endif
33
34#include "VBoxDD.h"
35#include "DevIommuAmd.h"
36
37
38/*********************************************************************************************************************************
39* Defined Constants And Macros *
40*********************************************************************************************************************************/
41/** Release log prefix string. */
42#define IOMMU_LOG_PFX "AMD-IOMMU"
43/** The current saved state version. */
44#define IOMMU_SAVED_STATE_VERSION 1
45/** The IOMMU device instance magic. */
46#define IOMMU_MAGIC 0x10acce55
47
48/** Enable the IOTLBE cache only in ring-3 for now, see @bugref{9654#c95}. */
49#ifdef IN_RING3
50//# define IOMMU_WITH_IOTLBE_CACHE /* Disabled for now, see @bugref{9654#c107}. */
51#endif
52/** Enable the interrupt cache. */
53#define IOMMU_WITH_IRTE_CACHE
54
55/* The DTE cache is mandatory for the IOTLB or interrupt cache to work. */
56#if defined(IOMMU_WITH_IOTLBE_CACHE) || defined(IOMMU_WITH_IRTE_CACHE)
57# define IOMMU_WITH_DTE_CACHE
58/** The maximum number of device IDs in the cache. */
59# define IOMMU_DEV_CACHE_COUNT 16
60/** An empty device ID. */
61# define IOMMU_DTE_CACHE_KEY_NIL 0
62#endif
63
64#ifdef IOMMU_WITH_IRTE_CACHE
65/** The maximum number of IRTE cache entries. */
66# define IOMMU_IRTE_CACHE_COUNT 32
67/** A NIL IRTE cache entry key. */
68# define IOMMU_IRTE_CACHE_KEY_NIL (~(uint32_t)0U)
69/** Gets the device ID from an IRTE cache entry key. */
70#define IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(a_Key) RT_HIWORD(a_Key)
71/** Gets the IOVA from the IOTLB entry key. */
72# define IOMMU_IRTE_CACHE_KEY_GET_OFF(a_Key) RT_LOWORD(a_Key)
73/** Makes an IRTE cache entry key.
74 *
75 * Bits 31:16 is the device ID (Bus, Device, Function).
76 * Bits 15:0 is the the offset into the IRTE table.
77 */
78# define IOMMU_IRTE_CACHE_KEY_MAKE(a_DevId, a_off) RT_MAKE_U32(a_off, a_DevId)
79#endif /* IOMMU_WITH_IRTE_CACHE */
80
81#ifdef IOMMU_WITH_IOTLBE_CACHE
82/** The maximum number of IOTLB entries. */
83# define IOMMU_IOTLBE_MAX 96
84/** The mask of bits covering the domain ID in the IOTLBE key. */
85# define IOMMU_IOTLB_DOMAIN_ID_MASK UINT64_C(0xffffff0000000000)
86/** The mask of bits covering the IOVA in the IOTLBE key. */
87# define IOMMU_IOTLB_IOVA_MASK (~IOMMU_IOTLB_DOMAIN_ID_MASK)
88/** The number of bits to shift for the domain ID of the IOTLBE key. */
89# define IOMMU_IOTLB_DOMAIN_ID_SHIFT 40
90/** A NIL IOTLB key. */
91# define IOMMU_IOTLB_KEY_NIL UINT64_C(0)
92/** Gets the domain ID from an IOTLB entry key. */
93# define IOMMU_IOTLB_KEY_GET_DOMAIN_ID(a_Key) ((a_Key) >> IOMMU_IOTLB_DOMAIN_ID_SHIFT)
94/** Gets the IOVA from the IOTLB entry key. */
95# define IOMMU_IOTLB_KEY_GET_IOVA(a_Key) (((a_Key) & IOMMU_IOTLB_IOVA_MASK) << X86_PAGE_4K_SHIFT)
96/** Makes an IOTLB entry key.
97 *
98 * Address bits 63:52 of the IOVA are zero extended, so top 12 bits are free.
99 * Address bits 11:0 of the IOVA are offset into the minimum page size of 4K,
100 * so bottom 12 bits are free.
101 *
102 * Thus we use the top 24 bits of key to hold bits 15:0 of the domain ID.
103 * We use the bottom 40 bits of the key to hold bits 51:12 of the IOVA.
104 */
105# define IOMMU_IOTLB_KEY_MAKE(a_DomainId, a_uIova) ( ((uint64_t)(a_DomainId) << IOMMU_IOTLB_DOMAIN_ID_SHIFT) \
106 | (((a_uIova) >> X86_PAGE_4K_SHIFT) & IOMMU_IOTLB_IOVA_MASK))
107#endif /* IOMMU_WITH_IOTLBE_CACHE */
108
109#ifdef IOMMU_WITH_DTE_CACHE
110/** @name IOMMU_DTE_CACHE_F_XXX: DTE cache flags.
111 *
112 * Some of these flags are "basic" i.e. they correspond directly to their bits in
113 * the DTE. The rest of the flags are based on checks or operations on several DTE
114 * bits.
115 *
116 * The basic flags are:
117 * - VALID (DTE.V)
118 * - IO_PERM_READ (DTE.IR)
119 * - IO_PERM_WRITE (DTE.IW)
120 * - IO_PERM_RSVD (bit following DTW.IW reserved for future & to keep
121 * masking consistent)
122 * - SUPPRESS_ALL_IOPF (DTE.SA)
123 * - SUPPRESS_IOPF (DTE.SE)
124 * - INTR_MAP_VALID (DTE.IV)
125 * - IGNORE_UNMAPPED_INTR (DTE.IG)
126 *
127 * @see iommuAmdGetBasicDevFlags()
128 * @{ */
129/** The DTE is present. */
130# define IOMMU_DTE_CACHE_F_PRESENT RT_BIT(0)
131/** The DTE is valid. */
132# define IOMMU_DTE_CACHE_F_VALID RT_BIT(1)
133/** The DTE permissions apply for address translations. */
134# define IOMMU_DTE_CACHE_F_IO_PERM RT_BIT(2)
135/** DTE permission - I/O read allowed. */
136# define IOMMU_DTE_CACHE_F_IO_PERM_READ RT_BIT(3)
137/** DTE permission - I/O write allowed. */
138# define IOMMU_DTE_CACHE_F_IO_PERM_WRITE RT_BIT(4)
139/** DTE permission - reserved. */
140# define IOMMU_DTE_CACHE_F_IO_PERM_RSVD RT_BIT(5)
141/** Address translation required. */
142# define IOMMU_DTE_CACHE_F_ADDR_TRANSLATE RT_BIT(6)
143/** Suppress all I/O page faults. */
144# define IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF RT_BIT(7)
145/** Suppress I/O page faults. */
146# define IOMMU_DTE_CACHE_F_SUPPRESS_IOPF RT_BIT(8)
147/** Interrupt map valid. */
148# define IOMMU_DTE_CACHE_F_INTR_MAP_VALID RT_BIT(9)
149/** Ignore unmapped interrupts. */
150# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR RT_BIT(10)
151/** An I/O page fault has been raised for this device. */
152# define IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED RT_BIT(11)
153/** Fixed and arbitrary interrupt control: Target Abort. */
154# define IOMMU_DTE_CACHE_F_INTR_CTRL_TARGET_ABORT RT_BIT(12)
155/** Fixed and arbitrary interrupt control: Forward unmapped. */
156# define IOMMU_DTE_CACHE_F_INTR_CTRL_FWD_UNMAPPED RT_BIT(13)
157/** Fixed and arbitrary interrupt control: Remapped. */
158# define IOMMU_DTE_CACHE_F_INTR_CTRL_REMAPPED RT_BIT(14)
159/** Fixed and arbitrary interrupt control: Reserved. */
160# define IOMMU_DTE_CACHE_F_INTR_CTRL_RSVD RT_BIT(15)
161/** @} */
162
163/** The number of bits to shift I/O device flags for DTE permissions. */
164# define IOMMU_DTE_CACHE_F_IO_PERM_SHIFT 3
165/** The mask of DTE permissions in I/O device flags. */
166# define IOMMU_DTE_CACHE_F_IO_PERM_MASK 0x3
167/** The number of bits to shift I/O device flags for interrupt control bits. */
168# define IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT 12
169/** The mask of interrupt control bits in I/O device flags. */
170# define IOMMU_DTE_CACHE_F_INTR_CTRL_MASK 0x3
171/** The number of bits to shift for ignore-unmapped interrupts bit. */
172# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR_SHIFT 10
173
174/** Acquires the cache lock. */
175# ifdef IN_RING3
176# define IOMMU_CACHE_LOCK(a_pDevIns, a_pThis) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VERR_IGNORED)
177# else
178# define IOMMU_CACHE_LOCK(a_pDevIns, a_pThis) \
179 do { \
180 int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VINF_SUCCESS); \
181 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV((a_pDevIns), &(a_pThis)->CritSectCache, rcLock); \
182 } while (0)
183# endif
184
185/** Releases the cache lock. */
186# define IOMMU_CACHE_UNLOCK(a_pDevIns, a_pThis) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSectCache)
187#endif /* IOMMU_WITH_DTE_CACHE */
188
189/** Acquires the PDM lock (returns a_rcBusy on contention). */
190#define IOMMU_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
191 do { \
192 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)); \
193 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
194 { /* likely */ } \
195 else \
196 return rcLock; \
197 } while (0)
198
199/** Acquires the PDM lock (can fail under extraordinary circumstance in in ring-0). */
200#ifdef IN_RING3
201# define IOMMU_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED)
202#else
203# define IOMMU_LOCK(a_pDevIns, a_pThisCC) \
204 do { \
205 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
206 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV((a_pDevIns), NULL, rcLock); \
207 } while (0)
208#endif
209
210/** Checks if the current thread owns the PDM lock. */
211# define IOMMU_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
212 do \
213 { \
214 Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner((a_pDevIns))); \
215 NOREF(a_pThisCC); \
216 } while (0)
217
218/** Releases the PDM lock. */
219# define IOMMU_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock((a_pDevIns))
220
221/** Gets the maximum valid IOVA for the given I/O page-table level. */
222#define IOMMU_GET_MAX_VALID_IOVA(a_Level) ((X86_PAGE_4K_SIZE << ((a_Level) * 9)) - 1)
223
224
225/*********************************************************************************************************************************
226* Structures and Typedefs *
227*********************************************************************************************************************************/
228/**
229 * IOMMU operation (transaction).
230 */
231typedef enum IOMMUOP
232{
233 /** Address translation request. */
234 IOMMUOP_TRANSLATE_REQ = 0,
235 /** Memory read request. */
236 IOMMUOP_MEM_READ,
237 /** Memory write request. */
238 IOMMUOP_MEM_WRITE,
239 /** Interrupt request. */
240 IOMMUOP_INTR_REQ,
241 /** Command. */
242 IOMMUOP_CMD
243} IOMMUOP;
244/** Pointer to a IOMMU operation. */
245typedef IOMMUOP *PIOMMUOP;
246
247/**
248 * I/O page lookup.
249 */
250typedef struct IOPAGELOOKUP
251{
252 /** The translated system physical address. */
253 RTGCPHYS GCPhysSpa;
254 /** The number of offset bits in the system physical address. */
255 uint8_t cShift;
256 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
257 uint8_t fPerm;
258} IOPAGELOOKUP;
259/** Pointer to an I/O page lookup. */
260typedef IOPAGELOOKUP *PIOPAGELOOKUP;
261/** Pointer to a const I/O page lookup. */
262typedef IOPAGELOOKUP const *PCIOPAGELOOKUP;
263
264/**
265 * I/O address range.
266 */
267typedef struct IOADDRRANGE
268{
269 /** The address (virtual or physical). */
270 uint64_t uAddr;
271 /** The size of the access in bytes. */
272 size_t cb;
273 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
274 uint8_t fPerm;
275} IOADDRRANGE;
276/** Pointer to an I/O address range. */
277typedef IOADDRRANGE *PIOADDRRANGE;
278/** Pointer to a const I/O address range. */
279typedef IOADDRRANGE const *PCIOADDRRANGE;
280
281#ifdef IOMMU_WITH_DTE_CACHE
282/**
283 * Device Table Entry Cache.
284 */
285typedef struct DTECACHE
286{
287 /** This device's flags, see IOMMU_DTE_CACHE_F_XXX. */
288 uint16_t fFlags;
289 /** The domain ID assigned for this device by software. */
290 uint16_t idDomain;
291} DTECACHE;
292/** Pointer to an I/O device struct. */
293typedef DTECACHE *PDTECACHE;
294/** Pointer to a const I/O device struct. */
295typedef DTECACHE *PCDTECACHE;
296AssertCompileSize(DTECACHE, 4);
297#endif /* IOMMU_WITH_DTE_CACHE */
298
299#ifdef IOMMU_WITH_IOTLBE_CACHE
300/**
301 * I/O TLB Entry.
302 * Keep this as small and aligned as possible.
303 */
304typedef struct IOTLBE
305{
306 /** The AVL tree node. */
307 AVLU64NODECORE Core;
308 /** The least recently used (LRU) list node. */
309 RTLISTNODE NdLru;
310 /** The I/O page lookup results of the translation. */
311 IOPAGELOOKUP PageLookup;
312 /** Whether the entry needs to be evicted from the cache. */
313 bool fEvictPending;
314} IOTLBE;
315/** Pointer to an IOMMU I/O TLB entry struct. */
316typedef IOTLBE *PIOTLBE;
317/** Pointer to a const IOMMU I/O TLB entry struct. */
318typedef IOTLBE const *PCIOTLBE;
319AssertCompileSizeAlignment(IOTLBE, 8);
320AssertCompileMemberOffset(IOTLBE, Core, 0);
321#endif /* IOMMU_WITH_IOTLBE_CACHE */
322
323#ifdef IOMMU_WITH_IRTE_CACHE
324/**
325 * Interrupt Remap Table Entry Cache.
326 */
327typedef struct IRTECACHE
328{
329 /** The key, see IOMMU_IRTE_CACHE_KEY_MAKE. */
330 uint32_t uKey;
331 /** The IRTE. */
332 IRTE_T Irte;
333} IRTECACHE;
334/** Pointer to an IRTE cache struct. */
335typedef IRTECACHE *PIRTECACHE;
336/** Pointer to a const IRTE cache struct. */
337typedef IRTECACHE const *PCIRTECACHE;
338AssertCompileSizeAlignment(IRTECACHE, 4);
339#endif /* IOMMU_WITH_IRTE_CACHE */
340
341/**
342 * The shared IOMMU device state.
343 */
344typedef struct IOMMU
345{
346 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
347 uint32_t idxIommu;
348 /** IOMMU magic. */
349 uint32_t u32Magic;
350
351 /** The MMIO handle. */
352 IOMMMIOHANDLE hMmio;
353 /** The event semaphore the command thread waits on. */
354 SUPSEMEVENT hEvtCmdThread;
355 /** Whether the command thread has been signaled for wake up. */
356 bool volatile fCmdThreadSignaled;
357 /** Padding. */
358 bool afPadding0[3];
359 /** The IOMMU PCI address. */
360 PCIBDF uPciAddress;
361
362#ifdef IOMMU_WITH_DTE_CACHE
363 /** The critsect that protects the cache from concurrent access. */
364 PDMCRITSECT CritSectCache;
365 /** Array of device IDs. */
366 uint16_t aDeviceIds[IOMMU_DEV_CACHE_COUNT];
367 /** Array of DTE cache entries. */
368 DTECACHE aDteCache[IOMMU_DEV_CACHE_COUNT];
369#endif
370#ifdef IOMMU_WITH_IRTE_CACHE
371 /** Array of IRTE cache entries. */
372 IRTECACHE aIrteCache[IOMMU_IRTE_CACHE_COUNT];
373#endif
374
375 /** @name PCI: Base capability block registers.
376 * @{ */
377 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
378 /** @} */
379
380 /** @name MMIO: Control and status registers.
381 * @{ */
382 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
383 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
384 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
385 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
386 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
387 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
388 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
389 /** @} */
390
391 /** @name MMIO: Peripheral Page Request (PPR) Log registers.
392 * @{ */
393 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
394 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
395 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
396 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
397 /** @} */
398
399 /** @todo IOMMU: SMI filter. */
400
401 /** @name MMIO: Guest Virtual-APIC Log registers.
402 * @{ */
403 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
404 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
405 /** @} */
406
407 /** @name MMIO: Alternate PPR and Event Log registers.
408 * @{ */
409 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
410 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
411 /** @} */
412
413 /** @name MMIO: Device-specific feature registers.
414 * @{ */
415 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
416 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
417 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
418 /** @} */
419
420 /** @name MMIO: MSI Capability Block registers.
421 * @{ */
422 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
423 /** @} */
424
425 /** @name MMIO: Performance Optimization Control registers.
426 * @{ */
427 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
428 /** @} */
429
430 /** @name MMIO: x2APIC Control registers.
431 * @{ */
432 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
433 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
434 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
435 /** @} */
436
437 /** @name MMIO: Memory Address Routing & Control (MARC) registers.
438 * @{ */
439 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
440 /** @} */
441
442 /** @name MMIO: Reserved register.
443 * @{ */
444 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
445 /** @} */
446
447 /** @name MMIO: Command and Event Log pointer registers.
448 * @{ */
449 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
450 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
451 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
452 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
453 /** @} */
454
455 /** @name MMIO: Command and Event Status register.
456 * @{ */
457 IOMMU_STATUS_T Status; /**< IOMMU status register. */
458 /** @} */
459
460 /** @name MMIO: PPR Log Head and Tail pointer registers.
461 * @{ */
462 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
463 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
464 /** @} */
465
466 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
467 * @{ */
468 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
469 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
470 /** @} */
471
472 /** @name MMIO: PPR Log B Head and Tail pointer registers.
473 * @{ */
474 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
475 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
476 /** @} */
477
478 /** @name MMIO: Event Log B Head and Tail pointer registers.
479 * @{ */
480 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
481 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
482 /** @} */
483
484 /** @name MMIO: PPR Log Overflow protection registers.
485 * @{ */
486 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
487 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
488 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
489 /** @} */
490
491 /** @todo IOMMU: IOMMU Event counter registers. */
492
493#ifdef VBOX_WITH_STATISTICS
494 /** @name IOMMU: Stat counters.
495 * @{ */
496 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
497 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
498 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
499 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
500
501 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
502 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
503
504 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
505 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
506 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
507 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
508
509 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
510 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
511 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
512 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
513
514 STAMCOUNTER StatCmd; /**< Number of commands processed in total. */
515 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
516 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
517 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
518 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
519 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
520 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
521 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
522 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
523
524 STAMCOUNTER StatIotlbeCached; /**< Number of IOTLB entries in the cache. */
525 STAMCOUNTER StatIotlbeLazyEvictReuse; /**< Number of IOTLB entries re-used after lazy eviction. */
526
527 STAMPROFILEADV StatProfDteLookup; /**< Profiling of I/O page walk (from memory). */
528 STAMPROFILEADV StatProfIotlbeLookup; /**< Profiling of IOTLB entry lookup (from cache). */
529
530 STAMPROFILEADV StatProfIrteLookup; /**< Profiling of IRTE entry lookup (from memory). */
531 STAMPROFILEADV StatProfIrteCacheLookup; /**< Profiling of IRTE entry lookup (from cache). */
532
533 STAMCOUNTER StatAccessCacheHit; /**< Number of IOTLB cache hits. */
534 STAMCOUNTER StatAccessCacheHitFull; /**< Number of accesses that were fully looked up from the cache. */
535 STAMCOUNTER StatAccessCacheMiss; /**< Number of cache misses (resulting in DTE lookups). */
536 STAMCOUNTER StatAccessCacheNonContig; /**< Number of cache accesses resulting in non-contiguous access. */
537 STAMCOUNTER StatAccessCachePermDenied; /**< Number of cache accesses resulting in insufficient permissions. */
538 STAMCOUNTER StatAccessDteNonContig; /**< Number of DTE accesses resulting in non-contiguous access. */
539 STAMCOUNTER StatAccessDtePermDenied; /**< Number of DTE accesses resulting in insufficient permissions. */
540
541 STAMCOUNTER StatIntrCacheHit; /**< Number of interrupt cache hits. */
542 STAMCOUNTER StatIntrCacheMiss; /**< Number of interrupt cache misses. */
543
544 STAMCOUNTER StatNonStdPageSize; /**< Number of non-standard page size translations. */
545 STAMCOUNTER StatIopfs; /**< Number of I/O page faults. */
546 /** @} */
547#endif
548} IOMMU;
549/** Pointer to the IOMMU device state. */
550typedef IOMMU *PIOMMU;
551/** Pointer to the const IOMMU device state. */
552typedef const IOMMU *PCIOMMU;
553AssertCompileMemberAlignment(IOMMU, hMmio, 8);
554#ifdef IOMMU_WITH_DTE_CACHE
555AssertCompileMemberAlignment(IOMMU, CritSectCache, 8);
556AssertCompileMemberAlignment(IOMMU, aDeviceIds, 8);
557AssertCompileMemberAlignment(IOMMU, aDteCache, 8);
558#endif
559#ifdef IOMMU_WITH_IRTE_CACHE
560AssertCompileMemberAlignment(IOMMU, aIrteCache, 8);
561#endif
562AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
563AssertCompileMemberAlignment(IOMMU, aDevTabBaseAddrs, 8);
564AssertCompileMemberAlignment(IOMMU, CmdBufHeadPtr, 8);
565AssertCompileMemberAlignment(IOMMU, Status, 8);
566
567/**
568 * The ring-3 IOMMU device state.
569 */
570typedef struct IOMMUR3
571{
572 /** Device instance. */
573 PPDMDEVINSR3 pDevInsR3;
574 /** The IOMMU helpers. */
575 R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
576 /** The command thread handle. */
577 R3PTRTYPE(PPDMTHREAD) pCmdThread;
578#ifdef IOMMU_WITH_IOTLBE_CACHE
579 /** Pointer to array of pre-allocated IOTLBEs. */
580 PIOTLBE paIotlbes;
581 /** Maps [DomainId,Iova] to [IOTLBE]. */
582 AVLU64TREE TreeIotlbe;
583 /** LRU list anchor for IOTLB entries. */
584 RTLISTANCHOR LstLruIotlbe;
585 /** Index of the next unused IOTLB. */
586 uint32_t idxUnusedIotlbe;
587 /** Number of cached IOTLB entries in the tree. */
588 uint32_t cCachedIotlbes;
589#endif
590} IOMMUR3;
591/** Pointer to the ring-3 IOMMU device state. */
592typedef IOMMUR3 *PIOMMUR3;
593/** Pointer to the const ring-3 IOMMU device state. */
594typedef const IOMMUR3 *PCIOMMUR3;
595#ifdef IOMMU_WITH_IOTLBE_CACHE
596AssertCompileMemberAlignment(IOMMUR3, paIotlbes, 8);
597AssertCompileMemberAlignment(IOMMUR3, TreeIotlbe, 8);
598AssertCompileMemberAlignment(IOMMUR3, LstLruIotlbe, 8);
599#endif
600
601/**
602 * The ring-0 IOMMU device state.
603 */
604typedef struct IOMMUR0
605{
606 /** Device instance. */
607 PPDMDEVINSR0 pDevInsR0;
608 /** The IOMMU helpers. */
609 R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
610} IOMMUR0;
611/** Pointer to the ring-0 IOMMU device state. */
612typedef IOMMUR0 *PIOMMUR0;
613
614/**
615 * The raw-mode IOMMU device state.
616 */
617typedef struct IOMMURC
618{
619 /** Device instance. */
620 PPDMDEVINSRC pDevInsRC;
621 /** The IOMMU helpers. */
622 RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
623} IOMMURC;
624/** Pointer to the raw-mode IOMMU device state. */
625typedef IOMMURC *PIOMMURC;
626
627/** The IOMMU device state for the current context. */
628typedef CTX_SUFF(IOMMU) IOMMUCC;
629/** Pointer to the IOMMU device state for the current context. */
630typedef CTX_SUFF(PIOMMU) PIOMMUCC;
631
632/**
633 * IOMMU register access.
634 */
635typedef struct IOMMUREGACC
636{
637 const char *pszName;
638 VBOXSTRICTRC (*pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value);
639 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
640} IOMMUREGACC;
641/** Pointer to an IOMMU register access. */
642typedef IOMMUREGACC *PIOMMUREGACC;
643/** Pointer to a const IOMMU register access. */
644typedef IOMMUREGACC const *PCIOMMUREGACC;
645
646#ifdef IOMMU_WITH_IOTLBE_CACHE
647/**
648 * IOTLBE flush argument.
649 */
650typedef struct IOTLBEFLUSHARG
651{
652 /** The ring-3 IOMMU device state. */
653 PIOMMUR3 pIommuR3;
654 /** The domain ID to flush. */
655 uint16_t idDomain;
656} IOTLBEFLUSHARG;
657/** Pointer to an IOTLBE flush argument. */
658typedef IOTLBEFLUSHARG *PIOTLBEFLUSHARG;
659/** Pointer to a const IOTLBE flush argument. */
660typedef IOTLBEFLUSHARG const *PCIOTLBEFLUSHARG;
661
662/**
663 * IOTLBE Info. argument.
664 */
665typedef struct IOTLBEINFOARG
666{
667 /** The ring-3 IOMMU device state. */
668 PIOMMUR3 pIommuR3;
669 /** The info helper. */
670 PCDBGFINFOHLP pHlp;
671 /** The domain ID to dump IOTLB entry. */
672 uint16_t idDomain;
673} IOTLBEINFOARG;
674/** Pointer to an IOTLBE flush argument. */
675typedef IOTLBEINFOARG *PIOTLBEINFOARG;
676/** Pointer to a const IOTLBE flush argument. */
677typedef IOTLBEINFOARG const *PCIOTLBEINFOARG;
678#endif
679
680/**
681 * IOMMU operation auxiliary info.
682 */
683typedef struct IOMMUOPAUX
684{
685 /** The IOMMU operation being performed. */
686 IOMMUOP enmOp;
687 /** The device table entry (can be NULL). */
688 PCDTE_T pDte;
689 /** The device ID (bus, device, function). */
690 uint16_t idDevice;
691 /** The domain ID (when the DTE isn't provided). */
692 uint16_t idDomain;
693} IOMMUOPAUX;
694/** Pointer to an I/O address lookup struct. */
695typedef IOMMUOPAUX *PIOMMUOPAUX;
696/** Pointer to a const I/O address lookup struct. */
697typedef IOMMUOPAUX const *PCIOMMUOPAUX;
698
699typedef DECLCALLBACKTYPE(int, FNIOPAGELOOKUP,(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
700 PIOPAGELOOKUP pPageLookup));
701typedef FNIOPAGELOOKUP *PFNIOPAGELOOKUP;
702
703
704/*********************************************************************************************************************************
705* Global Variables *
706*********************************************************************************************************************************/
707#ifdef IN_RING3
708/**
709 * An array of the number of device table segments supported.
710 * Indexed by u2DevTabSegSup.
711 */
712static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
713#endif
714
715#if (defined(IN_RING3) && defined(IOMMU_WITH_IOTLBE_CACHE)) || defined(LOG_ENABLED)
716/**
717 * The IOMMU I/O permission names.
718 */
719static const char * const g_aszPerm[] = { "none", "read", "write", "read+write" };
720#endif
721
722/**
723 * An array of the masks to select the device table segment index from a device ID.
724 */
725static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
726
727/**
728 * An array of the shift values to select the device table segment index from a
729 * device ID.
730 */
731static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
732
733/**
734 * The maximum size (inclusive) of each device table segment (0 to 7).
735 * Indexed by the device table segment index.
736 */
737static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
738
739
740#ifndef VBOX_DEVICE_STRUCT_TESTCASE
741/**
742 * Gets the maximum number of buffer entries for the given buffer length.
743 *
744 * @returns Number of buffer entries.
745 * @param uEncodedLen The length (power-of-2 encoded).
746 */
747DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
748{
749 Assert(uEncodedLen > 7);
750 Assert(uEncodedLen < 16);
751 return 2 << (uEncodedLen - 1);
752}
753
754
755/**
756 * Gets the total length of the buffer given a base register's encoded length.
757 *
758 * @returns The length of the buffer in bytes.
759 * @param uEncodedLen The length (power-of-2 encoded).
760 */
761DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
762{
763 Assert(uEncodedLen > 7);
764 Assert(uEncodedLen < 16);
765 return (2 << (uEncodedLen - 1)) << 4;
766}
767
768
769/**
770 * Gets the number of (unconsumed) entries in the event log.
771 *
772 * @returns The number of entries in the event log.
773 * @param pThis The shared IOMMU device state.
774 */
775static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
776{
777 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
778 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
779 if (idxTail >= idxHead)
780 return idxTail - idxHead;
781
782 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
783 return cMaxEvts - idxHead + idxTail;
784}
785
786
787#if (defined(IN_RING3) && defined(IOMMU_WITH_IOTLBE_CACHE)) || defined(LOG_ENABLED)
788/**
789 * Gets the descriptive I/O permission name for a memory access.
790 *
791 * @returns The I/O permission name.
792 * @param fPerm The I/O permissions for the access, see IOMMU_IO_PERM_XXX.
793 */
794static const char *iommuAmdMemAccessGetPermName(uint8_t fPerm)
795{
796 /* We shouldn't construct an access with "none" or "read+write" (must be read or write) permissions. */
797 Assert(fPerm > 0 && fPerm < RT_ELEMENTS(g_aszPerm));
798 return g_aszPerm[fPerm & IOMMU_IO_PERM_MASK];
799}
800#endif
801
802
803#ifdef IOMMU_WITH_DTE_CACHE
804/**
805 * Gets the basic I/O device flags for the given device table entry.
806 *
807 * @returns The basic I/O device flags.
808 * @param pDte The device table entry.
809 */
810static uint16_t iommuAmdGetBasicDevFlags(PCDTE_T pDte)
811{
812 /* Extract basic flags from bits 127:0 of the DTE. */
813 uint16_t fFlags = 0;
814 if (pDte->n.u1Valid)
815 {
816 fFlags |= IOMMU_DTE_CACHE_F_VALID;
817
818 /** @todo Skip the if checks here (shift/mask the relevant bits over). */
819 if (pDte->n.u1SuppressAllPfEvents)
820 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
821 if (pDte->n.u1SuppressPfEvents)
822 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_IOPF;
823
824 uint16_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
825 AssertCompile(IOMMU_DTE_CACHE_F_IO_PERM_MASK == IOMMU_IO_PERM_MASK);
826 fFlags |= fDtePerm << IOMMU_DTE_CACHE_F_IO_PERM_SHIFT;
827 }
828
829 /* Extract basic flags from bits 255:128 of the DTE. */
830 if (pDte->n.u1IntrMapValid)
831 {
832 fFlags |= IOMMU_DTE_CACHE_F_INTR_MAP_VALID;
833
834 /** @todo Skip the if check here (shift/mask the relevant bit over). */
835 if (pDte->n.u1IgnoreUnmappedIntrs)
836 fFlags |= IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
837
838 uint16_t const fIntrCtrl = IOMMU_DTE_GET_INTR_CTRL(pDte);
839 AssertCompile(IOMMU_DTE_CACHE_F_INTR_CTRL_MASK == IOMMU_DTE_INTR_CTRL_MASK);
840 fFlags |= fIntrCtrl << IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT;
841 }
842 return fFlags;
843}
844#endif
845
846
847/**
848 * Remaps the source MSI to the destination MSI given the IRTE.
849 *
850 * @param pMsiIn The source MSI.
851 * @param pMsiOut Where to store the remapped MSI.
852 * @param pIrte The IRTE used for the remapping.
853 */
854static void iommuAmdIrteRemapMsi(PCMSIMSG pMsiIn, PMSIMSG pMsiOut, PCIRTE_T pIrte)
855{
856 /* Preserve all bits from the source MSI address and data that don't map 1:1 from the IRTE. */
857 *pMsiOut = *pMsiIn;
858
859 pMsiOut->Addr.n.u1DestMode = pIrte->n.u1DestMode;
860 pMsiOut->Addr.n.u8DestId = pIrte->n.u8Dest;
861
862 pMsiOut->Data.n.u8Vector = pIrte->n.u8Vector;
863 pMsiOut->Data.n.u3DeliveryMode = pIrte->n.u3IntrType;
864}
865
866
867#ifdef IOMMU_WITH_DTE_CACHE
868/**
869 * Looks up an entry in the DTE cache for the given device ID.
870 *
871 * @returns The index of the entry, or the cache capacity if no entry was found.
872 * @param pThis The shared IOMMU device state.
873 * @param idDevice The device ID (bus, device, function).
874 */
875DECLINLINE(uint16_t) iommuAmdDteCacheEntryLookup(PIOMMU pThis, uint16_t idDevice)
876{
877 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
878 for (uint16_t i = 0; i < cDeviceIds; i++)
879 {
880 if (pThis->aDeviceIds[i] == idDevice)
881 return i;
882 }
883 return cDeviceIds;
884}
885
886
887/**
888 * Gets an free/unused DTE cache entry.
889 *
890 * @returns The index of an unused entry, or cache capacity if the cache is full.
891 * @param pThis The shared IOMMU device state.
892 */
893DECLINLINE(uint16_t) iommuAmdDteCacheEntryGetUnused(PCIOMMU pThis)
894{
895 /*
896 * ASSUMES device ID 0 is the PCI host bridge or the IOMMU itself
897 * (the latter being an ugly hack) and cannot be a valid device ID.
898 */
899 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
900 for (uint16_t i = 0; i < cDeviceIds; i++)
901 {
902 if (!pThis->aDeviceIds[i])
903 return i;
904 }
905 return cDeviceIds;
906}
907
908
909/**
910 * Adds a device-table entry to the cache.
911 *
912 * @returns VBox status code.
913 * @retval VERR_OUT_OF_RESOURCES if the cache is full.
914 *
915 * @param pDevIns The IOMMU instance data.
916 * @param idDevice The device ID (bus, device, function).
917 * @param pDte The device table entry.
918 */
919static int iommuAmdDteCacheAdd(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte)
920{
921 int rc = VINF_SUCCESS;
922 uint16_t const fFlags = iommuAmdGetBasicDevFlags(pDte) | IOMMU_DTE_CACHE_F_PRESENT;
923 uint16_t const idDomain = pDte->n.u16DomainId;
924
925 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
926 IOMMU_CACHE_LOCK(pDevIns, pThis);
927
928 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
929 uint16_t idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
930 if (idxDte >= cDteCache)
931 {
932 idxDte = iommuAmdDteCacheEntryGetUnused(pThis);
933 if (idxDte < cDteCache)
934 {
935 pThis->aDeviceIds[idxDte] = idDevice;
936 pThis->aDteCache[idxDte].fFlags = fFlags;
937 pThis->aDteCache[idxDte].idDomain = idDomain;
938 }
939 else
940 rc = VERR_OUT_OF_RESOURCES;
941 }
942 /* else: A DTE cache entry already exists, do nothing. */
943
944 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
945 return rc;
946}
947
948
949/**
950 * Adds one or more I/O device flags if the device is already present in the cache.
951 *
952 * @param pDevIns The IOMMU instance data.
953 * @param idDevice The device ID (bus, device, function).
954 * @param fOrMask Device flags to add to the existing flags, see
955 * IOMMU_DTE_CACHE_F_XXX.
956 * @param fAndMask Device flags to remove from the existing flags, see
957 * IOMMU_DTE_CACHE_F_XXX.
958 */
959static void iommuAmdDteCacheUpdateFlags(PPDMDEVINS pDevIns, uint16_t idDevice, uint16_t fOrMask, uint16_t fAndMask)
960{
961 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
962 IOMMU_CACHE_LOCK(pDevIns, pThis);
963
964 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
965 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
966 if ( idxDte < cDteCache
967 && (pThis->aDteCache[idxDte].fFlags & IOMMU_DTE_CACHE_F_PRESENT))
968 {
969 uint16_t const fNewFlags = (pThis->aDteCache[idxDte].fFlags | fOrMask) & ~fAndMask;
970 pThis->aDteCache[idxDte].fFlags = fNewFlags;
971 }
972
973 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
974}
975
976
977# ifdef IN_RING3
978/**
979 * Removes a DTE cache entry.
980 *
981 * @param pDevIns The IOMMU instance data.
982 * @param idDevice The device ID to remove cache entries for.
983 */
984static void iommuAmdDteCacheRemove(PPDMDEVINS pDevIns, uint16_t idDevice)
985{
986 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
987 IOMMU_CACHE_LOCK(pDevIns, pThis);
988
989 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
990 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
991 if (idxDte < cDteCache)
992 {
993 pThis->aDteCache[idxDte].fFlags = 0;
994 pThis->aDteCache[idxDte].idDomain = 0;
995 }
996
997 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
998}
999
1000
1001/**
1002 * Removes all entries in the device table entry cache.
1003 *
1004 * @param pDevIns The IOMMU instance data.
1005 */
1006static void iommuAmdDteCacheRemoveAll(PPDMDEVINS pDevIns)
1007{
1008 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1009 IOMMU_CACHE_LOCK(pDevIns, pThis);
1010 RT_ZERO(pThis->aDeviceIds);
1011 RT_ZERO(pThis->aDteCache);
1012 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1013}
1014# endif /* IN_RING3 */
1015#endif /* IOMMU_WITH_DTE_CACHE */
1016
1017
1018#ifdef IOMMU_WITH_IOTLBE_CACHE
1019/**
1020 * Moves the IOTLB entry to the least recently used slot.
1021 *
1022 * @param pThisR3 The ring-3 IOMMU device state.
1023 * @param pIotlbe The IOTLB entry to move.
1024 */
1025DECLINLINE(void) iommuAmdIotlbEntryMoveToLru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1026{
1027 if (!RTListNodeIsFirst(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1028 {
1029 RTListNodeRemove(&pIotlbe->NdLru);
1030 RTListPrepend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1031 }
1032}
1033
1034
1035/**
1036 * Moves the IOTLB entry to the most recently used slot.
1037 *
1038 * @param pThisR3 The ring-3 IOMMU device state.
1039 * @param pIotlbe The IOTLB entry to move.
1040 */
1041DECLINLINE(void) iommuAmdIotlbEntryMoveToMru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1042{
1043 if (!RTListNodeIsLast(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1044 {
1045 RTListNodeRemove(&pIotlbe->NdLru);
1046 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1047 }
1048}
1049
1050
1051# ifdef IN_RING3
1052/**
1053 * Dumps the IOTLB entry via the debug info helper.
1054 *
1055 * @returns VINF_SUCCESS.
1056 * @param pNode Pointer to an IOTLB entry to dump info.
1057 * @param pvUser Pointer to an IOTLBEINFOARG.
1058 */
1059static DECLCALLBACK(int) iommuAmdR3IotlbEntryInfo(PAVLU64NODECORE pNode, void *pvUser)
1060{
1061 /* Validate. */
1062 PCIOTLBEINFOARG pArgs = (PCIOTLBEINFOARG)pvUser;
1063 AssertPtr(pArgs);
1064 AssertPtr(pArgs->pIommuR3);
1065 AssertPtr(pArgs->pHlp);
1066 //Assert(pArgs->pIommuR3->u32Magic == IOMMU_MAGIC);
1067
1068 uint16_t const idDomain = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1069 if (idDomain == pArgs->idDomain)
1070 {
1071 PCIOTLBE pIotlbe = (PCIOTLBE)pNode;
1072 AVLU64KEY const uKey = pIotlbe->Core.Key;
1073 uint64_t const uIova = IOMMU_IOTLB_KEY_GET_IOVA(uKey);
1074 RTGCPHYS const GCPhysSpa = pIotlbe->PageLookup.GCPhysSpa;
1075 uint8_t const cShift = pIotlbe->PageLookup.cShift;
1076 size_t const cbPage = RT_BIT_64(cShift);
1077 uint8_t const fPerm = pIotlbe->PageLookup.fPerm;
1078 const char *pszPerm = iommuAmdMemAccessGetPermName(fPerm);
1079 bool const fEvictPending = pIotlbe->fEvictPending;
1080
1081 PCDBGFINFOHLP pHlp = pArgs->pHlp;
1082 pHlp->pfnPrintf(pHlp, " Key = %#RX64 (%#RX64)\n", uKey, uIova);
1083 pHlp->pfnPrintf(pHlp, " GCPhys = %#RGp\n", GCPhysSpa);
1084 pHlp->pfnPrintf(pHlp, " cShift = %u (%zu bytes)\n", cShift, cbPage);
1085 pHlp->pfnPrintf(pHlp, " fPerm = %#x (%s)\n", fPerm, pszPerm);
1086 pHlp->pfnPrintf(pHlp, " fEvictPending = %RTbool\n", fEvictPending);
1087 }
1088
1089 return VINF_SUCCESS;
1090}
1091# endif /* IN_RING3 */
1092
1093
1094/**
1095 * Removes the IOTLB entry if it's associated with the specified domain ID.
1096 *
1097 * @returns VINF_SUCCESS.
1098 * @param pNode Pointer to an IOTLBE.
1099 * @param pvUser Pointer to an IOTLBEFLUSHARG containing the domain ID.
1100 */
1101static DECLCALLBACK(int) iommuAmdIotlbEntryRemoveDomainId(PAVLU64NODECORE pNode, void *pvUser)
1102{
1103 /* Validate. */
1104 PCIOTLBEFLUSHARG pArgs = (PCIOTLBEFLUSHARG)pvUser;
1105 AssertPtr(pArgs);
1106 AssertPtr(pArgs->pIommuR3);
1107 //Assert(pArgs->pIommuR3->u32Magic == IOMMU_MAGIC);
1108
1109 uint16_t const idDomain = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1110 if (idDomain == pArgs->idDomain)
1111 {
1112 /* Mark this entry is as invalidated and needs to be evicted later. */
1113 PIOTLBE pIotlbe = (PIOTLBE)pNode;
1114 pIotlbe->fEvictPending = true;
1115 iommuAmdIotlbEntryMoveToLru(pArgs->pIommuR3, (PIOTLBE)pNode);
1116 }
1117 return VINF_SUCCESS;
1118}
1119
1120
1121/**
1122 * Destroys an IOTLB entry that's in the tree.
1123 *
1124 * @returns VINF_SUCCESS.
1125 * @param pNode Pointer to an IOTLBE.
1126 * @param pvUser Opaque data. Currently not used, will be NULL.
1127 */
1128static DECLCALLBACK(int) iommuAmdIotlbEntryDestroy(PAVLU64NODECORE pNode, void *pvUser)
1129{
1130 RT_NOREF(pvUser);
1131 PIOTLBE pIotlbe = (PIOTLBE)pNode;
1132 Assert(pIotlbe);
1133 pIotlbe->NdLru.pNext = NULL;
1134 pIotlbe->NdLru.pPrev = NULL;
1135 RT_ZERO(pIotlbe->PageLookup);
1136 pIotlbe->fEvictPending = false;
1137 return VINF_SUCCESS;
1138}
1139
1140
1141/**
1142 * Inserts an IOTLB entry into the cache.
1143 *
1144 * @param pThis The shared IOMMU device state.
1145 * @param pThisR3 The ring-3 IOMMU device state.
1146 * @param pIotlbe The IOTLB entry to initialize and insert.
1147 * @param idDomain The domain ID.
1148 * @param uIova The I/O virtual address.
1149 * @param pPageLookup The I/O page lookup result of the access.
1150 */
1151static void iommuAmdIotlbEntryInsert(PIOMMU pThis, PIOMMUR3 pThisR3, PIOTLBE pIotlbe, uint16_t idDomain, uint64_t uIova,
1152 PCIOPAGELOOKUP pPageLookup)
1153{
1154 /* Initialize the IOTLB entry with results of the I/O page walk. */
1155 AVLU64KEY const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1156 Assert(uKey != IOMMU_IOTLB_KEY_NIL);
1157
1158 /* Check if the entry already exists. */
1159 PIOTLBE pFound = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, uKey);
1160 if (!pFound)
1161 {
1162 /* Insert the entry into the cache. */
1163 pIotlbe->Core.Key = uKey;
1164 pIotlbe->PageLookup = *pPageLookup;
1165 Assert(!pIotlbe->fEvictPending);
1166
1167 bool const fInserted = RTAvlU64Insert(&pThisR3->TreeIotlbe, &pIotlbe->Core);
1168 Assert(fInserted); NOREF(fInserted);
1169 Assert(pThisR3->cCachedIotlbes < IOMMU_IOTLBE_MAX);
1170 ++pThisR3->cCachedIotlbes;
1171 STAM_COUNTER_INC(&pThis->StatIotlbeCached); NOREF(pThis);
1172 }
1173 else
1174 {
1175 /* Update the existing entry. */
1176 Assert(pFound->Core.Key == uKey);
1177 if (pFound->fEvictPending)
1178 {
1179 pFound->fEvictPending = false;
1180 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse); NOREF(pThis);
1181 }
1182 pFound->PageLookup = *pPageLookup;
1183 }
1184}
1185
1186
1187/**
1188 * Removes an IOTLB entry from the cache for the given key.
1189 *
1190 * @returns Pointer to the removed IOTLB entry, NULL if the entry wasn't found in
1191 * the tree.
1192 * @param pThis The shared IOMMU device state.
1193 * @param pThisR3 The ring-3 IOMMU device state.
1194 * @param uKey The key of the IOTLB entry to remove.
1195 */
1196static PIOTLBE iommuAmdIotlbEntryRemove(PIOMMU pThis, PIOMMUR3 pThisR3, AVLU64KEY uKey)
1197{
1198 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Remove(&pThisR3->TreeIotlbe, uKey);
1199 if (pIotlbe)
1200 {
1201 if (pIotlbe->fEvictPending)
1202 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse);
1203
1204 RT_ZERO(pIotlbe->Core);
1205 RT_ZERO(pIotlbe->PageLookup);
1206 /* We must not erase the LRU node connections here! */
1207 pIotlbe->fEvictPending = false;
1208 Assert(pIotlbe->Core.Key == IOMMU_IOTLB_KEY_NIL);
1209
1210 Assert(pThisR3->cCachedIotlbes > 0);
1211 --pThisR3->cCachedIotlbes;
1212 STAM_COUNTER_DEC(&pThis->StatIotlbeCached); NOREF(pThis);
1213 }
1214 return pIotlbe;
1215}
1216
1217
1218/**
1219 * Looks up an IOTLB from the cache.
1220 *
1221 * @returns Pointer to IOTLB entry if found, NULL otherwise.
1222 * @param pThis The shared IOMMU device state.
1223 * @param pThisR3 The ring-3 IOMMU device state.
1224 * @param idDomain The domain ID.
1225 * @param uIova The I/O virtual address.
1226 */
1227static PIOTLBE iommuAmdIotlbLookup(PIOMMU pThis, PIOMMUR3 pThisR3, uint64_t idDomain, uint64_t uIova)
1228{
1229 RT_NOREF(pThis);
1230
1231 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1232 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, uKey);
1233 if ( pIotlbe
1234 && !pIotlbe->fEvictPending)
1235 return pIotlbe;
1236
1237 /*
1238 * Domain Id wildcard invalidations only marks entries for eviction later but doesn't remove
1239 * them from the cache immediately. We found an entry pending eviction, just return that
1240 * nothing was found (rather than evicting now).
1241 */
1242 return NULL;
1243}
1244
1245
1246/**
1247 * Adds an IOTLB entry to the cache.
1248 *
1249 * @param pThis The shared IOMMU device state.
1250 * @param pThisR3 The ring-3 IOMMU device state.
1251 * @param idDomain The domain ID.
1252 * @param uIovaPage The I/O virtual address (must be 4K aligned).
1253 * @param pPageLookup The I/O page lookup result of the access.
1254 */
1255static void iommuAmdIotlbAdd(PIOMMU pThis, PIOMMUR3 pThisR3, uint16_t idDomain, uint64_t uIovaPage, PCIOPAGELOOKUP pPageLookup)
1256{
1257 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
1258 Assert(pPageLookup);
1259 Assert(pPageLookup->cShift <= 31);
1260 Assert(pPageLookup->fPerm != IOMMU_IO_PERM_NONE);
1261
1262 /*
1263 * If there are no unused IOTLB entries, evict the LRU entry.
1264 * Otherwise, get a new IOTLB entry from the pre-allocated list.
1265 */
1266 if (pThisR3->idxUnusedIotlbe == IOMMU_IOTLBE_MAX)
1267 {
1268 /* Grab the least recently used entry. */
1269 PIOTLBE pIotlbe = RTListGetFirst(&pThisR3->LstLruIotlbe, IOTLBE, NdLru);
1270 Assert(pIotlbe);
1271
1272 /* If the entry is in the cache, remove it. */
1273 if (pIotlbe->Core.Key != IOMMU_IOTLB_KEY_NIL)
1274 iommuAmdIotlbEntryRemove(pThis, pThisR3, pIotlbe->Core.Key);
1275
1276 /* Initialize and insert the IOTLB entry into the cache. */
1277 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, idDomain, uIovaPage, pPageLookup);
1278
1279 /* Move the entry to the most recently used slot. */
1280 iommuAmdIotlbEntryMoveToMru(pThisR3, pIotlbe);
1281 }
1282 else
1283 {
1284 /* Grab an unused IOTLB entry from the pre-allocated list. */
1285 PIOTLBE pIotlbe = &pThisR3->paIotlbes[pThisR3->idxUnusedIotlbe];
1286 ++pThisR3->idxUnusedIotlbe;
1287
1288 /* Initialize and insert the IOTLB entry into the cache. */
1289 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, idDomain, uIovaPage, pPageLookup);
1290
1291 /* Add the entry to the most recently used slot. */
1292 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1293 }
1294}
1295
1296
1297/**
1298 * Removes all IOTLB entries from the cache.
1299 *
1300 * @param pDevIns The IOMMU instance data.
1301 */
1302static void iommuAmdIotlbRemoveAll(PPDMDEVINS pDevIns)
1303{
1304 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1305 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1306 IOMMU_CACHE_LOCK(pDevIns, pThis);
1307
1308 if (pThisR3->cCachedIotlbes > 0)
1309 {
1310 RTAvlU64Destroy(&pThisR3->TreeIotlbe, iommuAmdIotlbEntryDestroy, NULL /* pvParam */);
1311 RTListInit(&pThisR3->LstLruIotlbe);
1312 pThisR3->idxUnusedIotlbe = 0;
1313 pThisR3->cCachedIotlbes = 0;
1314 STAM_COUNTER_RESET(&pThis->StatIotlbeCached);
1315 }
1316
1317 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1318}
1319
1320
1321/**
1322 * Removes IOTLB entries for the range of I/O virtual addresses and the specified
1323 * domain ID from the cache.
1324 *
1325 * @param pDevIns The IOMMU instance data.
1326 * @param idDomain The domain ID.
1327 * @param uIova The I/O virtual address to invalidate.
1328 * @param cbInvalidate The size of the invalidation (must be 4K aligned).
1329 */
1330static void iommuAmdIotlbRemoveRange(PPDMDEVINS pDevIns, uint16_t idDomain, uint64_t uIova, size_t cbInvalidate)
1331{
1332 /* Validate. */
1333 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1334 Assert(!(cbInvalidate & X86_PAGE_4K_OFFSET_MASK));
1335 Assert(cbInvalidate >= X86_PAGE_4K_SIZE);
1336
1337 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1338 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1339 IOMMU_CACHE_LOCK(pDevIns, pThis);
1340
1341 do
1342 {
1343 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1344 PIOTLBE pIotlbe = iommuAmdIotlbEntryRemove(pThis, pThisR3, uKey);
1345 if (pIotlbe)
1346 iommuAmdIotlbEntryMoveToLru(pThisR3, pIotlbe);
1347 uIova += X86_PAGE_4K_SIZE;
1348 cbInvalidate -= X86_PAGE_4K_SIZE;
1349 } while (cbInvalidate > 0);
1350
1351 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1352}
1353
1354
1355/**
1356 * Removes all IOTLB entries for the specified domain ID.
1357 *
1358 * @param pDevIns The IOMMU instance data.
1359 * @param idDomain The domain ID.
1360 */
1361static void iommuAmdIotlbRemoveDomainId(PPDMDEVINS pDevIns, uint16_t idDomain)
1362{
1363 /*
1364 * We need to iterate the tree and search based on the domain ID.
1365 * But it seems we cannot remove items while iterating the tree.
1366 * Thus, we simply mark entries for eviction later but move them to the LRU
1367 * so they will eventually get evicted and re-cycled as the cache gets re-populated.
1368 */
1369 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1370 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1371 IOMMU_CACHE_LOCK(pDevIns, pThis);
1372
1373 IOTLBEFLUSHARG Args;
1374 Args.pIommuR3 = pThisR3;
1375 Args.idDomain = idDomain;
1376 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdIotlbEntryRemoveDomainId, &Args);
1377
1378 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1379}
1380
1381
1382/**
1383 * Adds or updates IOTLB entries for the given range of I/O virtual addresses.
1384 *
1385 * @param pDevIns The IOMMU instance data.
1386 * @param idDomain The domain ID.
1387 * @param uIovaPage The I/O virtual address (must be 4K aligned).
1388 * @param cbContiguous The size of the access.
1389 * @param pAddrOut The translated I/O address lookup.
1390 *
1391 * @remarks All pages in the range specified by @c cbContiguous must have identical
1392 * permissions and page sizes.
1393 */
1394static void iommuAmdIotlbAddRange(PPDMDEVINS pDevIns, uint16_t idDomain, uint64_t uIovaPage, size_t cbContiguous,
1395 PCIOPAGELOOKUP pAddrOut)
1396{
1397 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
1398
1399 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1400 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1401
1402 IOPAGELOOKUP PageLookup;
1403 PageLookup.GCPhysSpa = pAddrOut->GCPhysSpa & X86_PAGE_4K_BASE_MASK;
1404 PageLookup.cShift = pAddrOut->cShift;
1405 PageLookup.fPerm = pAddrOut->fPerm;
1406
1407 size_t const cbIova = RT_ALIGN_Z(cbContiguous, X86_PAGE_4K_SIZE);
1408 Assert(!(cbIova & X86_PAGE_4K_OFFSET_MASK));
1409 Assert(cbIova >= X86_PAGE_4K_SIZE);
1410
1411 size_t cPages = cbIova / X86_PAGE_4K_SIZE;
1412 cPages = RT_MIN(cPages, IOMMU_IOTLBE_MAX);
1413
1414 IOMMU_CACHE_LOCK(pDevIns, pThis);
1415 /** @todo Re-check DTE cache? */
1416 /*
1417 * Add IOTLB entries for every page in the access.
1418 * The page size and permissions are assumed to be identical to every
1419 * page in this access.
1420 */
1421 while (cPages > 0)
1422 {
1423 iommuAmdIotlbAdd(pThis, pThisR3, idDomain, uIovaPage, &PageLookup);
1424 uIovaPage += X86_PAGE_4K_SIZE;
1425 PageLookup.GCPhysSpa += X86_PAGE_4K_SIZE;
1426 --cPages;
1427 }
1428 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1429}
1430#endif /* IOMMU_WITH_IOTLBE_CACHE */
1431
1432
1433#ifdef IOMMU_WITH_IRTE_CACHE
1434/**
1435 * Looks up an IRTE cache entry.
1436 *
1437 * @returns Index of the found entry, or cache capacity if not found.
1438 * @param pThis The shared IOMMU device state.
1439 * @param idDevice The device ID (bus, device, function).
1440 * @param offIrte The offset into the interrupt remap table.
1441 */
1442static uint16_t iommuAmdIrteCacheEntryLookup(PCIOMMU pThis, uint16_t idDevice, uint16_t offIrte)
1443{
1444 /** @todo Consider sorting and binary search when the cache capacity grows.
1445 * For the IRTE cache this should be okay since typically guests do not alter the
1446 * interrupt remapping once programmed, so hopefully sorting shouldn't happen
1447 * often. */
1448 uint32_t const uKey = IOMMU_IRTE_CACHE_KEY_MAKE(idDevice, offIrte);
1449 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1450 for (uint16_t i = 0; i < cIrteCache; i++)
1451 if (pThis->aIrteCache[i].uKey == uKey)
1452 return i;
1453 return cIrteCache;
1454}
1455
1456
1457/**
1458 * Gets a free/unused IRTE cache entry.
1459 *
1460 * @returns The index of an unused entry, or cache capacity if the cache is full.
1461 * @param pThis The shared IOMMU device state.
1462 */
1463static uint16_t iommuAmdIrteCacheEntryGetUnused(PCIOMMU pThis)
1464{
1465 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1466 for (uint16_t i = 0; i < cIrteCache; i++)
1467 if (pThis->aIrteCache[i].uKey == IOMMU_IRTE_CACHE_KEY_NIL)
1468 {
1469 Assert(!pThis->aIrteCache[i].Irte.u32);
1470 return i;
1471 }
1472 return cIrteCache;
1473}
1474
1475
1476/**
1477 * Looks up the IRTE cache for the given MSI.
1478 *
1479 * @returns VBox status code.
1480 * @param pDevIns The IOMMU instance data.
1481 * @param idDevice The device ID (bus, device, function).
1482 * @param enmOp The IOMMU operation being performed.
1483 * @param pMsiIn The source MSI.
1484 * @param pMsiOut Where to store the remapped MSI.
1485 */
1486static int iommuAmdIrteCacheLookup(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1487{
1488 RT_NOREF(enmOp); /* May need it if we have to report errors (currently we fallback to the slower path to do that). */
1489
1490 int rc = VERR_NOT_FOUND;
1491 /* Deal with such cases in the slower/fallback path. */
1492 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
1493 { /* likely */ }
1494 else
1495 return rc;
1496
1497 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1498 IOMMU_CACHE_LOCK(pDevIns, pThis);
1499
1500 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, idDevice);
1501 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
1502 {
1503 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
1504 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1505 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1506 {
1507 Assert((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE); /* Paranoia. */
1508
1509 /* Currently, we only cache remapping of fixed and arbitrated interrupts. */
1510 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
1511 if (u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
1512 {
1513 uint8_t const uIntrCtrl = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT)
1514 & IOMMU_DTE_CACHE_F_INTR_CTRL_MASK;
1515 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
1516 {
1517 /* Interrupt table length has been verified prior to adding entries to the cache. */
1518 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(pMsiIn->Data.u32);
1519 uint16_t const idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, idDevice, offIrte);
1520 if (idxIrteCache < RT_ELEMENTS(pThis->aIrteCache))
1521 {
1522 PCIRTE_T pIrte = &pThis->aIrteCache[idxIrteCache].Irte;
1523 Assert(pIrte->n.u1RemapEnable);
1524 Assert(pIrte->n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO);
1525 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, pIrte);
1526 rc = VINF_SUCCESS;
1527 }
1528 }
1529 else if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
1530 {
1531 *pMsiOut = *pMsiIn;
1532 rc = VINF_SUCCESS;
1533 }
1534 }
1535 }
1536 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
1537 {
1538 *pMsiOut = *pMsiIn;
1539 rc = VINF_SUCCESS;
1540 }
1541 }
1542
1543 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1544 return rc;
1545}
1546
1547
1548/**
1549 * Adds or updates the IRTE cache for the given IRTE.
1550 *
1551 * @returns VBox status code.
1552 * @retval VERR_OUT_OF_RESOURCES if the cache is full.
1553 *
1554 * @param pDevIns The IOMMU instance data.
1555 * @param idDevice The device ID (bus, device, function).
1556 * @param offIrte The offset into the interrupt remap table.
1557 * @param pIrte The IRTE to cache.
1558 */
1559static int iommuAmdIrteCacheAdd(PPDMDEVINS pDevIns, uint16_t idDevice, uint16_t offIrte, PCIRTE_T pIrte)
1560{
1561 Assert(offIrte != 0xffff); /* Shouldn't be a valid IRTE table offset since sizeof(IRTE) is a multiple of 4. */
1562
1563 int rc = VINF_SUCCESS;
1564 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1565 Assert(idDevice != pThis->uPciAddress);
1566 IOMMU_CACHE_LOCK(pDevIns, pThis);
1567
1568 /* Find an existing entry or get an unused slot. */
1569 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1570 uint16_t idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, idDevice, offIrte);
1571 if ( idxIrteCache < cIrteCache
1572 || (idxIrteCache = iommuAmdIrteCacheEntryGetUnused(pThis)) < cIrteCache)
1573 {
1574 pThis->aIrteCache[idxIrteCache].uKey = IOMMU_IRTE_CACHE_KEY_MAKE(idDevice, offIrte);
1575 pThis->aIrteCache[idxIrteCache].Irte = *pIrte;
1576 }
1577 else
1578 rc = VERR_OUT_OF_RESOURCES;
1579
1580 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1581 return rc;
1582}
1583
1584
1585# ifdef IN_RING3
1586/**
1587 * Removes IRTE cache entries for the given device ID.
1588 *
1589 * @param pDevIns The IOMMU instance data.
1590 * @param idDevice The device ID (bus, device, function).
1591 */
1592static void iommuAmdIrteCacheRemove(PPDMDEVINS pDevIns, uint16_t idDevice)
1593{
1594 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1595 IOMMU_CACHE_LOCK(pDevIns, pThis);
1596 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1597 for (uint16_t i = 0; i < cIrteCache; i++)
1598 {
1599 PIRTECACHE pIrteCache = &pThis->aIrteCache[i];
1600 if (idDevice == IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(pIrteCache->uKey))
1601 {
1602 pIrteCache->uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1603 pIrteCache->Irte.u32 = 0;
1604 /* There could multiple IRTE entries for a device ID, continue searching. */
1605 }
1606 }
1607 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1608}
1609
1610
1611/**
1612 * Removes all IRTE cache entries.
1613 *
1614 * @param pDevIns The IOMMU instance data.
1615 */
1616static void iommuAmdIrteCacheRemoveAll(PPDMDEVINS pDevIns)
1617{
1618 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1619 IOMMU_CACHE_LOCK(pDevIns, pThis);
1620 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1621 for (uint16_t i = 0; i < cIrteCache; i++)
1622 {
1623 pThis->aIrteCache[i].uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1624 pThis->aIrteCache[i].Irte.u32 = 0;
1625 }
1626 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1627}
1628# endif /* IN_RING3 */
1629#endif /* IOMMU_WITH_IRTE_CACHE */
1630
1631
1632/**
1633 * Atomically reads the control register without locking the IOMMU device.
1634 *
1635 * @returns The control register.
1636 * @param pThis The shared IOMMU device state.
1637 */
1638DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrlUnlocked(PCIOMMU pThis)
1639{
1640 IOMMU_CTRL_T Ctrl;
1641 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
1642 return Ctrl;
1643}
1644
1645
1646/**
1647 * Returns whether MSI is enabled for the IOMMU.
1648 *
1649 * @returns Whether MSI is enabled.
1650 * @param pDevIns The IOMMU device instance.
1651 *
1652 * @note There should be a PCIDevXxx function for this.
1653 */
1654static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
1655{
1656 MSI_CAP_HDR_T MsiCapHdr;
1657 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
1658 return MsiCapHdr.n.u1MsiEnable;
1659}
1660
1661
1662/**
1663 * Signals a PCI target abort.
1664 *
1665 * @param pDevIns The IOMMU device instance.
1666 */
1667static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
1668{
1669 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1670 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
1671 PDMPciDevSetStatus(pPciDev, u16Status);
1672}
1673
1674
1675/**
1676 * Wakes up the command thread if there are commands to be processed.
1677 *
1678 * @param pDevIns The IOMMU device instance.
1679 *
1680 * @remarks The IOMMU lock must be held while calling this!
1681 */
1682static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1683{
1684 Log4Func(("\n"));
1685
1686 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1687 if ( pThis->Status.n.u1CmdBufRunning
1688 && pThis->CmdBufTailPtr.n.off != pThis->CmdBufHeadPtr.n.off
1689 && !ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, true))
1690 {
1691 Log4Func(("Signaling command thread\n"));
1692 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
1693 }
1694}
1695
1696
1697/**
1698 * Reads the Device Table Base Address Register.
1699 */
1700static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1701{
1702 RT_NOREF(pDevIns, offReg);
1703 *pu64Value = pThis->aDevTabBaseAddrs[0].u64;
1704 return VINF_SUCCESS;
1705}
1706
1707
1708/**
1709 * Reads the Command Buffer Base Address Register.
1710 */
1711static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1712{
1713 RT_NOREF(pDevIns, offReg);
1714 *pu64Value = pThis->CmdBufBaseAddr.u64;
1715 return VINF_SUCCESS;
1716}
1717
1718
1719/**
1720 * Reads the Event Log Base Address Register.
1721 */
1722static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1723{
1724 RT_NOREF(pDevIns, offReg);
1725 *pu64Value = pThis->EvtLogBaseAddr.u64;
1726 return VINF_SUCCESS;
1727}
1728
1729
1730/**
1731 * Reads the Control Register.
1732 */
1733static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1734{
1735 RT_NOREF(pDevIns, offReg);
1736 *pu64Value = pThis->Ctrl.u64;
1737 return VINF_SUCCESS;
1738}
1739
1740
1741/**
1742 * Reads the Exclusion Range Base Address Register.
1743 */
1744static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1745{
1746 RT_NOREF(pDevIns, offReg);
1747 *pu64Value = pThis->ExclRangeBaseAddr.u64;
1748 return VINF_SUCCESS;
1749}
1750
1751
1752/**
1753 * Reads to the Exclusion Range Limit Register.
1754 */
1755static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1756{
1757 RT_NOREF(pDevIns, offReg);
1758 *pu64Value = pThis->ExclRangeLimit.u64;
1759 return VINF_SUCCESS;
1760}
1761
1762
1763/**
1764 * Reads to the Extended Feature Register.
1765 */
1766static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1767{
1768 RT_NOREF(pDevIns, offReg);
1769 *pu64Value = pThis->ExtFeat.u64;
1770 return VINF_SUCCESS;
1771}
1772
1773
1774/**
1775 * Reads to the PPR Log Base Address Register.
1776 */
1777static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1778{
1779 RT_NOREF(pDevIns, offReg);
1780 *pu64Value = pThis->PprLogBaseAddr.u64;
1781 return VINF_SUCCESS;
1782}
1783
1784
1785/**
1786 * Writes the Hardware Event Register (Hi).
1787 */
1788static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1789{
1790 RT_NOREF(pDevIns, offReg);
1791 *pu64Value = pThis->HwEvtHi.u64;
1792 return VINF_SUCCESS;
1793}
1794
1795
1796/**
1797 * Reads the Hardware Event Register (Lo).
1798 */
1799static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1800{
1801 RT_NOREF(pDevIns, offReg);
1802 *pu64Value = pThis->HwEvtLo;
1803 return VINF_SUCCESS;
1804}
1805
1806
1807/**
1808 * Reads the Hardware Event Status Register.
1809 */
1810static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1811{
1812 RT_NOREF(pDevIns, offReg);
1813 *pu64Value = pThis->HwEvtStatus.u64;
1814 return VINF_SUCCESS;
1815}
1816
1817
1818/**
1819 * Reads to the GA Log Base Address Register.
1820 */
1821static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1822{
1823 RT_NOREF(pDevIns, offReg);
1824 *pu64Value = pThis->GALogBaseAddr.u64;
1825 return VINF_SUCCESS;
1826}
1827
1828
1829/**
1830 * Reads to the PPR Log B Base Address Register.
1831 */
1832static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1833{
1834 RT_NOREF(pDevIns, offReg);
1835 *pu64Value = pThis->PprLogBBaseAddr.u64;
1836 return VINF_SUCCESS;
1837}
1838
1839
1840/**
1841 * Reads to the Event Log B Base Address Register.
1842 */
1843static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1844{
1845 RT_NOREF(pDevIns, offReg);
1846 *pu64Value = pThis->EvtLogBBaseAddr.u64;
1847 return VINF_SUCCESS;
1848}
1849
1850
1851/**
1852 * Reads the Device Table Segment Base Address Register.
1853 */
1854static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1855{
1856 RT_NOREF(pDevIns);
1857
1858 /* Figure out which segment is being written. */
1859 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1860 uint8_t const idxSegment = offSegment + 1;
1861 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1862
1863 *pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
1864 return VINF_SUCCESS;
1865}
1866
1867
1868/**
1869 * Reads the Device Specific Feature Extension (DSFX) Register.
1870 */
1871static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1872{
1873 RT_NOREF(pDevIns, offReg);
1874 *pu64Value = pThis->DevSpecificFeat.u64;
1875 return VINF_SUCCESS;
1876}
1877
1878/**
1879 * Reads the Device Specific Control Extension (DSCX) Register.
1880 */
1881static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1882{
1883 RT_NOREF(pDevIns, offReg);
1884 *pu64Value = pThis->DevSpecificCtrl.u64;
1885 return VINF_SUCCESS;
1886}
1887
1888
1889/**
1890 * Reads the Device Specific Status Extension (DSSX) Register.
1891 */
1892static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1893{
1894 RT_NOREF(pDevIns, offReg);
1895 *pu64Value = pThis->DevSpecificStatus.u64;
1896 return VINF_SUCCESS;
1897}
1898
1899
1900/**
1901 * Reads the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1902 */
1903static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1904{
1905 RT_NOREF(pDevIns, offReg);
1906 uint32_t const uLo = pThis->MiscInfo.au32[0];
1907 uint32_t const uHi = pThis->MiscInfo.au32[1];
1908 *pu64Value = RT_MAKE_U64(uLo, uHi);
1909 return VINF_SUCCESS;
1910}
1911
1912
1913/**
1914 * Reads the MSI Capability Header Register (32-bit) and the MSI Address (Lo)
1915 * Register (32-bit).
1916 */
1917static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1918{
1919 RT_NOREF(pThis, offReg);
1920 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1921 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1922 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1923 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1924 *pu64Value = RT_MAKE_U64(uLo, uHi);
1925 return VINF_SUCCESS;
1926}
1927
1928
1929/**
1930 * Reads the MSI Address (Hi) Register (32-bit) and the MSI data register (32-bit).
1931 */
1932static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1933{
1934 RT_NOREF(pThis, offReg);
1935 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1936 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1937 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1938 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1939 *pu64Value = RT_MAKE_U64(uLo, uHi);
1940 return VINF_SUCCESS;
1941}
1942
1943
1944/**
1945 * Reads the Command Buffer Head Pointer Register.
1946 */
1947static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1948{
1949 RT_NOREF(pDevIns, offReg);
1950 *pu64Value = pThis->CmdBufHeadPtr.u64;
1951 return VINF_SUCCESS;
1952}
1953
1954
1955/**
1956 * Reads the Command Buffer Tail Pointer Register.
1957 */
1958static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1959{
1960 RT_NOREF(pDevIns, offReg);
1961 *pu64Value = pThis->CmdBufTailPtr.u64;
1962 return VINF_SUCCESS;
1963}
1964
1965
1966/**
1967 * Reads the Event Log Head Pointer Register.
1968 */
1969static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1970{
1971 RT_NOREF(pDevIns, offReg);
1972 *pu64Value = pThis->EvtLogHeadPtr.u64;
1973 return VINF_SUCCESS;
1974}
1975
1976
1977/**
1978 * Reads the Event Log Tail Pointer Register.
1979 */
1980static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1981{
1982 RT_NOREF(pDevIns, offReg);
1983 *pu64Value = pThis->EvtLogTailPtr.u64;
1984 return VINF_SUCCESS;
1985}
1986
1987
1988/**
1989 * Reads the Status Register.
1990 */
1991static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1992{
1993 RT_NOREF(pDevIns, offReg);
1994 *pu64Value = pThis->Status.u64;
1995 return VINF_SUCCESS;
1996}
1997
1998
1999/**
2000 * Writes the Device Table Base Address Register.
2001 */
2002static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2003{
2004 RT_NOREF(pDevIns, offReg);
2005
2006 /* Mask out all unrecognized bits. */
2007 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
2008
2009 /* Update the register. */
2010 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
2011
2012 /* Paranoia. */
2013 Assert(pThis->aDevTabBaseAddrs[0].n.u9Size <= g_auDevTabSegMaxSizes[0]);
2014 return VINF_SUCCESS;
2015}
2016
2017
2018/**
2019 * Writes the Command Buffer Base Address Register.
2020 */
2021static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2022{
2023 RT_NOREF(pDevIns, offReg);
2024
2025 /*
2026 * While this is not explicitly specified like the event log base address register,
2027 * the AMD IOMMU spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
2028 * Inconsistent specs :/
2029 */
2030 if (pThis->Status.n.u1CmdBufRunning)
2031 {
2032 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2033 return VINF_SUCCESS;
2034 }
2035
2036 /* Mask out all unrecognized bits. */
2037 CMD_BUF_BAR_T CmdBufBaseAddr;
2038 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
2039
2040 /* Validate the length. */
2041 if (CmdBufBaseAddr.n.u4Len >= 8)
2042 {
2043 /* Update the register. */
2044 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
2045
2046 /*
2047 * Writing the command buffer base address, clears the command buffer head and tail pointers.
2048 * See AMD IOMMU spec. 2.4 "Commands".
2049 */
2050 pThis->CmdBufHeadPtr.u64 = 0;
2051 pThis->CmdBufTailPtr.u64 = 0;
2052 }
2053 else
2054 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
2055
2056 return VINF_SUCCESS;
2057}
2058
2059
2060/**
2061 * Writes the Event Log Base Address Register.
2062 */
2063static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2064{
2065 RT_NOREF(pDevIns, offReg);
2066
2067 /*
2068 * IOMMU behavior is undefined when software writes this register when event logging is running.
2069 * In our emulation, we ignore the write entirely.
2070 * See AMD IOMMU spec. "Event Log Base Address Register".
2071 */
2072 if (pThis->Status.n.u1EvtLogRunning)
2073 {
2074 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
2075 return VINF_SUCCESS;
2076 }
2077
2078 /* Mask out all unrecognized bits. */
2079 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
2080 EVT_LOG_BAR_T EvtLogBaseAddr;
2081 EvtLogBaseAddr.u64 = u64Value;
2082
2083 /* Validate the length. */
2084 if (EvtLogBaseAddr.n.u4Len >= 8)
2085 {
2086 /* Update the register. */
2087 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
2088
2089 /*
2090 * Writing the event log base address, clears the event log head and tail pointers.
2091 * See AMD IOMMU spec. 2.5 "Event Logging".
2092 */
2093 pThis->EvtLogHeadPtr.u64 = 0;
2094 pThis->EvtLogTailPtr.u64 = 0;
2095 }
2096 else
2097 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
2098
2099 return VINF_SUCCESS;
2100}
2101
2102
2103/**
2104 * Writes the Control Register.
2105 */
2106static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2107{
2108 RT_NOREF(pDevIns, offReg);
2109
2110 /* Mask out all unrecognized bits. */
2111 u64Value &= IOMMU_CTRL_VALID_MASK;
2112 IOMMU_CTRL_T NewCtrl;
2113 NewCtrl.u64 = u64Value;
2114
2115 /* Ensure the device table segments are within limits. */
2116 if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
2117 {
2118 IOMMU_CTRL_T const OldCtrl = pThis->Ctrl;
2119
2120 /* Update the register. */
2121 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
2122
2123 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
2124 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
2125
2126 /* Enable or disable event logging when the bit transitions. */
2127 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
2128 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
2129 if ( fOldEvtLogEn != fNewEvtLogEn
2130 || fOldIommuEn != fNewIommuEn)
2131 {
2132 if ( fNewIommuEn
2133 && fNewEvtLogEn)
2134 {
2135 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
2136 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
2137 }
2138 else
2139 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
2140 }
2141
2142 /* Enable or disable command buffer processing when the bit transitions. */
2143 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
2144 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
2145 if ( fOldCmdBufEn != fNewCmdBufEn
2146 || fOldIommuEn != fNewIommuEn)
2147 {
2148 if ( fNewCmdBufEn
2149 && fNewIommuEn)
2150 {
2151 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
2152 LogFunc(("Command buffer enabled\n"));
2153
2154 /* Wake up the command thread to start processing commands if any. */
2155 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2156 }
2157 else
2158 {
2159 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2160 LogFunc(("Command buffer disabled\n"));
2161 }
2162 }
2163 }
2164 else
2165 {
2166 LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
2167 pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
2168 }
2169
2170 return VINF_SUCCESS;
2171}
2172
2173
2174/**
2175 * Writes to the Exclusion Range Base Address Register.
2176 */
2177static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2178{
2179 RT_NOREF(pDevIns, offReg);
2180 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
2181 return VINF_SUCCESS;
2182}
2183
2184
2185/**
2186 * Writes to the Exclusion Range Limit Register.
2187 */
2188static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2189{
2190 RT_NOREF(pDevIns, offReg);
2191 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
2192 u64Value |= UINT64_C(0xfff);
2193 pThis->ExclRangeLimit.u64 = u64Value;
2194 return VINF_SUCCESS;
2195}
2196
2197
2198/**
2199 * Writes the Hardware Event Register (Hi).
2200 */
2201static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2202{
2203 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2204 RT_NOREF(pDevIns, offReg);
2205 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
2206 pThis->HwEvtHi.u64 = u64Value;
2207 return VINF_SUCCESS;
2208}
2209
2210
2211/**
2212 * Writes the Hardware Event Register (Lo).
2213 */
2214static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2215{
2216 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2217 RT_NOREF(pDevIns, offReg);
2218 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
2219 pThis->HwEvtLo = u64Value;
2220 return VINF_SUCCESS;
2221}
2222
2223
2224/**
2225 * Writes the Hardware Event Status Register.
2226 */
2227static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2228{
2229 RT_NOREF(pDevIns, offReg);
2230
2231 /* Mask out all unrecognized bits. */
2232 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
2233
2234 /*
2235 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
2236 * If the current status bits or the bits being written are both 0, we've nothing to do.
2237 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
2238 */
2239 uint64_t HwStatus = pThis->HwEvtStatus.u64;
2240 if (!(HwStatus & RT_BIT(0)))
2241 return VINF_SUCCESS;
2242 if (u64Value & HwStatus & RT_BIT_64(0))
2243 HwStatus &= ~RT_BIT_64(0);
2244 if (u64Value & HwStatus & RT_BIT_64(1))
2245 HwStatus &= ~RT_BIT_64(1);
2246
2247 /* Update the register. */
2248 pThis->HwEvtStatus.u64 = HwStatus;
2249 return VINF_SUCCESS;
2250}
2251
2252
2253/**
2254 * Writes the Device Table Segment Base Address Register.
2255 */
2256static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2257{
2258 RT_NOREF(pDevIns);
2259
2260 /* Figure out which segment is being written. */
2261 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
2262 uint8_t const idxSegment = offSegment + 1;
2263 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2264
2265 /* Mask out all unrecognized bits. */
2266 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
2267 DEV_TAB_BAR_T DevTabSegBar;
2268 DevTabSegBar.u64 = u64Value;
2269
2270 /* Validate the size. */
2271 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
2272 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
2273 if (uSegSize <= uMaxSegSize)
2274 {
2275 /* Update the register. */
2276 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
2277 }
2278 else
2279 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
2280
2281 return VINF_SUCCESS;
2282}
2283
2284
2285/**
2286 * Writes the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
2287 */
2288static VBOXSTRICTRC iommuAmdDevMsiVector_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2289{
2290 RT_NOREF(pDevIns, offReg);
2291
2292 /* MSI Vector Register 0 is read-only. */
2293 /* MSI Vector Register 1. */
2294 uint32_t const uReg = u64Value >> 32;
2295 pThis->MiscInfo.au32[1] = uReg & IOMMU_MSI_VECTOR_1_VALID_MASK;
2296 return VINF_SUCCESS;
2297}
2298
2299
2300/**
2301 * Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
2302 * Register (32-bit).
2303 */
2304static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2305{
2306 RT_NOREF(pThis, offReg);
2307 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2308 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2309
2310 /* MSI capability header. */
2311 {
2312 uint32_t const uReg = u64Value;
2313 MSI_CAP_HDR_T MsiCapHdr;
2314 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
2315 MsiCapHdr.n.u1MsiEnable = RT_BOOL(uReg & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
2316 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
2317 }
2318
2319 /* MSI Address Lo. */
2320 {
2321 uint32_t const uReg = u64Value >> 32;
2322 uint32_t const uMsiAddrLo = uReg & VBOX_MSI_ADDR_VALID_MASK;
2323 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
2324 }
2325
2326 return VINF_SUCCESS;
2327}
2328
2329
2330/**
2331 * Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
2332 */
2333static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2334{
2335 RT_NOREF(pThis, offReg);
2336 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2337 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2338
2339 /* MSI Address Hi. */
2340 {
2341 uint32_t const uReg = u64Value;
2342 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, uReg);
2343 }
2344
2345 /* MSI Data. */
2346 {
2347 uint32_t const uReg = u64Value >> 32;
2348 uint32_t const uMsiData = uReg & VBOX_MSI_DATA_VALID_MASK;
2349 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
2350 }
2351
2352 return VINF_SUCCESS;
2353}
2354
2355
2356/**
2357 * Writes the Command Buffer Head Pointer Register.
2358 */
2359static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2360{
2361 RT_NOREF(pDevIns, offReg);
2362
2363 /*
2364 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
2365 * In our emulation, we ignore the write entirely.
2366 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2367 */
2368 if (pThis->Status.n.u1CmdBufRunning)
2369 {
2370 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2371 return VINF_SUCCESS;
2372 }
2373
2374 /*
2375 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2376 * In our emulation, we ignore the write entirely.
2377 */
2378 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
2379 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2380 Assert(cbBuf <= _512K);
2381 if (offBuf >= cbBuf)
2382 {
2383 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
2384 return VINF_SUCCESS;
2385 }
2386
2387 /* Update the register. */
2388 pThis->CmdBufHeadPtr.au32[0] = offBuf;
2389
2390 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2391
2392 Log4Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
2393 return VINF_SUCCESS;
2394}
2395
2396
2397/**
2398 * Writes the Command Buffer Tail Pointer Register.
2399 */
2400static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2401{
2402 RT_NOREF(pDevIns, offReg);
2403
2404 /*
2405 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2406 * In our emulation, we ignore the write entirely.
2407 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2408 */
2409 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
2410 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2411 Assert(cbBuf <= _512K);
2412 if (offBuf >= cbBuf)
2413 {
2414 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2415 return VINF_SUCCESS;
2416 }
2417
2418 /*
2419 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
2420 * head pointer after adding one or more commands to the buffer.
2421 *
2422 * However, we cannot enforce this strictly because it's legal for software to shrink the
2423 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
2424 * at 0). Software might even make the queue empty by making head and tail equal which is
2425 * allowed. I don't think we can or should try too hard to prevent software shooting itself
2426 * in the foot here. As long as we make sure the offset value is within the circular buffer
2427 * bounds (which we do by masking bits above) it should be sufficient.
2428 */
2429 pThis->CmdBufTailPtr.au32[0] = offBuf;
2430
2431 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2432
2433 Log4Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
2434 return VINF_SUCCESS;
2435}
2436
2437
2438/**
2439 * Writes the Event Log Head Pointer Register.
2440 */
2441static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2442{
2443 RT_NOREF(pDevIns, offReg);
2444
2445 /*
2446 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2447 * In our emulation, we ignore the write entirely.
2448 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2449 */
2450 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
2451 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2452 Assert(cbBuf <= _512K);
2453 if (offBuf >= cbBuf)
2454 {
2455 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2456 return VINF_SUCCESS;
2457 }
2458
2459 /* Update the register. */
2460 pThis->EvtLogHeadPtr.au32[0] = offBuf;
2461
2462 Log4Func(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
2463 return VINF_SUCCESS;
2464}
2465
2466
2467/**
2468 * Writes the Event Log Tail Pointer Register.
2469 */
2470static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2471{
2472 RT_NOREF(pDevIns, offReg);
2473 NOREF(pThis);
2474
2475 /*
2476 * IOMMU behavior is undefined when software writes this register when the event log is running.
2477 * In our emulation, we ignore the write entirely.
2478 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2479 */
2480 if (pThis->Status.n.u1EvtLogRunning)
2481 {
2482 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
2483 return VINF_SUCCESS;
2484 }
2485
2486 /*
2487 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2488 * In our emulation, we ignore the write entirely.
2489 */
2490 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
2491 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2492 Assert(cbBuf <= _512K);
2493 if (offBuf >= cbBuf)
2494 {
2495 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2496 return VINF_SUCCESS;
2497 }
2498
2499 /* Update the register. */
2500 pThis->EvtLogTailPtr.au32[0] = offBuf;
2501
2502 Log4Func(("Set EvtLogTailPtr to %#RX32\n", offBuf));
2503 return VINF_SUCCESS;
2504}
2505
2506
2507/**
2508 * Writes the Status Register.
2509 */
2510static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2511{
2512 RT_NOREF(pDevIns, offReg);
2513
2514 /* Mask out all unrecognized bits. */
2515 u64Value &= IOMMU_STATUS_VALID_MASK;
2516
2517 /*
2518 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
2519 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
2520 */
2521 IOMMU_STATUS_T const OldStatus = pThis->Status;
2522 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
2523 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
2524 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
2525
2526 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
2527
2528 /* Update the register. */
2529 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
2530 return VINF_SUCCESS;
2531}
2532
2533
2534/**
2535 * Register access table 0.
2536 * The MMIO offset of each entry must be a multiple of 8!
2537 */
2538static const IOMMUREGACC g_aRegAccess0[] =
2539{
2540 /* MMIO off. Register name Read function Write function */
2541 { /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w },
2542 { /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w },
2543 { /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w },
2544 { /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w },
2545 { /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w },
2546 { /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w },
2547 { /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL },
2548 { /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL },
2549 { /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w },
2550 { /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w },
2551 { /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w },
2552 { /* 0x58 */ NULL, NULL, NULL },
2553
2554 { /* 0x60 */ "SMI_FLT_0", NULL, NULL },
2555 { /* 0x68 */ "SMI_FLT_1", NULL, NULL },
2556 { /* 0x70 */ "SMI_FLT_2", NULL, NULL },
2557 { /* 0x78 */ "SMI_FLT_3", NULL, NULL },
2558 { /* 0x80 */ "SMI_FLT_4", NULL, NULL },
2559 { /* 0x88 */ "SMI_FLT_5", NULL, NULL },
2560 { /* 0x90 */ "SMI_FLT_6", NULL, NULL },
2561 { /* 0x98 */ "SMI_FLT_7", NULL, NULL },
2562 { /* 0xa0 */ "SMI_FLT_8", NULL, NULL },
2563 { /* 0xa8 */ "SMI_FLT_9", NULL, NULL },
2564 { /* 0xb0 */ "SMI_FLT_10", NULL, NULL },
2565 { /* 0xb8 */ "SMI_FLT_11", NULL, NULL },
2566 { /* 0xc0 */ "SMI_FLT_12", NULL, NULL },
2567 { /* 0xc8 */ "SMI_FLT_13", NULL, NULL },
2568 { /* 0xd0 */ "SMI_FLT_14", NULL, NULL },
2569 { /* 0xd8 */ "SMI_FLT_15", NULL, NULL },
2570
2571 { /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL },
2572 { /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL },
2573 { /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL },
2574 { /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL },
2575
2576 { /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2577 { /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2578 { /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2579 { /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2580 { /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2581 { /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2582 { /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2583
2584 { /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL },
2585 { /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL },
2586 { /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL },
2587
2588 { /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, iommuAmdDevMsiVector_w },
2589 { /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrAndAddrLo_r, iommuAmdMsiCapHdrAndAddrLo_w },
2590 { /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiAndData_r, iommuAmdMsiAddrHiAndData_w },
2591 { /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL },
2592
2593 { /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL },
2594 { /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL },
2595 { /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL },
2596};
2597AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
2598
2599/**
2600 * Register access table 1.
2601 * The MMIO offset of each entry must be a multiple of 8!
2602 */
2603static const IOMMUREGACC g_aRegAccess1[] =
2604{
2605 /* MMIO offset Register name Read function Write function */
2606 { /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL },
2607 { /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL },
2608 { /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL },
2609 { /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL },
2610 { /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL },
2611 { /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL },
2612 { /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL },
2613 { /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL },
2614 { /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL },
2615 { /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL },
2616 { /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL },
2617 { /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL }
2618};
2619AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
2620
2621/**
2622 * Register access table 2.
2623 * The MMIO offset of each entry must be a multiple of 8!
2624 */
2625static const IOMMUREGACC g_aRegAccess2[] =
2626{
2627 /* MMIO offset Register name Read Function Write function */
2628 { /* 0x1ff8 */ "RSVD_REG", NULL, NULL },
2629
2630 { /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w },
2631 { /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w },
2632 { /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w },
2633 { /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w },
2634
2635 { /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w },
2636 { /* 0x2028 */ NULL, NULL, NULL },
2637
2638 { /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL },
2639 { /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL },
2640
2641 { /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL },
2642 { /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL },
2643
2644 { /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL },
2645 { /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL },
2646
2647 { /* 0x2060 */ NULL, NULL, NULL },
2648 { /* 0x2068 */ NULL, NULL, NULL },
2649
2650 { /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL },
2651 { /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL },
2652
2653 { /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL },
2654 { /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL },
2655 { /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL }
2656};
2657AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
2658
2659
2660/**
2661 * Gets the register access structure given its MMIO offset.
2662 *
2663 * @returns The register access structure, or NULL if the offset is invalid.
2664 * @param off The MMIO offset of the register being accessed.
2665 */
2666static PCIOMMUREGACC iommuAmdGetRegAccess(uint32_t off)
2667{
2668 /* Figure out which table the register belongs to and validate its index. */
2669 PCIOMMUREGACC pReg;
2670 if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
2671 {
2672 uint32_t const idxReg = off >> 3;
2673 Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
2674 pReg = &g_aRegAccess0[idxReg];
2675 }
2676 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
2677 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
2678 {
2679 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
2680 Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
2681 pReg = &g_aRegAccess1[idxReg];
2682 }
2683 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
2684 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
2685 {
2686 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
2687 Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
2688 pReg = &g_aRegAccess2[idxReg];
2689 }
2690 else
2691 pReg = NULL;
2692 return pReg;
2693}
2694
2695
2696/**
2697 * Writes an IOMMU register (32-bit and 64-bit).
2698 *
2699 * @returns Strict VBox status code.
2700 * @param pDevIns The IOMMU device instance.
2701 * @param off MMIO byte offset to the register.
2702 * @param cb The size of the write access.
2703 * @param uValue The value being written.
2704 *
2705 * @thread EMT.
2706 */
2707static VBOXSTRICTRC iommuAmdRegisterWrite(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
2708{
2709 /*
2710 * Validate the access in case of IOM bug or incorrect assumption.
2711 */
2712 Assert(off < IOMMU_MMIO_REGION_SIZE);
2713 AssertMsgReturn(cb == 4 || cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
2714 AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
2715
2716 Log4Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
2717
2718 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2719 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2720 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2721 if (pReg)
2722 { /* likely */ }
2723 else
2724 {
2725 LogFunc(("Writing unknown register %#x with %#RX64 -> Ignored\n", off, uValue));
2726 return VINF_SUCCESS;
2727 }
2728
2729 /* If a write handler doesn't exist, it's either a reserved or read-only register. */
2730 if (pReg->pfnWrite)
2731 { /* likely */ }
2732 else
2733 {
2734 LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2735 return VINF_SUCCESS;
2736 }
2737
2738 /*
2739 * If the write access is 64-bits and aligned on a 64-bit boundary, dispatch right away.
2740 * This handles writes to 64-bit registers as well as aligned, 64-bit writes to two
2741 * consecutive 32-bit registers.
2742 */
2743 if (cb == 8)
2744 {
2745 if (!(off & 7))
2746 {
2747 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2748 VBOXSTRICTRC rcStrict = pReg->pfnWrite(pDevIns, pThis, off, uValue);
2749 IOMMU_UNLOCK(pDevIns, pThisCC);
2750 return rcStrict;
2751 }
2752
2753 LogFunc(("Misaligned access while writing register at off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2754 return VINF_SUCCESS;
2755 }
2756
2757 /* We shouldn't get sizes other than 32 bits here as we've specified so with IOM. */
2758 Assert(cb == 4);
2759 if (!(off & 7))
2760 {
2761 VBOXSTRICTRC rcStrict;
2762 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2763
2764 /*
2765 * Lower 32 bits of a 64-bit register or a 32-bit register is being written.
2766 * Merge with higher 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2767 */
2768 uint64_t u64Read;
2769 if (pReg->pfnRead)
2770 rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
2771 else
2772 {
2773 rcStrict = VINF_SUCCESS;
2774 u64Read = 0;
2775 }
2776
2777 if (RT_SUCCESS(rcStrict))
2778 {
2779 uValue = (u64Read & UINT64_C(0xffffffff00000000)) | uValue;
2780 rcStrict = pReg->pfnWrite(pDevIns, pThis, off, uValue);
2781 }
2782 else
2783 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2784
2785 IOMMU_UNLOCK(pDevIns, pThisCC);
2786 return rcStrict;
2787 }
2788
2789 /*
2790 * Higher 32 bits of a 64-bit register or a 32-bit register at a 32-bit boundary is being written.
2791 * Merge with lower 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2792 */
2793 VBOXSTRICTRC rcStrict;
2794 Assert(!(off & 3));
2795 Assert(off & 7);
2796 Assert(off >= 4);
2797 uint64_t u64Read;
2798 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2799 if (pReg->pfnRead)
2800 rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
2801 else
2802 {
2803 rcStrict = VINF_SUCCESS;
2804 u64Read = 0;
2805 }
2806
2807 if (RT_SUCCESS(rcStrict))
2808 {
2809 uValue = (uValue << 32) | (u64Read & UINT64_C(0xffffffff));
2810 rcStrict = pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
2811 }
2812 else
2813 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2814
2815 IOMMU_UNLOCK(pDevIns, pThisCC);
2816 return rcStrict;
2817}
2818
2819
2820/**
2821 * Reads an IOMMU register (64-bit) given its MMIO offset.
2822 *
2823 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
2824 * boundary include the lower half of the subsequent register.
2825 *
2826 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
2827 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
2828 * software will only perform 32-bit reads on those 32-bit registers that are
2829 * aligned on 8-byte boundaries.
2830 *
2831 * @returns Strict VBox status code.
2832 * @param pDevIns The IOMMU device instance.
2833 * @param off The MMIO offset of the register in bytes.
2834 * @param puResult Where to store the value being read.
2835 *
2836 * @thread EMT.
2837 */
2838static VBOXSTRICTRC iommuAmdRegisterRead(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
2839{
2840 Assert(off < IOMMU_MMIO_REGION_SIZE);
2841 Assert(!(off & 7) || !(off & 3));
2842
2843 Log4Func(("off=%#x\n", off));
2844
2845 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2846 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2847 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2848 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); NOREF(pPciDev);
2849
2850 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2851 if (pReg)
2852 { /* likely */ }
2853 else
2854 {
2855 LogFunc(("Reading unknown register %#x -> Ignored\n", off));
2856 return VINF_IOM_MMIO_UNUSED_FF;
2857 }
2858
2859 /* If a read handler doesn't exist, it's a reserved or unknown register. */
2860 if (pReg->pfnRead)
2861 { /* likely */ }
2862 else
2863 {
2864 LogFunc(("Reading reserved or unknown register off=%#x -> returning 0s\n", off));
2865 return VINF_IOM_MMIO_UNUSED_00;
2866 }
2867
2868 /*
2869 * If the read access is aligned on a 64-bit boundary, read the full 64-bits and return.
2870 * The caller takes care of truncating upper 32 bits for 32-bit reads.
2871 */
2872 if (!(off & 7))
2873 {
2874 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
2875 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, puResult);
2876 IOMMU_UNLOCK(pDevIns, pThisCC);
2877 return rcStrict;
2878 }
2879
2880 /*
2881 * High 32 bits of a 64-bit register or a 32-bit register at a non 64-bit boundary is being read.
2882 * Read full 64 bits at the previous 64-bit boundary but return only the high 32 bits.
2883 */
2884 Assert(!(off & 3));
2885 Assert(off & 7);
2886 Assert(off >= 4);
2887 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
2888 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, puResult);
2889 IOMMU_UNLOCK(pDevIns, pThisCC);
2890 if (RT_SUCCESS(rcStrict))
2891 *puResult >>= 32;
2892 else
2893 {
2894 *puResult = 0;
2895 LogFunc(("Reading off %#x during split read failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2896 }
2897
2898 return rcStrict;
2899}
2900
2901
2902/**
2903 * Raises the MSI interrupt for the IOMMU device.
2904 *
2905 * @param pDevIns The IOMMU device instance.
2906 *
2907 * @thread Any.
2908 * @remarks The IOMMU lock may or may not be held.
2909 */
2910static void iommuAmdMsiInterruptRaise(PPDMDEVINS pDevIns)
2911{
2912 LogFlowFunc(("\n"));
2913 if (iommuAmdIsMsiEnabled(pDevIns))
2914 {
2915 LogFunc(("Raising MSI\n"));
2916 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
2917 }
2918}
2919
2920#if 0
2921/**
2922 * Clears the MSI interrupt for the IOMMU device.
2923 *
2924 * @param pDevIns The IOMMU device instance.
2925 *
2926 * @thread Any.
2927 * @remarks The IOMMU lock may or may not be held.
2928 */
2929static void iommuAmdMsiInterruptClear(PPDMDEVINS pDevIns)
2930{
2931 if (iommuAmdIsMsiEnabled(pDevIns))
2932 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
2933}
2934#endif
2935
2936/**
2937 * Writes an entry to the event log in memory.
2938 *
2939 * @returns VBox status code.
2940 * @param pDevIns The IOMMU device instance.
2941 * @param pEvent The event to log.
2942 *
2943 * @thread Any.
2944 * @remarks The IOMMU lock must be held while calling this function.
2945 */
2946static int iommuAmdEvtLogEntryWrite(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2947{
2948 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2949 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2950
2951 IOMMU_LOCK(pDevIns, pThisCC);
2952
2953 /* Check if event logging is active and the log has not overflowed. */
2954 IOMMU_STATUS_T const Status = pThis->Status;
2955 if ( Status.n.u1EvtLogRunning
2956 && !Status.n.u1EvtOverflow)
2957 {
2958 uint32_t const cbEvt = sizeof(*pEvent);
2959
2960 /* Get the offset we need to write the event to in memory (circular buffer offset). */
2961 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
2962 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
2963
2964 /* Ensure we have space in the event log. */
2965 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2966 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
2967 if (cEvts + 1 < cMaxEvts)
2968 {
2969 /* Write the event log entry to memory. */
2970 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
2971 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
2972 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
2973 if (RT_FAILURE(rc))
2974 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
2975
2976 /* Increment the event log tail pointer. */
2977 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2978 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
2979
2980 /* Indicate that an event log entry was written. */
2981 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
2982
2983 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
2984 if (pThis->Ctrl.n.u1EvtIntrEn)
2985 iommuAmdMsiInterruptRaise(pDevIns);
2986 }
2987 else
2988 {
2989 /* Indicate that the event log has overflowed. */
2990 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
2991
2992 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
2993 if (pThis->Ctrl.n.u1EvtIntrEn)
2994 iommuAmdMsiInterruptRaise(pDevIns);
2995 }
2996 }
2997
2998 IOMMU_UNLOCK(pDevIns, pThisCC);
2999
3000 return VINF_SUCCESS;
3001}
3002
3003
3004/**
3005 * Sets an event in the hardware error registers.
3006 *
3007 * @param pDevIns The IOMMU device instance.
3008 * @param pEvent The event.
3009 *
3010 * @thread Any.
3011 */
3012static void iommuAmdHwErrorSet(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3013{
3014 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3015 if (pThis->ExtFeat.n.u1HwErrorSup)
3016 {
3017 if (pThis->HwEvtStatus.n.u1Valid)
3018 pThis->HwEvtStatus.n.u1Overflow = 1;
3019 pThis->HwEvtStatus.n.u1Valid = 1;
3020 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
3021 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
3022 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
3023 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
3024 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
3025 }
3026}
3027
3028
3029/**
3030 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
3031 *
3032 * @param idDevice The device ID (bus, device, function).
3033 * @param idDomain The domain ID.
3034 * @param GCPhysPtEntity The system physical address of the page table
3035 * entity.
3036 * @param enmOp The IOMMU operation being performed.
3037 * @param pEvtPageTabHwErr Where to store the initialized event.
3038 */
3039static void iommuAmdPageTabHwErrorEventInit(uint16_t idDevice, uint16_t idDomain, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
3040 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3041{
3042 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
3043 pEvtPageTabHwErr->n.u16DevId = idDevice;
3044 pEvtPageTabHwErr->n.u16DomainOrPasidLo = idDomain;
3045 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
3046 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3047 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3048 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3049 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3050 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
3051 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
3052}
3053
3054
3055/**
3056 * Raises a PAGE_TAB_HARDWARE_ERROR event.
3057 *
3058 * @param pDevIns The IOMMU device instance.
3059 * @param enmOp The IOMMU operation being performed.
3060 * @param pEvtPageTabHwErr The page table hardware error event.
3061 *
3062 * @thread Any.
3063 */
3064static void iommuAmdPageTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3065{
3066 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
3067 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
3068
3069 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3070 IOMMU_LOCK(pDevIns, pThisCC);
3071
3072 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3073 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3074 if (enmOp != IOMMUOP_CMD)
3075 iommuAmdSetPciTargetAbort(pDevIns);
3076
3077 IOMMU_UNLOCK(pDevIns, pThisCC);
3078
3079 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. idDevice=%#x idDomain=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
3080 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
3081 pEvtPageTabHwErr->n.u2Type));
3082}
3083
3084
3085#ifdef IN_RING3
3086/**
3087 * Initializes a COMMAND_HARDWARE_ERROR event.
3088 *
3089 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
3090 * @param pEvtCmdHwErr Where to store the initialized event.
3091 */
3092static void iommuAmdCmdHwErrorEventInit(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3093{
3094 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
3095 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
3096 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
3097 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
3098}
3099
3100
3101/**
3102 * Raises a COMMAND_HARDWARE_ERROR event.
3103 *
3104 * @param pDevIns The IOMMU device instance.
3105 * @param pEvtCmdHwErr The command hardware error event.
3106 *
3107 * @thread Any.
3108 */
3109static void iommuAmdCmdHwErrorEventRaise(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3110{
3111 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
3112 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
3113 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3114
3115 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3116 IOMMU_LOCK(pDevIns, pThisCC);
3117
3118 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3119 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3120 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3121
3122 IOMMU_UNLOCK(pDevIns, pThisCC);
3123
3124 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
3125}
3126#endif /* IN_RING3 */
3127
3128
3129/**
3130 * Initializes a DEV_TAB_HARDWARE_ERROR event.
3131 *
3132 * @param idDevice The device ID (bus, device, function).
3133 * @param GCPhysDte The system physical address of the failed device table
3134 * access.
3135 * @param enmOp The IOMMU operation being performed.
3136 * @param pEvtDevTabHwErr Where to store the initialized event.
3137 */
3138static void iommuAmdDevTabHwErrorEventInit(uint16_t idDevice, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
3139 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3140{
3141 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
3142 pEvtDevTabHwErr->n.u16DevId = idDevice;
3143 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3144 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
3145 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3146 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3147 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3148 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
3149 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
3150}
3151
3152
3153/**
3154 * Raises a DEV_TAB_HARDWARE_ERROR event.
3155 *
3156 * @param pDevIns The IOMMU device instance.
3157 * @param enmOp The IOMMU operation being performed.
3158 * @param pEvtDevTabHwErr The device table hardware error event.
3159 *
3160 * @thread Any.
3161 */
3162static void iommuAmdDevTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3163{
3164 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
3165 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
3166
3167 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3168 IOMMU_LOCK(pDevIns, pThisCC);
3169
3170 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3171 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3172 if (enmOp != IOMMUOP_CMD)
3173 iommuAmdSetPciTargetAbort(pDevIns);
3174
3175 IOMMU_UNLOCK(pDevIns, pThisCC);
3176
3177 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. idDevice=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
3178 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
3179}
3180
3181
3182#ifdef IN_RING3
3183/**
3184 * Initializes an ILLEGAL_COMMAND_ERROR event.
3185 *
3186 * @param GCPhysCmd The system physical address of the failed command
3187 * access.
3188 * @param pEvtIllegalCmd Where to store the initialized event.
3189 */
3190static void iommuAmdIllegalCmdEventInit(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3191{
3192 Assert(!(GCPhysCmd & UINT64_C(0xf)));
3193 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
3194 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
3195 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
3196}
3197
3198
3199/**
3200 * Raises an ILLEGAL_COMMAND_ERROR event.
3201 *
3202 * @param pDevIns The IOMMU device instance.
3203 * @param pEvtIllegalCmd The illegal command error event.
3204 */
3205static void iommuAmdIllegalCmdEventRaise(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3206{
3207 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3208 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
3209 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3210
3211 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3212 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3213
3214 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
3215}
3216#endif /* IN_RING3 */
3217
3218
3219/**
3220 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
3221 *
3222 * @param idDevice The device ID (bus, device, function).
3223 * @param uIova The I/O virtual address.
3224 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
3225 * event was caused by an invalid level encoding in the
3226 * DTE.
3227 * @param enmOp The IOMMU operation being performed.
3228 * @param pEvtIllegalDte Where to store the initialized event.
3229 */
3230static void iommuAmdIllegalDteEventInit(uint16_t idDevice, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
3231 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
3232{
3233 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
3234 pEvtIllegalDte->n.u16DevId = idDevice;
3235 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3236 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3237 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
3238 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3239 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
3240 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
3241 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
3242 * IOMMU spec here but not for this field for I/O page fault event. */
3243 Assert(!(uIova & UINT64_C(0x3)));
3244}
3245
3246
3247/**
3248 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
3249 *
3250 * @param pDevIns The IOMMU instance data.
3251 * @param enmOp The IOMMU operation being performed.
3252 * @param pEvtIllegalDte The illegal device table entry event.
3253 * @param enmEvtType The illegal device table entry event type.
3254 *
3255 * @thread Any.
3256 */
3257static void iommuAmdIllegalDteEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
3258 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
3259{
3260 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3261 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
3262
3263 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3264 if (enmOp != IOMMUOP_CMD)
3265 iommuAmdSetPciTargetAbort(pDevIns);
3266
3267 LogFunc(("Raised ILLEGAL_DTE_EVENT. idDevice=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
3268 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
3269 NOREF(enmEvtType);
3270}
3271
3272
3273/**
3274 * Initializes an IO_PAGE_FAULT event.
3275 *
3276 * @param idDevice The device ID (bus, device, function).
3277 * @param idDomain The domain ID.
3278 * @param uIova The I/O virtual address being accessed.
3279 * @param fPresent Transaction to a page marked as present (including
3280 * DTE.V=1) or interrupt marked as remapped
3281 * (IRTE.RemapEn=1).
3282 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
3283 * the I/O page fault was caused by invalid level
3284 * encoding.
3285 * @param fPermDenied Permission denied for the address being accessed.
3286 * @param enmOp The IOMMU operation being performed.
3287 * @param pEvtIoPageFault Where to store the initialized event.
3288 */
3289static void iommuAmdIoPageFaultEventInit(uint16_t idDevice, uint16_t idDomain, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
3290 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
3291{
3292 Assert(!fPermDenied || fPresent);
3293 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
3294 pEvtIoPageFault->n.u16DevId = idDevice;
3295 //pEvtIoPageFault->n.u4PasidHi = 0;
3296 pEvtIoPageFault->n.u16DomainOrPasidLo = idDomain;
3297 //pEvtIoPageFault->n.u1GuestOrNested = 0;
3298 //pEvtIoPageFault->n.u1NoExecute = 0;
3299 //pEvtIoPageFault->n.u1User = 0;
3300 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3301 pEvtIoPageFault->n.u1Present = fPresent;
3302 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3303 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
3304 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
3305 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3306 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
3307 pEvtIoPageFault->n.u64Addr = uIova;
3308}
3309
3310
3311/**
3312 * Raises an IO_PAGE_FAULT event.
3313 *
3314 * @param pDevIns The IOMMU instance data.
3315 * @param fIoDevFlags The I/O device flags, see IOMMU_DTE_CACHE_F_XXX.
3316 * @param pIrte The interrupt remapping table entry, can be NULL.
3317 * @param enmOp The IOMMU operation being performed.
3318 * @param pEvtIoPageFault The I/O page fault event.
3319 * @param enmEvtType The I/O page fault event type.
3320 *
3321 * @thread Any.
3322 */
3323static void iommuAmdIoPageFaultEventRaise(PPDMDEVINS pDevIns, uint16_t fIoDevFlags, PCIRTE_T pIrte, IOMMUOP enmOp,
3324 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3325{
3326 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
3327 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
3328 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3329 STAM_COUNTER_INC(&pThis->StatIopfs); NOREF(pThis);
3330
3331#ifdef IOMMU_WITH_DTE_CACHE
3332# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) iommuAmdDteCacheUpdateFlags((a_pDevIns), (a_DevId), \
3333 IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED, \
3334 0 /* fAndMask */)
3335#else
3336# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) do { } while (0)
3337#endif
3338
3339 bool fSuppressEvtLogging = false;
3340 if ( enmOp == IOMMUOP_MEM_READ
3341 || enmOp == IOMMUOP_MEM_WRITE)
3342 {
3343 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_VALID
3344 | IOMMU_DTE_CACHE_F_SUPPRESS_IOPF | IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED;
3345 uint16_t const fSuppressAllIopf = IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
3346 if ( (fIoDevFlags & fSuppressAllIopf) == fSuppressAllIopf
3347 || (fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3348 {
3349 fSuppressEvtLogging = true;
3350 }
3351 }
3352 else if (enmOp == IOMMUOP_INTR_REQ)
3353 {
3354 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_INTR_MAP_VALID | IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
3355 if ((fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3356 fSuppressEvtLogging = true;
3357 else if (pIrte) /** @todo Make this compulsary and assert if it isn't provided. */
3358 fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
3359 }
3360 /* else: Events are never suppressed for commands. */
3361
3362 switch (enmEvtType)
3363 {
3364 case kIoPageFaultType_PermDenied:
3365 {
3366 /* Cannot be triggered by a command. */
3367 Assert(enmOp != IOMMUOP_CMD);
3368 RT_FALL_THRU();
3369 }
3370 case kIoPageFaultType_DteRsvdPagingMode:
3371 case kIoPageFaultType_PteInvalidPageSize:
3372 case kIoPageFaultType_PteInvalidLvlEncoding:
3373 case kIoPageFaultType_SkippedLevelIovaNotZero:
3374 case kIoPageFaultType_PteRsvdNotZero:
3375 case kIoPageFaultType_PteValidNotSet:
3376 case kIoPageFaultType_DteTranslationDisabled:
3377 case kIoPageFaultType_PasidInvalidRange:
3378 {
3379 /*
3380 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
3381 * create an event log entry. See AMD IOMMU spec. 2.1.3.2 "I/O Page Faults".
3382 */
3383 if (enmOp != IOMMUOP_TRANSLATE_REQ)
3384 {
3385 if (!fSuppressEvtLogging)
3386 {
3387 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3388 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3389 }
3390 if (enmOp != IOMMUOP_CMD)
3391 iommuAmdSetPciTargetAbort(pDevIns);
3392 }
3393 break;
3394 }
3395
3396 case kIoPageFaultType_UserSupervisor:
3397 {
3398 /* Access is blocked and only creates an event log entry. */
3399 if (!fSuppressEvtLogging)
3400 {
3401 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3402 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3403 }
3404 break;
3405 }
3406
3407 case kIoPageFaultType_IrteAddrInvalid:
3408 case kIoPageFaultType_IrteRsvdNotZero:
3409 case kIoPageFaultType_IrteRemapEn:
3410 case kIoPageFaultType_IrteRsvdIntType:
3411 case kIoPageFaultType_IntrReqAborted:
3412 case kIoPageFaultType_IntrWithPasid:
3413 {
3414 /* Only trigerred by interrupt requests. */
3415 Assert(enmOp == IOMMUOP_INTR_REQ);
3416 if (!fSuppressEvtLogging)
3417 {
3418 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3419 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3420 }
3421 iommuAmdSetPciTargetAbort(pDevIns);
3422 break;
3423 }
3424
3425 case kIoPageFaultType_SmiFilterMismatch:
3426 {
3427 /* Not supported and probably will never be, assert. */
3428 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
3429 break;
3430 }
3431
3432 case kIoPageFaultType_DevId_Invalid:
3433 {
3434 /* Cannot be triggered by a command. */
3435 Assert(enmOp != IOMMUOP_CMD);
3436 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
3437 if (!fSuppressEvtLogging)
3438 {
3439 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3440 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3441 }
3442 if ( enmOp == IOMMUOP_MEM_READ
3443 || enmOp == IOMMUOP_MEM_WRITE)
3444 iommuAmdSetPciTargetAbort(pDevIns);
3445 break;
3446 }
3447 }
3448
3449#undef IOMMU_DTE_CACHE_SET_PF_RAISED
3450}
3451
3452
3453/**
3454 * Raises an IO_PAGE_FAULT event given the DTE.
3455 *
3456 * @param pDevIns The IOMMU instance data.
3457 * @param pDte The device table entry.
3458 * @param pIrte The interrupt remapping table entry, can be NULL.
3459 * @param enmOp The IOMMU operation being performed.
3460 * @param pEvtIoPageFault The I/O page fault event.
3461 * @param enmEvtType The I/O page fault event type.
3462 *
3463 * @thread Any.
3464 */
3465static void iommuAmdIoPageFaultEventRaiseWithDte(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
3466 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3467{
3468 Assert(pDte);
3469 uint16_t const fIoDevFlags = iommuAmdGetBasicDevFlags(pDte);
3470 return iommuAmdIoPageFaultEventRaise(pDevIns, fIoDevFlags, pIrte, enmOp, pEvtIoPageFault, enmEvtType);
3471}
3472
3473
3474/**
3475 * Reads a device table entry for the given the device ID.
3476 *
3477 * @returns VBox status code.
3478 * @param pDevIns The IOMMU device instance.
3479 * @param idDevice The device ID (bus, device, function).
3480 * @param enmOp The IOMMU operation being performed.
3481 * @param pDte Where to store the device table entry.
3482 *
3483 * @thread Any.
3484 */
3485static int iommuAmdDteRead(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PDTE_T pDte)
3486{
3487 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3488 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3489
3490 IOMMU_LOCK(pDevIns, pThisCC);
3491
3492 /* Figure out which device table segment is being accessed. */
3493 uint8_t const idxSegsEn = pThis->Ctrl.n.u3DevTabSegEn;
3494 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
3495
3496 uint8_t const idxSeg = (idDevice & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
3497 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3498 AssertCompile(RT_ELEMENTS(g_auDevTabSegShifts) == RT_ELEMENTS(g_auDevTabSegMasks));
3499
3500 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
3501 uint32_t const offDte = (idDevice & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
3502 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
3503
3504 /* Ensure the DTE falls completely within the device table segment. */
3505 uint32_t const cbDevTabSeg = (pThis->aDevTabBaseAddrs[idxSeg].n.u9Size + 1) << X86_PAGE_4K_SHIFT;
3506
3507 IOMMU_UNLOCK(pDevIns, pThisCC);
3508
3509 if (offDte + sizeof(DTE_T) <= cbDevTabSeg)
3510 {
3511 /* Read the device table entry from guest memory. */
3512 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
3513 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
3514 if (RT_SUCCESS(rc))
3515 return VINF_SUCCESS;
3516
3517 /* Raise a device table hardware error. */
3518 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
3519
3520 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
3521 iommuAmdDevTabHwErrorEventInit(idDevice, GCPhysDte, enmOp, &EvtDevTabHwErr);
3522 iommuAmdDevTabHwErrorEventRaise(pDevIns, enmOp, &EvtDevTabHwErr);
3523 return VERR_IOMMU_DTE_READ_FAILED;
3524 }
3525
3526 /* Raise an I/O page fault for out-of-bounds acccess. */
3527 LogFunc(("Out-of-bounds device table entry. idDevice=%#x offDte=%u cbDevTabSeg=%u -> IOPF\n", idDevice, offDte, cbDevTabSeg));
3528 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3529 iommuAmdIoPageFaultEventInit(idDevice, 0 /* idDomain */, 0 /* uIova */, false /* fPresent */, false /* fRsvdNotZero */,
3530 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3531 iommuAmdIoPageFaultEventRaise(pDevIns, 0 /* fIoDevFlags */, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3532 kIoPageFaultType_DevId_Invalid);
3533 return VERR_IOMMU_DTE_BAD_OFFSET;
3534}
3535
3536
3537/**
3538 * Performs pre-translation checks for the given device table entry.
3539 *
3540 * @returns VBox status code.
3541 * @retval VINF_SUCCESS if the DTE is valid and supports address translation.
3542 * @retval VINF_IOMMU_ADDR_TRANSLATION_DISABLED if the DTE is valid but address
3543 * translation is disabled.
3544 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED if an error occurred and any
3545 * corresponding event was raised.
3546 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the DTE denies the requested
3547 * permissions.
3548 *
3549 * @param pDevIns The IOMMU device instance.
3550 * @param uIova The I/O virtual address to translate.
3551 * @param idDevice The device ID (bus, device, function).
3552 * @param fPerm The I/O permissions for this access, see
3553 * IOMMU_IO_PERM_XXX.
3554 * @param pDte The device table entry.
3555 * @param enmOp The IOMMU operation being performed.
3556 *
3557 * @thread Any.
3558 */
3559static int iommuAmdPreTranslateChecks(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, uint8_t fPerm, PCDTE_T pDte,
3560 IOMMUOP enmOp)
3561{
3562 /*
3563 * Check if the translation is valid, otherwise raise an I/O page fault.
3564 */
3565 if (pDte->n.u1TranslationValid)
3566 { /* likely */ }
3567 else
3568 {
3569 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
3570 * doesn't explicitly say whether an I/O page fault is raised. From other
3571 * places in the spec. it seems early page walk terminations (starting with
3572 * the DTE) return the state computed so far and raises an I/O page fault. So
3573 * returning an invalid translation rather than skipping translation. */
3574 LogFunc(("Translation valid bit not set -> IOPF\n"));
3575 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3576 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3577 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3578 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3579 kIoPageFaultType_DteTranslationDisabled);
3580 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3581 }
3582
3583 /*
3584 * Check permissions bits in the DTE.
3585 * Note: This MUST be checked prior to checking the root page table level below!
3586 */
3587 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3588 if ((fPerm & fDtePerm) == fPerm)
3589 { /* likely */ }
3590 else
3591 {
3592 LogFunc(("Permission denied by DTE (fPerm=%#x fDtePerm=%#x) -> IOPF\n", fPerm, fDtePerm));
3593 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3594 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3595 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3596 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3597 kIoPageFaultType_PermDenied);
3598 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3599 }
3600
3601 /*
3602 * If the root page table level is 0, translation is disabled and GPA=SPA and
3603 * the DTE.IR and DTE.IW bits control permissions (verified above).
3604 */
3605 uint8_t const uMaxLevel = pDte->n.u3Mode;
3606 if (uMaxLevel != 0)
3607 { /* likely */ }
3608 else
3609 {
3610 Assert((fPerm & fDtePerm) == fPerm); /* Verify we've checked permissions. */
3611 return VINF_IOMMU_ADDR_TRANSLATION_DISABLED;
3612 }
3613
3614 /*
3615 * If the root page table level exceeds the allowed host-address translation level,
3616 * page walk is terminated and translation fails.
3617 */
3618 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3619 { /* likely */ }
3620 else
3621 {
3622 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
3623 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
3624 * I'm just going with I/O page fault. */
3625 LogFunc(("Invalid root page table level %#x (idDevice=%#x) -> IOPF\n", uMaxLevel, idDevice));
3626 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3627 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3628 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3629 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3630 kIoPageFaultType_PteInvalidLvlEncoding);
3631 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3632 }
3633
3634 /* The DTE allows translations for this device. */
3635 return VINF_SUCCESS;
3636}
3637
3638
3639/**
3640 * Walks the I/O page table to translate the I/O virtual address to a system
3641 * physical address.
3642 *
3643 * @returns VBox status code.
3644 * @param pDevIns The IOMMU device instance.
3645 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
3646 * @param fPerm The I/O permissions for this access, see
3647 * IOMMU_IO_PERM_XXX.
3648 * @param idDevice The device ID (bus, device, function).
3649 * @param pDte The device table entry.
3650 * @param enmOp The IOMMU operation being performed.
3651 * @param pPageLookup Where to store the results of the I/O page lookup. This
3652 * is only updated when VINF_SUCCESS is returned.
3653 *
3654 * @thread Any.
3655 */
3656static int iommuAmdIoPageTableWalk(PPDMDEVINS pDevIns, uint64_t uIova, uint8_t fPerm, uint16_t idDevice, PCDTE_T pDte,
3657 IOMMUOP enmOp, PIOPAGELOOKUP pPageLookup)
3658{
3659 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3660 Assert(pDte->n.u1Valid);
3661 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
3662
3663 /* The virtual address bits indexing table. */
3664 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
3665 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
3666
3667 /*
3668 * Traverse the I/O page table starting with the page directory in the DTE.
3669 *
3670 * The Valid (Present bit), Translation Valid and Mode (Next-Level bits) in
3671 * the DTE have been validated already, see iommuAmdPreTranslateChecks.
3672 */
3673 IOPTENTITY_T PtEntity;
3674 PtEntity.u64 = pDte->au64[0];
3675 for (;;)
3676 {
3677 uint8_t const uLevel = PtEntity.n.u3NextLevel;
3678
3679 /* Read the page table entity at the current level. */
3680 {
3681 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
3682 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
3683 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
3684 uint64_t const offPte = idxPte << 3;
3685 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
3686 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
3687 if (RT_FAILURE(rc))
3688 {
3689 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
3690 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
3691 iommuAmdPageTabHwErrorEventInit(idDevice, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
3692 iommuAmdPageTabHwErrorEventRaise(pDevIns, enmOp, &EvtPageTabHwErr);
3693 return VERR_IOMMU_IPE_2;
3694 }
3695 }
3696
3697 /* Check present bit. */
3698 if (PtEntity.n.u1Present)
3699 { /* likely */ }
3700 else
3701 {
3702 LogFunc(("Page table entry not present. idDevice=%#x uIova=%#RX64 -> IOPF\n", idDevice, uIova));
3703 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3704 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3705 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3706 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3707 kIoPageFaultType_PermDenied);
3708 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3709 }
3710
3711 /* Validate the encoding of the next level. */
3712 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
3713#if IOMMU_MAX_HOST_PT_LEVEL < 6
3714 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3715 { /* likely */ }
3716 else
3717 {
3718 LogFunc(("Next-level/paging-mode field of the paging entity invalid. uNextLevel=%#x -> IOPF\n", uNextLevel));
3719 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3720 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, true /* fRsvdNotZero */,
3721 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3722 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3723 kIoPageFaultType_PteInvalidLvlEncoding);
3724 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3725 }
3726#endif
3727
3728 /* Check reserved bits. */
3729 uint64_t const fRsvdMask = uNextLevel == 0 || uNextLevel == 7 ? IOMMU_PTE_RSVD_MASK : IOMMU_PDE_RSVD_MASK;
3730 if (!(PtEntity.u64 & fRsvdMask))
3731 { /* likely */ }
3732 else
3733 {
3734 LogFunc(("Page table entity (%#RX64 level=%u) reserved bits set -> IOPF\n", PtEntity.u64, uNextLevel));
3735 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3736 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, true /* fRsvdNotZero */,
3737 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3738 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3739 kIoPageFaultType_PteRsvdNotZero);
3740 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3741 }
3742
3743 /* Check permission bits. */
3744 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3745 if ((fPerm & fPtePerm) == fPerm)
3746 { /* likely */ }
3747 else
3748 {
3749 LogFunc(("Page table entry access denied. idDevice=%#x fPerm=%#x fPtePerm=%#x -> IOPF\n", idDevice, fPerm, fPtePerm));
3750 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3751 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3752 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3753 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3754 kIoPageFaultType_PermDenied);
3755 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3756 }
3757
3758 /* If the next level is 0 or 7, this is the final level PTE. */
3759 if (uNextLevel == 0)
3760 {
3761 /* The page size of the translation is the default size for the level. */
3762 uint8_t const cShift = s_acIovaLevelShifts[uLevel];
3763 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3764 pPageLookup->GCPhysSpa = GCPhysPte & X86_GET_PAGE_BASE_MASK(cShift);
3765 pPageLookup->cShift = cShift;
3766 pPageLookup->fPerm = fPtePerm;
3767 return VINF_SUCCESS;
3768 }
3769 if (uNextLevel == 7)
3770 {
3771 /* The default page size of the translation is overridden. */
3772 uint8_t cShift = X86_PAGE_4K_SHIFT;
3773 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3774 while (GCPhysPte & RT_BIT_64(cShift++))
3775 ;
3776
3777 /* The page size must be larger than the default size and lower than the default size of the higher level. */
3778 if ( cShift > s_acIovaLevelShifts[uLevel]
3779 && cShift < s_acIovaLevelShifts[uLevel + 1])
3780 {
3781 pPageLookup->GCPhysSpa = GCPhysPte & X86_GET_PAGE_BASE_MASK(cShift);
3782 pPageLookup->cShift = cShift;
3783 pPageLookup->fPerm = fPtePerm;
3784 STAM_COUNTER_INC(&pThis->StatNonStdPageSize); NOREF(pThis);
3785 return VINF_SUCCESS;
3786 }
3787
3788 LogFunc(("Page size invalid. idDevice=%#x cShift=%u -> IOPF\n", idDevice, cShift));
3789 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3790 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3791 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3792 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3793 kIoPageFaultType_PteInvalidPageSize);
3794 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3795 }
3796
3797 /* Validate level transition. */
3798 if (uNextLevel < uLevel)
3799 { /* likely */ }
3800 else
3801 {
3802 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
3803 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3804 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3805 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3806 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3807 kIoPageFaultType_PteInvalidLvlEncoding);
3808 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3809 }
3810
3811 /* Ensure IOVA bits of skipped levels (if any) are zero. */
3812 uint64_t const fIovaSkipMask = IOMMU_GET_MAX_VALID_IOVA(uLevel - 1) - IOMMU_GET_MAX_VALID_IOVA(uNextLevel);
3813 if (!(uIova & fIovaSkipMask))
3814 { /* likely */ }
3815 else
3816 {
3817 LogFunc(("IOVA of skipped levels are not zero. uIova=%#RX64 fSkipMask=%#RX64 -> IOPF\n", uIova, fIovaSkipMask));
3818 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3819 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3820 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3821 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3822 kIoPageFaultType_SkippedLevelIovaNotZero);
3823 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3824 }
3825
3826 /* Traverse to the next level. */
3827 }
3828}
3829
3830
3831/**
3832 * Page lookup callback for finding an I/O page from guest memory.
3833 *
3834 * @returns VBox status code.
3835 * @retval VINF_SUCCESS when the page is found and has the right permissions.
3836 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED when address translation fails.
3837 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
3838 * insufficient to what is requested.
3839 *
3840 * @param pDevIns The IOMMU instance data.
3841 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
3842 * 4K aligned).
3843 * @param fPerm The I/O permissions for this access, see
3844 * IOMMU_IO_PERM_XXX.
3845 * @param pAux The auxiliary information required during lookup.
3846 * @param pPageLookup Where to store the looked up I/O page.
3847 */
3848static DECLCALLBACK(int) iommuAmdDteLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
3849 PIOPAGELOOKUP pPageLookup)
3850{
3851 AssertPtr(pAux);
3852 AssertPtr(pPageLookup);
3853 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
3854
3855 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3856 STAM_PROFILE_ADV_START(&pThis->StatProfDteLookup, a);
3857 int rc = iommuAmdIoPageTableWalk(pDevIns, uIovaPage, fPerm, pAux->idDevice, pAux->pDte, pAux->enmOp, pPageLookup);
3858 STAM_PROFILE_ADV_STOP(&pThis->StatProfDteLookup, a); NOREF(pThis);
3859 return rc;
3860}
3861
3862
3863/**
3864 * Looks up a range of I/O virtual addresses.
3865 *
3866 * @returns VBox status code.
3867 * @param pDevIns The IOMMU instance data.
3868 * @param pfnIoPageLookup The lookup function to use.
3869 * @param pAddrIn The I/O address range to lookup.
3870 * @param pAux The auxiliary information required by the lookup
3871 * function.
3872 * @param pAddrOut Where to store the translated I/O address page
3873 * lookup.
3874 * @param pcbContiguous Where to store the size of the access.
3875 */
3876static int iommuAmdLookupIoAddrRange(PPDMDEVINS pDevIns, PFNIOPAGELOOKUP pfnIoPageLookup, PCIOADDRRANGE pAddrIn,
3877 PCIOMMUOPAUX pAux, PIOPAGELOOKUP pAddrOut, size_t *pcbContiguous)
3878{
3879 int rc;
3880 size_t const cbIova = pAddrIn->cb;
3881 uint8_t const fPerm = pAddrIn->fPerm;
3882 uint64_t const uIova = pAddrIn->uAddr;
3883 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3884 size_t cbRemaining = cbIova;
3885 uint64_t uIovaPage = pAddrIn->uAddr & X86_PAGE_4K_BASE_MASK;
3886 uint64_t offIova = pAddrIn->uAddr & X86_PAGE_4K_OFFSET_MASK;
3887 size_t const cbPage = X86_PAGE_4K_SIZE;
3888
3889 IOPAGELOOKUP PageLookupPrev;
3890 RT_ZERO(PageLookupPrev);
3891 for (;;)
3892 {
3893 /* Lookup the physical page corresponding to the I/O virtual address. */
3894 IOPAGELOOKUP PageLookup;
3895 rc = pfnIoPageLookup(pDevIns, uIovaPage, fPerm, pAux, &PageLookup);
3896 if (RT_SUCCESS(rc))
3897 {
3898 /*
3899 * Validate results of the translation.
3900 */
3901 /* The IOTLB cache preserves the original page sizes even though the IOVAs are split into 4K pages. */
3902 Assert(PageLookup.cShift >= X86_PAGE_4K_SHIFT && PageLookup.cShift <= 51);
3903 Assert( pfnIoPageLookup != iommuAmdDteLookupPage
3904 || !(PageLookup.GCPhysSpa & X86_GET_PAGE_OFFSET_MASK(PageLookup.cShift)));
3905 Assert((PageLookup.fPerm & fPerm) == fPerm);
3906
3907 /* Store the translated address before continuing to access more pages. */
3908 if (cbRemaining == cbIova)
3909 {
3910 uint64_t const offSpa = uIova & X86_GET_PAGE_OFFSET_MASK(PageLookup.cShift);
3911 GCPhysSpa = PageLookup.GCPhysSpa | offSpa;
3912 }
3913 /*
3914 * Check if translated address results in a physically contiguous region.
3915 *
3916 * Also ensure that the permissions for all pages in this range are identical
3917 * because we specify a common permission while adding pages in this range
3918 * to the IOTLB cache.
3919 *
3920 * The page size must also be identical since we need to know how many offset
3921 * bits to copy into the final translated address (while retrieving 4K sized
3922 * pages from the IOTLB cache).
3923 */
3924 else if ( PageLookup.GCPhysSpa == PageLookupPrev.GCPhysSpa + cbPage
3925 && PageLookup.fPerm == PageLookupPrev.fPerm
3926 && PageLookup.cShift == PageLookupPrev.cShift)
3927 { /* likely */ }
3928 else
3929 {
3930 Assert(cbRemaining > 0);
3931 rc = VERR_OUT_OF_RANGE;
3932 break;
3933 }
3934
3935 /* Store the page lookup result from the first/previous page. */
3936 PageLookupPrev = PageLookup;
3937
3938 /* Check if we need to access more pages. */
3939 if (cbRemaining > cbPage - offIova)
3940 {
3941 cbRemaining -= (cbPage - offIova); /* Calculate how much more we need to access. */
3942 uIovaPage += cbPage; /* Update address of the next access. */
3943 offIova = 0; /* After the first page, remaining pages are accessed from offset 0. */
3944 }
3945 else
3946 {
3947 /* Caller (PDM) doesn't expect more data accessed than what was requested. */
3948 cbRemaining = 0;
3949 break;
3950 }
3951 }
3952 else
3953 break;
3954 }
3955
3956 pAddrOut->GCPhysSpa = GCPhysSpa; /* Update the translated address. */
3957 pAddrOut->cShift = PageLookupPrev.cShift; /* Update the page size of the lookup. */
3958 pAddrOut->fPerm = PageLookupPrev.fPerm; /* Update the allowed permissions for this access. */
3959 *pcbContiguous = cbIova - cbRemaining; /* Update the size of the contiguous memory region. */
3960 return rc;
3961}
3962
3963
3964/**
3965 * Looks up an I/O virtual address from the device table.
3966 *
3967 * @returns VBox status code.
3968 * @param pDevIns The IOMMU instance data.
3969 * @param idDevice The device ID (bus, device, function).
3970 * @param uIova The I/O virtual address to lookup.
3971 * @param cbIova The size of the access.
3972 * @param fPerm The I/O permissions for this access, see
3973 * IOMMU_IO_PERM_XXX.
3974 * @param enmOp The IOMMU operation being performed.
3975 * @param pGCPhysSpa Where to store the translated system physical address.
3976 * @param pcbContiguous Where to store the number of contiguous bytes translated
3977 * and permission-checked.
3978 *
3979 * @thread Any.
3980 */
3981static int iommuAmdDteLookup(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova, uint8_t fPerm, IOMMUOP enmOp,
3982 PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
3983{
3984 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3985 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3986 size_t cbContiguous = 0;
3987
3988 /* Read the device table entry from memory. */
3989 DTE_T Dte;
3990 int rc = iommuAmdDteRead(pDevIns, idDevice, enmOp, &Dte);
3991 if (RT_SUCCESS(rc))
3992 {
3993#ifdef IOMMU_WITH_IOTLBE_CACHE
3994 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte);
3995#endif
3996 if (Dte.n.u1Valid)
3997 {
3998 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
3999 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
4000 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
4001 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
4002 {
4003 /*
4004 * Check if the DTE is configured for translating addresses.
4005 * Note: Addresses cannot be subject to exclusion as we do -not- support remote IOTLBs,
4006 * so there's no need to check the address exclusion base/limit here.
4007 */
4008 rc = iommuAmdPreTranslateChecks(pDevIns, idDevice, uIova, fPerm, &Dte, enmOp);
4009 if (rc == VINF_SUCCESS)
4010 {
4011 IOADDRRANGE AddrIn;
4012 AddrIn.uAddr = uIova;
4013 AddrIn.cb = cbIova;
4014 AddrIn.fPerm = fPerm;
4015
4016 IOMMUOPAUX Aux;
4017 Aux.enmOp = enmOp;
4018 Aux.pDte = &Dte;
4019 Aux.idDevice = idDevice;
4020 Aux.idDomain = Dte.n.u16DomainId;
4021
4022 /* Lookup the address from the DTE and I/O page tables.*/
4023 IOPAGELOOKUP AddrOut;
4024 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdDteLookupPage, &AddrIn, &Aux, &AddrOut, &cbContiguous);
4025 GCPhysSpa = AddrOut.GCPhysSpa;
4026
4027 /*
4028 * If we stopped since translation resulted in non-contiguous physical addresses
4029 * or permissions aren't identical for all pages in the access, what we translated
4030 * thus far is still valid.
4031 */
4032 if (rc == VERR_OUT_OF_RANGE)
4033 {
4034 Assert(cbContiguous > 0 && cbContiguous < cbIova);
4035 rc = VINF_SUCCESS;
4036 STAM_COUNTER_INC(&pThis->StatAccessDteNonContig); NOREF(pThis);
4037 }
4038 else if (rc == VERR_IOMMU_ADDR_ACCESS_DENIED)
4039 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
4040
4041#ifdef IOMMU_WITH_IOTLBE_CACHE
4042 if (RT_SUCCESS(rc))
4043 {
4044 /* Update that addresses requires translation (cumulative permissions of DTE and I/O page tables). */
4045 iommuAmdDteCacheUpdateFlags(pDevIns, idDevice, IOMMU_DTE_CACHE_F_ADDR_TRANSLATE, 0 /* fAndMask */);
4046 /* Update IOTLB for the contiguous range of I/O virtual addresses. */
4047 iommuAmdIotlbAddRange(pDevIns, Aux.idDomain, uIova & X86_PAGE_4K_BASE_MASK, cbContiguous, &AddrOut);
4048 }
4049#endif
4050 }
4051 else if (rc == VINF_IOMMU_ADDR_TRANSLATION_DISABLED)
4052 {
4053 /*
4054 * Translation is disabled for this device (root paging mode is 0).
4055 * GPA=SPA, but the permission bits are important and controls accesses.
4056 */
4057 GCPhysSpa = uIova;
4058 cbContiguous = cbIova;
4059 rc = VINF_SUCCESS;
4060
4061#ifdef IOMMU_WITH_IOTLBE_CACHE
4062 /* Update that addresses permissions of DTE apply (but omit address translation). */
4063 iommuAmdDteCacheUpdateFlags(pDevIns, idDevice, IOMMU_DTE_CACHE_F_IO_PERM, IOMMU_DTE_CACHE_F_ADDR_TRANSLATE);
4064#endif
4065 }
4066 else
4067 {
4068 /* Address translation failed or access is denied. */
4069 Assert(rc == VERR_IOMMU_ADDR_ACCESS_DENIED || rc == VERR_IOMMU_ADDR_TRANSLATION_FAILED);
4070 GCPhysSpa = NIL_RTGCPHYS;
4071 cbContiguous = 0;
4072 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
4073 }
4074 }
4075 else
4076 {
4077 /* Invalid reserved bits in the DTE, raise an error event. */
4078 LogFunc(("Invalid DTE reserved bits (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4079 EVT_ILLEGAL_DTE_T Event;
4080 iommuAmdIllegalDteEventInit(idDevice, uIova, true /* fRsvdNotZero */, enmOp, &Event);
4081 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4082 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4083 }
4084 }
4085 else
4086 {
4087 /*
4088 * The DTE is not valid, forward addresses untranslated.
4089 * See AMD IOMMU spec. "Table 5: Feature Enablement for Address Translation".
4090 */
4091 GCPhysSpa = uIova;
4092 cbContiguous = cbIova;
4093 }
4094 }
4095 else
4096 {
4097 LogFunc(("Failed to read device table entry. idDevice=%#x rc=%Rrc\n", idDevice, rc));
4098 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4099 }
4100
4101 *pGCPhysSpa = GCPhysSpa;
4102 *pcbContiguous = cbContiguous;
4103 AssertMsg(rc != VINF_SUCCESS || cbContiguous > 0, ("cbContiguous=%zu\n", cbContiguous));
4104 return rc;
4105}
4106
4107
4108#ifdef IOMMU_WITH_IOTLBE_CACHE
4109/**
4110 * I/O page lookup callback for finding an I/O page from the IOTLB.
4111 *
4112 * @returns VBox status code.
4113 * @retval VINF_SUCCESS when the page is found and has the right permissions.
4114 * @retval VERR_NOT_FOUND when the page is not found.
4115 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
4116 * insufficient to what is requested.
4117 *
4118 * @param pDevIns The IOMMU instance data.
4119 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
4120 * 4K aligned).
4121 * @param fPerm The I/O permissions for this access, see
4122 * IOMMU_IO_PERM_XXX.
4123 * @param pAux The auxiliary information required during lookup.
4124 * @param pPageLookup Where to store the looked up I/O page.
4125 */
4126static DECLCALLBACK(int) iommuAmdCacheLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
4127 PIOPAGELOOKUP pPageLookup)
4128{
4129 Assert(pAux);
4130 Assert(pPageLookup);
4131 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
4132
4133 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4134 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4135
4136 STAM_PROFILE_ADV_START(&pThis->StatProfIotlbeLookup, a);
4137 PCIOTLBE pIotlbe = iommuAmdIotlbLookup(pThis, pThisR3, pAux->idDomain, uIovaPage);
4138 STAM_PROFILE_ADV_STOP(&pThis->StatProfIotlbeLookup, a);
4139 if (pIotlbe)
4140 {
4141 *pPageLookup = pIotlbe->PageLookup;
4142 if ((pPageLookup->fPerm & fPerm) == fPerm)
4143 {
4144 STAM_COUNTER_INC(&pThis->StatAccessCacheHit);
4145 return VINF_SUCCESS;
4146 }
4147 return VERR_IOMMU_ADDR_ACCESS_DENIED;
4148 }
4149 return VERR_NOT_FOUND;
4150}
4151
4152
4153/**
4154 * Lookups a memory access from the IOTLB cache.
4155 *
4156 * @returns VBox status code.
4157 * @retval VINF_SUCCESS if the access was cached and permissions are verified.
4158 * @retval VERR_OUT_OF_RANGE if the access resulted in a non-contiguous physical
4159 * address region.
4160 * @retval VERR_NOT_FOUND if the access was not cached.
4161 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the access was cached but permissions
4162 * are insufficient.
4163 *
4164 * @param pDevIns The IOMMU instance data.
4165 * @param idDevice The device ID (bus, device, function).
4166 * @param uIova The I/O virtual address to lookup.
4167 * @param cbIova The size of the access.
4168 * @param fPerm The I/O permissions for this access, see
4169 * IOMMU_IO_PERM_XXX.
4170 * @param enmOp The IOMMU operation being performed.
4171 * @param pGCPhysSpa Where to store the translated system physical address.
4172 * @param pcbContiguous Where to store the number of contiguous bytes translated
4173 * and permission-checked.
4174 */
4175static int iommuAmdIotlbCacheLookup(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova, uint8_t fPerm,
4176 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4177{
4178 int rc;
4179 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4180
4181#define IOMMU_IOTLB_LOOKUP_FAILED(a_rc) \
4182 do { \
4183 *pGCPhysSpa = NIL_RTGCPHYS; \
4184 *pcbContiguous = 0; \
4185 rc = (a_rc); \
4186 } while (0)
4187
4188 /*
4189 * We hold the cache lock across both the DTE and the IOTLB lookups (if any) because
4190 * we don't want the DTE cache to be invalidate while we perform IOTBL lookups.
4191 */
4192 IOMMU_CACHE_LOCK(pDevIns, pThis);
4193
4194 /* Lookup the DTE cache entry. */
4195 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, idDevice);
4196 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
4197 {
4198 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
4199 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4200 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4201 {
4202 /* Lookup IOTLB entries. */
4203 IOADDRRANGE AddrIn;
4204 AddrIn.uAddr = uIova;
4205 AddrIn.cb = cbIova;
4206 AddrIn.fPerm = fPerm;
4207
4208 IOMMUOPAUX Aux;
4209 Aux.enmOp = enmOp;
4210 Aux.pDte = NULL;
4211 Aux.idDevice = idDevice;
4212 Aux.idDomain = pDteCache->idDomain;
4213
4214 IOPAGELOOKUP AddrOut;
4215 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdCacheLookupPage, &AddrIn, &Aux, &AddrOut, pcbContiguous);
4216 *pGCPhysSpa = AddrOut.GCPhysSpa;
4217 Assert(*pcbContiguous <= cbIova);
4218 }
4219 else if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4220 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4221 {
4222 /* Address translation is disabled, but DTE permissions apply. */
4223 Assert(!(pDteCache->fFlags & IOMMU_DTE_CACHE_F_ADDR_TRANSLATE));
4224 uint8_t const fDtePerm = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_IO_PERM_SHIFT) & IOMMU_DTE_CACHE_F_IO_PERM_MASK;
4225 if ((fDtePerm & fPerm) == fPerm)
4226 {
4227 *pGCPhysSpa = uIova;
4228 *pcbContiguous = cbIova;
4229 rc = VINF_SUCCESS;
4230 }
4231 else
4232 IOMMU_IOTLB_LOOKUP_FAILED(VERR_IOMMU_ADDR_ACCESS_DENIED);
4233 }
4234 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
4235 {
4236 /* Forward addresses untranslated, without checking permissions. */
4237 *pGCPhysSpa = uIova;
4238 *pcbContiguous = cbIova;
4239 rc = VINF_SUCCESS;
4240 }
4241 else
4242 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4243 }
4244 else
4245 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4246
4247 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
4248
4249 return rc;
4250
4251#undef IOMMU_IOTLB_LOOKUP_FAILED
4252}
4253#endif /* IOMMU_WITH_IOTLBE_CACHE */
4254
4255
4256/**
4257 * Gets the I/O permission and IOMMU operation type for the given access flags.
4258 *
4259 * @param pThis The shared IOMMU device state.
4260 * @param fFlags The PDM IOMMU flags, PDMIOMMU_MEM_F_XXX.
4261 * @param penmOp Where to store the IOMMU operation.
4262 * @param pfPerm Where to store the IOMMU I/O permission.
4263 * @param fBulk Whether this is a bulk read or write.
4264 */
4265DECLINLINE(void) iommuAmdMemAccessGetPermAndOp(PIOMMU pThis, uint32_t fFlags, PIOMMUOP penmOp, uint8_t *pfPerm, bool fBulk)
4266{
4267 if (fFlags & PDMIOMMU_MEM_F_WRITE)
4268 {
4269 *penmOp = IOMMUOP_MEM_WRITE;
4270 *pfPerm = IOMMU_IO_PERM_WRITE;
4271#ifdef VBOX_WITH_STATISTICS
4272 if (!fBulk)
4273 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
4274 else
4275 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
4276#else
4277 RT_NOREF2(pThis, fBulk);
4278#endif
4279 }
4280 else
4281 {
4282 Assert(fFlags & PDMIOMMU_MEM_F_READ);
4283 *penmOp = IOMMUOP_MEM_READ;
4284 *pfPerm = IOMMU_IO_PERM_READ;
4285#ifdef VBOX_WITH_STATISTICS
4286 if (!fBulk)
4287 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
4288 else
4289 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
4290#else
4291 RT_NOREF2(pThis, fBulk);
4292#endif
4293 }
4294}
4295
4296
4297/**
4298 * Memory access transaction from a device.
4299 *
4300 * @returns VBox status code.
4301 * @param pDevIns The IOMMU device instance.
4302 * @param idDevice The device ID (bus, device, function).
4303 * @param uIova The I/O virtual address being accessed.
4304 * @param cbIova The size of the access.
4305 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4306 * @param pGCPhysSpa Where to store the translated system physical address.
4307 * @param pcbContiguous Where to store the number of contiguous bytes translated
4308 * and permission-checked.
4309 *
4310 * @thread Any.
4311 */
4312static DECLCALLBACK(int) iommuAmdMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
4313 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4314{
4315 /* Validate. */
4316 AssertPtr(pDevIns);
4317 AssertPtr(pGCPhysSpa);
4318 Assert(cbIova > 0);
4319 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4320
4321 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4322 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4323 if (Ctrl.n.u1IommuEn)
4324 {
4325 IOMMUOP enmOp;
4326 uint8_t fPerm;
4327 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, false /* fBulk */);
4328 LogFlowFunc(("%s: idDevice=%#x uIova=%#RX64 cb=%zu\n", iommuAmdMemAccessGetPermName(fPerm), idDevice, uIova, cbIova));
4329
4330 int rc;
4331#ifdef IOMMU_WITH_IOTLBE_CACHE
4332 /* Lookup the IOVA from the cache. */
4333 rc = iommuAmdIotlbCacheLookup(pDevIns, idDevice, uIova, cbIova, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4334 if (rc == VINF_SUCCESS)
4335 {
4336 /* All pages in the access were found in the cache with sufficient permissions. */
4337 Assert(*pcbContiguous == cbIova);
4338 Assert(*pGCPhysSpa != NIL_RTGCPHYS);
4339 STAM_COUNTER_INC(&pThis->StatAccessCacheHitFull);
4340 return VINF_SUCCESS;
4341 }
4342 if (rc != VERR_OUT_OF_RANGE)
4343 { /* likely */ }
4344 else
4345 {
4346 /* Access stopped since translations resulted in non-contiguous memory, let caller resume access. */
4347 Assert(*pcbContiguous > 0 && *pcbContiguous < cbIova);
4348 STAM_COUNTER_INC(&pThis->StatAccessCacheNonContig);
4349 return VINF_SUCCESS;
4350 }
4351
4352 /*
4353 * Access incomplete as not all pages were in the cache.
4354 * Or permissions were denied for the access (which typically doesn't happen)
4355 * so go through the slower path and raise the required event.
4356 */
4357 AssertMsg(*pcbContiguous < cbIova, ("Invalid size: cbContiguous=%zu cbIova=%zu\n", *pcbContiguous, cbIova));
4358 uIova += *pcbContiguous;
4359 cbIova -= *pcbContiguous;
4360 /* We currently are including any permission denied pages as cache misses too.*/
4361 STAM_COUNTER_INC(&pThis->StatAccessCacheMiss);
4362#endif
4363
4364 /* Lookup the IOVA from the device table. */
4365 rc = iommuAmdDteLookup(pDevIns, idDevice, uIova, cbIova, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4366 if (RT_SUCCESS(rc))
4367 { /* likely */ }
4368 else
4369 {
4370 Assert(rc != VERR_OUT_OF_RANGE);
4371 LogFunc(("DTE lookup failed! idDevice=%#x uIova=%#RX64 fPerm=%u cbIova=%zu rc=%#Rrc\n", idDevice, uIova, fPerm,
4372 cbIova, rc));
4373 }
4374
4375 return rc;
4376 }
4377
4378 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4379 *pGCPhysSpa = uIova;
4380 *pcbContiguous = cbIova;
4381 return VINF_SUCCESS;
4382}
4383
4384
4385/**
4386 * Memory access bulk (one or more 4K pages) request from a device.
4387 *
4388 * @returns VBox status code.
4389 * @param pDevIns The IOMMU device instance.
4390 * @param idDevice The device ID (bus, device, function).
4391 * @param cIovas The number of addresses being accessed.
4392 * @param pauIovas The I/O virtual addresses for each page being accessed.
4393 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4394 * @param paGCPhysSpa Where to store the translated physical addresses.
4395 *
4396 * @thread Any.
4397 */
4398static DECLCALLBACK(int) iommuAmdMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
4399 uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
4400{
4401 /* Validate. */
4402 AssertPtr(pDevIns);
4403 Assert(cIovas > 0);
4404 AssertPtr(pauIovas);
4405 AssertPtr(paGCPhysSpa);
4406 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4407
4408 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4409 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4410 if (Ctrl.n.u1IommuEn)
4411 {
4412 IOMMUOP enmOp;
4413 uint8_t fPerm;
4414 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, true /* fBulk */);
4415 LogFlowFunc(("%s: idDevice=%#x cIovas=%zu\n", iommuAmdMemAccessGetPermName(fPerm), idDevice, cIovas));
4416
4417 for (size_t i = 0; i < cIovas; i++)
4418 {
4419 int rc;
4420 size_t cbContig;
4421
4422#ifdef IOMMU_WITH_IOTLBE_CACHE
4423 /* Lookup the IOVA from the IOTLB cache. */
4424 rc = iommuAmdIotlbCacheLookup(pDevIns, idDevice, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i],
4425 &cbContig);
4426 if (rc == VINF_SUCCESS)
4427 {
4428 Assert(cbContig == X86_PAGE_SIZE);
4429 Assert(paGCPhysSpa[i] != NIL_RTGCPHYS);
4430 STAM_COUNTER_INC(&pThis->StatAccessCacheHitFull);
4431 continue;
4432 }
4433 Assert(rc == VERR_NOT_FOUND || rc == VERR_IOMMU_ADDR_ACCESS_DENIED);
4434 STAM_COUNTER_INC(&pThis->StatAccessCacheMiss);
4435#endif
4436
4437 /* Lookup the IOVA from the device table. */
4438 rc = iommuAmdDteLookup(pDevIns, idDevice, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i], &cbContig);
4439 if (RT_SUCCESS(rc))
4440 { /* likely */ }
4441 else
4442 {
4443 LogFunc(("Failed! idDevice=%#x uIova=%#RX64 fPerm=%u rc=%Rrc\n", idDevice, pauIovas[i], fPerm, rc));
4444 return rc;
4445 }
4446 Assert(cbContig == X86_PAGE_SIZE);
4447 }
4448 }
4449 else
4450 {
4451 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4452 for (size_t i = 0; i < cIovas; i++)
4453 paGCPhysSpa[i] = pauIovas[i];
4454 }
4455
4456 return VINF_SUCCESS;
4457}
4458
4459
4460/**
4461 * Reads an interrupt remapping table entry from guest memory given its DTE.
4462 *
4463 * @returns VBox status code.
4464 * @param pDevIns The IOMMU device instance.
4465 * @param idDevice The device ID (bus, device, function).
4466 * @param pDte The device table entry.
4467 * @param GCPhysIn The source MSI address (used for reporting errors).
4468 * @param uDataIn The source MSI data.
4469 * @param enmOp The IOMMU operation being performed.
4470 * @param pIrte Where to store the interrupt remapping table entry.
4471 *
4472 * @thread Any.
4473 */
4474static int iommuAmdIrteRead(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
4475 IOMMUOP enmOp, PIRTE_T pIrte)
4476{
4477 /* Ensure the IRTE length is valid. */
4478 Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
4479
4480 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
4481 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
4482 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(uDataIn);
4483 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
4484
4485 /* Ensure the IRTE falls completely within the interrupt table. */
4486 if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
4487 { /* likely */ }
4488 else
4489 {
4490 LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
4491 GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
4492
4493 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4494 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
4495 false /* fPermDenied */, enmOp, &EvtIoPageFault);
4496 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4497 kIoPageFaultType_IrteAddrInvalid);
4498 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4499 }
4500
4501 /* Read the IRTE from memory. */
4502 Assert(!(GCPhysIrte & 3));
4503 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
4504 if (RT_SUCCESS(rc))
4505 return VINF_SUCCESS;
4506
4507 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
4508 * situation. Is it an I/O page fault or a device table hardware error?
4509 * There's no interrupt table hardware error event, but it's unclear what
4510 * we should do here. */
4511 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
4512 return VERR_IOMMU_IPE_4;
4513}
4514
4515
4516/**
4517 * Remaps the interrupt using the interrupt remapping table.
4518 *
4519 * @returns VBox status code.
4520 * @param pDevIns The IOMMU instance data.
4521 * @param idDevice The device ID (bus, device, function).
4522 * @param pDte The device table entry.
4523 * @param enmOp The IOMMU operation being performed.
4524 * @param pMsiIn The source MSI.
4525 * @param pMsiOut Where to store the remapped MSI.
4526 *
4527 * @thread Any.
4528 */
4529static int iommuAmdIntrRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
4530 PMSIMSG pMsiOut)
4531{
4532 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
4533
4534 IRTE_T Irte;
4535 uint32_t const uMsiInData = pMsiIn->Data.u32;
4536 int rc = iommuAmdIrteRead(pDevIns, idDevice, pDte, pMsiIn->Addr.u64, uMsiInData, enmOp, &Irte);
4537 if (RT_SUCCESS(rc))
4538 {
4539 if (Irte.n.u1RemapEnable)
4540 {
4541 if (!Irte.n.u1GuestMode)
4542 {
4543 if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
4544 {
4545 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, &Irte);
4546#ifdef IOMMU_WITH_IRTE_CACHE
4547 iommuAmdIrteCacheAdd(pDevIns, idDevice, IOMMU_GET_IRTE_OFF(uMsiInData), &Irte);
4548#endif
4549 return VINF_SUCCESS;
4550 }
4551
4552 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
4553 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4554 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4555 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4556 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault,
4557 kIoPageFaultType_IrteRsvdIntType);
4558 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4559 }
4560
4561 LogFunc(("Guest mode not supported -> IOPF\n"));
4562 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4563 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4564 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4565 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
4566 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4567 }
4568
4569 LogFunc(("Remapping disabled -> IOPF\n"));
4570 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4571 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4572 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4573 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
4574 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4575 }
4576
4577 return rc;
4578}
4579
4580
4581/**
4582 * Looks up an MSI interrupt from the interrupt remapping table.
4583 *
4584 * @returns VBox status code.
4585 * @param pDevIns The IOMMU instance data.
4586 * @param idDevice The device ID (bus, device, function).
4587 * @param enmOp The IOMMU operation being performed.
4588 * @param pMsiIn The source MSI.
4589 * @param pMsiOut Where to store the remapped MSI.
4590 *
4591 * @thread Any.
4592 */
4593static int iommuAmdIntrTableLookup(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4594{
4595 LogFlowFunc(("idDevice=%#x (%#x:%#x:%#x) enmOp=%u\n", idDevice, ((idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK),
4596 ((idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK), (idDevice & VBOX_PCI_DEVFN_FUN_MASK),
4597 enmOp));
4598
4599 /* Read the device table entry from memory. */
4600 DTE_T Dte;
4601 int rc = iommuAmdDteRead(pDevIns, idDevice, enmOp, &Dte);
4602 if (RT_SUCCESS(rc))
4603 {
4604#ifdef IOMMU_WITH_IRTE_CACHE
4605 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte);
4606#endif
4607 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
4608 if (Dte.n.u1IntrMapValid)
4609 {
4610 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
4611 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
4612 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
4613 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
4614 { /* likely */ }
4615 else
4616 {
4617 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4618 EVT_ILLEGAL_DTE_T Event;
4619 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4620 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4621 return VERR_IOMMU_INTR_REMAP_FAILED;
4622 }
4623
4624 /*
4625 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
4626 * that's connected through HyperTransport it might be possible; but for us, it
4627 * doesn't seem we need to specially handle these pins.
4628 */
4629
4630 /*
4631 * Validate the MSI source address.
4632 *
4633 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
4634 * CPU is concerned, the MSI region is fixed and we must ensure no other device
4635 * claims the region as I/O space.
4636 *
4637 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
4638 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
4639 * See Intel spec. 10.11.1 "Message Address Register Format".
4640 */
4641 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
4642 {
4643 /*
4644 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
4645 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
4646 */
4647 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
4648 bool fPassThru = false;
4649 switch (u8DeliveryMode)
4650 {
4651 case VBOX_MSI_DELIVERY_MODE_FIXED:
4652 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
4653 {
4654 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
4655 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
4656 {
4657 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
4658 uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
4659 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4660 {
4661 /*
4662 * We don't support guest interrupt remapping yet. When we do, we'll need to
4663 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
4664 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
4665 * already reads the control register, add that as a parameter when we eventually
4666 * support guest interrupt remapping. For now, just assert.
4667 */
4668 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4669 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
4670 NOREF(pThis);
4671
4672 return iommuAmdIntrRemap(pDevIns, idDevice, &Dte, enmOp, pMsiIn, pMsiOut);
4673 }
4674
4675 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
4676 EVT_ILLEGAL_DTE_T Event;
4677 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
4678 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
4679 return VERR_IOMMU_INTR_REMAP_FAILED;
4680 }
4681
4682 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
4683 {
4684 fPassThru = true;
4685 break;
4686 }
4687
4688 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
4689 {
4690 LogRelMax(10, ("%s: Remapping disallowed for fixed/arbitrated interrupt %#x -> Target abort\n",
4691 IOMMU_LOG_PFX, pMsiIn->Data.n.u8Vector));
4692 iommuAmdSetPciTargetAbort(pDevIns);
4693 return VERR_IOMMU_INTR_REMAP_DENIED;
4694 }
4695
4696 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD); /* Paranoia. */
4697 LogRelMax(10, ("%s: IntCtl mode invalid %#x -> Illegal DTE\n", IOMMU_LOG_PFX, uIntrCtrl));
4698 EVT_ILLEGAL_DTE_T Event;
4699 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4700 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
4701 return VERR_IOMMU_INTR_REMAP_FAILED;
4702 }
4703
4704 /* SMIs are passed through unmapped. We don't implement SMI filters. */
4705 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
4706 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
4707 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
4708 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
4709 default:
4710 {
4711 LogRelMax(10, ("%s: MSI data delivery mode invalid %#x -> Target abort\n", IOMMU_LOG_PFX,
4712 u8DeliveryMode));
4713 iommuAmdSetPciTargetAbort(pDevIns);
4714 return VERR_IOMMU_INTR_REMAP_FAILED;
4715 }
4716 }
4717
4718 /*
4719 * For those other than fixed and arbitrated interrupts, destination mode must be 0 (physical).
4720 * See AMD IOMMU spec. The note below Table 19: "IOMMU Controls and Actions for Upstream Interrupts".
4721 */
4722 if ( u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO
4723 || !pMsiIn->Addr.n.u1DestMode)
4724 {
4725 if (fPassThru)
4726 {
4727 *pMsiOut = *pMsiIn;
4728 return VINF_SUCCESS;
4729 }
4730 LogRelMax(10, ("%s: Remapping/passthru disallowed for interrupt %#x -> Target abort\n", IOMMU_LOG_PFX,
4731 pMsiIn->Data.n.u8Vector));
4732 }
4733 else
4734 LogRelMax(10, ("%s: Logical destination mode invalid for delivery mode %#x\n -> Target abort\n",
4735 IOMMU_LOG_PFX, u8DeliveryMode));
4736
4737 iommuAmdSetPciTargetAbort(pDevIns);
4738 return VERR_IOMMU_INTR_REMAP_DENIED;
4739 }
4740 else
4741 {
4742 /** @todo should be cause a PCI target abort here? */
4743 LogRelMax(10, ("%s: MSI address region invalid %#RX64\n", IOMMU_LOG_PFX, pMsiIn->Addr.u64));
4744 return VERR_IOMMU_INTR_REMAP_FAILED;
4745 }
4746 }
4747 else
4748 {
4749 LogFlowFunc(("DTE interrupt map not valid\n"));
4750 *pMsiOut = *pMsiIn;
4751 return VINF_SUCCESS;
4752 }
4753 }
4754
4755 LogFunc(("Failed to read device table entry. idDevice=%#x rc=%Rrc\n", idDevice, rc));
4756 return VERR_IOMMU_INTR_REMAP_FAILED;
4757}
4758
4759
4760/**
4761 * Interrupt remap request from a device.
4762 *
4763 * @returns VBox status code.
4764 * @param pDevIns The IOMMU device instance.
4765 * @param idDevice The device ID (bus, device, function).
4766 * @param pMsiIn The source MSI.
4767 * @param pMsiOut Where to store the remapped MSI.
4768 */
4769static DECLCALLBACK(int) iommuAmdMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4770{
4771 /* Validate. */
4772 Assert(pDevIns);
4773 Assert(pMsiIn);
4774 Assert(pMsiOut);
4775
4776 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4777
4778 /* If this MSI was generated by the IOMMU itself, it's not subject to remapping, see @bugref{9654#c104}. */
4779 if (idDevice == pThis->uPciAddress)
4780 return VERR_IOMMU_CANNOT_CALL_SELF;
4781
4782 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
4783 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4784 if (Ctrl.n.u1IommuEn)
4785 {
4786 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
4787
4788 int rc;
4789#ifdef IOMMU_WITH_IRTE_CACHE
4790 STAM_PROFILE_ADV_START(&pThis->StatProfIrteCacheLookup, a);
4791 rc = iommuAmdIrteCacheLookup(pDevIns, idDevice, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4792 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteCacheLookup, a);
4793 if (RT_SUCCESS(rc))
4794 {
4795 STAM_COUNTER_INC(&pThis->StatIntrCacheHit);
4796 return VINF_SUCCESS;
4797 }
4798 STAM_COUNTER_INC(&pThis->StatIntrCacheMiss);
4799#endif
4800
4801 STAM_PROFILE_ADV_START(&pThis->StatProfIrteLookup, a);
4802 rc = iommuAmdIntrTableLookup(pDevIns, idDevice, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4803 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteLookup, a);
4804 return rc;
4805 }
4806
4807 *pMsiOut = *pMsiIn;
4808 return VINF_SUCCESS;
4809}
4810
4811
4812/**
4813 * @callback_method_impl{FNIOMMMIONEWWRITE}
4814 */
4815static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
4816{
4817 NOREF(pvUser);
4818 Assert(cb == 4 || cb == 8);
4819 Assert(!(off & (cb - 1)));
4820
4821 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4822 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
4823
4824 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
4825 return iommuAmdRegisterWrite(pDevIns, off, cb, uValue);
4826}
4827
4828
4829/**
4830 * @callback_method_impl{FNIOMMMIONEWREAD}
4831 */
4832static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
4833{
4834 NOREF(pvUser);
4835 Assert(cb == 4 || cb == 8);
4836 Assert(!(off & (cb - 1)));
4837
4838 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4839 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
4840
4841 uint64_t uResult;
4842 VBOXSTRICTRC rcStrict = iommuAmdRegisterRead(pDevIns, off, &uResult);
4843 if (rcStrict == VINF_SUCCESS)
4844 {
4845 if (cb == 8)
4846 *(uint64_t *)pv = uResult;
4847 else
4848 *(uint32_t *)pv = (uint32_t)uResult;
4849 }
4850
4851 return rcStrict;
4852}
4853
4854
4855#ifdef IN_RING3
4856/**
4857 * Processes an IOMMU command.
4858 *
4859 * @returns VBox status code.
4860 * @param pDevIns The IOMMU device instance.
4861 * @param pCmd The command to process.
4862 * @param GCPhysCmd The system physical address of the command.
4863 * @param pEvtError Where to store the error event in case of failures.
4864 *
4865 * @thread Command thread.
4866 */
4867static int iommuAmdR3CmdProcess(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
4868{
4869 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4870 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4871
4872 STAM_COUNTER_INC(&pThis->StatCmd);
4873
4874 uint8_t const bCmd = pCmd->n.u4Opcode;
4875 switch (bCmd)
4876 {
4877 case IOMMU_CMD_COMPLETION_WAIT:
4878 {
4879 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
4880
4881 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
4882 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
4883
4884 /* Validate reserved bits in the command. */
4885 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
4886 {
4887 /* If Completion Store is requested, write the StoreData to the specified address. */
4888 if (pCmdComWait->n.u1Store)
4889 {
4890 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
4891 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
4892 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
4893 if (RT_FAILURE(rc))
4894 {
4895 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
4896 GCPhysStore, rc));
4897 iommuAmdCmdHwErrorEventInit(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
4898 return VERR_IOMMU_CMD_HW_ERROR;
4899 }
4900 }
4901
4902 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
4903 if (pCmdComWait->n.u1Interrupt)
4904 {
4905 IOMMU_LOCK(pDevIns, pThisR3);
4906 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
4907 bool const fRaiseInt = pThis->Ctrl.n.u1CompWaitIntrEn;
4908 IOMMU_UNLOCK(pDevIns, pThisR3);
4909 if (fRaiseInt)
4910 iommuAmdMsiInterruptRaise(pDevIns);
4911 }
4912 return VINF_SUCCESS;
4913 }
4914 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4915 return VERR_IOMMU_CMD_INVALID_FORMAT;
4916 }
4917
4918 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
4919 {
4920 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
4921 PCCMD_INV_DTE_T pCmdInvDte = (PCCMD_INV_DTE_T)pCmd;
4922 AssertCompile(sizeof(*pCmdInvDte) == sizeof(*pCmd));
4923
4924 /* Validate reserved bits in the command. */
4925 if ( !(pCmdInvDte->au64[0] & ~IOMMU_CMD_INV_DTE_QWORD_0_VALID_MASK)
4926 && !(pCmdInvDte->au64[1] & ~IOMMU_CMD_INV_DTE_QWORD_1_VALID_MASK))
4927 {
4928#ifdef IOMMU_WITH_DTE_CACHE
4929 iommuAmdDteCacheRemove(pDevIns, pCmdInvDte->n.u16DevId);
4930#endif
4931 return VINF_SUCCESS;
4932 }
4933 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4934 return VERR_IOMMU_CMD_INVALID_FORMAT;
4935 }
4936
4937 case IOMMU_CMD_INV_IOMMU_PAGES:
4938 {
4939 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
4940 PCCMD_INV_IOMMU_PAGES_T pCmdInvPages = (PCCMD_INV_IOMMU_PAGES_T)pCmd;
4941 AssertCompile(sizeof(*pCmdInvPages) == sizeof(*pCmd));
4942
4943 /* Validate reserved bits in the command. */
4944 if ( !(pCmdInvPages->au64[0] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_0_VALID_MASK)
4945 && !(pCmdInvPages->au64[1] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_1_VALID_MASK))
4946 {
4947#ifdef IOMMU_WITH_IOTLBE_CACHE
4948 uint64_t const uIova = RT_MAKE_U64(pCmdInvPages->n.u20AddrLo << X86_PAGE_4K_SHIFT, pCmdInvPages->n.u32AddrHi);
4949 uint16_t const idDomain = pCmdInvPages->n.u16DomainId;
4950 uint8_t cShift;
4951 if (!pCmdInvPages->n.u1Size)
4952 cShift = X86_PAGE_4K_SHIFT;
4953 else
4954 {
4955 /* Find the first clear bit starting from bit 12 to 64 of the I/O virtual address. */
4956 unsigned const uFirstZeroBit = ASMBitLastSetU64(~(uIova >> X86_PAGE_4K_SHIFT));
4957 cShift = X86_PAGE_4K_SHIFT + uFirstZeroBit;
4958
4959 /*
4960 * For the address 0x7ffffffffffff000, cShift would be 76 (12+64) and the code below
4961 * would do the right thing by clearing the entire cache for the specified domain ID.
4962 *
4963 * However, for the address 0xfffffffffffff000, cShift would be computed as 12.
4964 * IOMMU behavior is undefined in this case, so it's safe to invalidate just one page.
4965 * A debug-time assert is in place here to let us know if any software tries this.
4966 *
4967 * See AMD IOMMU spec. 2.4.3 "INVALIDATE_IOMMU_PAGES".
4968 * See AMD IOMMU spec. Table 14: "Example Page Size Encodings".
4969 */
4970 Assert(uIova != UINT64_C(0xfffffffffffff000));
4971 }
4972
4973 /*
4974 * Validate invalidation size.
4975 * See AMD IOMMU spec. 2.2.3 "I/O Page Tables for Host Translations".
4976 */
4977 if ( cShift == 12 /* 4K */ || cShift == 13 /* 8K */
4978 || cShift == 14 /* 16K */ || cShift == 20 /* 1M */
4979 || cShift == 22 /* 4M */ || cShift == 32 /* 4G */)
4980 {
4981 /* Remove the range of I/O virtual addresses requesting to be invalidated. */
4982 size_t const cbIova = RT_BIT_64(cShift);
4983 iommuAmdIotlbRemoveRange(pDevIns, idDomain, uIova, cbIova);
4984 }
4985 else
4986 {
4987 /*
4988 * The guest provided size is invalid or exceeds the largest, meaningful page size.
4989 * In such situations we must remove all ranges for the specified domain ID.
4990 */
4991 iommuAmdIotlbRemoveDomainId(pDevIns, idDomain);
4992 }
4993#endif
4994 return VINF_SUCCESS;
4995 }
4996 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4997 return VERR_IOMMU_CMD_INVALID_FORMAT;
4998 }
4999
5000 case IOMMU_CMD_INV_IOTLB_PAGES:
5001 {
5002 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
5003
5004 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
5005 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
5006 {
5007 /** @todo IOMMU: Implement remote IOTLB invalidation. */
5008 return VERR_NOT_IMPLEMENTED;
5009 }
5010 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5011 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5012 }
5013
5014 case IOMMU_CMD_INV_INTR_TABLE:
5015 {
5016 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
5017
5018 PCCMD_INV_INTR_TABLE_T pCmdInvIntrTable = (PCCMD_INV_INTR_TABLE_T)pCmd;
5019 AssertCompile(sizeof(*pCmdInvIntrTable) == sizeof(*pCmd));
5020
5021 /* Validate reserved bits in the command. */
5022 if ( !(pCmdInvIntrTable->au64[0] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_0_VALID_MASK)
5023 && !(pCmdInvIntrTable->au64[1] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_1_VALID_MASK))
5024 {
5025#ifdef IOMMU_WITH_IRTE_CACHE
5026 iommuAmdIrteCacheRemove(pDevIns, pCmdInvIntrTable->u.u16DevId);
5027#endif
5028 return VINF_SUCCESS;
5029 }
5030 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5031 return VERR_IOMMU_CMD_INVALID_FORMAT;
5032 }
5033
5034 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
5035 {
5036 /* Linux doesn't use prefetching of IOMMU pages, so we don't bother for now. */
5037 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
5038 Assert(!pThis->ExtFeat.n.u1PrefetchSup);
5039 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5040 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5041 }
5042
5043 case IOMMU_CMD_COMPLETE_PPR_REQ:
5044 {
5045 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
5046
5047 /* We don't support PPR requests yet. */
5048 Assert(!pThis->ExtFeat.n.u1PprSup);
5049 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5050 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5051 }
5052
5053 case IOMMU_CMD_INV_IOMMU_ALL:
5054 {
5055 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
5056 if (pThis->ExtFeat.n.u1InvAllSup)
5057 {
5058 PCCMD_INV_IOMMU_ALL_T pCmdInvAll = (PCCMD_INV_IOMMU_ALL_T)pCmd;
5059 AssertCompile(sizeof(*pCmdInvAll) == sizeof(*pCmd));
5060
5061 /* Validate reserved bits in the command. */
5062 if ( !(pCmdInvAll->au64[0] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_0_VALID_MASK)
5063 && !(pCmdInvAll->au64[1] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_1_VALID_MASK))
5064 {
5065#ifdef IOMMU_WITH_DTE_CACHE
5066 iommuAmdDteCacheRemoveAll(pDevIns);
5067#endif
5068#ifdef IOMMU_WITH_IOTLBE_CACHE
5069 iommuAmdIotlbRemoveAll(pDevIns);
5070#endif
5071 return VINF_SUCCESS;
5072 }
5073 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5074 return VERR_IOMMU_CMD_INVALID_FORMAT;
5075 }
5076 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5077 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5078 }
5079 }
5080
5081 STAM_COUNTER_DEC(&pThis->StatCmd);
5082 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
5083 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5084 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5085}
5086
5087
5088/**
5089 * The IOMMU command thread.
5090 *
5091 * @returns VBox status code.
5092 * @param pDevIns The IOMMU device instance.
5093 * @param pThread The command thread.
5094 */
5095static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5096{
5097 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5098 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5099
5100 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
5101 return VINF_SUCCESS;
5102
5103 /*
5104 * Pre-allocate the maximum command buffer size supported by the IOMMU.
5105 * This avoid trashing the heap as well as not wasting time allocating
5106 * and freeing buffers while processing commands.
5107 */
5108 size_t const cbMaxCmdBuf = sizeof(CMD_GENERIC_T) * iommuAmdGetBufMaxEntries(15);
5109 void *pvCmds = RTMemAllocZ(cbMaxCmdBuf);
5110 AssertPtrReturn(pvCmds, VERR_NO_MEMORY);
5111
5112 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
5113 {
5114 /*
5115 * Sleep perpetually until we are woken up to process commands.
5116 */
5117 bool const fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
5118 if (!fSignaled)
5119 {
5120 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
5121 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
5122 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
5123 break;
5124 Log4Func(("Woken up with rc=%Rrc\n", rc));
5125 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
5126 }
5127
5128 /*
5129 * Fetch and process IOMMU commands.
5130 */
5131 /** @todo r=ramshankar: We currently copy all commands from guest memory into a
5132 * temporary host buffer before processing them as a batch. If we want to
5133 * save on host memory a bit, we could (once PGM has the necessary APIs)
5134 * lock the page mappings page mappings and access them directly. */
5135 IOMMU_LOCK(pDevIns, pThisR3);
5136
5137 if (pThis->Status.n.u1CmdBufRunning)
5138 {
5139 /* Get the offsets we need to read commands from memory (circular buffer offset). */
5140 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
5141 uint32_t const offTail = pThis->CmdBufTailPtr.n.off;
5142 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
5143
5144 /* Validate. */
5145 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
5146 Assert(offHead < cbCmdBuf);
5147 Assert(cbCmdBuf <= cbMaxCmdBuf);
5148
5149 if (offHead != offTail)
5150 {
5151 /* Read the entire command buffer from memory (avoids multiple PGM calls). */
5152 RTGCPHYS const GCPhysCmdBufBase = pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
5153
5154 IOMMU_UNLOCK(pDevIns, pThisR3);
5155 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmdBufBase, pvCmds, cbCmdBuf);
5156 IOMMU_LOCK(pDevIns, pThisR3);
5157
5158 if (RT_SUCCESS(rc))
5159 {
5160 /* Indicate to software we've fetched all commands from the buffer. */
5161 pThis->CmdBufHeadPtr.n.off = offTail;
5162
5163 /* Allow IOMMU to do other work while we process commands. */
5164 IOMMU_UNLOCK(pDevIns, pThisR3);
5165
5166 /* Process the fetched commands. */
5167 EVT_GENERIC_T EvtError;
5168 do
5169 {
5170 PCCMD_GENERIC_T pCmd = (PCCMD_GENERIC_T)((uintptr_t)pvCmds + offHead);
5171 rc = iommuAmdR3CmdProcess(pDevIns, pCmd, GCPhysCmdBufBase + offHead, &EvtError);
5172 if (RT_FAILURE(rc))
5173 {
5174 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
5175 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
5176 {
5177 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
5178 iommuAmdIllegalCmdEventRaise(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
5179 }
5180 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
5181 {
5182 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
5183 LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", pCmd->n.u4Opcode));
5184 iommuAmdCmdHwErrorEventRaise(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
5185 }
5186 break;
5187 }
5188
5189 /* Move to the next command in the circular buffer. */
5190 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
5191 } while (offHead != offTail);
5192 }
5193 else
5194 {
5195 LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmdBufBase, rc));
5196 EVT_CMD_HW_ERR_T EvtCmdHwErr;
5197 iommuAmdCmdHwErrorEventInit(GCPhysCmdBufBase, &EvtCmdHwErr);
5198 iommuAmdCmdHwErrorEventRaise(pDevIns, &EvtCmdHwErr);
5199
5200 IOMMU_UNLOCK(pDevIns, pThisR3);
5201 }
5202 }
5203 else
5204 IOMMU_UNLOCK(pDevIns, pThisR3);
5205 }
5206 else
5207 IOMMU_UNLOCK(pDevIns, pThisR3);
5208 }
5209
5210 RTMemFree(pvCmds);
5211 LogFlowFunc(("Command thread terminating\n"));
5212 return VINF_SUCCESS;
5213}
5214
5215
5216/**
5217 * Wakes up the command thread so it can respond to a state change.
5218 *
5219 * @returns VBox status code.
5220 * @param pDevIns The IOMMU device instance.
5221 * @param pThread The command thread.
5222 */
5223static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5224{
5225 RT_NOREF(pThread);
5226 Log4Func(("\n"));
5227 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5228 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
5229}
5230
5231
5232/**
5233 * @callback_method_impl{FNPCICONFIGREAD}
5234 */
5235static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5236 unsigned cb, uint32_t *pu32Value)
5237{
5238 /** @todo IOMMU: PCI config read stat counter. */
5239 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
5240 Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
5241 return rcStrict;
5242}
5243
5244
5245/**
5246 * Sets up the IOMMU MMIO region (usually in response to an IOMMU base address
5247 * register write).
5248 *
5249 * @returns VBox status code.
5250 * @param pDevIns The IOMMU instance data.
5251 *
5252 * @remarks Call this function only when the IOMMU BAR is enabled.
5253 */
5254static int iommuAmdR3MmioSetup(PPDMDEVINS pDevIns)
5255{
5256 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5257 Assert(pThis->IommuBar.n.u1Enable);
5258 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
5259 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
5260 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
5261 RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
5262
5263 /* If the MMIO region is already mapped at the specified address, we're done. */
5264 Assert(GCPhysMmioBase != NIL_RTGCPHYS);
5265 if (GCPhysMmioBasePrev == GCPhysMmioBase)
5266 return VINF_SUCCESS;
5267
5268 /* Unmap the previous MMIO region (which is at a different address). */
5269 if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
5270 {
5271 LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
5272 int rc = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
5273 if (RT_FAILURE(rc))
5274 {
5275 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBasePrev, rc));
5276 return rc;
5277 }
5278 }
5279
5280 /* Map the newly specified MMIO region. */
5281 LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
5282 int rc = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
5283 if (RT_FAILURE(rc))
5284 {
5285 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rc));
5286 return rc;
5287 }
5288
5289 return VINF_SUCCESS;
5290}
5291
5292
5293/**
5294 * @callback_method_impl{FNPCICONFIGWRITE}
5295 */
5296static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5297 unsigned cb, uint32_t u32Value)
5298{
5299 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5300
5301 /*
5302 * Discard writes to read-only registers that are specific to the IOMMU.
5303 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
5304 * See PCI spec. 6.1. "Configuration Space Organization".
5305 */
5306 switch (uAddress)
5307 {
5308 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
5309 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
5310 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
5311 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
5312 {
5313 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
5314 return VINF_SUCCESS;
5315 }
5316 }
5317
5318 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5319 IOMMU_LOCK(pDevIns, pThisR3);
5320
5321 VBOXSTRICTRC rcStrict;
5322 switch (uAddress)
5323 {
5324 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
5325 {
5326 if (!pThis->IommuBar.n.u1Enable)
5327 {
5328 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
5329 if (pThis->IommuBar.n.u1Enable)
5330 rcStrict = iommuAmdR3MmioSetup(pDevIns);
5331 else
5332 rcStrict = VINF_SUCCESS;
5333 }
5334 else
5335 {
5336 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
5337 rcStrict = VINF_SUCCESS;
5338 }
5339 break;
5340 }
5341
5342 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
5343 {
5344 if (!pThis->IommuBar.n.u1Enable)
5345 {
5346 AssertCompile((IOMMU_BAR_VALID_MASK >> 32) == 0xffffffff);
5347 pThis->IommuBar.au32[1] = u32Value;
5348 }
5349 else
5350 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
5351 rcStrict = VINF_SUCCESS;
5352 break;
5353 }
5354
5355 case IOMMU_PCI_OFF_MSI_CAP_HDR:
5356 {
5357 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
5358 RT_FALL_THRU();
5359 }
5360 default:
5361 {
5362 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
5363 break;
5364 }
5365 }
5366
5367 IOMMU_UNLOCK(pDevIns, pThisR3);
5368
5369 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
5370 return rcStrict;
5371}
5372
5373
5374/**
5375 * @callback_method_impl{FNDBGFHANDLERDEV}
5376 */
5377static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5378{
5379 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5380 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5381 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5382
5383 bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
5384
5385 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
5386 /* Device Table Base Addresses (all segments). */
5387 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
5388 {
5389 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
5390 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
5391 if (fVerbose)
5392 {
5393 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
5394 IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
5395 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5396 DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
5397 }
5398 }
5399 /* Command Buffer Base Address Register. */
5400 {
5401 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
5402 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
5403 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5404 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5405 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
5406 if (fVerbose)
5407 {
5408 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5409 CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
5410 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5411 cEntries, cbBuffer);
5412 }
5413 }
5414 /* Event Log Base Address Register. */
5415 {
5416 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
5417 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
5418 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5419 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5420 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
5421 if (fVerbose)
5422 {
5423 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5424 EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5425 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5426 cEntries, cbBuffer);
5427 }
5428 }
5429 /* IOMMU Control Register. */
5430 {
5431 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
5432 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
5433 if (fVerbose)
5434 {
5435 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
5436 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
5437 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
5438 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5439 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5440 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
5441 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
5442 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
5443 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
5444 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
5445 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
5446 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
5447 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
5448 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
5449 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
5450 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
5451 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
5452 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
5453 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
5454 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
5455 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
5456 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
5457 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
5458 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
5459 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
5460 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
5461 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
5462 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
5463 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
5464 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
5465 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
5466 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
5467 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
5468 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
5469 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
5470 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
5471 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
5472 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
5473 }
5474 }
5475 /* Exclusion Base Address Register. */
5476 {
5477 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
5478 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
5479 if (fVerbose)
5480 {
5481 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
5482 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
5483 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5484 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
5485 }
5486 }
5487 /* Exclusion Range Limit Register. */
5488 {
5489 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
5490 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
5491 if (fVerbose)
5492 {
5493 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n",
5494 (ExclRangeLimit.n.u40ExclRangeLimit << X86_PAGE_4K_SHIFT) | X86_PAGE_4K_OFFSET_MASK);
5495 }
5496 }
5497 /* Extended Feature Register. */
5498 {
5499 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
5500 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
5501 if (fVerbose)
5502 {
5503 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
5504 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
5505 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
5506 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
5507 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
5508 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
5509 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
5510 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
5511 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
5512 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
5513 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
5514 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
5515 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
5516 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
5517 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
5518 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
5519 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
5520 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
5521 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
5522 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
5523 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
5524 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
5525 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
5526 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
5527 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
5528 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
5529 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
5530 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
5531 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
5532 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
5533 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
5534 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
5535 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
5536 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
5537 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
5538 }
5539 }
5540 /* PPR Log Base Address Register. */
5541 {
5542 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
5543 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
5544 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5545 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5546 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
5547 if (fVerbose)
5548 {
5549 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5550 PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5551 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5552 cEntries, cbBuffer);
5553 }
5554 }
5555 /* Hardware Event (Hi) Register. */
5556 {
5557 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
5558 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
5559 if (fVerbose)
5560 {
5561 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
5562 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
5563 }
5564 }
5565 /* Hardware Event (Lo) Register. */
5566 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
5567 /* Hardware Event Status. */
5568 {
5569 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
5570 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
5571 if (fVerbose)
5572 {
5573 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
5574 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
5575 }
5576 }
5577 /* Guest Virtual-APIC Log Base Address Register. */
5578 {
5579 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
5580 uint8_t const uEncodedLen = GALogBar.n.u4Len;
5581 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5582 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5583 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
5584 if (fVerbose)
5585 {
5586 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5587 GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5588 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5589 cEntries, cbBuffer);
5590 }
5591 }
5592 /* Guest Virtual-APIC Log Tail Address Register. */
5593 {
5594 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
5595 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
5596 if (fVerbose)
5597 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
5598 }
5599 /* PPR Log B Base Address Register. */
5600 {
5601 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
5602 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
5603 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5604 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5605 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
5606 if (fVerbose)
5607 {
5608 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5609 PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5610 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5611 cEntries, cbBuffer);
5612 }
5613 }
5614 /* Event Log B Base Address Register. */
5615 {
5616 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
5617 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
5618 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5619 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5620 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
5621 if (fVerbose)
5622 {
5623 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5624 EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5625 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5626 cEntries, cbBuffer);
5627 }
5628 }
5629 /* Device-Specific Feature Extension Register. */
5630 {
5631 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
5632 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
5633 if (fVerbose)
5634 {
5635 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
5636 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
5637 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
5638 }
5639 }
5640 /* Device-Specific Control Extension Register. */
5641 {
5642 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
5643 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
5644 if (fVerbose)
5645 {
5646 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
5647 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
5648 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
5649 }
5650 }
5651 /* Device-Specific Status Extension Register. */
5652 {
5653 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
5654 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
5655 if (fVerbose)
5656 {
5657 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
5658 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
5659 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
5660 }
5661 }
5662 /* Miscellaneous Information Register (Lo and Hi). */
5663 {
5664 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
5665 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
5666 if (fVerbose)
5667 {
5668 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
5669 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
5670 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
5671 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
5672 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
5673 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
5674 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
5675 }
5676 }
5677 /* MSI Capability Header. */
5678 {
5679 MSI_CAP_HDR_T MsiCapHdr;
5680 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
5681 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
5682 if (fVerbose)
5683 {
5684 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
5685 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
5686 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
5687 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
5688 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
5689 }
5690 }
5691 /* MSI Address Register (Lo and Hi). */
5692 {
5693 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
5694 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
5695 MSIADDR MsiAddr;
5696 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
5697 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
5698 if (fVerbose)
5699 {
5700 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
5701 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
5702 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
5703 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
5704 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
5705 }
5706 }
5707 /* MSI Data. */
5708 {
5709 MSIDATA MsiData;
5710 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
5711 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
5712 if (fVerbose)
5713 {
5714 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
5715 MsiData.n.u8Vector);
5716 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
5717 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
5718 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
5719 "level" : "edge");
5720 }
5721 }
5722 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
5723 {
5724 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
5725 MsiMapCapHdr.u32 = 0;
5726 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
5727 if (fVerbose)
5728 {
5729 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
5730 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
5731 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
5732 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
5733 }
5734 }
5735 /* Performance Optimization Control Register. */
5736 {
5737 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
5738 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
5739 if (fVerbose)
5740 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
5741 }
5742 /* XT (x2APIC) General Interrupt Control Register. */
5743 {
5744 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
5745 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
5746 if (fVerbose)
5747 {
5748 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5749 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5750 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5751 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
5752 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
5753 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5754 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5755 }
5756 }
5757 /* XT (x2APIC) PPR Interrupt Control Register. */
5758 {
5759 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
5760 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
5761 if (fVerbose)
5762 {
5763 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5764 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5765 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5766 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
5767 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
5768 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5769 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5770 }
5771 }
5772 /* XT (X2APIC) GA Log Interrupt Control Register. */
5773 {
5774 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
5775 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
5776 if (fVerbose)
5777 {
5778 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5779 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5780 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5781 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
5782 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
5783 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5784 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5785 }
5786 }
5787 /* MARC Registers. */
5788 {
5789 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
5790 {
5791 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
5792 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
5793 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
5794
5795 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
5796 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
5797 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
5798 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
5799
5800 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
5801 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
5802 }
5803 }
5804 /* Reserved Register. */
5805 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
5806 /* Command Buffer Head Pointer Register. */
5807 {
5808 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
5809 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
5810 CmdBufHeadPtr.n.off);
5811 }
5812 /* Command Buffer Tail Pointer Register. */
5813 {
5814 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
5815 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
5816 CmdBufTailPtr.n.off);
5817 }
5818 /* Event Log Head Pointer Register. */
5819 {
5820 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
5821 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
5822 EvtLogHeadPtr.n.off);
5823 }
5824 /* Event Log Tail Pointer Register. */
5825 {
5826 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
5827 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
5828 EvtLogTailPtr.n.off);
5829 }
5830 /* Status Register. */
5831 {
5832 IOMMU_STATUS_T const Status = pThis->Status;
5833 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
5834 if (fVerbose)
5835 {
5836 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
5837 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
5838 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
5839 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
5840 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
5841 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
5842 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
5843 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
5844 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
5845 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
5846 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
5847 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
5848 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
5849 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
5850 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
5851 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
5852 }
5853 }
5854 /* PPR Log Head Pointer. */
5855 {
5856 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
5857 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
5858 PprLogHeadPtr.n.off);
5859 }
5860 /* PPR Log Tail Pointer. */
5861 {
5862 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
5863 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
5864 PprLogTailPtr.n.off);
5865 }
5866 /* Guest Virtual-APIC Log Head Pointer. */
5867 {
5868 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
5869 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
5870 GALogHeadPtr.n.u12GALogPtr);
5871 }
5872 /* Guest Virtual-APIC Log Tail Pointer. */
5873 {
5874 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
5875 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
5876 GALogTailPtr.n.u12GALogPtr);
5877 }
5878 /* PPR Log B Head Pointer. */
5879 {
5880 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
5881 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
5882 PprLogBHeadPtr.n.off);
5883 }
5884 /* PPR Log B Tail Pointer. */
5885 {
5886 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
5887 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
5888 PprLogBTailPtr.n.off);
5889 }
5890 /* Event Log B Head Pointer. */
5891 {
5892 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
5893 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
5894 EvtLogBHeadPtr.n.off);
5895 }
5896 /* Event Log B Tail Pointer. */
5897 {
5898 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
5899 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
5900 EvtLogBTailPtr.n.off);
5901 }
5902 /* PPR Log Auto Response Register. */
5903 {
5904 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
5905 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
5906 if (fVerbose)
5907 {
5908 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
5909 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
5910 }
5911 }
5912 /* PPR Log Overflow Early Warning Indicator Register. */
5913 {
5914 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
5915 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
5916 if (fVerbose)
5917 {
5918 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
5919 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
5920 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
5921 }
5922 }
5923 /* PPR Log Overflow Early Warning Indicator Register. */
5924 {
5925 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
5926 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
5927 if (fVerbose)
5928 {
5929 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
5930 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
5931 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
5932 }
5933 }
5934}
5935
5936
5937/**
5938 * Dumps the DTE via the info callback helper.
5939 *
5940 * @param pHlp The info helper.
5941 * @param pDte The device table entry.
5942 * @param pszPrefix The string prefix.
5943 */
5944static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
5945{
5946 AssertReturnVoid(pHlp);
5947 AssertReturnVoid(pDte);
5948 AssertReturnVoid(pszPrefix);
5949
5950 pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
5951 pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
5952 pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
5953 pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
5954 pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
5955 pDte->n.u40PageTableRootPtrLo << 12);
5956 pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
5957 pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
5958 pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
5959 pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
5960 pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
5961 pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
5962 pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
5963 (pDte->n.u21GstCr3TableRootPtrHi << 31)
5964 | (pDte->n.u16GstCr3TableRootPtrMid << 15)
5965 | (pDte->n.u3GstCr3TableRootPtrLo << 12));
5966 pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
5967 pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
5968 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
5969 pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
5970 pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
5971 pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
5972 pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
5973 pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
5974 pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
5975 pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
5976 pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
5977 pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
5978 pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
5979 uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
5980 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
5981 {
5982 uint16_t const cEntries = IOMMU_DTE_GET_INTR_TAB_ENTRIES(pDte);
5983 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
5984 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
5985 cbIntrTable);
5986 }
5987 else
5988 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
5989 pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
5990 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
5991 pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
5992 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
5993 pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
5994 pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
5995 pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
5996 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
5997 pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
5998 pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
5999 pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
6000 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
6001 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
6002 pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
6003 pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
6004 pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
6005 pHlp->pfnPrintf(pHlp, "\n");
6006}
6007
6008
6009/**
6010 * @callback_method_impl{FNDBGFHANDLERDEV}
6011 */
6012static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6013{
6014 if (pszArgs)
6015 {
6016 uint16_t idDevice = 0;
6017 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &idDevice);
6018 if (RT_SUCCESS(rc))
6019 {
6020 DTE_T Dte;
6021 rc = iommuAmdDteRead(pDevIns, idDevice, IOMMUOP_TRANSLATE_REQ, &Dte);
6022 if (RT_SUCCESS(rc))
6023 {
6024 pHlp->pfnPrintf(pHlp, "DTE for device %#x\n", idDevice);
6025 iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
6026 return;
6027 }
6028 pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", idDevice, idDevice, rc);
6029 }
6030 else
6031 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
6032 }
6033 else
6034 pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
6035}
6036
6037
6038# ifdef IOMMU_WITH_DTE_CACHE
6039/**
6040 * @callback_method_impl{FNDBGFHANDLERDEV}
6041 */
6042static DECLCALLBACK(void) iommuAmdR3DbgInfoDteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6043{
6044 RT_NOREF(pszArgs);
6045 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6046 IOMMU_CACHE_LOCK(pDevIns, pThis);
6047
6048 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDeviceIds);
6049 pHlp->pfnPrintf(pHlp, "DTE Cache: Capacity=%u entries\n", cDteCache);
6050 for (uint16_t i = 0; i < cDteCache; i++)
6051 {
6052 uint16_t const idDevice = pThis->aDeviceIds[i];
6053 if (idDevice)
6054 {
6055 pHlp->pfnPrintf(pHlp, " Entry[%u]: Device=%#x (BDF %02x:%02x.%d)\n", i, idDevice,
6056 (idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6057 (idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6058 idDevice & VBOX_PCI_DEVFN_FUN_MASK);
6059
6060 PCDTECACHE pDteCache = &pThis->aDteCache[i];
6061 pHlp->pfnPrintf(pHlp, " Flags = %#x\n", pDteCache->fFlags);
6062 pHlp->pfnPrintf(pHlp, " Domain Id = %u\n", pDteCache->idDomain);
6063 pHlp->pfnPrintf(pHlp, "\n");
6064 }
6065 }
6066 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
6067}
6068# endif /* IOMMU_WITH_DTE_CACHE */
6069
6070
6071# ifdef IOMMU_WITH_IOTLBE_CACHE
6072/**
6073 * @callback_method_impl{FNDBGFHANDLERDEV}
6074 */
6075static DECLCALLBACK(void) iommuAmdR3DbgInfoIotlb(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6076{
6077 if (pszArgs)
6078 {
6079 uint16_t idDomain = 0;
6080 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &idDomain);
6081 if (RT_SUCCESS(rc))
6082 {
6083 pHlp->pfnPrintf(pHlp, "IOTLBEs for domain %u (%#x):\n", idDomain, idDomain);
6084 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6085 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6086 IOTLBEINFOARG Args;
6087 Args.pIommuR3 = pThisR3;
6088 Args.pHlp = pHlp;
6089 Args.idDomain = idDomain;
6090
6091 IOMMU_CACHE_LOCK(pDevIns, pThis);
6092 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdR3IotlbEntryInfo, &Args);
6093 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
6094 }
6095 else
6096 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit domain ID. rc=%Rrc\n", rc);
6097 }
6098 else
6099 pHlp->pfnPrintf(pHlp, "Missing domain ID.\n");
6100}
6101# endif /* IOMMU_WITH_IOTLBE_CACHE */
6102
6103
6104# ifdef IOMMU_WITH_IRTE_CACHE
6105/**
6106 * Gets the interrupt type name for an interrupt type in the IRTE.
6107 *
6108 * @returns The interrupt type name.
6109 * @param uIntrType The interrupt type (as specified in the IRTE).
6110 */
6111static const char *iommuAmdIrteGetIntrTypeName(uint8_t uIntrType)
6112{
6113 switch (uIntrType)
6114 {
6115 case VBOX_MSI_DELIVERY_MODE_FIXED: return "Fixed";
6116 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO: return "Arbitrated";
6117 default: return "<Reserved>";
6118 }
6119}
6120
6121
6122/**
6123 * @callback_method_impl{FNDBGFHANDLERDEV}
6124 */
6125static DECLCALLBACK(void) iommuAmdR3DbgInfoIrteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6126{
6127 RT_NOREF(pszArgs);
6128
6129 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6130 IOMMU_CACHE_LOCK(pDevIns, pThis);
6131
6132 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
6133 pHlp->pfnPrintf(pHlp, "IRTE Cache: Capacity=%u entries\n", cIrteCache);
6134 for (uint16_t idxIrte = 0; idxIrte < cIrteCache; idxIrte++)
6135 {
6136 PCIRTECACHE pIrteCache = &pThis->aIrteCache[idxIrte];
6137 uint32_t const uKey = pIrteCache->uKey;
6138 if (uKey != IOMMU_IRTE_CACHE_KEY_NIL)
6139 {
6140 uint16_t const idDevice = IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(uKey);
6141 uint16_t const offIrte = IOMMU_IRTE_CACHE_KEY_GET_OFF(uKey);
6142 pHlp->pfnPrintf(pHlp, " Entry[%u]: Offset=%#x Device=%#x (BDF %02x:%02x.%d)\n",
6143 idxIrte, offIrte, idDevice,
6144 (idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6145 (idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6146 idDevice & VBOX_PCI_DEVFN_FUN_MASK);
6147
6148 PCIRTE_T pIrte = &pIrteCache->Irte;
6149 pHlp->pfnPrintf(pHlp, " Remap Enable = %RTbool\n", pIrte->n.u1RemapEnable);
6150 pHlp->pfnPrintf(pHlp, " Suppress IOPF = %RTbool\n", pIrte->n.u1SuppressIoPf);
6151 pHlp->pfnPrintf(pHlp, " Interrupt Type = %#x (%s)\n", pIrte->n.u3IntrType,
6152 iommuAmdIrteGetIntrTypeName(pIrte->n.u3IntrType));
6153 pHlp->pfnPrintf(pHlp, " Request EOI = %RTbool\n", pIrte->n.u1ReqEoi);
6154 pHlp->pfnPrintf(pHlp, " Destination mode = %s\n", pIrte->n.u1DestMode ? "Logical" : "Physical");
6155 pHlp->pfnPrintf(pHlp, " Destination Id = %u\n", pIrte->n.u8Dest);
6156 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", pIrte->n.u8Vector, pIrte->n.u8Vector);
6157 pHlp->pfnPrintf(pHlp, "\n");
6158 }
6159 }
6160 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
6161}
6162# endif /* IOMMU_WITH_IRTE_CACHE */
6163
6164
6165/**
6166 * @callback_method_impl{FNDBGFHANDLERDEV}
6167 */
6168static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6169{
6170 RT_NOREF(pszArgs);
6171
6172 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6173 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6174 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6175 NOREF(pPciDev);
6176
6177 uint8_t cSegments = 0;
6178 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6179 {
6180 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6181 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6182 if (GCPhysDevTab)
6183 ++cSegments;
6184 }
6185
6186 pHlp->pfnPrintf(pHlp, "AMD-IOMMU device tables with address translations enabled:\n");
6187 pHlp->pfnPrintf(pHlp, " DTE Segments=%u\n", cSegments);
6188 if (!cSegments)
6189 return;
6190
6191 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6192 {
6193 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6194 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6195 if (GCPhysDevTab)
6196 {
6197 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
6198 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
6199
6200 void *pvDevTab = RTMemAllocZ(cbDevTab);
6201 if (RT_LIKELY(pvDevTab))
6202 {
6203 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
6204 if (RT_SUCCESS(rc))
6205 {
6206 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
6207 {
6208 PCDTE_T pDte = (PCDTE_T)((uintptr_t)pvDevTab + idxDte * sizeof(DTE_T));
6209 if ( pDte->n.u1Valid
6210 && pDte->n.u1TranslationValid
6211 && pDte->n.u3Mode != 0)
6212 {
6213 pHlp->pfnPrintf(pHlp, " DTE %u (BDF %02x:%02x.%d)\n", idxDte,
6214 (idxDte >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6215 (idxDte >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6216 idxDte & VBOX_PCI_DEVFN_FUN_MASK);
6217 iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
6218 pHlp->pfnPrintf(pHlp, "\n");
6219 }
6220 }
6221 pHlp->pfnPrintf(pHlp, "\n");
6222 }
6223 else
6224 {
6225 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %zu bytes. rc=%Rrc!\n", GCPhysDevTab,
6226 cbDevTab, rc);
6227 }
6228
6229 RTMemFree(pvDevTab);
6230 }
6231 else
6232 {
6233 pHlp->pfnPrintf(pHlp, " Allocating %zu bytes for reading the device table failed!\n", cbDevTab);
6234 return;
6235 }
6236 }
6237 }
6238}
6239
6240
6241/**
6242 * @callback_method_impl{FNSSMDEVSAVEEXEC}
6243 */
6244static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6245{
6246 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6247 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6248 LogFlowFunc(("\n"));
6249
6250 /* First, save ExtFeat and other registers that cannot be modified by the guest. */
6251 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64);
6252 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64);
6253 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64);
6254 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64);
6255 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64);
6256 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg);
6257
6258 /* Next, save all registers that can be modified by the guest. */
6259 pHlp->pfnSSMPutU64(pSSM, pThis->IommuBar.u64);
6260
6261 uint8_t const cDevTabBaseAddrs = RT_ELEMENTS(pThis->aDevTabBaseAddrs);
6262 pHlp->pfnSSMPutU8(pSSM, cDevTabBaseAddrs);
6263 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6264 pHlp->pfnSSMPutU64(pSSM, pThis->aDevTabBaseAddrs[i].u64);
6265
6266 AssertReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8, VERR_IOMMU_IPE_4);
6267 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufBaseAddr.u64);
6268 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBaseAddr.u64);
6269 pHlp->pfnSSMPutU64(pSSM, pThis->Ctrl.u64);
6270 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeBaseAddr.u64);
6271 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeLimit.u64);
6272#if 0
6273 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64); /* read-only, done already (above). */
6274#endif
6275
6276 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBaseAddr.u64);
6277 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtHi.u64);
6278 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtLo);
6279 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtStatus.u64);
6280
6281 pHlp->pfnSSMPutU64(pSSM, pThis->GALogBaseAddr.u64);
6282 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailAddr.u64);
6283
6284 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBBaseAddr.u64);
6285 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBBaseAddr.u64);
6286
6287#if 0
6288 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6289 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6290 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6291
6292 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64); /* read-only, done already (above). */
6293#endif
6294 pHlp->pfnSSMPutU32(pSSM, pThis->PerfOptCtrl.u32);
6295
6296 pHlp->pfnSSMPutU64(pSSM, pThis->XtGenIntrCtrl.u64);
6297 pHlp->pfnSSMPutU64(pSSM, pThis->XtPprIntrCtrl.u64);
6298 pHlp->pfnSSMPutU64(pSSM, pThis->XtGALogIntrCtrl.u64);
6299
6300 size_t const cMarcApers = RT_ELEMENTS(pThis->aMarcApers);
6301 pHlp->pfnSSMPutU8(pSSM, cMarcApers);
6302 for (size_t i = 0; i < cMarcApers; i++)
6303 {
6304 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Base.u64);
6305 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Reloc.u64);
6306 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Length.u64);
6307 }
6308
6309#if 0
6310 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg); /* read-only, done already (above). */
6311#endif
6312
6313 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufHeadPtr.u64);
6314 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufTailPtr.u64);
6315 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogHeadPtr.u64);
6316 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogTailPtr.u64);
6317
6318 pHlp->pfnSSMPutU64(pSSM, pThis->Status.u64);
6319
6320 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogHeadPtr.u64);
6321 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogTailPtr.u64);
6322
6323 pHlp->pfnSSMPutU64(pSSM, pThis->GALogHeadPtr.u64);
6324 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailPtr.u64);
6325
6326 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBHeadPtr.u64);
6327 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBTailPtr.u64);
6328
6329 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBHeadPtr.u64);
6330 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBTailPtr.u64);
6331
6332 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogAutoResp.u64);
6333 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogOverflowEarly.u64);
6334 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBOverflowEarly.u64);
6335
6336 return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
6337}
6338
6339
6340/**
6341 * @callback_method_impl{FNSSMDEVLOADEXEC}
6342 */
6343static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6344{
6345 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6346 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6347 int const rcErr = VERR_SSM_UNEXPECTED_DATA;
6348 LogFlowFunc(("\n"));
6349
6350 /* Validate. */
6351 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
6352 if (uVersion != IOMMU_SAVED_STATE_VERSION)
6353 {
6354 LogRel(("%s: Invalid saved-state version %#x\n", IOMMU_LOG_PFX, uVersion));
6355 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
6356 }
6357
6358 /* Load ExtFeat and other read-only registers first. */
6359 int rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64);
6360 AssertRCReturn(rc, rc);
6361 AssertLogRelMsgReturn(pThis->ExtFeat.n.u2HostAddrTranslateSize < 0x3,
6362 ("ExtFeat.HATS register invalid %#RX64\n", pThis->ExtFeat.u64), rcErr);
6363 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64);
6364 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64);
6365 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64);
6366 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64);
6367 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg);
6368
6369 /* IOMMU base address register. */
6370 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->IommuBar.u64);
6371 AssertRCReturn(rc, rc);
6372 pThis->IommuBar.u64 &= IOMMU_BAR_VALID_MASK;
6373
6374 /* Device table base address registers. */
6375 uint8_t cDevTabBaseAddrs;
6376 rc = pHlp->pfnSSMGetU8(pSSM, &cDevTabBaseAddrs);
6377 AssertRCReturn(rc, rc);
6378 AssertLogRelMsgReturn(cDevTabBaseAddrs > 0 && cDevTabBaseAddrs <= RT_ELEMENTS(pThis->aDevTabBaseAddrs),
6379 ("Device table segment count invalid %#x\n", cDevTabBaseAddrs), rcErr);
6380 AssertCompile(RT_ELEMENTS(pThis->aDevTabBaseAddrs) == RT_ELEMENTS(g_auDevTabSegMaxSizes));
6381 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6382 {
6383 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aDevTabBaseAddrs[i].u64);
6384 AssertRCReturn(rc, rc);
6385 pThis->aDevTabBaseAddrs[i].u64 &= IOMMU_DEV_TAB_BAR_VALID_MASK;
6386 uint16_t const uSegSize = pThis->aDevTabBaseAddrs[i].n.u9Size;
6387 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[i];
6388 AssertLogRelMsgReturn(uSegSize <= uMaxSegSize,
6389 ("Device table [%u] segment size invalid %u (max %u)\n", i, uSegSize, uMaxSegSize), rcErr);
6390 }
6391
6392 /* Command buffer base address register. */
6393 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufBaseAddr.u64);
6394 AssertRCReturn(rc, rc);
6395 pThis->CmdBufBaseAddr.u64 &= IOMMU_CMD_BUF_BAR_VALID_MASK;
6396 AssertLogRelMsgReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8,
6397 ("Command buffer base address invalid %#RX64\n", pThis->CmdBufBaseAddr.u64), rcErr);
6398
6399 /* Event log base address register. */
6400 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBaseAddr.u64);
6401 AssertRCReturn(rc, rc);
6402 pThis->EvtLogBaseAddr.u64 &= IOMMU_EVT_LOG_BAR_VALID_MASK;
6403 AssertLogRelMsgReturn(pThis->EvtLogBaseAddr.n.u4Len >= 8,
6404 ("Event log base address invalid %#RX64\n", pThis->EvtLogBaseAddr.u64), rcErr);
6405
6406 /* Control register. */
6407 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Ctrl.u64);
6408 AssertRCReturn(rc, rc);
6409 pThis->Ctrl.u64 &= IOMMU_CTRL_VALID_MASK;
6410 AssertLogRelMsgReturn(pThis->Ctrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup,
6411 ("Control register invalid %#RX64\n", pThis->Ctrl.u64), rcErr);
6412
6413 /* Exclusion range base address register. */
6414 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeBaseAddr.u64);
6415 AssertRCReturn(rc, rc);
6416 pThis->ExclRangeBaseAddr.u64 &= IOMMU_EXCL_RANGE_BAR_VALID_MASK;
6417
6418 /* Exclusion range limit register. */
6419 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeLimit.u64);
6420 AssertRCReturn(rc, rc);
6421 pThis->ExclRangeLimit.u64 &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
6422 pThis->ExclRangeLimit.u64 |= UINT64_C(0xfff);
6423
6424#if 0
6425 pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64); /* read-only, done already (above). */
6426#endif
6427
6428 /* PPR log base address register. */
6429 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBaseAddr.u64);
6430 AssertRCReturn(rc, rc);
6431 Assert(!pThis->ExtFeat.n.u1PprSup);
6432
6433 /* Hardware event (Hi) register. */
6434 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtHi.u64);
6435 AssertRCReturn(rc, rc);
6436
6437 /* Hardware event (Lo) register. */
6438 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtLo);
6439 AssertRCReturn(rc, rc);
6440
6441 /* Hardware event status register. */
6442 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtStatus.u64);
6443 AssertRCReturn(rc, rc);
6444 pThis->HwEvtStatus.u64 &= IOMMU_HW_EVT_STATUS_VALID_MASK;
6445
6446 /* Guest Virtual-APIC log base address register. */
6447 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogBaseAddr.u64);
6448 AssertRCReturn(rc, rc);
6449 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6450
6451 /* Guest Virtual-APIC log tail address register. */
6452 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailAddr.u64);
6453 AssertRCReturn(rc, rc);
6454 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6455
6456 /* PPR log-B base address register. */
6457 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBBaseAddr.u64);
6458 AssertRCReturn(rc, rc);
6459 Assert(!pThis->ExtFeat.n.u1PprSup);
6460
6461 /* Event log-B base address register. */
6462 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBBaseAddr.u64);
6463 AssertRCReturn(rc, rc);
6464 Assert(!pThis->ExtFeat.n.u2DualPprLogSup);
6465
6466#if 0
6467 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6468 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6469 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6470
6471 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64); /* read-only, done already (above). */
6472#endif
6473
6474 /* Performance optimization control register. */
6475 rc = pHlp->pfnSSMGetU32(pSSM, &pThis->PerfOptCtrl.u32);
6476 AssertRCReturn(rc, rc);
6477 Assert(!pThis->ExtFeat.n.u1PerfOptSup);
6478
6479 /* x2APIC registers. */
6480 {
6481 Assert(!pThis->ExtFeat.n.u1X2ApicSup);
6482
6483 /* x2APIC general interrupt control register. */
6484 pHlp->pfnSSMGetU64(pSSM, &pThis->XtGenIntrCtrl.u64);
6485 AssertRCReturn(rc, rc);
6486
6487 /* x2APIC PPR interrupt control register. */
6488 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtPprIntrCtrl.u64);
6489 AssertRCReturn(rc, rc);
6490
6491 /* x2APIC GA log interrupt control register. */
6492 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtGALogIntrCtrl.u64);
6493 AssertRCReturn(rc, rc);
6494 }
6495
6496 /* MARC (Memory Access and Routing) registers. */
6497 {
6498 uint8_t cMarcApers;
6499 rc = pHlp->pfnSSMGetU8(pSSM, &cMarcApers);
6500 AssertRCReturn(rc, rc);
6501 AssertLogRelMsgReturn(cMarcApers > 0 && cMarcApers <= RT_ELEMENTS(pThis->aMarcApers),
6502 ("MARC register count invalid %#x\n", cMarcApers), rcErr);
6503 for (uint8_t i = 0; i < cMarcApers; i++)
6504 {
6505 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Base.u64);
6506 AssertRCReturn(rc, rc);
6507
6508 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Reloc.u64);
6509 AssertRCReturn(rc, rc);
6510
6511 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Length.u64);
6512 AssertRCReturn(rc, rc);
6513 }
6514 Assert(!pThis->ExtFeat.n.u2MarcSup);
6515 }
6516
6517#if 0
6518 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg); /* read-only, done already (above). */
6519#endif
6520
6521 /* Command buffer head pointer register. */
6522 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufHeadPtr.u64);
6523 AssertRCReturn(rc, rc);
6524 {
6525 /*
6526 * IOMMU behavior is undefined when software writes a value outside the buffer length.
6527 * In our emulation, since we ignore the write entirely (see iommuAmdCmdBufHeadPtr_w)
6528 * we shouldn't see such values in the saved state.
6529 */
6530 uint32_t const offBuf = pThis->CmdBufHeadPtr.u64 & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
6531 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6532 Assert(cbBuf <= _512K);
6533 AssertLogRelMsgReturn(offBuf < cbBuf,
6534 ("Command buffer head pointer invalid %#x\n", pThis->CmdBufHeadPtr.u64), rcErr);
6535 }
6536
6537 /* Command buffer tail pointer register. */
6538 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufTailPtr.u64);
6539 AssertRCReturn(rc, rc);
6540 {
6541 uint32_t const offBuf = pThis->CmdBufTailPtr.u64 & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
6542 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6543 Assert(cbBuf <= _512K);
6544 AssertLogRelMsgReturn(offBuf < cbBuf,
6545 ("Command buffer tail pointer invalid %#x\n", pThis->CmdBufTailPtr.u64), rcErr);
6546 }
6547
6548 /* Event log head pointer register. */
6549 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogHeadPtr.u64);
6550 AssertRCReturn(rc, rc);
6551 {
6552 uint32_t const offBuf = pThis->EvtLogHeadPtr.u64 & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
6553 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6554 Assert(cbBuf <= _512K);
6555 AssertLogRelMsgReturn(offBuf < cbBuf,
6556 ("Event log head pointer invalid %#x\n", pThis->EvtLogHeadPtr.u64), rcErr);
6557 }
6558
6559 /* Event log tail pointer register. */
6560 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogTailPtr.u64);
6561 AssertRCReturn(rc, rc);
6562 {
6563 uint32_t const offBuf = pThis->EvtLogTailPtr.u64 & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
6564 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6565 Assert(cbBuf <= _512K);
6566 AssertLogRelMsgReturn(offBuf < cbBuf,
6567 ("Event log tail pointer invalid %#x\n", pThis->EvtLogTailPtr.u64), rcErr);
6568 }
6569
6570 /* Status register. */
6571 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Status.u64);
6572 AssertRCReturn(rc, rc);
6573 pThis->Status.u64 &= IOMMU_STATUS_VALID_MASK;
6574
6575 /* PPR log head pointer register. */
6576 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogHeadPtr.u64);
6577 AssertRCReturn(rc, rc);
6578 Assert(!pThis->ExtFeat.n.u1PprSup);
6579
6580 /* PPR log tail pointer register. */
6581 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogTailPtr.u64);
6582 AssertRCReturn(rc, rc);
6583 Assert(!pThis->ExtFeat.n.u1PprSup);
6584
6585 /* Guest Virtual-APIC log head pointer register. */
6586 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogHeadPtr.u64);
6587 AssertRCReturn(rc, rc);
6588 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6589
6590 /* Guest Virtual-APIC log tail pointer register. */
6591 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailPtr.u64);
6592 AssertRCReturn(rc, rc);
6593 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6594
6595 /* PPR log-B head pointer register. */
6596 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBHeadPtr.u64);
6597 AssertRCReturn(rc, rc);
6598 Assert(!pThis->ExtFeat.n.u1PprSup);
6599
6600 /* PPR log-B head pointer register. */
6601 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBTailPtr.u64);
6602 AssertRCReturn(rc, rc);
6603 Assert(!pThis->ExtFeat.n.u1PprSup);
6604
6605 /* Event log-B head pointer register. */
6606 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBHeadPtr.u64);
6607 AssertRCReturn(rc, rc);
6608 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6609
6610 /* Event log-B tail pointer register. */
6611 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBTailPtr.u64);
6612 AssertRCReturn(rc, rc);
6613 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6614
6615 /* PPR log auto response register. */
6616 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogAutoResp.u64);
6617 AssertRCReturn(rc, rc);
6618 Assert(!pThis->ExtFeat.n.u1PprAutoRespSup);
6619
6620 /* PPR log overflow early indicator register. */
6621 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogOverflowEarly.u64);
6622 AssertRCReturn(rc, rc);
6623 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6624
6625 /* PPR log-B overflow early indicator register. */
6626 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBOverflowEarly.u64);
6627 AssertRCReturn(rc, rc);
6628 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6629
6630 /* End marker. */
6631 {
6632 uint32_t uEndMarker;
6633 rc = pHlp->pfnSSMGetU32(pSSM, &uEndMarker);
6634 AssertLogRelMsgRCReturn(rc, ("Failed to read end marker. rc=%Rrc\n", rc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6635 AssertLogRelMsgReturn(uEndMarker == UINT32_MAX, ("End marker invalid (%#x expected %#x)\n", uEndMarker, UINT32_MAX),
6636 rcErr);
6637 }
6638
6639 return rc;
6640}
6641
6642
6643/**
6644 * @callback_method_impl{FNSSMDEVLOADDONE}
6645 */
6646static DECLCALLBACK(int) iommuAmdR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6647{
6648 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6649 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6650 RT_NOREF(pSSM);
6651 LogFlowFunc(("\n"));
6652
6653 /* Sanity. */
6654 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
6655 AssertPtrReturn(pThisR3, VERR_INVALID_POINTER);
6656
6657 int rc;
6658 IOMMU_LOCK(pDevIns, pThisR3);
6659
6660 /* Map MMIO regions if the IOMMU BAR is enabled. */
6661 if (pThis->IommuBar.n.u1Enable)
6662 rc = iommuAmdR3MmioSetup(pDevIns);
6663 else
6664 rc = VINF_SUCCESS;
6665
6666 /* Wake up the command thread if commands need processing. */
6667 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
6668
6669 IOMMU_UNLOCK(pDevIns, pThisR3);
6670
6671 LogRel(("%s: Restored: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
6672 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
6673 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
6674 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
6675 pThis->ExtFeat.u64));
6676 return rc;
6677}
6678
6679
6680/**
6681 * @interface_method_impl{PDMDEVREG,pfnReset}
6682 */
6683static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
6684{
6685 /*
6686 * Resets read-write portion of the IOMMU state.
6687 *
6688 * NOTE! State not initialized here is expected to be initialized during
6689 * device construction and remain read-only through the lifetime of the VM.
6690 */
6691 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6692 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6693 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6694 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6695 LogFlowFunc(("\n"));
6696
6697 IOMMU_LOCK(pDevIns, pThisR3);
6698
6699 RT_ZERO(pThis->aDevTabBaseAddrs);
6700
6701 pThis->CmdBufBaseAddr.u64 = 0;
6702 pThis->CmdBufBaseAddr.n.u4Len = 8;
6703
6704 pThis->EvtLogBaseAddr.u64 = 0;
6705 pThis->EvtLogBaseAddr.n.u4Len = 8;
6706
6707 pThis->Ctrl.u64 = 0;
6708 pThis->Ctrl.n.u1Coherent = 1;
6709 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
6710
6711 pThis->ExclRangeBaseAddr.u64 = 0;
6712 pThis->ExclRangeLimit.u64 = 0;
6713
6714 pThis->PprLogBaseAddr.u64 = 0;
6715 pThis->PprLogBaseAddr.n.u4Len = 8;
6716
6717 pThis->HwEvtHi.u64 = 0;
6718 pThis->HwEvtLo = 0;
6719 pThis->HwEvtStatus.u64 = 0;
6720
6721 pThis->GALogBaseAddr.u64 = 0;
6722 pThis->GALogBaseAddr.n.u4Len = 8;
6723 pThis->GALogTailAddr.u64 = 0;
6724
6725 pThis->PprLogBBaseAddr.u64 = 0;
6726 pThis->PprLogBBaseAddr.n.u4Len = 8;
6727
6728 pThis->EvtLogBBaseAddr.u64 = 0;
6729 pThis->EvtLogBBaseAddr.n.u4Len = 8;
6730
6731 pThis->PerfOptCtrl.u32 = 0;
6732
6733 pThis->XtGenIntrCtrl.u64 = 0;
6734 pThis->XtPprIntrCtrl.u64 = 0;
6735 pThis->XtGALogIntrCtrl.u64 = 0;
6736
6737 RT_ZERO(pThis->aMarcApers);
6738
6739 pThis->CmdBufHeadPtr.u64 = 0;
6740 pThis->CmdBufTailPtr.u64 = 0;
6741 pThis->EvtLogHeadPtr.u64 = 0;
6742 pThis->EvtLogTailPtr.u64 = 0;
6743
6744 pThis->Status.u64 = 0;
6745
6746 pThis->PprLogHeadPtr.u64 = 0;
6747 pThis->PprLogTailPtr.u64 = 0;
6748
6749 pThis->GALogHeadPtr.u64 = 0;
6750 pThis->GALogTailPtr.u64 = 0;
6751
6752 pThis->PprLogBHeadPtr.u64 = 0;
6753 pThis->PprLogBTailPtr.u64 = 0;
6754
6755 pThis->EvtLogBHeadPtr.u64 = 0;
6756 pThis->EvtLogBTailPtr.u64 = 0;
6757
6758 pThis->PprLogAutoResp.u64 = 0;
6759 pThis->PprLogOverflowEarly.u64 = 0;
6760 pThis->PprLogBOverflowEarly.u64 = 0;
6761
6762 pThis->IommuBar.u64 = 0;
6763 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
6764 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
6765
6766 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
6767
6768 IOMMU_UNLOCK(pDevIns, pThisR3);
6769
6770#ifdef IOMMU_WITH_DTE_CACHE
6771 iommuAmdDteCacheRemoveAll(pDevIns);
6772#endif
6773#ifdef IOMMU_WITH_IOTLBE_CACHE
6774 iommuAmdIotlbRemoveAll(pDevIns);
6775#endif
6776#ifdef IOMMU_WITH_IRTE_CACHE
6777 iommuAmdIrteCacheRemoveAll(pDevIns);
6778#endif
6779}
6780
6781
6782/**
6783 * @interface_method_impl{PDMDEVREG,pfnDestruct}
6784 */
6785static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
6786{
6787 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
6788 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6789 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6790 LogFlowFunc(("\n"));
6791
6792 IOMMU_LOCK(pDevIns, pThisR3);
6793
6794 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
6795 {
6796 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
6797 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
6798 }
6799
6800#ifdef IOMMU_WITH_IOTLBE_CACHE
6801 if (pThisR3->paIotlbes)
6802 {
6803 PDMDevHlpMMHeapFree(pDevIns, pThisR3->paIotlbes);
6804 pThisR3->paIotlbes = NULL;
6805 pThisR3->idxUnusedIotlbe = 0;
6806 }
6807#endif
6808
6809 IOMMU_UNLOCK(pDevIns, pThisR3);
6810 return VINF_SUCCESS;
6811}
6812
6813
6814/**
6815 * @interface_method_impl{PDMDEVREG,pfnConstruct}
6816 */
6817static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
6818{
6819 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6820
6821 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6822 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6823 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6824
6825 pThis->u32Magic = IOMMU_MAGIC;
6826 pThisR3->pDevInsR3 = pDevIns;
6827
6828 LogFlowFunc(("iInstance=%d\n", iInstance));
6829
6830 /*
6831 * Validate and read the configuration.
6832 */
6833 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "PCIAddress", "");
6834 int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "PCIAddress", &pThis->uPciAddress, NIL_PCIBDF);
6835 if (RT_FAILURE(rc))
6836 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query 32-bit integer \"PCIAddress\""));
6837 if (!PCIBDF_IS_VALID(pThis->uPciAddress))
6838 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed \"PCIAddress\" of the AMD IOMMU cannot be invalid"));
6839
6840 /*
6841 * Register the IOMMU with PDM.
6842 */
6843 PDMIOMMUREGR3 IommuReg;
6844 RT_ZERO(IommuReg);
6845 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
6846 IommuReg.pfnMemAccess = iommuAmdMemAccess;
6847 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
6848 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
6849 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
6850 rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
6851 if (RT_FAILURE(rc))
6852 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
6853 if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
6854 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6855 N_("IOMMU helper version mismatch; got %#x expected %#x"),
6856 pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
6857 if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
6858 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6859 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
6860 pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
6861 AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
6862 AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
6863 AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
6864 AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
6865
6866 /*
6867 * We will use PDM's critical section (via helpers) for the IOMMU device.
6868 */
6869 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
6870 AssertRCReturn(rc, rc);
6871
6872 /*
6873 * Initialize read-only PCI configuration space.
6874 */
6875 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6876 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6877
6878 /* Header. */
6879 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
6880 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
6881 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
6882 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
6883 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
6884 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
6885 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
6886 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
6887 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
6888 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
6889 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
6890 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
6891 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
6892 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
6893
6894 /* Capability Header. */
6895 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
6896 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
6897 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
6898 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Next capability offset */
6899 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
6900 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
6901 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
6902 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
6903 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
6904 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
6905 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
6906
6907 /* Base Address Register. */
6908 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
6909 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
6910
6911 /* IOMMU Range Register. */
6912 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
6913
6914 /* Misc. Information Register. */
6915 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
6916 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
6917 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
6918 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
6919 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
6920 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
6921 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
6922 uint32_t const uMiscInfoReg1 = 0;
6923 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
6924 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
6925
6926 /* MSI Capability Header register. */
6927 PDMMSIREG MsiReg;
6928 RT_ZERO(MsiReg);
6929 MsiReg.cMsiVectors = 1;
6930 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
6931 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
6932 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support". */
6933
6934 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
6935#if 0
6936 /* MSI Address Lo. */
6937 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
6938 /* MSI Address Hi. */
6939 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
6940 /* MSI Data. */
6941 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
6942#endif
6943
6944#if 0
6945 /** @todo IOMMU: I don't know if we need to support this, enable later if
6946 * required. */
6947 /* MSI Mapping Capability Header register. */
6948 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
6949 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
6950 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
6951 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
6952 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
6953 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
6954 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
6955#endif
6956
6957 /*
6958 * Register the PCI function with PDM.
6959 */
6960 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
6961 AssertLogRelRCReturn(rc, rc);
6962
6963 /*
6964 * Register MSI support for the PCI device.
6965 * This must be done -after- registering it as a PCI device!
6966 */
6967 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
6968 AssertRCReturn(rc, rc);
6969
6970 /*
6971 * Intercept PCI config. space accesses.
6972 */
6973 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
6974 AssertLogRelRCReturn(rc, rc);
6975
6976 /*
6977 * Create the MMIO region.
6978 * Mapping of the region is done when software configures it via PCI config space.
6979 */
6980 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
6981 NULL /* pvUser */,
6982 IOMMMIO_FLAGS_READ_DWORD_QWORD
6983 | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING
6984 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
6985 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
6986 "AMD-IOMMU", &pThis->hMmio);
6987 AssertLogRelRCReturn(rc, rc);
6988
6989 /*
6990 * Register saved state handlers.
6991 */
6992 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL /* pszBefore */,
6993 NULL /* pfnLivePrep */, NULL /* pfnLiveExec */, NULL /* pfnLiveVote */,
6994 NULL /* pfnSavePrep */, iommuAmdR3SaveExec, NULL /* pfnSaveDone */,
6995 NULL /* pfnLoadPrep */, iommuAmdR3LoadExec, iommuAmdR3LoadDone);
6996 AssertLogRelRCReturn(rc, rc);
6997
6998 /*
6999 * Register debugger info items.
7000 */
7001 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
7002 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device (from memory). Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
7003 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display I/O device tables with translation enabled.", iommuAmdR3DbgInfoDevTabs);
7004#ifdef IOMMU_WITH_IOTLBE_CACHE
7005 PDMDevHlpDBGFInfoRegister(pDevIns, "iommutlb", "Display IOTLBs for a domain. Arguments: DomainID.", iommuAmdR3DbgInfoIotlb);
7006#endif
7007#ifdef IOMMU_WITH_DTE_CACHE
7008 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudtecache", "Display the DTE cache.", iommuAmdR3DbgInfoDteCache);
7009#endif
7010#ifdef IOMMU_WITH_IRTE_CACHE
7011 PDMDevHlpDBGFInfoRegister(pDevIns, "iommuirtecache", "Display the IRTE cache.", iommuAmdR3DbgInfoIrteCache);
7012#endif
7013
7014# ifdef VBOX_WITH_STATISTICS
7015 /*
7016 * Statistics.
7017 */
7018 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
7019 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
7020
7021 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
7022 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
7023
7024 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
7025 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
7026
7027 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
7028 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
7029
7030 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
7031 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
7032
7033 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
7034 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
7035
7036 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
7037 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
7038
7039 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
7040 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
7041 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
7042 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
7043 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
7044 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
7045 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
7046 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
7047 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
7048
7049
7050 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeCached, STAMTYPE_COUNTER, "IOTLB/Cached", STAMUNIT_OCCURENCES, "Number of IOTLB entries in the cache.");
7051 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeLazyEvictReuse, STAMTYPE_COUNTER, "IOTLB/LazyEvictReuse", STAMUNIT_OCCURENCES, "Number of IOTLB entries reused after lazy eviction.");
7052
7053 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfDteLookup, STAMTYPE_PROFILE, "Profile/DteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling DTE lookup.");
7054 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIotlbeLookup, STAMTYPE_PROFILE, "Profile/IotlbeLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IOTLBE lookup.");
7055
7056 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteLookup, STAMTYPE_PROFILE, "Profile/IrteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE lookup.");
7057 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteCacheLookup, STAMTYPE_PROFILE, "Profile/IrteCacheLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE cache lookup.");
7058
7059 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHit, STAMTYPE_COUNTER, "MemAccess/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
7060 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheMiss, STAMTYPE_COUNTER, "MemAccess/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
7061 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHitFull, STAMTYPE_COUNTER, "MemAccess/CacheHitFull", STAMUNIT_OCCURENCES, "Number of accesses that was entirely in the cache.");
7062 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheNonContig, STAMTYPE_COUNTER, "MemAccess/CacheNonContig", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in non-contiguous translated regions.");
7063 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCachePermDenied, STAMTYPE_COUNTER, "MemAccess/CacheAddrDenied", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in denied permissions.");
7064 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDteNonContig, STAMTYPE_COUNTER, "MemAccess/DteNonContig", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in non-contiguous translated regions.");
7065 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDtePermDenied, STAMTYPE_COUNTER, "MemAccess/DtePermDenied", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in denied permissions.");
7066
7067 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheHit, STAMTYPE_COUNTER, "Interrupt/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
7068 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheMiss, STAMTYPE_COUNTER, "Interrupt/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
7069
7070 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatNonStdPageSize, STAMTYPE_COUNTER, "MemAccess/NonStdPageSize", STAMUNIT_OCCURENCES, "Number of non-standard page size translations.");
7071 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIopfs, STAMTYPE_COUNTER, "MemAccess/IOPFs", STAMUNIT_OCCURENCES, "Number of I/O page faults.");
7072# endif
7073
7074 /*
7075 * Create the command thread and its event semaphore.
7076 */
7077 char szDevIommu[64];
7078 RT_ZERO(szDevIommu);
7079 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
7080 rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
7081 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
7082 AssertLogRelRCReturn(rc, rc);
7083
7084 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
7085 AssertLogRelRCReturn(rc, rc);
7086
7087#ifdef IOMMU_WITH_DTE_CACHE
7088 /*
7089 * Initialize the critsect of the cache.
7090 */
7091 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSectCache, RT_SRC_POS, "IOMMUCache-#%u", pDevIns->iInstance);
7092 AssertLogRelRCReturn(rc, rc);
7093
7094 /* Several places in this code relies on this basic assumption - assert it! */
7095 AssertCompile(RT_ELEMENTS(pThis->aDeviceIds) == RT_ELEMENTS(pThis->aDteCache));
7096#endif
7097
7098#ifdef IOMMU_WITH_IOTLBE_CACHE
7099 /*
7100 * Allocate IOTLB entries.
7101 * This is allocated upfront since we expect a relatively small number of entries,
7102 * is more cache-line efficient and easier to track least recently used entries for
7103 * eviction when the cache is full. This also avoids unpredictable behavior during
7104 * the lifetime of the VM if the hyperheap gets full.
7105 */
7106 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
7107 pThisR3->paIotlbes = (PIOTLBE)PDMDevHlpMMHeapAllocZ(pDevIns, cbIotlbes);
7108 if (!pThisR3->paIotlbes)
7109 return PDMDevHlpVMSetError(pDevIns, VERR_NO_MEMORY, RT_SRC_POS,
7110 N_("Failed to allocate %zu bytes from the hyperheap for the IOTLB cache."), cbIotlbes);
7111 RTListInit(&pThisR3->LstLruIotlbe);
7112 LogRel(("%s: Allocated %zu bytes from the hyperheap for the IOTLB cache\n", IOMMU_LOG_PFX, cbIotlbes));
7113#endif
7114
7115 /*
7116 * Initialize read-only registers.
7117 * NOTE! Fields here must match their corresponding field in the ACPI tables.
7118 */
7119 /* Don't remove the commented lines below as it lets us see all features at a glance. */
7120 pThis->ExtFeat.u64 = 0;
7121 //pThis->ExtFeat.n.u1PrefetchSup = 0;
7122 //pThis->ExtFeat.n.u1PprSup = 0;
7123 //pThis->ExtFeat.n.u1X2ApicSup = 0;
7124 //pThis->ExtFeat.n.u1NoExecuteSup = 0;
7125 //pThis->ExtFeat.n.u1GstTranslateSup = 0;
7126 pThis->ExtFeat.n.u1InvAllSup = 1;
7127 //pThis->ExtFeat.n.u1GstVirtApicSup = 0;
7128 pThis->ExtFeat.n.u1HwErrorSup = 1;
7129 //pThis->ExtFeat.n.u1PerfCounterSup = 0;
7130 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
7131 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
7132 //pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
7133 //pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
7134 //pThis->ExtFeat.n.u2SmiFilterSup = 0;
7135 //pThis->ExtFeat.n.u3SmiFilterCount = 0;
7136 //pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
7137 //pThis->ExtFeat.n.u2DualPprLogSup = 0;
7138 //pThis->ExtFeat.n.u2DualEvtLogSup = 0;
7139 //pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
7140 //pThis->ExtFeat.n.u1UserSupervisorSup = 0;
7141 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
7142 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
7143 //pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
7144 //pThis->ExtFeat.n.u1PprAutoRespSup = 0;
7145 //pThis->ExtFeat.n.u2MarcSup = 0;
7146 //pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
7147 //pThis->ExtFeat.n.u1PerfOptSup = 0;
7148 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
7149 //pThis->ExtFeat.n.u1GstIoSup = 0;
7150 //pThis->ExtFeat.n.u1HostAccessSup = 0;
7151 //pThis->ExtFeat.n.u1EnhancedPprSup = 0;
7152 //pThis->ExtFeat.n.u1AttrForwardSup = 0;
7153 //pThis->ExtFeat.n.u1HostDirtySup = 0;
7154 //pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
7155 //pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
7156 //pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
7157
7158 pThis->DevSpecificFeat.u64 = 0;
7159 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
7160 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
7161
7162 pThis->DevSpecificCtrl.u64 = 0;
7163 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
7164 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
7165
7166 pThis->DevSpecificStatus.u64 = 0;
7167 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
7168 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
7169
7170 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
7171
7172 pThis->RsvdReg = 0;
7173
7174 /*
7175 * Initialize parts of the IOMMU state as it would during reset.
7176 * Also initializes non-zero initial values like IRTE cache keys.
7177 * Must be called -after- initializing PCI config. space registers.
7178 */
7179 iommuAmdR3Reset(pDevIns);
7180
7181 LogRel(("%s: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
7182 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
7183 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
7184 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
7185 pThis->ExtFeat.u64));
7186 return VINF_SUCCESS;
7187}
7188
7189#else
7190
7191/**
7192 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
7193 */
7194static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
7195{
7196 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7197 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
7198 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
7199 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
7200
7201 /* We will use PDM's critical section (via helpers) for the IOMMU device. */
7202 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7203 AssertRCReturn(rc, rc);
7204
7205 /* Set up the MMIO RZ handlers. */
7206 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
7207 AssertRCReturn(rc, rc);
7208
7209 /* Set up the IOMMU RZ callbacks. */
7210 PDMIOMMUREGCC IommuReg;
7211 RT_ZERO(IommuReg);
7212 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
7213 IommuReg.idxIommu = pThis->idxIommu;
7214 IommuReg.pfnMemAccess = iommuAmdMemAccess;
7215 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
7216 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
7217 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
7218 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
7219 AssertRCReturn(rc, rc);
7220 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
7221 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
7222 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
7223 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
7224 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
7225 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
7226 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
7227 return VINF_SUCCESS;
7228}
7229#endif
7230
7231
7232/**
7233 * The device registration structure.
7234 */
7235const PDMDEVREG g_DeviceIommuAmd =
7236{
7237 /* .u32Version = */ PDM_DEVREG_VERSION,
7238 /* .uReserved0 = */ 0,
7239 /* .szName = */ "iommu-amd",
7240 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
7241 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
7242 /* .cMaxInstances = */ 1,
7243 /* .uSharedVersion = */ 42,
7244 /* .cbInstanceShared = */ sizeof(IOMMU),
7245 /* .cbInstanceCC = */ sizeof(IOMMUCC),
7246 /* .cbInstanceRC = */ sizeof(IOMMURC),
7247 /* .cMaxPciDevices = */ 1,
7248 /* .cMaxMsixVectors = */ 0,
7249 /* .pszDescription = */ "IOMMU (AMD)",
7250#if defined(IN_RING3)
7251 /* .pszRCMod = */ "VBoxDDRC.rc",
7252 /* .pszR0Mod = */ "VBoxDDR0.r0",
7253 /* .pfnConstruct = */ iommuAmdR3Construct,
7254 /* .pfnDestruct = */ iommuAmdR3Destruct,
7255 /* .pfnRelocate = */ NULL,
7256 /* .pfnMemSetup = */ NULL,
7257 /* .pfnPowerOn = */ NULL,
7258 /* .pfnReset = */ iommuAmdR3Reset,
7259 /* .pfnSuspend = */ NULL,
7260 /* .pfnResume = */ NULL,
7261 /* .pfnAttach = */ NULL,
7262 /* .pfnDetach = */ NULL,
7263 /* .pfnQueryInterface = */ NULL,
7264 /* .pfnInitComplete = */ NULL,
7265 /* .pfnPowerOff = */ NULL,
7266 /* .pfnSoftReset = */ NULL,
7267 /* .pfnReserved0 = */ NULL,
7268 /* .pfnReserved1 = */ NULL,
7269 /* .pfnReserved2 = */ NULL,
7270 /* .pfnReserved3 = */ NULL,
7271 /* .pfnReserved4 = */ NULL,
7272 /* .pfnReserved5 = */ NULL,
7273 /* .pfnReserved6 = */ NULL,
7274 /* .pfnReserved7 = */ NULL,
7275#elif defined(IN_RING0)
7276 /* .pfnEarlyConstruct = */ NULL,
7277 /* .pfnConstruct = */ iommuAmdRZConstruct,
7278 /* .pfnDestruct = */ NULL,
7279 /* .pfnFinalDestruct = */ NULL,
7280 /* .pfnRequest = */ NULL,
7281 /* .pfnReserved0 = */ NULL,
7282 /* .pfnReserved1 = */ NULL,
7283 /* .pfnReserved2 = */ NULL,
7284 /* .pfnReserved3 = */ NULL,
7285 /* .pfnReserved4 = */ NULL,
7286 /* .pfnReserved5 = */ NULL,
7287 /* .pfnReserved6 = */ NULL,
7288 /* .pfnReserved7 = */ NULL,
7289#elif defined(IN_RC)
7290 /* .pfnConstruct = */ iommuAmdRZConstruct,
7291 /* .pfnReserved0 = */ NULL,
7292 /* .pfnReserved1 = */ NULL,
7293 /* .pfnReserved2 = */ NULL,
7294 /* .pfnReserved3 = */ NULL,
7295 /* .pfnReserved4 = */ NULL,
7296 /* .pfnReserved5 = */ NULL,
7297 /* .pfnReserved6 = */ NULL,
7298 /* .pfnReserved7 = */ NULL,
7299#else
7300# error "Not in IN_RING3, IN_RING0 or IN_RC!"
7301#endif
7302 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
7303};
7304
7305#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
7306
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