VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 89394

Last change on this file since 89394 was 89067, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Debug asserts here is sufficient, not expected to fail.
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1/* $Id: DevIommuAmd.cpp 89067 2021-05-17 05:41:48Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26
27#include <iprt/x86.h>
28#include <iprt/string.h>
29#include <iprt/avl.h>
30#ifdef IN_RING3
31# include <iprt/mem.h>
32#endif
33
34#include "VBoxDD.h"
35#include "DevIommuAmd.h"
36
37
38/*********************************************************************************************************************************
39* Defined Constants And Macros *
40*********************************************************************************************************************************/
41/** Release log prefix string. */
42#define IOMMU_LOG_PFX "AMD-IOMMU"
43/** The current saved state version. */
44#define IOMMU_SAVED_STATE_VERSION 1
45/** The IOMMU device instance magic. */
46#define IOMMU_MAGIC 0x10acce55
47
48/** Enable the IOTLBE cache only in ring-3 for now, see @bugref{9654#c95}. */
49#ifdef IN_RING3
50# define IOMMU_WITH_IOTLBE_CACHE
51#endif
52/** Enable the interrupt cache. */
53#define IOMMU_WITH_IRTE_CACHE
54
55/* The DTE cache is mandatory for the IOTLB or interrupt cache to work. */
56#if defined(IOMMU_WITH_IOTLBE_CACHE) || defined(IOMMU_WITH_IRTE_CACHE)
57# define IOMMU_WITH_DTE_CACHE
58/** The maximum number of device IDs in the cache. */
59# define IOMMU_DEV_CACHE_COUNT 16
60/** An empty device ID. */
61# define IOMMU_DTE_CACHE_KEY_NIL 0
62#endif
63
64#ifdef IOMMU_WITH_IRTE_CACHE
65/** The maximum number of IRTE cache entries. */
66# define IOMMU_IRTE_CACHE_COUNT 32
67/** A NIL IRTE cache entry key. */
68# define IOMMU_IRTE_CACHE_KEY_NIL (~(uint32_t)0U)
69/** Gets the device ID from an IRTE cache entry key. */
70#define IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(a_Key) RT_HIWORD(a_Key)
71/** Gets the IOVA from the IOTLB entry key. */
72# define IOMMU_IRTE_CACHE_KEY_GET_OFF(a_Key) RT_LOWORD(a_Key)
73/** Makes an IRTE cache entry key.
74 *
75 * Bits 31:16 is the device ID (Bus, Device, Function).
76 * Bits 15:0 is the the offset into the IRTE table.
77 */
78# define IOMMU_IRTE_CACHE_KEY_MAKE(a_DevId, a_off) RT_MAKE_U32(a_off, a_DevId)
79#endif /* IOMMU_WITH_IRTE_CACHE */
80
81#ifdef IOMMU_WITH_IOTLBE_CACHE
82/** The maximum number of IOTLB entries. */
83# define IOMMU_IOTLBE_MAX 96
84/** The mask of bits covering the domain ID in the IOTLBE key. */
85# define IOMMU_IOTLB_DOMAIN_ID_MASK UINT64_C(0xffffff0000000000)
86/** The mask of bits covering the IOVA in the IOTLBE key. */
87# define IOMMU_IOTLB_IOVA_MASK (~IOMMU_IOTLB_DOMAIN_ID_MASK)
88/** The number of bits to shift for the domain ID of the IOTLBE key. */
89# define IOMMU_IOTLB_DOMAIN_ID_SHIFT 40
90/** A NIL IOTLB key. */
91# define IOMMU_IOTLB_KEY_NIL UINT64_C(0)
92/** Gets the domain ID from an IOTLB entry key. */
93# define IOMMU_IOTLB_KEY_GET_DOMAIN_ID(a_Key) ((a_Key) >> IOMMU_IOTLB_DOMAIN_ID_SHIFT)
94/** Gets the IOVA from the IOTLB entry key. */
95# define IOMMU_IOTLB_KEY_GET_IOVA(a_Key) (((a_Key) & IOMMU_IOTLB_IOVA_MASK) << X86_PAGE_4K_SHIFT)
96/** Makes an IOTLB entry key.
97 *
98 * Address bits 63:52 of the IOVA are zero extended, so top 12 bits are free.
99 * Address bits 11:0 of the IOVA are offset into the minimum page size of 4K,
100 * so bottom 12 bits are free.
101 *
102 * Thus we use the top 24 bits of key to hold bits 15:0 of the domain ID.
103 * We use the bottom 40 bits of the key to hold bits 51:12 of the IOVA.
104 */
105# define IOMMU_IOTLB_KEY_MAKE(a_DomainId, a_uIova) ( ((uint64_t)(a_DomainId) << IOMMU_IOTLB_DOMAIN_ID_SHIFT) \
106 | (((a_uIova) >> X86_PAGE_4K_SHIFT) & IOMMU_IOTLB_IOVA_MASK))
107#endif /* IOMMU_WITH_IOTLBE_CACHE */
108
109#ifdef IOMMU_WITH_DTE_CACHE
110/** @name IOMMU_DTE_CACHE_F_XXX: DTE cache flags.
111 *
112 * Some of these flags are "basic" i.e. they correspond directly to their bits in
113 * the DTE. The rest of the flags are based on checks or operations on several DTE
114 * bits.
115 *
116 * The basic flags are:
117 * - VALID (DTE.V)
118 * - IO_PERM_READ (DTE.IR)
119 * - IO_PERM_WRITE (DTE.IW)
120 * - IO_PERM_RSVD (bit following DTW.IW reserved for future & to keep
121 * masking consistent)
122 * - SUPPRESS_ALL_IOPF (DTE.SA)
123 * - SUPPRESS_IOPF (DTE.SE)
124 * - INTR_MAP_VALID (DTE.IV)
125 * - IGNORE_UNMAPPED_INTR (DTE.IG)
126 *
127 * @see iommuAmdGetBasicDevFlags()
128 * @{ */
129/** The DTE is present. */
130# define IOMMU_DTE_CACHE_F_PRESENT RT_BIT(0)
131/** The DTE is valid. */
132# define IOMMU_DTE_CACHE_F_VALID RT_BIT(1)
133/** The DTE permissions apply for address translations. */
134# define IOMMU_DTE_CACHE_F_IO_PERM RT_BIT(2)
135/** DTE permission - I/O read allowed. */
136# define IOMMU_DTE_CACHE_F_IO_PERM_READ RT_BIT(3)
137/** DTE permission - I/O write allowed. */
138# define IOMMU_DTE_CACHE_F_IO_PERM_WRITE RT_BIT(4)
139/** DTE permission - reserved. */
140# define IOMMU_DTE_CACHE_F_IO_PERM_RSVD RT_BIT(5)
141/** Address translation required. */
142# define IOMMU_DTE_CACHE_F_ADDR_TRANSLATE RT_BIT(6)
143/** Suppress all I/O page faults. */
144# define IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF RT_BIT(7)
145/** Suppress I/O page faults. */
146# define IOMMU_DTE_CACHE_F_SUPPRESS_IOPF RT_BIT(8)
147/** Interrupt map valid. */
148# define IOMMU_DTE_CACHE_F_INTR_MAP_VALID RT_BIT(9)
149/** Ignore unmapped interrupts. */
150# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR RT_BIT(10)
151/** An I/O page fault has been raised for this device. */
152# define IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED RT_BIT(11)
153/** Fixed and arbitrary interrupt control: Target Abort. */
154# define IOMMU_DTE_CACHE_F_INTR_CTRL_TARGET_ABORT RT_BIT(12)
155/** Fixed and arbitrary interrupt control: Forward unmapped. */
156# define IOMMU_DTE_CACHE_F_INTR_CTRL_FWD_UNMAPPED RT_BIT(13)
157/** Fixed and arbitrary interrupt control: Remapped. */
158# define IOMMU_DTE_CACHE_F_INTR_CTRL_REMAPPED RT_BIT(14)
159/** Fixed and arbitrary interrupt control: Reserved. */
160# define IOMMU_DTE_CACHE_F_INTR_CTRL_RSVD RT_BIT(15)
161/** @} */
162
163/** The number of bits to shift I/O device flags for DTE permissions. */
164# define IOMMU_DTE_CACHE_F_IO_PERM_SHIFT 3
165/** The mask of DTE permissions in I/O device flags. */
166# define IOMMU_DTE_CACHE_F_IO_PERM_MASK 0x3
167/** The number of bits to shift I/O device flags for interrupt control bits. */
168# define IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT 12
169/** The mask of interrupt control bits in I/O device flags. */
170# define IOMMU_DTE_CACHE_F_INTR_CTRL_MASK 0x3
171/** The number of bits to shift for ignore-unmapped interrupts bit. */
172# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR_SHIFT 10
173
174/** Acquires the cache lock. */
175#ifdef IN_RING3
176# define IOMMU_CACHE_LOCK(a_pDevIns, a_pThis) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VERR_IGNORED)
177#else
178# define IOMMU_CACHE_LOCK(a_pDevIns, a_pThis) \
179 do { \
180 int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VINF_SUCCESS); \
181 AssertRC(rcLock); \
182 } while (0)
183#endif
184
185/** Releases the cache lock. */
186# define IOMMU_CACHE_UNLOCK(a_pDevIns, a_pThis) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSectCache)
187#endif /* IOMMU_WITH_DTE_CACHE */
188
189/** Gets the page offset mask given the number of bits to shift. */
190#define IOMMU_GET_PAGE_OFF_MASK(a_cShift) (~(UINT64_C(0xffffffffffffffff) << (a_cShift)))
191
192/** Acquires the PDM lock (returns a_rcBusy on contention). */
193#define IOMMU_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
194 do { \
195 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)); \
196 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
197 { /* likely */ } \
198 else \
199 return rcLock; \
200 } while (0)
201
202/** Acquires the PDM lock (shouldn't really fail). */
203#ifdef IN_RING3
204# define IOMMU_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED)
205#else
206# define IOMMU_LOCK(a_pDevIns, a_pThisCC) \
207 do { \
208 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
209 AssertRC(rcLock); \
210 } while (0)
211#endif
212
213/** Checks if the current thread owns the PDM lock. */
214# define IOMMU_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
215 do \
216 { \
217 Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner((a_pDevIns))); \
218 NOREF(a_pThisCC); \
219 } while (0)
220
221/** Releases the PDM lock. */
222# define IOMMU_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock((a_pDevIns))
223
224
225/*********************************************************************************************************************************
226* Structures and Typedefs *
227*********************************************************************************************************************************/
228/**
229 * IOMMU operation (transaction).
230 */
231typedef enum IOMMUOP
232{
233 /** Address translation request. */
234 IOMMUOP_TRANSLATE_REQ = 0,
235 /** Memory read request. */
236 IOMMUOP_MEM_READ,
237 /** Memory write request. */
238 IOMMUOP_MEM_WRITE,
239 /** Interrupt request. */
240 IOMMUOP_INTR_REQ,
241 /** Command. */
242 IOMMUOP_CMD
243} IOMMUOP;
244/** Pointer to a IOMMU operation. */
245typedef IOMMUOP *PIOMMUOP;
246
247/**
248 * I/O page lookup.
249 */
250typedef struct IOPAGELOOKUP
251{
252 /** The translated system physical address. */
253 RTGCPHYS GCPhysSpa;
254 /** The number of offset bits in the system physical address. */
255 uint8_t cShift;
256 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
257 uint8_t fPerm;
258} IOPAGELOOKUP;
259/** Pointer to an I/O page lookup. */
260typedef IOPAGELOOKUP *PIOPAGELOOKUP;
261/** Pointer to a const I/O page lookup. */
262typedef IOPAGELOOKUP const *PCIOPAGELOOKUP;
263
264/**
265 * I/O address range.
266 */
267typedef struct IOADDRRANGE
268{
269 /** The address (virtual or physical). */
270 uint64_t uAddr;
271 /** The size of the access in bytes. */
272 size_t cb;
273 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
274 uint8_t fPerm;
275} IOADDRRANGE;
276/** Pointer to an I/O address range. */
277typedef IOADDRRANGE *PIOADDRRANGE;
278/** Pointer to a const I/O address range. */
279typedef IOADDRRANGE const *PCIOADDRRANGE;
280
281#ifdef IOMMU_WITH_DTE_CACHE
282/**
283 * Device Table Entry Cache.
284 */
285typedef struct DTECACHE
286{
287 /** This device's flags, see IOMMU_DTE_CACHE_F_XXX. */
288 uint16_t fFlags;
289 /** The domain ID assigned for this device by software. */
290 uint16_t idDomain;
291} DTECACHE;
292/** Pointer to an I/O device struct. */
293typedef DTECACHE *PDTECACHE;
294/** Pointer to a const I/O device struct. */
295typedef DTECACHE *PCDTECACHE;
296AssertCompileSize(DTECACHE, 4);
297#endif /* IOMMU_WITH_DTE_CACHE */
298
299#ifdef IOMMU_WITH_IOTLBE_CACHE
300/**
301 * I/O TLB Entry.
302 * Keep this as small and aligned as possible.
303 */
304typedef struct IOTLBE
305{
306 /** The AVL tree node. */
307 AVLU64NODECORE Core;
308 /** The least recently used (LRU) list node. */
309 RTLISTNODE NdLru;
310 /** The I/O page lookup results of the translation. */
311 IOPAGELOOKUP PageLookup;
312 /** Whether the entry needs to be evicted from the cache. */
313 bool fEvictPending;
314} IOTLBE;
315/** Pointer to an IOMMU I/O TLB entry struct. */
316typedef IOTLBE *PIOTLBE;
317/** Pointer to a const IOMMU I/O TLB entry struct. */
318typedef IOTLBE const *PCIOTLBE;
319AssertCompileSizeAlignment(IOTLBE, 8);
320AssertCompileMemberOffset(IOTLBE, Core, 0);
321#endif /* IOMMU_WITH_IOTLBE_CACHE */
322
323#ifdef IOMMU_WITH_IRTE_CACHE
324/**
325 * Interrupt Remap Table Entry Cache.
326 */
327typedef struct IRTECACHE
328{
329 /** The key, see IOMMU_IRTE_CACHE_KEY_MAKE. */
330 uint32_t uKey;
331 /** The IRTE. */
332 IRTE_T Irte;
333} IRTECACHE;
334/** Pointer to an IRTE cache struct. */
335typedef IRTECACHE *PIRTECACHE;
336/** Pointer to a const IRTE cache struct. */
337typedef IRTECACHE const *PCIRTECACHE;
338AssertCompileSizeAlignment(IRTECACHE, 4);
339#endif /* IOMMU_WITH_IRTE_CACHE */
340
341/**
342 * The shared IOMMU device state.
343 */
344typedef struct IOMMU
345{
346 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
347 uint32_t idxIommu;
348 /** IOMMU magic. */
349 uint32_t u32Magic;
350
351 /** The MMIO handle. */
352 IOMMMIOHANDLE hMmio;
353 /** The event semaphore the command thread waits on. */
354 SUPSEMEVENT hEvtCmdThread;
355 /** Whether the command thread has been signaled for wake up. */
356 bool volatile fCmdThreadSignaled;
357 /** Padding. */
358 bool afPadding0[7];
359
360#ifdef IOMMU_WITH_DTE_CACHE
361 /** The critsect that protects the cache from concurrent access. */
362 PDMCRITSECT CritSectCache;
363 /** Array of device IDs. */
364 uint16_t aDeviceIds[IOMMU_DEV_CACHE_COUNT];
365 /** Array of DTE cache entries. */
366 DTECACHE aDteCache[IOMMU_DEV_CACHE_COUNT];
367#endif
368#ifdef IOMMU_WITH_IRTE_CACHE
369 /** Array of IRTE cache entries. */
370 IRTECACHE aIrteCache[IOMMU_IRTE_CACHE_COUNT];
371#endif
372
373 /** @name PCI: Base capability block registers.
374 * @{ */
375 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
376 /** @} */
377
378 /** @name MMIO: Control and status registers.
379 * @{ */
380 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
381 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
382 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
383 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
384 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
385 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
386 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
387 /** @} */
388
389 /** @name MMIO: Peripheral Page Request (PPR) Log registers.
390 * @{ */
391 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
392 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
393 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
394 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
395 /** @} */
396
397 /** @todo IOMMU: SMI filter. */
398
399 /** @name MMIO: Guest Virtual-APIC Log registers.
400 * @{ */
401 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
402 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
403 /** @} */
404
405 /** @name MMIO: Alternate PPR and Event Log registers.
406 * @{ */
407 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
408 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
409 /** @} */
410
411 /** @name MMIO: Device-specific feature registers.
412 * @{ */
413 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
414 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
415 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
416 /** @} */
417
418 /** @name MMIO: MSI Capability Block registers.
419 * @{ */
420 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
421 /** @} */
422
423 /** @name MMIO: Performance Optimization Control registers.
424 * @{ */
425 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
426 /** @} */
427
428 /** @name MMIO: x2APIC Control registers.
429 * @{ */
430 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
431 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
432 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
433 /** @} */
434
435 /** @name MMIO: Memory Address Routing & Control (MARC) registers.
436 * @{ */
437 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
438 /** @} */
439
440 /** @name MMIO: Reserved register.
441 * @{ */
442 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
443 /** @} */
444
445 /** @name MMIO: Command and Event Log pointer registers.
446 * @{ */
447 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
448 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
449 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
450 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
451 /** @} */
452
453 /** @name MMIO: Command and Event Status register.
454 * @{ */
455 IOMMU_STATUS_T Status; /**< IOMMU status register. */
456 /** @} */
457
458 /** @name MMIO: PPR Log Head and Tail pointer registers.
459 * @{ */
460 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
461 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
462 /** @} */
463
464 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
465 * @{ */
466 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
467 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
468 /** @} */
469
470 /** @name MMIO: PPR Log B Head and Tail pointer registers.
471 * @{ */
472 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
473 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
474 /** @} */
475
476 /** @name MMIO: Event Log B Head and Tail pointer registers.
477 * @{ */
478 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
479 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
480 /** @} */
481
482 /** @name MMIO: PPR Log Overflow protection registers.
483 * @{ */
484 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
485 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
486 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
487 /** @} */
488
489 /** @todo IOMMU: IOMMU Event counter registers. */
490
491#ifdef VBOX_WITH_STATISTICS
492 /** @name IOMMU: Stat counters.
493 * @{ */
494 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
495 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
496 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
497 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
498
499 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
500 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
501
502 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
503 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
504 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
505 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
506
507 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
508 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
509 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
510 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
511
512 STAMCOUNTER StatCmd; /**< Number of commands processed in total. */
513 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
514 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
515 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
516 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
517 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
518 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
519 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
520 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
521
522 STAMCOUNTER StatIotlbeCached; /**< Number of IOTLB entries in the cache. */
523 STAMCOUNTER StatIotlbeLazyEvictReuse; /**< Number of IOTLB entries re-used after lazy eviction. */
524
525 STAMPROFILEADV StatProfDteLookup; /**< Profiling of I/O page walk (from memory). */
526 STAMPROFILEADV StatProfIotlbeLookup; /**< Profiling of IOTLB entry lookup (from cache). */
527
528 STAMPROFILEADV StatProfIrteLookup; /**< Profiling of IRTE entry lookup (from memory). */
529 STAMPROFILEADV StatProfIrteCacheLookup; /**< Profiling of IRTE entry lookup (from cache). */
530
531 STAMCOUNTER StatAccessCacheHit; /**< Number of IOTLB cache hits. */
532 STAMCOUNTER StatAccessCacheHitFull; /**< Number of accesses that were fully looked up from the cache. */
533 STAMCOUNTER StatAccessCacheMiss; /**< Number of cache misses (resulting in DTE lookups). */
534 STAMCOUNTER StatAccessCacheNonContig; /**< Number of cache accesses resulting in non-contiguous access. */
535 STAMCOUNTER StatAccessCachePermDenied; /**< Number of cache accesses resulting in insufficient permissions. */
536 STAMCOUNTER StatAccessDteNonContig; /**< Number of DTE accesses resulting in non-contiguous access. */
537 STAMCOUNTER StatAccessDtePermDenied; /**< Number of DTE accesses resulting in insufficient permissions. */
538
539 STAMCOUNTER StatIntrCacheHit; /**< Number of interrupt cache hits. */
540 STAMCOUNTER StatIntrCacheMiss; /**< Number of interrupt cache misses. */
541 /** @} */
542#endif
543} IOMMU;
544/** Pointer to the IOMMU device state. */
545typedef IOMMU *PIOMMU;
546/** Pointer to the const IOMMU device state. */
547typedef const IOMMU *PCIOMMU;
548AssertCompileMemberAlignment(IOMMU, hMmio, 8);
549#ifdef IOMMU_WITH_DTE_CACHE
550AssertCompileMemberAlignment(IOMMU, CritSectCache, 8);
551AssertCompileMemberAlignment(IOMMU, aDeviceIds, 8);
552AssertCompileMemberAlignment(IOMMU, aDteCache, 8);
553#endif
554#ifdef IOMMU_WITH_IRTE_CACHE
555AssertCompileMemberAlignment(IOMMU, aIrteCache, 8);
556#endif
557AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
558AssertCompileMemberAlignment(IOMMU, aDevTabBaseAddrs, 8);
559AssertCompileMemberAlignment(IOMMU, CmdBufHeadPtr, 8);
560AssertCompileMemberAlignment(IOMMU, Status, 8);
561
562/**
563 * The ring-3 IOMMU device state.
564 */
565typedef struct IOMMUR3
566{
567 /** Device instance. */
568 PPDMDEVINSR3 pDevInsR3;
569 /** The IOMMU helpers. */
570 R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
571 /** The command thread handle. */
572 R3PTRTYPE(PPDMTHREAD) pCmdThread;
573#ifdef IOMMU_WITH_IOTLBE_CACHE
574 /** Pointer to array of pre-allocated IOTLBEs. */
575 PIOTLBE paIotlbes;
576 /** Maps [DomainId,Iova] to [IOTLBE]. */
577 AVLU64TREE TreeIotlbe;
578 /** LRU list anchor for IOTLB entries. */
579 RTLISTANCHOR LstLruIotlbe;
580 /** Index of the next unused IOTLB. */
581 uint32_t idxUnusedIotlbe;
582 /** Number of cached IOTLB entries in the tree. */
583 uint32_t cCachedIotlbes;
584#endif
585} IOMMUR3;
586/** Pointer to the ring-3 IOMMU device state. */
587typedef IOMMUR3 *PIOMMUR3;
588/** Pointer to the const ring-3 IOMMU device state. */
589typedef const IOMMUR3 *PCIOMMUR3;
590#ifdef IOMMU_WITH_IOTLBE_CACHE
591AssertCompileMemberAlignment(IOMMUR3, paIotlbes, 8);
592AssertCompileMemberAlignment(IOMMUR3, TreeIotlbe, 8);
593AssertCompileMemberAlignment(IOMMUR3, LstLruIotlbe, 8);
594#endif
595
596/**
597 * The ring-0 IOMMU device state.
598 */
599typedef struct IOMMUR0
600{
601 /** Device instance. */
602 PPDMDEVINSR0 pDevInsR0;
603 /** The IOMMU helpers. */
604 R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
605} IOMMUR0;
606/** Pointer to the ring-0 IOMMU device state. */
607typedef IOMMUR0 *PIOMMUR0;
608
609/**
610 * The raw-mode IOMMU device state.
611 */
612typedef struct IOMMURC
613{
614 /** Device instance. */
615 PPDMDEVINSRC pDevInsRC;
616 /** The IOMMU helpers. */
617 RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
618} IOMMURC;
619/** Pointer to the raw-mode IOMMU device state. */
620typedef IOMMURC *PIOMMURC;
621
622/** The IOMMU device state for the current context. */
623typedef CTX_SUFF(IOMMU) IOMMUCC;
624/** Pointer to the IOMMU device state for the current context. */
625typedef CTX_SUFF(PIOMMU) PIOMMUCC;
626
627/**
628 * IOMMU register access.
629 */
630typedef struct IOMMUREGACC
631{
632 const char *pszName;
633 VBOXSTRICTRC (*pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value);
634 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
635} IOMMUREGACC;
636/** Pointer to an IOMMU register access. */
637typedef IOMMUREGACC *PIOMMUREGACC;
638/** Pointer to a const IOMMU register access. */
639typedef IOMMUREGACC const *PCIOMMUREGACC;
640
641#ifdef IOMMU_WITH_IOTLBE_CACHE
642/**
643 * IOTLBE flush argument.
644 */
645typedef struct IOTLBEFLUSHARG
646{
647 /** The ring-3 IOMMU device state. */
648 PIOMMUR3 pIommuR3;
649 /** The domain ID to flush. */
650 uint16_t idDomain;
651} IOTLBEFLUSHARG;
652/** Pointer to an IOTLBE flush argument. */
653typedef IOTLBEFLUSHARG *PIOTLBEFLUSHARG;
654/** Pointer to a const IOTLBE flush argument. */
655typedef IOTLBEFLUSHARG const *PCIOTLBEFLUSHARG;
656
657/**
658 * IOTLBE Info. argument.
659 */
660typedef struct IOTLBEINFOARG
661{
662 /** The ring-3 IOMMU device state. */
663 PIOMMUR3 pIommuR3;
664 /** The info helper. */
665 PCDBGFINFOHLP pHlp;
666 /** The domain ID to dump IOTLB entry. */
667 uint16_t idDomain;
668} IOTLBEINFOARG;
669/** Pointer to an IOTLBE flush argument. */
670typedef IOTLBEINFOARG *PIOTLBEINFOARG;
671/** Pointer to a const IOTLBE flush argument. */
672typedef IOTLBEINFOARG const *PCIOTLBEINFOARG;
673#endif
674
675/**
676 * IOMMU operation auxiliary info.
677 */
678typedef struct IOMMUOPAUX
679{
680 /** The IOMMU operation being performed. */
681 IOMMUOP enmOp;
682 /** The device table entry (can be NULL). */
683 PCDTE_T pDte;
684 /** The device ID (bus, device, function). */
685 uint16_t idDevice;
686 /** The domain ID (when the DTE isn't provided). */
687 uint16_t idDomain;
688} IOMMUOPAUX;
689/** Pointer to an I/O address lookup struct. */
690typedef IOMMUOPAUX *PIOMMUOPAUX;
691/** Pointer to a const I/O address lookup struct. */
692typedef IOMMUOPAUX const *PCIOMMUOPAUX;
693
694typedef DECLCALLBACKTYPE(int, FNIOPAGELOOKUP,(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
695 PIOPAGELOOKUP pPageLookup));
696typedef FNIOPAGELOOKUP *PFNIOPAGELOOKUP;
697
698
699/*********************************************************************************************************************************
700* Global Variables *
701*********************************************************************************************************************************/
702#ifdef IN_RING3
703/**
704 * An array of the number of device table segments supported.
705 * Indexed by u2DevTabSegSup.
706 */
707static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
708#endif
709
710#if defined(IN_RING3) || defined(LOG_ENABLED)
711/**
712 * The IOMMU I/O permission names.
713 */
714static const char * const g_aszPerm[] = { "none", "read", "write", "read+write" };
715#endif
716
717/**
718 * An array of the masks to select the device table segment index from a device ID.
719 */
720static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
721
722/**
723 * An array of the shift values to select the device table segment index from a
724 * device ID.
725 */
726static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
727
728/**
729 * The maximum size (inclusive) of each device table segment (0 to 7).
730 * Indexed by the device table segment index.
731 */
732static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
733
734
735#ifndef VBOX_DEVICE_STRUCT_TESTCASE
736/**
737 * Gets the maximum number of buffer entries for the given buffer length.
738 *
739 * @returns Number of buffer entries.
740 * @param uEncodedLen The length (power-of-2 encoded).
741 */
742DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
743{
744 Assert(uEncodedLen > 7);
745 Assert(uEncodedLen < 16);
746 return 2 << (uEncodedLen - 1);
747}
748
749
750/**
751 * Gets the total length of the buffer given a base register's encoded length.
752 *
753 * @returns The length of the buffer in bytes.
754 * @param uEncodedLen The length (power-of-2 encoded).
755 */
756DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
757{
758 Assert(uEncodedLen > 7);
759 Assert(uEncodedLen < 16);
760 return (2 << (uEncodedLen - 1)) << 4;
761}
762
763
764/**
765 * Gets the number of (unconsumed) entries in the event log.
766 *
767 * @returns The number of entries in the event log.
768 * @param pThis The shared IOMMU device state.
769 */
770static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
771{
772 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
773 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
774 if (idxTail >= idxHead)
775 return idxTail - idxHead;
776
777 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
778 return cMaxEvts - idxHead + idxTail;
779}
780
781
782#if defined(IN_RING3) || defined(LOG_ENABLED)
783/**
784 * Gets the descriptive I/O permission name for a memory access.
785 *
786 * @returns The I/O permission name.
787 * @param fPerm The I/O permissions for the access, see IOMMU_IO_PERM_XXX.
788 */
789static const char *iommuAmdMemAccessGetPermName(uint8_t fPerm)
790{
791 /* We shouldn't construct an access with "none" or "read+write" (must be read or write) permissions. */
792 Assert(fPerm > 0 && fPerm < RT_ELEMENTS(g_aszPerm));
793 return g_aszPerm[fPerm & IOMMU_IO_PERM_MASK];
794}
795#endif
796
797
798/**
799 * Checks whether two consecutive I/O page lookup results translates to a physically
800 * contiguous region.
801 *
802 * @returns @c true if they are contiguous, @c false otherwise.
803 * @param pPageLookupPrev The I/O page lookup result of the previous page.
804 * @param pPageLookup The I/O page lookup result of the current page.
805 */
806static bool iommuAmdLookupIsAccessContig(PCIOPAGELOOKUP pPageLookupPrev, PCIOPAGELOOKUP pPageLookup)
807{
808 Assert(pPageLookupPrev->fPerm == pPageLookup->fPerm);
809 size_t const cbPrev = RT_BIT_64(pPageLookupPrev->cShift);
810 RTGCPHYS const GCPhysPrev = pPageLookupPrev->GCPhysSpa;
811 RTGCPHYS const GCPhys = pPageLookup->GCPhysSpa;
812 uint64_t const offMaskPrev = IOMMU_GET_PAGE_OFF_MASK(pPageLookupPrev->cShift);
813 uint64_t const offMask = IOMMU_GET_PAGE_OFF_MASK(pPageLookup->cShift);
814
815 /* Paranoia: Ensure offset bits are 0. */
816 Assert(!(GCPhysPrev & offMaskPrev));
817 Assert(!(GCPhys & offMask));
818
819 if ((GCPhysPrev & ~offMaskPrev) + cbPrev == (GCPhys & ~offMask))
820 return true;
821 return false;
822}
823
824
825/**
826 * Gets the basic I/O device flags for the given device table entry.
827 *
828 * @returns The basic I/O device flags.
829 * @param pDte The device table entry.
830 */
831static uint16_t iommuAmdGetBasicDevFlags(PCDTE_T pDte)
832{
833 /* Extract basic flags from bits 127:0 of the DTE. */
834 uint16_t fFlags = 0;
835 if (pDte->n.u1Valid)
836 {
837 fFlags |= IOMMU_DTE_CACHE_F_VALID;
838
839 /** @todo Skip the if checks here (shift/mask the relevant bits over). */
840 if (pDte->n.u1SuppressAllPfEvents)
841 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
842 if (pDte->n.u1SuppressPfEvents)
843 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_IOPF;
844
845 uint16_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
846 AssertCompile(IOMMU_DTE_CACHE_F_IO_PERM_MASK == IOMMU_IO_PERM_MASK);
847 fFlags |= fDtePerm << IOMMU_DTE_CACHE_F_IO_PERM_SHIFT;
848 }
849
850 /* Extract basic flags from bits 255:128 of the DTE. */
851 if (pDte->n.u1IntrMapValid)
852 {
853 fFlags |= IOMMU_DTE_CACHE_F_INTR_MAP_VALID;
854
855 /** @todo Skip the if check here (shift/mask the relevant bit over). */
856 if (pDte->n.u1IgnoreUnmappedIntrs)
857 fFlags |= IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
858
859 uint16_t const fIntrCtrl = IOMMU_DTE_GET_INTR_CTRL(pDte);
860 AssertCompile(IOMMU_DTE_CACHE_F_INTR_CTRL_MASK == IOMMU_DTE_INTR_CTRL_MASK);
861 fFlags |= fIntrCtrl << IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT;
862 }
863 return fFlags;
864}
865
866
867/**
868 * Remaps the source MSI to the destination MSI given the IRTE.
869 *
870 * @param pMsiIn The source MSI.
871 * @param pMsiOut Where to store the remapped MSI.
872 * @param pIrte The IRTE used for the remapping.
873 */
874static void iommuAmdIrteRemapMsi(PCMSIMSG pMsiIn, PMSIMSG pMsiOut, PCIRTE_T pIrte)
875{
876 /* Preserve all bits from the source MSI address and data that don't map 1:1 from the IRTE. */
877 *pMsiOut = *pMsiIn;
878
879 pMsiOut->Addr.n.u1DestMode = pIrte->n.u1DestMode;
880 pMsiOut->Addr.n.u8DestId = pIrte->n.u8Dest;
881
882 pMsiOut->Data.n.u8Vector = pIrte->n.u8Vector;
883 pMsiOut->Data.n.u3DeliveryMode = pIrte->n.u3IntrType;
884}
885
886
887#ifdef IOMMU_WITH_DTE_CACHE
888/**
889 * Looks up an entry in the DTE cache for the given device ID.
890 *
891 * @returns The index of the entry, or the cache capacity if no entry was found.
892 * @param pThis The shared IOMMU device state.
893 * @param idDevice The device ID (bus, device, function).
894 */
895DECLINLINE(uint16_t) iommuAmdDteCacheEntryLookup(PIOMMU pThis, uint16_t idDevice)
896{
897 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
898 for (uint16_t i = 0; i < cDeviceIds; i++)
899 {
900 if (pThis->aDeviceIds[i] == idDevice)
901 return i;
902 }
903 return cDeviceIds;
904}
905
906
907/**
908 * Gets an free/unused DTE cache entry.
909 *
910 * @returns The index of an unused entry, or cache capacity if the cache is full.
911 * @param pThis The shared IOMMU device state.
912 */
913DECLINLINE(uint16_t) iommuAmdDteCacheEntryGetUnused(PCIOMMU pThis)
914{
915 /*
916 * ASSUMES device ID 0 is the PCI host bridge or the IOMMU itself
917 * (the latter being an ugly hack) and cannot be a valid device ID.
918 */
919 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
920 for (uint16_t i = 0; i < cDeviceIds; i++)
921 {
922 if (!pThis->aDeviceIds[i])
923 return i;
924 }
925 return cDeviceIds;
926}
927
928
929/**
930 * Adds or updates the I/O device flags for the given device ID.
931 *
932 * @returns VBox status code.
933 * @retval VERR_OUT_OF_RESOURCES if the cache is full.
934 *
935 * @param pDevIns The IOMMU instance data.
936 * @param idDevice The device ID (bus, device, function).
937 * @param pDte The device table entry.
938 * @param fOrMask The device flags (usually compound flags) to OR in with the
939 * basic flags, see IOMMU_DTE_CACHE_F_XXX.
940 */
941static int iommuAmdDteCacheAdd(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, uint16_t fOrMask)
942{
943 Assert(pDte);
944 Assert(idDevice);
945
946 int rc = VINF_SUCCESS;
947 uint16_t const fFlags = iommuAmdGetBasicDevFlags(pDte) | IOMMU_DTE_CACHE_F_PRESENT | fOrMask;
948 uint16_t const idDomain = pDte->n.u16DomainId;
949
950 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
951 IOMMU_CACHE_LOCK(pDevIns, pThis);
952
953 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
954 uint16_t idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
955 if (idxDte < cDteCache)
956 {
957 pThis->aDteCache[idxDte].fFlags = fFlags;
958 pThis->aDteCache[idxDte].idDomain = idDomain;
959 }
960 else if ((idxDte = iommuAmdDteCacheEntryGetUnused(pThis)) < cDteCache)
961 {
962 pThis->aDeviceIds[idxDte] = idDevice;
963 pThis->aDteCache[idxDte].fFlags = fFlags;
964 pThis->aDteCache[idxDte].idDomain = idDomain;
965 }
966 else
967 rc = VERR_OUT_OF_RESOURCES;
968
969 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
970 return rc;
971}
972
973
974/**
975 * Adds one or more I/O device flags if the device is already present in the cache.
976 *
977 * @param pDevIns The IOMMU instance data.
978 * @param idDevice The device ID (bus, device, function).
979 * @param fFlags Additional device flags to OR with existing flags, see
980 * IOMMU_DTE_CACHE_F_XXX.
981 */
982static void iommuAmdDteCacheAddFlags(PPDMDEVINS pDevIns, uint16_t idDevice, uint16_t fFlags)
983{
984 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
985 IOMMU_CACHE_LOCK(pDevIns, pThis);
986
987 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
988 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
989 if ( idxDte < cDteCache
990 && (pThis->aDteCache[idxDte].fFlags & IOMMU_DTE_CACHE_F_PRESENT))
991 pThis->aDteCache[idxDte].fFlags |= fFlags;
992
993 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
994}
995
996
997# ifdef IN_RING3
998/**
999 * Removes a DTE cache entry.
1000 *
1001 * @param pDevIns The IOMMU instance data.
1002 * @param idDevice The device ID to remove cache entries for.
1003 */
1004static void iommuAmdDteCacheRemove(PPDMDEVINS pDevIns, uint16_t idDevice)
1005{
1006 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1007 IOMMU_CACHE_LOCK(pDevIns, pThis);
1008
1009 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
1010 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
1011 if (idxDte < cDteCache)
1012 {
1013 pThis->aDteCache[idxDte].fFlags = 0;
1014 pThis->aDteCache[idxDte].idDomain = 0;
1015 }
1016
1017 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1018}
1019
1020
1021/**
1022 * Removes all entries in the device table entry cache.
1023 *
1024 * @param pDevIns The IOMMU instance data.
1025 */
1026static void iommuAmdDteCacheRemoveAll(PPDMDEVINS pDevIns)
1027{
1028 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1029 IOMMU_CACHE_LOCK(pDevIns, pThis);
1030 RT_ZERO(pThis->aDeviceIds);
1031 RT_ZERO(pThis->aDteCache);
1032 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1033}
1034# endif /* IN_RING3 */
1035#endif /* IOMMU_WITH_DTE_CACHE */
1036
1037
1038#ifdef IOMMU_WITH_IOTLBE_CACHE
1039/**
1040 * Moves the IOTLB entry to the least recently used slot.
1041 *
1042 * @param pThisR3 The ring-3 IOMMU device state.
1043 * @param pIotlbe The IOTLB entry to move.
1044 */
1045DECLINLINE(void) iommuAmdIotlbEntryMoveToLru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1046{
1047 if (!RTListNodeIsFirst(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1048 {
1049 RTListNodeRemove(&pIotlbe->NdLru);
1050 RTListPrepend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1051 }
1052}
1053
1054
1055/**
1056 * Moves the IOTLB entry to the most recently used slot.
1057 *
1058 * @param pThisR3 The ring-3 IOMMU device state.
1059 * @param pIotlbe The IOTLB entry to move.
1060 */
1061DECLINLINE(void) iommuAmdIotlbEntryMoveToMru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1062{
1063 if (!RTListNodeIsLast(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1064 {
1065 RTListNodeRemove(&pIotlbe->NdLru);
1066 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1067 }
1068}
1069
1070
1071# ifdef IN_RING3
1072/**
1073 * Dumps the IOTLB entry via the debug info helper.
1074 *
1075 * @returns VINF_SUCCESS.
1076 * @param pNode Pointer to an IOTLB entry to dump info.
1077 * @param pvUser Pointer to an IOTLBEINFOARG.
1078 */
1079static DECLCALLBACK(int) iommuAmdR3IotlbEntryInfo(PAVLU64NODECORE pNode, void *pvUser)
1080{
1081 /* Validate. */
1082 PCIOTLBEINFOARG pArgs = (PCIOTLBEINFOARG)pvUser;
1083 AssertPtr(pArgs);
1084 AssertPtr(pArgs->pIommuR3);
1085 AssertPtr(pArgs->pHlp);
1086 //Assert(pArgs->pIommuCC->u32Magic == IOMMU_MAGIC);
1087
1088 uint16_t const idDomain = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1089 if (idDomain == pArgs->idDomain)
1090 {
1091 PCIOTLBE pIotlbe = (PCIOTLBE)pNode;
1092 AVLU64KEY const uKey = pIotlbe->Core.Key;
1093 uint64_t const uIova = IOMMU_IOTLB_KEY_GET_IOVA(uKey);
1094 RTGCPHYS const GCPhysSpa = pIotlbe->PageLookup.GCPhysSpa;
1095 uint8_t const cShift = pIotlbe->PageLookup.cShift;
1096 size_t const cbPage = RT_BIT_64(cShift);
1097 uint8_t const fPerm = pIotlbe->PageLookup.fPerm;
1098 const char *pszPerm = iommuAmdMemAccessGetPermName(fPerm);
1099 bool const fEvictPending = pIotlbe->fEvictPending;
1100
1101 PCDBGFINFOHLP pHlp = pArgs->pHlp;
1102 pHlp->pfnPrintf(pHlp, " Key = %#RX64 (%#RX64)\n", uKey, uIova);
1103 pHlp->pfnPrintf(pHlp, " GCPhys = %#RGp\n", GCPhysSpa);
1104 pHlp->pfnPrintf(pHlp, " cShift = %u (%zu bytes)\n", cShift, cbPage);
1105 pHlp->pfnPrintf(pHlp, " fPerm = %#x (%s)\n", fPerm, pszPerm);
1106 pHlp->pfnPrintf(pHlp, " fEvictPending = %RTbool\n", fEvictPending);
1107 }
1108
1109 return VINF_SUCCESS;
1110}
1111# endif /* IN_RING3 */
1112
1113
1114/**
1115 * Removes the IOTLB entry if it's associated with the specified domain ID.
1116 *
1117 * @returns VINF_SUCCESS.
1118 * @param pNode Pointer to an IOTLBE.
1119 * @param pvUser Pointer to an IOTLBEFLUSHARG containing the domain ID.
1120 */
1121static DECLCALLBACK(int) iommuAmdIotlbEntryRemoveDomainId(PAVLU64NODECORE pNode, void *pvUser)
1122{
1123 /* Validate. */
1124 PCIOTLBEFLUSHARG pArgs = (PCIOTLBEFLUSHARG)pvUser;
1125 AssertPtr(pArgs);
1126 AssertPtr(pArgs->pIommuR3);
1127 //Assert(pArgs->pIommuR3->u32Magic == IOMMU_MAGIC);
1128
1129 uint16_t const idDomain = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1130 if (idDomain == pArgs->idDomain)
1131 {
1132 /* Mark this entry is as invalidated and needs to be evicted later. */
1133 PIOTLBE pIotlbe = (PIOTLBE)pNode;
1134 pIotlbe->fEvictPending = true;
1135 iommuAmdIotlbEntryMoveToLru(pArgs->pIommuR3, (PIOTLBE)pNode);
1136 }
1137 return VINF_SUCCESS;
1138}
1139
1140
1141/**
1142 * Inserts an IOTLB entry into the cache.
1143 *
1144 * @param pThis The shared IOMMU device state.
1145 * @param pThisR3 The ring-3 IOMMU device state.
1146 * @param pIotlbe The IOTLB entry to initialize and insert.
1147 * @param idDomain The domain ID.
1148 * @param uIova The I/O virtual address.
1149 * @param pPageLookup The I/O page lookup result of the access.
1150 */
1151static void iommuAmdIotlbEntryInsert(PIOMMU pThis, PIOMMUR3 pThisR3, PIOTLBE pIotlbe, uint16_t idDomain, uint64_t uIova,
1152 PCIOPAGELOOKUP pPageLookup)
1153{
1154 /* Initialize the IOTLB entry with results of the I/O page walk. */
1155 pIotlbe->Core.Key = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1156 pIotlbe->PageLookup = *pPageLookup;
1157
1158 /* Validate. */
1159 Assert(pIotlbe->Core.Key != IOMMU_IOTLB_KEY_NIL);
1160 Assert(!pIotlbe->fEvictPending);
1161
1162 /* Check if the entry already exists. */
1163 PIOTLBE pFound = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, pIotlbe->Core.Key);
1164 if (!pFound)
1165 {
1166 /* Insert the entry into the cache. */
1167 bool const fInserted = RTAvlU64Insert(&pThisR3->TreeIotlbe, &pIotlbe->Core);
1168 Assert(fInserted); NOREF(fInserted);
1169 Assert(pThisR3->cCachedIotlbes < IOMMU_IOTLBE_MAX);
1170 ++pThisR3->cCachedIotlbes;
1171 STAM_COUNTER_INC(&pThis->StatIotlbeCached); NOREF(pThis);
1172 }
1173 else
1174 {
1175 /* Update the existing entry. */
1176 if (pFound->fEvictPending)
1177 {
1178 pFound->fEvictPending = false;
1179 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse); NOREF(pThis);
1180 }
1181 Assert(pFound->PageLookup.cShift == pPageLookup->cShift);
1182 pFound->PageLookup.fPerm = pPageLookup->fPerm;
1183 pFound->PageLookup.GCPhysSpa = pPageLookup->GCPhysSpa;
1184 }
1185}
1186
1187
1188/**
1189 * Removes an IOTLB entry from the cache for the given key.
1190 *
1191 * @returns Pointer to the removed IOTLB entry, NULL if the entry wasn't found in
1192 * the tree.
1193 * @param pThis The shared IOMMU device state.
1194 * @param pThisR3 The ring-3 IOMMU device state.
1195 * @param uKey The key of the IOTLB entry to remove.
1196 */
1197static PIOTLBE iommuAmdIotlbEntryRemove(PIOMMU pThis, PIOMMUR3 pThisR3, AVLU64KEY uKey)
1198{
1199 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Remove(&pThisR3->TreeIotlbe, uKey);
1200 if (pIotlbe)
1201 {
1202 if (pIotlbe->fEvictPending)
1203 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse);
1204
1205 RT_ZERO(pIotlbe->Core);
1206 RT_ZERO(pIotlbe->PageLookup);
1207 /* We must not erase the LRU node connections here! */
1208 pIotlbe->fEvictPending = false;
1209 Assert(pIotlbe->Core.Key == IOMMU_IOTLB_KEY_NIL);
1210
1211 Assert(pThisR3->cCachedIotlbes > 0);
1212 --pThisR3->cCachedIotlbes;
1213 STAM_COUNTER_DEC(&pThis->StatIotlbeCached); NOREF(pThis);
1214 }
1215 return pIotlbe;
1216}
1217
1218
1219/**
1220 * Looks up an IOTLB from the cache.
1221 *
1222 * @returns Pointer to IOTLB entry if found, NULL otherwise.
1223 * @param pThis The shared IOMMU device state.
1224 * @param pThisR3 The ring-3 IOMMU device state.
1225 * @param idDomain The domain ID.
1226 * @param uIova The I/O virtual address.
1227 */
1228static PIOTLBE iommuAmdIotlbLookup(PIOMMU pThis, PIOMMUR3 pThisR3, uint64_t idDomain, uint64_t uIova)
1229{
1230 RT_NOREF(pThis);
1231
1232 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1233 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, uKey);
1234 if ( pIotlbe
1235 && !pIotlbe->fEvictPending)
1236 return pIotlbe;
1237
1238 /*
1239 * Domain Id wildcard invalidations only marks entries for eviction later but doesn't remove
1240 * them from the cache immediately. We found an entry pending eviction, just return that
1241 * nothing was found (rather than evicting now).
1242 */
1243 return NULL;
1244}
1245
1246
1247/**
1248 * Adds an IOTLB entry to the cache.
1249 *
1250 * @param pThis The shared IOMMU device state.
1251 * @param pThisR3 The ring-3 IOMMU device state.
1252 * @param idDomain The domain ID.
1253 * @param uIova The I/O virtual address.
1254 * @param pPageLookup The I/O page lookup result of the access.
1255 */
1256static void iommuAmdIotlbAdd(PIOMMU pThis, PIOMMUR3 pThisR3, uint16_t idDomain, uint64_t uIova, PCIOPAGELOOKUP pPageLookup)
1257{
1258 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1259 Assert(pPageLookup);
1260 Assert(pPageLookup->cShift <= 31);
1261 Assert(pPageLookup->fPerm != IOMMU_IO_PERM_NONE);
1262
1263 /*
1264 * If there are no unused IOTLB entries, evict the LRU entry.
1265 * Otherwise, get a new IOTLB entry from the pre-allocated list.
1266 */
1267 if (pThisR3->idxUnusedIotlbe == IOMMU_IOTLBE_MAX)
1268 {
1269 /* Grab the least recently used entry. */
1270 PIOTLBE pIotlbe = RTListGetFirst(&pThisR3->LstLruIotlbe, IOTLBE, NdLru);
1271 Assert(pIotlbe);
1272
1273 /* If the entry is in the cache, remove it. */
1274 if (pIotlbe->Core.Key != IOMMU_IOTLB_KEY_NIL)
1275 iommuAmdIotlbEntryRemove(pThis, pThisR3, pIotlbe->Core.Key);
1276
1277 /* Initialize and insert the IOTLB entry into the cache. */
1278 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, idDomain, uIova, pPageLookup);
1279
1280 /* Move the entry to the most recently used slot. */
1281 iommuAmdIotlbEntryMoveToMru(pThisR3, pIotlbe);
1282 }
1283 else
1284 {
1285 /* Grab an unused IOTLB entry from the pre-allocated list. */
1286 PIOTLBE pIotlbe = &pThisR3->paIotlbes[pThisR3->idxUnusedIotlbe];
1287 ++pThisR3->idxUnusedIotlbe;
1288
1289 /* Initialize and insert the IOTLB entry into the cache. */
1290 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, idDomain, uIova, pPageLookup);
1291
1292 /* Add the entry to the most recently used slot. */
1293 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1294 }
1295}
1296
1297
1298/**
1299 * Removes all IOTLB entries from the cache.
1300 *
1301 * @param pDevIns The IOMMU instance data.
1302 */
1303static void iommuAmdIotlbRemoveAll(PPDMDEVINS pDevIns)
1304{
1305 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1306 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1307 IOMMU_CACHE_LOCK(pDevIns, pThis);
1308
1309 if (pThisR3->cCachedIotlbes > 0)
1310 {
1311 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
1312 RT_BZERO(pThisR3->paIotlbes, cbIotlbes);
1313 pThisR3->idxUnusedIotlbe = 0;
1314 pThisR3->cCachedIotlbes = 0;
1315 STAM_COUNTER_RESET(&pThis->StatIotlbeCached);
1316 RTListInit(&pThisR3->LstLruIotlbe);
1317 }
1318
1319 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1320}
1321
1322
1323/**
1324 * Removes IOTLB entries for the range of I/O virtual addresses and the specified
1325 * domain ID from the cache.
1326 *
1327 * @param pDevIns The IOMMU instance data.
1328 * @param idDomain The domain ID.
1329 * @param uIova The I/O virtual address to invalidate.
1330 * @param cbInvalidate The size of the invalidation (must be 4K aligned).
1331 */
1332static void iommuAmdIotlbRemoveRange(PPDMDEVINS pDevIns, uint16_t idDomain, uint64_t uIova, size_t cbInvalidate)
1333{
1334 /* Validate. */
1335 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1336 Assert(!(cbInvalidate & X86_PAGE_4K_OFFSET_MASK));
1337 Assert(cbInvalidate >= X86_PAGE_4K_SIZE);
1338
1339 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1340 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1341 IOMMU_CACHE_LOCK(pDevIns, pThis);
1342
1343 do
1344 {
1345 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1346 PIOTLBE pIotlbe = iommuAmdIotlbEntryRemove(pThis, pThisR3, uKey);
1347 if (pIotlbe)
1348 iommuAmdIotlbEntryMoveToLru(pThisR3, pIotlbe);
1349 uIova += X86_PAGE_4K_SIZE;
1350 cbInvalidate -= X86_PAGE_4K_SIZE;
1351 } while (cbInvalidate > 0);
1352
1353 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1354}
1355
1356
1357/**
1358 * Removes all IOTLB entries for the specified domain ID.
1359 *
1360 * @param pDevIns The IOMMU instance data.
1361 * @param idDomain The domain ID.
1362 */
1363static void iommuAmdIotlbRemoveDomainId(PPDMDEVINS pDevIns, uint16_t idDomain)
1364{
1365 /*
1366 * We need to iterate the tree and search based on the domain ID.
1367 * But it seems we cannot remove items while iterating the tree.
1368 * Thus, we simply mark entries for eviction later but move them to the LRU
1369 * so they will eventually get evicted and re-cycled as the cache gets re-populated.
1370 */
1371 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1372 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1373 IOMMU_CACHE_LOCK(pDevIns, pThis);
1374
1375 IOTLBEFLUSHARG Args;
1376 Args.pIommuR3 = pThisR3;
1377 Args.idDomain = idDomain;
1378 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdIotlbEntryRemoveDomainId, &Args);
1379
1380 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1381}
1382
1383
1384/**
1385 * Adds or updates IOTLB entries for the given range of I/O virtual addresses.
1386 *
1387 * @param pDevIns The IOMMU instance data.
1388 * @param idDomain The domain ID.
1389 * @param uIova The I/O virtual address.
1390 * @param cbIova The size of the access (must be 4K aligned).
1391 * @param GCPhysSpa The translated system-physical address.
1392 * @param fPerm The I/O permissions for the access, see IOMMU_IO_PERM_XXX.
1393 */
1394static void iommuAmdIotlbAddRange(PPDMDEVINS pDevIns, uint16_t idDomain, uint64_t uIova, size_t cbIova, RTGCPHYS GCPhysSpa,
1395 uint8_t fPerm)
1396{
1397 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1398 Assert(!(GCPhysSpa & X86_PAGE_4K_OFFSET_MASK));
1399 Assert(!(cbIova & X86_PAGE_4K_OFFSET_MASK));
1400 Assert(cbIova >= X86_PAGE_4K_SIZE);
1401
1402 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1403 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1404
1405 /* Add IOTLB entries for every page in the access. */
1406 IOPAGELOOKUP PageLookup;
1407 RT_ZERO(PageLookup);
1408 PageLookup.cShift = X86_PAGE_4K_SHIFT;
1409 PageLookup.fPerm = fPerm;
1410 PageLookup.GCPhysSpa = GCPhysSpa;
1411
1412 size_t cPages = cbIova / X86_PAGE_4K_SIZE;
1413 cPages = RT_MIN(cPages, IOMMU_IOTLBE_MAX);
1414
1415 IOMMU_CACHE_LOCK(pDevIns, pThis);
1416 /** @todo Re-check DTE cache? */
1417 do
1418 {
1419 iommuAmdIotlbAdd(pThis, pThisR3, idDomain, uIova, &PageLookup);
1420 uIova += X86_PAGE_4K_SIZE;
1421 PageLookup.GCPhysSpa += X86_PAGE_4K_SIZE;
1422 --cPages;
1423 } while (cPages > 0);
1424 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1425}
1426#endif /* IOMMU_WITH_IOTLBE_CACHE */
1427
1428
1429#ifdef IOMMU_WITH_IRTE_CACHE
1430/**
1431 * Looks up an IRTE cache entry.
1432 *
1433 * @returns Index of the found entry, or cache capacity if not found.
1434 * @param pThis The shared IOMMU device state.
1435 * @param idDevice The device ID (bus, device, function).
1436 * @param offIrte The offset into the interrupt remap table.
1437 */
1438static uint16_t iommuAmdIrteCacheEntryLookup(PCIOMMU pThis, uint16_t idDevice, uint16_t offIrte)
1439{
1440 /** @todo Consider sorting and binary search when the cache capacity grows.
1441 * For the IRTE cache this should be okay since typically guests do not alter the
1442 * interrupt remapping once programmed, so hopefully sorting shouldn't happen
1443 * often. */
1444 uint32_t const uKey = IOMMU_IRTE_CACHE_KEY_MAKE(idDevice, offIrte);
1445 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1446 for (uint16_t i = 0; i < cIrteCache; i++)
1447 if (pThis->aIrteCache[i].uKey == uKey)
1448 return i;
1449 return cIrteCache;
1450}
1451
1452
1453/**
1454 * Gets a free/unused IRTE cache entry.
1455 *
1456 * @returns The index of an unused entry, or cache capacity if the cache is full.
1457 * @param pThis The shared IOMMU device state.
1458 */
1459static uint16_t iommuAmdIrteCacheEntryGetUnused(PCIOMMU pThis)
1460{
1461 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1462 for (uint16_t i = 0; i < cIrteCache; i++)
1463 if (pThis->aIrteCache[i].uKey == IOMMU_IRTE_CACHE_KEY_NIL)
1464 {
1465 Assert(!pThis->aIrteCache[i].Irte.u32);
1466 return i;
1467 }
1468 return cIrteCache;
1469}
1470
1471
1472/**
1473 * Looks up the IRTE cache for the given MSI.
1474 *
1475 * @returns VBox status code.
1476 * @param pDevIns The IOMMU instance data.
1477 * @param idDevice The device ID (bus, device, function).
1478 * @param enmOp The IOMMU operation being performed.
1479 * @param pMsiIn The source MSI.
1480 * @param pMsiOut Where to store the remapped MSI.
1481 */
1482static int iommuAmdIrteCacheLookup(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1483{
1484 RT_NOREF(enmOp); /* May need it if we have to report errors (currently we fallback to the slower path to do that). */
1485
1486 int rc = VERR_NOT_FOUND;
1487 /* Deal with such cases in the slower/fallback path. */
1488 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
1489 { /* likely */ }
1490 else
1491 return rc;
1492
1493 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1494 IOMMU_CACHE_LOCK(pDevIns, pThis);
1495
1496 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, idDevice);
1497 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
1498 {
1499 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
1500 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1501 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1502 {
1503 Assert((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE); /* Paranoia. */
1504
1505 /* Currently, we only cache remapping of fixed and arbitrated interrupts. */
1506 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
1507 if (u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
1508 {
1509 uint8_t const uIntrCtrl = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT)
1510 & IOMMU_DTE_CACHE_F_INTR_CTRL_MASK;
1511 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
1512 {
1513 /* Interrupt table length has been verified prior to adding entries to the cache. */
1514 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(pMsiIn->Data.u32);
1515 uint16_t const idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, idDevice, offIrte);
1516 if (idxIrteCache < RT_ELEMENTS(pThis->aIrteCache))
1517 {
1518 PCIRTE_T pIrte = &pThis->aIrteCache[idxIrteCache].Irte;
1519 Assert(pIrte->n.u1RemapEnable);
1520 Assert(pIrte->n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO);
1521 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, pIrte);
1522 rc = VINF_SUCCESS;
1523 }
1524 }
1525 else if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
1526 {
1527 *pMsiOut = *pMsiIn;
1528 rc = VINF_SUCCESS;
1529 }
1530 }
1531 }
1532 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
1533 {
1534 *pMsiOut = *pMsiIn;
1535 rc = VINF_SUCCESS;
1536 }
1537 }
1538
1539 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1540 return rc;
1541}
1542
1543
1544/**
1545 * Adds or updates the IRTE cache for the given IRTE.
1546 *
1547 * @returns VBox status code.
1548 * @retval VERR_OUT_OF_RESOURCES if the cache is full.
1549 *
1550 * @param pDevIns The IOMMU instance data.
1551 * @param idDevice The device ID (bus, device, function).
1552 * @param offIrte The offset into the interrupt remap table.
1553 * @param pIrte The IRTE to cache.
1554 */
1555static int iommuAmdIrteCacheAdd(PPDMDEVINS pDevIns, uint16_t idDevice, uint16_t offIrte, PCIRTE_T pIrte)
1556{
1557 Assert(offIrte != 0xffff); /* Shouldn't be a valid IRTE table offset since sizeof(IRTE) is a multiple of 4. */
1558
1559 int rc = VINF_SUCCESS;
1560 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1561 IOMMU_CACHE_LOCK(pDevIns, pThis);
1562
1563 /* Find an existing entry or get an unused slot. */
1564 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1565 uint16_t idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, idDevice, offIrte);
1566 if ( idxIrteCache < cIrteCache
1567 || (idxIrteCache = iommuAmdIrteCacheEntryGetUnused(pThis)) < cIrteCache)
1568 {
1569 pThis->aIrteCache[idxIrteCache].uKey = IOMMU_IRTE_CACHE_KEY_MAKE(idDevice, offIrte);
1570 pThis->aIrteCache[idxIrteCache].Irte = *pIrte;
1571 }
1572 else
1573 rc = VERR_OUT_OF_RESOURCES;
1574
1575 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1576 return rc;
1577}
1578
1579
1580# ifdef IN_RING3
1581/**
1582 * Removes IRTE cache entries for the given device ID.
1583 *
1584 * @param pDevIns The IOMMU instance data.
1585 * @param idDevice The device ID (bus, device, function).
1586 */
1587static void iommuAmdIrteCacheRemove(PPDMDEVINS pDevIns, uint16_t idDevice)
1588{
1589 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1590 IOMMU_CACHE_LOCK(pDevIns, pThis);
1591 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1592 for (uint16_t i = 0; i < cIrteCache; i++)
1593 {
1594 PIRTECACHE pIrteCache = &pThis->aIrteCache[i];
1595 if (idDevice == IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(pIrteCache->uKey))
1596 {
1597 pIrteCache->uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1598 pIrteCache->Irte.u32 = 0;
1599 /* There could multiple IRTE entries for a device ID, continue searching. */
1600 }
1601 }
1602 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1603}
1604
1605
1606/**
1607 * Removes all IRTE cache entries.
1608 *
1609 * @param pDevIns The IOMMU instance data.
1610 */
1611static void iommuAmdIrteCacheRemoveAll(PPDMDEVINS pDevIns)
1612{
1613 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1614 IOMMU_CACHE_LOCK(pDevIns, pThis);
1615 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1616 for (uint16_t i = 0; i < cIrteCache; i++)
1617 {
1618 pThis->aIrteCache[i].uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1619 pThis->aIrteCache[i].Irte.u32 = 0;
1620 }
1621 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1622}
1623# endif /* IN_RING3 */
1624#endif /* IOMMU_WITH_IRTE_CACHE */
1625
1626
1627/**
1628 * Atomically reads the control register without locking the IOMMU device.
1629 *
1630 * @returns The control register.
1631 * @param pThis The shared IOMMU device state.
1632 */
1633DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrlUnlocked(PCIOMMU pThis)
1634{
1635 IOMMU_CTRL_T Ctrl;
1636 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
1637 return Ctrl;
1638}
1639
1640
1641/**
1642 * Returns whether MSI is enabled for the IOMMU.
1643 *
1644 * @returns Whether MSI is enabled.
1645 * @param pDevIns The IOMMU device instance.
1646 *
1647 * @note There should be a PCIDevXxx function for this.
1648 */
1649static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
1650{
1651 MSI_CAP_HDR_T MsiCapHdr;
1652 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
1653 return MsiCapHdr.n.u1MsiEnable;
1654}
1655
1656
1657/**
1658 * Signals a PCI target abort.
1659 *
1660 * @param pDevIns The IOMMU device instance.
1661 */
1662static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
1663{
1664 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1665 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
1666 PDMPciDevSetStatus(pPciDev, u16Status);
1667}
1668
1669
1670/**
1671 * Wakes up the command thread if there are commands to be processed.
1672 *
1673 * @param pDevIns The IOMMU device instance.
1674 *
1675 * @remarks The IOMMU lock must be held while calling this!
1676 */
1677static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1678{
1679 Log4Func(("\n"));
1680
1681 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1682 if ( pThis->Status.n.u1CmdBufRunning
1683 && pThis->CmdBufTailPtr.n.off != pThis->CmdBufHeadPtr.n.off
1684 && !ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, true))
1685 {
1686 Log4Func(("Signaling command thread\n"));
1687 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
1688 }
1689}
1690
1691
1692/**
1693 * Reads the Device Table Base Address Register.
1694 */
1695static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1696{
1697 RT_NOREF(pDevIns, offReg);
1698 *pu64Value = pThis->aDevTabBaseAddrs[0].u64;
1699 return VINF_SUCCESS;
1700}
1701
1702
1703/**
1704 * Reads the Command Buffer Base Address Register.
1705 */
1706static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1707{
1708 RT_NOREF(pDevIns, offReg);
1709 *pu64Value = pThis->CmdBufBaseAddr.u64;
1710 return VINF_SUCCESS;
1711}
1712
1713
1714/**
1715 * Reads the Event Log Base Address Register.
1716 */
1717static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1718{
1719 RT_NOREF(pDevIns, offReg);
1720 *pu64Value = pThis->EvtLogBaseAddr.u64;
1721 return VINF_SUCCESS;
1722}
1723
1724
1725/**
1726 * Reads the Control Register.
1727 */
1728static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1729{
1730 RT_NOREF(pDevIns, offReg);
1731 *pu64Value = pThis->Ctrl.u64;
1732 return VINF_SUCCESS;
1733}
1734
1735
1736/**
1737 * Reads the Exclusion Range Base Address Register.
1738 */
1739static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1740{
1741 RT_NOREF(pDevIns, offReg);
1742 *pu64Value = pThis->ExclRangeBaseAddr.u64;
1743 return VINF_SUCCESS;
1744}
1745
1746
1747/**
1748 * Reads to the Exclusion Range Limit Register.
1749 */
1750static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1751{
1752 RT_NOREF(pDevIns, offReg);
1753 *pu64Value = pThis->ExclRangeLimit.u64;
1754 return VINF_SUCCESS;
1755}
1756
1757
1758/**
1759 * Reads to the Extended Feature Register.
1760 */
1761static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1762{
1763 RT_NOREF(pDevIns, offReg);
1764 *pu64Value = pThis->ExtFeat.u64;
1765 return VINF_SUCCESS;
1766}
1767
1768
1769/**
1770 * Reads to the PPR Log Base Address Register.
1771 */
1772static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1773{
1774 RT_NOREF(pDevIns, offReg);
1775 *pu64Value = pThis->PprLogBaseAddr.u64;
1776 return VINF_SUCCESS;
1777}
1778
1779
1780/**
1781 * Writes the Hardware Event Register (Hi).
1782 */
1783static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1784{
1785 RT_NOREF(pDevIns, offReg);
1786 *pu64Value = pThis->HwEvtHi.u64;
1787 return VINF_SUCCESS;
1788}
1789
1790
1791/**
1792 * Reads the Hardware Event Register (Lo).
1793 */
1794static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1795{
1796 RT_NOREF(pDevIns, offReg);
1797 *pu64Value = pThis->HwEvtLo;
1798 return VINF_SUCCESS;
1799}
1800
1801
1802/**
1803 * Reads the Hardware Event Status Register.
1804 */
1805static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1806{
1807 RT_NOREF(pDevIns, offReg);
1808 *pu64Value = pThis->HwEvtStatus.u64;
1809 return VINF_SUCCESS;
1810}
1811
1812
1813/**
1814 * Reads to the GA Log Base Address Register.
1815 */
1816static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1817{
1818 RT_NOREF(pDevIns, offReg);
1819 *pu64Value = pThis->GALogBaseAddr.u64;
1820 return VINF_SUCCESS;
1821}
1822
1823
1824/**
1825 * Reads to the PPR Log B Base Address Register.
1826 */
1827static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1828{
1829 RT_NOREF(pDevIns, offReg);
1830 *pu64Value = pThis->PprLogBBaseAddr.u64;
1831 return VINF_SUCCESS;
1832}
1833
1834
1835/**
1836 * Reads to the Event Log B Base Address Register.
1837 */
1838static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1839{
1840 RT_NOREF(pDevIns, offReg);
1841 *pu64Value = pThis->EvtLogBBaseAddr.u64;
1842 return VINF_SUCCESS;
1843}
1844
1845
1846/**
1847 * Reads the Device Table Segment Base Address Register.
1848 */
1849static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1850{
1851 RT_NOREF(pDevIns);
1852
1853 /* Figure out which segment is being written. */
1854 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1855 uint8_t const idxSegment = offSegment + 1;
1856 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1857
1858 *pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
1859 return VINF_SUCCESS;
1860}
1861
1862
1863/**
1864 * Reads the Device Specific Feature Extension (DSFX) Register.
1865 */
1866static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1867{
1868 RT_NOREF(pDevIns, offReg);
1869 *pu64Value = pThis->DevSpecificFeat.u64;
1870 return VINF_SUCCESS;
1871}
1872
1873/**
1874 * Reads the Device Specific Control Extension (DSCX) Register.
1875 */
1876static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1877{
1878 RT_NOREF(pDevIns, offReg);
1879 *pu64Value = pThis->DevSpecificCtrl.u64;
1880 return VINF_SUCCESS;
1881}
1882
1883
1884/**
1885 * Reads the Device Specific Status Extension (DSSX) Register.
1886 */
1887static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1888{
1889 RT_NOREF(pDevIns, offReg);
1890 *pu64Value = pThis->DevSpecificStatus.u64;
1891 return VINF_SUCCESS;
1892}
1893
1894
1895/**
1896 * Reads the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1897 */
1898static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1899{
1900 RT_NOREF(pDevIns, offReg);
1901 uint32_t const uLo = pThis->MiscInfo.au32[0];
1902 uint32_t const uHi = pThis->MiscInfo.au32[1];
1903 *pu64Value = RT_MAKE_U64(uLo, uHi);
1904 return VINF_SUCCESS;
1905}
1906
1907
1908/**
1909 * Reads the MSI Capability Header Register (32-bit) and the MSI Address (Lo)
1910 * Register (32-bit).
1911 */
1912static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1913{
1914 RT_NOREF(pThis, offReg);
1915 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1916 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1917 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1918 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1919 *pu64Value = RT_MAKE_U64(uLo, uHi);
1920 return VINF_SUCCESS;
1921}
1922
1923
1924/**
1925 * Reads the MSI Address (Hi) Register (32-bit) and the MSI data register (32-bit).
1926 */
1927static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1928{
1929 RT_NOREF(pThis, offReg);
1930 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1931 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1932 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1933 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1934 *pu64Value = RT_MAKE_U64(uLo, uHi);
1935 return VINF_SUCCESS;
1936}
1937
1938
1939/**
1940 * Reads the Command Buffer Head Pointer Register.
1941 */
1942static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1943{
1944 RT_NOREF(pDevIns, offReg);
1945 *pu64Value = pThis->CmdBufHeadPtr.u64;
1946 return VINF_SUCCESS;
1947}
1948
1949
1950/**
1951 * Reads the Command Buffer Tail Pointer Register.
1952 */
1953static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1954{
1955 RT_NOREF(pDevIns, offReg);
1956 *pu64Value = pThis->CmdBufTailPtr.u64;
1957 return VINF_SUCCESS;
1958}
1959
1960
1961/**
1962 * Reads the Event Log Head Pointer Register.
1963 */
1964static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1965{
1966 RT_NOREF(pDevIns, offReg);
1967 *pu64Value = pThis->EvtLogHeadPtr.u64;
1968 return VINF_SUCCESS;
1969}
1970
1971
1972/**
1973 * Reads the Event Log Tail Pointer Register.
1974 */
1975static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1976{
1977 RT_NOREF(pDevIns, offReg);
1978 *pu64Value = pThis->EvtLogTailPtr.u64;
1979 return VINF_SUCCESS;
1980}
1981
1982
1983/**
1984 * Reads the Status Register.
1985 */
1986static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1987{
1988 RT_NOREF(pDevIns, offReg);
1989 *pu64Value = pThis->Status.u64;
1990 return VINF_SUCCESS;
1991}
1992
1993
1994/**
1995 * Writes the Device Table Base Address Register.
1996 */
1997static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1998{
1999 RT_NOREF(pDevIns, offReg);
2000
2001 /* Mask out all unrecognized bits. */
2002 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
2003
2004 /* Update the register. */
2005 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
2006
2007 /* Paranoia. */
2008 Assert(pThis->aDevTabBaseAddrs[0].n.u9Size <= g_auDevTabSegMaxSizes[0]);
2009 return VINF_SUCCESS;
2010}
2011
2012
2013/**
2014 * Writes the Command Buffer Base Address Register.
2015 */
2016static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2017{
2018 RT_NOREF(pDevIns, offReg);
2019
2020 /*
2021 * While this is not explicitly specified like the event log base address register,
2022 * the AMD IOMMU spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
2023 * Inconsistent specs :/
2024 */
2025 if (pThis->Status.n.u1CmdBufRunning)
2026 {
2027 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2028 return VINF_SUCCESS;
2029 }
2030
2031 /* Mask out all unrecognized bits. */
2032 CMD_BUF_BAR_T CmdBufBaseAddr;
2033 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
2034
2035 /* Validate the length. */
2036 if (CmdBufBaseAddr.n.u4Len >= 8)
2037 {
2038 /* Update the register. */
2039 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
2040
2041 /*
2042 * Writing the command buffer base address, clears the command buffer head and tail pointers.
2043 * See AMD IOMMU spec. 2.4 "Commands".
2044 */
2045 pThis->CmdBufHeadPtr.u64 = 0;
2046 pThis->CmdBufTailPtr.u64 = 0;
2047 }
2048 else
2049 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
2050
2051 return VINF_SUCCESS;
2052}
2053
2054
2055/**
2056 * Writes the Event Log Base Address Register.
2057 */
2058static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2059{
2060 RT_NOREF(pDevIns, offReg);
2061
2062 /*
2063 * IOMMU behavior is undefined when software writes this register when event logging is running.
2064 * In our emulation, we ignore the write entirely.
2065 * See AMD IOMMU spec. "Event Log Base Address Register".
2066 */
2067 if (pThis->Status.n.u1EvtLogRunning)
2068 {
2069 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
2070 return VINF_SUCCESS;
2071 }
2072
2073 /* Mask out all unrecognized bits. */
2074 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
2075 EVT_LOG_BAR_T EvtLogBaseAddr;
2076 EvtLogBaseAddr.u64 = u64Value;
2077
2078 /* Validate the length. */
2079 if (EvtLogBaseAddr.n.u4Len >= 8)
2080 {
2081 /* Update the register. */
2082 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
2083
2084 /*
2085 * Writing the event log base address, clears the event log head and tail pointers.
2086 * See AMD IOMMU spec. 2.5 "Event Logging".
2087 */
2088 pThis->EvtLogHeadPtr.u64 = 0;
2089 pThis->EvtLogTailPtr.u64 = 0;
2090 }
2091 else
2092 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
2093
2094 return VINF_SUCCESS;
2095}
2096
2097
2098/**
2099 * Writes the Control Register.
2100 */
2101static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2102{
2103 RT_NOREF(pDevIns, offReg);
2104
2105 /* Mask out all unrecognized bits. */
2106 u64Value &= IOMMU_CTRL_VALID_MASK;
2107 IOMMU_CTRL_T NewCtrl;
2108 NewCtrl.u64 = u64Value;
2109
2110 /* Ensure the device table segments are within limits. */
2111 if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
2112 {
2113 IOMMU_CTRL_T const OldCtrl = pThis->Ctrl;
2114
2115 /* Update the register. */
2116 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
2117
2118 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
2119 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
2120
2121 /* Enable or disable event logging when the bit transitions. */
2122 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
2123 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
2124 if ( fOldEvtLogEn != fNewEvtLogEn
2125 || fOldIommuEn != fNewIommuEn)
2126 {
2127 if ( fNewIommuEn
2128 && fNewEvtLogEn)
2129 {
2130 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
2131 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
2132 }
2133 else
2134 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
2135 }
2136
2137 /* Enable or disable command buffer processing when the bit transitions. */
2138 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
2139 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
2140 if ( fOldCmdBufEn != fNewCmdBufEn
2141 || fOldIommuEn != fNewIommuEn)
2142 {
2143 if ( fNewCmdBufEn
2144 && fNewIommuEn)
2145 {
2146 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
2147 LogFunc(("Command buffer enabled\n"));
2148
2149 /* Wake up the command thread to start processing commands if any. */
2150 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2151 }
2152 else
2153 {
2154 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2155 LogFunc(("Command buffer disabled\n"));
2156 }
2157 }
2158 }
2159 else
2160 {
2161 LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
2162 pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
2163 }
2164
2165 return VINF_SUCCESS;
2166}
2167
2168
2169/**
2170 * Writes to the Exclusion Range Base Address Register.
2171 */
2172static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2173{
2174 RT_NOREF(pDevIns, offReg);
2175 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
2176 return VINF_SUCCESS;
2177}
2178
2179
2180/**
2181 * Writes to the Exclusion Range Limit Register.
2182 */
2183static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2184{
2185 RT_NOREF(pDevIns, offReg);
2186 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
2187 u64Value |= UINT64_C(0xfff);
2188 pThis->ExclRangeLimit.u64 = u64Value;
2189 return VINF_SUCCESS;
2190}
2191
2192
2193/**
2194 * Writes the Hardware Event Register (Hi).
2195 */
2196static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2197{
2198 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2199 RT_NOREF(pDevIns, offReg);
2200 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
2201 pThis->HwEvtHi.u64 = u64Value;
2202 return VINF_SUCCESS;
2203}
2204
2205
2206/**
2207 * Writes the Hardware Event Register (Lo).
2208 */
2209static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2210{
2211 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2212 RT_NOREF(pDevIns, offReg);
2213 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
2214 pThis->HwEvtLo = u64Value;
2215 return VINF_SUCCESS;
2216}
2217
2218
2219/**
2220 * Writes the Hardware Event Status Register.
2221 */
2222static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2223{
2224 RT_NOREF(pDevIns, offReg);
2225
2226 /* Mask out all unrecognized bits. */
2227 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
2228
2229 /*
2230 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
2231 * If the current status bits or the bits being written are both 0, we've nothing to do.
2232 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
2233 */
2234 uint64_t HwStatus = pThis->HwEvtStatus.u64;
2235 if (!(HwStatus & RT_BIT(0)))
2236 return VINF_SUCCESS;
2237 if (u64Value & HwStatus & RT_BIT_64(0))
2238 HwStatus &= ~RT_BIT_64(0);
2239 if (u64Value & HwStatus & RT_BIT_64(1))
2240 HwStatus &= ~RT_BIT_64(1);
2241
2242 /* Update the register. */
2243 pThis->HwEvtStatus.u64 = HwStatus;
2244 return VINF_SUCCESS;
2245}
2246
2247
2248/**
2249 * Writes the Device Table Segment Base Address Register.
2250 */
2251static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2252{
2253 RT_NOREF(pDevIns);
2254
2255 /* Figure out which segment is being written. */
2256 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
2257 uint8_t const idxSegment = offSegment + 1;
2258 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2259
2260 /* Mask out all unrecognized bits. */
2261 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
2262 DEV_TAB_BAR_T DevTabSegBar;
2263 DevTabSegBar.u64 = u64Value;
2264
2265 /* Validate the size. */
2266 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
2267 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
2268 if (uSegSize <= uMaxSegSize)
2269 {
2270 /* Update the register. */
2271 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
2272 }
2273 else
2274 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
2275
2276 return VINF_SUCCESS;
2277}
2278
2279
2280/**
2281 * Writes the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
2282 */
2283static VBOXSTRICTRC iommuAmdDevMsiVector_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2284{
2285 RT_NOREF(pDevIns, offReg);
2286
2287 /* MSI Vector Register 0 is read-only. */
2288 /* MSI Vector Register 1. */
2289 uint32_t const uReg = u64Value >> 32;
2290 pThis->MiscInfo.au32[1] = uReg & IOMMU_MSI_VECTOR_1_VALID_MASK;
2291 return VINF_SUCCESS;
2292}
2293
2294
2295/**
2296 * Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
2297 * Register (32-bit).
2298 */
2299static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2300{
2301 RT_NOREF(pThis, offReg);
2302 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2303 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2304
2305 /* MSI capability header. */
2306 {
2307 uint32_t const uReg = u64Value;
2308 MSI_CAP_HDR_T MsiCapHdr;
2309 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
2310 MsiCapHdr.n.u1MsiEnable = RT_BOOL(uReg & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
2311 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
2312 }
2313
2314 /* MSI Address Lo. */
2315 {
2316 uint32_t const uReg = u64Value >> 32;
2317 uint32_t const uMsiAddrLo = uReg & VBOX_MSI_ADDR_VALID_MASK;
2318 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
2319 }
2320
2321 return VINF_SUCCESS;
2322}
2323
2324
2325/**
2326 * Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
2327 */
2328static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2329{
2330 RT_NOREF(pThis, offReg);
2331 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2332 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2333
2334 /* MSI Address Hi. */
2335 {
2336 uint32_t const uReg = u64Value;
2337 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, uReg);
2338 }
2339
2340 /* MSI Data. */
2341 {
2342 uint32_t const uReg = u64Value >> 32;
2343 uint32_t const uMsiData = uReg & VBOX_MSI_DATA_VALID_MASK;
2344 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
2345 }
2346
2347 return VINF_SUCCESS;
2348}
2349
2350
2351/**
2352 * Writes the Command Buffer Head Pointer Register.
2353 */
2354static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2355{
2356 RT_NOREF(pDevIns, offReg);
2357
2358 /*
2359 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
2360 * In our emulation, we ignore the write entirely.
2361 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2362 */
2363 if (pThis->Status.n.u1CmdBufRunning)
2364 {
2365 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2366 return VINF_SUCCESS;
2367 }
2368
2369 /*
2370 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2371 * In our emulation, we ignore the write entirely.
2372 */
2373 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
2374 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2375 Assert(cbBuf <= _512K);
2376 if (offBuf >= cbBuf)
2377 {
2378 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
2379 return VINF_SUCCESS;
2380 }
2381
2382 /* Update the register. */
2383 pThis->CmdBufHeadPtr.au32[0] = offBuf;
2384
2385 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2386
2387 Log4Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
2388 return VINF_SUCCESS;
2389}
2390
2391
2392/**
2393 * Writes the Command Buffer Tail Pointer Register.
2394 */
2395static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2396{
2397 RT_NOREF(pDevIns, offReg);
2398
2399 /*
2400 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2401 * In our emulation, we ignore the write entirely.
2402 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2403 */
2404 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
2405 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2406 Assert(cbBuf <= _512K);
2407 if (offBuf >= cbBuf)
2408 {
2409 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2410 return VINF_SUCCESS;
2411 }
2412
2413 /*
2414 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
2415 * head pointer after adding one or more commands to the buffer.
2416 *
2417 * However, we cannot enforce this strictly because it's legal for software to shrink the
2418 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
2419 * at 0). Software might even make the queue empty by making head and tail equal which is
2420 * allowed. I don't think we can or should try too hard to prevent software shooting itself
2421 * in the foot here. As long as we make sure the offset value is within the circular buffer
2422 * bounds (which we do by masking bits above) it should be sufficient.
2423 */
2424 pThis->CmdBufTailPtr.au32[0] = offBuf;
2425
2426 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2427
2428 Log4Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
2429 return VINF_SUCCESS;
2430}
2431
2432
2433/**
2434 * Writes the Event Log Head Pointer Register.
2435 */
2436static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2437{
2438 RT_NOREF(pDevIns, offReg);
2439
2440 /*
2441 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2442 * In our emulation, we ignore the write entirely.
2443 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2444 */
2445 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
2446 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2447 Assert(cbBuf <= _512K);
2448 if (offBuf >= cbBuf)
2449 {
2450 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2451 return VINF_SUCCESS;
2452 }
2453
2454 /* Update the register. */
2455 pThis->EvtLogHeadPtr.au32[0] = offBuf;
2456
2457 LogFlowFunc(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
2458 return VINF_SUCCESS;
2459}
2460
2461
2462/**
2463 * Writes the Event Log Tail Pointer Register.
2464 */
2465static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2466{
2467 RT_NOREF(pDevIns, offReg);
2468 NOREF(pThis);
2469
2470 /*
2471 * IOMMU behavior is undefined when software writes this register when the event log is running.
2472 * In our emulation, we ignore the write entirely.
2473 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2474 */
2475 if (pThis->Status.n.u1EvtLogRunning)
2476 {
2477 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
2478 return VINF_SUCCESS;
2479 }
2480
2481 /*
2482 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2483 * In our emulation, we ignore the write entirely.
2484 */
2485 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
2486 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2487 Assert(cbBuf <= _512K);
2488 if (offBuf >= cbBuf)
2489 {
2490 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2491 return VINF_SUCCESS;
2492 }
2493
2494 /* Update the register. */
2495 pThis->EvtLogTailPtr.au32[0] = offBuf;
2496
2497 LogFlowFunc(("Set EvtLogTailPtr to %#RX32\n", offBuf));
2498 return VINF_SUCCESS;
2499}
2500
2501
2502/**
2503 * Writes the Status Register.
2504 */
2505static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2506{
2507 RT_NOREF(pDevIns, offReg);
2508
2509 /* Mask out all unrecognized bits. */
2510 u64Value &= IOMMU_STATUS_VALID_MASK;
2511
2512 /*
2513 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
2514 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
2515 */
2516 IOMMU_STATUS_T const OldStatus = pThis->Status;
2517 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
2518 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
2519 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
2520
2521 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
2522
2523 /* Update the register. */
2524 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
2525 return VINF_SUCCESS;
2526}
2527
2528
2529/**
2530 * Register access table 0.
2531 * The MMIO offset of each entry must be a multiple of 8!
2532 */
2533static const IOMMUREGACC g_aRegAccess0[] =
2534{
2535 /* MMIO off. Register name Read function Write function */
2536 { /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w },
2537 { /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w },
2538 { /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w },
2539 { /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w },
2540 { /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w },
2541 { /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w },
2542 { /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL },
2543 { /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL },
2544 { /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w },
2545 { /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w },
2546 { /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w },
2547 { /* 0x58 */ NULL, NULL, NULL },
2548
2549 { /* 0x60 */ "SMI_FLT_0", NULL, NULL },
2550 { /* 0x68 */ "SMI_FLT_1", NULL, NULL },
2551 { /* 0x70 */ "SMI_FLT_2", NULL, NULL },
2552 { /* 0x78 */ "SMI_FLT_3", NULL, NULL },
2553 { /* 0x80 */ "SMI_FLT_4", NULL, NULL },
2554 { /* 0x88 */ "SMI_FLT_5", NULL, NULL },
2555 { /* 0x90 */ "SMI_FLT_6", NULL, NULL },
2556 { /* 0x98 */ "SMI_FLT_7", NULL, NULL },
2557 { /* 0xa0 */ "SMI_FLT_8", NULL, NULL },
2558 { /* 0xa8 */ "SMI_FLT_9", NULL, NULL },
2559 { /* 0xb0 */ "SMI_FLT_10", NULL, NULL },
2560 { /* 0xb8 */ "SMI_FLT_11", NULL, NULL },
2561 { /* 0xc0 */ "SMI_FLT_12", NULL, NULL },
2562 { /* 0xc8 */ "SMI_FLT_13", NULL, NULL },
2563 { /* 0xd0 */ "SMI_FLT_14", NULL, NULL },
2564 { /* 0xd8 */ "SMI_FLT_15", NULL, NULL },
2565
2566 { /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL },
2567 { /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL },
2568 { /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL },
2569 { /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL },
2570
2571 { /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2572 { /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2573 { /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2574 { /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2575 { /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2576 { /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2577 { /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2578
2579 { /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL },
2580 { /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL },
2581 { /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL },
2582
2583 { /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, iommuAmdDevMsiVector_w },
2584 { /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrAndAddrLo_r, iommuAmdMsiCapHdrAndAddrLo_w },
2585 { /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiAndData_r, iommuAmdMsiAddrHiAndData_w },
2586 { /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL },
2587
2588 { /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL },
2589 { /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL },
2590 { /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL },
2591};
2592AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
2593
2594/**
2595 * Register access table 1.
2596 * The MMIO offset of each entry must be a multiple of 8!
2597 */
2598static const IOMMUREGACC g_aRegAccess1[] =
2599{
2600 /* MMIO offset Register name Read function Write function */
2601 { /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL },
2602 { /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL },
2603 { /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL },
2604 { /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL },
2605 { /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL },
2606 { /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL },
2607 { /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL },
2608 { /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL },
2609 { /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL },
2610 { /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL },
2611 { /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL },
2612 { /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL }
2613};
2614AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
2615
2616/**
2617 * Register access table 2.
2618 * The MMIO offset of each entry must be a multiple of 8!
2619 */
2620static const IOMMUREGACC g_aRegAccess2[] =
2621{
2622 /* MMIO offset Register name Read Function Write function */
2623 { /* 0x1ff8 */ "RSVD_REG", NULL, NULL },
2624
2625 { /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w },
2626 { /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w },
2627 { /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w },
2628 { /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w },
2629
2630 { /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w },
2631 { /* 0x2028 */ NULL, NULL, NULL },
2632
2633 { /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL },
2634 { /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL },
2635
2636 { /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL },
2637 { /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL },
2638
2639 { /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL },
2640 { /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL },
2641
2642 { /* 0x2060 */ NULL, NULL, NULL },
2643 { /* 0x2068 */ NULL, NULL, NULL },
2644
2645 { /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL },
2646 { /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL },
2647
2648 { /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL },
2649 { /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL },
2650 { /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL }
2651};
2652AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
2653
2654
2655/**
2656 * Gets the register access structure given its MMIO offset.
2657 *
2658 * @returns The register access structure, or NULL if the offset is invalid.
2659 * @param off The MMIO offset of the register being accessed.
2660 */
2661static PCIOMMUREGACC iommuAmdGetRegAccess(uint32_t off)
2662{
2663 /* Figure out which table the register belongs to and validate its index. */
2664 PCIOMMUREGACC pReg;
2665 if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
2666 {
2667 uint32_t const idxReg = off >> 3;
2668 Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
2669 pReg = &g_aRegAccess0[idxReg];
2670 }
2671 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
2672 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
2673 {
2674 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
2675 Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
2676 pReg = &g_aRegAccess1[idxReg];
2677 }
2678 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
2679 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
2680 {
2681 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
2682 Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
2683 pReg = &g_aRegAccess2[idxReg];
2684 }
2685 else
2686 pReg = NULL;
2687 return pReg;
2688}
2689
2690
2691/**
2692 * Writes an IOMMU register (32-bit and 64-bit).
2693 *
2694 * @returns Strict VBox status code.
2695 * @param pDevIns The IOMMU device instance.
2696 * @param off MMIO byte offset to the register.
2697 * @param cb The size of the write access.
2698 * @param uValue The value being written.
2699 *
2700 * @thread EMT.
2701 */
2702static VBOXSTRICTRC iommuAmdRegisterWrite(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
2703{
2704 /*
2705 * Validate the access in case of IOM bug or incorrect assumption.
2706 */
2707 Assert(off < IOMMU_MMIO_REGION_SIZE);
2708 AssertMsgReturn(cb == 4 || cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
2709 AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
2710
2711 Log4Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
2712
2713 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2714 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2715 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2716 if (pReg)
2717 { /* likely */ }
2718 else
2719 {
2720 LogFunc(("Writing unknown register %#x with %#RX64 -> Ignored\n", off, uValue));
2721 return VINF_SUCCESS;
2722 }
2723
2724 /* If a write handler doesn't exist, it's either a reserved or read-only register. */
2725 if (pReg->pfnWrite)
2726 { /* likely */ }
2727 else
2728 {
2729 LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2730 return VINF_SUCCESS;
2731 }
2732
2733 /*
2734 * If the write access is 64-bits and aligned on a 64-bit boundary, dispatch right away.
2735 * This handles writes to 64-bit registers as well as aligned, 64-bit writes to two
2736 * consecutive 32-bit registers.
2737 */
2738 if (cb == 8)
2739 {
2740 if (!(off & 7))
2741 {
2742 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2743 VBOXSTRICTRC rcStrict = pReg->pfnWrite(pDevIns, pThis, off, uValue);
2744 IOMMU_UNLOCK(pDevIns, pThisCC);
2745 return rcStrict;
2746 }
2747
2748 LogFunc(("Misaligned access while writing register at off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2749 return VINF_SUCCESS;
2750 }
2751
2752 /* We shouldn't get sizes other than 32 bits here as we've specified so with IOM. */
2753 Assert(cb == 4);
2754 if (!(off & 7))
2755 {
2756 VBOXSTRICTRC rcStrict;
2757 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2758
2759 /*
2760 * Lower 32 bits of a 64-bit register or a 32-bit register is being written.
2761 * Merge with higher 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2762 */
2763 uint64_t u64Read;
2764 if (pReg->pfnRead)
2765 rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
2766 else
2767 {
2768 rcStrict = VINF_SUCCESS;
2769 u64Read = 0;
2770 }
2771
2772 if (RT_SUCCESS(rcStrict))
2773 {
2774 uValue = (u64Read & UINT64_C(0xffffffff00000000)) | uValue;
2775 rcStrict = pReg->pfnWrite(pDevIns, pThis, off, uValue);
2776 }
2777 else
2778 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2779
2780 IOMMU_UNLOCK(pDevIns, pThisCC);
2781 return rcStrict;
2782 }
2783
2784 /*
2785 * Higher 32 bits of a 64-bit register or a 32-bit register at a 32-bit boundary is being written.
2786 * Merge with lower 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2787 */
2788 VBOXSTRICTRC rcStrict;
2789 Assert(!(off & 3));
2790 Assert(off & 7);
2791 Assert(off >= 4);
2792 uint64_t u64Read;
2793 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2794 if (pReg->pfnRead)
2795 rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
2796 else
2797 {
2798 rcStrict = VINF_SUCCESS;
2799 u64Read = 0;
2800 }
2801
2802 if (RT_SUCCESS(rcStrict))
2803 {
2804 uValue = (uValue << 32) | (u64Read & UINT64_C(0xffffffff));
2805 rcStrict = pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
2806 }
2807 else
2808 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2809
2810 IOMMU_UNLOCK(pDevIns, pThisCC);
2811 return rcStrict;
2812}
2813
2814
2815/**
2816 * Reads an IOMMU register (64-bit) given its MMIO offset.
2817 *
2818 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
2819 * boundary include the lower half of the subsequent register.
2820 *
2821 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
2822 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
2823 * software will only perform 32-bit reads on those 32-bit registers that are
2824 * aligned on 8-byte boundaries.
2825 *
2826 * @returns Strict VBox status code.
2827 * @param pDevIns The IOMMU device instance.
2828 * @param off The MMIO offset of the register in bytes.
2829 * @param puResult Where to store the value being read.
2830 *
2831 * @thread EMT.
2832 */
2833static VBOXSTRICTRC iommuAmdRegisterRead(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
2834{
2835 Assert(off < IOMMU_MMIO_REGION_SIZE);
2836 Assert(!(off & 7) || !(off & 3));
2837
2838 Log4Func(("off=%#x\n", off));
2839
2840 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2841 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2842 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2843 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); NOREF(pPciDev);
2844
2845 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2846 if (pReg)
2847 { /* likely */ }
2848 else
2849 {
2850 LogFunc(("Reading unknown register %#x -> Ignored\n", off));
2851 return VINF_IOM_MMIO_UNUSED_FF;
2852 }
2853
2854 /* If a read handler doesn't exist, it's a reserved or unknown register. */
2855 if (pReg->pfnRead)
2856 { /* likely */ }
2857 else
2858 {
2859 LogFunc(("Reading reserved or unknown register off=%#x -> returning 0s\n", off));
2860 return VINF_IOM_MMIO_UNUSED_00;
2861 }
2862
2863 /*
2864 * If the read access is aligned on a 64-bit boundary, read the full 64-bits and return.
2865 * The caller takes care of truncating upper 32 bits for 32-bit reads.
2866 */
2867 if (!(off & 7))
2868 {
2869 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
2870 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, puResult);
2871 IOMMU_UNLOCK(pDevIns, pThisCC);
2872 return rcStrict;
2873 }
2874
2875 /*
2876 * High 32 bits of a 64-bit register or a 32-bit register at a non 64-bit boundary is being read.
2877 * Read full 64 bits at the previous 64-bit boundary but return only the high 32 bits.
2878 */
2879 Assert(!(off & 3));
2880 Assert(off & 7);
2881 Assert(off >= 4);
2882 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
2883 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, puResult);
2884 IOMMU_UNLOCK(pDevIns, pThisCC);
2885 if (RT_SUCCESS(rcStrict))
2886 *puResult >>= 32;
2887 else
2888 {
2889 *puResult = 0;
2890 LogFunc(("Reading off %#x during split read failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2891 }
2892
2893 return rcStrict;
2894}
2895
2896
2897/**
2898 * Raises the MSI interrupt for the IOMMU device.
2899 *
2900 * @param pDevIns The IOMMU device instance.
2901 *
2902 * @thread Any.
2903 * @remarks The IOMMU lock may or may not be held.
2904 */
2905static void iommuAmdMsiInterruptRaise(PPDMDEVINS pDevIns)
2906{
2907 LogFlowFunc(("\n"));
2908 if (iommuAmdIsMsiEnabled(pDevIns))
2909 {
2910 LogFunc(("Raising MSI\n"));
2911 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
2912 }
2913}
2914
2915#if 0
2916/**
2917 * Clears the MSI interrupt for the IOMMU device.
2918 *
2919 * @param pDevIns The IOMMU device instance.
2920 *
2921 * @thread Any.
2922 * @remarks The IOMMU lock may or may not be held.
2923 */
2924static void iommuAmdMsiInterruptClear(PPDMDEVINS pDevIns)
2925{
2926 if (iommuAmdIsMsiEnabled(pDevIns))
2927 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
2928}
2929#endif
2930
2931/**
2932 * Writes an entry to the event log in memory.
2933 *
2934 * @returns VBox status code.
2935 * @param pDevIns The IOMMU device instance.
2936 * @param pEvent The event to log.
2937 *
2938 * @thread Any.
2939 * @remarks The IOMMU lock must be held while calling this function.
2940 */
2941static int iommuAmdEvtLogEntryWrite(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2942{
2943 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2944 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2945
2946 IOMMU_LOCK(pDevIns, pThisCC);
2947
2948 /* Check if event logging is active and the log has not overflowed. */
2949 IOMMU_STATUS_T const Status = pThis->Status;
2950 if ( Status.n.u1EvtLogRunning
2951 && !Status.n.u1EvtOverflow)
2952 {
2953 uint32_t const cbEvt = sizeof(*pEvent);
2954
2955 /* Get the offset we need to write the event to in memory (circular buffer offset). */
2956 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
2957 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
2958
2959 /* Ensure we have space in the event log. */
2960 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2961 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
2962 if (cEvts + 1 < cMaxEvts)
2963 {
2964 /* Write the event log entry to memory. */
2965 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
2966 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
2967 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
2968 if (RT_FAILURE(rc))
2969 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
2970
2971 /* Increment the event log tail pointer. */
2972 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2973 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
2974
2975 /* Indicate that an event log entry was written. */
2976 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
2977
2978 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
2979 if (pThis->Ctrl.n.u1EvtIntrEn)
2980 iommuAmdMsiInterruptRaise(pDevIns);
2981 }
2982 else
2983 {
2984 /* Indicate that the event log has overflowed. */
2985 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
2986
2987 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
2988 if (pThis->Ctrl.n.u1EvtIntrEn)
2989 iommuAmdMsiInterruptRaise(pDevIns);
2990 }
2991 }
2992
2993 IOMMU_UNLOCK(pDevIns, pThisCC);
2994
2995 return VINF_SUCCESS;
2996}
2997
2998
2999/**
3000 * Sets an event in the hardware error registers.
3001 *
3002 * @param pDevIns The IOMMU device instance.
3003 * @param pEvent The event.
3004 *
3005 * @thread Any.
3006 */
3007static void iommuAmdHwErrorSet(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3008{
3009 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3010 if (pThis->ExtFeat.n.u1HwErrorSup)
3011 {
3012 if (pThis->HwEvtStatus.n.u1Valid)
3013 pThis->HwEvtStatus.n.u1Overflow = 1;
3014 pThis->HwEvtStatus.n.u1Valid = 1;
3015 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
3016 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
3017 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
3018 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
3019 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
3020 }
3021}
3022
3023
3024/**
3025 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
3026 *
3027 * @param idDevice The device ID (bus, device, function).
3028 * @param idDomain The domain ID.
3029 * @param GCPhysPtEntity The system physical address of the page table
3030 * entity.
3031 * @param enmOp The IOMMU operation being performed.
3032 * @param pEvtPageTabHwErr Where to store the initialized event.
3033 */
3034static void iommuAmdPageTabHwErrorEventInit(uint16_t idDevice, uint16_t idDomain, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
3035 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3036{
3037 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
3038 pEvtPageTabHwErr->n.u16DevId = idDevice;
3039 pEvtPageTabHwErr->n.u16DomainOrPasidLo = idDomain;
3040 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
3041 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3042 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3043 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3044 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3045 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
3046 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
3047}
3048
3049
3050/**
3051 * Raises a PAGE_TAB_HARDWARE_ERROR event.
3052 *
3053 * @param pDevIns The IOMMU device instance.
3054 * @param enmOp The IOMMU operation being performed.
3055 * @param pEvtPageTabHwErr The page table hardware error event.
3056 *
3057 * @thread Any.
3058 */
3059static void iommuAmdPageTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3060{
3061 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
3062 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
3063
3064 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3065 IOMMU_LOCK(pDevIns, pThisCC);
3066
3067 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3068 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3069 if (enmOp != IOMMUOP_CMD)
3070 iommuAmdSetPciTargetAbort(pDevIns);
3071
3072 IOMMU_UNLOCK(pDevIns, pThisCC);
3073
3074 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. idDevice=%#x idDomain=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
3075 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
3076 pEvtPageTabHwErr->n.u2Type));
3077}
3078
3079
3080#ifdef IN_RING3
3081/**
3082 * Initializes a COMMAND_HARDWARE_ERROR event.
3083 *
3084 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
3085 * @param pEvtCmdHwErr Where to store the initialized event.
3086 */
3087static void iommuAmdCmdHwErrorEventInit(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3088{
3089 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
3090 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
3091 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
3092 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
3093}
3094
3095
3096/**
3097 * Raises a COMMAND_HARDWARE_ERROR event.
3098 *
3099 * @param pDevIns The IOMMU device instance.
3100 * @param pEvtCmdHwErr The command hardware error event.
3101 *
3102 * @thread Any.
3103 */
3104static void iommuAmdCmdHwErrorEventRaise(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3105{
3106 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
3107 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
3108 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3109
3110 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3111 IOMMU_LOCK(pDevIns, pThisCC);
3112
3113 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3114 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3115 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3116
3117 IOMMU_UNLOCK(pDevIns, pThisCC);
3118
3119 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
3120}
3121#endif /* IN_RING3 */
3122
3123
3124/**
3125 * Initializes a DEV_TAB_HARDWARE_ERROR event.
3126 *
3127 * @param idDevice The device ID (bus, device, function).
3128 * @param GCPhysDte The system physical address of the failed device table
3129 * access.
3130 * @param enmOp The IOMMU operation being performed.
3131 * @param pEvtDevTabHwErr Where to store the initialized event.
3132 */
3133static void iommuAmdDevTabHwErrorEventInit(uint16_t idDevice, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
3134 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3135{
3136 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
3137 pEvtDevTabHwErr->n.u16DevId = idDevice;
3138 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3139 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
3140 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3141 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3142 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3143 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
3144 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
3145}
3146
3147
3148/**
3149 * Raises a DEV_TAB_HARDWARE_ERROR event.
3150 *
3151 * @param pDevIns The IOMMU device instance.
3152 * @param enmOp The IOMMU operation being performed.
3153 * @param pEvtDevTabHwErr The device table hardware error event.
3154 *
3155 * @thread Any.
3156 */
3157static void iommuAmdDevTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3158{
3159 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
3160 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
3161
3162 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3163 IOMMU_LOCK(pDevIns, pThisCC);
3164
3165 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3166 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3167 if (enmOp != IOMMUOP_CMD)
3168 iommuAmdSetPciTargetAbort(pDevIns);
3169
3170 IOMMU_UNLOCK(pDevIns, pThisCC);
3171
3172 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. idDevice=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
3173 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
3174}
3175
3176
3177#ifdef IN_RING3
3178/**
3179 * Initializes an ILLEGAL_COMMAND_ERROR event.
3180 *
3181 * @param GCPhysCmd The system physical address of the failed command
3182 * access.
3183 * @param pEvtIllegalCmd Where to store the initialized event.
3184 */
3185static void iommuAmdIllegalCmdEventInit(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3186{
3187 Assert(!(GCPhysCmd & UINT64_C(0xf)));
3188 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
3189 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
3190 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
3191}
3192
3193
3194/**
3195 * Raises an ILLEGAL_COMMAND_ERROR event.
3196 *
3197 * @param pDevIns The IOMMU device instance.
3198 * @param pEvtIllegalCmd The illegal command error event.
3199 */
3200static void iommuAmdIllegalCmdEventRaise(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3201{
3202 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3203 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
3204 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3205
3206 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3207 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3208
3209 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
3210}
3211#endif /* IN_RING3 */
3212
3213
3214/**
3215 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
3216 *
3217 * @param idDevice The device ID (bus, device, function).
3218 * @param uIova The I/O virtual address.
3219 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
3220 * event was caused by an invalid level encoding in the
3221 * DTE.
3222 * @param enmOp The IOMMU operation being performed.
3223 * @param pEvtIllegalDte Where to store the initialized event.
3224 */
3225static void iommuAmdIllegalDteEventInit(uint16_t idDevice, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
3226 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
3227{
3228 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
3229 pEvtIllegalDte->n.u16DevId = idDevice;
3230 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3231 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3232 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
3233 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3234 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
3235 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
3236 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
3237 * IOMMU spec here but not for this field for I/O page fault event. */
3238 Assert(!(uIova & UINT64_C(0x3)));
3239}
3240
3241
3242/**
3243 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
3244 *
3245 * @param pDevIns The IOMMU instance data.
3246 * @param enmOp The IOMMU operation being performed.
3247 * @param pEvtIllegalDte The illegal device table entry event.
3248 * @param enmEvtType The illegal device table entry event type.
3249 *
3250 * @thread Any.
3251 */
3252static void iommuAmdIllegalDteEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
3253 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
3254{
3255 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3256 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
3257
3258 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3259 if (enmOp != IOMMUOP_CMD)
3260 iommuAmdSetPciTargetAbort(pDevIns);
3261
3262 LogFunc(("Raised ILLEGAL_DTE_EVENT. idDevice=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
3263 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
3264 NOREF(enmEvtType);
3265}
3266
3267
3268/**
3269 * Initializes an IO_PAGE_FAULT event.
3270 *
3271 * @param idDevice The device ID (bus, device, function).
3272 * @param idDomain The domain ID.
3273 * @param uIova The I/O virtual address being accessed.
3274 * @param fPresent Transaction to a page marked as present (including
3275 * DTE.V=1) or interrupt marked as remapped
3276 * (IRTE.RemapEn=1).
3277 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
3278 * the I/O page fault was caused by invalid level
3279 * encoding.
3280 * @param fPermDenied Permission denied for the address being accessed.
3281 * @param enmOp The IOMMU operation being performed.
3282 * @param pEvtIoPageFault Where to store the initialized event.
3283 */
3284static void iommuAmdIoPageFaultEventInit(uint16_t idDevice, uint16_t idDomain, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
3285 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
3286{
3287 Assert(!fPermDenied || fPresent);
3288 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
3289 pEvtIoPageFault->n.u16DevId = idDevice;
3290 //pEvtIoPageFault->n.u4PasidHi = 0;
3291 pEvtIoPageFault->n.u16DomainOrPasidLo = idDomain;
3292 //pEvtIoPageFault->n.u1GuestOrNested = 0;
3293 //pEvtIoPageFault->n.u1NoExecute = 0;
3294 //pEvtIoPageFault->n.u1User = 0;
3295 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3296 pEvtIoPageFault->n.u1Present = fPresent;
3297 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3298 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
3299 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
3300 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3301 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
3302 pEvtIoPageFault->n.u64Addr = uIova;
3303}
3304
3305
3306/**
3307 * Raises an IO_PAGE_FAULT event.
3308 *
3309 * @param pDevIns The IOMMU instance data.
3310 * @param fIoDevFlags The I/O device flags, see IOMMU_DTE_CACHE_F_XXX.
3311 * @param pIrte The interrupt remapping table entry, can be NULL.
3312 * @param enmOp The IOMMU operation being performed.
3313 * @param pEvtIoPageFault The I/O page fault event.
3314 * @param enmEvtType The I/O page fault event type.
3315 *
3316 * @thread Any.
3317 */
3318static void iommuAmdIoPageFaultEventRaise(PPDMDEVINS pDevIns, uint16_t fIoDevFlags, PCIRTE_T pIrte, IOMMUOP enmOp,
3319 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3320{
3321 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
3322 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
3323
3324#ifdef IOMMU_WITH_DTE_CACHE
3325# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) iommuAmdDteCacheAddFlags((a_pDevIns), (a_DevId), \
3326 IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED)
3327#else
3328# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) do { } while (0)
3329#endif
3330
3331 bool fSuppressEvtLogging = false;
3332 if ( enmOp == IOMMUOP_MEM_READ
3333 || enmOp == IOMMUOP_MEM_WRITE)
3334 {
3335 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_VALID
3336 | IOMMU_DTE_CACHE_F_SUPPRESS_IOPF | IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED;
3337 uint16_t const fSuppressAllIopf = IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
3338 if ( (fIoDevFlags & fSuppressAllIopf) == fSuppressAllIopf
3339 || (fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3340 {
3341 fSuppressEvtLogging = true;
3342 }
3343 }
3344 else if (enmOp == IOMMUOP_INTR_REQ)
3345 {
3346 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_INTR_MAP_VALID | IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
3347 if ((fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3348 fSuppressEvtLogging = true;
3349 else if (pIrte) /** @todo Make this compulsary and assert if it isn't provided. */
3350 fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
3351 }
3352 /* else: Events are never suppressed for commands. */
3353
3354 switch (enmEvtType)
3355 {
3356 case kIoPageFaultType_PermDenied:
3357 {
3358 /* Cannot be triggered by a command. */
3359 Assert(enmOp != IOMMUOP_CMD);
3360 RT_FALL_THRU();
3361 }
3362 case kIoPageFaultType_DteRsvdPagingMode:
3363 case kIoPageFaultType_PteInvalidPageSize:
3364 case kIoPageFaultType_PteInvalidLvlEncoding:
3365 case kIoPageFaultType_SkippedLevelIovaNotZero:
3366 case kIoPageFaultType_PteRsvdNotZero:
3367 case kIoPageFaultType_PteValidNotSet:
3368 case kIoPageFaultType_DteTranslationDisabled:
3369 case kIoPageFaultType_PasidInvalidRange:
3370 {
3371 /*
3372 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
3373 * create an event log entry. See AMD IOMMU spec. 2.1.3.2 "I/O Page Faults".
3374 */
3375 if (enmOp != IOMMUOP_TRANSLATE_REQ)
3376 {
3377 if (!fSuppressEvtLogging)
3378 {
3379 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3380 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3381 }
3382 if (enmOp != IOMMUOP_CMD)
3383 iommuAmdSetPciTargetAbort(pDevIns);
3384 }
3385 break;
3386 }
3387
3388 case kIoPageFaultType_UserSupervisor:
3389 {
3390 /* Access is blocked and only creates an event log entry. */
3391 if (!fSuppressEvtLogging)
3392 {
3393 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3394 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3395 }
3396 break;
3397 }
3398
3399 case kIoPageFaultType_IrteAddrInvalid:
3400 case kIoPageFaultType_IrteRsvdNotZero:
3401 case kIoPageFaultType_IrteRemapEn:
3402 case kIoPageFaultType_IrteRsvdIntType:
3403 case kIoPageFaultType_IntrReqAborted:
3404 case kIoPageFaultType_IntrWithPasid:
3405 {
3406 /* Only trigerred by interrupt requests. */
3407 Assert(enmOp == IOMMUOP_INTR_REQ);
3408 if (!fSuppressEvtLogging)
3409 {
3410 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3411 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3412 }
3413 iommuAmdSetPciTargetAbort(pDevIns);
3414 break;
3415 }
3416
3417 case kIoPageFaultType_SmiFilterMismatch:
3418 {
3419 /* Not supported and probably will never be, assert. */
3420 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
3421 break;
3422 }
3423
3424 case kIoPageFaultType_DevId_Invalid:
3425 {
3426 /* Cannot be triggered by a command. */
3427 Assert(enmOp != IOMMUOP_CMD);
3428 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
3429 if (!fSuppressEvtLogging)
3430 {
3431 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3432 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3433 }
3434 if ( enmOp == IOMMUOP_MEM_READ
3435 || enmOp == IOMMUOP_MEM_WRITE)
3436 iommuAmdSetPciTargetAbort(pDevIns);
3437 break;
3438 }
3439 }
3440
3441#undef IOMMU_DTE_CACHE_SET_PF_RAISED
3442}
3443
3444
3445/**
3446 * Raises an IO_PAGE_FAULT event given the DTE.
3447 *
3448 * @param pDevIns The IOMMU instance data.
3449 * @param pDte The device table entry.
3450 * @param pIrte The interrupt remapping table entry, can be NULL.
3451 * @param enmOp The IOMMU operation being performed.
3452 * @param pEvtIoPageFault The I/O page fault event.
3453 * @param enmEvtType The I/O page fault event type.
3454 *
3455 * @thread Any.
3456 */
3457static void iommuAmdIoPageFaultEventRaiseWithDte(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
3458 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3459{
3460 Assert(pDte);
3461 uint16_t const fIoDevFlags = iommuAmdGetBasicDevFlags(pDte);
3462 return iommuAmdIoPageFaultEventRaise(pDevIns, fIoDevFlags, pIrte, enmOp, pEvtIoPageFault, enmEvtType);
3463}
3464
3465
3466/**
3467 * Reads a device table entry for the given the device ID.
3468 *
3469 * @returns VBox status code.
3470 * @param pDevIns The IOMMU device instance.
3471 * @param idDevice The device ID (bus, device, function).
3472 * @param enmOp The IOMMU operation being performed.
3473 * @param pDte Where to store the device table entry.
3474 *
3475 * @thread Any.
3476 */
3477static int iommuAmdDteRead(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PDTE_T pDte)
3478{
3479 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3480 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3481
3482 IOMMU_LOCK(pDevIns, pThisCC);
3483
3484 /* Figure out which device table segment is being accessed. */
3485 uint8_t const idxSegsEn = pThis->Ctrl.n.u3DevTabSegEn;
3486 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
3487
3488 uint8_t const idxSeg = (idDevice & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
3489 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3490 AssertCompile(RT_ELEMENTS(g_auDevTabSegShifts) == RT_ELEMENTS(g_auDevTabSegMasks));
3491
3492 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
3493 uint32_t const offDte = (idDevice & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
3494 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
3495
3496 /* Ensure the DTE falls completely within the device table segment. */
3497 uint32_t const cbDevTabSeg = (pThis->aDevTabBaseAddrs[idxSeg].n.u9Size + 1) << X86_PAGE_4K_SHIFT;
3498
3499 IOMMU_UNLOCK(pDevIns, pThisCC);
3500
3501 if (offDte + sizeof(DTE_T) <= cbDevTabSeg)
3502 {
3503 /* Read the device table entry from guest memory. */
3504 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
3505 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
3506 if (RT_SUCCESS(rc))
3507 return rc;
3508
3509 /* Raise a device table hardware error. */
3510 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
3511
3512 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
3513 iommuAmdDevTabHwErrorEventInit(idDevice, GCPhysDte, enmOp, &EvtDevTabHwErr);
3514 iommuAmdDevTabHwErrorEventRaise(pDevIns, enmOp, &EvtDevTabHwErr);
3515 return VERR_IOMMU_DTE_READ_FAILED;
3516 }
3517
3518 /* Raise an I/O page fault for out-of-bounds acccess. */
3519 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3520 iommuAmdIoPageFaultEventInit(idDevice, 0 /* idDomain */, 0 /* uIova */, false /* fPresent */, false /* fRsvdNotZero */,
3521 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3522 iommuAmdIoPageFaultEventRaise(pDevIns, 0 /* fIoDevFlags */, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3523 kIoPageFaultType_DevId_Invalid);
3524 return VERR_IOMMU_DTE_BAD_OFFSET;
3525}
3526
3527
3528/**
3529 * Performs pre-translation checks for the given device table entry.
3530 *
3531 * @returns VBox status code.
3532 * @retval VINF_SUCCESS if the DTE is valid and supports address translation.
3533 * @retval VINF_IOMMU_ADDR_TRANSLATION_DISABLED if the DTE is valid but address
3534 * translation is disabled.
3535 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED if an error occurred and any
3536 * corresponding event was raised.
3537 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the DTE denies the requested
3538 * permissions.
3539 *
3540 * @param pDevIns The IOMMU device instance.
3541 * @param uIova The I/O virtual address to translate.
3542 * @param idDevice The device ID (bus, device, function).
3543 * @param fPerm The I/O permissions for this access, see
3544 * IOMMU_IO_PERM_XXX.
3545 * @param pDte The device table entry.
3546 * @param enmOp The IOMMU operation being performed.
3547 *
3548 * @thread Any.
3549 */
3550static int iommuAmdPreTranslateChecks(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, uint8_t fPerm, PCDTE_T pDte,
3551 IOMMUOP enmOp)
3552{
3553 /*
3554 * Check if the translation is valid, otherwise raise an I/O page fault.
3555 */
3556 if (pDte->n.u1TranslationValid)
3557 { /* likely */ }
3558 else
3559 {
3560 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
3561 * doesn't explicitly say whether an I/O page fault is raised. From other
3562 * places in the spec. it seems early page walk terminations (starting with
3563 * the DTE) return the state computed so far and raises an I/O page fault. So
3564 * returning an invalid translation rather than skipping translation. */
3565 LogFunc(("Translation valid bit not set -> IOPF\n"));
3566 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3567 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3568 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3569 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3570 kIoPageFaultType_DteTranslationDisabled);
3571 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3572 }
3573
3574 /*
3575 * Check permissions bits in the DTE.
3576 * Note: This MUST be checked prior to checking the root page table level below!
3577 */
3578 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3579 if ((fPerm & fDtePerm) == fPerm)
3580 { /* likely */ }
3581 else
3582 {
3583 LogFunc(("Permission denied by DTE (fPerm=%#x fDtePerm=%#x) -> IOPF\n", fPerm, fDtePerm));
3584 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3585 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3586 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3587 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3588 kIoPageFaultType_PermDenied);
3589 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3590 }
3591
3592 /*
3593 * If the root page table level is 0, translation is disabled and GPA=SPA and
3594 * the DTE.IR and DTE.IW bits control permissions (verified above).
3595 */
3596 uint8_t const uMaxLevel = pDte->n.u3Mode;
3597 if (uMaxLevel != 0)
3598 { /* likely */ }
3599 else
3600 {
3601 Assert((fPerm & fDtePerm) == fPerm); /* Verify we've checked permissions. */
3602 return VINF_IOMMU_ADDR_TRANSLATION_DISABLED;
3603 }
3604
3605 /*
3606 * If the root page table level exceeds the allowed host-address translation level,
3607 * page walk is terminated and translation fails.
3608 */
3609 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3610 { /* likely */ }
3611 else
3612 {
3613 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
3614 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
3615 * I'm just going with I/O page fault. */
3616 LogFunc(("Invalid root page table level %#x (idDevice=%#x) -> IOPF\n", uMaxLevel, idDevice));
3617 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3618 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3619 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3620 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3621 kIoPageFaultType_PteInvalidLvlEncoding);
3622 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3623 }
3624
3625 /* The DTE allows translations for this device. */
3626 return VINF_SUCCESS;
3627}
3628
3629
3630/**
3631 * Walks the I/O page table to translate the I/O virtual address to a system
3632 * physical address.
3633 *
3634 * @returns VBox status code.
3635 * @param pDevIns The IOMMU device instance.
3636 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
3637 * @param fPerm The I/O permissions for this access, see
3638 * IOMMU_IO_PERM_XXX.
3639 * @param idDevice The device ID (bus, device, function).
3640 * @param pDte The device table entry.
3641 * @param enmOp The IOMMU operation being performed.
3642 * @param pPageLookup Where to store the results of the I/O page lookup. This
3643 * is only updated when VINF_SUCCESS is returned.
3644 *
3645 * @thread Any.
3646 */
3647static int iommuAmdIoPageTableWalk(PPDMDEVINS pDevIns, uint64_t uIova, uint8_t fPerm, uint16_t idDevice, PCDTE_T pDte,
3648 IOMMUOP enmOp, PIOPAGELOOKUP pPageLookup)
3649{
3650 Assert(pDte->n.u1Valid);
3651 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
3652
3653 /* The virtual address bits indexing table. */
3654 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
3655 static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
3656 UINT64_C(0x00000000001ff000),
3657 UINT64_C(0x000000003fe00000),
3658 UINT64_C(0x0000007fc0000000),
3659 UINT64_C(0x0000ff8000000000),
3660 UINT64_C(0x01ff000000000000),
3661 UINT64_C(0xfe00000000000000),
3662 UINT64_C(0x0000000000000000) };
3663 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
3664 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
3665
3666 /* Traverse the I/O page table starting with the page directory in the DTE. */
3667 IOPTENTITY_T PtEntity;
3668 PtEntity.u64 = pDte->au64[0];
3669 for (;;)
3670 {
3671 /* Figure out the system physical address of the page table at the current level. */
3672 uint8_t const uLevel = PtEntity.n.u3NextLevel;
3673
3674 /* Read the page table entity at the current level. */
3675 {
3676 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
3677 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
3678 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
3679 uint64_t const offPte = idxPte << 3;
3680 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
3681 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
3682 if (RT_FAILURE(rc))
3683 {
3684 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
3685 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
3686 iommuAmdPageTabHwErrorEventInit(idDevice, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
3687 iommuAmdPageTabHwErrorEventRaise(pDevIns, enmOp, &EvtPageTabHwErr);
3688 return VERR_IOMMU_IPE_2;
3689 }
3690 }
3691
3692 /* Check present bit. */
3693 if (PtEntity.n.u1Present)
3694 { /* likely */ }
3695 else
3696 {
3697 LogFunc(("Page table entry not present (idDevice=%#x) -> IOPF\n", idDevice));
3698 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3699 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3700 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3701 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3702 kIoPageFaultType_PermDenied);
3703 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3704 }
3705
3706 /* Check permission bits. */
3707 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3708 if ((fPerm & fPtePerm) == fPerm)
3709 { /* likely */ }
3710 else
3711 {
3712 LogFunc(("Page table entry access denied (idDevice=%#x fPerm=%#x fPtePerm=%#x) -> IOPF\n", idDevice, fPerm, fPtePerm));
3713 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3714 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3715 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3716 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3717 kIoPageFaultType_PermDenied);
3718 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3719 }
3720
3721 /* If this is a PTE, we're at the final level and we're done. */
3722 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
3723 if (uNextLevel == 0)
3724 {
3725 /* The page size of the translation is the default (4K). */
3726 pPageLookup->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3727 pPageLookup->cShift = X86_PAGE_4K_SHIFT;
3728 pPageLookup->fPerm = fPtePerm;
3729 return VINF_SUCCESS;
3730 }
3731 if (uNextLevel == 7)
3732 {
3733 /* The default page size of the translation is overridden. */
3734 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3735 uint8_t cShift = X86_PAGE_4K_SHIFT;
3736 while (GCPhysPte & RT_BIT_64(cShift++))
3737 ;
3738
3739 /* The page size must be larger than the default size and lower than the default size of the higher level. */
3740 Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
3741 if ( cShift > s_acIovaLevelShifts[uLevel]
3742 && cShift < s_acIovaLevelShifts[uLevel + 1])
3743 {
3744 pPageLookup->GCPhysSpa = GCPhysPte;
3745 pPageLookup->cShift = cShift;
3746 pPageLookup->fPerm = fPtePerm;
3747 return VINF_SUCCESS;
3748 }
3749
3750 LogFunc(("Page size invalid cShift=%#x -> IOPF\n", cShift));
3751 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3752 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3753 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3754 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3755 kIoPageFaultType_PteInvalidPageSize);
3756 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3757 }
3758
3759 /* Validate the next level encoding of the PDE. */
3760#if IOMMU_MAX_HOST_PT_LEVEL < 6
3761 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3762 { /* likely */ }
3763 else
3764 {
3765 LogFunc(("Next level of PDE invalid uNextLevel=%#x -> IOPF\n", uNextLevel));
3766 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3767 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3768 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3769 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3770 kIoPageFaultType_PteInvalidLvlEncoding);
3771 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3772 }
3773#else
3774 Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
3775#endif
3776
3777 /* Validate level transition. */
3778 if (uNextLevel < uLevel)
3779 { /* likely */ }
3780 else
3781 {
3782 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
3783 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3784 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3785 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3786 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3787 kIoPageFaultType_PteInvalidLvlEncoding);
3788 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3789 }
3790
3791 /* Ensure IOVA bits of skipped levels are zero. */
3792 Assert(uLevel > 0);
3793 uint64_t uIovaSkipMask = 0;
3794 for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
3795 uIovaSkipMask |= s_auIovaLevelMasks[idxLevel];
3796 if (!(uIova & uIovaSkipMask))
3797 { /* likely */ }
3798 else
3799 {
3800 LogFunc(("IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF\n", uIova, uIovaSkipMask));
3801 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3802 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3803 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3804 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3805 kIoPageFaultType_SkippedLevelIovaNotZero);
3806 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3807 }
3808
3809 /* Continue with traversing the page directory at this level. */
3810 }
3811}
3812
3813
3814/**
3815 * Page lookup callback for finding an I/O page from guest memory.
3816 *
3817 * @returns VBox status code.
3818 * @retval VINF_SUCCESS when the page is found and has the right permissions.
3819 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED when address translation fails.
3820 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
3821 * insufficient to what is requested.
3822 *
3823 * @param pDevIns The IOMMU instance data.
3824 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
3825 * 4K aligned).
3826 * @param fPerm The I/O permissions for this access, see
3827 * IOMMU_IO_PERM_XXX.
3828 * @param pAux The auxiliary information required during lookup.
3829 * @param pPageLookup Where to store the looked up I/O page.
3830 */
3831static DECLCALLBACK(int) iommuAmdDteLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
3832 PIOPAGELOOKUP pPageLookup)
3833{
3834 AssertPtr(pAux);
3835 AssertPtr(pPageLookup);
3836 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
3837
3838 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3839 STAM_PROFILE_ADV_START(&pThis->StatProfDteLookup, a);
3840 int rc = iommuAmdIoPageTableWalk(pDevIns, uIovaPage, fPerm, pAux->idDevice, pAux->pDte, pAux->enmOp, pPageLookup);
3841 STAM_PROFILE_ADV_STOP(&pThis->StatProfDteLookup, a); NOREF(pThis);
3842 return rc;
3843}
3844
3845
3846/**
3847 * Looks up a range of I/O virtual addresses.
3848 *
3849 * @returns VBox status code.
3850 * @param pDevIns The IOMMU instance data.
3851 * @param pfnIoPageLookup The lookup function to use.
3852 * @param pAddrIn The I/O address range to lookup.
3853 * @param pAux The auxiliary information required by the lookup
3854 * function.
3855 * @param pAddrOut Where to store the translated I/O address range.
3856 * @param pcbPages Where to store the size of the access (round up to
3857 * the page size). Optional, can be NULL.
3858 */
3859static int iommuAmdLookupIoAddrRange(PPDMDEVINS pDevIns, PFNIOPAGELOOKUP pfnIoPageLookup, PCIOADDRRANGE pAddrIn,
3860 PCIOMMUOPAUX pAux, PIOADDRRANGE pAddrOut, size_t *pcbPages)
3861{
3862 AssertPtr(pfnIoPageLookup);
3863 AssertPtr(pAddrIn);
3864 AssertPtr(pAddrOut);
3865
3866 int rc;
3867 size_t const cbIova = pAddrIn->cb;
3868 uint8_t const fPerm = pAddrIn->fPerm;
3869 uint64_t const uIova = pAddrIn->uAddr;
3870 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3871 size_t cbRemaining = cbIova;
3872 uint64_t uIovaPage = pAddrIn->uAddr & X86_PAGE_4K_BASE_MASK;
3873 uint64_t offIova = pAddrIn->uAddr & X86_PAGE_4K_OFFSET_MASK;
3874 uint64_t cbPages = 0;
3875
3876 IOPAGELOOKUP PageLookupPrev;
3877 RT_ZERO(PageLookupPrev);
3878 for (;;)
3879 {
3880 IOPAGELOOKUP PageLookup;
3881 rc = pfnIoPageLookup(pDevIns, uIovaPage, fPerm, pAux, &PageLookup);
3882 if (RT_SUCCESS(rc))
3883 {
3884 Assert(PageLookup.cShift >= X86_PAGE_4K_SHIFT);
3885
3886 /* Store the translated address before continuing to access more pages. */
3887 if (cbRemaining == cbIova)
3888 {
3889 uint64_t const offMask = IOMMU_GET_PAGE_OFF_MASK(PageLookup.cShift);
3890 uint64_t const offSpa = uIova & offMask;
3891 Assert(!(PageLookup.GCPhysSpa & offMask));
3892 GCPhysSpa = PageLookup.GCPhysSpa | offSpa;
3893 }
3894 /* Check if addresses translated so far result in a physically contiguous region. */
3895 else if (!iommuAmdLookupIsAccessContig(&PageLookupPrev, &PageLookup))
3896 {
3897 rc = VERR_OUT_OF_RANGE;
3898 break;
3899 }
3900
3901 /* Store the page lookup result from the first/previous page. */
3902 PageLookupPrev = PageLookup;
3903
3904 /* Update size of all pages read thus far. */
3905 uint64_t const cbPage = RT_BIT_64(PageLookup.cShift);
3906 cbPages += cbPage;
3907
3908 /* Check if we need to access more pages. */
3909 if (cbRemaining > cbPage - offIova)
3910 {
3911 cbRemaining -= (cbPage - offIova); /* Calculate how much more we need to access. */
3912 uIovaPage += cbPage; /* Update address of the next access. */
3913 offIova = 0; /* After first page, all pages are accessed from off 0. */
3914 }
3915 else
3916 {
3917 cbRemaining = 0;
3918 break;
3919 }
3920 }
3921 else
3922 break;
3923 }
3924
3925 pAddrOut->uAddr = GCPhysSpa; /* Update the translated address. */
3926 pAddrOut->cb = cbIova - cbRemaining; /* Update the size of the contiguous memory region. */
3927 pAddrOut->fPerm = PageLookupPrev.fPerm; /* Update the allowed permissions for this access. */
3928 if (pcbPages)
3929 *pcbPages = cbPages; /* Update the size of the pages accessed. */
3930 return rc;
3931}
3932
3933
3934/**
3935 * Looks up an I/O virtual address from the device table.
3936 *
3937 * @returns VBox status code.
3938 * @param pDevIns The IOMMU instance data.
3939 * @param idDevice The device ID (bus, device, function).
3940 * @param uIova The I/O virtual address to lookup.
3941 * @param cbIova The size of the access.
3942 * @param fPerm The I/O permissions for this access, see
3943 * IOMMU_IO_PERM_XXX.
3944 * @param enmOp The IOMMU operation being performed.
3945 * @param pGCPhysSpa Where to store the translated system physical address.
3946 * @param pcbContiguous Where to store the number of contiguous bytes translated
3947 * and permission-checked.
3948 *
3949 * @thread Any.
3950 */
3951static int iommuAmdDteLookup(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova, uint8_t fPerm, IOMMUOP enmOp,
3952 PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
3953{
3954 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3955 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3956 size_t cbContiguous = 0;
3957
3958 /* Read the device table entry from memory. */
3959 DTE_T Dte;
3960 int rc = iommuAmdDteRead(pDevIns, idDevice, enmOp, &Dte);
3961 if (RT_SUCCESS(rc))
3962 {
3963 if (Dte.n.u1Valid)
3964 {
3965 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
3966 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
3967 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
3968 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
3969 {
3970 /*
3971 * Check if the DTE is configured for translating addresses.
3972 * Note: Addresses cannot be subject to exclusion as we do -not- support remote IOTLBs,
3973 * so there's no need to check the address exclusion base/limit here.
3974 */
3975 rc = iommuAmdPreTranslateChecks(pDevIns, idDevice, uIova, fPerm, &Dte, enmOp);
3976 if (rc == VINF_SUCCESS)
3977 {
3978 IOADDRRANGE AddrIn;
3979 AddrIn.uAddr = uIova;
3980 AddrIn.cb = cbIova;
3981 AddrIn.fPerm = fPerm;
3982
3983 IOMMUOPAUX Aux;
3984 Aux.enmOp = enmOp;
3985 Aux.pDte = &Dte;
3986 Aux.idDevice = idDevice;
3987 Aux.idDomain = Dte.n.u16DomainId;
3988
3989 IOADDRRANGE AddrOut;
3990
3991 /* Lookup the address from the DTE and I/O page tables.*/
3992 size_t cbPages = 0;
3993 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdDteLookupPage, &AddrIn, &Aux, &AddrOut, &cbPages);
3994 GCPhysSpa = AddrOut.uAddr;
3995 cbContiguous = AddrOut.cb;
3996
3997 /* If we stopped since translation resulted in non-contiguous physical addresses,
3998 what we translated so far is still valid. */
3999 if (rc == VERR_OUT_OF_RANGE)
4000 {
4001 Assert(cbContiguous > 0 && cbContiguous < cbIova);
4002 rc = VINF_SUCCESS;
4003 STAM_COUNTER_INC(&pThis->StatAccessDteNonContig); NOREF(pThis);
4004 }
4005
4006 if (rc == VERR_IOMMU_ADDR_ACCESS_DENIED)
4007 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
4008
4009#ifdef IOMMU_WITH_IOTLBE_CACHE
4010 if (RT_SUCCESS(rc))
4011 {
4012 /* Update that addresses requires translation (cumulative permissions of DTE and I/O page tables). */
4013 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, IOMMU_DTE_CACHE_F_ADDR_TRANSLATE);
4014 /* Update IOTLB for the contiguous range of I/O virtual addresses. */
4015 iommuAmdIotlbAddRange(pDevIns, Dte.n.u16DomainId, uIova & X86_PAGE_4K_BASE_MASK, cbPages,
4016 GCPhysSpa & X86_PAGE_4K_BASE_MASK, AddrOut.fPerm);
4017 }
4018#endif
4019 }
4020 else if (rc == VINF_IOMMU_ADDR_TRANSLATION_DISABLED)
4021 {
4022 /*
4023 * Translation is disabled for this device (root paging mode is 0).
4024 * GPA=SPA, but the permission bits are important and controls accesses.
4025 */
4026 GCPhysSpa = uIova;
4027 cbContiguous = cbIova;
4028 rc = VINF_SUCCESS;
4029
4030#ifdef IOMMU_WITH_IOTLBE_CACHE
4031 /* Update that addresses permissions of DTE apply (but omit address translation). */
4032 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, IOMMU_DTE_CACHE_F_IO_PERM);
4033#endif
4034 }
4035 else
4036 {
4037 /* Address translation failed or access is denied. */
4038 Assert(rc == VERR_IOMMU_ADDR_ACCESS_DENIED || rc == VERR_IOMMU_ADDR_TRANSLATION_FAILED);
4039 GCPhysSpa = NIL_RTGCPHYS;
4040 cbContiguous = 0;
4041 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
4042 }
4043 }
4044 else
4045 {
4046 /* Invalid reserved bits in the DTE, raise an error event. */
4047 LogFunc(("Invalid DTE reserved bits (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4048 EVT_ILLEGAL_DTE_T Event;
4049 iommuAmdIllegalDteEventInit(idDevice, uIova, true /* fRsvdNotZero */, enmOp, &Event);
4050 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4051 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4052 }
4053 }
4054 else
4055 {
4056 /*
4057 * The DTE is not valid, forward addresses untranslated.
4058 * See AMD IOMMU spec. "Table 5: Feature Enablement for Address Translation".
4059 */
4060 GCPhysSpa = uIova;
4061 cbContiguous = cbIova;
4062
4063#ifdef IOMMU_WITH_IOTLBE_CACHE
4064 /* Update that addresses don't require translation (nor permission checks) but a DTE is present. */
4065 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, 0 /* fFlags */);
4066#endif
4067 }
4068 }
4069 else
4070 {
4071 LogFunc(("Failed to read device table entry. idDevice=%#x rc=%Rrc\n", idDevice, rc));
4072 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4073 }
4074
4075 *pGCPhysSpa = GCPhysSpa;
4076 *pcbContiguous = cbContiguous;
4077 AssertMsg(rc != VINF_SUCCESS || cbContiguous > 0, ("cbContiguous=%zu\n", cbContiguous));
4078 return rc;
4079}
4080
4081
4082#ifdef IOMMU_WITH_IOTLBE_CACHE
4083/**
4084 * I/O page lookup callback for finding an I/O page from the IOTLB.
4085 *
4086 * @returns VBox status code.
4087 * @retval VINF_SUCCESS when the page is found and has the right permissions.
4088 * @retval VERR_NOT_FOUND when the page is not found.
4089 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
4090 * insufficient to what is requested.
4091 *
4092 * @param pDevIns The IOMMU instance data.
4093 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
4094 * 4K aligned).
4095 * @param fPerm The I/O permissions for this access, see
4096 * IOMMU_IO_PERM_XXX.
4097 * @param pAux The auxiliary information required during lookup.
4098 * @param pPageLookup Where to store the looked up I/O page.
4099 */
4100static DECLCALLBACK(int) iommuAmdCacheLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
4101 PIOPAGELOOKUP pPageLookup)
4102{
4103 Assert(pAux);
4104 Assert(pPageLookup);
4105 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
4106
4107 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4108 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4109
4110 STAM_PROFILE_ADV_START(&pThis->StatProfIotlbeLookup, a);
4111 PCIOTLBE pIotlbe = iommuAmdIotlbLookup(pThis, pThisR3, pAux->idDomain, uIovaPage);
4112 STAM_PROFILE_ADV_STOP(&pThis->StatProfIotlbeLookup, a);
4113 if (pIotlbe)
4114 {
4115 *pPageLookup = pIotlbe->PageLookup;
4116 if ((pPageLookup->fPerm & fPerm) == fPerm)
4117 {
4118 STAM_COUNTER_INC(&pThis->StatAccessCacheHit);
4119 return VINF_SUCCESS;
4120 }
4121 return VERR_IOMMU_ADDR_ACCESS_DENIED;
4122 }
4123 return VERR_NOT_FOUND;
4124}
4125
4126
4127/**
4128 * Lookups a memory access from the IOTLB cache.
4129 *
4130 * @returns VBox status code.
4131 * @retval VINF_SUCCESS if the access was cached and permissions are verified.
4132 * @retval VERR_OUT_OF_RANGE if the access resulted in a non-contiguous physical
4133 * address region.
4134 * @retval VERR_NOT_FOUND if the access was not cached.
4135 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the access was cached but permissions
4136 * are insufficient.
4137 *
4138 * @param pDevIns The IOMMU instance data.
4139 * @param idDevice The device ID (bus, device, function).
4140 * @param uIova The I/O virtual address to lookup.
4141 * @param cbIova The size of the access.
4142 * @param fPerm The I/O permissions for this access, see
4143 * IOMMU_IO_PERM_XXX.
4144 * @param enmOp The IOMMU operation being performed.
4145 * @param pGCPhysSpa Where to store the translated system physical address.
4146 * @param pcbContiguous Where to store the number of contiguous bytes translated
4147 * and permission-checked.
4148 */
4149static int iommuAmdIotlbCacheLookup(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova, uint8_t fPerm,
4150 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4151{
4152 int rc;
4153 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4154
4155#define IOMMU_IOTLB_LOOKUP_FAILED(a_rc) \
4156 do { \
4157 *pGCPhysSpa = NIL_RTGCPHYS; \
4158 *pcbContiguous = 0; \
4159 rc = (a_rc); \
4160 } while (0)
4161
4162 /*
4163 * We hold the cache lock across both the DTE and the IOTLB lookups (if any) because
4164 * we don't want the DTE cache to be invalidate while we perform IOTBL lookups.
4165 */
4166 IOMMU_CACHE_LOCK(pDevIns, pThis);
4167
4168 /* Lookup the DTE cache entry. */
4169 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, idDevice);
4170 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
4171 {
4172 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
4173 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4174 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4175 {
4176 /* Lookup IOTLB entries. */
4177 IOADDRRANGE AddrIn;
4178 AddrIn.uAddr = uIova;
4179 AddrIn.cb = cbIova;
4180 AddrIn.fPerm = fPerm;
4181
4182 IOMMUOPAUX Aux;
4183 Aux.enmOp = enmOp;
4184 Aux.pDte = NULL;
4185 Aux.idDevice = idDevice;
4186 Aux.idDomain = pDteCache->idDomain;
4187
4188 IOADDRRANGE AddrOut;
4189 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdCacheLookupPage, &AddrIn, &Aux, &AddrOut, NULL /* pcbPages */);
4190 Assert(AddrOut.cb <= cbIova);
4191 *pGCPhysSpa = AddrOut.uAddr;
4192 *pcbContiguous = AddrOut.cb;
4193 }
4194 else if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4195 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4196 {
4197 /* Address translation is disabled, but DTE permissions apply. */
4198 Assert(!(pDteCache->fFlags & IOMMU_DTE_CACHE_F_ADDR_TRANSLATE));
4199 uint8_t const fDtePerm = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_IO_PERM_SHIFT) & IOMMU_DTE_CACHE_F_IO_PERM_MASK;
4200 if ((fDtePerm & fPerm) == fPerm)
4201 {
4202 *pGCPhysSpa = uIova;
4203 *pcbContiguous = cbIova;
4204 rc = VINF_SUCCESS;
4205 }
4206 else
4207 IOMMU_IOTLB_LOOKUP_FAILED(VERR_IOMMU_ADDR_ACCESS_DENIED);
4208 }
4209 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
4210 {
4211 /* Forward addresses untranslated, without checking permissions. */
4212 *pGCPhysSpa = uIova;
4213 *pcbContiguous = cbIova;
4214 rc = VINF_SUCCESS;
4215 }
4216 else
4217 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4218 }
4219 else
4220 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4221
4222 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
4223
4224 return rc;
4225
4226#undef IOMMU_IOTLB_LOOKUP_FAILED
4227}
4228#endif /* IOMMU_WITH_IOTLBE_CACHE */
4229
4230
4231/**
4232 * Gets the I/O permission and IOMMU operation type for the given access flags.
4233 *
4234 * @param pThis The shared IOMMU device state.
4235 * @param fFlags The PDM IOMMU flags, PDMIOMMU_MEM_F_XXX.
4236 * @param penmOp Where to store the IOMMU operation.
4237 * @param pfPerm Where to store the IOMMU I/O permission.
4238 * @param fBulk Whether this is a bulk read or write.
4239 */
4240DECLINLINE(void) iommuAmdMemAccessGetPermAndOp(PIOMMU pThis, uint32_t fFlags, PIOMMUOP penmOp, uint8_t *pfPerm, bool fBulk)
4241{
4242 if (fFlags & PDMIOMMU_MEM_F_WRITE)
4243 {
4244 *penmOp = IOMMUOP_MEM_WRITE;
4245 *pfPerm = IOMMU_IO_PERM_WRITE;
4246#ifdef VBOX_WITH_STATISTICS
4247 if (!fBulk)
4248 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
4249 else
4250 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
4251#else
4252 RT_NOREF2(pThis, fBulk);
4253#endif
4254 }
4255 else
4256 {
4257 Assert(fFlags & PDMIOMMU_MEM_F_READ);
4258 *penmOp = IOMMUOP_MEM_READ;
4259 *pfPerm = IOMMU_IO_PERM_READ;
4260#ifdef VBOX_WITH_STATISTICS
4261 if (!fBulk)
4262 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
4263 else
4264 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
4265#else
4266 RT_NOREF2(pThis, fBulk);
4267#endif
4268 }
4269}
4270
4271
4272/**
4273 * Memory access transaction from a device.
4274 *
4275 * @returns VBox status code.
4276 * @param pDevIns The IOMMU device instance.
4277 * @param idDevice The device ID (bus, device, function).
4278 * @param uIova The I/O virtual address being accessed.
4279 * @param cbIova The size of the access.
4280 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4281 * @param pGCPhysSpa Where to store the translated system physical address.
4282 * @param pcbContiguous Where to store the number of contiguous bytes translated
4283 * and permission-checked.
4284 *
4285 * @thread Any.
4286 */
4287static DECLCALLBACK(int) iommuAmdMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
4288 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4289{
4290 /* Validate. */
4291 AssertPtr(pDevIns);
4292 AssertPtr(pGCPhysSpa);
4293 Assert(cbIova > 0);
4294 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4295
4296 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4297 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4298 if (Ctrl.n.u1IommuEn)
4299 {
4300 IOMMUOP enmOp;
4301 uint8_t fPerm;
4302 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, false /* fBulk */);
4303 LogFlowFunc(("%s: idDevice=%#x uIova=%#RX64 cb=%zu\n", iommuAmdMemAccessGetPermName(fPerm), idDevice, uIova, cbIova));
4304
4305 int rc;
4306#ifdef IOMMU_WITH_IOTLBE_CACHE
4307 /* Lookup the IOVA from the cache. */
4308 rc = iommuAmdIotlbCacheLookup(pDevIns, idDevice, uIova, cbIova, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4309 if (rc == VINF_SUCCESS)
4310 {
4311 /* All pages in the access were found in the cache with sufficient permissions. */
4312 Assert(*pcbContiguous == cbIova);
4313 Assert(*pGCPhysSpa != NIL_RTGCPHYS);
4314 STAM_COUNTER_INC(&pThis->StatAccessCacheHitFull);
4315 return VINF_SUCCESS;
4316 }
4317 if (rc != VERR_OUT_OF_RANGE)
4318 { /* likely */ }
4319 else
4320 {
4321 /* Access stopped since translations resulted in non-contiguous memory, let caller resume access. */
4322 Assert(*pcbContiguous > 0 && *pcbContiguous < cbIova);
4323 STAM_COUNTER_INC(&pThis->StatAccessCacheNonContig);
4324 return VINF_SUCCESS;
4325 }
4326
4327 /*
4328 * Access incomplete as not all pages were in the cache.
4329 * Or permissions were denied for the access (which typically doesn't happen)
4330 * so go through the slower path and raise the required event.
4331 */
4332 AssertMsg(*pcbContiguous < cbIova, ("Invalid size: cbContiguous=%zu cbIova=%zu\n", *pcbContiguous, cbIova));
4333 uIova += *pcbContiguous;
4334 cbIova -= *pcbContiguous;
4335 /* We currently are including any permission denied pages as cache misses too.*/
4336 STAM_COUNTER_INC(&pThis->StatAccessCacheMiss);
4337#endif
4338
4339 /* Lookup the IOVA from the device table. */
4340 rc = iommuAmdDteLookup(pDevIns, idDevice, uIova, cbIova, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4341 if (RT_SUCCESS(rc))
4342 { /* likely */ }
4343 else
4344 {
4345 Assert(rc != VERR_OUT_OF_RANGE);
4346 LogFunc(("DTE lookup failed! idDevice=%#x uIova=%#RX64 fPerm=%u cbIova=%zu rc=%#Rrc\n", idDevice, uIova, fPerm,
4347 cbIova, rc));
4348 }
4349
4350 return rc;
4351 }
4352
4353 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4354 *pGCPhysSpa = uIova;
4355 *pcbContiguous = cbIova;
4356 return VINF_SUCCESS;
4357}
4358
4359
4360/**
4361 * Memory access bulk (one or more 4K pages) request from a device.
4362 *
4363 * @returns VBox status code.
4364 * @param pDevIns The IOMMU device instance.
4365 * @param idDevice The device ID (bus, device, function).
4366 * @param cIovas The number of addresses being accessed.
4367 * @param pauIovas The I/O virtual addresses for each page being accessed.
4368 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4369 * @param paGCPhysSpa Where to store the translated physical addresses.
4370 *
4371 * @thread Any.
4372 */
4373static DECLCALLBACK(int) iommuAmdMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
4374 uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
4375{
4376 /* Validate. */
4377 AssertPtr(pDevIns);
4378 Assert(cIovas > 0);
4379 AssertPtr(pauIovas);
4380 AssertPtr(paGCPhysSpa);
4381 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4382
4383 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4384 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4385 if (Ctrl.n.u1IommuEn)
4386 {
4387 IOMMUOP enmOp;
4388 uint8_t fPerm;
4389 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, true /* fBulk */);
4390 LogFlowFunc(("%s: idDevice=%#x cIovas=%zu\n", iommuAmdMemAccessGetPermName(fPerm), idDevice, cIovas));
4391
4392 for (size_t i = 0; i < cIovas; i++)
4393 {
4394 int rc;
4395 size_t cbContig;
4396
4397#ifdef IOMMU_WITH_IOTLBE_CACHE
4398 /* Lookup the IOVA from the IOTLB cache. */
4399 rc = iommuAmdIotlbCacheLookup(pDevIns, idDevice, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i],
4400 &cbContig);
4401 if (rc == VINF_SUCCESS)
4402 {
4403 Assert(cbContig == X86_PAGE_SIZE);
4404 Assert(paGCPhysSpa[i] != NIL_RTGCPHYS);
4405 STAM_COUNTER_INC(&pThis->StatAccessCacheHitFull);
4406 continue;
4407 }
4408 Assert(rc == VERR_NOT_FOUND || rc == VERR_IOMMU_ADDR_ACCESS_DENIED);
4409 STAM_COUNTER_INC(&pThis->StatAccessCacheMiss);
4410#endif
4411
4412 /* Lookup the IOVA from the device table. */
4413 rc = iommuAmdDteLookup(pDevIns, idDevice, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i], &cbContig);
4414 if (RT_SUCCESS(rc))
4415 { /* likely */ }
4416 else
4417 {
4418 LogFunc(("Failed! idDevice=%#x uIova=%#RX64 fPerm=%u rc=%Rrc\n", idDevice, pauIovas[i], fPerm, rc));
4419 return rc;
4420 }
4421 Assert(cbContig == X86_PAGE_SIZE);
4422 }
4423 }
4424 else
4425 {
4426 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4427 for (size_t i = 0; i < cIovas; i++)
4428 paGCPhysSpa[i] = pauIovas[i];
4429 }
4430
4431 return VINF_SUCCESS;
4432}
4433
4434
4435/**
4436 * Reads an interrupt remapping table entry from guest memory given its DTE.
4437 *
4438 * @returns VBox status code.
4439 * @param pDevIns The IOMMU device instance.
4440 * @param idDevice The device ID (bus, device, function).
4441 * @param pDte The device table entry.
4442 * @param GCPhysIn The source MSI address (used for reporting errors).
4443 * @param uDataIn The source MSI data.
4444 * @param enmOp The IOMMU operation being performed.
4445 * @param pIrte Where to store the interrupt remapping table entry.
4446 *
4447 * @thread Any.
4448 */
4449static int iommuAmdIrteRead(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
4450 IOMMUOP enmOp, PIRTE_T pIrte)
4451{
4452 /* Ensure the IRTE length is valid. */
4453 Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
4454
4455 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
4456 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
4457 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(uDataIn);
4458 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
4459
4460 /* Ensure the IRTE falls completely within the interrupt table. */
4461 if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
4462 { /* likely */ }
4463 else
4464 {
4465 LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
4466 GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
4467
4468 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4469 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
4470 false /* fPermDenied */, enmOp, &EvtIoPageFault);
4471 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4472 kIoPageFaultType_IrteAddrInvalid);
4473 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4474 }
4475
4476 /* Read the IRTE from memory. */
4477 Assert(!(GCPhysIrte & 3));
4478 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
4479 if (RT_SUCCESS(rc))
4480 return VINF_SUCCESS;
4481
4482 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
4483 * situation. Is it an I/O page fault or a device table hardware error?
4484 * There's no interrupt table hardware error event, but it's unclear what
4485 * we should do here. */
4486 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
4487 return VERR_IOMMU_IPE_4;
4488}
4489
4490
4491/**
4492 * Remaps the interrupt using the interrupt remapping table.
4493 *
4494 * @returns VBox status code.
4495 * @param pDevIns The IOMMU instance data.
4496 * @param idDevice The device ID (bus, device, function).
4497 * @param pDte The device table entry.
4498 * @param enmOp The IOMMU operation being performed.
4499 * @param pMsiIn The source MSI.
4500 * @param pMsiOut Where to store the remapped MSI.
4501 *
4502 * @thread Any.
4503 */
4504static int iommuAmdIntrRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
4505 PMSIMSG pMsiOut)
4506{
4507 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
4508
4509 IRTE_T Irte;
4510 uint32_t const uMsiInData = pMsiIn->Data.u32;
4511 int rc = iommuAmdIrteRead(pDevIns, idDevice, pDte, pMsiIn->Addr.u64, uMsiInData, enmOp, &Irte);
4512 if (RT_SUCCESS(rc))
4513 {
4514 if (Irte.n.u1RemapEnable)
4515 {
4516 if (!Irte.n.u1GuestMode)
4517 {
4518 if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
4519 {
4520 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, &Irte);
4521#ifdef IOMMU_WITH_IRTE_CACHE
4522 iommuAmdIrteCacheAdd(pDevIns, idDevice, IOMMU_GET_IRTE_OFF(uMsiInData), &Irte);
4523#endif
4524 return VINF_SUCCESS;
4525 }
4526
4527 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
4528 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4529 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4530 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4531 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault,
4532 kIoPageFaultType_IrteRsvdIntType);
4533 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4534 }
4535
4536 LogFunc(("Guest mode not supported -> IOPF\n"));
4537 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4538 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4539 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4540 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
4541 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4542 }
4543
4544 LogFunc(("Remapping disabled -> IOPF\n"));
4545 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4546 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4547 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4548 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
4549 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4550 }
4551
4552 return rc;
4553}
4554
4555
4556/**
4557 * Looks up an MSI interrupt from the interrupt remapping table.
4558 *
4559 * @returns VBox status code.
4560 * @param pDevIns The IOMMU instance data.
4561 * @param idDevice The device ID (bus, device, function).
4562 * @param enmOp The IOMMU operation being performed.
4563 * @param pMsiIn The source MSI.
4564 * @param pMsiOut Where to store the remapped MSI.
4565 *
4566 * @thread Any.
4567 */
4568static int iommuAmdIntrTableLookup(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4569{
4570 LogFlowFunc(("idDevice=%#x (%#x:%#x:%#x) enmOp=%u\n", idDevice, ((idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK),
4571 ((idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK), (idDevice & VBOX_PCI_DEVFN_FUN_MASK),
4572 enmOp));
4573
4574 /* Read the device table entry from memory. */
4575 DTE_T Dte;
4576 int rc = iommuAmdDteRead(pDevIns, idDevice, enmOp, &Dte);
4577 if (RT_SUCCESS(rc))
4578 {
4579#ifdef IOMMU_WITH_IRTE_CACHE
4580 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, 0 /* fFlags */);
4581#endif
4582 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
4583 if (Dte.n.u1IntrMapValid)
4584 {
4585 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
4586 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
4587 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
4588 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
4589 { /* likely */ }
4590 else
4591 {
4592 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4593 EVT_ILLEGAL_DTE_T Event;
4594 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4595 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4596 return VERR_IOMMU_INTR_REMAP_FAILED;
4597 }
4598
4599 /*
4600 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
4601 * that's connected through HyperTransport it might be possible; but for us, it
4602 * doesn't seem we need to specially handle these pins.
4603 */
4604
4605 /*
4606 * Validate the MSI source address.
4607 *
4608 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
4609 * CPU is concerned, the MSI region is fixed and we must ensure no other device
4610 * claims the region as I/O space.
4611 *
4612 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
4613 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
4614 * See Intel spec. 10.11.1 "Message Address Register Format".
4615 */
4616 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
4617 {
4618 /*
4619 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
4620 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
4621 */
4622 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
4623 bool fPassThru = false;
4624 switch (u8DeliveryMode)
4625 {
4626 case VBOX_MSI_DELIVERY_MODE_FIXED:
4627 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
4628 {
4629 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
4630 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
4631 {
4632 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
4633 uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
4634 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4635 {
4636 /*
4637 * We don't support guest interrupt remapping yet. When we do, we'll need to
4638 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
4639 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
4640 * already reads the control register, add that as a parameter when we eventually
4641 * support guest interrupt remapping. For now, just assert.
4642 */
4643 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4644 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
4645 NOREF(pThis);
4646
4647 return iommuAmdIntrRemap(pDevIns, idDevice, &Dte, enmOp, pMsiIn, pMsiOut);
4648 }
4649
4650 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
4651 EVT_ILLEGAL_DTE_T Event;
4652 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
4653 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
4654 return VERR_IOMMU_INTR_REMAP_FAILED;
4655 }
4656
4657 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
4658 {
4659 fPassThru = true;
4660 break;
4661 }
4662
4663 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
4664 {
4665 LogRelMax(10, ("%s: Remapping disallowed for fixed/arbitrated interrupt %#x -> Target abort\n",
4666 IOMMU_LOG_PFX, pMsiIn->Data.n.u8Vector));
4667 iommuAmdSetPciTargetAbort(pDevIns);
4668 return VERR_IOMMU_INTR_REMAP_DENIED;
4669 }
4670
4671 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD); /* Paranoia. */
4672 LogRelMax(10, ("%s: IntCtl mode invalid %#x -> Illegal DTE\n", IOMMU_LOG_PFX, uIntrCtrl));
4673 EVT_ILLEGAL_DTE_T Event;
4674 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4675 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
4676 return VERR_IOMMU_INTR_REMAP_FAILED;
4677 }
4678
4679 /* SMIs are passed through unmapped. We don't implement SMI filters. */
4680 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
4681 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
4682 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
4683 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
4684 default:
4685 {
4686 LogRelMax(10, ("%s: MSI data delivery mode invalid %#x -> Target abort\n", IOMMU_LOG_PFX,
4687 u8DeliveryMode));
4688 iommuAmdSetPciTargetAbort(pDevIns);
4689 return VERR_IOMMU_INTR_REMAP_FAILED;
4690 }
4691 }
4692
4693 /*
4694 * For those other than fixed and arbitrated interrupts, destination mode must be 0 (physical).
4695 * See AMD IOMMU spec. The note below Table 19: "IOMMU Controls and Actions for Upstream Interrupts".
4696 */
4697 if ( u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO
4698 || !pMsiIn->Addr.n.u1DestMode)
4699 {
4700 if (fPassThru)
4701 {
4702 *pMsiOut = *pMsiIn;
4703 return VINF_SUCCESS;
4704 }
4705 LogRelMax(10, ("%s: Remapping/passthru disallowed for interrupt %#x -> Target abort\n", IOMMU_LOG_PFX,
4706 pMsiIn->Data.n.u8Vector));
4707 }
4708 else
4709 LogRelMax(10, ("%s: Logical destination mode invalid for delivery mode %#x\n -> Target abort\n",
4710 IOMMU_LOG_PFX, u8DeliveryMode));
4711
4712 iommuAmdSetPciTargetAbort(pDevIns);
4713 return VERR_IOMMU_INTR_REMAP_DENIED;
4714 }
4715 else
4716 {
4717 /** @todo should be cause a PCI target abort here? */
4718 LogRelMax(10, ("%s: MSI address region invalid %#RX64\n", IOMMU_LOG_PFX, pMsiIn->Addr.u64));
4719 return VERR_IOMMU_INTR_REMAP_FAILED;
4720 }
4721 }
4722 else
4723 {
4724 LogFlowFunc(("DTE interrupt map not valid\n"));
4725 *pMsiOut = *pMsiIn;
4726 return VINF_SUCCESS;
4727 }
4728 }
4729
4730 LogFunc(("Failed to read device table entry. idDevice=%#x rc=%Rrc\n", idDevice, rc));
4731 return VERR_IOMMU_INTR_REMAP_FAILED;
4732}
4733
4734
4735/**
4736 * Interrupt remap request from a device.
4737 *
4738 * @returns VBox status code.
4739 * @param pDevIns The IOMMU device instance.
4740 * @param idDevice The device ID (bus, device, function).
4741 * @param pMsiIn The source MSI.
4742 * @param pMsiOut Where to store the remapped MSI.
4743 */
4744static DECLCALLBACK(int) iommuAmdMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4745{
4746 /* Validate. */
4747 Assert(pDevIns);
4748 Assert(pMsiIn);
4749 Assert(pMsiOut);
4750
4751 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4752
4753 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
4754 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4755 if (Ctrl.n.u1IommuEn)
4756 {
4757 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
4758
4759 int rc;
4760#ifdef IOMMU_WITH_IRTE_CACHE
4761 STAM_PROFILE_ADV_START(&pThis->StatProfIrteCacheLookup, a);
4762 rc = iommuAmdIrteCacheLookup(pDevIns, idDevice, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4763 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteCacheLookup, a);
4764 if (RT_SUCCESS(rc))
4765 {
4766 STAM_COUNTER_INC(&pThis->StatIntrCacheHit);
4767 return VINF_SUCCESS;
4768 }
4769 STAM_COUNTER_INC(&pThis->StatIntrCacheMiss);
4770#endif
4771
4772 STAM_PROFILE_ADV_START(&pThis->StatProfIrteLookup, a);
4773 rc = iommuAmdIntrTableLookup(pDevIns, idDevice, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4774 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteLookup, a);
4775 return rc;
4776 }
4777
4778 *pMsiOut = *pMsiIn;
4779 return VINF_SUCCESS;
4780}
4781
4782
4783/**
4784 * @callback_method_impl{FNIOMMMIONEWWRITE}
4785 */
4786static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
4787{
4788 NOREF(pvUser);
4789 Assert(cb == 4 || cb == 8);
4790 Assert(!(off & (cb - 1)));
4791
4792 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4793 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
4794
4795 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
4796 return iommuAmdRegisterWrite(pDevIns, off, cb, uValue);
4797}
4798
4799
4800/**
4801 * @callback_method_impl{FNIOMMMIONEWREAD}
4802 */
4803static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
4804{
4805 NOREF(pvUser);
4806 Assert(cb == 4 || cb == 8);
4807 Assert(!(off & (cb - 1)));
4808
4809 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4810 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
4811
4812 uint64_t uResult;
4813 VBOXSTRICTRC rcStrict = iommuAmdRegisterRead(pDevIns, off, &uResult);
4814 if (rcStrict == VINF_SUCCESS)
4815 {
4816 if (cb == 8)
4817 *(uint64_t *)pv = uResult;
4818 else
4819 *(uint32_t *)pv = (uint32_t)uResult;
4820 }
4821
4822 return rcStrict;
4823}
4824
4825
4826#ifdef IN_RING3
4827/**
4828 * Processes an IOMMU command.
4829 *
4830 * @returns VBox status code.
4831 * @param pDevIns The IOMMU device instance.
4832 * @param pCmd The command to process.
4833 * @param GCPhysCmd The system physical address of the command.
4834 * @param pEvtError Where to store the error event in case of failures.
4835 *
4836 * @thread Command thread.
4837 */
4838static int iommuAmdR3CmdProcess(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
4839{
4840 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4841 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4842
4843 STAM_COUNTER_INC(&pThis->StatCmd);
4844
4845 uint8_t const bCmd = pCmd->n.u4Opcode;
4846 switch (bCmd)
4847 {
4848 case IOMMU_CMD_COMPLETION_WAIT:
4849 {
4850 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
4851
4852 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
4853 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
4854
4855 /* Validate reserved bits in the command. */
4856 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
4857 {
4858 /* If Completion Store is requested, write the StoreData to the specified address. */
4859 if (pCmdComWait->n.u1Store)
4860 {
4861 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
4862 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
4863 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
4864 if (RT_FAILURE(rc))
4865 {
4866 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
4867 GCPhysStore, rc));
4868 iommuAmdCmdHwErrorEventInit(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
4869 return VERR_IOMMU_CMD_HW_ERROR;
4870 }
4871 }
4872
4873 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
4874 if (pCmdComWait->n.u1Interrupt)
4875 {
4876 IOMMU_LOCK(pDevIns, pThisR3);
4877 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
4878 bool const fRaiseInt = pThis->Ctrl.n.u1CompWaitIntrEn;
4879 IOMMU_UNLOCK(pDevIns, pThisR3);
4880 if (fRaiseInt)
4881 iommuAmdMsiInterruptRaise(pDevIns);
4882 }
4883 return VINF_SUCCESS;
4884 }
4885 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4886 return VERR_IOMMU_CMD_INVALID_FORMAT;
4887 }
4888
4889 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
4890 {
4891 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
4892 PCCMD_INV_DTE_T pCmdInvDte = (PCCMD_INV_DTE_T)pCmd;
4893 AssertCompile(sizeof(*pCmdInvDte) == sizeof(*pCmd));
4894
4895 /* Validate reserved bits in the command. */
4896 if ( !(pCmdInvDte->au64[0] & ~IOMMU_CMD_INV_DTE_QWORD_0_VALID_MASK)
4897 && !(pCmdInvDte->au64[1] & ~IOMMU_CMD_INV_DTE_QWORD_1_VALID_MASK))
4898 {
4899#ifdef IOMMU_WITH_DTE_CACHE
4900 iommuAmdDteCacheRemove(pDevIns, pCmdInvDte->n.u16DevId);
4901#endif
4902 return VINF_SUCCESS;
4903 }
4904 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4905 return VERR_IOMMU_CMD_INVALID_FORMAT;
4906 }
4907
4908 case IOMMU_CMD_INV_IOMMU_PAGES:
4909 {
4910 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
4911 PCCMD_INV_IOMMU_PAGES_T pCmdInvPages = (PCCMD_INV_IOMMU_PAGES_T)pCmd;
4912 AssertCompile(sizeof(*pCmdInvPages) == sizeof(*pCmd));
4913
4914 /* Validate reserved bits in the command. */
4915 if ( !(pCmdInvPages->au64[0] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_0_VALID_MASK)
4916 && !(pCmdInvPages->au64[1] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_1_VALID_MASK))
4917 {
4918#ifdef IOMMU_WITH_IOTLBE_CACHE
4919 uint64_t const uIova = RT_MAKE_U64(pCmdInvPages->n.u20AddrLo << X86_PAGE_4K_SHIFT, pCmdInvPages->n.u32AddrHi);
4920 uint16_t const idDomain = pCmdInvPages->n.u16DomainId;
4921 uint8_t cShift;
4922 if (!pCmdInvPages->n.u1Size)
4923 cShift = X86_PAGE_4K_SHIFT;
4924 else
4925 {
4926 /* Find the first clear bit starting from bit 12 to 64 of the I/O virtual address. */
4927 unsigned const uFirstZeroBit = ASMBitLastSetU64(~(uIova >> X86_PAGE_4K_SHIFT));
4928 cShift = X86_PAGE_4K_SHIFT + uFirstZeroBit;
4929
4930 /*
4931 * For the address 0x7ffffffffffff000, cShift would be 76 (12+64) and the code below
4932 * would do the right thing by clearing the entire cache for the specified domain ID.
4933 *
4934 * However, for the address 0xfffffffffffff000, cShift would be computed as 12.
4935 * IOMMU behavior is undefined in this case, so it's safe to invalidate just one page.
4936 * A debug-time assert is in place here to let us know if any software tries this.
4937 *
4938 * See AMD IOMMU spec. 2.4.3 "INVALIDATE_IOMMU_PAGES".
4939 * See AMD IOMMU spec. Table 14: "Example Page Size Encodings".
4940 */
4941 Assert(uIova != UINT64_C(0xfffffffffffff000));
4942 }
4943
4944 /*
4945 * Validate invalidation size.
4946 * See AMD IOMMU spec. 2.2.3 "I/O Page Tables for Host Translations".
4947 */
4948 if ( cShift == 12 /* 4K */ || cShift == 13 /* 8K */
4949 || cShift == 14 /* 16K */ || cShift == 20 /* 1M */
4950 || cShift == 22 /* 4M */ || cShift == 32 /* 4G */)
4951 {
4952 /* Remove the range of I/O virtual addresses requesting to be invalidated. */
4953 size_t const cbIova = RT_BIT_64(cShift);
4954 iommuAmdIotlbRemoveRange(pDevIns, idDomain, uIova, cbIova);
4955 }
4956 else
4957 {
4958 /*
4959 * The guest provided size is invalid or exceeds the largest, meaningful page size.
4960 * In such situations we must remove all ranges for the specified domain ID.
4961 */
4962 iommuAmdIotlbRemoveDomainId(pDevIns, idDomain);
4963 }
4964#endif
4965 return VINF_SUCCESS;
4966 }
4967 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4968 return VERR_IOMMU_CMD_INVALID_FORMAT;
4969 }
4970
4971 case IOMMU_CMD_INV_IOTLB_PAGES:
4972 {
4973 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
4974
4975 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
4976 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
4977 {
4978 /** @todo IOMMU: Implement remote IOTLB invalidation. */
4979 return VERR_NOT_IMPLEMENTED;
4980 }
4981 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4982 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4983 }
4984
4985 case IOMMU_CMD_INV_INTR_TABLE:
4986 {
4987 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
4988
4989 PCCMD_INV_INTR_TABLE_T pCmdInvIntrTable = (PCCMD_INV_INTR_TABLE_T)pCmd;
4990 AssertCompile(sizeof(*pCmdInvIntrTable) == sizeof(*pCmd));
4991
4992 /* Validate reserved bits in the command. */
4993 if ( !(pCmdInvIntrTable->au64[0] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_0_VALID_MASK)
4994 && !(pCmdInvIntrTable->au64[1] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_1_VALID_MASK))
4995 {
4996#ifdef IOMMU_WITH_IRTE_CACHE
4997 iommuAmdIrteCacheRemove(pDevIns, pCmdInvIntrTable->u.u16DevId);
4998#endif
4999 return VINF_SUCCESS;
5000 }
5001 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5002 return VERR_IOMMU_CMD_INVALID_FORMAT;
5003 }
5004
5005 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
5006 {
5007 /* Linux doesn't use prefetching of IOMMU pages, so we don't bother for now. */
5008 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
5009 Assert(!pThis->ExtFeat.n.u1PrefetchSup);
5010 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5011 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5012 }
5013
5014 case IOMMU_CMD_COMPLETE_PPR_REQ:
5015 {
5016 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
5017
5018 /* We don't support PPR requests yet. */
5019 Assert(!pThis->ExtFeat.n.u1PprSup);
5020 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5021 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5022 }
5023
5024 case IOMMU_CMD_INV_IOMMU_ALL:
5025 {
5026 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
5027 if (pThis->ExtFeat.n.u1InvAllSup)
5028 {
5029 PCCMD_INV_IOMMU_ALL_T pCmdInvAll = (PCCMD_INV_IOMMU_ALL_T)pCmd;
5030 AssertCompile(sizeof(*pCmdInvAll) == sizeof(*pCmd));
5031
5032 /* Validate reserved bits in the command. */
5033 if ( !(pCmdInvAll->au64[0] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_0_VALID_MASK)
5034 && !(pCmdInvAll->au64[1] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_1_VALID_MASK))
5035 {
5036#ifdef IOMMU_WITH_DTE_CACHE
5037 iommuAmdDteCacheRemoveAll(pDevIns);
5038#endif
5039#ifdef IOMMU_WITH_IOTLBE_CACHE
5040 iommuAmdIotlbRemoveAll(pDevIns);
5041#endif
5042 return VINF_SUCCESS;
5043 }
5044 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5045 return VERR_IOMMU_CMD_INVALID_FORMAT;
5046 }
5047 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5048 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5049 }
5050 }
5051
5052 STAM_COUNTER_DEC(&pThis->StatCmd);
5053 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
5054 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5055 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5056}
5057
5058
5059/**
5060 * The IOMMU command thread.
5061 *
5062 * @returns VBox status code.
5063 * @param pDevIns The IOMMU device instance.
5064 * @param pThread The command thread.
5065 */
5066static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5067{
5068 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5069 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5070
5071 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
5072 return VINF_SUCCESS;
5073
5074 /*
5075 * Pre-allocate the maximum command buffer size supported by the IOMMU.
5076 * This avoid trashing the heap as well as not wasting time allocating
5077 * and freeing buffers while processing commands.
5078 */
5079 size_t const cbMaxCmdBuf = sizeof(CMD_GENERIC_T) * iommuAmdGetBufMaxEntries(15);
5080 void *pvCmds = RTMemAllocZ(cbMaxCmdBuf);
5081 AssertPtrReturn(pvCmds, VERR_NO_MEMORY);
5082
5083 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
5084 {
5085 /*
5086 * Sleep perpetually until we are woken up to process commands.
5087 */
5088 bool const fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
5089 if (!fSignaled)
5090 {
5091 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
5092 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
5093 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
5094 break;
5095 Log4Func(("Woken up with rc=%Rrc\n", rc));
5096 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
5097 }
5098
5099 /*
5100 * Fetch and process IOMMU commands.
5101 */
5102 /** @todo r=ramshankar: We currently copy all commands from guest memory into a
5103 * temporary host buffer before processing them as a batch. If we want to
5104 * save on host memory a bit, we could (once PGM has the necessary APIs)
5105 * lock the page mappings page mappings and access them directly. */
5106 IOMMU_LOCK(pDevIns, pThisR3);
5107
5108 if (pThis->Status.n.u1CmdBufRunning)
5109 {
5110 /* Get the offsets we need to read commands from memory (circular buffer offset). */
5111 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
5112 uint32_t const offTail = pThis->CmdBufTailPtr.n.off;
5113 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
5114
5115 /* Validate. */
5116 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
5117 Assert(offHead < cbCmdBuf);
5118 Assert(cbCmdBuf <= cbMaxCmdBuf);
5119
5120 if (offHead != offTail)
5121 {
5122 /* Read the entire command buffer from memory (avoids multiple PGM calls). */
5123 RTGCPHYS const GCPhysCmdBufBase = pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
5124
5125 IOMMU_UNLOCK(pDevIns, pThisR3);
5126 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmdBufBase, pvCmds, cbCmdBuf);
5127 IOMMU_LOCK(pDevIns, pThisR3);
5128
5129 if (RT_SUCCESS(rc))
5130 {
5131 /* Indicate to software we've fetched all commands from the buffer. */
5132 pThis->CmdBufHeadPtr.n.off = offTail;
5133
5134 /* Allow IOMMU to do other work while we process commands. */
5135 IOMMU_UNLOCK(pDevIns, pThisR3);
5136
5137 /* Process the fetched commands. */
5138 EVT_GENERIC_T EvtError;
5139 do
5140 {
5141 PCCMD_GENERIC_T pCmd = (PCCMD_GENERIC_T)((uintptr_t)pvCmds + offHead);
5142 rc = iommuAmdR3CmdProcess(pDevIns, pCmd, GCPhysCmdBufBase + offHead, &EvtError);
5143 if (RT_FAILURE(rc))
5144 {
5145 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
5146 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
5147 {
5148 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
5149 iommuAmdIllegalCmdEventRaise(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
5150 }
5151 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
5152 {
5153 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
5154 LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", pCmd->n.u4Opcode));
5155 iommuAmdCmdHwErrorEventRaise(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
5156 }
5157 break;
5158 }
5159
5160 /* Move to the next command in the circular buffer. */
5161 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
5162 } while (offHead != offTail);
5163 }
5164 else
5165 {
5166 LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmdBufBase, rc));
5167 EVT_CMD_HW_ERR_T EvtCmdHwErr;
5168 iommuAmdCmdHwErrorEventInit(GCPhysCmdBufBase, &EvtCmdHwErr);
5169 iommuAmdCmdHwErrorEventRaise(pDevIns, &EvtCmdHwErr);
5170
5171 IOMMU_UNLOCK(pDevIns, pThisR3);
5172 }
5173 }
5174 else
5175 IOMMU_UNLOCK(pDevIns, pThisR3);
5176 }
5177 else
5178 IOMMU_UNLOCK(pDevIns, pThisR3);
5179 }
5180
5181 RTMemFree(pvCmds);
5182 LogFlowFunc(("Command thread terminating\n"));
5183 return VINF_SUCCESS;
5184}
5185
5186
5187/**
5188 * Wakes up the command thread so it can respond to a state change.
5189 *
5190 * @returns VBox status code.
5191 * @param pDevIns The IOMMU device instance.
5192 * @param pThread The command thread.
5193 */
5194static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5195{
5196 RT_NOREF(pThread);
5197 LogFlowFunc(("\n"));
5198 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5199 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
5200}
5201
5202
5203/**
5204 * @callback_method_impl{FNPCICONFIGREAD}
5205 */
5206static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5207 unsigned cb, uint32_t *pu32Value)
5208{
5209 /** @todo IOMMU: PCI config read stat counter. */
5210 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
5211 Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
5212 return rcStrict;
5213}
5214
5215
5216/**
5217 * Sets up the IOMMU MMIO region (usually in response to an IOMMU base address
5218 * register write).
5219 *
5220 * @returns VBox status code.
5221 * @param pDevIns The IOMMU instance data.
5222 *
5223 * @remarks Call this function only when the IOMMU BAR is enabled.
5224 */
5225static int iommuAmdR3MmioSetup(PPDMDEVINS pDevIns)
5226{
5227 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5228 Assert(pThis->IommuBar.n.u1Enable);
5229 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
5230 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
5231 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
5232 RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
5233
5234 /* If the MMIO region is already mapped at the specified address, we're done. */
5235 Assert(GCPhysMmioBase != NIL_RTGCPHYS);
5236 if (GCPhysMmioBasePrev == GCPhysMmioBase)
5237 return VINF_SUCCESS;
5238
5239 /* Unmap the previous MMIO region (which is at a different address). */
5240 if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
5241 {
5242 LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
5243 int rc = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
5244 if (RT_FAILURE(rc))
5245 {
5246 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBasePrev, rc));
5247 return rc;
5248 }
5249 }
5250
5251 /* Map the newly specified MMIO region. */
5252 LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
5253 int rc = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
5254 if (RT_FAILURE(rc))
5255 {
5256 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rc));
5257 return rc;
5258 }
5259
5260 return VINF_SUCCESS;
5261}
5262
5263
5264/**
5265 * @callback_method_impl{FNPCICONFIGWRITE}
5266 */
5267static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5268 unsigned cb, uint32_t u32Value)
5269{
5270 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5271
5272 /*
5273 * Discard writes to read-only registers that are specific to the IOMMU.
5274 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
5275 * See PCI spec. 6.1. "Configuration Space Organization".
5276 */
5277 switch (uAddress)
5278 {
5279 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
5280 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
5281 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
5282 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
5283 {
5284 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
5285 return VINF_SUCCESS;
5286 }
5287 }
5288
5289 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5290 IOMMU_LOCK(pDevIns, pThisR3);
5291
5292 VBOXSTRICTRC rcStrict;
5293 switch (uAddress)
5294 {
5295 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
5296 {
5297 if (!pThis->IommuBar.n.u1Enable)
5298 {
5299 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
5300 if (pThis->IommuBar.n.u1Enable)
5301 rcStrict = iommuAmdR3MmioSetup(pDevIns);
5302 else
5303 rcStrict = VINF_SUCCESS;
5304 }
5305 else
5306 {
5307 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
5308 rcStrict = VINF_SUCCESS;
5309 }
5310 break;
5311 }
5312
5313 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
5314 {
5315 if (!pThis->IommuBar.n.u1Enable)
5316 {
5317 AssertCompile((IOMMU_BAR_VALID_MASK >> 32) == 0xffffffff);
5318 pThis->IommuBar.au32[1] = u32Value;
5319 }
5320 else
5321 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
5322 rcStrict = VINF_SUCCESS;
5323 break;
5324 }
5325
5326 case IOMMU_PCI_OFF_MSI_CAP_HDR:
5327 {
5328 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
5329 RT_FALL_THRU();
5330 }
5331 default:
5332 {
5333 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
5334 break;
5335 }
5336 }
5337
5338 IOMMU_UNLOCK(pDevIns, pThisR3);
5339
5340 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
5341 return rcStrict;
5342}
5343
5344
5345/**
5346 * @callback_method_impl{FNDBGFHANDLERDEV}
5347 */
5348static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5349{
5350 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5351 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5352 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5353
5354 bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
5355
5356 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
5357 /* Device Table Base Addresses (all segments). */
5358 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
5359 {
5360 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
5361 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
5362 if (fVerbose)
5363 {
5364 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
5365 IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
5366 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5367 DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
5368 }
5369 }
5370 /* Command Buffer Base Address Register. */
5371 {
5372 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
5373 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
5374 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5375 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5376 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
5377 if (fVerbose)
5378 {
5379 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5380 CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
5381 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5382 cEntries, cbBuffer);
5383 }
5384 }
5385 /* Event Log Base Address Register. */
5386 {
5387 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
5388 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
5389 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5390 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5391 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
5392 if (fVerbose)
5393 {
5394 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5395 EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5396 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5397 cEntries, cbBuffer);
5398 }
5399 }
5400 /* IOMMU Control Register. */
5401 {
5402 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
5403 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
5404 if (fVerbose)
5405 {
5406 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
5407 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
5408 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
5409 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5410 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5411 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
5412 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
5413 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
5414 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
5415 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
5416 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
5417 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
5418 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
5419 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
5420 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
5421 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
5422 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
5423 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
5424 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
5425 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
5426 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
5427 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
5428 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
5429 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
5430 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
5431 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
5432 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
5433 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
5434 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
5435 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
5436 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
5437 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
5438 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
5439 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
5440 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
5441 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
5442 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
5443 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
5444 }
5445 }
5446 /* Exclusion Base Address Register. */
5447 {
5448 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
5449 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
5450 if (fVerbose)
5451 {
5452 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
5453 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
5454 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5455 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
5456 }
5457 }
5458 /* Exclusion Range Limit Register. */
5459 {
5460 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
5461 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
5462 if (fVerbose)
5463 {
5464 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n",
5465 (ExclRangeLimit.n.u40ExclRangeLimit << X86_PAGE_4K_SHIFT) | X86_PAGE_4K_OFFSET_MASK);
5466 }
5467 }
5468 /* Extended Feature Register. */
5469 {
5470 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
5471 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
5472 if (fVerbose)
5473 {
5474 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
5475 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
5476 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
5477 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
5478 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
5479 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
5480 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
5481 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
5482 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
5483 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
5484 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
5485 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
5486 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
5487 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
5488 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
5489 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
5490 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
5491 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
5492 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
5493 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
5494 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
5495 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
5496 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
5497 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
5498 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
5499 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
5500 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
5501 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
5502 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
5503 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
5504 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
5505 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
5506 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
5507 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
5508 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
5509 }
5510 }
5511 /* PPR Log Base Address Register. */
5512 {
5513 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
5514 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
5515 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5516 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5517 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
5518 if (fVerbose)
5519 {
5520 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5521 PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5522 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5523 cEntries, cbBuffer);
5524 }
5525 }
5526 /* Hardware Event (Hi) Register. */
5527 {
5528 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
5529 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
5530 if (fVerbose)
5531 {
5532 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
5533 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
5534 }
5535 }
5536 /* Hardware Event (Lo) Register. */
5537 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
5538 /* Hardware Event Status. */
5539 {
5540 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
5541 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
5542 if (fVerbose)
5543 {
5544 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
5545 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
5546 }
5547 }
5548 /* Guest Virtual-APIC Log Base Address Register. */
5549 {
5550 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
5551 uint8_t const uEncodedLen = GALogBar.n.u4Len;
5552 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5553 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5554 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
5555 if (fVerbose)
5556 {
5557 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5558 GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5559 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5560 cEntries, cbBuffer);
5561 }
5562 }
5563 /* Guest Virtual-APIC Log Tail Address Register. */
5564 {
5565 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
5566 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
5567 if (fVerbose)
5568 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
5569 }
5570 /* PPR Log B Base Address Register. */
5571 {
5572 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
5573 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
5574 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5575 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5576 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
5577 if (fVerbose)
5578 {
5579 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5580 PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5581 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5582 cEntries, cbBuffer);
5583 }
5584 }
5585 /* Event Log B Base Address Register. */
5586 {
5587 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
5588 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
5589 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5590 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5591 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
5592 if (fVerbose)
5593 {
5594 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5595 EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5596 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5597 cEntries, cbBuffer);
5598 }
5599 }
5600 /* Device-Specific Feature Extension Register. */
5601 {
5602 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
5603 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
5604 if (fVerbose)
5605 {
5606 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
5607 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
5608 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
5609 }
5610 }
5611 /* Device-Specific Control Extension Register. */
5612 {
5613 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
5614 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
5615 if (fVerbose)
5616 {
5617 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
5618 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
5619 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
5620 }
5621 }
5622 /* Device-Specific Status Extension Register. */
5623 {
5624 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
5625 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
5626 if (fVerbose)
5627 {
5628 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
5629 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
5630 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
5631 }
5632 }
5633 /* Miscellaneous Information Register (Lo and Hi). */
5634 {
5635 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
5636 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
5637 if (fVerbose)
5638 {
5639 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
5640 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
5641 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
5642 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
5643 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
5644 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
5645 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
5646 }
5647 }
5648 /* MSI Capability Header. */
5649 {
5650 MSI_CAP_HDR_T MsiCapHdr;
5651 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
5652 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
5653 if (fVerbose)
5654 {
5655 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
5656 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
5657 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
5658 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
5659 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
5660 }
5661 }
5662 /* MSI Address Register (Lo and Hi). */
5663 {
5664 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
5665 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
5666 MSIADDR MsiAddr;
5667 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
5668 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
5669 if (fVerbose)
5670 {
5671 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
5672 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
5673 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
5674 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
5675 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
5676 }
5677 }
5678 /* MSI Data. */
5679 {
5680 MSIDATA MsiData;
5681 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
5682 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
5683 if (fVerbose)
5684 {
5685 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
5686 MsiData.n.u8Vector);
5687 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
5688 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
5689 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
5690 "level" : "edge");
5691 }
5692 }
5693 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
5694 {
5695 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
5696 MsiMapCapHdr.u32 = 0;
5697 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
5698 if (fVerbose)
5699 {
5700 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
5701 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
5702 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
5703 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
5704 }
5705 }
5706 /* Performance Optimization Control Register. */
5707 {
5708 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
5709 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
5710 if (fVerbose)
5711 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
5712 }
5713 /* XT (x2APIC) General Interrupt Control Register. */
5714 {
5715 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
5716 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
5717 if (fVerbose)
5718 {
5719 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5720 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5721 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5722 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
5723 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
5724 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5725 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5726 }
5727 }
5728 /* XT (x2APIC) PPR Interrupt Control Register. */
5729 {
5730 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
5731 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
5732 if (fVerbose)
5733 {
5734 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5735 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5736 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5737 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
5738 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
5739 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5740 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5741 }
5742 }
5743 /* XT (X2APIC) GA Log Interrupt Control Register. */
5744 {
5745 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
5746 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
5747 if (fVerbose)
5748 {
5749 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5750 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5751 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5752 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
5753 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
5754 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5755 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5756 }
5757 }
5758 /* MARC Registers. */
5759 {
5760 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
5761 {
5762 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
5763 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
5764 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
5765
5766 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
5767 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
5768 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
5769 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
5770
5771 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
5772 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
5773 }
5774 }
5775 /* Reserved Register. */
5776 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
5777 /* Command Buffer Head Pointer Register. */
5778 {
5779 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
5780 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
5781 CmdBufHeadPtr.n.off);
5782 }
5783 /* Command Buffer Tail Pointer Register. */
5784 {
5785 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
5786 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
5787 CmdBufTailPtr.n.off);
5788 }
5789 /* Event Log Head Pointer Register. */
5790 {
5791 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
5792 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
5793 EvtLogHeadPtr.n.off);
5794 }
5795 /* Event Log Tail Pointer Register. */
5796 {
5797 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
5798 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
5799 EvtLogTailPtr.n.off);
5800 }
5801 /* Status Register. */
5802 {
5803 IOMMU_STATUS_T const Status = pThis->Status;
5804 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
5805 if (fVerbose)
5806 {
5807 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
5808 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
5809 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
5810 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
5811 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
5812 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
5813 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
5814 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
5815 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
5816 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
5817 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
5818 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
5819 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
5820 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
5821 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
5822 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
5823 }
5824 }
5825 /* PPR Log Head Pointer. */
5826 {
5827 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
5828 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
5829 PprLogHeadPtr.n.off);
5830 }
5831 /* PPR Log Tail Pointer. */
5832 {
5833 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
5834 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
5835 PprLogTailPtr.n.off);
5836 }
5837 /* Guest Virtual-APIC Log Head Pointer. */
5838 {
5839 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
5840 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
5841 GALogHeadPtr.n.u12GALogPtr);
5842 }
5843 /* Guest Virtual-APIC Log Tail Pointer. */
5844 {
5845 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
5846 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
5847 GALogTailPtr.n.u12GALogPtr);
5848 }
5849 /* PPR Log B Head Pointer. */
5850 {
5851 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
5852 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
5853 PprLogBHeadPtr.n.off);
5854 }
5855 /* PPR Log B Tail Pointer. */
5856 {
5857 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
5858 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
5859 PprLogBTailPtr.n.off);
5860 }
5861 /* Event Log B Head Pointer. */
5862 {
5863 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
5864 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
5865 EvtLogBHeadPtr.n.off);
5866 }
5867 /* Event Log B Tail Pointer. */
5868 {
5869 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
5870 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
5871 EvtLogBTailPtr.n.off);
5872 }
5873 /* PPR Log Auto Response Register. */
5874 {
5875 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
5876 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
5877 if (fVerbose)
5878 {
5879 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
5880 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
5881 }
5882 }
5883 /* PPR Log Overflow Early Warning Indicator Register. */
5884 {
5885 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
5886 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
5887 if (fVerbose)
5888 {
5889 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
5890 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
5891 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
5892 }
5893 }
5894 /* PPR Log Overflow Early Warning Indicator Register. */
5895 {
5896 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
5897 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
5898 if (fVerbose)
5899 {
5900 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
5901 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
5902 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
5903 }
5904 }
5905}
5906
5907
5908/**
5909 * Dumps the DTE via the info callback helper.
5910 *
5911 * @param pHlp The info helper.
5912 * @param pDte The device table entry.
5913 * @param pszPrefix The string prefix.
5914 */
5915static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
5916{
5917 AssertReturnVoid(pHlp);
5918 AssertReturnVoid(pDte);
5919 AssertReturnVoid(pszPrefix);
5920
5921 pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
5922 pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
5923 pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
5924 pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
5925 pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
5926 pDte->n.u40PageTableRootPtrLo << 12);
5927 pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
5928 pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
5929 pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
5930 pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
5931 pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
5932 pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
5933 pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
5934 (pDte->n.u21GstCr3TableRootPtrHi << 31)
5935 | (pDte->n.u16GstCr3TableRootPtrMid << 15)
5936 | (pDte->n.u3GstCr3TableRootPtrLo << 12));
5937 pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
5938 pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
5939 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
5940 pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
5941 pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
5942 pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
5943 pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
5944 pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
5945 pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
5946 pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
5947 pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
5948 pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
5949 pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
5950 uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
5951 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
5952 {
5953 uint16_t const cEntries = IOMMU_DTE_GET_INTR_TAB_ENTRIES(pDte);
5954 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
5955 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
5956 cbIntrTable);
5957 }
5958 else
5959 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
5960 pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
5961 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
5962 pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
5963 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
5964 pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
5965 pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
5966 pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
5967 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
5968 pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
5969 pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
5970 pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
5971 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
5972 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
5973 pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
5974 pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
5975 pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
5976 pHlp->pfnPrintf(pHlp, "\n");
5977}
5978
5979
5980/**
5981 * @callback_method_impl{FNDBGFHANDLERDEV}
5982 */
5983static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5984{
5985 if (pszArgs)
5986 {
5987 uint16_t idDevice = 0;
5988 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &idDevice);
5989 if (RT_SUCCESS(rc))
5990 {
5991 DTE_T Dte;
5992 rc = iommuAmdDteRead(pDevIns, idDevice, IOMMUOP_TRANSLATE_REQ, &Dte);
5993 if (RT_SUCCESS(rc))
5994 {
5995 pHlp->pfnPrintf(pHlp, "DTE for device %#x\n", idDevice);
5996 iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
5997 return;
5998 }
5999 pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", idDevice, idDevice, rc);
6000 }
6001 else
6002 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
6003 }
6004 else
6005 pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
6006}
6007
6008
6009# ifdef IOMMU_WITH_DTE_CACHE
6010/**
6011 * @callback_method_impl{FNDBGFHANDLERDEV}
6012 */
6013static DECLCALLBACK(void) iommuAmdR3DbgInfoDteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6014{
6015 RT_NOREF(pszArgs);
6016 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6017 IOMMU_CACHE_LOCK(pDevIns, pThis);
6018
6019 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDeviceIds);
6020 pHlp->pfnPrintf(pHlp, "DTE Cache: Capacity=%u entries\n", cDteCache);
6021 for (uint16_t i = 0; i < cDteCache; i++)
6022 {
6023 uint16_t const idDevice = pThis->aDeviceIds[i];
6024 if (idDevice)
6025 {
6026 pHlp->pfnPrintf(pHlp, " Entry[%u]: Device=%#x (BDF %02x:%02x.%d)\n", i, idDevice,
6027 (idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6028 (idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6029 idDevice & VBOX_PCI_DEVFN_FUN_MASK);
6030
6031 PCDTECACHE pDteCache = &pThis->aDteCache[i];
6032 pHlp->pfnPrintf(pHlp, " Flags = %#x\n", pDteCache->fFlags);
6033 pHlp->pfnPrintf(pHlp, " Domain Id = %u\n", pDteCache->idDomain);
6034 pHlp->pfnPrintf(pHlp, "\n");
6035 }
6036 }
6037 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
6038}
6039# endif /* IOMMU_WITH_DTE_CACHE */
6040
6041
6042# ifdef IOMMU_WITH_IOTLBE_CACHE
6043/**
6044 * @callback_method_impl{FNDBGFHANDLERDEV}
6045 */
6046static DECLCALLBACK(void) iommuAmdR3DbgInfoIotlb(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6047{
6048 if (pszArgs)
6049 {
6050 uint16_t idDomain = 0;
6051 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &idDomain);
6052 if (RT_SUCCESS(rc))
6053 {
6054 pHlp->pfnPrintf(pHlp, "IOTLBEs for domain %u (%#x):\n", idDomain, idDomain);
6055 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6056 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6057 IOTLBEINFOARG Args;
6058 Args.pIommuR3 = pThisR3;
6059 Args.pHlp = pHlp;
6060 Args.idDomain = idDomain;
6061
6062 IOMMU_CACHE_LOCK(pDevIns, pThis);
6063 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdR3IotlbEntryInfo, &Args);
6064 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
6065 }
6066 else
6067 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit domain ID. rc=%Rrc\n", rc);
6068 }
6069 else
6070 pHlp->pfnPrintf(pHlp, "Missing domain ID.\n");
6071}
6072# endif /* IOMMU_WITH_IOTLBE_CACHE */
6073
6074
6075# ifdef IOMMU_WITH_IRTE_CACHE
6076/**
6077 * Gets the interrupt type name for an interrupt type in the IRTE.
6078 *
6079 * @returns The interrupt type name.
6080 * @param uIntrType The interrupt type (as specified in the IRTE).
6081 */
6082static const char *iommuAmdIrteGetIntrTypeName(uint8_t uIntrType)
6083{
6084 switch (uIntrType)
6085 {
6086 case VBOX_MSI_DELIVERY_MODE_FIXED: return "Fixed";
6087 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO: return "Arbitrated";
6088 default: return "<Reserved>";
6089 }
6090}
6091
6092
6093/**
6094 * @callback_method_impl{FNDBGFHANDLERDEV}
6095 */
6096static DECLCALLBACK(void) iommuAmdR3DbgInfoIrteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6097{
6098 RT_NOREF(pszArgs);
6099
6100 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6101 IOMMU_CACHE_LOCK(pDevIns, pThis);
6102
6103 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
6104 pHlp->pfnPrintf(pHlp, "IRTE Cache: Capacity=%u entries\n", cIrteCache);
6105 for (uint16_t idxIrte = 0; idxIrte < cIrteCache; idxIrte++)
6106 {
6107 PCIRTECACHE pIrteCache = &pThis->aIrteCache[idxIrte];
6108 uint32_t const uKey = pIrteCache->uKey;
6109 if (uKey != IOMMU_IRTE_CACHE_KEY_NIL)
6110 {
6111 uint16_t const idDevice = IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(uKey);
6112 uint16_t const offIrte = IOMMU_IRTE_CACHE_KEY_GET_OFF(uKey);
6113 pHlp->pfnPrintf(pHlp, " Entry[%u]: Offset=%#x Device=%#x (BDF %02x:%02x.%d)\n",
6114 idxIrte, offIrte, idDevice,
6115 (idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6116 (idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6117 idDevice & VBOX_PCI_DEVFN_FUN_MASK);
6118
6119 PCIRTE_T pIrte = &pIrteCache->Irte;
6120 pHlp->pfnPrintf(pHlp, " Remap Enable = %RTbool\n", pIrte->n.u1RemapEnable);
6121 pHlp->pfnPrintf(pHlp, " Suppress IOPF = %RTbool\n", pIrte->n.u1SuppressIoPf);
6122 pHlp->pfnPrintf(pHlp, " Interrupt Type = %#x (%s)\n", pIrte->n.u3IntrType,
6123 iommuAmdIrteGetIntrTypeName(pIrte->n.u3IntrType));
6124 pHlp->pfnPrintf(pHlp, " Request EOI = %RTbool\n", pIrte->n.u1ReqEoi);
6125 pHlp->pfnPrintf(pHlp, " Destination mode = %s\n", pIrte->n.u1DestMode ? "Logical" : "Physical");
6126 pHlp->pfnPrintf(pHlp, " Destination Id = %u\n", pIrte->n.u8Dest);
6127 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", pIrte->n.u8Vector, pIrte->n.u8Vector);
6128 pHlp->pfnPrintf(pHlp, "\n");
6129 }
6130 }
6131 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
6132}
6133# endif /* IOMMU_WITH_IRTE_CACHE */
6134
6135
6136/**
6137 * @callback_method_impl{FNDBGFHANDLERDEV}
6138 */
6139static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6140{
6141 RT_NOREF(pszArgs);
6142
6143 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6144 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6145 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6146 NOREF(pPciDev);
6147
6148 uint8_t cSegments = 0;
6149 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6150 {
6151 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6152 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6153 if (GCPhysDevTab)
6154 ++cSegments;
6155 }
6156
6157 pHlp->pfnPrintf(pHlp, "AMD-IOMMU device tables with address translations enabled:\n");
6158 pHlp->pfnPrintf(pHlp, " DTE Segments=%u\n", cSegments);
6159 if (!cSegments)
6160 return;
6161
6162 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6163 {
6164 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6165 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6166 if (GCPhysDevTab)
6167 {
6168 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
6169 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
6170
6171 void *pvDevTab = RTMemAllocZ(cbDevTab);
6172 if (RT_LIKELY(pvDevTab))
6173 {
6174 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
6175 if (RT_SUCCESS(rc))
6176 {
6177 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
6178 {
6179 PCDTE_T pDte = (PCDTE_T)((uintptr_t)pvDevTab + idxDte * sizeof(DTE_T));
6180 if ( pDte->n.u1Valid
6181 && pDte->n.u1TranslationValid
6182 && pDte->n.u3Mode != 0)
6183 {
6184 pHlp->pfnPrintf(pHlp, " DTE %u (BDF %02x:%02x.%d)\n", idxDte,
6185 (idxDte >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6186 (idxDte >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6187 idxDte & VBOX_PCI_DEVFN_FUN_MASK);
6188 iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
6189 pHlp->pfnPrintf(pHlp, "\n");
6190 }
6191 }
6192 pHlp->pfnPrintf(pHlp, "\n");
6193 }
6194 else
6195 {
6196 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %zu bytes. rc=%Rrc!\n", GCPhysDevTab,
6197 cbDevTab, rc);
6198 }
6199
6200 RTMemFree(pvDevTab);
6201 }
6202 else
6203 {
6204 pHlp->pfnPrintf(pHlp, " Allocating %zu bytes for reading the device table failed!\n", cbDevTab);
6205 return;
6206 }
6207 }
6208 }
6209}
6210
6211
6212/**
6213 * @callback_method_impl{FNSSMDEVSAVEEXEC}
6214 */
6215static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6216{
6217 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6218 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6219 LogFlowFunc(("\n"));
6220
6221 /* First, save ExtFeat and other registers that cannot be modified by the guest. */
6222 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64);
6223 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64);
6224 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64);
6225 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64);
6226 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64);
6227 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg);
6228
6229 /* Next, save all registers that can be modified by the guest. */
6230 pHlp->pfnSSMPutU64(pSSM, pThis->IommuBar.u64);
6231
6232 uint8_t const cDevTabBaseAddrs = RT_ELEMENTS(pThis->aDevTabBaseAddrs);
6233 pHlp->pfnSSMPutU8(pSSM, cDevTabBaseAddrs);
6234 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6235 pHlp->pfnSSMPutU64(pSSM, pThis->aDevTabBaseAddrs[i].u64);
6236
6237 AssertReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8, VERR_IOMMU_IPE_4);
6238 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufBaseAddr.u64);
6239 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBaseAddr.u64);
6240 pHlp->pfnSSMPutU64(pSSM, pThis->Ctrl.u64);
6241 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeBaseAddr.u64);
6242 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeLimit.u64);
6243#if 0
6244 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64); /* read-only, done already (above). */
6245#endif
6246
6247 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBaseAddr.u64);
6248 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtHi.u64);
6249 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtLo);
6250 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtStatus.u64);
6251
6252 pHlp->pfnSSMPutU64(pSSM, pThis->GALogBaseAddr.u64);
6253 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailAddr.u64);
6254
6255 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBBaseAddr.u64);
6256 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBBaseAddr.u64);
6257
6258#if 0
6259 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6260 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6261 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6262
6263 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64); /* read-only, done already (above). */
6264#endif
6265 pHlp->pfnSSMPutU32(pSSM, pThis->PerfOptCtrl.u32);
6266
6267 pHlp->pfnSSMPutU64(pSSM, pThis->XtGenIntrCtrl.u64);
6268 pHlp->pfnSSMPutU64(pSSM, pThis->XtPprIntrCtrl.u64);
6269 pHlp->pfnSSMPutU64(pSSM, pThis->XtGALogIntrCtrl.u64);
6270
6271 size_t const cMarcApers = RT_ELEMENTS(pThis->aMarcApers);
6272 pHlp->pfnSSMPutU8(pSSM, cMarcApers);
6273 for (size_t i = 0; i < cMarcApers; i++)
6274 {
6275 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Base.u64);
6276 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Reloc.u64);
6277 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Length.u64);
6278 }
6279
6280#if 0
6281 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg); /* read-only, done already (above). */
6282#endif
6283
6284 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufHeadPtr.u64);
6285 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufTailPtr.u64);
6286 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogHeadPtr.u64);
6287 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogTailPtr.u64);
6288
6289 pHlp->pfnSSMPutU64(pSSM, pThis->Status.u64);
6290
6291 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogHeadPtr.u64);
6292 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogTailPtr.u64);
6293
6294 pHlp->pfnSSMPutU64(pSSM, pThis->GALogHeadPtr.u64);
6295 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailPtr.u64);
6296
6297 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBHeadPtr.u64);
6298 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBTailPtr.u64);
6299
6300 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBHeadPtr.u64);
6301 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBTailPtr.u64);
6302
6303 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogAutoResp.u64);
6304 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogOverflowEarly.u64);
6305 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBOverflowEarly.u64);
6306
6307 return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
6308}
6309
6310
6311/**
6312 * @callback_method_impl{FNSSMDEVLOADEXEC}
6313 */
6314static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6315{
6316 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6317 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6318 int const rcErr = VERR_SSM_UNEXPECTED_DATA;
6319 LogFlowFunc(("\n"));
6320
6321 /* Validate. */
6322 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
6323 if (uVersion != IOMMU_SAVED_STATE_VERSION)
6324 {
6325 LogRel(("%s: Invalid saved-state version %#x\n", IOMMU_LOG_PFX, uVersion));
6326 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
6327 }
6328
6329 /* Load ExtFeat and other read-only registers first. */
6330 int rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64);
6331 AssertRCReturn(rc, rc);
6332 AssertLogRelMsgReturn(pThis->ExtFeat.n.u2HostAddrTranslateSize < 0x3,
6333 ("ExtFeat.HATS register invalid %#RX64\n", pThis->ExtFeat.u64), rcErr);
6334 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64);
6335 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64);
6336 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64);
6337 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64);
6338 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg);
6339
6340 /* IOMMU base address register. */
6341 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->IommuBar.u64);
6342 AssertRCReturn(rc, rc);
6343 pThis->IommuBar.u64 &= IOMMU_BAR_VALID_MASK;
6344
6345 /* Device table base address registers. */
6346 uint8_t cDevTabBaseAddrs;
6347 rc = pHlp->pfnSSMGetU8(pSSM, &cDevTabBaseAddrs);
6348 AssertRCReturn(rc, rc);
6349 AssertLogRelMsgReturn(cDevTabBaseAddrs > 0 && cDevTabBaseAddrs <= RT_ELEMENTS(pThis->aDevTabBaseAddrs),
6350 ("Device table segment count invalid %#x\n", cDevTabBaseAddrs), rcErr);
6351 AssertCompile(RT_ELEMENTS(pThis->aDevTabBaseAddrs) == RT_ELEMENTS(g_auDevTabSegMaxSizes));
6352 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6353 {
6354 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aDevTabBaseAddrs[i].u64);
6355 AssertRCReturn(rc, rc);
6356 pThis->aDevTabBaseAddrs[i].u64 &= IOMMU_DEV_TAB_BAR_VALID_MASK;
6357 uint16_t const uSegSize = pThis->aDevTabBaseAddrs[i].n.u9Size;
6358 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[i];
6359 AssertLogRelMsgReturn(uSegSize <= uMaxSegSize,
6360 ("Device table [%u] segment size invalid %u (max %u)\n", i, uSegSize, uMaxSegSize), rcErr);
6361 }
6362
6363 /* Command buffer base address register. */
6364 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufBaseAddr.u64);
6365 AssertRCReturn(rc, rc);
6366 pThis->CmdBufBaseAddr.u64 &= IOMMU_CMD_BUF_BAR_VALID_MASK;
6367 AssertLogRelMsgReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8,
6368 ("Command buffer base address invalid %#RX64\n", pThis->CmdBufBaseAddr.u64), rcErr);
6369
6370 /* Event log base address register. */
6371 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBaseAddr.u64);
6372 AssertRCReturn(rc, rc);
6373 pThis->EvtLogBaseAddr.u64 &= IOMMU_EVT_LOG_BAR_VALID_MASK;
6374 AssertLogRelMsgReturn(pThis->EvtLogBaseAddr.n.u4Len >= 8,
6375 ("Event log base address invalid %#RX64\n", pThis->EvtLogBaseAddr.u64), rcErr);
6376
6377 /* Control register. */
6378 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Ctrl.u64);
6379 AssertRCReturn(rc, rc);
6380 pThis->Ctrl.u64 &= IOMMU_CTRL_VALID_MASK;
6381 AssertLogRelMsgReturn(pThis->Ctrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup,
6382 ("Control register invalid %#RX64\n", pThis->Ctrl.u64), rcErr);
6383
6384 /* Exclusion range base address register. */
6385 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeBaseAddr.u64);
6386 AssertRCReturn(rc, rc);
6387 pThis->ExclRangeBaseAddr.u64 &= IOMMU_EXCL_RANGE_BAR_VALID_MASK;
6388
6389 /* Exclusion range limit register. */
6390 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeLimit.u64);
6391 AssertRCReturn(rc, rc);
6392 pThis->ExclRangeLimit.u64 &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
6393 pThis->ExclRangeLimit.u64 |= UINT64_C(0xfff);
6394
6395#if 0
6396 pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64); /* read-only, done already (above). */
6397#endif
6398
6399 /* PPR log base address register. */
6400 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBaseAddr.u64);
6401 AssertRCReturn(rc, rc);
6402 Assert(!pThis->ExtFeat.n.u1PprSup);
6403
6404 /* Hardware event (Hi) register. */
6405 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtHi.u64);
6406 AssertRCReturn(rc, rc);
6407
6408 /* Hardware event (Lo) register. */
6409 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtLo);
6410 AssertRCReturn(rc, rc);
6411
6412 /* Hardware event status register. */
6413 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtStatus.u64);
6414 AssertRCReturn(rc, rc);
6415 pThis->HwEvtStatus.u64 &= IOMMU_HW_EVT_STATUS_VALID_MASK;
6416
6417 /* Guest Virtual-APIC log base address register. */
6418 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogBaseAddr.u64);
6419 AssertRCReturn(rc, rc);
6420 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6421
6422 /* Guest Virtual-APIC log tail address register. */
6423 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailAddr.u64);
6424 AssertRCReturn(rc, rc);
6425 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6426
6427 /* PPR log-B base address register. */
6428 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBBaseAddr.u64);
6429 AssertRCReturn(rc, rc);
6430 Assert(!pThis->ExtFeat.n.u1PprSup);
6431
6432 /* Event log-B base address register. */
6433 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBBaseAddr.u64);
6434 AssertRCReturn(rc, rc);
6435 Assert(!pThis->ExtFeat.n.u2DualPprLogSup);
6436
6437#if 0
6438 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6439 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6440 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6441
6442 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64); /* read-only, done already (above). */
6443#endif
6444
6445 /* Performance optimization control register. */
6446 rc = pHlp->pfnSSMGetU32(pSSM, &pThis->PerfOptCtrl.u32);
6447 AssertRCReturn(rc, rc);
6448 Assert(!pThis->ExtFeat.n.u1PerfOptSup);
6449
6450 /* x2APIC registers. */
6451 {
6452 Assert(!pThis->ExtFeat.n.u1X2ApicSup);
6453
6454 /* x2APIC general interrupt control register. */
6455 pHlp->pfnSSMGetU64(pSSM, &pThis->XtGenIntrCtrl.u64);
6456 AssertRCReturn(rc, rc);
6457
6458 /* x2APIC PPR interrupt control register. */
6459 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtPprIntrCtrl.u64);
6460 AssertRCReturn(rc, rc);
6461
6462 /* x2APIC GA log interrupt control register. */
6463 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtGALogIntrCtrl.u64);
6464 AssertRCReturn(rc, rc);
6465 }
6466
6467 /* MARC (Memory Access and Routing) registers. */
6468 {
6469 uint8_t cMarcApers;
6470 rc = pHlp->pfnSSMGetU8(pSSM, &cMarcApers);
6471 AssertRCReturn(rc, rc);
6472 AssertLogRelMsgReturn(cMarcApers > 0 && cMarcApers <= RT_ELEMENTS(pThis->aMarcApers),
6473 ("MARC register count invalid %#x\n", cMarcApers), rcErr);
6474 for (uint8_t i = 0; i < cMarcApers; i++)
6475 {
6476 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Base.u64);
6477 AssertRCReturn(rc, rc);
6478
6479 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Reloc.u64);
6480 AssertRCReturn(rc, rc);
6481
6482 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Length.u64);
6483 AssertRCReturn(rc, rc);
6484 }
6485 Assert(!pThis->ExtFeat.n.u2MarcSup);
6486 }
6487
6488#if 0
6489 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg); /* read-only, done already (above). */
6490#endif
6491
6492 /* Command buffer head pointer register. */
6493 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufHeadPtr.u64);
6494 AssertRCReturn(rc, rc);
6495 {
6496 /*
6497 * IOMMU behavior is undefined when software writes a value outside the buffer length.
6498 * In our emulation, since we ignore the write entirely (see iommuAmdCmdBufHeadPtr_w)
6499 * we shouldn't see such values in the saved state.
6500 */
6501 uint32_t const offBuf = pThis->CmdBufHeadPtr.u64 & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
6502 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6503 Assert(cbBuf <= _512K);
6504 AssertLogRelMsgReturn(offBuf < cbBuf,
6505 ("Command buffer head pointer invalid %#x\n", pThis->CmdBufHeadPtr.u64), rcErr);
6506 }
6507
6508 /* Command buffer tail pointer register. */
6509 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufTailPtr.u64);
6510 AssertRCReturn(rc, rc);
6511 {
6512 uint32_t const offBuf = pThis->CmdBufTailPtr.u64 & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
6513 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6514 Assert(cbBuf <= _512K);
6515 AssertLogRelMsgReturn(offBuf < cbBuf,
6516 ("Command buffer tail pointer invalid %#x\n", pThis->CmdBufTailPtr.u64), rcErr);
6517 }
6518
6519 /* Event log head pointer register. */
6520 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogHeadPtr.u64);
6521 AssertRCReturn(rc, rc);
6522 {
6523 uint32_t const offBuf = pThis->EvtLogHeadPtr.u64 & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
6524 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6525 Assert(cbBuf <= _512K);
6526 AssertLogRelMsgReturn(offBuf < cbBuf,
6527 ("Event log head pointer invalid %#x\n", pThis->EvtLogHeadPtr.u64), rcErr);
6528 }
6529
6530 /* Event log tail pointer register. */
6531 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogTailPtr.u64);
6532 AssertRCReturn(rc, rc);
6533 {
6534 uint32_t const offBuf = pThis->EvtLogTailPtr.u64 & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
6535 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6536 Assert(cbBuf <= _512K);
6537 AssertLogRelMsgReturn(offBuf < cbBuf,
6538 ("Event log tail pointer invalid %#x\n", pThis->EvtLogTailPtr.u64), rcErr);
6539 }
6540
6541 /* Status register. */
6542 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Status.u64);
6543 AssertRCReturn(rc, rc);
6544 pThis->Status.u64 &= IOMMU_STATUS_VALID_MASK;
6545
6546 /* PPR log head pointer register. */
6547 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogHeadPtr.u64);
6548 AssertRCReturn(rc, rc);
6549 Assert(!pThis->ExtFeat.n.u1PprSup);
6550
6551 /* PPR log tail pointer register. */
6552 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogTailPtr.u64);
6553 AssertRCReturn(rc, rc);
6554 Assert(!pThis->ExtFeat.n.u1PprSup);
6555
6556 /* Guest Virtual-APIC log head pointer register. */
6557 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogHeadPtr.u64);
6558 AssertRCReturn(rc, rc);
6559 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6560
6561 /* Guest Virtual-APIC log tail pointer register. */
6562 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailPtr.u64);
6563 AssertRCReturn(rc, rc);
6564 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6565
6566 /* PPR log-B head pointer register. */
6567 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBHeadPtr.u64);
6568 AssertRCReturn(rc, rc);
6569 Assert(!pThis->ExtFeat.n.u1PprSup);
6570
6571 /* PPR log-B head pointer register. */
6572 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBTailPtr.u64);
6573 AssertRCReturn(rc, rc);
6574 Assert(!pThis->ExtFeat.n.u1PprSup);
6575
6576 /* Event log-B head pointer register. */
6577 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBHeadPtr.u64);
6578 AssertRCReturn(rc, rc);
6579 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6580
6581 /* Event log-B tail pointer register. */
6582 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBTailPtr.u64);
6583 AssertRCReturn(rc, rc);
6584 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6585
6586 /* PPR log auto response register. */
6587 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogAutoResp.u64);
6588 AssertRCReturn(rc, rc);
6589 Assert(!pThis->ExtFeat.n.u1PprAutoRespSup);
6590
6591 /* PPR log overflow early indicator register. */
6592 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogOverflowEarly.u64);
6593 AssertRCReturn(rc, rc);
6594 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6595
6596 /* PPR log-B overflow early indicator register. */
6597 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBOverflowEarly.u64);
6598 AssertRCReturn(rc, rc);
6599 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6600
6601 /* End marker. */
6602 {
6603 uint32_t uEndMarker;
6604 rc = pHlp->pfnSSMGetU32(pSSM, &uEndMarker);
6605 AssertLogRelMsgRCReturn(rc, ("Failed to read end marker. rc=%Rrc\n", rc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6606 AssertLogRelMsgReturn(uEndMarker == UINT32_MAX, ("End marker invalid (%#x expected %#x)\n", uEndMarker, UINT32_MAX),
6607 rcErr);
6608 }
6609
6610 return rc;
6611}
6612
6613
6614/**
6615 * @callback_method_impl{FNSSMDEVLOADDONE}
6616 */
6617static DECLCALLBACK(int) iommuAmdR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6618{
6619 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6620 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6621 RT_NOREF(pSSM);
6622 LogFlowFunc(("\n"));
6623
6624 /* Sanity. */
6625 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
6626 AssertPtrReturn(pThisR3, VERR_INVALID_POINTER);
6627
6628 int rc;
6629 IOMMU_LOCK(pDevIns, pThisR3);
6630
6631 /* Map MMIO regions if the IOMMU BAR is enabled. */
6632 if (pThis->IommuBar.n.u1Enable)
6633 rc = iommuAmdR3MmioSetup(pDevIns);
6634 else
6635 rc = VINF_SUCCESS;
6636
6637 /* Wake up the command thread if commands need processing. */
6638 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
6639
6640 IOMMU_UNLOCK(pDevIns, pThisR3);
6641
6642 LogRel(("%s: Restored: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
6643 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
6644 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
6645 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
6646 pThis->ExtFeat.u64));
6647 return rc;
6648}
6649
6650
6651/**
6652 * @interface_method_impl{PDMDEVREG,pfnReset}
6653 */
6654static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
6655{
6656 /*
6657 * Resets read-write portion of the IOMMU state.
6658 *
6659 * NOTE! State not initialized here is expected to be initialized during
6660 * device construction and remain read-only through the lifetime of the VM.
6661 */
6662 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6663 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6664 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6665 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6666 LogFlowFunc(("\n"));
6667
6668 IOMMU_LOCK(pDevIns, pThisR3);
6669
6670 RT_ZERO(pThis->aDevTabBaseAddrs);
6671
6672 pThis->CmdBufBaseAddr.u64 = 0;
6673 pThis->CmdBufBaseAddr.n.u4Len = 8;
6674
6675 pThis->EvtLogBaseAddr.u64 = 0;
6676 pThis->EvtLogBaseAddr.n.u4Len = 8;
6677
6678 pThis->Ctrl.u64 = 0;
6679 pThis->Ctrl.n.u1Coherent = 1;
6680 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
6681
6682 pThis->ExclRangeBaseAddr.u64 = 0;
6683 pThis->ExclRangeLimit.u64 = 0;
6684
6685 pThis->PprLogBaseAddr.u64 = 0;
6686 pThis->PprLogBaseAddr.n.u4Len = 8;
6687
6688 pThis->HwEvtHi.u64 = 0;
6689 pThis->HwEvtLo = 0;
6690 pThis->HwEvtStatus.u64 = 0;
6691
6692 pThis->GALogBaseAddr.u64 = 0;
6693 pThis->GALogBaseAddr.n.u4Len = 8;
6694 pThis->GALogTailAddr.u64 = 0;
6695
6696 pThis->PprLogBBaseAddr.u64 = 0;
6697 pThis->PprLogBBaseAddr.n.u4Len = 8;
6698
6699 pThis->EvtLogBBaseAddr.u64 = 0;
6700 pThis->EvtLogBBaseAddr.n.u4Len = 8;
6701
6702 pThis->PerfOptCtrl.u32 = 0;
6703
6704 pThis->XtGenIntrCtrl.u64 = 0;
6705 pThis->XtPprIntrCtrl.u64 = 0;
6706 pThis->XtGALogIntrCtrl.u64 = 0;
6707
6708 RT_ZERO(pThis->aMarcApers);
6709
6710 pThis->CmdBufHeadPtr.u64 = 0;
6711 pThis->CmdBufTailPtr.u64 = 0;
6712 pThis->EvtLogHeadPtr.u64 = 0;
6713 pThis->EvtLogTailPtr.u64 = 0;
6714
6715 pThis->Status.u64 = 0;
6716
6717 pThis->PprLogHeadPtr.u64 = 0;
6718 pThis->PprLogTailPtr.u64 = 0;
6719
6720 pThis->GALogHeadPtr.u64 = 0;
6721 pThis->GALogTailPtr.u64 = 0;
6722
6723 pThis->PprLogBHeadPtr.u64 = 0;
6724 pThis->PprLogBTailPtr.u64 = 0;
6725
6726 pThis->EvtLogBHeadPtr.u64 = 0;
6727 pThis->EvtLogBTailPtr.u64 = 0;
6728
6729 pThis->PprLogAutoResp.u64 = 0;
6730 pThis->PprLogOverflowEarly.u64 = 0;
6731 pThis->PprLogBOverflowEarly.u64 = 0;
6732
6733 pThis->IommuBar.u64 = 0;
6734 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
6735 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
6736
6737 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
6738
6739 IOMMU_UNLOCK(pDevIns, pThisR3);
6740
6741#ifdef IOMMU_WITH_DTE_CACHE
6742 iommuAmdDteCacheRemoveAll(pDevIns);
6743#endif
6744#ifdef IOMMU_WITH_IOTLBE_CACHE
6745 iommuAmdIotlbRemoveAll(pDevIns);
6746#endif
6747#ifdef IOMMU_WITH_IRTE_CACHE
6748 iommuAmdIrteCacheRemoveAll(pDevIns);
6749#endif
6750}
6751
6752
6753/**
6754 * @interface_method_impl{PDMDEVREG,pfnDestruct}
6755 */
6756static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
6757{
6758 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
6759 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6760 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6761 LogFlowFunc(("\n"));
6762
6763 IOMMU_LOCK(pDevIns, pThisR3);
6764
6765 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
6766 {
6767 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
6768 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
6769 }
6770
6771#ifdef IOMMU_WITH_IOTLBE_CACHE
6772 if (pThisR3->paIotlbes)
6773 {
6774 PDMDevHlpMMHeapFree(pDevIns, pThisR3->paIotlbes);
6775 pThisR3->paIotlbes = NULL;
6776 pThisR3->idxUnusedIotlbe = 0;
6777 }
6778#endif
6779
6780 IOMMU_UNLOCK(pDevIns, pThisR3);
6781 return VINF_SUCCESS;
6782}
6783
6784
6785/**
6786 * @interface_method_impl{PDMDEVREG,pfnConstruct}
6787 */
6788static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
6789{
6790 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6791 RT_NOREF(pCfg);
6792
6793 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6794 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6795 pThis->u32Magic = IOMMU_MAGIC;
6796 pThisR3->pDevInsR3 = pDevIns;
6797
6798 LogFlowFunc(("iInstance=%d\n", iInstance));
6799
6800 /*
6801 * Register the IOMMU with PDM.
6802 */
6803 PDMIOMMUREGR3 IommuReg;
6804 RT_ZERO(IommuReg);
6805 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
6806 IommuReg.pfnMemAccess = iommuAmdMemAccess;
6807 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
6808 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
6809 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
6810 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
6811 if (RT_FAILURE(rc))
6812 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
6813 if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
6814 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6815 N_("IOMMU helper version mismatch; got %#x expected %#x"),
6816 pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
6817 if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
6818 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6819 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
6820 pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
6821 AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
6822 AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
6823 AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
6824 AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
6825
6826 /*
6827 * We will use PDM's critical section (via helpers) for the IOMMU device.
6828 */
6829 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
6830 AssertRCReturn(rc, rc);
6831
6832 /*
6833 * Initialize read-only PCI configuration space.
6834 */
6835 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6836 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6837
6838 /* Header. */
6839 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
6840 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
6841 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
6842 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
6843 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
6844 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
6845 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
6846 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
6847 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
6848 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
6849 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
6850 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
6851 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
6852 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
6853
6854 /* Capability Header. */
6855 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
6856 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
6857 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
6858 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Next capability offset */
6859 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
6860 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
6861 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
6862 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
6863 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
6864 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
6865 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
6866
6867 /* Base Address Register. */
6868 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
6869 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
6870
6871 /* IOMMU Range Register. */
6872 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
6873
6874 /* Misc. Information Register. */
6875 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
6876 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
6877 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
6878 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
6879 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
6880 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
6881 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
6882 uint32_t const uMiscInfoReg1 = 0;
6883 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
6884 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
6885
6886 /* MSI Capability Header register. */
6887 PDMMSIREG MsiReg;
6888 RT_ZERO(MsiReg);
6889 MsiReg.cMsiVectors = 1;
6890 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
6891 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
6892 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support". */
6893
6894 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
6895#if 0
6896 /* MSI Address Lo. */
6897 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
6898 /* MSI Address Hi. */
6899 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
6900 /* MSI Data. */
6901 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
6902#endif
6903
6904#if 0
6905 /** @todo IOMMU: I don't know if we need to support this, enable later if
6906 * required. */
6907 /* MSI Mapping Capability Header register. */
6908 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
6909 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
6910 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
6911 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
6912 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
6913 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
6914 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
6915#endif
6916
6917 /*
6918 * Register the PCI function with PDM.
6919 */
6920 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
6921 AssertLogRelRCReturn(rc, rc);
6922
6923 /*
6924 * Register MSI support for the PCI device.
6925 * This must be done -after- registering it as a PCI device!
6926 */
6927 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
6928 AssertRCReturn(rc, rc);
6929
6930 /*
6931 * Intercept PCI config. space accesses.
6932 */
6933 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
6934 AssertLogRelRCReturn(rc, rc);
6935
6936 /*
6937 * Create the MMIO region.
6938 * Mapping of the region is done when software configures it via PCI config space.
6939 */
6940 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
6941 NULL /* pvUser */,
6942 IOMMMIO_FLAGS_READ_DWORD_QWORD
6943 | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING
6944 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
6945 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
6946 "AMD-IOMMU", &pThis->hMmio);
6947 AssertLogRelRCReturn(rc, rc);
6948
6949 /*
6950 * Register saved state handlers.
6951 */
6952 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL /* pszBefore */,
6953 NULL /* pfnLivePrep */, NULL /* pfnLiveExec */, NULL /* pfnLiveVote */,
6954 NULL /* pfnSavePrep */, iommuAmdR3SaveExec, NULL /* pfnSaveDone */,
6955 NULL /* pfnLoadPrep */, iommuAmdR3LoadExec, iommuAmdR3LoadDone);
6956 AssertLogRelRCReturn(rc, rc);
6957
6958 /*
6959 * Register debugger info items.
6960 */
6961 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
6962 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device (from memory). Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
6963 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display I/O device tables with translation enabled.", iommuAmdR3DbgInfoDevTabs);
6964#ifdef IOMMU_WITH_IOTLBE_CACHE
6965 PDMDevHlpDBGFInfoRegister(pDevIns, "iommutlb", "Display IOTLBs for a domain. Arguments: DomainID.", iommuAmdR3DbgInfoIotlb);
6966#endif
6967#ifdef IOMMU_WITH_DTE_CACHE
6968 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudtecache", "Display the DTE cache.", iommuAmdR3DbgInfoDteCache);
6969#endif
6970#ifdef IOMMU_WITH_IRTE_CACHE
6971 PDMDevHlpDBGFInfoRegister(pDevIns, "iommuirtecache", "Display the IRTE cache.", iommuAmdR3DbgInfoIrteCache);
6972#endif
6973
6974# ifdef VBOX_WITH_STATISTICS
6975 /*
6976 * Statistics.
6977 */
6978 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
6979 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
6980
6981 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
6982 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
6983
6984 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
6985 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
6986
6987 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
6988 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
6989
6990 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
6991 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
6992
6993 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
6994 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
6995
6996 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
6997 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
6998
6999 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
7000 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
7001 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
7002 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
7003 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
7004 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
7005 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
7006 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
7007 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
7008
7009
7010 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeCached, STAMTYPE_COUNTER, "IOTLB/Cached", STAMUNIT_OCCURENCES, "Number of IOTLB entries in the cache.");
7011 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeLazyEvictReuse, STAMTYPE_COUNTER, "IOTLB/LazyEvictReuse", STAMUNIT_OCCURENCES, "Number of IOTLB entries reused after lazy eviction.");
7012
7013 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfDteLookup, STAMTYPE_PROFILE, "Profile/DteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling DTE lookup.");
7014 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIotlbeLookup, STAMTYPE_PROFILE, "Profile/IotlbeLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IOTLBE lookup.");
7015
7016 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteLookup, STAMTYPE_PROFILE, "Profile/IrteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE lookup.");
7017 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteCacheLookup, STAMTYPE_PROFILE, "Profile/IrteCacheLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE cache lookup.");
7018
7019 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHit, STAMTYPE_COUNTER, "MemAccess/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
7020 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheMiss, STAMTYPE_COUNTER, "MemAccess/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
7021 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHitFull, STAMTYPE_COUNTER, "MemAccess/CacheHitFull", STAMUNIT_OCCURENCES, "Number of accesses that was entirely in the cache.");
7022 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheNonContig, STAMTYPE_COUNTER, "MemAccess/CacheNonContig", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in non-contiguous translated regions.");
7023 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCachePermDenied, STAMTYPE_COUNTER, "MemAccess/CacheAddrDenied", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in denied permissions.");
7024 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDteNonContig, STAMTYPE_COUNTER, "MemAccess/DteNonContig", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in non-contiguous translated regions.");
7025 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDtePermDenied, STAMTYPE_COUNTER, "MemAccess/DtePermDenied", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in denied permissions.");
7026
7027 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheHit, STAMTYPE_COUNTER, "Interrupt/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
7028 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheMiss, STAMTYPE_COUNTER, "Interrupt/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
7029# endif
7030
7031 /*
7032 * Create the command thread and its event semaphore.
7033 */
7034 char szDevIommu[64];
7035 RT_ZERO(szDevIommu);
7036 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
7037 rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
7038 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
7039 AssertLogRelRCReturn(rc, rc);
7040
7041 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
7042 AssertLogRelRCReturn(rc, rc);
7043
7044#ifdef IOMMU_WITH_DTE_CACHE
7045 /*
7046 * Initialize the critsect of the cache.
7047 */
7048 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSectCache, RT_SRC_POS, "IOMMUCache-#%u", pDevIns->iInstance);
7049 AssertLogRelRCReturn(rc, rc);
7050
7051 /* Several places in this code relies on this basic assumption - assert it! */
7052 AssertCompile(RT_ELEMENTS(pThis->aDeviceIds) == RT_ELEMENTS(pThis->aDteCache));
7053#endif
7054
7055#ifdef IOMMU_WITH_IOTLBE_CACHE
7056 /*
7057 * Allocate IOTLB entries.
7058 * This is allocated upfront since we expect a relatively small number of entries,
7059 * is more cache-line efficient and easier to track least recently used entries for
7060 * eviction when the cache is full. This also avoids unpredictable behavior during
7061 * the lifetime of the VM if the hyperheap gets full.
7062 */
7063 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
7064 pThisR3->paIotlbes = (PIOTLBE)PDMDevHlpMMHeapAllocZ(pDevIns, cbIotlbes);
7065 if (!pThisR3->paIotlbes)
7066 return PDMDevHlpVMSetError(pDevIns, VERR_NO_MEMORY, RT_SRC_POS,
7067 N_("Failed to allocate %zu bytes from the hyperheap for the IOTLB cache."), cbIotlbes);
7068 RTListInit(&pThisR3->LstLruIotlbe);
7069 LogRel(("%s: Allocated %zu bytes from the hyperheap for the IOTLB cache\n", IOMMU_LOG_PFX, cbIotlbes));
7070#endif
7071
7072 /*
7073 * Initialize read-only registers.
7074 * NOTE! Fields here must match their corresponding field in the ACPI tables.
7075 */
7076 /* Don't remove the commented lines below as it lets us see all features at a glance. */
7077 pThis->ExtFeat.u64 = 0;
7078 //pThis->ExtFeat.n.u1PrefetchSup = 0;
7079 //pThis->ExtFeat.n.u1PprSup = 0;
7080 //pThis->ExtFeat.n.u1X2ApicSup = 0;
7081 //pThis->ExtFeat.n.u1NoExecuteSup = 0;
7082 //pThis->ExtFeat.n.u1GstTranslateSup = 0;
7083 pThis->ExtFeat.n.u1InvAllSup = 1;
7084 //pThis->ExtFeat.n.u1GstVirtApicSup = 0;
7085 pThis->ExtFeat.n.u1HwErrorSup = 1;
7086 //pThis->ExtFeat.n.u1PerfCounterSup = 0;
7087 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
7088 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
7089 //pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
7090 //pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
7091 //pThis->ExtFeat.n.u2SmiFilterSup = 0;
7092 //pThis->ExtFeat.n.u3SmiFilterCount = 0;
7093 //pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
7094 //pThis->ExtFeat.n.u2DualPprLogSup = 0;
7095 //pThis->ExtFeat.n.u2DualEvtLogSup = 0;
7096 //pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
7097 //pThis->ExtFeat.n.u1UserSupervisorSup = 0;
7098 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
7099 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
7100 //pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
7101 //pThis->ExtFeat.n.u1PprAutoRespSup = 0;
7102 //pThis->ExtFeat.n.u2MarcSup = 0;
7103 //pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
7104 //pThis->ExtFeat.n.u1PerfOptSup = 0;
7105 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
7106 //pThis->ExtFeat.n.u1GstIoSup = 0;
7107 //pThis->ExtFeat.n.u1HostAccessSup = 0;
7108 //pThis->ExtFeat.n.u1EnhancedPprSup = 0;
7109 //pThis->ExtFeat.n.u1AttrForwardSup = 0;
7110 //pThis->ExtFeat.n.u1HostDirtySup = 0;
7111 //pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
7112 //pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
7113 //pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
7114
7115 pThis->DevSpecificFeat.u64 = 0;
7116 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
7117 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
7118
7119 pThis->DevSpecificCtrl.u64 = 0;
7120 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
7121 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
7122
7123 pThis->DevSpecificStatus.u64 = 0;
7124 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
7125 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
7126
7127 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
7128
7129 pThis->RsvdReg = 0;
7130
7131 /*
7132 * Initialize parts of the IOMMU state as it would during reset.
7133 * Also initializes non-zero initial values like IRTE cache keys.
7134 * Must be called -after- initializing PCI config. space registers.
7135 */
7136 iommuAmdR3Reset(pDevIns);
7137
7138 LogRel(("%s: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
7139 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
7140 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
7141 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
7142 pThis->ExtFeat.u64));
7143 return VINF_SUCCESS;
7144}
7145
7146#else
7147
7148/**
7149 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
7150 */
7151static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
7152{
7153 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7154 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
7155 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
7156 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
7157
7158 /* We will use PDM's critical section (via helpers) for the IOMMU device. */
7159 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7160 AssertRCReturn(rc, rc);
7161
7162 /* Set up the MMIO RZ handlers. */
7163 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
7164 AssertRCReturn(rc, rc);
7165
7166 /* Set up the IOMMU RZ callbacks. */
7167 PDMIOMMUREGCC IommuReg;
7168 RT_ZERO(IommuReg);
7169 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
7170 IommuReg.idxIommu = pThis->idxIommu;
7171 IommuReg.pfnMemAccess = iommuAmdMemAccess;
7172 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
7173 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
7174 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
7175 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
7176 AssertRCReturn(rc, rc);
7177 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
7178 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
7179 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
7180 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
7181 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
7182 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
7183 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
7184 return VINF_SUCCESS;
7185}
7186#endif
7187
7188
7189/**
7190 * The device registration structure.
7191 */
7192const PDMDEVREG g_DeviceIommuAmd =
7193{
7194 /* .u32Version = */ PDM_DEVREG_VERSION,
7195 /* .uReserved0 = */ 0,
7196 /* .szName = */ "iommu-amd",
7197 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
7198 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
7199 /* .cMaxInstances = */ 1,
7200 /* .uSharedVersion = */ 42,
7201 /* .cbInstanceShared = */ sizeof(IOMMU),
7202 /* .cbInstanceCC = */ sizeof(IOMMUCC),
7203 /* .cbInstanceRC = */ sizeof(IOMMURC),
7204 /* .cMaxPciDevices = */ 1,
7205 /* .cMaxMsixVectors = */ 0,
7206 /* .pszDescription = */ "IOMMU (AMD)",
7207#if defined(IN_RING3)
7208 /* .pszRCMod = */ "VBoxDDRC.rc",
7209 /* .pszR0Mod = */ "VBoxDDR0.r0",
7210 /* .pfnConstruct = */ iommuAmdR3Construct,
7211 /* .pfnDestruct = */ iommuAmdR3Destruct,
7212 /* .pfnRelocate = */ NULL,
7213 /* .pfnMemSetup = */ NULL,
7214 /* .pfnPowerOn = */ NULL,
7215 /* .pfnReset = */ iommuAmdR3Reset,
7216 /* .pfnSuspend = */ NULL,
7217 /* .pfnResume = */ NULL,
7218 /* .pfnAttach = */ NULL,
7219 /* .pfnDetach = */ NULL,
7220 /* .pfnQueryInterface = */ NULL,
7221 /* .pfnInitComplete = */ NULL,
7222 /* .pfnPowerOff = */ NULL,
7223 /* .pfnSoftReset = */ NULL,
7224 /* .pfnReserved0 = */ NULL,
7225 /* .pfnReserved1 = */ NULL,
7226 /* .pfnReserved2 = */ NULL,
7227 /* .pfnReserved3 = */ NULL,
7228 /* .pfnReserved4 = */ NULL,
7229 /* .pfnReserved5 = */ NULL,
7230 /* .pfnReserved6 = */ NULL,
7231 /* .pfnReserved7 = */ NULL,
7232#elif defined(IN_RING0)
7233 /* .pfnEarlyConstruct = */ NULL,
7234 /* .pfnConstruct = */ iommuAmdRZConstruct,
7235 /* .pfnDestruct = */ NULL,
7236 /* .pfnFinalDestruct = */ NULL,
7237 /* .pfnRequest = */ NULL,
7238 /* .pfnReserved0 = */ NULL,
7239 /* .pfnReserved1 = */ NULL,
7240 /* .pfnReserved2 = */ NULL,
7241 /* .pfnReserved3 = */ NULL,
7242 /* .pfnReserved4 = */ NULL,
7243 /* .pfnReserved5 = */ NULL,
7244 /* .pfnReserved6 = */ NULL,
7245 /* .pfnReserved7 = */ NULL,
7246#elif defined(IN_RC)
7247 /* .pfnConstruct = */ iommuAmdRZConstruct,
7248 /* .pfnReserved0 = */ NULL,
7249 /* .pfnReserved1 = */ NULL,
7250 /* .pfnReserved2 = */ NULL,
7251 /* .pfnReserved3 = */ NULL,
7252 /* .pfnReserved4 = */ NULL,
7253 /* .pfnReserved5 = */ NULL,
7254 /* .pfnReserved6 = */ NULL,
7255 /* .pfnReserved7 = */ NULL,
7256#else
7257# error "Not in IN_RING3, IN_RING0 or IN_RC!"
7258#endif
7259 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
7260};
7261
7262#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
7263
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