VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio_old/DevIchHda.cpp@ 62463

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1/* $Id: DevIchHda.cpp 62463 2016-07-22 16:32:54Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2016 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22
23/*********************************************************************************************************************************
24* Header Files *
25*********************************************************************************************************************************/
26#define LOG_GROUP LOG_GROUP_DEV_HDA
27#include <VBox/log.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/pdmaudioifs.h>
30#include <VBox/version.h>
31
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34#include <iprt/asm-math.h>
35#include <iprt/list.h>
36#ifdef IN_RING3
37# include <iprt/mem.h>
38# include <iprt/semaphore.h>
39# include <iprt/string.h>
40# include <iprt/uuid.h>
41#endif
42
43#include "VBoxDD.h"
44
45#include "AudioMixBuffer.h"
46#include "AudioMixer.h"
47#include "DevIchHdaCodec.h"
48#include "DrvAudio.h"
49
50
51/*********************************************************************************************************************************
52* Defined Constants And Macros *
53*********************************************************************************************************************************/
54//#define HDA_AS_PCI_EXPRESS
55#define VBOX_WITH_INTEL_HDA
56
57#ifdef DEBUG_andy
58/* Enables experimental support for separate mic-in handling.
59 Do not enable this yet for regular builds, as this needs more testing first! */
60//# define VBOX_WITH_HDA_MIC_IN
61#endif
62
63#if defined(VBOX_WITH_HP_HDA)
64/* HP Pavilion dv4t-1300 */
65# define HDA_PCI_VENDOR_ID 0x103c
66# define HDA_PCI_DEVICE_ID 0x30f7
67#elif defined(VBOX_WITH_INTEL_HDA)
68/* Intel HDA controller */
69# define HDA_PCI_VENDOR_ID 0x8086
70# define HDA_PCI_DEVICE_ID 0x2668
71#elif defined(VBOX_WITH_NVIDIA_HDA)
72/* nVidia HDA controller */
73# define HDA_PCI_VENDOR_ID 0x10de
74# define HDA_PCI_DEVICE_ID 0x0ac0
75#else
76# error "Please specify your HDA device vendor/device IDs"
77#endif
78
79/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
80 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
81 * is read only except for bit 15 like the HDA spec states.
82 *
83 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
84 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
85#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
86
87#define HDA_NREGS 114
88#define HDA_NREGS_SAVED 112
89
90/**
91 * NB: Register values stored in memory (au32Regs[]) are indexed through
92 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
93 * register descriptors in g_aHdaRegMap[] are indexed through the
94 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
95 *
96 * The au32Regs[] layout is kept unchanged for saved state
97 * compatibility. */
98
99/* Registers */
100#define HDA_REG_IND_NAME(x) HDA_REG_##x
101#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
102#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
103#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
104#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
105#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
106#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
107#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
108
109
110#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
111#define HDA_RMX_GCAP 0
112/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
113 * oss (15:12) - number of output streams supported
114 * iss (11:8) - number of input streams supported
115 * bss (7:3) - number of bidirectional streams supported
116 * bds (2:1) - number of serial data out signals supported
117 * b64sup (0) - 64 bit addressing supported.
118 */
119#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
120 ( (((oss) & 0xF) << 12) \
121 | (((iss) & 0xF) << 8) \
122 | (((bss) & 0x1F) << 3) \
123 | (((bds) & 0x3) << 2) \
124 | ((b64sup) & 1))
125
126#define HDA_REG_VMIN 1 /* 0x02 */
127#define HDA_RMX_VMIN 1
128
129#define HDA_REG_VMAJ 2 /* 0x03 */
130#define HDA_RMX_VMAJ 2
131
132#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
133#define HDA_RMX_OUTPAY 3
134
135#define HDA_REG_INPAY 4 /* 0x06-0x07 */
136#define HDA_RMX_INPAY 4
137
138#define HDA_REG_GCTL 5 /* 0x08-0x0B */
139#define HDA_RMX_GCTL 5
140#define HDA_GCTL_RST_SHIFT 0
141#define HDA_GCTL_FSH_SHIFT 1
142#define HDA_GCTL_UR_SHIFT 8
143
144#define HDA_REG_WAKEEN 6 /* 0x0C */
145#define HDA_RMX_WAKEEN 6
146
147#define HDA_REG_STATESTS 7 /* 0x0E */
148#define HDA_RMX_STATESTS 7
149#define HDA_STATES_SCSF 0x7
150
151#define HDA_REG_GSTS 8 /* 0x10-0x11*/
152#define HDA_RMX_GSTS 8
153#define HDA_GSTS_FSH_SHIFT 1
154
155#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
156#define HDA_RMX_OUTSTRMPAY 112
157
158#define HDA_REG_INSTRMPAY 10 /* 0x1a */
159#define HDA_RMX_INSTRMPAY 113
160
161#define HDA_REG_INTCTL 11 /* 0x20 */
162#define HDA_RMX_INTCTL 9
163#define HDA_INTCTL_GIE_SHIFT 31
164#define HDA_INTCTL_CIE_SHIFT 30
165#define HDA_INTCTL_S0_SHIFT 0
166#define HDA_INTCTL_S1_SHIFT 1
167#define HDA_INTCTL_S2_SHIFT 2
168#define HDA_INTCTL_S3_SHIFT 3
169#define HDA_INTCTL_S4_SHIFT 4
170#define HDA_INTCTL_S5_SHIFT 5
171#define HDA_INTCTL_S6_SHIFT 6
172#define HDA_INTCTL_S7_SHIFT 7
173#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
174
175#define HDA_REG_INTSTS 12 /* 0x24 */
176#define HDA_RMX_INTSTS 10
177#define HDA_INTSTS_GIS_SHIFT 31
178#define HDA_INTSTS_CIS_SHIFT 30
179#define HDA_INTSTS_S0_SHIFT 0
180#define HDA_INTSTS_S1_SHIFT 1
181#define HDA_INTSTS_S2_SHIFT 2
182#define HDA_INTSTS_S3_SHIFT 3
183#define HDA_INTSTS_S4_SHIFT 4
184#define HDA_INTSTS_S5_SHIFT 5
185#define HDA_INTSTS_S6_SHIFT 6
186#define HDA_INTSTS_S7_SHIFT 7
187#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
188
189#define HDA_REG_WALCLK 13 /* 0x24 */
190#define HDA_RMX_WALCLK /* Not defined! */
191
192/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
193 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
194 * the datasheet.
195 */
196#define HDA_REG_SSYNC 14 /* 0x34 */
197#define HDA_RMX_SSYNC 12
198
199#define HDA_REG_CORBLBASE 15 /* 0x40 */
200#define HDA_RMX_CORBLBASE 13
201
202#define HDA_REG_CORBUBASE 16 /* 0x44 */
203#define HDA_RMX_CORBUBASE 14
204
205#define HDA_REG_CORBWP 17 /* 0x48 */
206#define HDA_RMX_CORBWP 15
207
208#define HDA_REG_CORBRP 18 /* 0x4A */
209#define HDA_RMX_CORBRP 16
210#define HDA_CORBRP_RST_SHIFT 15
211#define HDA_CORBRP_WP_SHIFT 0
212#define HDA_CORBRP_WP_MASK 0xFF
213
214#define HDA_REG_CORBCTL 19 /* 0x4C */
215#define HDA_RMX_CORBCTL 17
216#define HDA_CORBCTL_DMA_SHIFT 1
217#define HDA_CORBCTL_CMEIE_SHIFT 0
218
219#define HDA_REG_CORBSTS 20 /* 0x4D */
220#define HDA_RMX_CORBSTS 18
221#define HDA_CORBSTS_CMEI_SHIFT 0
222
223#define HDA_REG_CORBSIZE 21 /* 0x4E */
224#define HDA_RMX_CORBSIZE 19
225#define HDA_CORBSIZE_SZ_CAP 0xF0
226#define HDA_CORBSIZE_SZ 0x3
227/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
228
229#define HDA_REG_RIRBLBASE 22 /* 0x50 */
230#define HDA_RMX_RIRBLBASE 20
231
232#define HDA_REG_RIRBUBASE 23 /* 0x54 */
233#define HDA_RMX_RIRBUBASE 21
234
235#define HDA_REG_RIRBWP 24 /* 0x58 */
236#define HDA_RMX_RIRBWP 22
237#define HDA_RIRBWP_RST_SHIFT 15
238#define HDA_RIRBWP_WP_MASK 0xFF
239
240#define HDA_REG_RINTCNT 25 /* 0x5A */
241#define HDA_RMX_RINTCNT 23
242#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
243
244#define HDA_REG_RIRBCTL 26 /* 0x5C */
245#define HDA_RMX_RIRBCTL 24
246#define HDA_RIRBCTL_RIC_SHIFT 0
247#define HDA_RIRBCTL_DMA_SHIFT 1
248#define HDA_ROI_DMA_SHIFT 2
249
250#define HDA_REG_RIRBSTS 27 /* 0x5D */
251#define HDA_RMX_RIRBSTS 25
252#define HDA_RIRBSTS_RINTFL_SHIFT 0
253#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
254
255#define HDA_REG_RIRBSIZE 28 /* 0x5E */
256#define HDA_RMX_RIRBSIZE 26
257#define HDA_RIRBSIZE_SZ_CAP 0xF0
258#define HDA_RIRBSIZE_SZ 0x3
259
260#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
261#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
262
263
264#define HDA_REG_IC 29 /* 0x60 */
265#define HDA_RMX_IC 27
266
267#define HDA_REG_IR 30 /* 0x64 */
268#define HDA_RMX_IR 28
269
270#define HDA_REG_IRS 31 /* 0x68 */
271#define HDA_RMX_IRS 29
272#define HDA_IRS_ICB_SHIFT 0
273#define HDA_IRS_IRV_SHIFT 1
274
275#define HDA_REG_DPLBASE 32 /* 0x70 */
276#define HDA_RMX_DPLBASE 30
277#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
278
279#define HDA_REG_DPUBASE 33 /* 0x74 */
280#define HDA_RMX_DPUBASE 31
281#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
282
283#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
284
285#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
286#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
287/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
288#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
289
290#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
291
292#define HDA_REG_SD0CTL 34 /* 0x80 */
293#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
294#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
295#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
296#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
297#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
298#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
299#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
300#define HDA_RMX_SD0CTL 32
301#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
302#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
303#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
304#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
305#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
306#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
307#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
308
309#define SD(func, num) SD##num##func
310
311#define HDA_SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
312#define HDA_SDCTL_NUM(pThis, num) ((HDA_SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
313#define HDA_SDCTL_NUM_MASK 0xF
314#define HDA_SDCTL_NUM_SHIFT 20
315#define HDA_SDCTL_DIR_SHIFT 19
316#define HDA_SDCTL_TP_SHIFT 18
317#define HDA_SDCTL_STRIPE_MASK 0x3
318#define HDA_SDCTL_STRIPE_SHIFT 16
319#define HDA_SDCTL_DEIE_SHIFT 4
320#define HDA_SDCTL_FEIE_SHIFT 3
321#define HDA_SDCTL_ICE_SHIFT 2
322#define HDA_SDCTL_RUN_SHIFT 1
323#define HDA_SDCTL_SRST_SHIFT 0
324
325#define HDA_REG_SD0STS 35 /* 0x83 */
326#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
327#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
328#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
329#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
330#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
331#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
332#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
333#define HDA_RMX_SD0STS 33
334#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
335#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
336#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
337#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
338#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
339#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
340#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
341
342#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
343#define HDA_SDSTS_FIFORDY_SHIFT 5
344#define HDA_SDSTS_DE_SHIFT 4
345#define HDA_SDSTS_FE_SHIFT 3
346#define HDA_SDSTS_BCIS_SHIFT 2
347
348#define HDA_REG_SD0LPIB 36 /* 0x84 */
349#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
350#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
351#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
352#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
353#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
354#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
355#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
356#define HDA_RMX_SD0LPIB 34
357#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
358#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
359#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
360#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
361#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
362#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
363#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
364
365#define HDA_REG_SD0CBL 37 /* 0x88 */
366#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
367#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
368#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
369#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
370#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
371#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
372#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
373#define HDA_RMX_SD0CBL 35
374#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
375#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
376#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
377#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
378#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
379#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
380#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
381
382#define HDA_REG_SD0LVI 38 /* 0x8C */
383#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
384#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
385#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
386#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
387#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
388#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
389#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
390#define HDA_RMX_SD0LVI 36
391#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
392#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
393#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
394#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
395#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
396#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
397#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
398
399#define HDA_REG_SD0FIFOW 39 /* 0x8E */
400#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
401#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
402#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
403#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
404#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
405#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
406#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
407#define HDA_RMX_SD0FIFOW 37
408#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
409#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
410#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
411#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
412#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
413#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
414#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
415
416/*
417 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
418 */
419#define HDA_SDFIFOW_8B 0x2
420#define HDA_SDFIFOW_16B 0x3
421#define HDA_SDFIFOW_32B 0x4
422
423#define HDA_REG_SD0FIFOS 40 /* 0x90 */
424#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
425#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
426#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
427#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
428#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
429#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
430#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
431#define HDA_RMX_SD0FIFOS 38
432#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
433#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
434#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
435#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
436#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
437#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
438#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
439
440/*
441 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
442 * formula: size - 1
443 * Other values not listed are not supported.
444 */
445#define HDA_SDINFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
446#define HDA_SDINFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
447
448#define HDA_SDONFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
449#define HDA_SDONFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
450#define HDA_SDONFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
451#define HDA_SDONFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
452#define HDA_SDONFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
453#define HDA_SDONFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
454#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
455
456#define HDA_REG_SD0FMT 41 /* 0x92 */
457#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
458#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
459#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
460#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
461#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
462#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
463#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
464#define HDA_RMX_SD0FMT 39
465#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
466#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
467#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
468#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
469#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
470#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
471#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
472
473#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
474#define HDA_SDFMT_BASE_RATE_SHIFT 14
475#define HDA_SDFMT_MULT_SHIFT 11
476#define HDA_SDFMT_MULT_MASK 0x7
477#define HDA_SDFMT_DIV_SHIFT 8
478#define HDA_SDFMT_DIV_MASK 0x7
479#define HDA_SDFMT_BITS_SHIFT 4
480#define HDA_SDFMT_BITS_MASK 0x7
481#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
482#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
483#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
484
485#define HDA_REG_SD0BDPL 42 /* 0x98 */
486#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
487#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
488#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
489#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
490#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
491#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
492#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
493#define HDA_RMX_SD0BDPL 40
494#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
495#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
496#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
497#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
498#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
499#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
500#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
501
502#define HDA_REG_SD0BDPU 43 /* 0x9C */
503#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
504#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
505#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
506#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
507#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
508#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
509#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
510#define HDA_RMX_SD0BDPU 41
511#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
512#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
513#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
514#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
515#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
516#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
517#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
518
519#define HDA_CODEC_CAD_SHIFT 28
520/* Encodes the (required) LUN into a codec command. */
521#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
522
523
524
525/*********************************************************************************************************************************
526* Structures and Typedefs *
527*********************************************************************************************************************************/
528
529/**
530 * Internal state of a Buffer Descriptor List Entry (BDLE),
531 * needed to keep track of the data needed for the actual device
532 * emulation.
533 */
534typedef struct HDABDLESTATE
535{
536 /** Own index within the BDL (Buffer Descriptor List). */
537 uint32_t u32BDLIndex;
538 /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
539 * Used to check if we need fill up the FIFO again. */
540 uint32_t cbBelowFIFOW;
541 /** The buffer descriptor's internal DMA buffer. */
542 uint8_t au8FIFO[HDA_SDONFIFO_256B + 1];
543 /** Current offset in DMA buffer (in bytes).*/
544 uint32_t u32BufOff;
545 uint32_t Padding;
546} HDABDLESTATE, *PHDABDLESTATE;
547
548/**
549 * Buffer Descriptor List Entry (BDLE) (3.6.3).
550 *
551 * Contains only register values which do *not* change until a
552 * stream reset occurs.
553 */
554typedef struct HDABDLE
555{
556 /** Starting address of the actual buffer. Must be 128-bit aligned. */
557 uint64_t u64BufAdr;
558 /** Size of the actual buffer (in bytes). */
559 uint32_t u32BufSize;
560 /** Interrupt on completion; the controller will generate
561 * an interrupt when the last byte of the buffer has been
562 * fetched by the DMA engine. */
563 bool fIntOnCompletion;
564 /** Internal state of this BDLE.
565 * Not part of the actual BDLE registers. */
566 HDABDLESTATE State;
567} HDABDLE, *PHDABDLE;
568
569/**
570 * Internal state of a HDA stream.
571 */
572typedef struct HDASTREAMSTATE
573{
574 /** Current BDLE to use. Wraps around to 0 if
575 * maximum (cBDLE) is reached. */
576 uint16_t uCurBDLE;
577 /** Stop indicator. */
578 volatile bool fDoStop;
579 /** Flag indicating whether this stream is in an
580 * active (operative) state or not. */
581 volatile bool fActive;
582 /** Flag indicating whether this stream currently is
583 * in reset mode and therefore not acccessible by the guest. */
584 volatile bool fInReset;
585 /** Unused, padding. */
586 bool fPadding;
587 /** Event signalling that the stream's state has been changed. */
588 RTSEMEVENT hStateChangedEvent;
589 /** Current BDLE (Buffer Descriptor List Entry). */
590 HDABDLE BDLE;
591} HDASTREAMSTATE, *PHDASTREAMSTATE;
592
593/**
594 * Structure for keeping a HDA stream state.
595 *
596 * Contains only register values which do *not* change until a
597 * stream reset occurs.
598 */
599typedef struct HDASTREAM
600{
601 /** Stream number (SDn). */
602 uint8_t u8Strm;
603 uint8_t Padding0[7];
604 /** DMA base address (SDnBDPU - SDnBDPL). */
605 uint64_t u64BDLBase;
606 /** Cyclic Buffer Length (SDnCBL).
607 * Represents the size of the ring buffer. */
608 uint32_t u32CBL;
609 /** Format (SDnFMT). */
610 uint16_t u16FMT;
611 /** FIFO Size (FIFOS).
612 * Maximum number of bytes that may have been DMA'd into
613 * memory but not yet transmitted on the link.
614 *
615 * Must be a power of two. */
616 uint16_t u16FIFOS;
617 /** Last Valid Index (SDnLVI). */
618 uint16_t u16LVI;
619 uint16_t Padding1[3];
620 /** Internal state of this stream. */
621 HDASTREAMSTATE State;
622} HDASTREAM, *PHDASTREAM;
623
624typedef struct HDAINPUTSTREAM
625{
626 /** PCM line input stream. */
627 R3PTRTYPE(PPDMAUDIOGSTSTRMIN) pStrmIn;
628 /** Mixer handle for line input stream. */
629 R3PTRTYPE(PAUDMIXSTREAM) phStrmIn;
630} HDAINPUTSTREAM, *PHDAINPUTSTREAM;
631
632typedef struct HDAOUTPUTSTREAM
633{
634 /** PCM output stream. */
635 R3PTRTYPE(PPDMAUDIOGSTSTRMOUT) pStrmOut;
636 /** Mixer handle for line output stream. */
637 R3PTRTYPE(PAUDMIXSTREAM) phStrmOut;
638} HDAOUTPUTSTREAM, *PHDAOUTPUTSTREAM;
639
640/**
641 * Struct for maintaining a host backend driver.
642 * This driver must be associated to one, and only one,
643 * HDA codec. The HDA controller does the actual multiplexing
644 * of HDA codec data to various host backend drivers then.
645 *
646 * This HDA device uses a timer in order to synchronize all
647 * read/write accesses across all attached LUNs / backends.
648 */
649typedef struct HDADRIVER
650{
651 /** Node for storing this driver in our device driver list of HDASTATE. */
652 RTLISTNODER3 Node;
653 /** Pointer to HDA controller (state). */
654 R3PTRTYPE(PHDASTATE) pHDAState;
655 /** Driver flags. */
656 PDMAUDIODRVFLAGS Flags;
657 uint8_t u32Padding0[2];
658 /** LUN to which this driver has been assigned. */
659 uint8_t uLUN;
660 /** Whether this driver is in an attached state or not. */
661 bool fAttached;
662 /** Pointer to attached driver base interface. */
663 R3PTRTYPE(PPDMIBASE) pDrvBase;
664 /** Audio connector interface to the underlying host backend. */
665 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
666 /** Stream for line input. */
667 HDAINPUTSTREAM LineIn;
668 /** Stream for mic input. */
669 HDAINPUTSTREAM MicIn;
670 /** Stream for output. */
671 HDAOUTPUTSTREAM Out;
672} HDADRIVER;
673
674/**
675 * ICH Intel HD Audio Controller state.
676 */
677typedef struct HDASTATE
678{
679 /** The PCI device structure. */
680 PCIDevice PciDev;
681 /** R3 Pointer to the device instance. */
682 PPDMDEVINSR3 pDevInsR3;
683 /** R0 Pointer to the device instance. */
684 PPDMDEVINSR0 pDevInsR0;
685 /** R0 Pointer to the device instance. */
686 PPDMDEVINSRC pDevInsRC;
687 /** Padding for alignment. */
688 uint32_t u32Padding;
689 /** The base interface for LUN\#0. */
690 PDMIBASE IBase;
691 RTGCPHYS MMIOBaseAddr;
692 /** The HDA's register set. */
693 uint32_t au32Regs[HDA_NREGS];
694 /** Stream state for line-in. */
695 HDASTREAM StrmStLineIn;
696 /** Stream state for microphone-in. */
697 HDASTREAM StrmStMicIn;
698 /** Stream state for output. */
699 HDASTREAM StrmStOut;
700 /** CORB buffer base address. */
701 uint64_t u64CORBBase;
702 /** RIRB buffer base address. */
703 uint64_t u64RIRBBase;
704 /** DMA base address.
705 * Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
706 uint64_t u64DPBase;
707 /** DMA position buffer enable bit. */
708 bool fDMAPosition;
709 /** Padding for alignment. */
710 uint8_t u32Padding0[7];
711 /** Pointer to CORB buffer. */
712 R3PTRTYPE(uint32_t *) pu32CorbBuf;
713 /** Size in bytes of CORB buffer. */
714 uint32_t cbCorbBuf;
715 /** Padding for alignment. */
716 uint32_t u32Padding1;
717 /** Pointer to RIRB buffer. */
718 R3PTRTYPE(uint64_t *) pu64RirbBuf;
719 /** Size in bytes of RIRB buffer. */
720 uint32_t cbRirbBuf;
721 /** Indicates if HDA is in reset. */
722 bool fInReset;
723 /** Flag whether the R0 part is enabled. */
724 bool fR0Enabled;
725 /** Flag whether the RC part is enabled. */
726 bool fRCEnabled;
727#ifndef VBOX_WITH_AUDIO_CALLBACKS
728 /** The timer for pumping data thru the attached LUN drivers. */
729 PTMTIMERR3 pTimer;
730 /** The timer interval for pumping data thru the LUN drivers in timer ticks. */
731 uint64_t cTimerTicks;
732 /** Timestamp of the last timer callback (hdaTimer).
733 * Used to calculate the time actually elapsed between two timer callbacks. */
734 uint64_t uTimerTS;
735#endif
736#ifdef VBOX_WITH_STATISTICS
737# ifndef VBOX_WITH_AUDIO_CALLBACKS
738 STAMPROFILE StatTimer;
739# endif
740 STAMCOUNTER StatBytesRead;
741 STAMCOUNTER StatBytesWritten;
742#endif
743 /** Pointer to HDA codec to use. */
744 R3PTRTYPE(PHDACODEC) pCodec;
745 /** List of associated LUN drivers (HDADRIVER). */
746 RTLISTANCHORR3 lstDrv;
747 /** The device' software mixer. */
748 R3PTRTYPE(PAUDIOMIXER) pMixer;
749 /** Audio sink for PCM output. */
750 R3PTRTYPE(PAUDMIXSINK) pSinkOutput;
751 /** Audio mixer sink for line input. */
752 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
753 /** Audio mixer sink for microphone input. */
754 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
755 uint64_t u64BaseTS;
756 /** Response Interrupt Count (RINTCNT). */
757 uint8_t u8RespIntCnt;
758 /** Padding for alignment. */
759 uint8_t au8Padding2[7];
760} HDASTATE;
761/** Pointer to the ICH Intel HD Audio Controller state. */
762typedef HDASTATE *PHDASTATE;
763
764#ifdef VBOX_WITH_AUDIO_CALLBACKS
765typedef struct HDACALLBACKCTX
766{
767 PHDASTATE pThis;
768 PHDADRIVER pDriver;
769} HDACALLBACKCTX, *PHDACALLBACKCTX;
770#endif
771
772
773/*********************************************************************************************************************************
774* Internal Functions *
775*********************************************************************************************************************************/
776#ifndef VBOX_DEVICE_STRUCT_TESTCASE
777static FNPDMDEVRESET hdaReset;
778
779/*
780 * Stubs.
781 */
782static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
783static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
784
785/*
786 * Global register set read/write functions.
787 */
788static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
789static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
790static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
791static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
792static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
793static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
794static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
795static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
796static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
797static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
798static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
799static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
800static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
801static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
802static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
803
804/*
805 * {IOB}SDn read/write functions.
806 */
807static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
808static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
809static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
810static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
811static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
812static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
813static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
814static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
815static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
816inline bool hdaRegWriteSDIsAllowed(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
817
818/*
819 * Generic register read/write functions.
820 */
821static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
822static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
823static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
824static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
825static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
826static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
827static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
828static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
829
830#ifdef IN_RING3
831static void hdaStreamDestroy(PHDASTREAM pStrmSt);
832static int hdaStreamStart(PHDASTREAM pStrmSt);
833static int hdaStreamStop(PHDASTREAM pStrmSt);
834static int hdaStreamWaitForStateChange(PHDASTREAM pStrmSt, RTMSINTERVAL msTimeout);
835static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t cbToProcess, uint32_t *pcbProcessed);
836#endif
837
838#ifdef IN_RING3
839static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
840DECLINLINE(void) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t u32LPIB);
841# ifdef LOG_ENABLED
842static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t cBDLE);
843# endif
844#endif
845
846
847/*********************************************************************************************************************************
848* Global Variables *
849*********************************************************************************************************************************/
850
851/** Offset of the SD0 register map. */
852#define HDA_REG_DESC_SD0_BASE 0x80
853
854/** Turn a short global register name into an memory index and a stringized name. */
855#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
856
857/** Turns a short stream register name into an memory index and a stringized name. */
858#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
859
860/** Same as above for a register *not* stored in memory. */
861#define HDA_REG_IDX_LOCAL(abbrev) 0, #abbrev
862
863/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
864#define HDA_REG_MAP_STRM(offset, name) \
865 /* offset size read mask write mask read callback write callback index + abbrev description */ \
866 /* ------- ------- ---------- ---------- -------------- ----------------- ------------------------------ ----------- */ \
867 /* Offset 0x80 (SD0) */ \
868 { offset, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
869 /* Offset 0x83 (SD0) */ \
870 { offset + 0x3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
871 /* Offset 0x84 (SD0) */ \
872 { offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
873 /* Offset 0x88 (SD0) */ \
874 { offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDCBL , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
875 /* Offset 0x8C (SD0) */ \
876 { offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16, hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
877 /* Reserved: FIFO Watermark. ** @todo Document this! */ \
878 { offset + 0xE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16, hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
879 /* Offset 0x90 (SD0) */ \
880 { offset + 0x10, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16, hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
881 /* Offset 0x92 (SD0) */ \
882 { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16, hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Stream Format" }, \
883 /* Reserved: 0x94 - 0x98. */ \
884 /* Offset 0x98 (SD0) */ \
885 { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32, hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
886 /* Offset 0x9C (SD0) */ \
887 { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
888
889/** Defines a single audio stream register set (e.g. OSD0). */
890#define HDA_REG_MAP_DEF_STREAM(index, name) \
891 HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
892
893/* See 302349 p 6.2. */
894static const struct HDAREGDESC
895{
896 /** Register offset in the register space. */
897 uint32_t offset;
898 /** Size in bytes. Registers of size > 4 are in fact tables. */
899 uint32_t size;
900 /** Readable bits. */
901 uint32_t readable;
902 /** Writable bits. */
903 uint32_t writable;
904 /** Read callback. */
905 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
906 /** Write callback. */
907 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
908 /** Index into the register storage array. */
909 uint32_t mem_idx;
910 /** Abbreviated name. */
911 const char *abbrev;
912 /** Descripton. */
913 const char *desc;
914} g_aHdaRegMap[HDA_NREGS] =
915
916{
917 /* offset size read mask write mask read callback write callback index + abbrev */
918 /*------- ------- ---------- ---------- ----------------------- ---------------------- ---------------- */
919 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
920 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
921 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
922 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
923 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
924 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
925 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
926 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , HDA_REG_IDX(STATESTS) }, /* State Change Status */
927 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
928 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
929 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
930 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
931 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
932 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , HDA_REG_IDX_LOCAL(WALCLK) }, /* Wall Clock Counter */
933 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
934 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
935 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
936 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
937 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
938 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
939 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
940 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
941 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
942 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
943 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
944 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
945 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
946 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
947 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
948 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
949 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
950 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
951 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
952 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
953 /* 4 Input Stream Descriptors (ISD). */
954 HDA_REG_MAP_DEF_STREAM(0, SD0),
955 HDA_REG_MAP_DEF_STREAM(1, SD1),
956 HDA_REG_MAP_DEF_STREAM(2, SD2),
957 HDA_REG_MAP_DEF_STREAM(3, SD3),
958 /* 4 Output Stream Descriptors (OSD). */
959 HDA_REG_MAP_DEF_STREAM(4, SD4),
960 HDA_REG_MAP_DEF_STREAM(5, SD5),
961 HDA_REG_MAP_DEF_STREAM(6, SD6),
962 HDA_REG_MAP_DEF_STREAM(7, SD7)
963};
964
965/**
966 * HDA register aliases (HDA spec 3.3.45).
967 * @remarks Sorted by offReg.
968 */
969static const struct
970{
971 /** The alias register offset. */
972 uint32_t offReg;
973 /** The register index. */
974 int idxAlias;
975} g_aHdaRegAliases[] =
976{
977 { 0x2084, HDA_REG_SD0LPIB },
978 { 0x20a4, HDA_REG_SD1LPIB },
979 { 0x20c4, HDA_REG_SD2LPIB },
980 { 0x20e4, HDA_REG_SD3LPIB },
981 { 0x2104, HDA_REG_SD4LPIB },
982 { 0x2124, HDA_REG_SD5LPIB },
983 { 0x2144, HDA_REG_SD6LPIB },
984 { 0x2164, HDA_REG_SD7LPIB },
985};
986
987#ifdef IN_RING3
988/** HDABDLE field descriptors for the v6+ saved state. */
989static SSMFIELD const g_aSSMBDLEFields6[] =
990{
991 SSMFIELD_ENTRY(HDABDLE, u64BufAdr),
992 SSMFIELD_ENTRY(HDABDLE, u32BufSize),
993 SSMFIELD_ENTRY(HDABDLE, fIntOnCompletion),
994 SSMFIELD_ENTRY_TERM()
995};
996
997/** HDABDLESTATE field descriptors for the v6+ saved state. */
998static SSMFIELD const g_aSSMBDLEStateFields6[] =
999{
1000 SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
1001 SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
1002 SSMFIELD_ENTRY(HDABDLESTATE, au8FIFO),
1003 SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
1004 SSMFIELD_ENTRY_TERM()
1005};
1006
1007/** HDASTREAMSTATE field descriptors for the v6+ saved state. */
1008static SSMFIELD const g_aSSMStreamStateFields6[] =
1009{
1010 SSMFIELD_ENTRY_OLD(cBDLE, 2),
1011 SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
1012 SSMFIELD_ENTRY(HDASTREAMSTATE, fDoStop),
1013 SSMFIELD_ENTRY(HDASTREAMSTATE, fActive),
1014 SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
1015 SSMFIELD_ENTRY_TERM()
1016};
1017#endif
1018
1019/**
1020 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
1021 */
1022static uint32_t const g_afMasks[5] =
1023{
1024 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
1025};
1026
1027#ifdef IN_RING3
1028DECLINLINE(void) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t u32LPIB)
1029{
1030 AssertPtrReturnVoid(pThis);
1031 AssertPtrReturnVoid(pStrmSt);
1032
1033 Assert(u32LPIB <= pStrmSt->u32CBL);
1034
1035 LogFlowFunc(("[SD%RU8]: LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
1036 pStrmSt->u8Strm, u32LPIB, pThis->fDMAPosition));
1037
1038 /* Update LPIB in any case. */
1039 HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) = u32LPIB;
1040
1041 /* Do we need to tell the current DMA position? */
1042 if (pThis->fDMAPosition)
1043 {
1044 int rc2 = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
1045 (pThis->u64DPBase & DPBASE_ADDR_MASK) + (pStrmSt->u8Strm * 2 * sizeof(uint32_t)),
1046 (void *)&u32LPIB, sizeof(uint32_t));
1047 AssertRC(rc2);
1048#ifdef DEBUG
1049 hdaBDLEDumpAll(pThis, pStrmSt->u64BDLBase, pStrmSt->State.uCurBDLE);
1050#endif
1051 }
1052}
1053#endif
1054
1055/**
1056 * Retrieves the number of bytes of a FIFOS register.
1057 *
1058 * @return Number of bytes of a given FIFOS register.
1059 */
1060DECLINLINE(uint16_t) hdaSDFIFOSToBytes(uint32_t u32RegFIFOS)
1061{
1062 uint16_t cb;
1063 switch (u32RegFIFOS)
1064 {
1065 /* Input */
1066 case HDA_SDINFIFO_120B: cb = 120; break;
1067 case HDA_SDINFIFO_160B: cb = 160; break;
1068
1069 /* Output */
1070 case HDA_SDONFIFO_16B: cb = 16; break;
1071 case HDA_SDONFIFO_32B: cb = 32; break;
1072 case HDA_SDONFIFO_64B: cb = 64; break;
1073 case HDA_SDONFIFO_128B: cb = 128; break;
1074 case HDA_SDONFIFO_192B: cb = 192; break;
1075 case HDA_SDONFIFO_256B: cb = 256; break;
1076 default:
1077 {
1078 cb = 0; /* Can happen on stream reset. */
1079 break;
1080 }
1081 }
1082
1083 return cb;
1084}
1085
1086/**
1087 * Retrieves the number of bytes of a FIFOW register.
1088 *
1089 * @return Number of bytes of a given FIFOW register.
1090 */
1091DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
1092{
1093 uint32_t cb;
1094 switch (u32RegFIFOW)
1095 {
1096 case HDA_SDFIFOW_8B: cb = 8; break;
1097 case HDA_SDFIFOW_16B: cb = 16; break;
1098 case HDA_SDFIFOW_32B: cb = 32; break;
1099 default: cb = 0; break;
1100 }
1101
1102#ifdef RT_STRICT
1103 Assert(RT_IS_POWER_OF_TWO(cb));
1104#endif
1105 return cb;
1106}
1107
1108#ifdef IN_RING3
1109/**
1110 * Fetches the next BDLE to use for a stream.
1111 *
1112 * @return IPRT status code.
1113 */
1114DECLINLINE(int) hdaStreamGetNextBDLE(PHDASTATE pThis, PHDASTREAM pStrmSt)
1115{
1116 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1117 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1118
1119 NOREF(pThis);
1120
1121 Assert(pStrmSt->State.uCurBDLE < pStrmSt->u16LVI + 1);
1122
1123#ifdef DEBUG
1124 uint32_t uOldBDLE = pStrmSt->State.uCurBDLE;
1125#endif
1126
1127 /*
1128 * Switch to the next BDLE entry and do a wrap around
1129 * if we reached the end of the Buffer Descriptor List (BDL).
1130 */
1131 pStrmSt->State.uCurBDLE++;
1132 if (pStrmSt->State.uCurBDLE == pStrmSt->u16LVI + 1)
1133 {
1134 pStrmSt->State.uCurBDLE = 0;
1135
1136 hdaStreamUpdateLPIB(pThis, pStrmSt, 0);
1137 }
1138
1139 Assert(pStrmSt->State.uCurBDLE < pStrmSt->u16LVI + 1);
1140
1141 int rc = hdaBDLEFetch(pThis, &pStrmSt->State.BDLE, pStrmSt->u64BDLBase, pStrmSt->State.uCurBDLE);
1142
1143#ifdef DEBUG
1144 LogFlowFunc(("[SD%RU8]: uOldBDLE=%RU16, uCurBDLE=%RU16, LVI=%RU32, %R[bdle]\n",
1145 pStrmSt->u8Strm, uOldBDLE, pStrmSt->State.uCurBDLE, pStrmSt->u16LVI, &pStrmSt->State.BDLE));
1146#endif
1147 return rc;
1148}
1149#endif
1150
1151DECLINLINE(PHDASTREAM) hdaStreamFromID(PHDASTATE pThis, uint8_t uStreamID)
1152{
1153 PHDASTREAM pStrmSt;
1154
1155 switch (uStreamID)
1156 {
1157 case 0: /** @todo Use dynamic indices, based on stream assignment. */
1158 {
1159 pStrmSt = &pThis->StrmStLineIn;
1160 break;
1161 }
1162# ifdef VBOX_WITH_HDA_MIC_IN
1163 case 2: /** @todo Use dynamic indices, based on stream assignment. */
1164 {
1165 pStrmSt = &pThis->StrmStMicIn;
1166 break;
1167 }
1168# endif
1169 case 4: /** @todo Use dynamic indices, based on stream assignment. */
1170 {
1171 pStrmSt = &pThis->StrmStOut;
1172 break;
1173 }
1174
1175 default:
1176 {
1177 pStrmSt = NULL;
1178 LogFunc(("Warning: Stream with ID=%RU8 not handled\n", uStreamID));
1179 break;
1180 }
1181 }
1182
1183 return pStrmSt;
1184}
1185
1186/**
1187 * Retrieves the minimum number of bytes accumulated/free in the
1188 * FIFO before the controller will start a fetch/eviction of data.
1189 *
1190 * Uses SDFIFOW (FIFO Watermark Register).
1191 *
1192 * @return Number of bytes accumulated/free in the FIFO.
1193 */
1194DECLINLINE(uint8_t) hdaStreamGetFIFOW(PHDASTATE pThis, PHDASTREAM pStrmSt)
1195{
1196 AssertPtrReturn(pThis, 0);
1197 AssertPtrReturn(pStrmSt, 0);
1198
1199#ifdef VBOX_HDA_WITH_FIFO
1200 return hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, pStrmSt->u8Strm));
1201#else
1202 return 0;
1203#endif
1204}
1205
1206static int hdaProcessInterrupt(PHDASTATE pThis)
1207{
1208#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
1209 ( INTCTL_SX((pThis), num) \
1210 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1211
1212 bool fIrq = false;
1213
1214 if (/* Controller Interrupt Enable (CIE). */
1215 HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
1216 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1217 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1218 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1219 fIrq = true;
1220
1221 /** @todo Don't hardcode stream numbers here. */
1222 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1223 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
1224 {
1225#ifdef IN_RING3
1226 LogFunc(("BCIS\n"));
1227#endif
1228 fIrq = true;
1229 }
1230
1231 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1232 {
1233 LogFunc(("%s\n", fIrq ? "Asserted" : "Deasserted"));
1234 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , fIrq);
1235 }
1236
1237#undef IS_INTERRUPT_OCCURED_AND_ENABLED
1238
1239 return VINF_SUCCESS;
1240}
1241
1242/**
1243 * Looks up a register at the exact offset given by @a offReg.
1244 *
1245 * @returns Register index on success, -1 if not found.
1246 * @param pThis The HDA device state.
1247 * @param offReg The register offset.
1248 */
1249static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
1250{
1251 /*
1252 * Aliases.
1253 */
1254 if (offReg >= g_aHdaRegAliases[0].offReg)
1255 {
1256 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1257 if (offReg == g_aHdaRegAliases[i].offReg)
1258 return g_aHdaRegAliases[i].idxAlias;
1259 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1260 return -1;
1261 }
1262
1263 /*
1264 * Binary search the
1265 */
1266 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1267 int idxLow = 0;
1268 for (;;)
1269 {
1270 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1271 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1272 {
1273 if (idxLow == idxMiddle)
1274 break;
1275 idxEnd = idxMiddle;
1276 }
1277 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1278 {
1279 idxLow = idxMiddle + 1;
1280 if (idxLow >= idxEnd)
1281 break;
1282 }
1283 else
1284 return idxMiddle;
1285 }
1286
1287#ifdef RT_STRICT
1288 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1289 Assert(g_aHdaRegMap[i].offset != offReg);
1290#endif
1291 return -1;
1292}
1293
1294/**
1295 * Looks up a register covering the offset given by @a offReg.
1296 *
1297 * @returns Register index on success, -1 if not found.
1298 * @param pThis The HDA device state.
1299 * @param offReg The register offset.
1300 */
1301static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
1302{
1303 /*
1304 * Aliases.
1305 */
1306 if (offReg >= g_aHdaRegAliases[0].offReg)
1307 {
1308 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1309 {
1310 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1311 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1312 return g_aHdaRegAliases[i].idxAlias;
1313 }
1314 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1315 return -1;
1316 }
1317
1318 /*
1319 * Binary search the register map.
1320 */
1321 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1322 int idxLow = 0;
1323 for (;;)
1324 {
1325 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1326 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1327 {
1328 if (idxLow == idxMiddle)
1329 break;
1330 idxEnd = idxMiddle;
1331 }
1332 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1333 {
1334 idxLow = idxMiddle + 1;
1335 if (idxLow >= idxEnd)
1336 break;
1337 }
1338 else
1339 return idxMiddle;
1340 }
1341
1342#ifdef RT_STRICT
1343 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1344 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1345#endif
1346 return -1;
1347}
1348
1349#ifdef IN_RING3
1350static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1351{
1352 int rc = VINF_SUCCESS;
1353 if (fLocal)
1354 {
1355 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1356 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1357 if (RT_FAILURE(rc))
1358 AssertRCReturn(rc, rc);
1359#ifdef DEBUG_CMD_BUFFER
1360 uint8_t i = 0;
1361 do
1362 {
1363 LogFunc(("CORB%02x: ", i));
1364 uint8_t j = 0;
1365 do
1366 {
1367 const char *pszPrefix;
1368 if ((i + j) == HDA_REG(pThis, CORBRP));
1369 pszPrefix = "[R]";
1370 else if ((i + j) == HDA_REG(pThis, CORBWP));
1371 pszPrefix = "[W]";
1372 else
1373 pszPrefix = " "; /* three spaces */
1374 LogFunc(("%s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
1375 j++;
1376 } while (j < 8);
1377 LogFunc(("\n"));
1378 i += 8;
1379 } while(i != 0);
1380#endif
1381 }
1382 else
1383 {
1384 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1385 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1386 if (RT_FAILURE(rc))
1387 AssertRCReturn(rc, rc);
1388#ifdef DEBUG_CMD_BUFFER
1389 uint8_t i = 0;
1390 do {
1391 LogFunc(("RIRB%02x: ", i));
1392 uint8_t j = 0;
1393 do {
1394 const char *prefix;
1395 if ((i + j) == HDA_REG(pThis, RIRBWP))
1396 prefix = "[W]";
1397 else
1398 prefix = " ";
1399 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1400 } while (++j < 8);
1401 LogFunc(("\n"));
1402 i += 8;
1403 } while (i != 0);
1404#endif
1405 }
1406 return rc;
1407}
1408
1409static int hdaCORBCmdProcess(PHDASTATE pThis)
1410{
1411 PFNHDACODECVERBPROCESSOR pfn = (PFNHDACODECVERBPROCESSOR)NULL;
1412
1413 int rc = hdaCmdSync(pThis, true);
1414 if (RT_FAILURE(rc))
1415 AssertRCReturn(rc, rc);
1416
1417 uint8_t corbRp = HDA_REG(pThis, CORBRP);
1418 uint8_t corbWp = HDA_REG(pThis, CORBWP);
1419 uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
1420
1421 Assert((corbWp != corbRp));
1422 LogFlowFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1423
1424 while (corbRp != corbWp)
1425 {
1426 uint32_t cmd;
1427 uint64_t resp;
1428 pfn = NULL;
1429 corbRp++;
1430 cmd = pThis->pu32CorbBuf[corbRp];
1431
1432 rc = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(cmd, 0 /* Codec index */), &pfn);
1433 if (RT_SUCCESS(rc))
1434 {
1435 AssertPtr(pfn);
1436 rc = pfn(pThis->pCodec, HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1437 }
1438
1439 if (RT_FAILURE(rc))
1440 AssertRCReturn(rc, rc);
1441 (rirbWp)++;
1442
1443 LogFunc(("verb:%08x->%016lx\n", cmd, resp));
1444 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
1445 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1446 {
1447 LogFunc(("unexpected unsolicited response.\n"));
1448 HDA_REG(pThis, CORBRP) = corbRp;
1449 return rc;
1450 }
1451
1452 pThis->pu64RirbBuf[rirbWp] = resp;
1453
1454 pThis->u8RespIntCnt++;
1455 if (pThis->u8RespIntCnt == RINTCNT_N(pThis))
1456 break;
1457 }
1458 HDA_REG(pThis, CORBRP) = corbRp;
1459 HDA_REG(pThis, RIRBWP) = rirbWp;
1460 rc = hdaCmdSync(pThis, false);
1461 LogFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1462 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1463 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1464 {
1465 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1466
1467 pThis->u8RespIntCnt = 0;
1468 rc = hdaProcessInterrupt(pThis);
1469 }
1470 if (RT_FAILURE(rc))
1471 AssertRCReturn(rc, rc);
1472 return rc;
1473}
1474
1475static int hdaStreamCreate(PHDASTREAM pStrmSt)
1476{
1477 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1478
1479 int rc = RTSemEventCreate(&pStrmSt->State.hStateChangedEvent);
1480 AssertRC(rc);
1481
1482 pStrmSt->u8Strm = UINT8_MAX;
1483
1484 pStrmSt->State.fActive = false;
1485 pStrmSt->State.fInReset = false;
1486 pStrmSt->State.fDoStop = false;
1487
1488 LogFlowFuncLeaveRC(rc);
1489 return rc;
1490}
1491
1492static void hdaStreamDestroy(PHDASTREAM pStrmSt)
1493{
1494 AssertPtrReturnVoid(pStrmSt);
1495
1496 LogFlowFunc(("[SD%RU8]: Destroy\n", pStrmSt->u8Strm));
1497
1498 int rc2 = hdaStreamStop(pStrmSt);
1499 AssertRC(rc2);
1500
1501 if (pStrmSt->State.hStateChangedEvent != NIL_RTSEMEVENT)
1502 {
1503 rc2 = RTSemEventDestroy(pStrmSt->State.hStateChangedEvent);
1504 AssertRC(rc2);
1505 }
1506
1507 LogFlowFuncLeave();
1508}
1509
1510static int hdaStreamInit(PHDASTATE pThis, PHDASTREAM pStrmSt, uint8_t u8Strm)
1511{
1512 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1513 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1514
1515 pStrmSt->u8Strm = u8Strm;
1516 pStrmSt->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStrmSt->u8Strm),
1517 HDA_STREAM_REG(pThis, BDPU, pStrmSt->u8Strm));
1518 pStrmSt->u16LVI = HDA_STREAM_REG(pThis, LVI, pStrmSt->u8Strm);
1519 pStrmSt->u32CBL = HDA_STREAM_REG(pThis, CBL, pStrmSt->u8Strm);
1520 pStrmSt->u16FIFOS = hdaSDFIFOSToBytes(HDA_STREAM_REG(pThis, FIFOS, pStrmSt->u8Strm));
1521
1522 RT_ZERO(pStrmSt->State.BDLE);
1523 pStrmSt->State.uCurBDLE = 0;
1524
1525 LogFlowFunc(("[SD%RU8]: DMA @ 0x%x (%RU32 bytes), LVI=%RU16, FIFOS=%RU16\n",
1526 pStrmSt->u8Strm, pStrmSt->u64BDLBase, pStrmSt->u32CBL, pStrmSt->u16LVI, pStrmSt->u16FIFOS));
1527
1528#ifdef DEBUG
1529 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
1530 HDA_STREAM_REG(pThis, BDPU, u8Strm));
1531 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, u8Strm);
1532 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
1533
1534 LogFlowFunc(("\t-> DMA @ 0x%x, LVI=%RU16, CBL=%RU32\n", u64BaseDMA, u16LVI, u32CBL));
1535
1536 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
1537#endif
1538
1539 return VINF_SUCCESS;
1540}
1541
1542static void hdaStreamReset(PHDASTATE pThis, PHDASTREAM pStrmSt, uint8_t u8Strm)
1543{
1544 AssertPtrReturnVoid(pThis);
1545 AssertPtrReturnVoid(pStrmSt);
1546 AssertReturnVoid(u8Strm <= 7); /** @todo Use a define for MAX_STREAMS! */
1547
1548#ifdef VBOX_STRICT
1549 AssertReleaseMsg(!RT_BOOL(HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
1550 ("Cannot reset stream %RU8 while in running state\n", u8Strm));
1551#endif
1552
1553 /*
1554 * Set reset state.
1555 */
1556 Assert(ASMAtomicReadBool(&pStrmSt->State.fInReset) == false); /* No nested calls. */
1557 ASMAtomicXchgBool(&pStrmSt->State.fInReset, true);
1558
1559 /*
1560 * First, reset the internal stream state.
1561 */
1562 RT_BZERO(pStrmSt, sizeof(HDASTREAM));
1563
1564 /*
1565 * Second, initialize the registers.
1566 */
1567 HDA_STREAM_REG(pThis, STS, u8Strm) = 0;
1568 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1569 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
1570 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1571 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39. */
1572 HDA_STREAM_REG(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
1573 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
1574 HDA_STREAM_REG(pThis, FIFOW, u8Strm) = HDA_SDFIFOW_32B;
1575 HDA_STREAM_REG(pThis, LPIB, u8Strm) = 0;
1576 HDA_STREAM_REG(pThis, CBL, u8Strm) = 0;
1577 HDA_STREAM_REG(pThis, LVI, u8Strm) = 0;
1578 HDA_STREAM_REG(pThis, FMT, u8Strm) = 0;
1579 HDA_STREAM_REG(pThis, BDPU, u8Strm) = 0;
1580 HDA_STREAM_REG(pThis, BDPL, u8Strm) = 0;
1581
1582 /*
1583 * Third, set the internal state according to the just set registers.
1584 */
1585 pStrmSt->u8Strm = u8Strm;
1586 pStrmSt->u16FIFOS = HDA_STREAM_REG(pThis, FIFOS, u8Strm);
1587
1588
1589 /* Report that we're done resetting this stream. */
1590 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0;
1591
1592 LogFunc(("[SD%RU8]: Reset\n", u8Strm));
1593
1594 /* Exit reset mode. */
1595 ASMAtomicXchgBool(&pStrmSt->State.fInReset, false);
1596}
1597
1598static int hdaStreamStart(PHDASTREAM pStrmSt)
1599{
1600 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1601
1602 ASMAtomicXchgBool(&pStrmSt->State.fDoStop, false);
1603 ASMAtomicXchgBool(&pStrmSt->State.fActive, true);
1604
1605 LogFlowFuncLeave();
1606 return VINF_SUCCESS;
1607}
1608
1609static int hdaStreamStop(PHDASTREAM pStrmSt)
1610{
1611 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1612
1613 /* Already in stopped state? */
1614 bool fActive = ASMAtomicReadBool(&pStrmSt->State.fActive);
1615 if (!fActive)
1616 return VINF_SUCCESS;
1617
1618#if 0 /** @todo Does not work (yet), as EMT deadlocks then. */
1619 /*
1620 * Wait for the stream to stop.
1621 */
1622 ASMAtomicXchgBool(&pStrmSt->State.fDoStop, true);
1623
1624 int rc = hdaStreamWaitForStateChange(pStrmSt, 60 * 1000 /* ms timeout */);
1625 fActive = ASMAtomicReadBool(&pStrmSt->State.fActive);
1626 if ( /* Waiting failed? */
1627 RT_FAILURE(rc)
1628 /* Stream is still active? */
1629 || fActive)
1630 {
1631 AssertRC(rc);
1632 LogRel(("HDA: Warning: Unable to stop stream %RU8 (state: %s), rc=%Rrc\n",
1633 pStrmSt->u8Strm, fActive ? "active" : "stopped", rc));
1634 }
1635#else
1636 int rc = VINF_SUCCESS;
1637#endif
1638
1639 LogFlowFuncLeaveRC(rc);
1640 return rc;
1641}
1642
1643static int hdaStreamWaitForStateChange(PHDASTREAM pStrmSt, RTMSINTERVAL msTimeout)
1644{
1645 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
1646
1647 LogFlowFunc(("[SD%RU8]: msTimeout=%RU32\n", pStrmSt->u8Strm, msTimeout));
1648 return RTSemEventWait(pStrmSt->State.hStateChangedEvent, msTimeout);
1649}
1650#endif /* IN_RING3 */
1651
1652/* Register access handlers. */
1653
1654static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1655{
1656 *pu32Value = 0;
1657 return VINF_SUCCESS;
1658}
1659
1660static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1661{
1662 return VINF_SUCCESS;
1663}
1664
1665/* U8 */
1666static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1667{
1668 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1669 return hdaRegReadU32(pThis, iReg, pu32Value);
1670}
1671
1672static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1673{
1674 Assert((u32Value & 0xffffff00) == 0);
1675 return hdaRegWriteU32(pThis, iReg, u32Value);
1676}
1677
1678/* U16 */
1679static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1680{
1681 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1682 return hdaRegReadU32(pThis, iReg, pu32Value);
1683}
1684
1685static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1686{
1687 Assert((u32Value & 0xffff0000) == 0);
1688 return hdaRegWriteU32(pThis, iReg, u32Value);
1689}
1690
1691/* U24 */
1692static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1693{
1694 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
1695 return hdaRegReadU32(pThis, iReg, pu32Value);
1696}
1697
1698static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1699{
1700 Assert((u32Value & 0xff000000) == 0);
1701 return hdaRegWriteU32(pThis, iReg, u32Value);
1702}
1703
1704/* U32 */
1705static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1706{
1707 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1708
1709 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
1710 return VINF_SUCCESS;
1711}
1712
1713static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1714{
1715 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1716
1717 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
1718 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
1719 return VINF_SUCCESS;
1720}
1721
1722static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1723{
1724 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1725 {
1726 /* Set the CRST bit to indicate that we're leaving reset mode. */
1727 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1728
1729 if (pThis->fInReset)
1730 {
1731 LogFunc(("Leaving reset\n"));
1732 pThis->fInReset = false;
1733 }
1734 }
1735 else
1736 {
1737#ifdef IN_RING3
1738 /* Enter reset state. */
1739 if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
1740 || HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
1741 {
1742 LogFunc(("Entering reset with DMA(RIRB:%s, CORB:%s)\n",
1743 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
1744 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
1745 }
1746
1747 /* Clear the CRST bit to indicate that we're in reset mode. */
1748 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1749 pThis->fInReset = true;
1750
1751 /* As the CRST bit now is set, we now can proceed resetting stuff. */
1752 hdaReset(pThis->CTX_SUFF(pDevIns));
1753#else
1754 return VINF_IOM_R3_MMIO_WRITE;
1755#endif
1756 }
1757 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1758 {
1759 /* Flush: GSTS:1 set, see 6.2.6. */
1760 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* Set the flush state. */
1761 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
1762 }
1763 return VINF_SUCCESS;
1764}
1765
1766static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1767{
1768 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1769
1770 uint32_t v = pThis->au32Regs[iRegMem];
1771 uint32_t nv = u32Value & HDA_STATES_SCSF;
1772 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
1773 return VINF_SUCCESS;
1774}
1775
1776static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1777{
1778 uint32_t v = 0;
1779 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1780 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1781 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
1782 || HDA_REG(pThis, STATESTS))
1783 {
1784 v |= RT_BIT(30); /* Touch CIS. */
1785 }
1786
1787#define HDA_IS_STREAM_EVENT(pThis, num) \
1788 ( (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1789 || (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1790 || (SDSTS((pThis), num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1791
1792#define HDA_MARK_STREAM(pThis, num, v) \
1793 do { (v) |= HDA_IS_STREAM_EVENT((pThis), num) ? RT_BIT((num)) : 0; } while(0)
1794
1795 HDA_MARK_STREAM(pThis, 0, v);
1796 HDA_MARK_STREAM(pThis, 1, v);
1797 HDA_MARK_STREAM(pThis, 2, v);
1798 HDA_MARK_STREAM(pThis, 3, v);
1799 HDA_MARK_STREAM(pThis, 4, v);
1800 HDA_MARK_STREAM(pThis, 5, v);
1801 HDA_MARK_STREAM(pThis, 6, v);
1802 HDA_MARK_STREAM(pThis, 7, v);
1803
1804#undef HDA_IS_STREAM_EVENT
1805#undef HDA_MARK_STREAM
1806
1807 v |= v ? RT_BIT(31) : 0;
1808
1809 *pu32Value = v;
1810 return VINF_SUCCESS;
1811}
1812
1813static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1814{
1815 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
1816 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
1817 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
1818
1819 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32CBL));
1820
1821 *pu32Value = u32LPIB;
1822 return VINF_SUCCESS;
1823}
1824
1825static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1826{
1827 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1828 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
1829 - pThis->u64BaseTS, 24, 1000);
1830 LogFlowFunc(("%RU32\n", *pu32Value));
1831 return VINF_SUCCESS;
1832}
1833
1834static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1835{
1836 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1837 {
1838 HDA_REG(pThis, CORBRP) = 0;
1839 }
1840#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
1841 else
1842 return hdaRegWriteU8(pThis, iReg, u32Value);
1843#endif
1844 return VINF_SUCCESS;
1845}
1846
1847static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1848{
1849#ifdef IN_RING3
1850 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1851 AssertRC(rc);
1852 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1853 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
1854 {
1855 return hdaCORBCmdProcess(pThis);
1856 }
1857 return rc;
1858#else
1859 return VINF_IOM_R3_MMIO_WRITE;
1860#endif
1861}
1862
1863static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1864{
1865 uint32_t v = HDA_REG(pThis, CORBSTS);
1866 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1867 return VINF_SUCCESS;
1868}
1869
1870static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1871{
1872#ifdef IN_RING3
1873 int rc;
1874 rc = hdaRegWriteU16(pThis, iReg, u32Value);
1875 if (RT_FAILURE(rc))
1876 AssertRCReturn(rc, rc);
1877 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
1878 return VINF_SUCCESS;
1879 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1880 return VINF_SUCCESS;
1881 rc = hdaCORBCmdProcess(pThis);
1882 return rc;
1883#else
1884 return VINF_IOM_R3_MMIO_WRITE;
1885#endif
1886}
1887
1888static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1889{
1890 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1891 if (RT_SUCCESS(rc))
1892 {
1893 uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, CBL, iReg);
1894
1895 PHDASTREAM pStrmSt = hdaStreamFromID(pThis, u8Strm);
1896 if (pStrmSt)
1897 {
1898 pStrmSt->u32CBL = u32Value;
1899
1900 /* Reset BDLE state. */
1901 RT_ZERO(pStrmSt->State.BDLE);
1902 pStrmSt->State.uCurBDLE = 0;
1903 }
1904
1905 LogFlowFunc(("[SD%RU8]: CBL=%RU32\n", u8Strm, u32Value));
1906 }
1907 else
1908 AssertRCReturn(rc, VINF_SUCCESS);
1909
1910 return rc;
1911}
1912
1913static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1914{
1915 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1916 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1917 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1918 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1919
1920 uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
1921
1922 PHDASTREAM pStrmSt = hdaStreamFromID(pThis, u8Strm);
1923 if (!pStrmSt)
1924 {
1925 LogFunc(("Warning: Changing SDCTL on non-attached stream with ID=%RU8 (iReg=0x%x)\n", u8Strm, iReg));
1926 return hdaRegWriteU24(pThis, iReg, u32Value); /* Write 3 bytes. */
1927 }
1928
1929 LogFunc(("[SD%RU8]: fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
1930 u8Strm, fRun, fInRun, fReset, fInReset, u32Value));
1931
1932 if (fInReset)
1933 {
1934 /* Guest is resetting HDA's stream, we're expecting guest will mark stream as exit. */
1935 Assert(!fReset);
1936 LogFunc(("Guest initiated exit of stream reset\n"));
1937 }
1938 else if (fReset)
1939 {
1940#ifdef IN_RING3
1941 /* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
1942 Assert(!fInRun && !fRun);
1943
1944 LogFunc(("Guest initiated enter to stream reset\n"));
1945 hdaStreamReset(pThis, pStrmSt, u8Strm);
1946#else
1947 return VINF_IOM_R3_MMIO_WRITE;
1948#endif
1949 }
1950 else
1951 {
1952#ifdef IN_RING3
1953 /*
1954 * We enter here to change DMA states only.
1955 */
1956 if (fInRun != fRun)
1957 {
1958 Assert(!fReset && !fInReset);
1959 LogFunc(("[SD%RU8]: fRun=%RTbool\n", u8Strm, fRun));
1960
1961 PHDADRIVER pDrv;
1962 switch (u8Strm)
1963 {
1964 case 0: /** @todo Use a variable here. Later. */
1965 {
1966 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1967 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1968 pDrv->LineIn.pStrmIn, fRun);
1969 break;
1970 }
1971# ifdef VBOX_WITH_HDA_MIC_IN
1972 case 2: /** @todo Use a variable here. Later. */
1973 {
1974 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1975 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1976 pDrv->MicIn.pStrmIn, fRun);
1977 break;
1978 }
1979# endif
1980 case 4: /** @todo Use a variable here. Later. */
1981 {
1982 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1983 pDrv->pConnector->pfnEnableOut(pDrv->pConnector,
1984 pDrv->Out.pStrmOut, fRun);
1985 break;
1986 }
1987 default:
1988 AssertMsgFailed(("Changing RUN bit on non-attached stream, register %RU32\n", iReg));
1989 break;
1990 }
1991 }
1992
1993 if (!fInRun && !fRun)
1994 hdaStreamInit(pThis, pStrmSt, u8Strm);
1995
1996#else /* !IN_RING3 */
1997 return VINF_IOM_R3_MMIO_WRITE;
1998#endif /* IN_RING3 */
1999 }
2000
2001 return hdaRegWriteU24(pThis, iReg, u32Value);
2002}
2003
2004static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2005{
2006 uint32_t v = HDA_REG_IND(pThis, iReg);
2007 v &= ~(u32Value & v);
2008 HDA_REG_IND(pThis, iReg) = v;
2009 hdaProcessInterrupt(pThis);
2010 return VINF_SUCCESS;
2011}
2012
2013static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2014{
2015 if (!hdaRegWriteSDIsAllowed(pThis, iReg, u32Value))
2016 return VINF_SUCCESS;
2017
2018 int rc = hdaRegWriteU16(pThis, iReg, u32Value);
2019 if (RT_SUCCESS(rc))
2020 {
2021 uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, LVI, iReg);
2022
2023 PHDASTREAM pStrmSt = hdaStreamFromID(pThis, u8Strm);
2024 if (pStrmSt)
2025 {
2026 pStrmSt->u16LVI = u32Value;
2027
2028 /* Reset BDLE state. */
2029 RT_ZERO(pStrmSt->State.BDLE);
2030 pStrmSt->State.uCurBDLE = 0;
2031 }
2032
2033 LogFlowFunc(("[SD%RU8]: CBL=%RU32\n", u8Strm, u32Value));
2034 }
2035 else
2036 AssertRCReturn(rc, VINF_SUCCESS);
2037
2038 return rc;
2039}
2040
2041static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2042{
2043 switch (u32Value)
2044 {
2045 case HDA_SDFIFOW_8B:
2046 case HDA_SDFIFOW_16B:
2047 case HDA_SDFIFOW_32B:
2048 return hdaRegWriteU16(pThis, iReg, u32Value);
2049 default:
2050 LogFunc(("Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
2051 return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);
2052 }
2053 return VINF_SUCCESS; /* Never reached. */
2054}
2055
2056/**
2057 * @note This method could be called for changing value on Output Streams
2058 * only (ICH6 datasheet 18.2.39).
2059 */
2060static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2061{
2062 /** @todo Only allow updating FIFOS if RUN bit is 0? */
2063 uint32_t u32FIFOS = 0;
2064
2065 switch (iReg)
2066 {
2067 /* SDInFIFOS is RO, n=0-3. */
2068 case HDA_REG_SD0FIFOS:
2069 case HDA_REG_SD1FIFOS:
2070 case HDA_REG_SD2FIFOS:
2071 case HDA_REG_SD3FIFOS:
2072 {
2073 LogFunc(("Guest tries to change R/O value of FIFO size of input stream, ignoring\n"));
2074 break;
2075 }
2076 case HDA_REG_SD4FIFOS:
2077 case HDA_REG_SD5FIFOS:
2078 case HDA_REG_SD6FIFOS:
2079 case HDA_REG_SD7FIFOS:
2080 {
2081 switch(u32Value)
2082 {
2083 case HDA_SDONFIFO_16B:
2084 case HDA_SDONFIFO_32B:
2085 case HDA_SDONFIFO_64B:
2086 case HDA_SDONFIFO_128B:
2087 case HDA_SDONFIFO_192B:
2088 u32FIFOS = u32Value;
2089 break;
2090
2091 case HDA_SDONFIFO_256B: /** @todo r=andy Investigate this. */
2092 LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
2093 /* Fall through is intentional. */
2094 default:
2095 u32FIFOS = HDA_SDONFIFO_192B;
2096 break;
2097 }
2098
2099 break;
2100 }
2101 default:
2102 {
2103 AssertMsgFailed(("Something weird happened with register lookup routine\n"));
2104 break;
2105 }
2106 }
2107
2108 if (u32FIFOS)
2109 {
2110 LogFunc(("[SD%RU8]: Updating FIFOS to %RU32 bytes\n", 0, hdaSDFIFOSToBytes(u32FIFOS)));
2111 /** @todo Update internal stream state with new FIFOS. */
2112
2113 return hdaRegWriteU16(pThis, iReg, u32FIFOS);
2114 }
2115
2116 return VINF_SUCCESS;
2117}
2118
2119#ifdef IN_RING3
2120static int hdaSDFMTToStrmCfg(uint32_t u32SDFMT, PPDMAUDIOSTREAMCFG pCfg)
2121{
2122 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2123
2124# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
2125
2126 int rc = VINF_SUCCESS;
2127
2128 uint32_t u32Hz = (u32SDFMT & HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
2129 uint32_t u32HzMult = 1;
2130 uint32_t u32HzDiv = 1;
2131
2132 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
2133 {
2134 case 0: u32HzMult = 1; break;
2135 case 1: u32HzMult = 2; break;
2136 case 2: u32HzMult = 3; break;
2137 case 3: u32HzMult = 4; break;
2138 default:
2139 LogFunc(("Unsupported multiplier %x\n",
2140 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
2141 rc = VERR_NOT_SUPPORTED;
2142 break;
2143 }
2144 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
2145 {
2146 case 0: u32HzDiv = 1; break;
2147 case 1: u32HzDiv = 2; break;
2148 case 2: u32HzDiv = 3; break;
2149 case 3: u32HzDiv = 4; break;
2150 case 4: u32HzDiv = 5; break;
2151 case 5: u32HzDiv = 6; break;
2152 case 6: u32HzDiv = 7; break;
2153 case 7: u32HzDiv = 8; break;
2154 default:
2155 LogFunc(("Unsupported divisor %x\n",
2156 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
2157 rc = VERR_NOT_SUPPORTED;
2158 break;
2159 }
2160
2161 PDMAUDIOFMT enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
2162 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
2163 {
2164 case 0:
2165 LogFunc(("Requested 8-bit\n"));
2166 enmFmt = AUD_FMT_S8;
2167 break;
2168 case 1:
2169 LogFunc(("Requested 16-bit\n"));
2170 enmFmt = AUD_FMT_S16;
2171 break;
2172 case 2:
2173 LogFunc(("Requested 20-bit\n"));
2174 break;
2175 case 3:
2176 LogFunc(("Requested 24-bit\n"));
2177 break;
2178 case 4:
2179 LogFunc(("Requested 32-bit\n"));
2180 enmFmt = AUD_FMT_S32;
2181 break;
2182 default:
2183 AssertMsgFailed(("Unsupported bits shift %x\n",
2184 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
2185 rc = VERR_NOT_SUPPORTED;
2186 break;
2187 }
2188
2189 if (RT_SUCCESS(rc))
2190 {
2191 pCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
2192 pCfg->cChannels = (u32SDFMT & 0xf) + 1;
2193 pCfg->enmFormat = enmFmt;
2194 pCfg->enmEndianness = PDMAUDIOHOSTENDIANNESS;
2195 }
2196
2197# undef EXTRACT_VALUE
2198
2199 LogFlowFuncLeaveRC(rc);
2200 return rc;
2201}
2202#endif
2203
2204static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2205{
2206#ifdef IN_RING3
2207# ifdef VBOX_WITH_HDA_CODEC_EMU
2208 /* No reason to re-open stream with same settings. */
2209 if (u32Value == HDA_REG_IND(pThis, iReg))
2210 return VINF_SUCCESS;
2211
2212 PDMAUDIOSTREAMCFG strmCfg;
2213 int rc = hdaSDFMTToStrmCfg(u32Value, &strmCfg);
2214 if (RT_FAILURE(rc))
2215 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2216
2217 uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, FMT, iReg);
2218
2219 PHDADRIVER pDrv;
2220 switch (iReg)
2221 {
2222 case HDA_REG_SD0FMT:
2223 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2224 rc = hdaCodecOpenStream(pThis->pCodec, PI_INDEX, &strmCfg);
2225 break;
2226# ifdef VBOX_WITH_HDA_MIC_IN
2227 case HDA_REG_SD2FMT:
2228 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2229 rc = hdaCodecOpenStream(pThis->pCodec, MC_INDEX, &strmCfg);
2230 break;
2231# endif
2232 case HDA_REG_SD4FMT:
2233 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2234 rc = hdaCodecOpenStream(pThis->pCodec, PO_INDEX, &strmCfg);
2235 break;
2236 default:
2237 LogFunc(("Warning: Changing SDFMT on non-attached stream with ID=%RU8 (iReg=0x%x)\n", u8Strm, iReg));
2238 break;
2239 }
2240
2241 /** @todo r=andy rc gets lost; needs fixing. */
2242 return hdaRegWriteU16(pThis, iReg, u32Value);
2243# else /* !VBOX_WITH_HDA_CODEC_EMU */
2244 return hdaRegWriteU16(pThis, iReg, u32Value);
2245# endif
2246#else /* !IN_RING3 */
2247 return VINF_IOM_R3_MMIO_WRITE;
2248#endif
2249}
2250
2251/* Note: Will be called for both, BDPL and BDPU, registers. */
2252DECLINLINE(int) hdaRegWriteSDBDPX(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t u8Strm)
2253{
2254 if (!hdaRegWriteSDIsAllowed(pThis, iReg, u32Value))
2255 return VINF_SUCCESS;
2256
2257 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2258 if (RT_SUCCESS(rc))
2259 {
2260 PHDASTREAM pStrmSt = hdaStreamFromID(pThis, u8Strm);
2261 if (pStrmSt)
2262 {
2263 pStrmSt->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
2264 HDA_STREAM_REG(pThis, BDPU, u8Strm));
2265 /* Reset BDLE state. */
2266 RT_ZERO(pStrmSt->State.BDLE);
2267 pStrmSt->State.uCurBDLE = 0;
2268 }
2269 }
2270 else
2271 AssertRCReturn(rc, VINF_SUCCESS);
2272
2273 return rc;
2274}
2275
2276static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2277{
2278 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPL, iReg));
2279}
2280
2281static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2282{
2283 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPU, iReg));
2284}
2285
2286/**
2287 * Checks whether a write to a specific SDnXXX register is allowed or not.
2288 *
2289 * @return bool Returns @true if write is allowed, @false if not.
2290 * @param pThis Pointer to HDA state.
2291 * @param iReg Register to write.
2292 * @param u32Value Value to write.
2293 */
2294inline bool hdaRegWriteSDIsAllowed(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2295{
2296 /* Check if the SD's RUN bit is set. */
2297 bool fIsRunning = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2298 if (fIsRunning)
2299 {
2300#ifdef VBOX_STRICT
2301 AssertMsgFailed(("[SD%RU8]: Cannot write to register 0x%x (0x%x) when RUN bit is set\n",
2302 HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), iReg, u32Value));
2303#endif
2304 return false;
2305 }
2306
2307 return true;
2308}
2309
2310static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2311{
2312 int rc = VINF_SUCCESS;
2313 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2314 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2315 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
2316 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2317
2318 rc = hdaRegReadU32(pThis, iReg, pu32Value);
2319 return rc;
2320}
2321
2322static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2323{
2324 int rc = VINF_SUCCESS;
2325
2326 /*
2327 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
2328 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
2329 */
2330 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
2331 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
2332 {
2333#ifdef IN_RING3
2334 PFNHDACODECVERBPROCESSOR pfn = NULL;
2335 uint64_t resp;
2336 uint32_t cmd = HDA_REG(pThis, IC);
2337 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
2338 {
2339 /*
2340 * 3.4.3 defines behavior of immediate Command status register.
2341 */
2342 LogRel(("guest attempted process immediate verb (%x) with active CORB\n", cmd));
2343 return rc;
2344 }
2345 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2346 LogFunc(("IC:%x\n", cmd));
2347
2348 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
2349 HDA_CODEC_CMD(cmd, 0 /* LUN */),
2350 &pfn);
2351 if (RT_FAILURE(rc))
2352 AssertRCReturn(rc, rc);
2353 rc = pfn(pThis->pCodec,
2354 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
2355 if (RT_FAILURE(rc))
2356 AssertRCReturn(rc, rc);
2357
2358 HDA_REG(pThis, IR) = (uint32_t)resp;
2359 LogFunc(("IR:%x\n", HDA_REG(pThis, IR)));
2360 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
2361 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
2362#else /* !IN_RING3 */
2363 rc = VINF_IOM_R3_MMIO_WRITE;
2364#endif
2365 return rc;
2366 }
2367 /*
2368 * Once the guest read the response, it should clean the IRV bit of the IRS register.
2369 */
2370 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
2371 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
2372 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
2373 return rc;
2374}
2375
2376static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2377{
2378 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
2379 {
2380 HDA_REG(pThis, RIRBWP) = 0;
2381 }
2382 /* The remaining bits are O, see 6.2.22 */
2383 return VINF_SUCCESS;
2384}
2385
2386static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2387{
2388 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2389 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2390 if (RT_FAILURE(rc))
2391 AssertRCReturn(rc, rc);
2392
2393 switch(iReg)
2394 {
2395 case HDA_REG_CORBLBASE:
2396 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
2397 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
2398 break;
2399 case HDA_REG_CORBUBASE:
2400 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
2401 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2402 break;
2403 case HDA_REG_RIRBLBASE:
2404 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
2405 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
2406 break;
2407 case HDA_REG_RIRBUBASE:
2408 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
2409 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2410 break;
2411 case HDA_REG_DPLBASE:
2412 {
2413 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
2414 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
2415
2416 /* Also make sure to handle the DMA position enable bit. */
2417 pThis->fDMAPosition = pThis->au32Regs[iRegMem] & RT_BIT_32(0);
2418 LogRel(("HDA: %s DMA position buffer\n", pThis->fDMAPosition ? "Enabled" : "Disabled"));
2419 break;
2420 }
2421 case HDA_REG_DPUBASE:
2422 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
2423 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2424 break;
2425 default:
2426 AssertMsgFailed(("Invalid index\n"));
2427 break;
2428 }
2429
2430 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
2431 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
2432 return rc;
2433}
2434
2435static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2436{
2437 uint8_t v = HDA_REG(pThis, RIRBSTS);
2438 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
2439
2440 return hdaProcessInterrupt(pThis);
2441}
2442
2443#ifdef IN_RING3
2444#ifdef LOG_ENABLED
2445static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE)
2446{
2447 LogFlowFunc(("BDLEs @ 0x%x (%RU16):\n", u64BDLBase, cBDLE));
2448 if (!u64BDLBase)
2449 return;
2450
2451 uint32_t cbBDLE = 0;
2452 for (uint16_t i = 0; i < cBDLE; i++)
2453 {
2454 uint8_t bdle[16]; /** @todo Use a define. */
2455 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BDLBase + i * 16, bdle, 16); /** @todo Use a define. */
2456
2457 uint64_t addr = *(uint64_t *)bdle;
2458 uint32_t len = *(uint32_t *)&bdle[8];
2459 uint32_t ioc = *(uint32_t *)&bdle[12];
2460
2461 LogFlowFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
2462 i, addr, len, RT_BOOL(ioc & 0x1)));
2463
2464 cbBDLE += len;
2465 }
2466
2467 LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
2468
2469 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
2470 return;
2471
2472 LogFlowFunc(("DMA counters:\n"));
2473
2474 for (int i = 0; i < cBDLE; i++)
2475 {
2476 uint32_t uDMACnt;
2477 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
2478 &uDMACnt, sizeof(uDMACnt));
2479
2480 LogFlowFunc(("\t#%03d DMA @ 0x%x\n", i , uDMACnt));
2481 }
2482}
2483#endif
2484
2485/**
2486 * Fetches a Bundle Descriptor List Entry (BDLE) from the DMA engine.
2487 *
2488 * @param pThis Pointer to HDA state.
2489 * @param pBDLE Where to store the fetched result.
2490 * @param u64BaseDMA Address base of DMA engine to use.
2491 * @param u16Entry BDLE entry to fetch.
2492 */
2493static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry)
2494{
2495 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2496 AssertPtrReturn(pBDLE, VERR_INVALID_POINTER);
2497 AssertReturn(u64BaseDMA, VERR_INVALID_PARAMETER);
2498 /** @todo Compare u16Entry with LVI. */
2499
2500 uint8_t uBundleEntry[16]; /** @todo Define a BDLE length. */
2501 int rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + u16Entry * 16, /** @todo Define a BDLE length. */
2502 uBundleEntry, RT_ELEMENTS(uBundleEntry));
2503 if (RT_FAILURE(rc))
2504 return rc;
2505
2506 RT_BZERO(pBDLE, sizeof(HDABDLE));
2507
2508 pBDLE->State.u32BDLIndex = u16Entry;
2509 pBDLE->u64BufAdr = *(uint64_t *) uBundleEntry;
2510 pBDLE->u32BufSize = *(uint32_t *)&uBundleEntry[8];
2511 if (pBDLE->u32BufSize < sizeof(uint16_t)) /* Must be at least one word. */
2512 return VERR_INVALID_STATE;
2513
2514 pBDLE->fIntOnCompletion = (*(uint32_t *)&uBundleEntry[12]) & 0x1;
2515
2516 return VINF_SUCCESS;
2517}
2518
2519/**
2520 * Returns the number of outstanding stream data bytes which need to be processed
2521 * by the DMA engine assigned to this stream.
2522 *
2523 * @return Number of bytes for the DMA engine to process.
2524 */
2525DECLINLINE(uint32_t) hdaStreamGetTransferSize(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t cbMax)
2526{
2527 AssertPtrReturn(pThis, 0);
2528 AssertPtrReturn(pStrmSt, 0);
2529
2530 if (!cbMax)
2531 return 0;
2532
2533 PHDABDLE pBDLE = &pStrmSt->State.BDLE;
2534
2535 uint32_t cbFree = pStrmSt->u32CBL - HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2536 if (cbFree)
2537 {
2538 /* Limit to the available free space of the current BDLE. */
2539 cbFree = RT_MIN(cbFree, pBDLE->u32BufSize - pBDLE->State.u32BufOff);
2540
2541 /* Make sure we only copy as much as the stream's FIFO can hold (SDFIFOS, 18.2.39). */
2542 cbFree = RT_MIN(cbFree, pStrmSt->u16FIFOS);
2543
2544 /* Make sure we only transfer as many bytes as requested. */
2545 cbFree = RT_MIN(cbFree, cbMax);
2546
2547 if (pBDLE->State.cbBelowFIFOW)
2548 {
2549 /* Are we not going to reach (or exceed) the FIFO watermark yet with the data to copy?
2550 * No need to read data from DMA then. */
2551 if (cbFree > pBDLE->State.cbBelowFIFOW)
2552 {
2553 /* Subtract the amount of bytes that still would fit in the stream's FIFO
2554 * and therefore do not need to be processed by DMA. */
2555 cbFree -= pBDLE->State.cbBelowFIFOW;
2556 }
2557 }
2558 }
2559
2560 LogFlowFunc(("[SD%RU8]: CBL=%RU32, LPIB=%RU32, cbFree=%RU32, %R[bdle]\n", pStrmSt->u8Strm,
2561 pStrmSt->u32CBL, HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm), cbFree, pBDLE));
2562 return cbFree;
2563}
2564
2565DECLINLINE(void) hdaBDLEUpdate(PHDABDLE pBDLE, uint32_t cbData, uint32_t cbProcessed)
2566{
2567 AssertPtrReturnVoid(pBDLE);
2568
2569 if (!cbData || !cbProcessed)
2570 return;
2571
2572 /* Fewer than cbBelowFIFOW bytes were copied.
2573 * Probably we need to move the buffer, but it is rather hard to imagine a situation
2574 * where it might happen. */
2575 AssertMsg((cbProcessed == pBDLE->State.cbBelowFIFOW + cbData), /* we assume that we write the entire buffer including unreported bytes */
2576 ("cbProcessed=%RU32 != pBDLE->State.cbBelowFIFOW=%RU32 + cbData=%RU32\n",
2577 cbProcessed, pBDLE->State.cbBelowFIFOW, cbData));
2578
2579#if 0
2580 if ( pBDLE->State.cbBelowFIFOW
2581 && pBDLE->State.cbBelowFIFOW <= cbWritten)
2582 {
2583 LogFlowFunc(("BDLE(cbUnderFifoW:%RU32, off:%RU32, size:%RU32)\n",
2584 pBDLE->State.cbBelowFIFOW, pBDLE->State.u32BufOff, pBDLE->u32BufSize));
2585 }
2586#endif
2587
2588 pBDLE->State.cbBelowFIFOW -= RT_MIN(pBDLE->State.cbBelowFIFOW, cbProcessed);
2589 Assert(pBDLE->State.cbBelowFIFOW == 0);
2590
2591 /* We always increment the position of DMA buffer counter because we're always reading
2592 * into an intermediate buffer. */
2593 pBDLE->State.u32BufOff += cbData;
2594 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2595
2596 LogFlowFunc(("cbData=%RU32, cbProcessed=%RU32, %R[bdle]\n", cbData, cbProcessed, pBDLE));
2597}
2598
2599DECLINLINE(bool) hdaStreamNeedsNextBDLE(PHDASTATE pThis, PHDASTREAM pStrmSt)
2600{
2601 AssertPtrReturn(pThis, false);
2602 AssertPtrReturn(pStrmSt, false);
2603
2604 PHDABDLE pBDLE = &pStrmSt->State.BDLE;
2605 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2606
2607 /* Did we reach the CBL (Cyclic Buffer List) limit? */
2608 bool fCBLLimitReached = u32LPIB >= pStrmSt->u32CBL;
2609
2610 /* Do we need to use the next BDLE entry? Either because we reached
2611 * the CBL limit or our internal DMA buffer is full. */
2612 bool fNeedsNextBDLE = ( fCBLLimitReached
2613 || (pBDLE->State.u32BufOff >= pBDLE->u32BufSize));
2614
2615 Assert(u32LPIB <= pStrmSt->u32CBL);
2616 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2617
2618 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32, fCBLLimitReached=%RTbool, fNeedsNextBDLE=%RTbool, %R[bdle]\n",
2619 pStrmSt->u8Strm, u32LPIB, pStrmSt->u32CBL, fCBLLimitReached, fNeedsNextBDLE, pBDLE));
2620
2621 if (fCBLLimitReached)
2622 {
2623 /* Reset LPIB register. */
2624 u32LPIB -= RT_MIN(u32LPIB, pStrmSt->u32CBL);
2625 hdaStreamUpdateLPIB(pThis, pStrmSt, u32LPIB);
2626 }
2627
2628 return fNeedsNextBDLE;
2629}
2630
2631DECLINLINE(void) hdaStreamTransferUpdate(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t cbInc)
2632{
2633 AssertPtrReturnVoid(pThis);
2634 AssertPtrReturnVoid(pStrmSt);
2635
2636 LogFlowFunc(("[SD%RU8]: cbInc=%RU32\n", pStrmSt->u8Strm, cbInc));
2637
2638 Assert(cbInc <= pStrmSt->u16FIFOS);
2639
2640 PHDABDLE pBDLE = &pStrmSt->State.BDLE;
2641
2642 /*
2643 * If we're below the FIFO watermark (SDFIFOW), it's expected that HDA
2644 * doesn't fetch anything via DMA, so just update LPIB.
2645 * (ICH6 datasheet 18.2.38).
2646 */
2647 if (pBDLE->State.cbBelowFIFOW == 0) /* Did we hit (or exceed) the watermark? */
2648 {
2649 const uint32_t u32LPIB = RT_MIN(HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) + cbInc,
2650 pStrmSt->u32CBL);
2651
2652 LogFlowFunc(("[SD%RU8]: LPIB: %RU32 -> %RU32, CBL=%RU32\n",
2653 pStrmSt->u8Strm,
2654 HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm), HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm) + cbInc,
2655 pStrmSt->u32CBL));
2656
2657 hdaStreamUpdateLPIB(pThis, pStrmSt, u32LPIB);
2658 }
2659}
2660
2661static bool hdaStreamTransferIsComplete(PHDASTATE pThis, PHDASTREAM pStrmSt)
2662{
2663 AssertPtrReturn(pThis, true);
2664 AssertPtrReturn(pStrmSt, true);
2665
2666 bool fIsComplete = false;
2667
2668 PHDABDLE pBDLE = &pStrmSt->State.BDLE;
2669 const uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStrmSt->u8Strm);
2670
2671 if ( pBDLE->State.u32BufOff >= pBDLE->u32BufSize
2672 || u32LPIB >= pStrmSt->u32CBL)
2673 {
2674 Assert(pBDLE->State.u32BufOff <= pBDLE->u32BufSize);
2675 Assert(u32LPIB <= pStrmSt->u32CBL);
2676
2677 if (/* IOC (Interrupt On Completion) bit set? */
2678 pBDLE->fIntOnCompletion
2679 /* All data put into the DMA FIFO? */
2680 && pBDLE->State.cbBelowFIFOW == 0
2681 )
2682 {
2683 /**
2684 * Set the BCIS (Buffer Completion Interrupt Status) flag as the
2685 * last byte of data for the current descriptor has been fetched
2686 * from memory and put into the DMA FIFO.
2687 *
2688 ** @todo More carefully investigate BCIS flag.
2689 *
2690 * Speech synthesis works fine on Mac Guest if this bit isn't set
2691 * but in general sound quality gets worse.
2692 */
2693 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
2694
2695 /*
2696 * If the ICE (IOCE, "Interrupt On Completion Enable") bit of the SDCTL register is set
2697 * we need to generate an interrupt.
2698 */
2699 if (HDA_STREAM_REG(pThis, CTL, pStrmSt->u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
2700 hdaProcessInterrupt(pThis);
2701 }
2702
2703 fIsComplete = true;
2704 }
2705
2706 LogFlowFunc(("[SD%RU8]: u32LPIB=%RU32, CBL=%RU32, %R[bdle] => %s\n",
2707 pStrmSt->u8Strm, u32LPIB, pStrmSt->u32CBL, pBDLE, fIsComplete ? "COMPLETE" : "INCOMPLETE"));
2708
2709 return fIsComplete;
2710}
2711
2712/**
2713 * hdaReadAudio - copies samples from audio backend to DMA.
2714 * Note: This function writes to the DMA buffer immediately,
2715 * but "reports bytes" when all conditions are met (FIFOW).
2716 */
2717static int hdaReadAudio(PHDASTATE pThis, PHDASTREAM pStrmSt, PAUDMIXSINK pSink, uint32_t cbMax, uint32_t *pcbRead)
2718{
2719 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2720 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
2721 AssertPtrReturn(pSink, VERR_INVALID_POINTER);
2722 /* pcbRead is optional. */
2723
2724 PHDABDLE pBDLE = &pStrmSt->State.BDLE;
2725
2726 int rc;
2727 uint32_t cbRead = 0;
2728 uint32_t cbBuf = hdaStreamGetTransferSize(pThis, pStrmSt, cbMax);
2729
2730 LogFlowFunc(("cbBuf=%RU32, %R[bdle]\n", cbBuf, pBDLE));
2731
2732 if (!cbBuf)
2733 {
2734 /* Nothing to write, bail out. */
2735 rc = VINF_EOF;
2736 }
2737 else
2738 {
2739 rc = AudioMixerProcessSinkIn(pSink, AUDMIXOP_BLEND, pBDLE->State.au8FIFO, cbBuf, &cbRead);
2740 if (RT_SUCCESS(rc))
2741 {
2742 Assert(cbRead);
2743 Assert(cbRead == cbBuf);
2744 Assert(cbRead <= pBDLE->u32BufSize - pBDLE->State.u32BufOff);
2745
2746 /*
2747 * Write to the BDLE's DMA buffer.
2748 */
2749 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2750 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
2751 pBDLE->State.au8FIFO, cbRead);
2752 AssertRC(rc);
2753
2754 if (pBDLE->State.cbBelowFIFOW + cbRead > hdaStreamGetFIFOW(pThis, pStrmSt))
2755 {
2756 pBDLE->State.u32BufOff += cbRead;
2757 pBDLE->State.cbBelowFIFOW = 0;
2758 //hdaBackendReadTransferReported(pBDLE, cbDMAData, cbRead, &cbRead, pcbAvail);
2759 }
2760 else
2761 {
2762 pBDLE->State.u32BufOff += cbRead;
2763 pBDLE->State.cbBelowFIFOW += cbRead;
2764 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStrmSt));
2765 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbRead, pcbAvail);
2766
2767 rc = VERR_NO_DATA;
2768 }
2769 }
2770 }
2771
2772 Assert(cbRead <= pStrmSt->u16FIFOS);
2773
2774 if (RT_SUCCESS(rc))
2775 {
2776 if (pcbRead)
2777 *pcbRead = cbRead;
2778 }
2779
2780 LogFunc(("Returning cbRead=%RU32, rc=%Rrc\n", cbRead, rc));
2781 return rc;
2782}
2783
2784static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAM pStrmSt, uint32_t cbMax, uint32_t *pcbWritten)
2785{
2786 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2787 AssertPtrReturn(pStrmSt, VERR_INVALID_POINTER);
2788 AssertPtrReturn(pcbWritten, VERR_INVALID_POINTER);
2789 /* pcbWritten is optional. */
2790
2791 PHDABDLE pBDLE = &pStrmSt->State.BDLE;
2792
2793 uint32_t cbWritten = 0;
2794 uint32_t cbData = hdaStreamGetTransferSize(pThis, pStrmSt, cbMax);
2795
2796 LogFlowFunc(("cbData=%RU32, %R[bdle]\n", cbData, pBDLE));
2797
2798 /*
2799 * Copy from DMA to the corresponding stream buffer (if there are any bytes from the
2800 * previous unreported transfer we write at offset 'pBDLE->State.cbUnderFifoW').
2801 */
2802 int rc;
2803 if (!cbData)
2804 {
2805 rc = VINF_EOF;
2806 }
2807 else
2808 {
2809 /*
2810 * Read from the current BDLE's DMA buffer.
2811 */
2812 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2813 pBDLE->u64BufAdr + pBDLE->State.u32BufOff,
2814 pBDLE->State.au8FIFO + pBDLE->State.cbBelowFIFOW, cbData);
2815 AssertRC(rc);
2816
2817#ifdef VBOX_WITH_STATISTICS
2818 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbData);
2819#endif
2820 /*
2821 * Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
2822 */
2823 uint32_t cbToWrite = cbData + pBDLE->State.cbBelowFIFOW;
2824 if (cbToWrite >= hdaStreamGetFIFOW(pThis, pStrmSt))
2825 {
2826 uint32_t cbWrittenToStream;
2827 int rc2;
2828
2829 PHDADRIVER pDrv;
2830 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2831 {
2832 if (pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut))
2833 {
2834 rc2 = pDrv->pConnector->pfnWrite(pDrv->pConnector, pDrv->Out.pStrmOut,
2835 pBDLE->State.au8FIFO, cbToWrite, &cbWrittenToStream);
2836 if (RT_SUCCESS(rc2))
2837 {
2838 if (cbWrittenToStream < cbToWrite) /* Lagging behind? */
2839 LogFlowFunc(("\tLUN#%RU8: Warning: Only written %RU32 / %RU32 bytes, expect lags\n",
2840 pDrv->uLUN, cbWrittenToStream, cbToWrite));
2841 }
2842 }
2843 else /* Stream disabled, not fatal. */
2844 {
2845 cbWrittenToStream = 0;
2846 rc2 = VERR_NOT_AVAILABLE;
2847 /* Keep going. */
2848 }
2849
2850 LogFlowFunc(("\tLUN#%RU8: cbToWrite=%RU32, cbWrittenToStream=%RU32, rc=%Rrc\n",
2851 pDrv->uLUN, cbToWrite, cbWrittenToStream, rc2));
2852 }
2853
2854 /* Always report all data as being written;
2855 * backends who were not able to catch up have to deal with it themselves. */
2856 cbWritten = cbToWrite;
2857
2858 hdaBDLEUpdate(pBDLE, cbData, cbWritten);
2859 }
2860 else
2861 {
2862 pBDLE->State.u32BufOff += cbWritten;
2863 pBDLE->State.cbBelowFIFOW += cbWritten;
2864 Assert(pBDLE->State.cbBelowFIFOW <= hdaStreamGetFIFOW(pThis, pStrmSt));
2865
2866 /* Not enough bytes to be processed and reported, we'll try our luck next time around. */
2867 //hdaBackendTransferUnreported(pThis, pBDLE, pStreamDesc, cbAvail, NULL);
2868 rc = VINF_EOF;
2869 }
2870 }
2871
2872 Assert(cbWritten <= pStrmSt->u16FIFOS);
2873
2874 if (RT_SUCCESS(rc))
2875 {
2876 if (pcbWritten)
2877 *pcbWritten = cbWritten;
2878 }
2879
2880 LogFunc(("Returning cbWritten=%RU32, rc=%Rrc\n", cbWritten, rc));
2881 return rc;
2882}
2883
2884/**
2885 * @interface_method_impl{HDACODEC,pfnReset}
2886 */
2887static DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
2888{
2889 PHDASTATE pThis = pCodec->pHDAState;
2890 NOREF(pThis);
2891 return VINF_SUCCESS;
2892}
2893
2894
2895static DECLCALLBACK(void) hdaCloseIn(PHDASTATE pThis, PDMAUDIORECSOURCE enmRecSource)
2896{
2897 NOREF(pThis);
2898 NOREF(enmRecSource);
2899 LogFlowFuncEnter();
2900}
2901
2902static DECLCALLBACK(void) hdaCloseOut(PHDASTATE pThis)
2903{
2904 NOREF(pThis);
2905 LogFlowFuncEnter();
2906}
2907
2908static DECLCALLBACK(int) hdaOpenIn(PHDASTATE pThis,
2909 const char *pszName, PDMAUDIORECSOURCE enmRecSource,
2910 PPDMAUDIOSTREAMCFG pCfg)
2911{
2912 PAUDMIXSINK pSink;
2913
2914 switch (enmRecSource)
2915 {
2916# ifdef VBOX_WITH_HDA_MIC_IN
2917 case PDMAUDIORECSOURCE_MIC:
2918 pSink = pThis->pSinkMicIn;
2919 break;
2920# endif
2921 case PDMAUDIORECSOURCE_LINE_IN:
2922 pSink = pThis->pSinkLineIn;
2923 break;
2924 default:
2925 AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
2926 return VERR_NOT_SUPPORTED;
2927 }
2928
2929 int rc = VINF_SUCCESS;
2930 char *pszDesc;
2931
2932 PHDADRIVER pDrv;
2933 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2934 {
2935 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2936 {
2937 rc = VERR_NO_MEMORY;
2938 break;
2939 }
2940
2941 rc = pDrv->pConnector->pfnCreateIn(pDrv->pConnector, pszDesc, enmRecSource, pCfg, &pDrv->LineIn.pStrmIn);
2942 LogFlowFunc(("LUN#%RU8: Created input \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2943 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2944 {
2945 AudioMixerRemoveStream(pSink, pDrv->LineIn.phStrmIn);
2946 rc = AudioMixerAddStreamIn(pSink,
2947 pDrv->pConnector, pDrv->LineIn.pStrmIn,
2948 0 /* uFlags */, &pDrv->LineIn.phStrmIn);
2949 }
2950
2951 RTStrFree(pszDesc);
2952 }
2953
2954 LogFlowFuncLeaveRC(rc);
2955 return rc;
2956}
2957
2958static DECLCALLBACK(int) hdaOpenOut(PHDASTATE pThis,
2959 const char *pszName, PPDMAUDIOSTREAMCFG pCfg)
2960{
2961 int rc = VINF_SUCCESS;
2962 char *pszDesc;
2963
2964 PHDADRIVER pDrv;
2965 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2966 {
2967 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s (%RU32Hz, %RU8 %s)",
2968 pDrv->uLUN, pszName, pCfg->uHz, pCfg->cChannels, pCfg->cChannels > 1 ? "Channels" : "Channel") <= 0)
2969 {
2970 rc = VERR_NO_MEMORY;
2971 break;
2972 }
2973
2974 rc = pDrv->pConnector->pfnCreateOut(pDrv->pConnector, pszDesc, pCfg, &pDrv->Out.pStrmOut);
2975 LogFlowFunc(("LUN#%RU8: Created output \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2976 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2977 {
2978 AudioMixerRemoveStream(pThis->pSinkOutput, pDrv->Out.phStrmOut);
2979 rc = AudioMixerAddStreamOut(pThis->pSinkOutput,
2980 pDrv->pConnector, pDrv->Out.pStrmOut,
2981 0 /* uFlags */, &pDrv->Out.phStrmOut);
2982 }
2983
2984 RTStrFree(pszDesc);
2985 }
2986
2987 LogFlowFuncLeaveRC(rc);
2988 return rc;
2989}
2990
2991static DECLCALLBACK(int) hdaSetVolume(PHDASTATE pThis, ENMSOUNDSOURCE enmSource,
2992 bool fMute, uint8_t uVolLeft, uint8_t uVolRight)
2993{
2994 int rc = VINF_SUCCESS;
2995 PDMAUDIOVOLUME vol = { fMute, uVolLeft, uVolRight };
2996 PAUDMIXSINK pSink;
2997
2998 /* Convert the audio source to corresponding sink. */
2999 switch (enmSource)
3000 {
3001 case PO_INDEX:
3002 pSink = pThis->pSinkOutput;
3003 break;
3004 case PI_INDEX:
3005 pSink = pThis->pSinkLineIn;
3006 break;
3007 case MC_INDEX:
3008 pSink = pThis->pSinkMicIn;
3009 break;
3010 default:
3011 AssertFailedReturn(VERR_INVALID_PARAMETER);
3012 break;
3013 }
3014
3015 /* Set the volume. Codec already converted it to the correct range. */
3016 AudioMixerSetSinkVolume(pSink, &vol);
3017
3018 LogFlowFuncLeaveRC(rc);
3019 return rc;
3020}
3021
3022#ifndef VBOX_WITH_AUDIO_CALLBACKS
3023
3024static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3025{
3026 PHDASTATE pThis = (PHDASTATE)pvUser;
3027 Assert(pThis == PDMINS_2_DATA(pDevIns, PHDASTATE));
3028 AssertPtr(pThis);
3029
3030 STAM_PROFILE_START(&pThis->StatTimer, a);
3031
3032 uint32_t cbInMax = 0;
3033 uint32_t cbOutMin = UINT32_MAX;
3034
3035 PHDADRIVER pDrv;
3036
3037 uint64_t cTicksNow = TMTimerGet(pTimer);
3038 uint64_t cTicksElapsed = cTicksNow - pThis->uTimerTS;
3039 uint64_t cTicksPerSec = TMTimerGetFreq(pTimer);
3040
3041 pThis->uTimerTS = cTicksNow;
3042
3043 /*
3044 * Calculate the codec's (fixed) sampling rate.
3045 */
3046 AssertPtr(pThis->pCodec);
3047 PDMPCMPROPS codecStrmProps;
3048
3049 int rc = DrvAudioStreamCfgToProps(&pThis->pCodec->strmCfg, &codecStrmProps);
3050 AssertRC(rc);
3051
3052 uint32_t cCodecSamplesMin = (int)((2 * cTicksElapsed * pThis->pCodec->strmCfg.uHz + cTicksPerSec) / cTicksPerSec / 2);
3053 uint32_t cbCodecSamplesMin = cCodecSamplesMin << codecStrmProps.cShift;
3054
3055 /*
3056 * Process all driver nodes.
3057 */
3058 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3059 {
3060 uint32_t cbIn = 0;
3061 uint32_t cbOut = 0;
3062
3063 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector, &cbIn, &cbOut, NULL /* pcSamplesLive */);
3064 if (RT_SUCCESS(rc))
3065 rc = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, NULL /* pcSamplesPlayed */);
3066
3067#ifdef DEBUG_TIMER
3068 LogFlowFunc(("LUN#%RU8: rc=%Rrc, cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, rc, cbIn, cbOut));
3069#endif
3070 /* If we there was an error handling (available) output or there simply is no output available,
3071 * then calculate the minimum data rate which must be processed by the device emulation in order
3072 * to function correctly.
3073 *
3074 * This is not the optimal solution, but as we have to deal with this on a timer-based approach
3075 * (until we have the audio callbacks) we need to have device' DMA engines running. */
3076 if (!pDrv->pConnector->pfnIsValidOut(pDrv->pConnector, pDrv->Out.pStrmOut))
3077 {
3078 /* Use the codec's (fixed) sampling rate. */
3079 cbOut = RT_MAX(cbOut, cbCodecSamplesMin);
3080 continue;
3081 }
3082
3083 const bool fIsActiveOut = pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut);
3084 if ( RT_FAILURE(rc)
3085 || !fIsActiveOut)
3086 {
3087 uint32_t cSamplesMin = (int)((2 * cTicksElapsed * pDrv->Out.pStrmOut->Props.uHz + cTicksPerSec) / cTicksPerSec / 2);
3088 uint32_t cbSamplesMin = AUDIOMIXBUF_S2B(&pDrv->Out.pStrmOut->MixBuf, cSamplesMin);
3089
3090#ifdef DEBUG_TIMER
3091 LogFlowFunc(("\trc=%Rrc, cSamplesMin=%RU32, cbSamplesMin=%RU32\n", rc, cSamplesMin, cbSamplesMin));
3092#endif
3093 cbOut = RT_MAX(cbOut, cbSamplesMin);
3094 }
3095
3096 cbOutMin = RT_MIN(cbOutMin, cbOut);
3097 cbInMax = RT_MAX(cbInMax, cbIn);
3098 }
3099
3100#ifdef DEBUG_TIMER
3101 LogFlowFunc(("cbInMax=%RU32, cbOutMin=%RU32\n", cbInMax, cbOutMin));
3102#endif
3103
3104 if (cbOutMin == UINT32_MAX)
3105 cbOutMin = 0;
3106
3107 /* Do the actual device transfers. */
3108 hdaTransfer(pThis, PO_INDEX, cbOutMin /* cbToProcess */, NULL /* pcbProcessed */);
3109 hdaTransfer(pThis, PI_INDEX, cbInMax /* cbToProcess */, NULL /* pcbProcessed */);
3110
3111 /* Kick the timer again. */
3112 uint64_t cTicks = pThis->cTimerTicks;
3113 /** @todo adjust cTicks down by now much cbOutMin represents. */
3114 TMTimerSet(pThis->pTimer, cTicksNow + cTicks);
3115
3116 STAM_PROFILE_STOP(&pThis->StatTimer, a);
3117}
3118
3119#else /* VBOX_WITH_AUDIO_CALLBACKS */
3120
3121static DECLCALLBACK(int) hdaCallbackInput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
3122{
3123 Assert(enmType == PDMAUDIOCALLBACKTYPE_INPUT);
3124 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
3125 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
3126 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
3127 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
3128
3129 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
3130 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
3131
3132 PPDMAUDIOCALLBACKDATAIN pData = (PPDMAUDIOCALLBACKDATAIN)pvUser;
3133 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAIN), VERR_INVALID_PARAMETER);
3134
3135 return hdaTransfer(pCtx->pThis, PI_INDEX, UINT32_MAX, &pData->cbOutRead);
3136}
3137
3138static DECLCALLBACK(int) hdaCallbackOutput(PDMAUDIOCALLBACKTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
3139{
3140 Assert(enmType == PDMAUDIOCALLBACKTYPE_OUTPUT);
3141 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
3142 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
3143 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
3144 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
3145
3146 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
3147 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
3148
3149 PPDMAUDIOCALLBACKDATAOUT pData = (PPDMAUDIOCALLBACKDATAOUT)pvUser;
3150 AssertReturn(cbUser == sizeof(PDMAUDIOCALLBACKDATAOUT), VERR_INVALID_PARAMETER);
3151
3152 PHDASTATE pThis = pCtx->pThis;
3153
3154 int rc = hdaTransfer(pCtx->pThis, PO_INDEX, UINT32_MAX, &pData->cbOutWritten);
3155 if ( RT_SUCCESS(rc)
3156 && pData->cbOutWritten)
3157 {
3158 PHDADRIVER pDrv;
3159 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3160 {
3161 uint32_t cSamplesPlayed;
3162 int rc2 = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, &cSamplesPlayed);
3163 LogFlowFunc(("LUN#%RU8: cSamplesPlayed=%RU32, rc=%Rrc\n", pDrv->uLUN, cSamplesPlayed, rc2));
3164 }
3165 }
3166}
3167#endif /* VBOX_WITH_AUDIO_CALLBACKS */
3168
3169static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t cbToProcess, uint32_t *pcbProcessed)
3170{
3171 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3172 /* pcbProcessed is optional. */
3173
3174 if (ASMAtomicReadBool(&pThis->fInReset)) /* HDA controller in reset mode? Bail out. */
3175 {
3176 LogFlowFunc(("In reset mode, skipping\n"));
3177
3178 if (pcbProcessed)
3179 *pcbProcessed = 0;
3180 return VINF_SUCCESS;
3181 }
3182
3183 PHDASTREAM pStrmSt;
3184 switch (enmSrc)
3185 {
3186 case PI_INDEX:
3187 {
3188 pStrmSt = &pThis->StrmStLineIn;
3189 break;
3190 }
3191
3192#ifdef VBOX_WITH_HDA_MIC_IN
3193 case MC_INDEX:
3194 {
3195 pStrmSt = &pThis->StrmStMicIn;
3196 break;
3197 }
3198#endif
3199 case PO_INDEX:
3200 {
3201 pStrmSt = &pThis->StrmStOut;
3202 break;
3203 }
3204
3205 default:
3206 {
3207 AssertMsgFailed(("Unknown source index %ld\n", enmSrc));
3208 return VERR_NOT_SUPPORTED;
3209 }
3210 }
3211
3212 int rc = VINF_SUCCESS;
3213 bool fProceed = true;
3214
3215 /* Stop request received? */
3216 if (ASMAtomicReadBool(&pStrmSt->State.fDoStop))
3217 {
3218 pStrmSt->State.fActive = false;
3219
3220 rc = RTSemEventSignal(pStrmSt->State.hStateChangedEvent);
3221 AssertRC(rc);
3222
3223 fProceed = false;
3224 }
3225 /* Is the stream not in a running state currently? */
3226 else if (!(HDA_STREAM_REG(pThis, CTL, pStrmSt->u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)))
3227 fProceed = false;
3228 /* Nothing to process? */
3229 else if (!cbToProcess)
3230 fProceed = false;
3231
3232 if (!fProceed)
3233 {
3234 if (pcbProcessed)
3235 *pcbProcessed = 0;
3236 return VINF_SUCCESS;
3237 }
3238
3239 LogFlowFunc(("enmSrc=%RU32, cbToProcess=%RU32\n", enmSrc, cbToProcess));
3240
3241 /* Sanity checks. */
3242 Assert(pStrmSt->u8Strm <= 7); /** @todo Use a define for MAX_STREAMS! */
3243 Assert(pStrmSt->u64BDLBase);
3244 Assert(pStrmSt->u32CBL);
3245
3246 /* State sanity checks. */
3247 Assert(ASMAtomicReadBool(&pStrmSt->State.fInReset) == false);
3248
3249 uint32_t cbProcessedTotal = 0;
3250 bool fIsComplete = false;
3251
3252 while (cbToProcess)
3253 {
3254 /* Do we need to fetch the next Buffer Descriptor Entry (BDLE)? */
3255 if (hdaStreamNeedsNextBDLE(pThis, pStrmSt))
3256 hdaStreamGetNextBDLE(pThis, pStrmSt);
3257
3258 /* Set the FIFORDY bit on the stream while doing the transfer. */
3259 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
3260
3261 uint32_t cbProcessed;
3262 switch (enmSrc)
3263 {
3264 case PI_INDEX:
3265 rc = hdaReadAudio(pThis, pStrmSt, pThis->pSinkLineIn, cbToProcess, &cbProcessed);
3266 break;
3267 case PO_INDEX:
3268 rc = hdaWriteAudio(pThis, pStrmSt, cbToProcess, &cbProcessed);
3269 break;
3270#ifdef VBOX_WITH_HDA_MIC_IN
3271 case MC_INDEX:
3272 rc = hdaReadAudio(pThis, pStrmSt, pThis->pSinkMicIn, cbToProcess, &cbProcessed);
3273 break;
3274#endif
3275 default:
3276 AssertMsgFailed(("Unsupported source index %ld\n", enmSrc));
3277 rc = VERR_NOT_SUPPORTED;
3278 break;
3279 }
3280
3281 /* Remove the FIFORDY bit again. */
3282 HDA_STREAM_REG(pThis, STS, pStrmSt->u8Strm) &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
3283
3284 if (RT_FAILURE(rc))
3285 break;
3286
3287 hdaStreamTransferUpdate(pThis, pStrmSt, cbProcessed);
3288
3289 cbToProcess -= RT_MIN(cbToProcess, cbProcessed);
3290 cbProcessedTotal += cbProcessed;
3291
3292 LogFlowFunc(("cbProcessed=%RU32, cbToProcess=%RU32, cbProcessedTotal=%RU32, rc=%Rrc\n",
3293 cbProcessed, cbToProcess, cbProcessedTotal, rc));
3294
3295 if (rc == VINF_EOF)
3296 fIsComplete = true;
3297
3298 if (!fIsComplete)
3299 fIsComplete = hdaStreamTransferIsComplete(pThis, pStrmSt);
3300
3301 if (fIsComplete)
3302 break;
3303 }
3304
3305 if (RT_SUCCESS(rc))
3306 {
3307 if (pcbProcessed)
3308 *pcbProcessed = cbProcessedTotal;
3309 }
3310
3311 LogFlowFuncLeaveRC(rc);
3312 return rc;
3313}
3314#endif /* IN_RING3 */
3315
3316/* MMIO callbacks */
3317
3318/**
3319 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
3320 *
3321 * @note During implementation, we discovered so-called "forgotten" or "hole"
3322 * registers whose description is not listed in the RPM, datasheet, or
3323 * spec.
3324 */
3325PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3326{
3327 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3328 int rc;
3329
3330 /*
3331 * Look up and log.
3332 */
3333 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3334 int idxRegDsc = hdaRegLookup(pThis, offReg); /* Register descriptor index. */
3335#ifdef LOG_ENABLED
3336 unsigned const cbLog = cb;
3337 uint32_t offRegLog = offReg;
3338#endif
3339
3340 LogFunc(("offReg=%#x cb=%#x\n", offReg, cb));
3341 Assert(cb == 4); Assert((offReg & 3) == 0);
3342
3343 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
3344 LogFunc(("\tAccess to registers except GCTL is blocked while reset\n"));
3345
3346 if (idxRegDsc == -1)
3347 LogRel(("HDA: Invalid read access @0x%x (bytes=%d)\n", offReg, cb));
3348
3349 if (idxRegDsc != -1)
3350 {
3351 /* ASSUMES gapless DWORD at end of map. */
3352 if (g_aHdaRegMap[idxRegDsc].size == 4)
3353 {
3354 /*
3355 * Straight forward DWORD access.
3356 */
3357 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
3358 LogFunc(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
3359 }
3360 else
3361 {
3362 /*
3363 * Multi register read (unless there are trailing gaps).
3364 * ASSUMES that only DWORD reads have sideeffects.
3365 */
3366 uint32_t u32Value = 0;
3367 unsigned cbLeft = 4;
3368 do
3369 {
3370 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
3371 uint32_t u32Tmp = 0;
3372
3373 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
3374 LogFunc(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
3375 if (rc != VINF_SUCCESS)
3376 break;
3377 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
3378
3379 cbLeft -= cbReg;
3380 offReg += cbReg;
3381 idxRegDsc++;
3382 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
3383
3384 if (rc == VINF_SUCCESS)
3385 *(uint32_t *)pv = u32Value;
3386 else
3387 Assert(!IOM_SUCCESS(rc));
3388 }
3389 }
3390 else
3391 {
3392 rc = VINF_IOM_MMIO_UNUSED_FF;
3393 LogFunc(("\tHole at %x is accessed for read\n", offReg));
3394 }
3395
3396 /*
3397 * Log the outcome.
3398 */
3399#ifdef LOG_ENABLED
3400 if (cbLog == 4)
3401 LogFunc(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
3402 else if (cbLog == 2)
3403 LogFunc(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
3404 else if (cbLog == 1)
3405 LogFunc(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
3406#endif
3407 return rc;
3408}
3409
3410
3411DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
3412{
3413 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
3414 {
3415 LogRel2(("HDA: Access to register 0x%x is blocked while reset\n", idxRegDsc));
3416 return VINF_SUCCESS;
3417 }
3418
3419 uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3420#ifdef LOG_ENABLED
3421 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
3422#endif
3423 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
3424 LogFunc(("write %#x -> %s[%db]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
3425 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
3426 return rc;
3427}
3428
3429
3430/**
3431 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
3432 */
3433PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
3434{
3435 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3436 int rc;
3437
3438 /*
3439 * The behavior of accesses that aren't aligned on natural boundraries is
3440 * undefined. Just reject them outright.
3441 */
3442 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
3443 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
3444 if (GCPhysAddr & (cb - 1))
3445 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
3446
3447 /*
3448 * Look up and log the access.
3449 */
3450 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3451 int idxRegDsc = hdaRegLookup(pThis, offReg);
3452 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
3453 uint64_t u64Value;
3454 if (cb == 4) u64Value = *(uint32_t const *)pv;
3455 else if (cb == 2) u64Value = *(uint16_t const *)pv;
3456 else if (cb == 1) u64Value = *(uint8_t const *)pv;
3457 else if (cb == 8) u64Value = *(uint64_t const *)pv;
3458 else
3459 {
3460 u64Value = 0; /* shut up gcc. */
3461 AssertReleaseMsgFailed(("%u\n", cb));
3462 }
3463
3464#ifdef LOG_ENABLED
3465 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
3466 if (idxRegDsc == -1)
3467 LogFunc(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
3468 else if (cb == 4)
3469 LogFunc(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
3470 else if (cb == 2)
3471 LogFunc(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
3472 else if (cb == 1)
3473 LogFunc(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
3474
3475 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
3476 LogFunc(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
3477#endif
3478
3479 /*
3480 * Try for a direct hit first.
3481 */
3482 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
3483 {
3484 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
3485#ifdef LOG_ENABLED
3486 LogFunc(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
3487#endif
3488 }
3489 /*
3490 * Partial or multiple register access, loop thru the requested memory.
3491 */
3492 else
3493 {
3494 /*
3495 * If it's an access beyond the start of the register, shift the input
3496 * value and fill in missing bits. Natural alignment rules means we
3497 * will only see 1 or 2 byte accesses of this kind, so no risk of
3498 * shifting out input values.
3499 */
3500 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(pThis, offReg)) != -1)
3501 {
3502 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
3503 offReg -= cbBefore;
3504 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3505 u64Value <<= cbBefore * 8;
3506 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
3507 LogFunc(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
3508 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
3509 }
3510
3511 /* Loop thru the write area, it may cover multiple registers. */
3512 rc = VINF_SUCCESS;
3513 for (;;)
3514 {
3515 uint32_t cbReg;
3516 if (idxRegDsc != -1)
3517 {
3518 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3519 cbReg = g_aHdaRegMap[idxRegDsc].size;
3520 if (cb < cbReg)
3521 {
3522 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
3523 LogFunc(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
3524 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
3525 }
3526 uint32_t u32LogOldVal = pThis->au32Regs[idxRegMem];
3527 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
3528 LogFunc(("\t%#x -> %#x\n", u32LogOldVal, pThis->au32Regs[idxRegMem]));
3529 }
3530 else
3531 {
3532 LogRel(("HDA: Invalid write access @0x%x\n", offReg));
3533 cbReg = 1;
3534 }
3535 if (rc != VINF_SUCCESS)
3536 break;
3537 if (cbReg >= cb)
3538 break;
3539
3540 /* Advance. */
3541 offReg += cbReg;
3542 cb -= cbReg;
3543 u64Value >>= cbReg * 8;
3544 if (idxRegDsc == -1)
3545 idxRegDsc = hdaRegLookup(pThis, offReg);
3546 else
3547 {
3548 idxRegDsc++;
3549 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
3550 || g_aHdaRegMap[idxRegDsc].offset != offReg)
3551 {
3552 idxRegDsc = -1;
3553 }
3554 }
3555 }
3556 }
3557
3558 return rc;
3559}
3560
3561
3562/* PCI callback. */
3563
3564#ifdef IN_RING3
3565/**
3566 * @callback_method_impl{FNPCIIOREGIONMAP}
3567 */
3568static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
3569 PCIADDRESSSPACE enmType)
3570{
3571 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3572 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
3573 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
3574 int rc;
3575
3576 /*
3577 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
3578 *
3579 * Let IOM talk DWORDs when reading, saves a lot of complications. On
3580 * writing though, we have to do it all ourselves because of sideeffects.
3581 */
3582 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
3583 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
3584 IOMMMIO_FLAGS_READ_DWORD
3585 | IOMMMIO_FLAGS_WRITE_PASSTHRU,
3586 hdaMMIOWrite, hdaMMIORead, "HDA");
3587
3588 if (RT_FAILURE(rc))
3589 return rc;
3590
3591 if (pThis->fR0Enabled)
3592 {
3593 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
3594 "hdaMMIOWrite", "hdaMMIORead");
3595 if (RT_FAILURE(rc))
3596 return rc;
3597 }
3598
3599 if (pThis->fRCEnabled)
3600 {
3601 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
3602 "hdaMMIOWrite", "hdaMMIORead");
3603 if (RT_FAILURE(rc))
3604 return rc;
3605 }
3606
3607 pThis->MMIOBaseAddr = GCPhysAddress;
3608 return VINF_SUCCESS;
3609}
3610
3611
3612/* Saved state callbacks. */
3613
3614static int hdaSaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStrm)
3615{
3616 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3617
3618 LogFlowFunc(("[SD%RU8]\n", pStrm->u8Strm));
3619
3620 /* Save stream ID. */
3621 int rc = SSMR3PutU8(pSSM, pStrm->u8Strm);
3622 AssertRCReturn(rc, rc);
3623 Assert(pStrm->u8Strm <= 7); /** @todo Use a define. */
3624
3625 rc = SSMR3PutStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /*fFlags*/, g_aSSMStreamStateFields6, NULL);
3626 AssertRCReturn(rc, rc);
3627
3628#ifdef DEBUG /* Sanity checks. */
3629 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStrm->u8Strm),
3630 HDA_STREAM_REG(pThis, BDPU, pStrm->u8Strm));
3631 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStrm->u8Strm);
3632 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStrm->u8Strm);
3633
3634 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
3635
3636 Assert(u64BaseDMA == pStrm->u64BDLBase);
3637 Assert(u16LVI == pStrm->u16LVI);
3638 Assert(u32CBL == pStrm->u32CBL);
3639#endif
3640
3641 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE, sizeof(HDABDLE),
3642 0 /*fFlags*/, g_aSSMBDLEFields6, NULL);
3643 AssertRCReturn(rc, rc);
3644
3645 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
3646 0 /*fFlags*/, g_aSSMBDLEStateFields6, NULL);
3647 AssertRCReturn(rc, rc);
3648
3649#ifdef DEBUG /* Sanity checks. */
3650 PHDABDLE pBDLE = &pStrm->State.BDLE;
3651 if (u64BaseDMA)
3652 {
3653 Assert(pStrm->State.uCurBDLE <= u16LVI + 1);
3654
3655 HDABDLE curBDLE;
3656 rc = hdaBDLEFetch(pThis, &curBDLE, u64BaseDMA, pStrm->State.uCurBDLE);
3657 AssertRC(rc);
3658
3659 Assert(curBDLE.u32BufSize == pBDLE->u32BufSize);
3660 Assert(curBDLE.u64BufAdr == pBDLE->u64BufAdr);
3661 Assert(curBDLE.fIntOnCompletion == pBDLE->fIntOnCompletion);
3662 }
3663 else
3664 {
3665 Assert(pBDLE->u64BufAdr == 0);
3666 Assert(pBDLE->u32BufSize == 0);
3667 }
3668#endif
3669 return rc;
3670}
3671
3672/**
3673 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3674 */
3675static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3676{
3677 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3678
3679 /* Save Codec nodes states. */
3680 hdaCodecSaveState(pThis->pCodec, pSSM);
3681
3682 /* Save MMIO registers. */
3683 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3684 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3685 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3686
3687 /* Save number of streams. */
3688#ifdef VBOX_WITH_HDA_MIC_IN
3689 SSMR3PutU32(pSSM, 3);
3690#else
3691 SSMR3PutU32(pSSM, 2);
3692#endif
3693
3694 /* Save stream states. */
3695 int rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStOut);
3696 AssertRCReturn(rc, rc);
3697#ifdef VBOX_WITH_HDA_MIC_IN
3698 rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStMicIn);
3699 AssertRCReturn(rc, rc);
3700#endif
3701 rc = hdaSaveStream(pDevIns, pSSM, &pThis->StrmStLineIn);
3702 AssertRCReturn(rc, rc);
3703
3704 return rc;
3705}
3706
3707
3708/**
3709 * @callback_method_impl{FNSSMDEVLOADEXEC}
3710 */
3711static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3712{
3713 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3714
3715 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3716
3717 LogRel2(("hdaLoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
3718
3719 /*
3720 * Load Codec nodes states.
3721 */
3722 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
3723 if (RT_FAILURE(rc))
3724 {
3725 LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
3726 return rc;
3727 }
3728
3729 /*
3730 * Load MMIO registers.
3731 */
3732 uint32_t cRegs;
3733 switch (uVersion)
3734 {
3735 case HDA_SSM_VERSION_1:
3736 /* Starting with r71199, we would save 112 instead of 113
3737 registers due to some code cleanups. This only affected trunk
3738 builds in the 4.1 development period. */
3739 cRegs = 113;
3740 if (SSMR3HandleRevision(pSSM) >= 71199)
3741 {
3742 uint32_t uVer = SSMR3HandleVersion(pSSM);
3743 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3744 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3745 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3746 cRegs = 112;
3747 }
3748 break;
3749
3750 case HDA_SSM_VERSION_2:
3751 case HDA_SSM_VERSION_3:
3752 cRegs = 112;
3753 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3754 break;
3755
3756 /* Since version 4 we store the register count to stay flexible. */
3757 case HDA_SSM_VERSION_4:
3758 case HDA_SSM_VERSION_5:
3759 case HDA_SSM_VERSION:
3760 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3761 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3762 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3763 break;
3764
3765 default:
3766 LogRel(("HDA: Unsupported / too new saved state version (%RU32)\n", uVersion));
3767 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3768 }
3769
3770 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3771 {
3772 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3773 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3774 }
3775 else
3776 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3777
3778 /*
3779 * Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
3780 * *every* BDLE state, whereas it only needs to be stored
3781 * *once* for every stream. Most of the BDLE state we can
3782 * get out of the registers anyway, so just ignore those values.
3783 *
3784 * Also, only the current BDLE was saved, regardless whether
3785 * there were more than one (and there are at least two entries,
3786 * according to the spec).
3787 */
3788#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
3789 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
3790 AssertRCReturn(rc, rc); \
3791 rc = SSMR3GetU64(pSSM, &x.u64BufAdr); /* u64BdleCviAddr */ \
3792 AssertRCReturn(rc, rc); \
3793 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
3794 AssertRCReturn(rc, rc); \
3795 rc = SSMR3GetU32(pSSM, &x.State.u32BDLIndex); /* u32BdleCvi */ \
3796 AssertRCReturn(rc, rc); \
3797 rc = SSMR3GetU32(pSSM, &x.u32BufSize); /* u32BdleCviLen */ \
3798 AssertRCReturn(rc, rc); \
3799 rc = SSMR3GetU32(pSSM, &x.State.u32BufOff); /* u32BdleCviPos */ \
3800 AssertRCReturn(rc, rc); \
3801 rc = SSMR3GetBool(pSSM, &x.fIntOnCompletion); /* fBdleCviIoc */ \
3802 AssertRCReturn(rc, rc); \
3803 rc = SSMR3GetU32(pSSM, &x.State.cbBelowFIFOW); /* cbUnderFifoW */ \
3804 AssertRCReturn(rc, rc); \
3805 rc = SSMR3GetMem(pSSM, &x.State.au8FIFO, sizeof(x.State.au8FIFO)); \
3806 AssertRCReturn(rc, rc); \
3807 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
3808 AssertRCReturn(rc, rc); \
3809
3810 /*
3811 * Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3812 */
3813 switch (uVersion)
3814 {
3815 case HDA_SSM_VERSION_1:
3816 case HDA_SSM_VERSION_2:
3817 case HDA_SSM_VERSION_3:
3818 case HDA_SSM_VERSION_4:
3819 {
3820 /* Only load the internal states.
3821 * The rest will be initialized from the saved registers later. */
3822
3823 /* Note 1: Only the *current* BDLE for a stream was saved! */
3824 /* Note 2: The stream's saving order is/was fixed, so don't touch! */
3825
3826 /* Output */
3827 rc = hdaStreamInit(pThis, &pThis->StrmStOut, 4 /* Stream number, hardcoded */);
3828 if (RT_FAILURE(rc))
3829 break;
3830 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pThis->StrmStOut.State.BDLE);
3831 pThis->StrmStOut.State.uCurBDLE = pThis->StrmStOut.State.BDLE.State.u32BDLIndex;
3832
3833 /* Microphone-In */
3834 rc = hdaStreamInit(pThis, &pThis->StrmStMicIn, 2 /* Stream number, hardcoded */);
3835 if (RT_FAILURE(rc))
3836 break;
3837 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pThis->StrmStMicIn.State.BDLE);
3838 pThis->StrmStMicIn.State.uCurBDLE = pThis->StrmStMicIn.State.BDLE.State.u32BDLIndex;
3839
3840 /* Line-In */
3841 rc = hdaStreamInit(pThis, &pThis->StrmStLineIn, 0 /* Stream number, hardcoded */);
3842 if (RT_FAILURE(rc))
3843 break;
3844 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pThis->StrmStLineIn.State.BDLE);
3845 pThis->StrmStLineIn.State.uCurBDLE = pThis->StrmStLineIn.State.BDLE.State.u32BDLIndex;
3846 break;
3847 }
3848
3849 /* Since v5 we support flexible stream and BDLE counts. */
3850 case HDA_SSM_VERSION_5:
3851 case HDA_SSM_VERSION:
3852 {
3853 uint32_t cStreams;
3854 rc = SSMR3GetU32(pSSM, &cStreams);
3855 if (RT_FAILURE(rc))
3856 break;
3857
3858 LogRel2(("hdaLoadExec: cStreams=%RU32\n", cStreams));
3859
3860 /* Load stream states. */
3861 for (uint32_t i = 0; i < cStreams; i++)
3862 {
3863 uint8_t uStreamID;
3864 rc = SSMR3GetU8(pSSM, &uStreamID);
3865 if (RT_FAILURE(rc))
3866 break;
3867
3868 PHDASTREAM pStrm = hdaStreamFromID(pThis, uStreamID);
3869 HDASTREAM StreamDummy;
3870
3871 if (!pStrm)
3872 {
3873 pStrm = &StreamDummy;
3874 LogRel2(("HDA: Warning: Stream ID=%RU32 not supported, skipping to load ...\n", uStreamID));
3875 break;
3876 }
3877
3878 RT_BZERO(pStrm, sizeof(HDASTREAM));
3879
3880 rc = hdaStreamInit(pThis, pStrm, uStreamID);
3881 if (RT_FAILURE(rc))
3882 {
3883 LogRel(("HDA: Stream #%RU32: Initialization of stream %RU8 failed, rc=%Rrc\n", i, uStreamID, rc));
3884 break;
3885 }
3886
3887 if (uVersion == HDA_SSM_VERSION_5)
3888 {
3889 /* Get the current BDLE entry and skip the rest. */
3890 uint16_t cBDLE;
3891
3892 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
3893 AssertRC(rc);
3894 rc = SSMR3GetU16(pSSM, &cBDLE); /* cBDLE */
3895 AssertRC(rc);
3896 rc = SSMR3GetU16(pSSM, &pStrm->State.uCurBDLE); /* uCurBDLE */
3897 AssertRC(rc);
3898 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
3899 AssertRC(rc);
3900
3901 uint32_t u32BDLEIndex;
3902 for (uint16_t a = 0; a < cBDLE; a++)
3903 {
3904 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
3905 AssertRC(rc);
3906 rc = SSMR3GetU32(pSSM, &u32BDLEIndex); /* u32BDLIndex */
3907 AssertRC(rc);
3908
3909 /* Does the current BDLE index match the current BDLE to process? */
3910 if (u32BDLEIndex == pStrm->State.uCurBDLE)
3911 {
3912 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.cbBelowFIFOW); /* cbBelowFIFOW */
3913 AssertRC(rc);
3914 rc = SSMR3GetMem(pSSM,
3915 &pStrm->State.BDLE.State.au8FIFO,
3916 sizeof(pStrm->State.BDLE.State.au8FIFO)); /* au8FIFO */
3917 AssertRC(rc);
3918 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.u32BufOff); /* u32BufOff */
3919 AssertRC(rc);
3920 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
3921 AssertRC(rc);
3922 }
3923 else /* Skip not current BDLEs. */
3924 {
3925 rc = SSMR3Skip(pSSM, sizeof(uint32_t) /* cbBelowFIFOW */
3926 + sizeof(uint8_t) * 256 /* au8FIFO */
3927 + sizeof(uint32_t) /* u32BufOff */
3928 + sizeof(uint32_t)); /* End marker */
3929 AssertRC(rc);
3930 }
3931 }
3932 }
3933 else
3934 {
3935 rc = SSMR3GetStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE),
3936 0 /* fFlags */, g_aSSMStreamStateFields6, NULL);
3937 if (RT_FAILURE(rc))
3938 break;
3939
3940 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE, sizeof(HDABDLE),
3941 0 /* fFlags */, g_aSSMBDLEFields6, NULL);
3942 if (RT_FAILURE(rc))
3943 break;
3944
3945 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
3946 0 /* fFlags */, g_aSSMBDLEStateFields6, NULL);
3947 if (RT_FAILURE(rc))
3948 break;
3949 }
3950 }
3951 break;
3952 }
3953
3954 default:
3955 AssertReleaseFailed(); /* Never reached. */
3956 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3957 }
3958
3959#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
3960
3961 if (RT_SUCCESS(rc))
3962 {
3963 /*
3964 * Update stuff after the state changes.
3965 */
3966 bool fEnableIn = RT_BOOL(HDA_SDCTL(pThis, 0 /** @todo Use a define. */) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3967#ifdef VBOX_WITH_HDA_MIC_IN
3968 bool fEnableMicIn = RT_BOOL(HDA_SDCTL(pThis, 2 /** @todo Use a define. */) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3969#endif
3970 bool fEnableOut = RT_BOOL(HDA_SDCTL(pThis, 4 /** @todo Use a define. */) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3971
3972 PHDADRIVER pDrv;
3973 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3974 {
3975 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, fEnableIn);
3976 if (RT_FAILURE(rc))
3977 break;
3978#ifdef VBOX_WITH_HDA_MIC_IN
3979 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, fEnableMicIn);
3980 if (RT_FAILURE(rc))
3981 break;
3982#endif
3983 rc = pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, fEnableOut);
3984 if (RT_FAILURE(rc))
3985 break;
3986 }
3987 }
3988
3989 if (RT_SUCCESS(rc))
3990 {
3991 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3992 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3993 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
3994
3995 /* Also make sure to update the DMA position bit if this was enabled when saving the state. */
3996 pThis->fDMAPosition = RT_BOOL(HDA_REG(pThis, DPLBASE) & RT_BIT_32(0));
3997 }
3998 else
3999 LogRel(("HDA: Failed loading device state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
4000
4001 LogFlowFuncLeaveRC(rc);
4002 return rc;
4003}
4004
4005#ifdef DEBUG
4006/* Debug and log type formatters. */
4007
4008/**
4009 * @callback_method_impl{FNRTSTRFORMATTYPE}
4010 */
4011static DECLCALLBACK(size_t) hdaDbgFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4012 const char *pszType, void const *pvValue,
4013 int cchWidth, int cchPrecision, unsigned fFlags,
4014 void *pvUser)
4015{
4016 PHDABDLE pBDLE = (PHDABDLE)pvValue;
4017 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4018 "BDLE(idx:%RU32, off:%RU32, fifow:%RU32, DMA[%RU32 bytes @ 0x%x])",
4019 pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW, pBDLE->u32BufSize, pBDLE->u64BufAdr);
4020}
4021
4022/**
4023 * @callback_method_impl{FNRTSTRFORMATTYPE}
4024 */
4025static DECLCALLBACK(size_t) hdaDbgFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4026 const char *pszType, void const *pvValue,
4027 int cchWidth, int cchPrecision, unsigned fFlags,
4028 void *pvUser)
4029{
4030 uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
4031 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4032 "SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
4033 uSDCTL,
4034 (uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)) ? "OUT" : "IN",
4035 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
4036 (uSDCTL & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
4037 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
4038 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, FEIE)),
4039 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
4040 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
4041 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
4042}
4043
4044/**
4045 * @callback_method_impl{FNRTSTRFORMATTYPE}
4046 */
4047static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4048 const char *pszType, void const *pvValue,
4049 int cchWidth, int cchPrecision, unsigned fFlags,
4050 void *pvUser)
4051{
4052 uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
4053 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, hdaSDFIFOSToBytes(uSDFIFOS));
4054}
4055
4056/**
4057 * @callback_method_impl{FNRTSTRFORMATTYPE}
4058 */
4059static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4060 const char *pszType, void const *pvValue,
4061 int cchWidth, int cchPrecision, unsigned fFlags,
4062 void *pvUser)
4063{
4064 uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
4065 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
4066}
4067
4068/**
4069 * @callback_method_impl{FNRTSTRFORMATTYPE}
4070 */
4071static DECLCALLBACK(size_t) hdaDbgFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4072 const char *pszType, void const *pvValue,
4073 int cchWidth, int cchPrecision, unsigned fFlags,
4074 void *pvUser)
4075{
4076 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
4077 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4078 "SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
4079 uSdSts,
4080 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
4081 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
4082 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
4083 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
4084}
4085
4086static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
4087{
4088 int iReg = 0;
4089 for (; iReg < HDA_NREGS; ++iReg)
4090 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
4091 return iReg;
4092 return -1;
4093}
4094
4095
4096static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
4097{
4098 Assert( pThis
4099 && iHdaIndex >= 0
4100 && iHdaIndex < HDA_NREGS);
4101 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
4102}
4103
4104/**
4105 * @callback_method_impl{FNDBGFHANDLERDEV}
4106 */
4107static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4108{
4109 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4110 int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
4111 if (iHdaRegisterIndex != -1)
4112 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4113 else
4114 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
4115 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4116}
4117
4118static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
4119{
4120 Assert( pThis
4121 && iHdaStrmIndex >= 0
4122 && iHdaStrmIndex < 7);
4123 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
4124 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, CTL, iHdaStrmIndex));
4125 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, STS, iHdaStrmIndex));
4126 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOS, iHdaStrmIndex));
4127 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOW, iHdaStrmIndex));
4128}
4129
4130static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
4131{
4132 /* todo: add args parsing */
4133 return -1;
4134}
4135
4136/**
4137 * @callback_method_impl{FNDBGFHANDLERDEV}
4138 */
4139static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4140{
4141 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4142 int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
4143 if (iHdaStrmIndex != -1)
4144 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
4145 else
4146 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
4147 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
4148}
4149
4150/**
4151 * @callback_method_impl{FNDBGFHANDLERDEV}
4152 */
4153static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4154{
4155 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4156
4157 if (pThis->pCodec->pfnDbgListNodes)
4158 pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
4159 else
4160 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4161}
4162
4163/**
4164 * @callback_method_impl{FNDBGFHANDLERDEV}
4165 */
4166static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4167{
4168 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4169
4170 if (pThis->pCodec->pfnDbgSelector)
4171 pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
4172 else
4173 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4174}
4175
4176/**
4177 * @callback_method_impl{FNDBGFHANDLERDEV}
4178 */
4179static DECLCALLBACK(void) hdaInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4180{
4181 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4182
4183 if (pThis->pMixer)
4184 AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
4185 else
4186 pHlp->pfnPrintf(pHlp, "Mixer not available\n");
4187}
4188#endif /* DEBUG */
4189
4190/* PDMIBASE */
4191
4192/**
4193 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
4194 */
4195static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
4196{
4197 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
4198 Assert(&pThis->IBase == pInterface);
4199
4200 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
4201 return NULL;
4202}
4203
4204
4205/* PDMDEVREG */
4206
4207/**
4208 * Reset notification.
4209 *
4210 * @returns VBox status code.
4211 * @param pDevIns The device instance data.
4212 *
4213 * @remark The original sources didn't install a reset handler, but it seems to
4214 * make sense to me so we'll do it.
4215 */
4216static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
4217{
4218 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4219
4220 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
4221 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
4222 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
4223 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
4224 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
4225 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
4226 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
4227 HDA_REG(pThis, CORBRP) = 0x0;
4228 HDA_REG(pThis, RIRBWP) = 0x0;
4229
4230 LogFunc(("Resetting ...\n"));
4231
4232# ifndef VBOX_WITH_AUDIO_CALLBACKS
4233 /*
4234 * Stop the timer, if any.
4235 */
4236 int rc2;
4237 if (pThis->pTimer)
4238 {
4239 rc2 = TMTimerStop(pThis->pTimer);
4240 AssertRC(rc2);
4241 }
4242# endif
4243
4244 /*
4245 * Stop any audio currently playing and/or recording.
4246 */
4247 PHDADRIVER pDrv;
4248 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4249 {
4250 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, false /* Disable */);
4251# ifdef VBOX_WITH_HDA_MIC_IN
4252 /* Ignore rc. */
4253 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, false /* Disable */);
4254# endif
4255 /* Ditto. */
4256 pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, false /* Disable */);
4257 /* Ditto. */
4258 }
4259
4260 pThis->cbCorbBuf = 256 * sizeof(uint32_t); /** @todo Use a define here. */
4261
4262 if (pThis->pu32CorbBuf)
4263 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
4264 else
4265 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
4266
4267 pThis->cbRirbBuf = 256 * sizeof(uint64_t); /** @todo Use a define here. */
4268 if (pThis->pu64RirbBuf)
4269 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
4270 else
4271 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
4272
4273 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
4274
4275 for (uint8_t u8Strm = 0; u8Strm < 8; u8Strm++) /** @todo Use a define here. */
4276 {
4277 PHDASTREAM pStrmSt = NULL;
4278 if (u8Strm == 0) /** @todo Implement dynamic stream IDs. */
4279 pStrmSt = &pThis->StrmStLineIn;
4280# ifdef VBOX_WITH_HDA_MIC_IN
4281 else if (u8Strm == 2) /** @todo Implement dynamic stream IDs. */
4282 pStrmSt = &pThis->StrmStMicIn;
4283# endif
4284 else if (u8Strm == 4) /** @todo Implement dynamic stream IDs. */
4285 pStrmSt = &pThis->StrmStOut;
4286
4287 if (pStrmSt)
4288 {
4289 /* Remove the RUN bit from SDnCTL in case the stream was in a running state before. */
4290 HDA_STREAM_REG(pThis, CTL, u8Strm) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN);
4291
4292 hdaStreamReset(pThis, pStrmSt, u8Strm);
4293 }
4294 }
4295
4296 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
4297 HDA_REG(pThis, STATESTS) = 0x1;
4298
4299# ifndef VBOX_WITH_AUDIO_CALLBACKS
4300 /*
4301 * Start timer again, if any.
4302 */
4303 if (pThis->pTimer)
4304 {
4305 LogFunc(("Restarting timer\n"));
4306 rc2 = TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->cTimerTicks);
4307 AssertRC(rc2);
4308 }
4309# endif
4310
4311 LogRel(("HDA: Reset\n"));
4312}
4313
4314/**
4315 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4316 */
4317static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
4318{
4319 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4320
4321 PHDADRIVER pDrv;
4322 while (!RTListIsEmpty(&pThis->lstDrv))
4323 {
4324 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
4325
4326 RTListNodeRemove(&pDrv->Node);
4327 RTMemFree(pDrv);
4328 }
4329
4330 if (pThis->pMixer)
4331 {
4332 AudioMixerDestroy(pThis->pMixer);
4333 pThis->pMixer = NULL;
4334 }
4335
4336 if (pThis->pCodec)
4337 {
4338 int rc = hdaCodecDestruct(pThis->pCodec);
4339 AssertRC(rc);
4340
4341 RTMemFree(pThis->pCodec);
4342 pThis->pCodec = NULL;
4343 }
4344
4345 RTMemFree(pThis->pu32CorbBuf);
4346 pThis->pu32CorbBuf = NULL;
4347
4348 RTMemFree(pThis->pu64RirbBuf);
4349 pThis->pu64RirbBuf = NULL;
4350
4351 hdaStreamDestroy(&pThis->StrmStLineIn);
4352 hdaStreamDestroy(&pThis->StrmStMicIn);
4353 hdaStreamDestroy(&pThis->StrmStOut);
4354
4355 return VINF_SUCCESS;
4356}
4357
4358
4359/**
4360 * Attach command, internal version.
4361 *
4362 * This is called to let the device attach to a driver for a specified LUN
4363 * during runtime. This is not called during VM construction, the device
4364 * constructor has to attach to all the available drivers.
4365 *
4366 * @returns VBox status code.
4367 * @param pDevIns The device instance.
4368 * @param pDrv Driver to (re-)use for (re-)attaching to.
4369 * If NULL is specified, a new driver will be created and appended
4370 * to the driver list.
4371 * @param uLUN The logical unit which is being detached.
4372 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4373 */
4374static int hdaAttachInternal(PPDMDEVINS pDevIns, PHDADRIVER pDrv, unsigned uLUN, uint32_t fFlags)
4375{
4376 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4377
4378 /*
4379 * Attach driver.
4380 */
4381 char *pszDesc = NULL;
4382 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
4383 AssertReleaseMsgReturn(pszDesc,
4384 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
4385 VERR_NO_MEMORY);
4386
4387 PPDMIBASE pDrvBase;
4388 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
4389 &pThis->IBase, &pDrvBase, pszDesc);
4390 if (RT_SUCCESS(rc))
4391 {
4392 if (pDrv == NULL)
4393 pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
4394 if (pDrv)
4395 {
4396 pDrv->pDrvBase = pDrvBase;
4397 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
4398 AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
4399 pDrv->pHDAState = pThis;
4400 pDrv->uLUN = uLUN;
4401
4402 /*
4403 * For now we always set the driver at LUN 0 as our primary
4404 * host backend. This might change in the future.
4405 */
4406 if (pDrv->uLUN == 0)
4407 pDrv->Flags |= PDMAUDIODRVFLAG_PRIMARY;
4408
4409 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
4410
4411 /* Attach to driver list if not attached yet. */
4412 if (!pDrv->fAttached)
4413 {
4414 RTListAppend(&pThis->lstDrv, &pDrv->Node);
4415 pDrv->fAttached = true;
4416 }
4417 }
4418 else
4419 rc = VERR_NO_MEMORY;
4420 }
4421 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4422 LogFunc(("No attached driver for LUN #%u\n", uLUN));
4423
4424 if (RT_FAILURE(rc))
4425 {
4426 /* Only free this string on failure;
4427 * must remain valid for the live of the driver instance. */
4428 RTStrFree(pszDesc);
4429 }
4430
4431 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
4432 return rc;
4433}
4434
4435/**
4436 * Attach command.
4437 *
4438 * This is called to let the device attach to a driver for a specified LUN
4439 * during runtime. This is not called during VM construction, the device
4440 * constructor has to attach to all the available drivers.
4441 *
4442 * @returns VBox status code.
4443 * @param pDevIns The device instance.
4444 * @param uLUN The logical unit which is being detached.
4445 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4446 */
4447static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4448{
4449 return hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, fFlags);
4450}
4451
4452static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4453{
4454 LogFunc(("iLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
4455}
4456
4457/**
4458 * Re-attach.
4459 *
4460 * @returns VBox status code.
4461 * @param pThis Device instance.
4462 * @param pDrv Driver instance used for attaching to.
4463 * If NULL is specified, a new driver will be created and appended
4464 * to the driver list.
4465 * @param uLUN The logical unit which is being re-detached.
4466 * @param pszDriver Driver name.
4467 */
4468static int hdaReattach(PHDASTATE pThis, PHDADRIVER pDrv, uint8_t uLUN, const char *pszDriver)
4469{
4470 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4471 AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
4472
4473 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
4474 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
4475 PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/hda/0/");
4476
4477 /* Remove LUN branch. */
4478 CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
4479
4480 if (pDrv)
4481 {
4482 /* Re-use a driver instance => detach the driver before. */
4483 int rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
4484 if (RT_FAILURE(rc))
4485 return rc;
4486 }
4487
4488#define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
4489
4490 int rc = VINF_SUCCESS;
4491 do
4492 {
4493 PCFGMNODE pLunL0;
4494 rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
4495 rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
4496 rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
4497
4498 PCFGMNODE pLunL1, pLunL2;
4499 rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
4500 rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
4501 rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
4502
4503 rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
4504
4505 } while (0);
4506
4507 if (RT_SUCCESS(rc))
4508 rc = hdaAttachInternal(pThis->pDevInsR3, pDrv, uLUN, 0 /* fFlags */);
4509
4510 LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
4511
4512#undef RC_CHECK
4513
4514 return rc;
4515}
4516
4517/**
4518 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4519 */
4520static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4521{
4522 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4523 Assert(iInstance == 0);
4524 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4525
4526 /*
4527 * Validations.
4528 */
4529 if (!CFGMR3AreValuesValid(pCfg, "R0Enabled\0"
4530 "RCEnabled\0"
4531 "TimerHz\0"))
4532 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4533 N_ ("Invalid configuration for the Intel HDA device"));
4534
4535 int rc = CFGMR3QueryBoolDef(pCfg, "RCEnabled", &pThis->fRCEnabled, false);
4536 if (RT_FAILURE(rc))
4537 return PDMDEV_SET_ERROR(pDevIns, rc,
4538 N_("HDA configuration error: failed to read RCEnabled as boolean"));
4539 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, false);
4540 if (RT_FAILURE(rc))
4541 return PDMDEV_SET_ERROR(pDevIns, rc,
4542 N_("HDA configuration error: failed to read R0Enabled as boolean"));
4543#ifndef VBOX_WITH_AUDIO_CALLBACKS
4544 uint16_t uTimerHz;
4545 rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &uTimerHz, 200 /* Hz */);
4546 if (RT_FAILURE(rc))
4547 return PDMDEV_SET_ERROR(pDevIns, rc,
4548 N_("HDA configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
4549#endif
4550
4551 /*
4552 * Initialize data (most of it anyway).
4553 */
4554 pThis->pDevInsR3 = pDevIns;
4555 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
4556 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4557 /* IBase */
4558 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
4559
4560 /* PCI Device */
4561 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
4562 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
4563
4564 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
4565 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
4566 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
4567 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
4568 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
4569 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
4570 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
4571 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
4572 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
4573 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
4574 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
4575
4576#if defined(HDA_AS_PCI_EXPRESS)
4577 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
4578#elif defined(VBOX_WITH_MSI_DEVICES)
4579 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
4580#else
4581 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
4582#endif
4583
4584 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
4585 /// of these values needs to be properly documented!
4586 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
4587 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
4588
4589 /* Power Management */
4590 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
4591 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
4592 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
4593
4594#ifdef HDA_AS_PCI_EXPRESS
4595 /* PCI Express */
4596 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
4597 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
4598 /* Device flags */
4599 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
4600 /* version */ 0x1 |
4601 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
4602 /* MSI */ (100) << 9 );
4603 /* Device capabilities */
4604 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
4605 /* Device control */
4606 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
4607 /* Device status */
4608 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
4609 /* Link caps */
4610 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
4611 /* Link control */
4612 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
4613 /* Link status */
4614 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
4615 /* Slot capabilities */
4616 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
4617 /* Slot control */
4618 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
4619 /* Slot status */
4620 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
4621 /* Root control */
4622 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
4623 /* Root capabilities */
4624 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
4625 /* Root status */
4626 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
4627 /* Device capabilities 2 */
4628 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
4629 /* Device control 2 */
4630 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
4631 /* Link control 2 */
4632 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
4633 /* Slot control 2 */
4634 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
4635#endif
4636
4637 /*
4638 * Register the PCI device.
4639 */
4640 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
4641 if (RT_FAILURE(rc))
4642 return rc;
4643
4644 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
4645 if (RT_FAILURE(rc))
4646 return rc;
4647
4648#ifdef VBOX_WITH_MSI_DEVICES
4649 PDMMSIREG MsiReg;
4650 RT_ZERO(MsiReg);
4651 MsiReg.cMsiVectors = 1;
4652 MsiReg.iMsiCapOffset = 0x60;
4653 MsiReg.iMsiNextOffset = 0x50;
4654 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
4655 if (RT_FAILURE(rc))
4656 {
4657 /* That's OK, we can work without MSI */
4658 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
4659 }
4660#endif
4661
4662 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
4663 if (RT_FAILURE(rc))
4664 return rc;
4665
4666 RTListInit(&pThis->lstDrv);
4667
4668 uint8_t uLUN;
4669 for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
4670 {
4671 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
4672 rc = hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, 0 /* fFlags */);
4673 if (RT_FAILURE(rc))
4674 {
4675 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4676 rc = VINF_SUCCESS;
4677 else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
4678 {
4679 hdaReattach(pThis, NULL /* pDrv */, uLUN, "NullAudio");
4680 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
4681 N_("No audio devices could be opened. Selecting the NULL audio backend "
4682 "with the consequence that no sound is audible"));
4683 /* attaching to the NULL audio backend will never fail */
4684 rc = VINF_SUCCESS;
4685 }
4686 break;
4687 }
4688 }
4689
4690 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
4691
4692 if (RT_SUCCESS(rc))
4693 {
4694 rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
4695 if (RT_SUCCESS(rc))
4696 {
4697 /* Set a default audio format for our mixer. */
4698 PDMAUDIOSTREAMCFG streamCfg;
4699 streamCfg.uHz = 44100;
4700 streamCfg.cChannels = 2;
4701 streamCfg.enmFormat = AUD_FMT_S16;
4702 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANNESS;
4703
4704 rc = AudioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
4705 AssertRC(rc);
4706
4707 /* Add all required audio sinks. */
4708 rc = AudioMixerAddSink(pThis->pMixer, "[Playback] PCM Output",
4709 AUDMIXSINKDIR_OUTPUT, &pThis->pSinkOutput);
4710 AssertRC(rc);
4711
4712 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Line In",
4713 AUDMIXSINKDIR_INPUT, &pThis->pSinkLineIn);
4714 AssertRC(rc);
4715
4716 rc = AudioMixerAddSink(pThis->pMixer, "[Recording] Microphone In",
4717 AUDMIXSINKDIR_INPUT, &pThis->pSinkMicIn);
4718 AssertRC(rc);
4719
4720 /* There is no master volume control. Set the master to max. */
4721 PDMAUDIOVOLUME vol = { false, 255, 255 };
4722 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
4723 AssertRC(rc);
4724 }
4725 }
4726
4727 if (RT_SUCCESS(rc))
4728 {
4729 /* Construct codec. */
4730 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
4731 if (!pThis->pCodec)
4732 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
4733
4734 /* Audio driver callbacks for multiplexing. */
4735 pThis->pCodec->pfnCloseIn = hdaCloseIn;
4736 pThis->pCodec->pfnCloseOut = hdaCloseOut;
4737 pThis->pCodec->pfnOpenIn = hdaOpenIn;
4738 pThis->pCodec->pfnOpenOut = hdaOpenOut;
4739 pThis->pCodec->pfnReset = hdaCodecReset;
4740 pThis->pCodec->pfnSetVolume = hdaSetVolume;
4741
4742 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
4743
4744 /* Construct the codec. */
4745 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfg);
4746 if (RT_FAILURE(rc))
4747 AssertRCReturn(rc, rc);
4748
4749 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
4750 verb F20 should provide device/codec recognition. */
4751 Assert(pThis->pCodec->u16VendorId);
4752 Assert(pThis->pCodec->u16DeviceId);
4753 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
4754 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
4755 }
4756
4757 if (RT_SUCCESS(rc))
4758 {
4759 rc = hdaStreamCreate(&pThis->StrmStLineIn);
4760 AssertRC(rc);
4761#ifdef VBOX_WITH_HDA_MIC_IN
4762 rc = hdaStreamCreate(&pThis->StrmStMicIn);
4763 AssertRC(rc);
4764#endif
4765 rc = hdaStreamCreate(&pThis->StrmStOut);
4766 AssertRC(rc);
4767
4768 PHDADRIVER pDrv;
4769 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4770 {
4771 /*
4772 * Only primary drivers are critical for the VM to run. Everything else
4773 * might not worth showing an own error message box in the GUI.
4774 */
4775 if (!(pDrv->Flags & PDMAUDIODRVFLAG_PRIMARY))
4776 continue;
4777
4778 PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
4779 AssertPtr(pCon);
4780
4781 bool fValidLineIn = pCon->pfnIsValidIn(pCon, pDrv->LineIn.pStrmIn);
4782#ifdef VBOX_WITH_HDA_MIC_IN
4783 bool fValidMicIn = pCon->pfnIsValidIn (pCon, pDrv->MicIn.pStrmIn);
4784#endif
4785 bool fValidOut = pCon->pfnIsValidOut(pCon, pDrv->Out.pStrmOut);
4786
4787 if ( !fValidLineIn
4788#ifdef VBOX_WITH_HDA_MIC_IN
4789 && !fValidMicIn
4790#endif
4791 && !fValidOut)
4792 {
4793 LogRel(("HDA: Falling back to NULL backend (no sound audible)\n"));
4794
4795 hdaReset(pDevIns);
4796 hdaReattach(pThis, pDrv, pDrv->uLUN, "NullAudio");
4797
4798 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
4799 N_("No audio devices could be opened. Selecting the NULL audio backend "
4800 "with the consequence that no sound is audible"));
4801 }
4802 else
4803 {
4804 bool fWarn = false;
4805
4806 PDMAUDIOBACKENDCFG backendCfg;
4807 int rc2 = pCon->pfnGetConfiguration(pCon, &backendCfg);
4808 if (RT_SUCCESS(rc2))
4809 {
4810 if (backendCfg.cMaxHstStrmsIn)
4811 {
4812#ifdef VBOX_WITH_HDA_MIC_IN
4813 /* If the audio backend supports two or more input streams at once,
4814 * warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
4815 if (backendCfg.cMaxHstStrmsIn >= 2)
4816 fWarn = !fValidLineIn || !fValidMicIn;
4817 /* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
4818 * *not* ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
4819 * One of the two simply is not in use then. */
4820 else if (backendCfg.cMaxHstStrmsIn == 1)
4821 fWarn = !fValidLineIn && !fValidMicIn;
4822 /* Don't warn if our backend is not able of supporting any input streams at all. */
4823#else
4824 /* We only have line-in as input source. */
4825 fWarn = !fValidLineIn;
4826#endif
4827 }
4828
4829 if ( !fWarn
4830 && backendCfg.cMaxHstStrmsOut)
4831 {
4832 fWarn = !fValidOut;
4833 }
4834 }
4835 else
4836 AssertReleaseMsgFailed(("Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n",
4837 pDrv->uLUN, rc2));
4838
4839 if (fWarn)
4840 {
4841 char szMissingStreams[255];
4842 size_t len = 0;
4843 if (!fValidLineIn)
4844 {
4845 LogRel(("HDA: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
4846 len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
4847 }
4848#ifdef VBOX_WITH_HDA_MIC_IN
4849 if (!fValidMicIn)
4850 {
4851 LogRel(("HDA: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
4852 len += RTStrPrintf(szMissingStreams + len,
4853 sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
4854 }
4855#endif
4856 if (!fValidOut)
4857 {
4858 LogRel(("HDA: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
4859 len += RTStrPrintf(szMissingStreams + len,
4860 sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
4861 }
4862
4863 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
4864 N_("Some HDA audio streams (%s) could not be opened. Guest applications generating audio "
4865 "output or depending on audio input may hang. Make sure your host audio device "
4866 "is working properly. Check the logfile for error messages of the audio "
4867 "subsystem"), szMissingStreams);
4868 }
4869 }
4870 }
4871 }
4872
4873 if (RT_SUCCESS(rc))
4874 {
4875 hdaReset(pDevIns);
4876
4877 /*
4878 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
4879 * hdaReset shouldn't affects these registers.
4880 */
4881 HDA_REG(pThis, WAKEEN) = 0x0;
4882 HDA_REG(pThis, STATESTS) = 0x0;
4883
4884#ifdef DEBUG
4885 /*
4886 * Debug and string formatter types.
4887 */
4888 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
4889 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
4890 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
4891 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
4892 PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaInfoMixer);
4893
4894 rc = RTStrFormatTypeRegister("bdle", hdaDbgFmtBDLE, NULL);
4895 AssertRC(rc);
4896 rc = RTStrFormatTypeRegister("sdctl", hdaDbgFmtSDCTL, NULL);
4897 AssertRC(rc);
4898 rc = RTStrFormatTypeRegister("sdsts", hdaDbgFmtSDSTS, NULL);
4899 AssertRC(rc);
4900 rc = RTStrFormatTypeRegister("sdfifos", hdaDbgFmtSDFIFOS, NULL);
4901 AssertRC(rc);
4902 rc = RTStrFormatTypeRegister("sdfifow", hdaDbgFmtSDFIFOW, NULL);
4903 AssertRC(rc);
4904#endif /* DEBUG */
4905
4906 /*
4907 * Some debug assertions.
4908 */
4909 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
4910 {
4911 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
4912 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
4913
4914 /* binary search order. */
4915 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
4916 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4917 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
4918
4919 /* alignment. */
4920 AssertReleaseMsg( pReg->size == 1
4921 || (pReg->size == 2 && (pReg->offset & 1) == 0)
4922 || (pReg->size == 3 && (pReg->offset & 3) == 0)
4923 || (pReg->size == 4 && (pReg->offset & 3) == 0),
4924 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4925
4926 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
4927 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
4928 if (pReg->offset & 3)
4929 {
4930 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
4931 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4932 if (pPrevReg)
4933 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
4934 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4935 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
4936 }
4937#if 0
4938 if ((pReg->offset + pReg->size) & 3)
4939 {
4940 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4941 if (pNextReg)
4942 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
4943 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
4944 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
4945 }
4946#endif
4947 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
4948 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
4949 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4950 }
4951 }
4952
4953# ifndef VBOX_WITH_AUDIO_CALLBACKS
4954 if (RT_SUCCESS(rc))
4955 {
4956 /* Start the emulation timer. */
4957 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
4958 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
4959 AssertRCReturn(rc, rc);
4960
4961 if (RT_SUCCESS(rc))
4962 {
4963 pThis->cTimerTicks = TMTimerGetFreq(pThis->pTimer) / uTimerHz;
4964 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
4965 LogFunc(("Timer ticks=%RU64 (%RU16 Hz)\n", pThis->cTimerTicks, uTimerHz));
4966
4967 /* Fire off timer. */
4968 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->cTimerTicks);
4969 }
4970 }
4971# else
4972 if (RT_SUCCESS(rc))
4973 {
4974 PHDADRIVER pDrv;
4975 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4976 {
4977 /* Only register primary driver.
4978 * The device emulation does the output multiplexing then. */
4979 if (pDrv->Flags != PDMAUDIODRVFLAG_PRIMARY)
4980 continue;
4981
4982 PDMAUDIOCALLBACK AudioCallbacks[2];
4983
4984 HDACALLBACKCTX Ctx = { pThis, pDrv };
4985
4986 AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
4987 AudioCallbacks[0].pfnCallback = hdaCallbackInput;
4988 AudioCallbacks[0].pvCtx = &Ctx;
4989 AudioCallbacks[0].cbCtx = sizeof(HDACALLBACKCTX);
4990
4991 AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
4992 AudioCallbacks[1].pfnCallback = hdaCallbackOutput;
4993 AudioCallbacks[1].pvCtx = &Ctx;
4994 AudioCallbacks[1].cbCtx = sizeof(HDACALLBACKCTX);
4995
4996 rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
4997 if (RT_FAILURE(rc))
4998 break;
4999 }
5000 }
5001# endif
5002
5003# ifdef VBOX_WITH_STATISTICS
5004 if (RT_SUCCESS(rc))
5005 {
5006 /*
5007 * Register statistics.
5008 */
5009# ifndef VBOX_WITH_AUDIO_CALLBACKS
5010 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
5011# endif
5012 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
5013 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
5014 }
5015# endif
5016
5017 LogFlowFuncLeaveRC(rc);
5018 return rc;
5019}
5020
5021/**
5022 * The device registration structure.
5023 */
5024const PDMDEVREG g_DeviceICH6_HDA =
5025{
5026 /* u32Version */
5027 PDM_DEVREG_VERSION,
5028 /* szName */
5029 "hda",
5030 /* szRCMod */
5031 "VBoxDDRC.rc",
5032 /* szR0Mod */
5033 "VBoxDDR0.r0",
5034 /* pszDescription */
5035 "Intel HD Audio Controller",
5036 /* fFlags */
5037 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
5038 /* fClass */
5039 PDM_DEVREG_CLASS_AUDIO,
5040 /* cMaxInstances */
5041 1,
5042 /* cbInstance */
5043 sizeof(HDASTATE),
5044 /* pfnConstruct */
5045 hdaConstruct,
5046 /* pfnDestruct */
5047 hdaDestruct,
5048 /* pfnRelocate */
5049 NULL,
5050 /* pfnMemSetup */
5051 NULL,
5052 /* pfnPowerOn */
5053 NULL,
5054 /* pfnReset */
5055 hdaReset,
5056 /* pfnSuspend */
5057 NULL,
5058 /* pfnResume */
5059 NULL,
5060 /* pfnAttach */
5061 hdaAttach,
5062 /* pfnDetach */
5063 hdaDetach,
5064 /* pfnQueryInterface. */
5065 NULL,
5066 /* pfnInitComplete */
5067 NULL,
5068 /* pfnPowerOff */
5069 NULL,
5070 /* pfnSoftReset */
5071 NULL,
5072 /* u32VersionEnd */
5073 PDM_DEVREG_VERSION
5074};
5075
5076#endif /* IN_RING3 */
5077#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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