VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp@ 36475

Last change on this file since 36475 was 35515, checked in by vboxsync, 14 years ago

Audio/HDA: more clean up.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 101.5 KB
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1/* $Id: DevIchIntelHDA.cpp 35515 2011-01-13 07:35:07Z vboxsync $ */
2/** @file
3 * DevIchIntelHD - VBox ICH Intel HD Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_AUDIO
22#include <VBox/vmm/pdmdev.h>
23#include <iprt/assert.h>
24#include <iprt/uuid.h>
25#include <iprt/string.h>
26#include <iprt/mem.h>
27#include <iprt/asm.h>
28#include <iprt/asm-math.h>
29
30#include "VBoxDD.h"
31
32extern "C" {
33#include "audio.h"
34}
35#include "DevCodec.h"
36
37#define VBOX_WITH_INTEL_HDA
38
39#if defined(VBOX_WITH_HP_HDA)
40/* HP Pavilion dv4t-1300 */
41# define HDA_PCI_VENDOR_ID 0x103c
42# define HDA_PCI_DEICE_ID 0x30f7
43#elif defined(VBOX_WITH_INTEL_HDA)
44/* Intel HDA controller */
45# define HDA_PCI_VENDOR_ID 0x8086
46# define HDA_PCI_DEICE_ID 0x2668
47#elif defined(VBOX_WITH_NVIDIA_HDA)
48/* nVidia HDA controller */
49# define HDA_PCI_VENDOR_ID 0x10de
50# define HDA_PCI_DEICE_ID 0x0ac0
51#else
52# error "Please specify your HDA device vendor/device IDs"
53#endif
54
55#define HDA_SSM_VERSION 1
56PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
57PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
58static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns);
59
60/* Registers */
61#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
62#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
63#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
64#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
65#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
66#define HDA_REG_IND(pState, x) ((pState)->au32Regs[(x)])
67#define HDA_REG(pState, x) (HDA_REG_IND((pState), HDA_REG_IND_NAME(x)))
68#define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
69#define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
70#define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
71
72#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
73#define GCAP(pState) (HDA_REG((pState), GCAP))
74/* GCAP HDASpec 3.3.2 This macro compact following information about HDA
75 * oss (15:12) - number of output streams supported
76 * iss (11:8) - number of input streams supported
77 * bss (7:3) - number of bidirection streams suppoted
78 * bds (2:1) - number of serial data out signals supported
79 * b64sup (0) - 64 bit addressing supported.
80 */
81#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
82 ( (((oss) & 0xF) << 12) \
83 | (((iss) & 0xF) << 8) \
84 | (((bss) & 0x1F) << 3) \
85 | (((bds) & 0x3) << 2) \
86 | ((b64sup) & 1))
87#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
88#define VMIN(pState) (HDA_REG((pState), VMIN))
89
90#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
91#define VMAJ(pState) (HDA_REG((pState), VMAJ))
92
93#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
94#define OUTPAY(pState) (HDA_REG((pState), OUTPAY))
95
96#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
97#define INPAY(pState) (HDA_REG((pState), INPAY))
98
99#define ICH6_HDA_REG_GCTL (5)
100#define ICH6_HDA_GCTL_RST_SHIFT (0)
101#define ICH6_HDA_GCTL_FSH_SHIFT (1)
102#define ICH6_HDA_GCTL_UR_SHIFT (8)
103#define GCTL(pState) (HDA_REG((pState), GCTL))
104
105#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
106#define WAKEEN(pState) (HDA_REG((pState), WAKEEN))
107
108#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
109#define STATESTS(pState) (HDA_REG((pState), STATESTS))
110#define ICH6_HDA_STATES_SCSF 0x7
111
112#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
113#define ICH6_HDA_GSTS_FSH_SHIFT (1)
114#define GSTS(pState) (HDA_REG(pState, GSTS))
115
116#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
117#define ICH6_HDA_INTCTL_GIE_SHIFT 31
118#define ICH6_HDA_INTCTL_CIE_SHIFT 30
119#define ICH6_HDA_INTCTL_S0_SHIFT (0)
120#define ICH6_HDA_INTCTL_S1_SHIFT (1)
121#define ICH6_HDA_INTCTL_S2_SHIFT (2)
122#define ICH6_HDA_INTCTL_S3_SHIFT (3)
123#define ICH6_HDA_INTCTL_S4_SHIFT (4)
124#define ICH6_HDA_INTCTL_S5_SHIFT (5)
125#define ICH6_HDA_INTCTL_S6_SHIFT (6)
126#define ICH6_HDA_INTCTL_S7_SHIFT (7)
127#define INTCTL(pState) (HDA_REG((pState), INTCTL))
128#define INTCTL_GIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, GIE))
129#define INTCTL_CIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, CIE))
130#define INTCTL_SX(pState, X) (HDA_REG_FLAG_VALUE((pState), INTCTL, S##X))
131#define INTCTL_SALL(pState) (INTCTL((pState)) & 0xFF)
132
133/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
134 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
135 * the datasheet.
136 */
137#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
138#define SSYNC(pState) (HDA_REG((pState), SSYNC))
139
140#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
141#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
142#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
143#define ICH6_HDA_INTSTS_S0_SHIFT (0)
144#define ICH6_HDA_INTSTS_S1_SHIFT (1)
145#define ICH6_HDA_INTSTS_S2_SHIFT (2)
146#define ICH6_HDA_INTSTS_S3_SHIFT (3)
147#define ICH6_HDA_INTSTS_S4_SHIFT (4)
148#define ICH6_HDA_INTSTS_S5_SHIFT (5)
149#define ICH6_HDA_INTSTS_S6_SHIFT (6)
150#define ICH6_HDA_INTSTS_S7_SHIFT (7)
151#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
152#define INTSTS(pState) (HDA_REG((pState), INTSTS))
153#define INTSTS_GIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, GIS)
154#define INTSTS_CIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, CIS)
155#define INTSTS_SX(pState, X) (HDA_REG_FLAG_VALUE(pState), INTSTS, S##X)
156#define INTSTS_SANY(pState) (INTSTS((pState)) & 0xFF)
157
158#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
159#define CORBLBASE(pState) (HDA_REG((pState), CORBLBASE))
160#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
161#define CORBUBASE(pState) (HDA_REG((pState), CORBUBASE))
162#define ICH6_HDA_REG_CORBWP 15 /* 48 */
163#define ICH6_HDA_REG_CORBRP 16 /* 4A */
164#define ICH6_HDA_CORBRP_RST_SHIFT 15
165#define ICH6_HDA_CORBRP_WP_SHIFT 0
166#define ICH6_HDA_CORBRP_WP_MASK 0xFF
167
168#define CORBRP(pState) (HDA_REG(pState, CORBRP))
169#define CORBWP(pState) (HDA_REG(pState, CORBWP))
170
171#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
172#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
173#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
174
175#define CORBCTL(pState) (HDA_REG(pState, CORBCTL))
176
177
178#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
179#define CORBSTS(pState) (HDA_REG(pState, CORBSTS))
180#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
181
182#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
183#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
184#define ICH6_HDA_CORBSIZE_SZ 0x3
185#define CORBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
186#define CORBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
187/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
188
189#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
190#define RIRLBASE(pState) (HDA_REG((pState), RIRLBASE))
191
192#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
193#define RIRUBASE(pState) (HDA_REG((pState), RIRUBASE))
194
195#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
196#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
197#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
198#define RIRBWP(pState) (HDA_REG(pState, RIRBWP))
199
200#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
201#define RINTCNT(pState) (HDA_REG((pState), RINTCNT))
202#define RINTCNT_N(pState) (RINTCNT((pState)) & 0xff)
203
204#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
205#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
206#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
207#define ICH6_HDA_ROI_DMA_SHIFT (2)
208#define RIRBCTL(pState) (HDA_REG((pState), RIRBCTL))
209#define RIRBCTL_RIRB_RIC(pState) (HDA_REG_FLAG_VALUE(pState, RIRBCTL, RIC))
210#define RIRBCTL_RIRB_DMA(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, DMA)
211#define RIRBCTL_ROI(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, ROI))
212
213#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
214#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
215#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
216#define RIRBSTS(pState) (HDA_REG(pState, RIRBSTS))
217#define RIRBSTS_RINTFL(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RINTFL))
218#define RIRBSTS_RIRBOIS(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RIRBOIS))
219
220#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
221#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
222#define ICH6_HDA_RIRBSIZE_SZ 0x3
223
224#define RIRBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
225#define RIRBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
226
227
228#define ICH6_HDA_REG_IC 27 /* 0x60 */
229#define IC(pState) (HDA_REG(pState, IC))
230#define ICH6_HDA_REG_IR 28 /* 0x64 */
231#define IR(pState) (HDA_REG(pState, IR))
232#define ICH6_HDA_REG_IRS 29 /* 0x68 */
233#define ICH6_HDA_IRS_ICB_SHIFT (0)
234#define ICH6_HDA_IRS_IRV_SHIFT (1)
235#define IRS(pState) (HDA_REG(pState, IRS))
236#define IRS_ICB(pState) (HDA_REG_FLAG_VALUE(pState, IRS, ICB))
237#define IRS_IRV(pState) (HDA_REG_FLAG_VALUE(pState, IRS, IRV))
238
239#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
240#define DPLBASE(pState) (HDA_REG((pState), DPLBASE))
241#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
242#define DPUBASE(pState) (HDA_REG((pState), DPUBASE))
243#define DPBASE_ENABLED 1
244#define DPBASE_ADDR_MASK (~0x7f)
245
246#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
247#define HDA_STREAM_REG(pState, name, num) (HDA_REG((pState), N_(HDA_STREAM_REG_DEF(name, num))))
248/* Note: sdnum here _MUST_ be stream reg number [0,7] */
249#define HDA_STREAM_REG2(pState, name, sdnum) (HDA_REG_IND((pState), ICH6_HDA_REG_SD0##name + (sdnum) * 10))
250
251#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
252#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
253#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
254#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
255#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
256#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
257#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
258#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
259
260#define SD(func, num) SD##num##func
261#define SDCTL(pState, num) HDA_REG((pState), SD(CTL, num))
262#define SDCTL_NUM(pState, num) ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
263#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
264#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
265#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
266#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
267#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
268#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
269#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
270
271#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
272#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
273#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
274#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
275#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
276#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
277#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
278#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
279
280#define SDSTS(pState, num) HDA_REG((pState), SD(STS, num))
281#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
282#define ICH6_HDA_SDSTS_DE_SHIFT (4)
283#define ICH6_HDA_SDSTS_FE_SHIFT (3)
284#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
285
286#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
287#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
288#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
289#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
290#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
291#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
292#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
293#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
294
295#define SDLPIB(pState, num) HDA_REG((pState), SD(LPIB, num))
296
297#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
298#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
299#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
300#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
301#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
302#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
303#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
304#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
305
306#define SDLCBL(pState, num) HDA_REG((pState), SD(CBL, num))
307
308#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
309#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
310#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
311#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
312#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
313#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
314#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
315#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
316
317#define SDLVI(pState, num) HDA_REG((pState), SD(LVI, num))
318
319#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
320#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
321#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
322#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
323#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
324#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
325#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
326#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
327
328/*
329 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
330 */
331#define HDA_SDFIFOW_8B (0x2)
332#define HDA_SDFIFOW_16B (0x3)
333#define HDA_SDFIFOW_32B (0x4)
334#define SDFIFOW(pState, num) HDA_REG((pState), SD(FIFOW, num))
335
336#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
337#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
338#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
339#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
340#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
341#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
342#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
343#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
344
345/*
346 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
347 * formula: size - 1
348 * Other values not listed are not supported.
349 */
350#define HDA_SDONFIFO_16B (0xF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
351#define HDA_SDONFIFO_32B (0x1F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
352#define HDA_SDONFIFO_64B (0x3F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
353#define HDA_SDONFIFO_128B (0x7F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
354#define HDA_SDONFIFO_192B (0xBF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
355#define HDA_SDONFIFO_256B (0xFF) /* 20-, 24-bit Output Streams */
356#define HDA_SDINFIFO_120B (0x77) /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
357#define HDA_SDINFIFO_160B (0x9F) /* 20-, 24-bit Input Streams Streams */
358#define SDFIFOS(pState, num) HDA_REG((pState), SD(FIFOS, num))
359
360#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
361#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
362#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
363#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
364#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
365#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
366#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
367#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
368
369#define SDFMT(pState, num) (HDA_REG((pState), SD(FMT, num)))
370#define ICH6_HDA_SDFMT_BASE_RATE_SHIFT (14)
371#define ICH6_HDA_SDFMT_MULT_SHIFT (11)
372#define ICH6_HDA_SDFMT_MULT_MASK (0x7)
373#define ICH6_HDA_SDFMT_DIV_SHIFT (8)
374#define ICH6_HDA_SDFMT_DIV_MASK (0x7)
375#define SDFMT_BASE_RATE(pState, num) ((SDFMT(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
376#define SDFMT_MULT(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
377#define SDFMT_DIV(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
378
379#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
380#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
381#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
382#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
383#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
384#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
385#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
386#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
387
388#define SDBDPL(pState, num) HDA_REG((pState), SD(BDPL, num))
389
390#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
391#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
392#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
393#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
394#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
395#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
396#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
397#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
398
399#define SDBDPU(pState, num) HDA_REG((pState), SD(BDPU, num))
400
401/* Predicates */
402
403typedef struct HDABDLEDESC
404{
405 uint64_t u64BdleCviAddr;
406 uint32_t u32BdleMaxCvi;
407 uint32_t u32BdleCvi;
408 uint32_t u32BdleCviLen;
409 uint32_t u32BdleCviPos;
410 bool fBdleCviIoc;
411 uint32_t cbUnderFifoW;
412 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
413} HDABDLEDESC, *PHDABDLEDESC;
414
415typedef struct HDASTREAMTRANSFERDESC
416{
417 uint64_t u64BaseDMA;
418 uint32_t u32Ctl;
419 uint32_t *pu32Sts;
420 uint8_t u8Strm;
421 uint32_t *pu32Lpib;
422 uint32_t u32Cbl;
423 uint32_t u32Fifos;
424} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
425
426typedef struct INTELHDLinkState
427{
428 /** Pointer to the device instance. */
429 PPDMDEVINSR3 pDevIns;
430 /** Pointer to the connector of the attached audio driver. */
431 PPDMIAUDIOCONNECTOR pDrv;
432 /** Pointer to the attached audio driver. */
433 PPDMIBASE pDrvBase;
434 /** The base interface for LUN\#0. */
435 PDMIBASE IBase;
436 RTGCPHYS addrMMReg;
437 uint32_t au32Regs[113];
438 HDABDLEDESC stInBdle;
439 HDABDLEDESC stOutBdle;
440 HDABDLEDESC stMicBdle;
441 /* Interrupt on completion */
442 bool fCviIoc;
443 uint64_t u64CORBBase;
444 uint64_t u64RIRBBase;
445 uint64_t u64DPBase;
446 /* pointer on CORB buf */
447 uint32_t *pu32CorbBuf;
448 /* size in bytes of CORB buf */
449 uint32_t cbCorbBuf;
450 /* pointer on RIRB buf */
451 uint64_t *pu64RirbBuf;
452 /* size in bytes of RIRB buf */
453 uint32_t cbRirbBuf;
454 /* indicates if HDA in reset. */
455 bool fInReset;
456 CODECState Codec;
457 uint8_t u8Counter;
458 uint64_t u64BaseTS;
459} INTELHDLinkState, *PINTELHDLinkState;
460
461#define ICH6_HDASTATE_2_DEVINS(pINTELHD) ((pINTELHD)->pDevIns)
462#define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PCIINTELHDLinkState *)(pPciDev))
463
464#define ISD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, In, \
465 SDFMT_BASE_RATE(pState, 0), SDFMT_MULT(pState, 0), SDFMT_DIV(pState, 0)))
466#define OSD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, Out, \
467 SDFMT_BASE_RATE(pState, 4), SDFMT_MULT(pState, 4), SDFMT_DIV(pState, 4)))
468
469
470
471
472typedef struct PCIINTELHDLinkState
473{
474 PCIDevice dev;
475 INTELHDLinkState hda;
476} PCIINTELHDLinkState;
477
478
479DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
480DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
481DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
482DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
483DECLCALLBACK(int)hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
484DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
485DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
486DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
487DECLCALLBACK(int)hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
488DECLCALLBACK(int)hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
489DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
490DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
491DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
492DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
493DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
494DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
495DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
496DECLCALLBACK(int)hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
497DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
498DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
499
500DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
501DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
502DECLCALLBACK(int)hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
503DECLCALLBACK(int)hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
504DECLCALLBACK(int)hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
505DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
506DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
507DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
508DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
509DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
510DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
511DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
512DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
513DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
514DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
515DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
516
517static inline void hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc);
518static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset);
519static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
520#ifdef LOG_ENABLED
521static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
522#endif
523
524/* see 302349 p 6.2*/
525const static struct stIchIntelHDRegMap
526{
527 /** Register offset in the register space. */
528 uint32_t offset;
529 /** Size in bytes. Registers of size > 4 are in fact tables. */
530 uint32_t size;
531 /** Readable bits. */
532 uint32_t readable;
533 /** Writable bits. */
534 uint32_t writable;
535 /** Read callback. */
536 int (*pfnRead)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
537 /** Write callback. */
538 int (*pfnWrite)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
539 /** Abbreviated name. */
540 const char *abbrev;
541 /** Full name. */
542 const char *name;
543} s_ichIntelHDRegMap[] =
544{
545 /* offset size read mask write mask read callback write callback abbrev full name */
546 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
547 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
548 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
549 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
550 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
551 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
552 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
553 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
554 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
555 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
556 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
557 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
558 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
559 //** @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
560 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
561 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
562 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
563 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
564 { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
565 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
566 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
567 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
568 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
569 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
570 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8, hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
571 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
572 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
573 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
574 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
575 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
576 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
577 { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
578 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
579 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
580
581 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
582 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
583 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
584 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
585 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
586 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD0FIFOW", "ISD0 FIFO Watermark" },
587 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
588 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD0FMT" , "ISD0 Format" },
589 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
590 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
591
592 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
593 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
594 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
595 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
596 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
597 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD1FIFOW", "ISD1 FIFO Watermark" },
598 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
599 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD1FMT" , "ISD1 Format" },
600 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
601 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
602
603 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
604 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
605 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
606 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
607 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
608 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD2FIFOW", "ISD2 FIFO Watermark" },
609 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
610 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD2FMT" , "ISD2 Format" },
611 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
612 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
613
614 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
615 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
616 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
617 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
618 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
619 { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
620 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
621 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD3FMT" , "ISD3 Format" },
622 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
623 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
624
625 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
626 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
627 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
628 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
629 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
630 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD0FIFOW", "OSD0 FIFO Watermark" },
631 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD0FIFOS", "OSD0 FIFO Size" },
632 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD0FMT" , "OSD0 Format" },
633 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
634 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
635
636 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
637 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
638 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
639 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
640 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
641 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD1FIFOW", "OSD1 FIFO Watermark" },
642 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD1FIFOS", "OSD1 FIFO Size" },
643 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD1FMT" , "OSD1 Format" },
644 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
645 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
646
647 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
648 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
649 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
650 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
651 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
652 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD2FIFOW", "OSD2 FIFO Watermark" },
653 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD2FIFOS", "OSD2 FIFO Size" },
654 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD2FMT" , "OSD2 Format" },
655 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
656 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
657
658 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
659 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
660 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
661 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
662 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
663 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD3FIFOW", "OSD3 FIFO Watermark" },
664 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD3FIFOS", "OSD3 FIFO Size" },
665 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD3FMT" , "OSD3 Format" },
666 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
667 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
668};
669
670static void inline hdaUpdatePosBuf(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
671{
672 if (pState->u64DPBase & DPBASE_ENABLED)
673 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState),
674 (pState->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm*8, pStreamDesc->pu32Lpib, sizeof(uint32_t));
675}
676static uint32_t inline hdaFifoWToSz(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
677{
678#if 0
679 switch(HDA_STREAM_REG2(pState, FIFOW, pStreamDesc->u8Strm))
680 {
681 case HDA_SDFIFOW_8B: return 8;
682 case HDA_SDFIFOW_16B: return 16;
683 case HDA_SDFIFOW_32B: return 32;
684 default:
685 AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pState, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
686 }
687#endif
688 return 0;
689}
690
691static int hdaProcessInterrupt(INTELHDLinkState* pState)
692{
693#define IS_INTERRUPT_OCCURED_AND_ENABLED(pState, num) \
694 ( INTCTL_SX((pState), num) \
695 && (SDSTS(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
696 bool fIrq = false;
697 if ( INTCTL_CIE(pState)
698 && ( RIRBSTS_RINTFL(pState)
699 || RIRBSTS_RIRBOIS(pState)
700 || (STATESTS(pState) & WAKEEN(pState))))
701 fIrq = true;
702
703 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 0)
704 || IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 4))
705 fIrq = true;
706
707 if (INTCTL_GIE(pState))
708 {
709 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
710 PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pState), 0 , fIrq);
711 }
712 return VINF_SUCCESS;
713}
714
715static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset)
716{
717 int index = 0;
718 //** @todo r=michaln: A linear search of an array with over 100 elements is very inefficient.
719 for (;index < (int)(sizeof(s_ichIntelHDRegMap)/sizeof(s_ichIntelHDRegMap[0])); ++index)
720 {
721 if ( u32Offset >= s_ichIntelHDRegMap[index].offset
722 && u32Offset < s_ichIntelHDRegMap[index].offset + s_ichIntelHDRegMap[index].size)
723 {
724 return index;
725 }
726 }
727 /* Aliases HDA spec 3.3.45 */
728 switch(u32Offset)
729 {
730 case 0x2084:
731 return HDA_REG_IND_NAME(SD0LPIB);
732 case 0x20A4:
733 return HDA_REG_IND_NAME(SD1LPIB);
734 case 0x20C4:
735 return HDA_REG_IND_NAME(SD2LPIB);
736 case 0x20E4:
737 return HDA_REG_IND_NAME(SD3LPIB);
738 case 0x2104:
739 return HDA_REG_IND_NAME(SD4LPIB);
740 case 0x2124:
741 return HDA_REG_IND_NAME(SD5LPIB);
742 case 0x2144:
743 return HDA_REG_IND_NAME(SD6LPIB);
744 case 0x2164:
745 return HDA_REG_IND_NAME(SD7LPIB);
746 }
747 return -1;
748}
749
750static int hdaCmdSync(INTELHDLinkState *pState, bool fLocal)
751{
752 int rc = VINF_SUCCESS;
753 if (fLocal)
754 {
755 Assert((HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)));
756 rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
757 if (RT_FAILURE(rc))
758 AssertRCReturn(rc, rc);
759#ifdef DEBUG_CMD_BUFFER
760 uint8_t i = 0;
761 do
762 {
763 Log(("hda: corb%02x: ", i));
764 uint8_t j = 0;
765 do
766 {
767 const char *prefix;
768 if ((i + j) == CORBRP(pState))
769 prefix = "[R]";
770 else if ((i + j) == CORBWP(pState))
771 prefix = "[W]";
772 else
773 prefix = " "; /* three spaces */
774 Log(("%s%08x", prefix, pState->pu32CorbBuf[i + j]));
775 j++;
776 } while (j < 8);
777 Log(("\n"));
778 i += 8;
779 } while(i != 0);
780#endif
781 }
782 else
783 {
784 Assert((HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA)));
785 rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
786 if (RT_FAILURE(rc))
787 AssertRCReturn(rc, rc);
788#ifdef DEBUG_CMD_BUFFER
789 uint8_t i = 0;
790 do {
791 Log(("hda: rirb%02x: ", i));
792 uint8_t j = 0;
793 do {
794 const char *prefix;
795 if ((i + j) == RIRBWP(pState))
796 prefix = "[W]";
797 else
798 prefix = " ";
799 Log((" %s%016lx", prefix, pState->pu64RirbBuf[i + j]));
800 } while (++j < 8);
801 Log(("\n"));
802 i += 8;
803 } while (i != 0);
804#endif
805 }
806 return rc;
807}
808
809static int hdaCORBCmdProcess(INTELHDLinkState *pState)
810{
811 int rc;
812 uint8_t corbRp;
813 uint8_t corbWp;
814 uint8_t rirbWp;
815
816 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
817
818 rc = hdaCmdSync(pState, true);
819 if (RT_FAILURE(rc))
820 AssertRCReturn(rc, rc);
821 corbRp = CORBRP(pState);
822 corbWp = CORBWP(pState);
823 rirbWp = RIRBWP(pState);
824 Assert((corbWp != corbRp));
825 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
826 while (corbRp != corbWp)
827 {
828 uint32_t cmd;
829 uint64_t resp;
830 corbRp++;
831 cmd = pState->pu32CorbBuf[corbRp];
832 rc = (pState)->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
833 if (RT_FAILURE(rc))
834 AssertRCReturn(rc, rc);
835 Assert(pfn);
836 (rirbWp)++;
837 rc = pfn(&pState->Codec, cmd, &resp);
838 if (RT_FAILURE(rc))
839 AssertRCReturn(rc, rc);
840 Log(("hda: verb:%08x->%016lx\n", cmd, resp));
841 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
842 && !HDA_REG_FLAG_VALUE(pState, GCTL, UR))
843 {
844 Log(("hda: unexpected unsolicited response.\n"));
845 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
846 return rc;
847 }
848 pState->pu64RirbBuf[rirbWp] = resp;
849 pState->u8Counter++;
850 if (pState->u8Counter == RINTCNT_N(pState))
851 break;
852 }
853 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
854 pState->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
855 rc = hdaCmdSync(pState, false);
856 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
857 if (RIRBCTL_RIRB_RIC(pState))
858 {
859 RIRBSTS((pState)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
860 pState->u8Counter = 0;
861 rc = hdaProcessInterrupt(pState);
862 }
863 if (RT_FAILURE(rc))
864 AssertRCReturn(rc, rc);
865 return rc;
866}
867
868static void hdaStreamReset(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
869{
870 Log(("hda: reset of stream (%d) started\n", u8Strm));
871 Assert(( pState
872 && pBdle
873 && pStreamDesc
874 && u8Strm <= 7));
875 memset(pBdle, 0, sizeof(HDABDLEDESC));
876 *pStreamDesc->pu32Lpib = 0;
877 *pStreamDesc->pu32Sts = 0;
878 /* According to ICH6 datasheet, 0x40000 is default value for stream descriptor register 23:20
879 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
880 HDA_STREAM_REG2(pState, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG2(pState, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
881
882 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
883 HDA_STREAM_REG2(pState, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
884 HDA_STREAM_REG2(pState, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
885 HDA_STREAM_REG2(pState, CBL, u8Strm) = 0;
886 HDA_STREAM_REG2(pState, LVI, u8Strm) = 0;
887 HDA_STREAM_REG2(pState, FMT, u8Strm) = 0;
888 HDA_STREAM_REG2(pState, BDPU, u8Strm) = 0;
889 HDA_STREAM_REG2(pState, BDPL, u8Strm) = 0;
890 Log(("hda: reset of stream (%d) finished\n", u8Strm));
891}
892
893
894DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
895{
896 *pu32Value = 0;
897 return VINF_SUCCESS;
898}
899DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
900{
901 return VINF_SUCCESS;
902}
903/* U8 */
904DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
905{
906 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffffff00) == 0);
907 return hdaRegReadU32(pState, offset, index, pu32Value);
908}
909
910DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
911{
912 Assert(((u32Value & 0xffffff00) == 0));
913 return hdaRegWriteU32(pState, offset, index, u32Value);
914}
915/* U16 */
916DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
917{
918 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffff0000) == 0);
919 return hdaRegReadU32(pState, offset, index, pu32Value);
920}
921
922DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
923{
924 Assert(((u32Value & 0xffff0000) == 0));
925 return hdaRegWriteU32(pState, offset, index, u32Value);
926}
927
928/* U24 */
929DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
930{
931 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xff000000) == 0);
932 return hdaRegReadU32(pState, offset, index, pu32Value);
933}
934
935DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
936{
937 Assert(((u32Value & 0xff000000) == 0));
938 return hdaRegWriteU32(pState, offset, index, u32Value);
939}
940/* U32 */
941DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
942{
943 *pu32Value = pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable;
944 return VINF_SUCCESS;
945}
946
947DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
948{
949 pState->au32Regs[index] = (u32Value & s_ichIntelHDRegMap[index].writable)
950 | (pState->au32Regs[index] & ~s_ichIntelHDRegMap[index].writable);
951 return VINF_SUCCESS;
952}
953
954DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
955{
956 return hdaRegReadU32(pState, offset, index, pu32Value);
957}
958
959DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
960{
961 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
962 {
963 /* exit reset state */
964 GCTL(pState) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
965 pState->fInReset = false;
966 }
967 else
968 {
969 /* enter reset state*/
970 if ( HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)
971 || HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
972 {
973 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
974 HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
975 HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
976 }
977 hdaReset(ICH6_HDASTATE_2_DEVINS(pState));
978 GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
979 pState->fInReset = true;
980 }
981 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
982 {
983 /* Flush: GSTS:1 set, see 6.2.6*/
984 GSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
985 /* DPLBASE and DPUBASE, should be initialized with initial value (see 6.2.6)*/
986 }
987 return VINF_SUCCESS;
988}
989
990DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
991{
992 uint32_t v = pState->au32Regs[index];
993 uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
994 pState->au32Regs[index] &= ~(v & nv); /* write of 1 clears corresponding bit */
995 return VINF_SUCCESS;
996}
997
998DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
999{
1000 uint32_t v = 0;
1001 if ( RIRBSTS_RIRBOIS(pState)
1002 || RIRBSTS_RINTFL(pState)
1003 || HDA_REG_FLAG_VALUE(pState, CORBSTS, CMEI)
1004 || STATESTS(pState))
1005 v |= RT_BIT(30);
1006#define HDA_IS_STREAM_EVENT(pState, stream) \
1007 ( (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1008 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1009 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1010#define MARK_STREAM(pState, stream, v) do {(v) |= HDA_IS_STREAM_EVENT((pState),stream) ? RT_BIT((stream)) : 0;}while(0)
1011 MARK_STREAM(pState, 0, v);
1012 MARK_STREAM(pState, 1, v);
1013 MARK_STREAM(pState, 2, v);
1014 MARK_STREAM(pState, 3, v);
1015 MARK_STREAM(pState, 4, v);
1016 MARK_STREAM(pState, 5, v);
1017 MARK_STREAM(pState, 6, v);
1018 MARK_STREAM(pState, 7, v);
1019 v |= v ? RT_BIT(31) : 0;
1020 *pu32Value = v;
1021 return VINF_SUCCESS;
1022}
1023
1024DECLCALLBACK(int)hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1025{
1026 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1027 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(ICH6_HDASTATE_2_DEVINS(pState)) - pState->u64BaseTS, 24, 1000);
1028 return VINF_SUCCESS;
1029}
1030
1031DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1032{
1033 return hdaRegReadU16(pState, offset, index, pu32Value);
1034}
1035
1036DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1037{
1038 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1039 CORBRP(pState) = 0;
1040 else
1041 return hdaRegWriteU8(pState, offset, index, u32Value);
1042 return VINF_SUCCESS;
1043}
1044
1045DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1046{
1047 int rc = hdaRegWriteU8(pState, offset, index, u32Value);
1048 AssertRC(rc);
1049 if ( CORBWP(pState) != CORBRP(pState)
1050 && HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) != 0)
1051 return hdaCORBCmdProcess(pState);
1052 return rc;
1053}
1054
1055DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1056{
1057 uint32_t v = CORBSTS(pState);
1058 CORBSTS(pState) &= ~(v & u32Value);
1059 return VINF_SUCCESS;
1060}
1061
1062DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1063{
1064 int rc;
1065 rc = hdaRegWriteU16(pState, offset, index, u32Value);
1066 if (RT_FAILURE(rc))
1067 AssertRCReturn(rc, rc);
1068 if (CORBWP(pState) == CORBRP(pState))
1069 return VINF_SUCCESS;
1070 if (!HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1071 return VINF_SUCCESS;
1072 rc = hdaCORBCmdProcess(pState);
1073 return rc;
1074}
1075
1076DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1077{
1078 return hdaRegReadU24(pState, offset, index, pu32Value);
1079}
1080
1081DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1082{
1083 bool fRun = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1084 bool fInRun = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1085 bool fReset = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1086 bool fInReset = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1087 int rc = VINF_SUCCESS;
1088 if (fInReset)
1089 {
1090 /* Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1091 * from reset
1092 */
1093 Assert((!fReset));
1094 Log(("hda: guest initiate exit of stream reset.\n"));
1095 goto done;
1096 }
1097 else if (fReset)
1098 {
1099 /*
1100 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1101 */
1102 uint8_t u8Strm = 0;
1103 PHDABDLEDESC pBdle = NULL;
1104 HDASTREAMTRANSFERDESC stStreamDesc;
1105 Assert((!fInRun && !fRun));
1106 switch (index)
1107 {
1108 case ICH6_HDA_REG_SD0CTL:
1109 u8Strm = 0;
1110 pBdle = &pState->stInBdle;
1111 break;
1112 case ICH6_HDA_REG_SD4CTL:
1113 u8Strm = 4;
1114 pBdle = &pState->stOutBdle;
1115 break;
1116 default:
1117 Log(("hda: changing SRST bit on non-attached stream\n"));
1118 goto done;
1119 }
1120 Log(("hda: guest initiate enter to stream reset.\n"));
1121 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &stStreamDesc);
1122 hdaStreamReset(pState, pBdle, &stStreamDesc, u8Strm);
1123 goto done;
1124 }
1125
1126 /* we enter here to change DMA states only */
1127 if ( (fInRun && !fRun)
1128 || (fRun && !fInRun))
1129 {
1130 Assert((!fReset && !fInReset));
1131 switch (index)
1132 {
1133 case ICH6_HDA_REG_SD0CTL:
1134 AUD_set_active_in(pState->Codec.SwVoiceIn, fRun);
1135 break;
1136 case ICH6_HDA_REG_SD4CTL:
1137 AUD_set_active_out(pState->Codec.SwVoiceOut, fRun);
1138 break;
1139 default:
1140 Log(("hda: changing RUN bit on non-attached stream\n"));
1141 goto done;
1142 }
1143 }
1144
1145 done:
1146 rc = hdaRegWriteU24(pState, offset, index, u32Value);
1147 if (RT_FAILURE(rc))
1148 AssertRCReturn(rc, VINF_SUCCESS);
1149 return rc;
1150}
1151
1152DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1153{
1154 uint32_t v = HDA_REG_IND(pState, index);
1155 v &= ~(u32Value & v);
1156 HDA_REG_IND(pState, index) = v;
1157 hdaProcessInterrupt(pState);
1158 return VINF_SUCCESS;
1159}
1160
1161DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1162{
1163 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1164 if (RT_FAILURE(rc))
1165 AssertRCReturn(rc, VINF_SUCCESS);
1166 return rc;
1167}
1168
1169DECLCALLBACK(int)hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1170{
1171 switch (u32Value)
1172 {
1173 case HDA_SDFIFOW_8B:
1174 case HDA_SDFIFOW_16B:
1175 case HDA_SDFIFOW_32B:
1176 return hdaRegWriteU16(pState, offset, index, u32Value);
1177 default:
1178 Log(("hda: Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1179 return hdaRegWriteU16(pState, offset, index, HDA_SDFIFOW_32B);
1180 }
1181 return VINF_SUCCESS;
1182}
1183/*
1184 * Note this method could be called for changing value on Output Streams only (ICH6 datacheet 18.2.39)
1185 *
1186 */
1187DECLCALLBACK(int)hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1188{
1189 switch (index)
1190 {
1191 /* SDInFIFOS is RO, n=0-3 */
1192 case ICH6_HDA_REG_SD0FIFOS:
1193 case ICH6_HDA_REG_SD1FIFOS:
1194 case ICH6_HDA_REG_SD2FIFOS:
1195 case ICH6_HDA_REG_SD3FIFOS:
1196 Log(("hda: Guest tries change value of FIFO size of Input Stream\n"));
1197 return VINF_SUCCESS;
1198 case ICH6_HDA_REG_SD4FIFOS:
1199 case ICH6_HDA_REG_SD5FIFOS:
1200 case ICH6_HDA_REG_SD6FIFOS:
1201 case ICH6_HDA_REG_SD7FIFOS:
1202 switch(u32Value)
1203 {
1204 case HDA_SDONFIFO_16B:
1205 case HDA_SDONFIFO_32B:
1206 case HDA_SDONFIFO_64B:
1207 case HDA_SDONFIFO_128B:
1208 case HDA_SDONFIFO_192B:
1209 return hdaRegWriteU16(pState, offset, index, u32Value);
1210
1211 case HDA_SDONFIFO_256B:
1212 Log(("hda: 256 bit is unsupported, HDA is switched into 192B mode\n"));
1213 default:
1214 return hdaRegWriteU16(pState, offset, index, HDA_SDONFIFO_192B);
1215 }
1216 return VINF_SUCCESS;
1217 default:
1218 AssertMsgFailed(("Something wierd happens with register lookup routine"));
1219 }
1220 return VINF_SUCCESS;
1221}
1222
1223static void inline hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pAudSetting)
1224{
1225 Assert((pAudSetting));
1226#define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1227 uint32_t u32Hz = (u32SdFmt & ICH6_HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1228 uint32_t u32HzMult = 1;
1229 uint32_t u32HzDiv = 1;
1230 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_MULT_MASK, ICH6_HDA_SDFMT_MULT_SHIFT))
1231 {
1232 case 0: u32HzMult = 1; break;
1233 case 1: u32HzMult = 2; break;
1234 case 2: u32HzMult = 3; break;
1235 case 3: u32HzMult = 4; break;
1236 default:
1237 Log(("hda: unsupported multiplier %x\n", u32SdFmt));
1238 }
1239 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_DIV_MASK, ICH6_HDA_SDFMT_DIV_SHIFT))
1240 {
1241 case 0: u32HzDiv = 1; break;
1242 case 1: u32HzDiv = 2; break;
1243 case 2: u32HzDiv = 3; break;
1244 case 3: u32HzDiv = 4; break;
1245 case 4: u32HzDiv = 5; break;
1246 case 5: u32HzDiv = 6; break;
1247 case 6: u32HzDiv = 7; break;
1248 case 7: u32HzDiv = 8; break;
1249 }
1250 pAudSetting->freq = u32Hz * u32HzMult / u32HzDiv;
1251 pAudSetting->nchannels = 2;
1252 pAudSetting->fmt = AUD_FMT_S16;
1253 pAudSetting->endianness = 0;
1254#undef EXTRACT_VALUE
1255}
1256
1257DECLCALLBACK(int)hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1258{
1259#if 0
1260 /* @todo here some more investigations are required. */
1261 audsettings_t as;
1262 /* no reason to reopen voice with same settings */
1263 if (u32Value == HDA_REG_IND(pState, index))
1264 return VINF_SUCCESS;
1265 hdaSdFmtToAudSettings(u32Value, &as);
1266 switch (index)
1267 {
1268 case ICH6_HDA_REG_SD0FMT:
1269 codecOpenVoice(&pState->Codec, PI_INDEX, &as);
1270 break;
1271 case ICH6_HDA_REG_SD4FMT:
1272 codecOpenVoice(&pState->Codec, PO_INDEX, &as);
1273 break;
1274 default:
1275 AssertMsgFailed(("unimplemented"));
1276 }
1277#endif
1278 return hdaRegWriteU16(pState, offset, index, u32Value);
1279}
1280
1281DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1282{
1283 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1284 if (RT_FAILURE(rc))
1285 AssertRCReturn(rc, VINF_SUCCESS);
1286 return rc;
1287}
1288
1289DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1290{
1291 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1292 if (RT_FAILURE(rc))
1293 AssertRCReturn(rc, VINF_SUCCESS);
1294 return rc;
1295}
1296
1297DECLCALLBACK(int)hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1298{
1299 int rc = VINF_SUCCESS;
1300 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1301 if ( CORBWP(pState) != CORBRP(pState)
1302 || HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1303 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1304
1305 rc = hdaRegReadU32(pState, offset, index, pu32Value);
1306 return rc;
1307}
1308
1309DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1310{
1311 int rc = VINF_SUCCESS;
1312 uint64_t resp;
1313 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
1314 /*
1315 * if guest set ICB bit of IRS register HDA should process verb in IC register and
1316 * writes response in IR register and set IRV (valid in case of success) bit of IRS register.
1317 */
1318 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1319 && !IRS_ICB(pState))
1320 {
1321 uint32_t cmd = IC(pState);
1322 if (CORBWP(pState) != CORBRP(pState))
1323 {
1324 /*
1325 * 3.4.3 defines behaviour of immediate Command status register.
1326 */
1327 LogRel(("hda: guest has tried process immediate verb (%x) with active CORB\n", cmd));
1328 return rc;
1329 }
1330 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1331 Log(("hda: IC:%x\n", cmd));
1332 rc = pState->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
1333 if (RT_FAILURE(rc))
1334 AssertRCReturn(rc, rc);
1335 rc = pfn(&pState->Codec, cmd, &resp);
1336 if (RT_FAILURE(rc))
1337 AssertRCReturn(rc, rc);
1338 IR(pState) = (uint32_t)resp;
1339 Log(("hda: IR:%x\n", IR(pState)));
1340 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1341 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1342 return rc;
1343 }
1344 /*
1345 * when guest's read the response it should clean the IRV bit of the IRS register.
1346 */
1347 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1348 && IRS_IRV(pState))
1349 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1350 return rc;
1351}
1352
1353DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1354{
1355 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1356 {
1357 RIRBWP(pState) = 0;
1358 }
1359 /*The rest of bits are O, see 6.2.22 */
1360 return VINF_SUCCESS;
1361}
1362
1363DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1364{
1365 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1366 if (RT_FAILURE(rc))
1367 AssertRCReturn(rc, rc);
1368 switch(index)
1369 {
1370 case ICH6_HDA_REG_CORBLBASE:
1371 pState->u64CORBBase &= 0xFFFFFFFF00000000ULL;
1372 pState->u64CORBBase |= pState->au32Regs[index];
1373 break;
1374 case ICH6_HDA_REG_CORBUBASE:
1375 pState->u64CORBBase &= 0x00000000FFFFFFFFULL;
1376 pState->u64CORBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1377 break;
1378 case ICH6_HDA_REG_RIRLBASE:
1379 pState->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
1380 pState->u64RIRBBase |= pState->au32Regs[index];
1381 break;
1382 case ICH6_HDA_REG_RIRUBASE:
1383 pState->u64RIRBBase &= 0x00000000FFFFFFFFULL;
1384 pState->u64RIRBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1385 break;
1386 case ICH6_HDA_REG_DPLBASE:
1387 /* @todo: first bit has special meaning */
1388 pState->u64DPBase &= 0xFFFFFFFF00000000ULL;
1389 pState->u64DPBase |= pState->au32Regs[index];
1390 break;
1391 case ICH6_HDA_REG_DPUBASE:
1392 pState->u64DPBase &= 0x00000000FFFFFFFFULL;
1393 pState->u64DPBase |= ((uint64_t)pState->au32Regs[index] << 32);
1394 break;
1395 default:
1396 AssertMsgFailed(("Invalid index"));
1397 }
1398 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
1399 return rc;
1400}
1401
1402DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1403{
1404 uint8_t v = RIRBSTS(pState);
1405 RIRBSTS(pState) &= ~(v & u32Value);
1406
1407 return hdaProcessInterrupt(pState);
1408}
1409
1410#ifdef LOG_ENABLED
1411static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1412{
1413#if 0
1414 uint64_t addr;
1415 uint32_t len;
1416 uint32_t ioc;
1417 uint8_t bdle[16];
1418 uint32_t counter;
1419 uint32_t i;
1420 uint32_t sum = 0;
1421 Assert(pBdle && pBdle->u32BdleMaxCvi);
1422 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1423 {
1424 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), u64BaseDMA + i*16, bdle, 16);
1425 addr = *(uint64_t *)bdle;
1426 len = *(uint32_t *)&bdle[8];
1427 ioc = *(uint32_t *)&bdle[12];
1428 Log(("hda: %s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1429 sum += len;
1430 }
1431 Log(("hda: sum: %d\n", sum));
1432 for (i = 0; i < 8; ++i)
1433 {
1434 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
1435 Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pState, 4) || i == SDCTL_NUM(pState, 0)? "[C]": " ",
1436 i , counter));
1437 }
1438#endif
1439}
1440#endif
1441
1442static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1443{
1444 uint8_t bdle[16];
1445 Assert(( pStreamDesc->u64BaseDMA
1446 && pBdle
1447 && pBdle->u32BdleMaxCvi));
1448 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1449 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
1450 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
1451 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1452#ifdef LOG_ENABLED
1453 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1454#endif
1455}
1456
1457static inline uint32_t hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
1458{
1459 uint32_t cb2Copy;
1460 /*
1461 * Amounts of bytes depends on current position in buffer (u32BdleCviLen-u32BdleCviPos)
1462 */
1463 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
1464 cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1465 /*
1466 * we may increase the counter in range of [0, FIFOS + 1]
1467 */
1468 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
1469 Assert((u32SoundBackendBufferBytesAvail > 0));
1470
1471 /* sanity check to avoid overriding sound backend buffer */
1472 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
1473 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
1474
1475 if (cb2Copy <= pBdle->cbUnderFifoW)
1476 return 0;
1477 cb2Copy -= pBdle->cbUnderFifoW; /* forcely reserve amount of ureported bytes to copy */
1478 return cb2Copy;
1479}
1480
1481static inline void hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1482{
1483 Log(("hda:hdaBackendWriteTransferReported: cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1484 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1485 Assert((cbCopied));
1486 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
1487 /* Assertion!!! It was copied less than cbUnderFifoW
1488 * Probably we need to move the buffer, but it rather hard to imagine situation
1489 * why it may happen.
1490 */
1491 Assert((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy)); /* we assume that we write whole buffer including not reported bytes */
1492 if ( pBdle->cbUnderFifoW
1493 && pBdle->cbUnderFifoW <= cbCopied)
1494 Log(("hda:hdaBackendWriteTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1495
1496 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
1497 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Assumption failed */
1498
1499 /* We always increment position on DMA buffer counter because we're always reading to intermediate buffer */
1500 pBdle->u32BdleCviPos += cbArranged2Copy;
1501
1502 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
1503 /* We reports all bytes (including unreported previously) */
1504 *pu32DMACursor += cbCopied;
1505 /* reducing backend counter on amount of bytes we copied to backend */
1506 *pu32BackendBufferCapacity -= cbCopied;
1507 Log(("hda:hdaBackendWriteTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1508 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
1509}
1510
1511static inline void hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1512{
1513 Assert((cbCopied, cbArranged2Copy));
1514 *pu32BackendBufferCapacity -= cbCopied;
1515 pBdle->u32BdleCviPos += cbCopied;
1516 Log(("hda:hdaBackendReadTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1517 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
1518 pBdle->cbUnderFifoW = 0;
1519 Log(("hda:hdaBackendReadTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1520 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1521}
1522
1523static inline void hdaBackendTransferUnreported(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
1524{
1525 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1526 pBdle->u32BdleCviPos += cbCopied;
1527 pBdle->cbUnderFifoW += cbCopied;
1528 /* In case of read transaction we're always coping from backend buffer */
1529 if (pu32BackendBufferCapacity)
1530 *pu32BackendBufferCapacity -= cbCopied;
1531 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1532 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pState, pStreamDesc)));
1533}
1534static inline bool hdaIsTransferCountersOverlapped(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1535{
1536 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
1537 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
1538
1539 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1540
1541 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1542 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
1543 hdaUpdatePosBuf(pState, pStreamDesc);
1544
1545 /* don't touch BdleCvi counter on uninitialized descriptor */
1546 if ( pBdle->u32BdleCviPos
1547 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
1548 {
1549 pBdle->u32BdleCviPos = 0;
1550 pBdle->u32BdleCvi++;
1551 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
1552 pBdle->u32BdleCvi = 0;
1553 }
1554 return fOnBufferEdge;
1555}
1556
1557static inline void hdaStreamCounterUpdate(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbInc)
1558{
1559 /*
1560 * if we're under FIFO Watermark it's expected that HDA doesn't fetch anything.
1561 * (ICH6 datasheet 18.2.38)
1562 */
1563 if (!pBdle->cbUnderFifoW)
1564 {
1565 *pStreamDesc->pu32Lpib += cbInc;
1566
1567 /*
1568 * Assert. Overlapping of buffer counter shouldn't happen.
1569 */
1570 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1571
1572 hdaUpdatePosBuf(pState, pStreamDesc);
1573
1574 }
1575}
1576
1577static inline bool hdaDoNextTransferCycle(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1578{
1579 bool fDoNextTransferLoop = true;
1580 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
1581 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1582 {
1583 if ( !pBdle->cbUnderFifoW
1584 && pBdle->fBdleCviIoc)
1585 {
1586 /*
1587 * @todo - more carefully investigate BCIS flag.
1588 * Speech synthesis works fine on Mac Guest if this bit isn't set
1589 * but in general sound quality becomes lesser.
1590 */
1591 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1592
1593 /*
1594 * we should generate the interrupt if ICE bit of SDCTL register is set.
1595 */
1596 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
1597 hdaProcessInterrupt(pState);
1598 }
1599 fDoNextTransferLoop = false;
1600 }
1601 return fDoNextTransferLoop;
1602}
1603
1604/*
1605 * hdaReadAudio - copies samples from Qemu Sound back-end to DMA.
1606 * Note: this function writes immediately to DMA buffer, but "reports bytes" when all conditions meet (FIFOW)
1607 */
1608static uint32_t hdaReadAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1609{
1610 PHDABDLEDESC pBdle = &pState->stInBdle;
1611 uint32_t cbTransfered = 0;
1612 uint32_t cb2Copy = 0;
1613 uint32_t cbBackendCopy = 0;
1614
1615 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1616
1617 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1618 if (!cb2Copy)
1619 {
1620 /* if we enter here we can't report "unreported bits" */
1621 *fStop = true;
1622 goto done;
1623 }
1624
1625
1626 /*
1627 * read from backend input line to last ureported position or at the begining.
1628 */
1629 cbBackendCopy = AUD_read (pState->Codec.SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
1630 /*
1631 * write on the HDA DMA
1632 */
1633 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
1634
1635 /* Don't see reasons why cb2Copy could differ from cbBackendCopy */
1636 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
1637
1638 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pState, 0))
1639 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransfered, pu32Avail);
1640 else
1641 {
1642 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
1643 *fStop = true;
1644 }
1645 done:
1646 Assert((cbTransfered <= (SDFIFOS(pState, 0) + 1)));
1647 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransfered: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransfered));
1648 return cbTransfered;
1649}
1650
1651static uint32_t hdaWriteAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1652{
1653 PHDABDLEDESC pBdle = &pState->stOutBdle;
1654 uint32_t cbTransfered = 0;
1655 uint32_t cb2Copy = 0; /* local byte counter (on local buffer) */
1656 uint32_t cbBackendCopy = 0; /* local byte counter, how many bytes copied to backend */
1657
1658 Log(("hda:wa: CVI(cvi:%d, pos:%d, len:%d)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1659
1660 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1661
1662 /*
1663 * Copy from DMA to the corresponding hdaBuffer (if there exists some bytes from the previous not reported transfer we write to ''pBdle->cbUnderFifoW'' offset)
1664 */
1665 if (!cb2Copy)
1666 {
1667 *fStop = true;
1668 goto done;
1669 }
1670
1671 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
1672 /*
1673 * Write to audio backend. we should be sure whether we have enought bytes to copy to Audio backend.
1674 */
1675 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pState, pStreamDesc))
1676 {
1677 /*
1678 * We feed backend with new portion of fetched samples including not reported.
1679 */
1680 cbBackendCopy = AUD_write (pState->Codec.SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
1681 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransfered, pu32Avail);
1682 }
1683 else
1684 {
1685 /* Not enough bytes to be processed and reported, check luck on next enterence */
1686 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cb2Copy, NULL);
1687 *fStop = true;
1688 }
1689
1690 done:
1691 Assert((cbTransfered <= (SDFIFOS(pState, 4) + 1)));
1692 Log(("hda:wa: CVI(pos:%d, len:%d, cbTransfered:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransfered));
1693 return cbTransfered;
1694}
1695
1696DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
1697{
1698 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1699 return VINF_SUCCESS;
1700}
1701
1702static inline void hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc)
1703{
1704 Assert(( pState
1705 && pBdle
1706 && pStreamDesc
1707 && u8Strm <= 7));
1708 memset(pStreamDesc, 0, sizeof(HDASTREAMTRANSFERDESC));
1709 pStreamDesc->u8Strm = u8Strm;
1710 pStreamDesc->u32Ctl = HDA_STREAM_REG2(pState, CTL, u8Strm);
1711 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG2(pState, BDPL, u8Strm),
1712 HDA_STREAM_REG2(pState, BDPU, u8Strm));
1713 pStreamDesc->pu32Lpib = &HDA_STREAM_REG2(pState, LPIB, u8Strm);
1714 pStreamDesc->pu32Sts = &HDA_STREAM_REG2(pState, STS, u8Strm);
1715 pStreamDesc->u32Cbl = HDA_STREAM_REG2(pState, CBL, u8Strm);
1716 pStreamDesc->u32Fifos = HDA_STREAM_REG2(pState, FIFOS, u8Strm);
1717
1718 pBdle->u32BdleMaxCvi = HDA_STREAM_REG2(pState, LVI, u8Strm);
1719#ifdef LOG_ENABLED
1720 if ( pBdle
1721 && pBdle->u32BdleMaxCvi)
1722 {
1723 Log(("Initialization of transfer descriptor:\n"));
1724 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1725 }
1726#endif
1727}
1728
1729DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
1730{
1731 bool fStop = false;
1732 uint8_t u8Strm = 0;
1733 PHDABDLEDESC pBdle = NULL;
1734 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1735 HDASTREAMTRANSFERDESC stStreamDesc;
1736 uint32_t nBytes;
1737 switch (src)
1738 {
1739 case PO_INDEX:
1740 {
1741 u8Strm = 4;
1742 pBdle = &pState->stOutBdle;
1743 break;
1744 }
1745 case PI_INDEX:
1746 {
1747 u8Strm = 0;
1748 pBdle = &pState->stInBdle;
1749 break;
1750 }
1751 default:
1752 return;
1753 }
1754 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &stStreamDesc);
1755 while( avail && !fStop)
1756 {
1757 Assert ( (stStreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1758 && avail
1759 && stStreamDesc.u64BaseDMA);
1760
1761 /* Fetch the Buffer Descriptor Entry (BDE). */
1762
1763 if (hdaIsTransferCountersOverlapped(pState, pBdle, &stStreamDesc))
1764 hdaFetchBdle(pState, pBdle, &stStreamDesc);
1765 *stStreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1766 Assert((avail >= 0 && (stStreamDesc.u32Cbl >= (*stStreamDesc.pu32Lpib)))); /* sanity */
1767 uint32_t u32CblLimit = stStreamDesc.u32Cbl - (*stStreamDesc.pu32Lpib);
1768 Assert((u32CblLimit > hdaFifoWToSz(pState, &stStreamDesc)));
1769 Log(("hda: CBL=%d, LPIB=%d\n", stStreamDesc.u32Cbl, *stStreamDesc.pu32Lpib));
1770 switch (src)
1771 {
1772 case PO_INDEX:
1773 nBytes = hdaWriteAudio(pState, &stStreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1774 break;
1775 case PI_INDEX:
1776 nBytes = hdaReadAudio(pState, &stStreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1777 break;
1778 default:
1779 nBytes = 0;
1780 fStop = true;
1781 AssertMsgFailed(("Unsupported"));
1782 }
1783 Assert(nBytes <= (stStreamDesc.u32Fifos + 1));
1784 *stStreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1785
1786 /* Process end of buffer condition. */
1787 hdaStreamCounterUpdate(pState, pBdle, &stStreamDesc, nBytes);
1788 fStop = !fStop ? !hdaDoNextTransferCycle(pState, pBdle, &stStreamDesc) : fStop;
1789 }
1790}
1791
1792/**
1793 * Handle register read operation.
1794 *
1795 * Looks up and calls appropriate handler.
1796 *
1797 * @note: while implementation was detected so called "forgotten" or "hole" registers
1798 * which description is missed in RPM, datasheet or spec.
1799 *
1800 * @returns VBox status code.
1801 *
1802 * @param pState The device state structure.
1803 * @param uOffset Register offset in memory-mapped frame.
1804 * @param pv Where to fetch the value.
1805 * @param cb Number of bytes to write.
1806 * @thread EMT
1807 */
1808PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1809{
1810 int rc = VINF_SUCCESS;
1811 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1812 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1813 int index = hdaLookup(&pThis->hda, u32Offset);
1814 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1815 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1816
1817 if ( index == -1
1818 || cb > 4)
1819 LogRel(("hda: Invalid read access @0x%x(of bytes:%d)\n", u32Offset, cb));
1820
1821 if (index != -1)
1822 {
1823 uint32_t mask = 0;
1824 uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1825 uint32_t v = 0;
1826 switch(cb)
1827 {
1828 case 1: mask = 0x000000ff; break;
1829 case 2: mask = 0x0000ffff; break;
1830 case 3: mask = 0x00ffffff; break;
1831 case 4: mask = 0xffffffff; break;
1832 }
1833 mask <<= shift;
1834 rc = s_ichIntelHDRegMap[index].pfnRead(&pThis->hda, u32Offset, index, &v);
1835 *(uint32_t *)pv = (v & mask) >> shift;
1836 Log(("hda: read %s[%x/%x]\n", s_ichIntelHDRegMap[index].abbrev, v, *(uint32_t *)pv));
1837 return rc;
1838 }
1839 *(uint32_t *)pv = 0xFF;
1840 Log(("hda: hole at %X is accessed for read\n", u32Offset));
1841 return rc;
1842}
1843
1844/**
1845 * Handle register write operation.
1846 *
1847 * Looks up and calls appropriate handler.
1848 *
1849 * @returns VBox status code.
1850 *
1851 * @param pState The device state structure.
1852 * @param uOffset Register offset in memory-mapped frame.
1853 * @param pv Where to fetch the value.
1854 * @param cb Number of bytes to write.
1855 * @thread EMT
1856 */
1857PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1858{
1859 int rc = VINF_SUCCESS;
1860 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1861 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1862 int index = hdaLookup(&pThis->hda, u32Offset);
1863
1864 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1865 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1866
1867 if ( index == -1
1868 || cb > 4)
1869 LogRel(("hda: Invalid write access @0x%x(of bytes:%d)\n", u32Offset, cb));
1870
1871 if (index != -1)
1872 {
1873 uint32_t v = pThis->hda.au32Regs[index];
1874 uint32_t mask = 0;
1875 uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1876 switch(cb)
1877 {
1878 case 1: mask = 0xffffff00; break;
1879 case 2: mask = 0xffff0000; break;
1880 case 3: mask = 0xff000000; break;
1881 case 4: mask = 0x00000000; break;
1882 }
1883 mask <<= shift;
1884 *(uint32_t *)pv = ((v & mask) | (*(uint32_t *)pv & ~mask)) >> shift;
1885 rc = s_ichIntelHDRegMap[index].pfnWrite(&pThis->hda, u32Offset, index, *(uint32_t *)pv);
1886 Log(("hda: write %s:(%x) %x => %x\n", s_ichIntelHDRegMap[index].abbrev, *(uint32_t *)pv, v, pThis->hda.au32Regs[index]));
1887 return rc;
1888 }
1889 Log(("hda: hole at %X is accessed for write\n", u32Offset));
1890 return rc;
1891}
1892
1893/**
1894 * Callback function for mapping a PCI I/O region.
1895 *
1896 * @return VBox status code.
1897 * @param pPciDev Pointer to PCI device.
1898 * Use pPciDev->pDevIns to get the device instance.
1899 * @param iRegion The region number.
1900 * @param GCPhysAddress Physical address of the region.
1901 * If iType is PCI_ADDRESS_SPACE_IO, this is an
1902 * I/O port, else it's a physical address.
1903 * This address is *NOT* relative
1904 * to pci_mem_base like earlier!
1905 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
1906 */
1907static DECLCALLBACK(int) hdaMap (PPCIDEVICE pPciDev, int iRegion,
1908 RTGCPHYS GCPhysAddress, uint32_t cb,
1909 PCIADDRESSSPACE enmType)
1910{
1911 int rc;
1912 PPDMDEVINS pDevIns = pPciDev->pDevIns;
1913 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
1914 PCIINTELHDLinkState *pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);
1915
1916 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
1917 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, 0,
1918 hdaMMIOWrite, hdaMMIORead, NULL, "ICH6_HDA");
1919
1920 if (RT_FAILURE(rc))
1921 return rc;
1922
1923 pThis->hda.addrMMReg = GCPhysAddress;
1924 return VINF_SUCCESS;
1925}
1926
1927/**
1928 * Saves a state of the HDA device.
1929 *
1930 * @returns VBox status code.
1931 * @param pDevIns The device instance.
1932 * @param pSSMHandle The handle to save the state to.
1933 */
1934static DECLCALLBACK(int) hdaSaveExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1935{
1936 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1937 /* Save Codec nodes states */
1938 codecSaveState(&pThis->hda.Codec, pSSMHandle);
1939 /* Save MMIO registers */
1940 SSMR3PutMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
1941 /* Save HDA dma counters */
1942 SSMR3PutMem (pSSMHandle, &pThis->hda.stOutBdle, sizeof (HDABDLEDESC));
1943 SSMR3PutMem (pSSMHandle, &pThis->hda.stMicBdle, sizeof (HDABDLEDESC));
1944 SSMR3PutMem (pSSMHandle, &pThis->hda.stInBdle, sizeof (HDABDLEDESC));
1945 return VINF_SUCCESS;
1946}
1947
1948/**
1949 * Loads a saved HDA device state.
1950 *
1951 * @returns VBox status code.
1952 * @param pDevIns The device instance.
1953 * @param pSSMHandle The handle to the saved state.
1954 * @param uVersion The data unit version number.
1955 * @param uPass The data pass.
1956 */
1957static DECLCALLBACK(int) hdaLoadExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1958 uint32_t uVersion, uint32_t uPass)
1959{
1960 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1961 /* Load Codec nodes states */
1962 AssertMsgReturn (uVersion == HDA_SSM_VERSION, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1963 Assert (uPass == SSM_PASS_FINAL); NOREF(uPass);
1964
1965 codecLoadState(&pThis->hda.Codec, pSSMHandle);
1966 /* Load MMIO registers */
1967 SSMR3GetMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
1968 /* Load HDA dma counters */
1969 SSMR3GetMem (pSSMHandle, &pThis->hda.stOutBdle, sizeof (HDABDLEDESC));
1970 SSMR3GetMem (pSSMHandle, &pThis->hda.stMicBdle, sizeof (HDABDLEDESC));
1971 SSMR3GetMem (pSSMHandle, &pThis->hda.stInBdle, sizeof (HDABDLEDESC));
1972
1973 AUD_set_active_in(pThis->hda.Codec.SwVoiceIn, SDCTL(&pThis->hda, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1974 AUD_set_active_out(pThis->hda.Codec.SwVoiceOut, SDCTL(&pThis->hda, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1975
1976 pThis->hda.u64CORBBase = CORBLBASE(&pThis->hda);
1977 pThis->hda.u64CORBBase |= ((uint64_t)CORBUBASE(&pThis->hda)) << 32;
1978 pThis->hda.u64RIRBBase = RIRLBASE(&pThis->hda);
1979 pThis->hda.u64RIRBBase |= ((uint64_t)RIRUBASE(&pThis->hda)) << 32;
1980 pThis->hda.u64DPBase = DPLBASE(&pThis->hda);
1981 pThis->hda.u64DPBase |= ((uint64_t)DPUBASE(&pThis->hda)) << 32;
1982 return VINF_SUCCESS;
1983}
1984
1985/**
1986 * Reset notification.
1987 *
1988 * @returns VBox status.
1989 * @param pDevIns The device instance data.
1990 *
1991 * @remark The original sources didn't install a reset handler, but it seems to
1992 * make sense to me so we'll do it.
1993 */
1994static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
1995{
1996 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1997 GCAP(&pThis->hda) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
1998 VMIN(&pThis->hda) = 0x00; /* see 6.2.2 */
1999 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
2000 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
2001 OUTPAY(&pThis->hda) = 0x003C; /* see 6.2.4 */
2002 INPAY(&pThis->hda) = 0x001D; /* see 6.2.5 */
2003 pThis->hda.au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
2004 pThis->hda.au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
2005 CORBRP(&pThis->hda) = 0x0;
2006 RIRBWP(&pThis->hda) = 0x0;
2007
2008 Log(("hda: inter HDA reset.\n"));
2009 pThis->hda.cbCorbBuf = 256 * sizeof(uint32_t);
2010
2011 if (pThis->hda.pu32CorbBuf)
2012 memset(pThis->hda.pu32CorbBuf, 0, pThis->hda.cbCorbBuf);
2013 else
2014 pThis->hda.pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->hda.cbCorbBuf);
2015
2016 pThis->hda.cbRirbBuf = 256 * sizeof(uint64_t);
2017 if (pThis->hda.pu64RirbBuf)
2018 memset(pThis->hda.pu64RirbBuf, 0, pThis->hda.cbRirbBuf);
2019 else
2020 pThis->hda.pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->hda.cbRirbBuf);
2021
2022 pThis->hda.u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
2023
2024 HDABDLEDESC stEmptyBdle;
2025 for(uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
2026 {
2027 HDASTREAMTRANSFERDESC stStreamDesc;
2028 PHDABDLEDESC pBdle = NULL;
2029 if (u8Strm == 0)
2030 pBdle = &pThis->hda.stInBdle;
2031 else if(u8Strm == 4)
2032 pBdle = &pThis->hda.stOutBdle;
2033 else
2034 {
2035 memset(&stEmptyBdle, 0, sizeof(HDABDLEDESC));
2036 pBdle = &stEmptyBdle;
2037 }
2038 hdaInitTransferDescriptor(&pThis->hda, pBdle, u8Strm, &stStreamDesc);
2039 /* hdaStreamReset prevents changing SRST bit, so we zerro it here forcely. */
2040 HDA_STREAM_REG2(&pThis->hda, CTL, u8Strm) = 0;
2041 hdaStreamReset(&pThis->hda, pBdle, &stStreamDesc, u8Strm);
2042 }
2043
2044 /* emulateion of codec "wake up" HDA spec (5.5.1 and 6.5)*/
2045 STATESTS(&pThis->hda) = 0x1;
2046
2047 Log(("hda: reset finished\n"));
2048}
2049
2050/**
2051 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2052 */
2053static DECLCALLBACK(void *) hdaQueryInterface (struct PDMIBASE *pInterface,
2054 const char *pszIID)
2055{
2056 PCIINTELHDLinkState *pThis = RT_FROM_MEMBER(pInterface, PCIINTELHDLinkState, hda.IBase);
2057 Assert(&pThis->hda.IBase == pInterface);
2058
2059 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->hda.IBase);
2060 return NULL;
2061}
2062
2063//#define HDA_AS_PCI_EXPRESS
2064
2065/**
2066 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2067 */
2068static DECLCALLBACK(int) hdaConstruct (PPDMDEVINS pDevIns, int iInstance,
2069 PCFGMNODE pCfgHandle)
2070{
2071 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2072 INTELHDLinkState *s = &pThis->hda;
2073 int rc;
2074
2075 Assert(iInstance == 0);
2076 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2077
2078 /*
2079 * Validations.
2080 */
2081 if (!CFGMR3AreValuesValid (pCfgHandle, "\0"))
2082 return PDMDEV_SET_ERROR (pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2083 N_ ("Invalid configuration for the INTELHD device"));
2084
2085 // ** @todo r=michaln: This device may need R0/RC enabling, especially if guests
2086 // poll some register(s).
2087
2088 /*
2089 * Initialize data (most of it anyway).
2090 */
2091 s->pDevIns = pDevIns;
2092 /* IBase */
2093 s->IBase.pfnQueryInterface = hdaQueryInterface;
2094
2095 /* PCI Device (the assertions will be removed later) */
2096 PCIDevSetVendorId (&pThis->dev, HDA_PCI_VENDOR_ID); /* nVidia */
2097 PCIDevSetDeviceId (&pThis->dev, HDA_PCI_DEICE_ID); /* HDA */
2098
2099 PCIDevSetCommand (&pThis->dev, 0x0000); /* 04 rw,ro - pcicmd. */
2100 PCIDevSetStatus (&pThis->dev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
2101 PCIDevSetRevisionId (&pThis->dev, 0x01); /* 08 ro - rid. */
2102 PCIDevSetClassProg (&pThis->dev, 0x00); /* 09 ro - pi. */
2103 PCIDevSetClassSub (&pThis->dev, 0x03); /* 0a ro - scc; 03 == HDA. */
2104 PCIDevSetClassBase (&pThis->dev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
2105 PCIDevSetHeaderType (&pThis->dev, 0x00); /* 0e ro - headtyp. */
2106 PCIDevSetBaseAddress (&pThis->dev, 0, /* 10 rw - MMIO */
2107 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
2108 PCIDevSetInterruptLine (&pThis->dev, 0x00); /* 3c rw. */
2109 PCIDevSetInterruptPin (&pThis->dev, 0x01); /* 3d ro - INTA#. */
2110
2111#if defined(HDA_AS_PCI_EXPRESS)
2112 PCIDevSetCapabilityList (&pThis->dev, 0x80);
2113#elif defined(VBOX_WITH_MSI_DEVICES)
2114 PCIDevSetCapabilityList (&pThis->dev, 0x60);
2115#else
2116 PCIDevSetCapabilityList (&pThis->dev, 0x50); /* ICH6 datasheet 18.1.16 */
2117#endif
2118
2119 //** @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
2120 // of these values needs to be properly documented!
2121 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
2122 PCIDevSetByte(&pThis->dev, 0x40, 0x01);
2123
2124 /* Power Management */
2125 PCIDevSetByte(&pThis->dev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
2126 PCIDevSetByte(&pThis->dev, 0x50 + 1, 0x0); /* next */
2127 PCIDevSetWord(&pThis->dev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
2128
2129#ifdef HDA_AS_PCI_EXPRESS
2130 /* PCI Express */
2131 PCIDevSetByte (&pThis->dev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
2132 PCIDevSetByte (&pThis->dev, 0x80 + 1, 0x60); /* next */
2133 /* Device flags */
2134 PCIDevSetWord (&pThis->dev, 0x80 + 2,
2135 /* version */ 0x1 |
2136 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
2137 /* MSI */ (100) << 9
2138 );
2139 /* Device capabilities */
2140 PCIDevSetDWord (&pThis->dev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
2141 /* Device control */
2142 PCIDevSetWord (&pThis->dev, 0x80 + 8, 0);
2143 /* Device status */
2144 PCIDevSetWord (&pThis->dev, 0x80 + 10, 0);
2145 /* Link caps */
2146 PCIDevSetDWord (&pThis->dev, 0x80 + 12, 0);
2147 /* Link control */
2148 PCIDevSetWord (&pThis->dev, 0x80 + 16, 0);
2149 /* Link status */
2150 PCIDevSetWord (&pThis->dev, 0x80 + 18, 0);
2151 /* Slot capabilities */
2152 PCIDevSetDWord (&pThis->dev, 0x80 + 20, 0);
2153 /* Slot control */
2154 PCIDevSetWord (&pThis->dev, 0x80 + 24, 0);
2155 /* Slot status */
2156 PCIDevSetWord (&pThis->dev, 0x80 + 26, 0);
2157 /* Root control */
2158 PCIDevSetWord (&pThis->dev, 0x80 + 28, 0);
2159 /* Root capabilities */
2160 PCIDevSetWord (&pThis->dev, 0x80 + 30, 0);
2161 /* Root status */
2162 PCIDevSetDWord (&pThis->dev, 0x80 + 32, 0);
2163 /* Device capabilities 2 */
2164 PCIDevSetDWord (&pThis->dev, 0x80 + 36, 0);
2165 /* Device control 2 */
2166 PCIDevSetQWord (&pThis->dev, 0x80 + 40, 0);
2167 /* Link control 2 */
2168 PCIDevSetQWord (&pThis->dev, 0x80 + 48, 0);
2169 /* Slot control 2 */
2170 PCIDevSetWord (&pThis->dev, 0x80 + 56, 0);
2171#endif
2172
2173 /*
2174 * Register the PCI device.
2175 */
2176 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
2177 if (RT_FAILURE (rc))
2178 return rc;
2179
2180 rc = PDMDevHlpPCIIORegionRegister (pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM,
2181 hdaMap);
2182 if (RT_FAILURE (rc))
2183 return rc;
2184
2185#ifdef VBOX_WITH_MSI_DEVICES
2186 PDMMSIREG aMsiReg;
2187
2188 RT_ZERO(aMsiReg);
2189 aMsiReg.cMsiVectors = 1;
2190 aMsiReg.iMsiCapOffset = 0x60;
2191 aMsiReg.iMsiNextOffset = 0x50;
2192 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
2193 if (RT_FAILURE (rc))
2194 {
2195 LogRel(("Chipset cannot do MSI: %Rrc\n", rc));
2196 PCIDevSetCapabilityList (&pThis->dev, 0x50);
2197 }
2198#endif
2199
2200 rc = PDMDevHlpSSMRegister (pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
2201 if (RT_FAILURE (rc))
2202 return rc;
2203
2204 /*
2205 * Attach driver.
2206 */
2207 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase,
2208 &s->pDrvBase, "Audio Driver Port");
2209 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2210 Log (("hda: No attached driver!\n"));
2211 else if (RT_FAILURE (rc))
2212 {
2213 AssertMsgFailed (("Failed to attach INTELHD LUN #0! rc=%Rrc\n", rc));
2214 return rc;
2215 }
2216
2217
2218
2219 pThis->hda.Codec.pHDAState = (void *)&pThis->hda;
2220 rc = codecConstruct(pDevIns, &pThis->hda.Codec, /* ALC885_CODEC */ STAC9220_CODEC);
2221 if (RT_FAILURE(rc))
2222 AssertRCReturn(rc, rc);
2223
2224 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
2225 verb F20 should provide device/codec recognition. */
2226 Assert(pThis->hda.Codec.u16VendorId);
2227 Assert(pThis->hda.Codec.u16DeviceId);
2228 PCIDevSetSubSystemVendorId (&pThis->dev, pThis->hda.Codec.u16VendorId); /* 2c ro - intel.) */
2229 PCIDevSetSubSystemId (&pThis->dev, pThis->hda.Codec.u16DeviceId); /* 2e ro. */
2230
2231 hdaReset (pDevIns);
2232 pThis->hda.Codec.id = 0;
2233 pThis->hda.Codec.pfnTransfer = hdaTransfer;
2234 pThis->hda.Codec.pfnReset = hdaCodecReset;
2235 /*
2236 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
2237 * hdaReset shouldn't affects these registers.
2238 */
2239 WAKEEN(&pThis->hda) = 0x0;
2240 STATESTS(&pThis->hda) = 0x0;
2241
2242 return VINF_SUCCESS;
2243}
2244
2245/**
2246 * @interface_method_impl{PDMDEVREG,pfnDestruct}
2247 */
2248static DECLCALLBACK(int) hdaDestruct (PPDMDEVINS pDevIns)
2249{
2250 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2251
2252 int rc = codecDestruct(&pThis->hda.Codec);
2253 AssertRC(rc);
2254 if (pThis->hda.pu32CorbBuf)
2255 RTMemFree(pThis->hda.pu32CorbBuf);
2256 if (pThis->hda.pu64RirbBuf)
2257 RTMemFree(pThis->hda.pu64RirbBuf);
2258 return VINF_SUCCESS;
2259}
2260
2261/**
2262 * The device registration structure.
2263 */
2264const PDMDEVREG g_DeviceICH6_HDA =
2265{
2266 /* u32Version */
2267 PDM_DEVREG_VERSION,
2268 /* szName */
2269 "hda",
2270 /* szRCMod */
2271 "",
2272 /* szR0Mod */
2273 "",
2274 /* pszDescription */
2275 "ICH IntelHD Audio Controller",
2276 /* fFlags */
2277 PDM_DEVREG_FLAGS_DEFAULT_BITS,
2278 /* fClass */
2279 PDM_DEVREG_CLASS_AUDIO,
2280 /* cMaxInstances */
2281 1,
2282 /* cbInstance */
2283 sizeof(PCIINTELHDLinkState),
2284 /* pfnConstruct */
2285 hdaConstruct,
2286 /* pfnDestruct */
2287 hdaDestruct,
2288 /* pfnRelocate */
2289 NULL,
2290 /* pfnIOCtl */
2291 NULL,
2292 /* pfnPowerOn */
2293 NULL,
2294 /* pfnReset */
2295 hdaReset,
2296 /* pfnSuspend */
2297 NULL,
2298 /* pfnResume */
2299 NULL,
2300 /* pfnAttach */
2301 NULL,
2302 /* pfnDetach */
2303 NULL,
2304 /* pfnQueryInterface. */
2305 NULL,
2306 /* pfnInitComplete */
2307 NULL,
2308 /* pfnPowerOff */
2309 NULL,
2310 /* pfnSoftReset */
2311 NULL,
2312 /* u32VersionEnd */
2313 PDM_DEVREG_VERSION
2314};
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