DevIchIntelHDA.cpp@ 31808

Last change on this file since 31808 was 31771, checked in by vboxsync, 14 years ago
Audio/HDA: introduces saved states.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 79.7 KB

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1	/* $Id: DevIchIntelHDA.cpp 31771 2010-08-19 09:15:42Z vboxsync $ */
2	/** @file
3	* DevIchIntelHD - VBox ICH Intel HD Audio Controller.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV_AUDIO
22	#include <VBox/pdmdev.h>
23	#include <iprt/assert.h>
24	#include <iprt/uuid.h>
25	#include <iprt/string.h>
26	#include <iprt/mem.h>
27	#include <iprt/asm.h>
28
29	#include "../Builtins.h"
30
31	extern "C" {
32	#include "audio.h"
33	}
34	#include "DevCodec.h"
35
36	#undef LOG_VOICES
37	#ifndef VBOX
38	//#define USE_MIXER
39	#else
40	#define USE_MIXER
41	#endif
42
43	#define HDA_SSM_VERSION 1
44	PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
45	PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
46	static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns);
47
48	/* Registers */
49	#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
50	#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
51	#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
52	#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
53	#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
54	#define HDA_REG_IND(pState, x) ((pState)->au32Regs[(x)])
55	#define HDA_REG(pState, x) (HDA_REG_IND((pState), HDA_REG_IND_NAME(x)))
56	#define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
57	#define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
58	#define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
59
60	#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
61	#define GCAP(pState) (HDA_REG((pState), GCAP))
62
63	#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
64	#define VMIN(pState) (HDA_REG((pState), VMIN))
65
66	#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
67	#define VMAJ(pState) (HDA_REG((pState), VMAJ))
68
69	#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
70	#define OUTPAY(pState) (HDA_REG((pState), OUTPAY))
71
72	#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
73	#define INPAY(pState) (HDA_REG((pState), INPAY))
74
75	#define ICH6_HDA_REG_GCTL (5)
76	#define ICH6_HDA_GCTL_RST_SHIFT (0)
77	#define ICH6_HDA_GCTL_FSH_SHIFT (1)
78	#define ICH6_HDA_GCTL_UR_SHIFT (8)
79	#define GCTL(pState) (HDA_REG((pState), GCTL))
80
81	#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
82	#define WAKEEN(pState) (HDA_REG((pState), WAKEEN))
83
84	#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
85	#define STATESTS(pState) (HDA_REG((pState), STATESTS))
86	#define ICH6_HDA_STATES_SCSF 0x7
87
88	#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
89	#define ICH6_HDA_GSTS_FSH_SHIFT (1)
90	#define GSTS(pState) (HDA_REG(pState, GSTS))
91
92	#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
93	#define ICH6_HDA_INTCTL_GIE_SHIFT 31
94	#define ICH6_HDA_INTCTL_CIE_SHIFT 30
95	#define ICH6_HDA_INTCTL_S0_SHIFT (0)
96	#define ICH6_HDA_INTCTL_S1_SHIFT (1)
97	#define ICH6_HDA_INTCTL_S2_SHIFT (2)
98	#define ICH6_HDA_INTCTL_S3_SHIFT (3)
99	#define ICH6_HDA_INTCTL_S4_SHIFT (4)
100	#define ICH6_HDA_INTCTL_S5_SHIFT (5)
101	#define ICH6_HDA_INTCTL_S6_SHIFT (6)
102	#define ICH6_HDA_INTCTL_S7_SHIFT (7)
103	#define INTCTL(pState) (HDA_REG((pState), INTCTL))
104	#define INTCTL_GIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, GIE))
105	#define INTCTL_CIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, CIE))
106	#define INTCTL_SX(pState, X) (HDA_REG_FLAG_VALUE((pState), INTCTL, S##X))
107	#define INTCTL_SALL(pState) (INTCTL((pState)) & 0xFF)
108
109	/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
110	* ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
111	* the datasheet.
112	*/
113	#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
114	#define SSYNC(pState) (HDA_REG((pState), SSYNC))
115
116	#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
117	#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
118	#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
119	#define ICH6_HDA_INTSTS_S0_SHIFT (0)
120	#define ICH6_HDA_INTSTS_S1_SHIFT (1)
121	#define ICH6_HDA_INTSTS_S2_SHIFT (2)
122	#define ICH6_HDA_INTSTS_S3_SHIFT (3)
123	#define ICH6_HDA_INTSTS_S4_SHIFT (4)
124	#define ICH6_HDA_INTSTS_S5_SHIFT (5)
125	#define ICH6_HDA_INTSTS_S6_SHIFT (6)
126	#define ICH6_HDA_INTSTS_S7_SHIFT (7)
127	#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
128	#define INTSTS(pState) (HDA_REG((pState), INTSTS))
129	#define INTSTS_GIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, GIS)
130	#define INTSTS_CIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, CIS)
131	#define INTSTS_SX(pState, X) (HDA_REG_FLAG_VALUE(pState), INTSTS, S##X)
132	#define INTSTS_SANY(pState) (INTSTS((pState)) & 0xFF)
133
134	#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
135	#define CORBLBASE(pState) (HDA_REG((pState), CORBLBASE))
136	#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
137	#define CORBUBASE(pState) (HDA_REG((pState), CORBUBASE))
138	#define ICH6_HDA_REG_CORBWP 15 /* 48 */
139	#define ICH6_HDA_REG_CORBRP 16 /* 4A */
140	#define ICH6_HDA_CORBRP_RST_SHIFT 15
141	#define ICH6_HDA_CORBRP_WP_SHIFT 0
142	#define ICH6_HDA_CORBRP_WP_MASK 0xFF
143
144	#define CORBRP(pState) (HDA_REG(pState, CORBRP))
145	#define CORBWP(pState) (HDA_REG(pState, CORBWP))
146
147	#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
148	#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
149	#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
150
151	#define CORBCTL(pState) (HDA_REG(pState, CORBCTL))
152
153
154	#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
155	#define CORBSTS(pState) (HDA_REG(pState, CORBSTS))
156	#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
157
158	#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
159	#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
160	#define ICH6_HDA_CORBSIZE_SZ 0x3
161	#define CORBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
162	#define CORBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
163	/* till ich 10 sizes of CORB and RIRB are harcoded to 256 in real hw */
164
165	#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
166	#define RIRLBASE(pState) (HDA_REG((pState), RIRLBASE))
167
168	#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
169	#define RIRUBASE(pState) (HDA_REG((pState), RIRUBASE))
170
171	#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
172	#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
173	#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
174	#define RIRBWP(pState) (HDA_REG(pState, RIRBWP))
175
176	#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
177	#define RINTCNT(pState) (HDA_REG((pState), RINTCNT))
178	#define RINTCNT_N(pState) (RINTCNT((pState)) & 0xff)
179
180	#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
181	#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
182	#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
183	#define ICH6_HDA_ROI_DMA_SHIFT (2)
184	#define RIRBCTL(pState) (HDA_REG((pState), RIRBCTL))
185	#define RIRBCTL_RIRB_RIC(pState) (HDA_REG_FLAG_VALUE(pState, RIRBCTL, RIC))
186	#define RIRBCTL_RIRB_DMA(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, DMA)
187	#define RIRBCTL_ROI(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, ROI))
188
189	#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
190	#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
191	#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
192	#define RIRBSTS(pState) (HDA_REG(pState, RIRBSTS))
193	#define RIRBSTS_RINTFL(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RINTFL))
194	#define RIRBSTS_RIRBOIS(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RIRBOIS))
195
196	#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
197	#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
198	#define ICH6_HDA_RIRBSIZE_SZ 0x3
199
200	#define RIRBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
201	#define RIRBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
202
203
204	#define ICH6_HDA_REG_IC 27 /* 0x60 */
205	#define IC(pState) (HDA_REG(pState, IC))
206	#define ICH6_HDA_REG_IR 28 /* 0x64 */
207	#define IR(pState) (HDA_REG(pState, IR))
208	#define ICH6_HDA_REG_IRS 29 /* 0x68 */
209	#define ICH6_HDA_IRS_ICB_SHIFT (0)
210	#define ICH6_HDA_IRS_IRV_SHIFT (1)
211	#define IRS(pState) (HDA_REG(pState, IRS))
212	#define IRS_ICB(pState) (HDA_REG_FLAG_VALUE(pState, IRS, ICB))
213	#define IRS_IRV(pState) (HDA_REG_FLAG_VALUE(pState, IRS, IRV))
214
215	#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
216	#define DPLBASE(pState) (HDA_REG((pState), DPLBASE))
217	#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
218	#define DPUBASE(pState) (HDA_REG((pState), DPUBASE))
219
220	#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
221	#define HDA_STREAM_REG(pState, name, num) (HDA_REG((pState), N_(HDA_STREAM_REG_DEF(name, num))))
222
223	#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
224	#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
225	#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
226	#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
227	#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
228	#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
229	#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
230	#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
231
232	#define SD(func, num) SD##num##func
233	#define SDCTL(pState, num) HDA_REG((pState), SD(CTL, num))
234	#define SDCTL_NUM(pState, num) ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
235	#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
236	#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
237	#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
238	#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
239	#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
240	#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
241	#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
242
243	#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
244	#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
245	#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
246	#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
247	#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
248	#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
249	#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
250	#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
251
252	#define SDSTS(pState, num) HDA_REG((pState), SD(STS, num))
253	#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
254	#define ICH6_HDA_SDSTS_DE_SHIFT (4)
255	#define ICH6_HDA_SDSTS_FE_SHIFT (3)
256	#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
257
258	#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
259	#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
260	#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
261	#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
262	#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
263	#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
264	#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
265	#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
266
267	#define SDLPIB(pState, num) HDA_REG((pState), SD(LPIB, num))
268
269	#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
270	#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
271	#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
272	#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
273	#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
274	#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
275	#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
276	#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
277
278	#define SDLCBL(pState, num) HDA_REG((pState), SD(CBL, num))
279
280	#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
281	#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
282	#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
283	#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
284	#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
285	#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
286	#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
287	#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
288
289	#define SDLVI(pState, num) HDA_REG((pState), SD(LVI, num))
290
291	#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
292	#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
293	#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
294	#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
295	#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
296	#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
297	#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
298	#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
299
300	#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
301	#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
302	#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
303	#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
304	#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
305	#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
306	#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
307	#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
308
309	#define SDFIFOS(pState, num) HDA_REG((pState), SD(FIFOS, num))
310
311	#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
312	#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
313	#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
314	#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
315	#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
316	#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
317	#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
318	#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
319
320	#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
321	#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
322	#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
323	#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
324	#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
325	#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
326	#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
327	#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
328
329	#define SDBDPL(pState, num) HDA_REG((pState), SD(BDPL, num))
330
331	#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
332	#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
333	#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
334	#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
335	#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
336	#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
337	#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
338	#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
339
340	#define SDBDPU(pState, num) HDA_REG((pState), SD(BDPU, num))
341
342	/* Predicates */
343
344	typedef struct HDABDLEDESC
345	{
346	uint64_t u64BdleCviAddr;
347	uint32_t u32BdleMaxCvi;
348	uint32_t u32BdleCvi;
349	uint32_t u32BdleCviLen;
350	uint32_t u32BdleCviPos;
351	bool fBdleCviIoc;
352	} HDABDLEDESC, *PHDABDLEDESC;
353
354	typedef struct INTELHDLinkState
355	{
356	/** Pointer to the device instance. */
357	PPDMDEVINSR3 pDevIns;
358	/** Pointer to the connector of the attached audio driver. */
359	PPDMIAUDIOCONNECTOR pDrv;
360	/** Pointer to the attached audio driver. */
361	PPDMIBASE pDrvBase;
362	/** The base interface for LUN\#0. */
363	PDMIBASE IBase;
364	RTGCPHYS addrMMReg;
365	uint32_t au32Regs[113];
366	HDABDLEDESC stInBdle;
367	HDABDLEDESC stOutBdle;
368	HDABDLEDESC stMicBdle;
369	/* Interrupt on completition */
370	bool fCviIoc;
371	uint64_t u64CORBBase;
372	uint64_t u64RIRBBase;
373	uint64_t u64DPBase;
374	/* pointer on CORB buf */
375	uint32_t *pu32CorbBuf;
376	/* size in bytes of CORB buf */
377	uint32_t cbCorbBuf;
378	/* pointer on RIRB buf */
379	uint64_t *pu64RirbBuf;
380	/* size in bytes of RIRB buf */
381	uint32_t cbRirbBuf;
382	/* indicates if HDA in reset. */
383	bool fInReset;
384	CODECState Codec;
385	uint8_t u8Counter;
386	uint8_t u8StreamsInReset;
387	} INTELHDLinkState;
388
389	#define ICH6_HDASTATE_2_DEVINS(pINTELHD) ((pINTELHD)->pDevIns)
390	#define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PCIINTELHDLinkState *)(pPciDev))
391
392
393
394
395	typedef struct PCIINTELHDLinkState
396	{
397	PCIDevice dev;
398	INTELHDLinkState hda;
399	} PCIINTELHDLinkState;
400
401	DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
402	DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
403	DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
404	DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
405	DECLCALLBACK(int)hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
406	DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
407	DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
408	DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
409	DECLCALLBACK(int)hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
410	DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
411	DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
412	DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
413	DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
414	DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
415	DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
416	DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
417	DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
418	DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
419
420	DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
421	DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
422	DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
423	DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
424	DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
425	DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
426	DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
427	DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
428	DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
429	DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
430	DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
431	DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
432	DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
433	static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset);
434	static void fetch_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
435
436	/* see 302349 p 6.2*/
437	const static struct stIchIntelHDRegMap
438	{
439	/** Register offset in the register space. */
440	uint32_t offset;
441	/** Size in bytes. Registers of size > 4 are in fact tables. */
442	uint32_t size;
443	/** Readable bits. */
444	uint32_t readable;
445	/** Writable bits. */
446	uint32_t writable;
447	/** Read callback. */
448	int (pfnRead)(INTELHDLinkState pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
449	/** Write callback. */
450	int (pfnWrite)(INTELHDLinkState pState, uint32_t offset, uint32_t index, uint32_t u32Value);
451	/** Abbreviated name. */
452	const char *abbrev;
453	/** Full name. */
454	const char *name;
455	} s_ichIntelHDRegMap[] =
456	{
457	/* offset size read mask write mask read callback write callback abbrev full name */
458	/------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------/
459	{ 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
460	{ 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
461	{ 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
462	{ 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
463	{ 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
464	{ 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
465	{ 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
466	{ 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
467	{ 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
468	{ 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
469	{ 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
470	//** @todo r=michaln: Are guests really not reading the WALCLK register at all?
471	{ 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
472	//** @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
473	{ 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
474	{ 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
475	{ 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
476	{ 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
477	{ 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
478	{ 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
479	{ 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
480	{ 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
481	{ 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
482	{ 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
483	{ 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8, hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
484	{ 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
485	{ 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
486	{ 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
487	{ 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
488	{ 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
489	{ 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
490	{ 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadU16 , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
491	{ 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
492	{ 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
493
494	{ 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
495	{ 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
496	{ 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
497	{ 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
498	{ 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
499	{ 0x0008E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOW", "ISD0 FIFO Watermark" },
500	{ 0x00090, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
501	{ 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FMT" , "ISD0 Format" },
502	{ 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
503	{ 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
504
505	{ 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
506	{ 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
507	{ 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
508	{ 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
509	{ 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
510	{ 0x000AE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOW", "ISD1 FIFO Watermark" },
511	{ 0x000B0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
512	{ 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FMT" , "ISD1 Format" },
513	{ 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
514	{ 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
515
516	{ 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
517	{ 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
518	{ 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
519	{ 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
520	{ 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
521	{ 0x000CE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOW", "ISD2 FIFO Watermark" },
522	{ 0x000D0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
523	{ 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FMT" , "ISD2 Format" },
524	{ 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
525	{ 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
526
527	{ 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
528	{ 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
529	{ 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
530	{ 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
531	{ 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
532	{ 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
533	{ 0x000F0, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
534	{ 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FMT" , "ISD3 Format" },
535	{ 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
536	{ 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
537
538	{ 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
539	{ 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
540	{ 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
541	{ 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
542	{ 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
543	{ 0x0010E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FIFOW", "OSD0 FIFO Watermark" },
544	{ 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FIFOS", "OSD0 FIFO Size" },
545	{ 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD0FMT" , "OSD0 Format" },
546	{ 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
547	{ 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
548
549	{ 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
550	{ 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
551	{ 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
552	{ 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
553	{ 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
554	{ 0x0012E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FIFOW", "OSD1 FIFO Watermark" },
555	{ 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FIFOS", "OSD1 FIFO Size" },
556	{ 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD1FMT" , "OSD1 Format" },
557	{ 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
558	{ 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
559
560	{ 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
561	{ 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
562	{ 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
563	{ 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
564	{ 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
565	{ 0x0014E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FIFOW", "OSD2 FIFO Watermark" },
566	{ 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FIFOS", "OSD2 FIFO Size" },
567	{ 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD2FMT" , "OSD2 Format" },
568	{ 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
569	{ 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
570
571	{ 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
572	{ 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
573	{ 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
574	{ 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
575	{ 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
576	{ 0x0016E, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FIFOW", "OSD3 FIFO Watermark" },
577	{ 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FIFOS", "OSD3 FIFO Size" },
578	{ 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteU16 , "OSD3FMT" , "OSD3 Format" },
579	{ 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
580	{ 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
581	};
582
583	static int hdaProcessInterrupt(INTELHDLinkState* pState)
584	{
585	#define IS_INTERRUPT_OCCURED_AND_ENABLED(pState, num) \
586	( INTCTL_SX((pState), num) \
587	&& (SDSTS(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
588	bool fIrq = false;
589	if( INTCTL_CIE(pState)
590	&& ( RIRBSTS_RINTFL(pState)
591	\|\| RIRBSTS_RIRBOIS(pState)
592	\|\| STATESTS(pState)))
593	{
594	fIrq = true;
595	}
596	if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 0)
597	\|\| IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 4))
598	{
599	fIrq = true;
600	}
601	if (INTCTL_GIE(pState))
602	{
603	Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
604	PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pState), 0 , fIrq);
605	}
606	return VINF_SUCCESS;
607	}
608
609	static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset)
610	{
611	int index = 0;
612	//** @todo r=michaln: A linear search of an array with over 100 elements is very inefficient.
613	for (;index < (int)(sizeof(s_ichIntelHDRegMap)/sizeof(s_ichIntelHDRegMap[0])); ++index)
614	{
615	if ( u32Offset >= s_ichIntelHDRegMap[index].offset
616	&& u32Offset < s_ichIntelHDRegMap[index].offset + s_ichIntelHDRegMap[index].size)
617	{
618	return index;
619	}
620	}
621	/* Aliases HDA spec 3.3.45 */
622	switch(u32Offset)
623	{
624	case 0x2084:
625	return HDA_REG_IND_NAME(SD0LPIB);
626	case 0x20A4:
627	return HDA_REG_IND_NAME(SD1LPIB);
628	case 0x20C4:
629	return HDA_REG_IND_NAME(SD2LPIB);
630	case 0x20E4:
631	return HDA_REG_IND_NAME(SD3LPIB);
632	case 0x2104:
633	return HDA_REG_IND_NAME(SD4LPIB);
634	case 0x2124:
635	return HDA_REG_IND_NAME(SD5LPIB);
636	case 0x2144:
637	return HDA_REG_IND_NAME(SD6LPIB);
638	case 0x2164:
639	return HDA_REG_IND_NAME(SD7LPIB);
640	}
641	return -1;
642	}
643
644	static int hdaCmdSync(INTELHDLinkState *pState, bool fLocal)
645	{
646	int rc = VINF_SUCCESS;
647	if (fLocal)
648	{
649	Assert((HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)));
650	rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
651	if (RT_FAILURE(rc))
652	AssertRCReturn(rc, rc);
653	uint8_t i = 0;
654	do
655	{
656	Log(("hda: corb%02x: ", i));
657	uint8_t j = 0;
658	do
659	{
660	const char *prefix;
661	if ((i + j) == CORBRP(pState))
662	prefix = "[R]";
663	else if ((i + j) == CORBWP(pState))
664	prefix = "[W]";
665	else
666	prefix = " "; /* three spaces */
667	Log(("%s%08x", prefix, pState->pu32CorbBuf[i + j]));
668	j++;
669	} while (j < 8);
670	Log(("\n"));
671	i += 8;
672	} while(i != 0);
673	}
674	else
675	{
676	Assert((HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA)));
677	rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
678	if (RT_FAILURE(rc))
679	AssertRCReturn(rc, rc);
680	uint8_t i = 0;
681	do {
682	Log(("hda: rirb%02x: ", i));
683	uint8_t j = 0;
684	do {
685	const char *prefix;
686	if ((i + j) == RIRBWP(pState))
687	prefix = "[W]";
688	else
689	prefix = " ";
690	Log((" %s%016lx", prefix, pState->pu64RirbBuf[i + j]));
691	} while (++j < 8);
692	Log(("\n"));
693	i += 8;
694	} while (i != 0);
695	}
696	return rc;
697	}
698
699	#if 0
700	static int hdaUnsolictedResponse(INTELHDLinkState *pState, uint64_t pu64UnsolictedResponse)
701	{
702	uint8_t rirbWp;
703	if (!HDA_REG_FLAG_VALUE(pState, GCTL, UR))
704	{
705	Log(("hda: unsolicited response %016lx is ignored\n"));
706	return VINF_SUCCESS;
707	}
708	}
709	#endif
710
711	static int hdaCORBCmdProcess(INTELHDLinkState *pState)
712	{
713	int rc;
714	uint8_t corbRp;
715	uint8_t corbWp;
716	uint8_t rirbWp;
717
718	PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
719
720	rc = hdaCmdSync(pState, true);
721	if (RT_FAILURE(rc))
722	AssertRCReturn(rc, rc);
723	corbRp = CORBRP(pState);
724	corbWp = CORBWP(pState);
725	rirbWp = RIRBWP(pState);
726	Assert((corbWp != corbRp));
727	Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
728	while (corbRp != corbWp)
729	{
730	uint32_t cmd;
731	uint64_t resp;
732	corbRp++;
733	cmd = pState->pu32CorbBuf[corbRp];
734	rc = (pState)->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
735	if (RT_FAILURE(rc))
736	AssertRCReturn(rc, rc);
737	Assert(pfn);
738	(rirbWp)++;
739	rc = pfn(&pState->Codec, cmd, &resp);
740	if (RT_FAILURE(rc))
741	AssertRCReturn(rc, rc);
742	Log(("hda: verb:%08x->%016lx\n", cmd, resp));
743	if ( (resp & CODEC_RESPONSE_UNSOLICITED)
744	&& !HDA_REG_FLAG_VALUE(pState, GCTL, UR))
745	{
746	Log(("hda: unexpected unsolicited response.\n"));
747	pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
748	return rc;
749	}
750	pState->pu64RirbBuf[rirbWp] = resp;
751	pState->u8Counter++;
752	if (pState->u8Counter == RINTCNT_N(pState))
753	break;
754	}
755	pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
756	pState->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
757	rc = hdaCmdSync(pState, false);
758	Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
759	if (RIRBCTL_RIRB_RIC(pState))
760	{
761	RIRBSTS((pState)) \|= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
762	pState->u8Counter = 0;
763	rc = hdaProcessInterrupt(pState);
764	}
765	if (RT_FAILURE(rc))
766	AssertRCReturn(rc, rc);
767	return rc;
768	}
769
770	static void hdaStreamReset(INTELHDLinkState *pState, uint32_t u32Offset)
771	{
772	Log(("hda: reset of stream (%x) started\n", u32Offset));
773	Log(("hda: reset of stream (%x) finished\n", u32Offset));
774	}
775
776
777	DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
778	{
779	*pu32Value = 0;
780	return VINF_SUCCESS;
781	}
782	DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
783	{
784	return VINF_SUCCESS;
785	}
786	/* U8 */
787	DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
788	{
789	Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffffff00) == 0);
790	return hdaRegReadU32(pState, offset, index, pu32Value);
791	}
792
793	DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
794	{
795	Assert(((u32Value & 0xffffff00) == 0));
796	return hdaRegWriteU32(pState, offset, index, u32Value);
797	}
798	/* U16 */
799	DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
800	{
801	Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffff0000) == 0);
802	return hdaRegReadU32(pState, offset, index, pu32Value);
803	}
804
805	DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
806	{
807	Assert(((u32Value & 0xffff0000) == 0));
808	return hdaRegWriteU32(pState, offset, index, u32Value);
809	}
810
811	/* U24 */
812	DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
813	{
814	Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xff000000) == 0);
815	return hdaRegReadU32(pState, offset, index, pu32Value);
816	}
817
818	DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
819	{
820	Assert(((u32Value & 0xff000000) == 0));
821	return hdaRegWriteU32(pState, offset, index, u32Value);
822	}
823	/* U32 */
824	DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
825	{
826	*pu32Value = pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable;
827	return VINF_SUCCESS;
828	}
829
830	DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
831	{
832	pState->au32Regs[index] = (u32Value & s_ichIntelHDRegMap[index].writable)
833	\| (pState->au32Regs[index] & ~s_ichIntelHDRegMap[index].writable);
834	return VINF_SUCCESS;
835	}
836
837	DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
838	{
839	return hdaRegReadU32(pState, offset, index, pu32Value);
840	}
841
842	DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
843	{
844	if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
845	{
846	/* exit reset state */
847	GCTL(pState) \|= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
848	pState->fInReset = false;
849	}
850	else
851	{
852	/* enter reset state*/
853	if ( HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)
854	\|\| HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
855	{
856	Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
857	HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
858	HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
859	}
860	hdaReset(ICH6_HDASTATE_2_DEVINS(pState));
861	GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
862	pState->fInReset = true;
863	}
864	if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
865	{
866	/* Flush: GSTS:1 set, see 6.2.6*/
867	GSTS(pState) \|= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
868	/* DPLBASE and DPUBASE, should be initialized with initial value (see 6.2.6)*/
869	}
870	return VINF_SUCCESS;
871	}
872
873	DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
874	{
875	uint32_t v = pState->au32Regs[index];
876	uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
877	pState->au32Regs[index] = (v ^ nv) & v; /* write of 1 clears corresponding bit */
878	return VINF_SUCCESS;
879	}
880
881	DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
882	{
883	uint32_t v = 0;
884	if ( RIRBSTS_RIRBOIS(pState)
885	\|\| RIRBSTS_RINTFL(pState)
886	\|\| HDA_REG_FLAG_VALUE(pState, CORBSTS, CMEI)
887	\|\| STATESTS(pState))
888	v \|= RT_BIT(30);
889	#define HDA_IS_STREAM_EVENT(pState, stream) \
890	( (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
891	\|\| (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
892	\|\| (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
893	#define MARK_STREAM(pState, stream, v) do {(v) \|= HDA_IS_STREAM_EVENT((pState),stream) ? RT_BIT((stream)) : 0;}while(0)
894	MARK_STREAM(pState, 0, v);
895	MARK_STREAM(pState, 1, v);
896	MARK_STREAM(pState, 2, v);
897	MARK_STREAM(pState, 3, v);
898	MARK_STREAM(pState, 4, v);
899	MARK_STREAM(pState, 5, v);
900	MARK_STREAM(pState, 6, v);
901	MARK_STREAM(pState, 7, v);
902	v \|= v ? RT_BIT(31) : 0;
903	*pu32Value = v;
904	return VINF_SUCCESS;
905	}
906
907	DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
908	{
909	return hdaRegReadU16(pState, offset, index, pu32Value);
910	}
911
912	DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
913	{
914	if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
915	CORBRP(pState) = 0;
916	else
917	return hdaRegWriteU8(pState, offset, index, u32Value);
918	return VINF_SUCCESS;
919	}
920
921	DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
922	{
923	int rc = hdaRegWriteU8(pState, offset, index, u32Value);
924	AssertRC(rc);
925	if ( CORBWP(pState) != CORBRP(pState)
926	&& HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) != 0)
927	return hdaCORBCmdProcess(pState);
928	return rc;
929	}
930
931	DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
932	{
933	uint32_t v = CORBSTS(pState);
934	v = (v ^ u32Value) & v;
935	CORBSTS(pState) = v;
936	return VINF_SUCCESS;
937	}
938
939	DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
940	{
941	int rc;
942	rc = hdaRegWriteU16(pState, offset, index, u32Value);
943	if (RT_FAILURE(rc))
944	AssertRCReturn(rc, rc);
945	if (CORBWP(pState) == CORBRP(pState))
946	return VINF_SUCCESS;
947	if (!HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
948	return VINF_SUCCESS;
949	rc = hdaCORBCmdProcess(pState);
950	return rc;
951	}
952
953	DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
954	{
955	return hdaRegReadU24(pState, offset, index, pu32Value);
956	}
957	#define HDA_STREAM_BITMASK(offset) (1 << (((offset) - 0x80) >> 5))
958	#define HDA_IS_STREAM_IN_RESET(pState, offset) ((pState)->u8StreamsInReset & HDA_STREAM_BITMASK((offset)))
959	DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
960	{
961	if(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST))
962	{
963	LogRel(("hda: guest has iniated hw stream reset\n"));
964	pState->u8StreamsInReset \|= HDA_STREAM_BITMASK(offset);
965	hdaStreamReset(pState, offset);
966	HDA_REG_IND(pState, index) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
967	}
968	else if (HDA_IS_STREAM_IN_RESET(pState, offset))
969	{
970	LogRel(("hda: guest has iniated exit of stream reset\n"));
971	pState->u8StreamsInReset &= ~HDA_STREAM_BITMASK(offset);
972	HDA_REG_IND(pState, index) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
973	}
974	/* @todo: use right offsets for right streams */
975	if (u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
976	{
977	Log(("hda: DMA(%x) switched on\n", offset));
978	if (offset == 0x80)
979	{
980	AUD_set_active_in(pState->Codec.voice_pi, 1);
981	//AUD_set_active_in(pState->Codec.voice_mc, 1);
982	}
983	if (offset == 0x100)
984	{
985	uint64_t u64BaseDMA = SDBDPL(pState, 4);
986	u64BaseDMA \|= (((uint64_t)SDBDPU(pState, 4)) << 32);
987	if (u64BaseDMA)
988	{
989	//fetch_bd(pState, u64BaseDMA);
990	AUD_set_active_out(pState->Codec.voice_po, 1);
991	}
992	//SDSTS(pState, 4) \|= (1<<5);
993	}
994	}
995	else
996	{
997	Log(("hda: DMA(%x) switched off\n", offset));
998	if (offset == 0x80)
999	{
1000	AUD_set_active_in(pState->Codec.voice_pi, 0);
1001	//AUD_set_active_in(pState->Codec.voice_mc, 0);
1002	}
1003	if (offset == 0x100)
1004	{
1005	SDSTS(pState, 4) &= ~(1<<5);
1006	AUD_set_active_out(pState->Codec.voice_po, 0);
1007	}
1008	//SSYNC(pState) &= ~(1<< (offset - 0x80));
1009	}
1010	int rc = hdaRegWriteU24(pState, offset, index, u32Value);
1011	if (RT_FAILURE(rc))
1012	AssertRCReturn(rc, VINF_SUCCESS);
1013	return rc;
1014	}
1015
1016	DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1017	{
1018	uint32_t v = HDA_REG_IND(pState, index);
1019	v ^= (u32Value & v);
1020	HDA_REG_IND(pState, index) = v;
1021	hdaProcessInterrupt(pState);
1022	#if 0
1023	if ( v != u32Value
1024	&& (INTCTL_SALL(pState) & (1 << ((offset - 0x83) >> 5))))
1025	{
1026	int rc;
1027	rc = hdaProcessInterrupt(pState);
1028	if (RT_FAILURE(rc))
1029	AssertRCReturn(rc, rc);
1030	}
1031	#endif
1032	return VINF_SUCCESS;
1033	}
1034	DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1035	{
1036	int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1037	if (RT_FAILURE(rc))
1038	AssertRCReturn(rc, VINF_SUCCESS);
1039	return rc;
1040	}
1041
1042	DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1043	{
1044	int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1045	if (RT_FAILURE(rc))
1046	AssertRCReturn(rc, VINF_SUCCESS);
1047	return rc;
1048	}
1049
1050	DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1051	{
1052	int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1053	if (RT_FAILURE(rc))
1054	AssertRCReturn(rc, VINF_SUCCESS);
1055	return rc;
1056	}
1057
1058	DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1059	{
1060	int rc = VINF_SUCCESS;
1061	uint64_t resp;
1062	PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
1063	if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1064	&& !IRS_ICB(pState))
1065	{
1066	uint32_t cmd = IC(pState);
1067	IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1068	Log(("hda: IC:%x\n", cmd));
1069	rc = pState->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
1070	if (RT_FAILURE(rc))
1071	AssertRCReturn(rc, rc);
1072	rc = pfn(&pState->Codec, cmd, &resp);
1073	if (RT_FAILURE(rc))
1074	AssertRCReturn(rc, rc);
1075	IR(pState) = (uint32_t)resp;
1076	Log(("hda: IR:%x\n", IR(pState)));
1077	IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* clear busy, result is ready */
1078	return rc;
1079	}
1080	if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1081	&& IRS_IRV(pState))
1082	IRS(pState) ^= HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1083	return rc;
1084	}
1085
1086	DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1087	{
1088	if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1089	{
1090	RIRBWP(pState) = 0;
1091	}
1092	/The rest of bits are O, see 6.2.22 /
1093	return VINF_SUCCESS;
1094	}
1095
1096	DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1097	{
1098	int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1099	if (RT_FAILURE(rc))
1100	AssertRCReturn(rc, rc);
1101	switch(index)
1102	{
1103	case ICH6_HDA_REG_CORBLBASE:
1104	pState->u64CORBBase &= 0xFFFFFFFF00000000ULL;
1105	pState->u64CORBBase \|= pState->au32Regs[index];
1106	break;
1107	case ICH6_HDA_REG_CORBUBASE:
1108	pState->u64CORBBase &= 0x00000000FFFFFFFFULL;
1109	pState->u64CORBBase \|= ((uint64_t)pState->au32Regs[index] << 32);
1110	break;
1111	case ICH6_HDA_REG_RIRLBASE:
1112	pState->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
1113	pState->u64RIRBBase \|= pState->au32Regs[index];
1114	break;
1115	case ICH6_HDA_REG_RIRUBASE:
1116	pState->u64RIRBBase &= 0x00000000FFFFFFFFULL;
1117	pState->u64RIRBBase \|= ((uint64_t)pState->au32Regs[index] << 32);
1118	break;
1119	case ICH6_HDA_REG_DPLBASE:
1120	/* @todo: first bit has special meaning */
1121	pState->u64DPBase &= 0xFFFFFFFF00000000ULL;
1122	pState->u64DPBase \|= pState->au32Regs[index];
1123	break;
1124	case ICH6_HDA_REG_DPUBASE:
1125	pState->u64DPBase &= 0x00000000FFFFFFFFULL;
1126	pState->u64DPBase \|= ((uint64_t)pState->au32Regs[index] << 32);
1127	break;
1128	default:
1129	AssertMsgFailed(("Invalid index"));
1130	}
1131	Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
1132	return rc;
1133	}
1134
1135	DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1136	{
1137	uint8_t nv = u32Value;
1138	uint8_t v = RIRBSTS(pState);
1139	RIRBSTS(pState) = (v ^ nv) & v;
1140
1141	return hdaProcessInterrupt(pState);
1142	}
1143
1144	static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1145	{
1146	uint64_t addr;
1147	uint32_t len;
1148	uint32_t ioc;
1149	uint8_t bdle[16];
1150	uint32_t counter;
1151	uint32_t i;
1152	uint32_t sum = 0;
1153	Assert(pBdle && pBdle->u32BdleMaxCvi);
1154	for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1155	{
1156	PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), u64BaseDMA + i*16, bdle, 16);
1157	addr = (uint64_t )bdle;
1158	len = (uint32_t )&bdle[8];
1159	ioc = (uint32_t )&bdle[12];
1160	Log(("hda: %s bdle[%d] a:%x, len:%x, ios:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc));
1161	sum += len;
1162	}
1163	Log(("hda: sum: %d\n", sum));
1164	for (i = 0; i < 8; ++i)
1165	{
1166	PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64DPBase + i*8, &counter, 4);
1167	Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pState, 4) \|\| i == SDCTL_NUM(pState, 0)? "[C]": " ",
1168	i , counter));
1169	}
1170	}
1171	static void fetch_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1172	{
1173	uint8_t bdle[16];
1174	Assert((u64BaseDMA && pBdle && pBdle->u32BdleMaxCvi));
1175	PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1176	pBdle->u64BdleCviAddr = (uint64_t )bdle;
1177	pBdle->u32BdleCviLen = (uint32_t )&bdle[8];
1178	pBdle->fBdleCviIoc = ((uint32_t )&bdle[12]) & 0x1;
1179	dump_bd(pState, pBdle, u64BaseDMA);
1180	}
1181
1182	static uint32_t read_audio(INTELHDLinkState pState, int avail, bool fStop)
1183	{
1184	uint8_t tmpbuf[4096];
1185	uint32_t temp;
1186	uint32_t u32Rest = 0;
1187	uint32_t cbRead = 0;
1188	uint32_t to_copy = 0;
1189	/* todo: add input line detection */
1190	PHDABDLEDESC pBdle = &pState->stInBdle;
1191	SWVoiceIn *voice = pState->Codec.voice_pi;
1192	u32Rest = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1193	temp = audio_MIN(u32Rest, (uint32_t)avail);
1194	if (!temp)
1195	{
1196	*fStop = true;
1197	return cbRead;
1198	}
1199	while (temp)
1200	{
1201	int copied;
1202	to_copy = audio_MIN(temp, 4096U);
1203	copied = AUD_read (voice, tmpbuf, to_copy);
1204	Log (("hda: read_audio max=%x to_copy=%x copied=%x\n",
1205	avail, to_copy, copied));
1206	if (!copied)
1207	{
1208	*fStop = true;
1209	break;
1210	}
1211	PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, tmpbuf, copied);
1212	temp -= copied;
1213	cbRead += copied;
1214	pBdle->u32BdleCviPos += copied;
1215	}
1216	return cbRead;
1217	}
1218	static uint32_t write_audio(INTELHDLinkState pState, int avail, bool fStop)
1219	{
1220	uint8_t tmpbuf[4096];
1221	uint32_t temp;
1222	uint32_t u32Rest;
1223	uint32_t written = 0;
1224	int to_copy = 0;
1225	PHDABDLEDESC pBdle = &pState->stOutBdle;
1226	u32Rest = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1227	temp = audio_MIN(u32Rest, (uint32_t)avail);
1228	if (!temp)
1229	{
1230	*fStop = true;
1231	return written;
1232	}
1233	while (temp)
1234	{
1235	int copied;
1236	to_copy = audio_MIN(temp, 4096U);
1237	PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, tmpbuf, to_copy);
1238	copied = AUD_write (pState->Codec.voice_po, tmpbuf, to_copy);
1239	Log (("hda: write_audio max=%x to_copy=%x copied=%x\n",
1240	avail, to_copy, copied));
1241	Assert((copied));
1242	if (!copied)
1243	{
1244	*fStop = true;
1245	break;
1246	}
1247	temp -= copied;
1248	written += copied;
1249	pBdle->u32BdleCviPos += copied;
1250	}
1251	return written;
1252	}
1253
1254	DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
1255	{
1256	INTELHDLinkState pState = (INTELHDLinkState )pCodecState->pHDAState;
1257	return VINF_SUCCESS;
1258	}
1259
1260	DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
1261	{
1262	bool fStop = false;
1263	uint64_t u64BaseDMA = 0;
1264	PHDABDLEDESC pBdle = NULL;
1265	INTELHDLinkState pState = (INTELHDLinkState )pCodecState->pHDAState;
1266	uint32_t u32Counter;
1267	uint32_t nBytes;
1268	uint32_t u32Ctl;
1269	uint32_t *pu32Sts;
1270	uint8_t u8Strm;
1271	uint32_t *pu32Lpib;
1272	uint32_t u32Lcbl;
1273	switch (src)
1274	{
1275	case PO_INDEX:
1276	{
1277	u8Strm = 4;
1278	u32Ctl = SDCTL(pState, 4);
1279	u64BaseDMA = SDBDPL(pState, 4);
1280	u64BaseDMA \|= (((uint64_t)SDBDPU(pState, 4)) << 32);
1281	pu32Lpib = &SDLPIB(pState, 4);
1282	pu32Sts = &SDSTS(pState, 4);
1283	u32Lcbl = SDLCBL(pState, 4);
1284	pBdle = &pState->stOutBdle;
1285	pBdle->u32BdleMaxCvi = SDLVI(pState, 4);
1286	break;
1287	}
1288	case PI_INDEX:
1289	{
1290	u8Strm = 0;
1291	u32Ctl = SDCTL(pState, 0);
1292	pu32Lpib = &SDLPIB(pState, 0);
1293	pu32Sts = &SDSTS(pState, 0);
1294	u32Lcbl = SDLCBL(pState, 0);
1295	u64BaseDMA = SDBDPL(pState, 0);
1296	u64BaseDMA \|= (((uint64_t)SDBDPU(pState, 0)) << 32);
1297	pBdle = &pState->stInBdle;
1298	pBdle->u32BdleMaxCvi = SDLVI(pState, 0);
1299	break;
1300	}
1301	default:
1302	return;
1303	}
1304	if ( !(u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1305	\|\| !avail
1306	\|\| !u64BaseDMA)
1307	return;
1308	fetch_bd(pState, pBdle, u64BaseDMA);
1309	while( avail
1310	&& !fStop)
1311	{
1312	PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & ~0x1) + u8Strm*8, &u32Counter, 4);
1313	switch (src)
1314	{
1315	case PO_INDEX:
1316	nBytes = write_audio(pState, avail, &fStop);
1317	break;
1318	case PI_INDEX:
1319	nBytes = read_audio(pState, avail, &fStop);
1320	break;
1321	default:
1322	AssertMsgFailed(("Unsupported"));
1323	}
1324	if ( fStop
1325	&& pBdle->u32BdleCviLen != pBdle->u32BdleCviPos)
1326	break;
1327	*pu32Lpib += nBytes;
1328	avail -= nBytes;
1329	u32Counter += nBytes;
1330	PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & ~0x1) + u8Strm*8, &u32Counter, 4);
1331	if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
1332	\|\| *pu32Lpib == u32Lcbl)
1333	{
1334	if ( u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)
1335	&& ( ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
1336	&& pBdle->fBdleCviIoc )
1337	\|\| *pu32Lpib == u32Lcbl))
1338	{
1339	*pu32Sts \|= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1340	hdaProcessInterrupt(pState);
1341	if (*pu32Lpib == u32Lcbl)
1342	{
1343	*pu32Lpib = 0;
1344	u32Counter = 0;
1345	PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & ~0x1) + u8Strm*8, &u32Counter, 4);
1346	}
1347	}
1348	if (pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
1349	{
1350	pBdle->u32BdleCviPos = 0;
1351	pBdle->u32BdleCvi++;
1352	if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
1353	pBdle->u32BdleCvi = 0;
1354	}
1355	fStop = false;
1356	fetch_bd(pState, pBdle, u64BaseDMA);
1357	}
1358	}
1359	}
1360
1361	/**
1362	* Handle register read operation.
1363	*
1364	* Looks up and calls appropriate handler.
1365	*
1366	* @note: while implementation was detected so called "forgotten" or "hole" registers
1367	* which description is missed in RPM, datasheet or spec.
1368	*
1369	* @returns VBox status code.
1370	*
1371	* @param pState The device state structure.
1372	* @param uOffset Register offset in memory-mapped frame.
1373	* @param pv Where to fetch the value.
1374	* @param cb Number of bytes to write.
1375	* @thread EMT
1376	*/
1377	PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
1378	{
1379	int rc = VINF_SUCCESS;
1380	PCIINTELHDLinkState pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState );
1381	uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1382	int index = hdaLookup(&pThis->hda, u32Offset);
1383	if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1384	{
1385	Log(("hda: access to registers except GCTL is blocked while reset\n"));
1386	}
1387	Assert( index != -1
1388	&& cb <= 4);
1389	if (index != -1)
1390	{
1391	uint32_t mask = 0;
1392	uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1393	uint32_t v = 0;
1394	switch(cb)
1395	{
1396	case 1: mask = 0x000000ff; break;
1397	case 2: mask = 0x0000ffff; break;
1398	case 3: mask = 0x00ffffff; break;
1399	case 4: mask = 0xffffffff; break;
1400	}
1401	mask <<= shift;
1402	rc = s_ichIntelHDRegMap[index].pfnRead(&pThis->hda, u32Offset, index, &v);
1403	(uint32_t )pv = (v & mask) >> shift;
1404	Log(("hda: read %s[%x/%x]\n", s_ichIntelHDRegMap[index].abbrev, v, (uint32_t )pv));
1405	return rc;
1406	}
1407	(uint32_t )pv = 0xFF;
1408	Log(("hda: hole at %X is accessed for read\n", u32Offset));
1409	return rc;
1410	}
1411
1412	/**
1413	* Handle register write operation.
1414	*
1415	* Looks up and calls appropriate handler.
1416	*
1417	* @returns VBox status code.
1418	*
1419	* @param pState The device state structure.
1420	* @param uOffset Register offset in memory-mapped frame.
1421	* @param pv Where to fetch the value.
1422	* @param cb Number of bytes to write.
1423	* @thread EMT
1424	*/
1425	PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
1426	{
1427	int rc = VINF_SUCCESS;
1428	PCIINTELHDLinkState pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState );
1429	uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1430	int index = hdaLookup(&pThis->hda, u32Offset);
1431	if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1432	{
1433	Log(("hda: access to registers except GCTL is blocked while reset\n"));
1434	}
1435	Assert( index != -1
1436	&& cb <= 4);
1437	if (index != -1)
1438	{
1439	uint32_t v = pThis->hda.au32Regs[index];
1440	uint32_t mask = 0;
1441	uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1442	switch(cb)
1443	{
1444	case 1: mask = 0xffffff00; break;
1445	case 2: mask = 0xffff0000; break;
1446	case 3: mask = 0xff000000; break;
1447	case 4: mask = 0x00000000; break;
1448	}
1449	mask <<= shift;
1450	(uint32_t )pv = ((v & mask) \| ((uint32_t )pv & ~mask)) >> shift;
1451	rc = s_ichIntelHDRegMap[index].pfnWrite(&pThis->hda, u32Offset, index, (uint32_t )pv);
1452	Log(("hda: write %s:(%x) %x => %x\n", s_ichIntelHDRegMap[index].abbrev, (uint32_t )pv, v, pThis->hda.au32Regs[index]));
1453	return rc;
1454	}
1455	Log(("hda: hole at %X is accessed for write\n", u32Offset));
1456	return rc;
1457	}
1458
1459	/**
1460	* Callback function for mapping a PCI I/O region.
1461	*
1462	* @return VBox status code.
1463	* @param pPciDev Pointer to PCI device.
1464	* Use pPciDev->pDevIns to get the device instance.
1465	* @param iRegion The region number.
1466	* @param GCPhysAddress Physical address of the region.
1467	* If iType is PCI_ADDRESS_SPACE_IO, this is an
1468	* I/O port, else it's a physical address.
1469	* This address is NOT relative
1470	* to pci_mem_base like earlier!
1471	* @param enmType One of the PCI_ADDRESS_SPACE_* values.
1472	*/
1473	static DECLCALLBACK(int) hdaMap (PPCIDEVICE pPciDev, int iRegion,
1474	RTGCPHYS GCPhysAddress, uint32_t cb,
1475	PCIADDRESSSPACE enmType)
1476	{
1477	int rc;
1478	PPDMDEVINS pDevIns = pPciDev->pDevIns;
1479	RTIOPORT Port = (RTIOPORT)GCPhysAddress;
1480	PCIINTELHDLinkState *pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);
1481
1482	Assert(enmType == PCI_ADDRESS_SPACE_MEM);
1483	rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, 0,
1484	hdaMMIOWrite, hdaMMIORead, NULL, "ICH6_HDA");
1485
1486	if (RT_FAILURE(rc))
1487	return rc;
1488
1489	pThis->hda.addrMMReg = GCPhysAddress;
1490	return VINF_SUCCESS;
1491	}
1492
1493	/**
1494	* Saves a state of the HDA device.
1495	*
1496	* @returns VBox status code.
1497	* @param pDevIns The device instance.
1498	* @param pSSMHandle The handle to save the state to.
1499	*/
1500	static DECLCALLBACK(int) hdaSaveExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1501	{
1502	PCIINTELHDLinkState pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState );
1503	/* Save Codec nodes states */
1504	stac9220SaveState(&pThis->hda.Codec, pSSMHandle);
1505	/* Save MMIO registers */
1506	SSMR3PutMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
1507	/* Save HDA dma counters */
1508	SSMR3PutMem (pSSMHandle, &pThis->hda.stOutBdle, sizeof (HDABDLEDESC));
1509	SSMR3PutMem (pSSMHandle, &pThis->hda.stMicBdle, sizeof (HDABDLEDESC));
1510	SSMR3PutMem (pSSMHandle, &pThis->hda.stInBdle, sizeof (HDABDLEDESC));
1511	uint8_t voices = AUD_is_active_in(pThis->hda.Codec.voice_pi)? RT_BIT(0):0;
1512	voices \|= AUD_is_active_in(pThis->hda.Codec.voice_mc)? RT_BIT(1):0;
1513	voices \|= AUD_is_active_out(pThis->hda.Codec.voice_po)? RT_BIT(2):0;
1514	SSMR3PutU8(pSSMHandle, voices);
1515	return VINF_SUCCESS;
1516	}
1517
1518	/**
1519	* Loads a saved HDA device state.
1520	*
1521	* @returns VBox status code.
1522	* @param pDevIns The device instance.
1523	* @param pSSMHandle The handle to the saved state.
1524	* @param uVersion The data unit version number.
1525	* @param uPass The data pass.
1526	*/
1527	static DECLCALLBACK(int) hdaLoadExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1528	uint32_t uVersion, uint32_t uPass)
1529	{
1530	PCIINTELHDLinkState pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState );
1531	/* Load Codec nodes states */
1532	stac9220LoadState(&pThis->hda.Codec, pSSMHandle);
1533	/* Load MMIO registers */
1534	SSMR3GetMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
1535	/* Load HDA dma counters */
1536	SSMR3GetMem (pSSMHandle, &pThis->hda.stOutBdle, sizeof (HDABDLEDESC));
1537	SSMR3GetMem (pSSMHandle, &pThis->hda.stMicBdle, sizeof (HDABDLEDESC));
1538	SSMR3GetMem (pSSMHandle, &pThis->hda.stInBdle, sizeof (HDABDLEDESC));
1539	uint8_t voices;
1540	SSMR3GetU8(pSSMHandle, &voices);
1541	AUD_set_active_in(pThis->hda.Codec.voice_pi, voices & RT_BIT(0));
1542	AUD_set_active_in(pThis->hda.Codec.voice_mc, voices & RT_BIT(1));
1543	AUD_set_active_out(pThis->hda.Codec.voice_po, voices & RT_BIT(2));
1544	pThis->hda.u64CORBBase = CORBLBASE(&pThis->hda);
1545	pThis->hda.u64CORBBase \|= ((uint64_t)CORBUBASE(&pThis->hda)) << 32;
1546	pThis->hda.u64RIRBBase = RIRLBASE(&pThis->hda);
1547	pThis->hda.u64RIRBBase \|= ((uint64_t)RIRUBASE(&pThis->hda)) << 32;
1548	pThis->hda.u64DPBase = DPLBASE(&pThis->hda);
1549	pThis->hda.u64DPBase \|= ((uint64_t)DPUBASE(&pThis->hda)) << 32;
1550	return VINF_SUCCESS;
1551	}
1552
1553	/**
1554	* Reset notification.
1555	*
1556	* @returns VBox status.
1557	* @param pDevIns The device instance data.
1558	*
1559	* @remark The original sources didn't install a reset handler, but it seems to
1560	* make sense to me so we'll do it.
1561	*/
1562	static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns)
1563	{
1564	PCIINTELHDLinkState pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState );
1565	GCAP(&pThis->hda) = 0x4401; /* see 6.2.1 */
1566	VMIN(&pThis->hda) = 0x00; /* see 6.2.2 */
1567	VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
1568	VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
1569	OUTPAY(&pThis->hda) = 0x003C; /* see 6.2.4 */
1570	INPAY(&pThis->hda) = 0x001D; /* see 6.2.5 */
1571	pThis->hda.au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
1572	pThis->hda.au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
1573	CORBRP(&pThis->hda) = 0x0;
1574	RIRBWP(&pThis->hda) = 0x0;
1575
1576	LogRel(("hda: inter HDA reset.\n"));
1577	//** @todo r=michaln: There should be LogRel statements when the guest initializes
1578	// or resets the HDA chip, and possibly also when opening the PCM streams.
1579	pThis->hda.cbCorbBuf = 256 * sizeof(uint32_t);
1580
1581	if (pThis->hda.pu32CorbBuf)
1582	memset(pThis->hda.pu32CorbBuf, 0, pThis->hda.cbCorbBuf);
1583	else
1584	pThis->hda.pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->hda.cbCorbBuf);
1585
1586	pThis->hda.cbRirbBuf = 256 * sizeof(uint64_t);
1587	if (pThis->hda.pu64RirbBuf)
1588	memset(pThis->hda.pu64RirbBuf, 0, pThis->hda.cbRirbBuf);
1589	else
1590	pThis->hda.pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->hda.cbRirbBuf);
1591
1592	/* Accoding to ICH6 datasheet, 0x40000 is default value for stream descriptor register 23:20
1593	* bits are reserved for stream number 18.2.33 */
1594	SDCTL(&pThis->hda, 0) = 0x40000;
1595	SDCTL(&pThis->hda, 1) = 0x40000;
1596	SDCTL(&pThis->hda, 2) = 0x40000;
1597	SDCTL(&pThis->hda, 3) = 0x40000;
1598	SDCTL(&pThis->hda, 4) = 0x40000;
1599	SDCTL(&pThis->hda, 5) = 0x40000;
1600	SDCTL(&pThis->hda, 6) = 0x40000;
1601	SDCTL(&pThis->hda, 7) = 0x40000;
1602
1603	/* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
1604	SDFIFOS(&pThis->hda, 0) = 0x77;
1605	SDFIFOS(&pThis->hda, 1) = 0x77;
1606	SDFIFOS(&pThis->hda, 2) = 0x77;
1607	SDFIFOS(&pThis->hda, 3) = 0x77;
1608	SDFIFOS(&pThis->hda, 4) = 0xBF;
1609	SDFIFOS(&pThis->hda, 5) = 0xBF;
1610	SDFIFOS(&pThis->hda, 6) = 0xBF;
1611	SDFIFOS(&pThis->hda, 7) = 0xBF;
1612
1613	/* emulateion of codec "wake up" HDA spec (5.5.1 and 6.5)*/
1614	STATESTS(&pThis->hda) = 0x1;
1615
1616	Log(("hda: reset finished\n"));
1617	}
1618
1619	/**
1620	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
1621	*/
1622	static DECLCALLBACK(void ) hdaQueryInterface (struct PDMIBASE pInterface,
1623	const char *pszIID)
1624	{
1625	PCIINTELHDLinkState *pThis = RT_FROM_MEMBER(pInterface, PCIINTELHDLinkState, hda.IBase);
1626	Assert(&pThis->hda.IBase == pInterface);
1627
1628	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->hda.IBase);
1629	return NULL;
1630	}
1631
1632	/**
1633	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1634	*/
1635	static DECLCALLBACK(int) hdaConstruct (PPDMDEVINS pDevIns, int iInstance,
1636	PCFGMNODE pCfgHandle)
1637	{
1638	PCIINTELHDLinkState pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState );
1639	INTELHDLinkState *s = &pThis->hda;
1640	int rc;
1641
1642	Assert(iInstance == 0);
1643	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1644
1645	/*
1646	* Validations.
1647	*/
1648	if (!CFGMR3AreValuesValid (pCfgHandle, "\0"))
1649	return PDMDEV_SET_ERROR (pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1650	N_ ("Invalid configuration for the INTELHD device"));
1651
1652	// ** @todo r=michaln: This device may need R0/RC enabling, especially if guests
1653	// poll some register(s).
1654
1655	/*
1656	* Initialize data (most of it anyway).
1657	*/
1658	s->pDevIns = pDevIns;
1659	/* IBase */
1660	s->IBase.pfnQueryInterface = hdaQueryInterface;
1661
1662	/* PCI Device (the assertions will be removed later) */
1663	PCIDevSetVendorId (&pThis->dev, 0x8086); /* 00 ro - intel. */
1664	PCIDevSetDeviceId (&pThis->dev, 0x2668); /* 02 ro - 82801 / 82801aa(?). */
1665	PCIDevSetCommand (&pThis->dev, 0x0000); /* 04 rw,ro - pcicmd. */
1666	PCIDevSetStatus (&pThis->dev, 0x0010); /* 06 rwc?,ro? - pcists. */
1667	PCIDevSetRevisionId (&pThis->dev, 0x01); /* 08 ro - rid. */
1668	PCIDevSetClassProg (&pThis->dev, 0x00); /* 09 ro - pi. */
1669	PCIDevSetClassSub (&pThis->dev, 0x03); /* 0a ro - scc; 03 == HDA. */
1670	PCIDevSetClassBase (&pThis->dev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
1671	PCIDevSetHeaderType (&pThis->dev, 0x00); /* 0e ro - headtyp. */
1672	PCIDevSetBaseAddress (&pThis->dev, 0, /* 10 rw - MMIO */
1673	false /* fIoSpace /, false / fPrefetchable /, true / f64Bit */, 0x00000000);
1674	/* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
1675	verb F20 should provide device/codec recognition. */
1676	PCIDevSetSubSystemVendorId (&pThis->dev, 0x0000); /* 2c ro - intel.) */
1677	PCIDevSetSubSystemId (&pThis->dev, 0x0000); /* 2e ro. */
1678	PCIDevSetInterruptLine (&pThis->dev, 0x00); /* 3c rw. */
1679	PCIDevSetInterruptPin (&pThis->dev, 0x01); /* 3d ro - INTA#. */ Assert (pThis->dev.config[0x3d] == 0x01);
1680	PCIDevSetCapabilityList(&pThis->dev, 0x50); /* ICH6 datasheet 18.1.16 */
1681
1682	//** @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
1683	// of these values needs to be properly documented!
1684	/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1685	pThis->dev.config[0x40] = 0x01;
1686
1687	pThis->dev.config[0x50] = 0x01;
1688	pThis->dev.config[0x51] = 0x60; /* next */
1689	pThis->dev.config[0x52] = 0x22;
1690	pThis->dev.config[0x53] = 0x00; /* PM - disabled, */
1691
1692	#if 0
1693	pThis->dev.config[0x60] = 0x05;
1694	pThis->dev.config[0x61] = 0x70; /* next */
1695	pThis->dev.config[0x62] = 0x00;
1696	pThis->dev.config[0x63] = 0x80;
1697	#endif
1698
1699	/*
1700	* Register the PCI device.
1701	*/
1702	rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
1703	if (RT_FAILURE (rc))
1704	return rc;
1705
1706	rc = PDMDevHlpPCIIORegionRegister (pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM,
1707	hdaMap);
1708	if (RT_FAILURE (rc))
1709	return rc;
1710
1711	rc = PDMDevHlpSSMRegister (pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
1712	if (RT_FAILURE (rc))
1713	return rc;
1714
1715	/*
1716	* Attach driver.
1717	*/
1718	rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase,
1719	&s->pDrvBase, "Audio Driver Port");
1720	if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1721	Log (("hda: No attached driver!\n"));
1722	else if (RT_FAILURE (rc))
1723	{
1724	AssertMsgFailed (("Failed to attach INTELHD LUN #0! rc=%Rrc\n", rc));
1725	return rc;
1726	}
1727
1728
1729
1730	pThis->hda.Codec.pHDAState = (void *)&pThis->hda;
1731	rc = stac9220Construct(&pThis->hda.Codec);
1732	if (RT_FAILURE(rc))
1733	AssertRCReturn(rc, rc);
1734	hdaReset (pDevIns);
1735	pThis->hda.Codec.id = 0;
1736	pThis->hda.Codec.pfnTransfer = hdaTransfer;
1737	pThis->hda.Codec.pfnReset = hdaCodecReset;
1738	/*
1739	* 18.2.6,7 defines that values of this registers might be cleared on power on/reset
1740	* hdaReset shouldn't affects these registers.
1741	*/
1742	WAKEEN(&pThis->hda) = 0x0;
1743	STATESTS(&pThis->hda) = 0x0;
1744
1745	return VINF_SUCCESS;
1746	}
1747
1748	/**
1749	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1750	*/
1751	static DECLCALLBACK(int) hdaDestruct (PPDMDEVINS pDevIns)
1752	{
1753	PCIINTELHDLinkState pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState );
1754
1755	int rc = stac9220Destruct(&pThis->hda.Codec);
1756	AssertRC(rc);
1757	if (pThis->hda.pu32CorbBuf)
1758	RTMemFree(pThis->hda.pu32CorbBuf);
1759	if (pThis->hda.pu64RirbBuf)
1760	RTMemFree(pThis->hda.pu64RirbBuf);
1761	return VINF_SUCCESS;
1762	}
1763
1764	/**
1765	* The device registration structure.
1766	*/
1767	const PDMDEVREG g_DeviceICH6_HDA =
1768	{
1769	/* u32Version */
1770	PDM_DEVREG_VERSION,
1771	/* szName */
1772	"hda",
1773	/* szRCMod */
1774	"",
1775	/* szR0Mod */
1776	"",
1777	/* pszDescription */
1778	"ICH IntelHD Audio Controller",
1779	/* fFlags */
1780	PDM_DEVREG_FLAGS_DEFAULT_BITS,
1781	/* fClass */
1782	PDM_DEVREG_CLASS_AUDIO,
1783	/* cMaxInstances */
1784	1,
1785	/* cbInstance */
1786	sizeof(PCIINTELHDLinkState),
1787	/* pfnConstruct */
1788	hdaConstruct,
1789	/* pfnDestruct */
1790	hdaDestruct,
1791	/* pfnRelocate */
1792	NULL,
1793	/* pfnIOCtl */
1794	NULL,
1795	/* pfnPowerOn */
1796	NULL,
1797	/* pfnReset */
1798	hdaReset,
1799	/* pfnSuspend */
1800	NULL,
1801	/* pfnResume */
1802	NULL,
1803	/* pfnAttach */
1804	NULL,
1805	/* pfnDetach */
1806	NULL,
1807	/* pfnQueryInterface. */
1808	NULL,
1809	/* pfnInitComplete */
1810	NULL,
1811	/* pfnPowerOff */
1812	NULL,
1813	/* pfnSoftReset */
1814	NULL,
1815	/* u32VersionEnd */
1816	PDM_DEVREG_VERSION
1817	};

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source: vbox/trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp@ 31808

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