VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchIntelHDA.cpp@ 37636

Last change on this file since 37636 was 37636, checked in by vboxsync, 13 years ago

Changed FNIOMMMIOWRITE to take a const buffer pointer.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 112.1 KB
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1/* $Id: DevIchIntelHDA.cpp 37636 2011-06-24 14:59:59Z vboxsync $ */
2/** @file
3 * DevIchIntelHD - VBox ICH Intel HD Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_AUDIO
22#include <VBox/vmm/pdmdev.h>
23#include <iprt/assert.h>
24#include <iprt/uuid.h>
25#include <iprt/string.h>
26#include <iprt/mem.h>
27#include <iprt/asm.h>
28#include <iprt/asm-math.h>
29
30#include "VBoxDD.h"
31
32extern "C" {
33#include "audio.h"
34}
35#include "DevCodec.h"
36
37#define VBOX_WITH_INTEL_HDA
38
39#if defined(VBOX_WITH_HP_HDA)
40/* HP Pavilion dv4t-1300 */
41# define HDA_PCI_VENDOR_ID 0x103c
42# define HDA_PCI_DEICE_ID 0x30f7
43#elif defined(VBOX_WITH_INTEL_HDA)
44/* Intel HDA controller */
45# define HDA_PCI_VENDOR_ID 0x8086
46# define HDA_PCI_DEICE_ID 0x2668
47#elif defined(VBOX_WITH_NVIDIA_HDA)
48/* nVidia HDA controller */
49# define HDA_PCI_VENDOR_ID 0x10de
50# define HDA_PCI_DEICE_ID 0x0ac0
51#else
52# error "Please specify your HDA device vendor/device IDs"
53#endif
54
55PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
56PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
57static DECLCALLBACK(void) hdaReset (PPDMDEVINS pDevIns);
58
59#define HDA_NREGS 112
60/* Registers */
61#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
62#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
63#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
64#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
65#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
66#define HDA_REG_IND(pState, x) ((pState)->au32Regs[(x)])
67#define HDA_REG(pState, x) (HDA_REG_IND((pState), HDA_REG_IND_NAME(x)))
68#define HDA_REG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
69#define HDA_REG_FLAG_VALUE(pState, reg, val) (HDA_REG((pState),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
70#define HDA_REG_SVALUE(pState, reg, val) (HDA_REG_VALUE(pState, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
71
72#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
73#define GCAP(pState) (HDA_REG((pState), GCAP))
74/* GCAP HDASpec 3.3.2 This macro compact following information about HDA
75 * oss (15:12) - number of output streams supported
76 * iss (11:8) - number of input streams supported
77 * bss (7:3) - number of bidirection streams suppoted
78 * bds (2:1) - number of serial data out signals supported
79 * b64sup (0) - 64 bit addressing supported.
80 */
81#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
82 ( (((oss) & 0xF) << 12) \
83 | (((iss) & 0xF) << 8) \
84 | (((bss) & 0x1F) << 3) \
85 | (((bds) & 0x3) << 2) \
86 | ((b64sup) & 1))
87#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
88#define VMIN(pState) (HDA_REG((pState), VMIN))
89
90#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
91#define VMAJ(pState) (HDA_REG((pState), VMAJ))
92
93#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
94#define OUTPAY(pState) (HDA_REG((pState), OUTPAY))
95
96#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
97#define INPAY(pState) (HDA_REG((pState), INPAY))
98
99#define ICH6_HDA_REG_GCTL (5)
100#define ICH6_HDA_GCTL_RST_SHIFT (0)
101#define ICH6_HDA_GCTL_FSH_SHIFT (1)
102#define ICH6_HDA_GCTL_UR_SHIFT (8)
103#define GCTL(pState) (HDA_REG((pState), GCTL))
104
105#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
106#define WAKEEN(pState) (HDA_REG((pState), WAKEEN))
107
108#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
109#define STATESTS(pState) (HDA_REG((pState), STATESTS))
110#define ICH6_HDA_STATES_SCSF 0x7
111
112#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
113#define ICH6_HDA_GSTS_FSH_SHIFT (1)
114#define GSTS(pState) (HDA_REG(pState, GSTS))
115
116#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
117#define ICH6_HDA_INTCTL_GIE_SHIFT 31
118#define ICH6_HDA_INTCTL_CIE_SHIFT 30
119#define ICH6_HDA_INTCTL_S0_SHIFT (0)
120#define ICH6_HDA_INTCTL_S1_SHIFT (1)
121#define ICH6_HDA_INTCTL_S2_SHIFT (2)
122#define ICH6_HDA_INTCTL_S3_SHIFT (3)
123#define ICH6_HDA_INTCTL_S4_SHIFT (4)
124#define ICH6_HDA_INTCTL_S5_SHIFT (5)
125#define ICH6_HDA_INTCTL_S6_SHIFT (6)
126#define ICH6_HDA_INTCTL_S7_SHIFT (7)
127#define INTCTL(pState) (HDA_REG((pState), INTCTL))
128#define INTCTL_GIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, GIE))
129#define INTCTL_CIE(pState) (HDA_REG_FLAG_VALUE(pState, INTCTL, CIE))
130#define INTCTL_SX(pState, X) (HDA_REG_FLAG_VALUE((pState), INTCTL, S##X))
131#define INTCTL_SALL(pState) (INTCTL((pState)) & 0xFF)
132
133/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
134 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
135 * the datasheet.
136 */
137#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
138#define SSYNC(pState) (HDA_REG((pState), SSYNC))
139
140#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
141#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
142#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
143#define ICH6_HDA_INTSTS_S0_SHIFT (0)
144#define ICH6_HDA_INTSTS_S1_SHIFT (1)
145#define ICH6_HDA_INTSTS_S2_SHIFT (2)
146#define ICH6_HDA_INTSTS_S3_SHIFT (3)
147#define ICH6_HDA_INTSTS_S4_SHIFT (4)
148#define ICH6_HDA_INTSTS_S5_SHIFT (5)
149#define ICH6_HDA_INTSTS_S6_SHIFT (6)
150#define ICH6_HDA_INTSTS_S7_SHIFT (7)
151#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
152#define INTSTS(pState) (HDA_REG((pState), INTSTS))
153#define INTSTS_GIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, GIS)
154#define INTSTS_CIS(pState) (HDA_REG_FLAG_VALUE((pState), INTSTS, CIS)
155#define INTSTS_SX(pState, X) (HDA_REG_FLAG_VALUE(pState), INTSTS, S##X)
156#define INTSTS_SANY(pState) (INTSTS((pState)) & 0xFF)
157
158#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
159#define CORBLBASE(pState) (HDA_REG((pState), CORBLBASE))
160#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
161#define CORBUBASE(pState) (HDA_REG((pState), CORBUBASE))
162#define ICH6_HDA_REG_CORBWP 15 /* 48 */
163#define ICH6_HDA_REG_CORBRP 16 /* 4A */
164#define ICH6_HDA_CORBRP_RST_SHIFT 15
165#define ICH6_HDA_CORBRP_WP_SHIFT 0
166#define ICH6_HDA_CORBRP_WP_MASK 0xFF
167
168#define CORBRP(pState) (HDA_REG(pState, CORBRP))
169#define CORBWP(pState) (HDA_REG(pState, CORBWP))
170
171#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
172#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
173#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
174
175#define CORBCTL(pState) (HDA_REG(pState, CORBCTL))
176
177
178#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
179#define CORBSTS(pState) (HDA_REG(pState, CORBSTS))
180#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
181
182#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
183#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
184#define ICH6_HDA_CORBSIZE_SZ 0x3
185#define CORBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
186#define CORBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
187/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
188
189#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
190#define RIRLBASE(pState) (HDA_REG((pState), RIRLBASE))
191
192#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
193#define RIRUBASE(pState) (HDA_REG((pState), RIRUBASE))
194
195#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
196#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
197#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
198#define RIRBWP(pState) (HDA_REG(pState, RIRBWP))
199
200#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
201#define RINTCNT(pState) (HDA_REG((pState), RINTCNT))
202#define RINTCNT_N(pState) (RINTCNT((pState)) & 0xff)
203
204#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
205#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
206#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
207#define ICH6_HDA_ROI_DMA_SHIFT (2)
208#define RIRBCTL(pState) (HDA_REG((pState), RIRBCTL))
209#define RIRBCTL_RIRB_RIC(pState) (HDA_REG_FLAG_VALUE(pState, RIRBCTL, RIC))
210#define RIRBCTL_RIRB_DMA(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, DMA)
211#define RIRBCTL_ROI(pState) (HDA_REG_FLAG_VALUE((pState), RIRBCTL, ROI))
212
213#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
214#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
215#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
216#define RIRBSTS(pState) (HDA_REG(pState, RIRBSTS))
217#define RIRBSTS_RINTFL(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RINTFL))
218#define RIRBSTS_RIRBOIS(pState) (HDA_REG_FLAG_VALUE(pState, RIRBSTS, RIRBOIS))
219
220#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
221#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
222#define ICH6_HDA_RIRBSIZE_SZ 0x3
223
224#define RIRBSIZE_SZ(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
225#define RIRBSIZE_SZ_CAP(pState) (HDA_REG(pState, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
226
227
228#define ICH6_HDA_REG_IC 27 /* 0x60 */
229#define IC(pState) (HDA_REG(pState, IC))
230#define ICH6_HDA_REG_IR 28 /* 0x64 */
231#define IR(pState) (HDA_REG(pState, IR))
232#define ICH6_HDA_REG_IRS 29 /* 0x68 */
233#define ICH6_HDA_IRS_ICB_SHIFT (0)
234#define ICH6_HDA_IRS_IRV_SHIFT (1)
235#define IRS(pState) (HDA_REG(pState, IRS))
236#define IRS_ICB(pState) (HDA_REG_FLAG_VALUE(pState, IRS, ICB))
237#define IRS_IRV(pState) (HDA_REG_FLAG_VALUE(pState, IRS, IRV))
238
239#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
240#define DPLBASE(pState) (HDA_REG((pState), DPLBASE))
241#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
242#define DPUBASE(pState) (HDA_REG((pState), DPUBASE))
243#define DPBASE_ENABLED 1
244#define DPBASE_ADDR_MASK (~0x7f)
245
246#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
247#define HDA_STREAM_REG(pState, name, num) (HDA_REG((pState), N_(HDA_STREAM_REG_DEF(name, num))))
248/* Note: sdnum here _MUST_ be stream reg number [0,7] */
249#define HDA_STREAM_REG2(pState, name, sdnum) (HDA_REG_IND((pState), ICH6_HDA_REG_SD0##name + (sdnum) * 10))
250
251#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
252#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
253#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
254#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
255#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
256#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
257#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
258#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
259
260#define SD(func, num) SD##num##func
261#define SDCTL(pState, num) HDA_REG((pState), SD(CTL, num))
262#define SDCTL_NUM(pState, num) ((SDCTL((pState), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
263#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
264#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
265#define ICH6_HDA_SDCTL_DIR_SHIFT (19)
266#define ICH6_HDA_SDCTL_TP_SHIFT (18)
267#define ICH6_HDA_SDCTL_STRIPE_MASK (0x3)
268#define ICH6_HDA_SDCTL_STRIPE_SHIFT (16)
269#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
270#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
271#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
272#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
273#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
274
275#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
276#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
277#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
278#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
279#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
280#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
281#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
282#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
283
284#define SDSTS(pState, num) HDA_REG((pState), SD(STS, num))
285#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
286#define ICH6_HDA_SDSTS_DE_SHIFT (4)
287#define ICH6_HDA_SDSTS_FE_SHIFT (3)
288#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
289
290#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
291#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
292#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
293#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
294#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
295#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
296#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
297#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
298
299#define SDLPIB(pState, num) HDA_REG((pState), SD(LPIB, num))
300
301#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
302#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
303#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
304#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
305#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
306#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
307#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
308#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
309
310#define SDLCBL(pState, num) HDA_REG((pState), SD(CBL, num))
311
312#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
313#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
314#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
315#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
316#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
317#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
318#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
319#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
320
321#define SDLVI(pState, num) HDA_REG((pState), SD(LVI, num))
322
323#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
324#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
325#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
326#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
327#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
328#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
329#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
330#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
331
332/*
333 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
334 */
335#define HDA_SDFIFOW_8B (0x2)
336#define HDA_SDFIFOW_16B (0x3)
337#define HDA_SDFIFOW_32B (0x4)
338#define SDFIFOW(pState, num) HDA_REG((pState), SD(FIFOW, num))
339
340#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
341#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
342#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
343#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
344#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
345#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
346#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
347#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
348
349/*
350 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
351 * formula: size - 1
352 * Other values not listed are not supported.
353 */
354#define HDA_SDONFIFO_16B (0xF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
355#define HDA_SDONFIFO_32B (0x1F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
356#define HDA_SDONFIFO_64B (0x3F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
357#define HDA_SDONFIFO_128B (0x7F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
358#define HDA_SDONFIFO_192B (0xBF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
359#define HDA_SDONFIFO_256B (0xFF) /* 20-, 24-bit Output Streams */
360#define HDA_SDINFIFO_120B (0x77) /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
361#define HDA_SDINFIFO_160B (0x9F) /* 20-, 24-bit Input Streams Streams */
362#define SDFIFOS(pState, num) HDA_REG((pState), SD(FIFOS, num))
363
364#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
365#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
366#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
367#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
368#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
369#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
370#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
371#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
372
373#define SDFMT(pState, num) (HDA_REG((pState), SD(FMT, num)))
374#define ICH6_HDA_SDFMT_BASE_RATE_SHIFT (14)
375#define ICH6_HDA_SDFMT_MULT_SHIFT (11)
376#define ICH6_HDA_SDFMT_MULT_MASK (0x7)
377#define ICH6_HDA_SDFMT_DIV_SHIFT (8)
378#define ICH6_HDA_SDFMT_DIV_MASK (0x7)
379#define ICH6_HDA_SDFMT_BITS_SHIFT (4)
380#define ICH6_HDA_SDFMT_BITS_MASK (0x7)
381#define SDFMT_BASE_RATE(pState, num) ((SDFMT(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
382#define SDFMT_MULT(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
383#define SDFMT_DIV(pState, num) ((SDFMT((pState), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
384
385#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
386#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
387#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
388#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
389#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
390#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
391#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
392#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
393
394#define SDBDPL(pState, num) HDA_REG((pState), SD(BDPL, num))
395
396#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
397#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
398#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
399#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
400#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
401#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
402#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
403#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
404
405#define SDBDPU(pState, num) HDA_REG((pState), SD(BDPU, num))
406
407/* Predicates */
408
409typedef struct HDABDLEDESC
410{
411 uint64_t u64BdleCviAddr;
412 uint32_t u32BdleMaxCvi;
413 uint32_t u32BdleCvi;
414 uint32_t u32BdleCviLen;
415 uint32_t u32BdleCviPos;
416 bool fBdleCviIoc;
417 uint32_t cbUnderFifoW;
418 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
419} HDABDLEDESC, *PHDABDLEDESC;
420
421static SSMFIELD const g_aHdaBDLEDescFields[] =
422{
423 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
424 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
425 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
426 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
427 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
428 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
429 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
430 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
431 SSMFIELD_ENTRY_TERM()
432};
433
434typedef struct HDASTREAMTRANSFERDESC
435{
436 uint64_t u64BaseDMA;
437 uint32_t u32Ctl;
438 uint32_t *pu32Sts;
439 uint8_t u8Strm;
440 uint32_t *pu32Lpib;
441 uint32_t u32Cbl;
442 uint32_t u32Fifos;
443} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
444
445typedef struct INTELHDLinkState
446{
447 /** Pointer to the device instance. */
448 PPDMDEVINSR3 pDevIns;
449 /** Pointer to the connector of the attached audio driver. */
450 PPDMIAUDIOCONNECTOR pDrv;
451 /** Pointer to the attached audio driver. */
452 PPDMIBASE pDrvBase;
453 /** The base interface for LUN\#0. */
454 PDMIBASE IBase;
455 RTGCPHYS addrMMReg;
456 uint32_t au32Regs[HDA_NREGS];
457 HDABDLEDESC stInBdle;
458 HDABDLEDESC stOutBdle;
459 HDABDLEDESC stMicBdle;
460 /* Interrupt on completion */
461 bool fCviIoc;
462 uint64_t u64CORBBase;
463 uint64_t u64RIRBBase;
464 uint64_t u64DPBase;
465 /* pointer on CORB buf */
466 uint32_t *pu32CorbBuf;
467 /* size in bytes of CORB buf */
468 uint32_t cbCorbBuf;
469 /* pointer on RIRB buf */
470 uint64_t *pu64RirbBuf;
471 /* size in bytes of RIRB buf */
472 uint32_t cbRirbBuf;
473 /* indicates if HDA in reset. */
474 bool fInReset;
475 CODECState Codec;
476 uint8_t u8Counter;
477 uint64_t u64BaseTS;
478} INTELHDLinkState, *PINTELHDLinkState;
479
480#define ICH6_HDASTATE_2_DEVINS(pINTELHD) ((pINTELHD)->pDevIns)
481#define PCIDEV_2_ICH6_HDASTATE(pPciDev) ((PCIINTELHDLinkState *)(pPciDev))
482
483#define ISD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, In, \
484 SDFMT_BASE_RATE(pState, 0), SDFMT_MULT(pState, 0), SDFMT_DIV(pState, 0)))
485#define OSD0FMT_TO_AUDIO_SELECTOR(pState) (AUDIO_FORMAT_SELECTOR(&(pState)->Codec, Out, \
486 SDFMT_BASE_RATE(pState, 4), SDFMT_MULT(pState, 4), SDFMT_DIV(pState, 4)))
487
488
489
490
491typedef struct PCIINTELHDLinkState
492{
493 PCIDevice dev;
494 INTELHDLinkState hda;
495} PCIINTELHDLinkState;
496
497
498DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
499DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
500DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
501DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
502DECLCALLBACK(int)hdaRegReadSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
503DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
504DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
505DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
506DECLCALLBACK(int)hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
507DECLCALLBACK(int)hdaRegWriteINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
508DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
509DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
510DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
511DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
512DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
513DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
514DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
515DECLCALLBACK(int)hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
516DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
517DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
518
519DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
520DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
521DECLCALLBACK(int)hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
522DECLCALLBACK(int)hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
523DECLCALLBACK(int)hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
524DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
525DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
526DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
527DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
528DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
529DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
530DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
531DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
532DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
533DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
534DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t pu32Value);
535
536static inline void hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc);
537static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset);
538static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
539#ifdef LOG_ENABLED
540static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
541#endif
542
543
544/* see 302349 p 6.2*/
545const static struct stIchIntelHDRegMap
546{
547 /** Register offset in the register space. */
548 uint32_t offset;
549 /** Size in bytes. Registers of size > 4 are in fact tables. */
550 uint32_t size;
551 /** Readable bits. */
552 uint32_t readable;
553 /** Writable bits. */
554 uint32_t writable;
555 /** Read callback. */
556 int (*pfnRead)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
557 /** Write callback. */
558 int (*pfnWrite)(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
559 /** Abbreviated name. */
560 const char *abbrev;
561 /** Full name. */
562 const char *name;
563} s_ichIntelHDRegMap[HDA_NREGS] =
564{
565 /* offset size read mask write mask read callback write callback abbrev full name */
566 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
567 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
568 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
569 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
570 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
571 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
572 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
573 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
574 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
575 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
576 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
577 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
578 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
579 //** @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
580 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
581 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
582 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
583 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
584 { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
585 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
586 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
587 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
588 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
589 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
590 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8, hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
591 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
592 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
593 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
594 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
595 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
596 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
597 { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
598 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
599 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
600
601 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
602 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
603 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
604 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
605 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
606 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD0FIFOW", "ISD0 FIFO Watermark" },
607 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
608 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD0FMT" , "ISD0 Format" },
609 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
610 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
611
612 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
613 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
614 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
615 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
616 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
617 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD1FIFOW", "ISD1 FIFO Watermark" },
618 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
619 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD1FMT" , "ISD1 Format" },
620 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
621 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
622
623 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
624 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
625 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
626 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
627 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
628 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD2FIFOW", "ISD2 FIFO Watermark" },
629 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
630 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD2FMT" , "ISD2 Format" },
631 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
632 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
633
634 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
635 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
636 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
637 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
638 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
639 { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
640 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
641 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD3FMT" , "ISD3 Format" },
642 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
643 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
644
645 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
646 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
647 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
648 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
649 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
650 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD0FIFOW", "OSD0 FIFO Watermark" },
651 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD0FIFOS", "OSD0 FIFO Size" },
652 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD0FMT" , "OSD0 Format" },
653 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
654 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
655
656 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
657 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
658 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
659 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
660 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
661 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD1FIFOW", "OSD1 FIFO Watermark" },
662 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD1FIFOS", "OSD1 FIFO Size" },
663 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD1FMT" , "OSD1 Format" },
664 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
665 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
666
667 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
668 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
669 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
670 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
671 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
672 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD2FIFOW", "OSD2 FIFO Watermark" },
673 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD2FIFOS", "OSD2 FIFO Size" },
674 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD2FMT" , "OSD2 Format" },
675 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
676 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
677
678 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
679 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
680 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
681 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
682 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
683 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD3FIFOW", "OSD3 FIFO Watermark" },
684 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD3FIFOS", "OSD3 FIFO Size" },
685 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD3FMT" , "OSD3 Format" },
686 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
687 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
688};
689
690static void inline hdaUpdatePosBuf(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
691{
692 if (pState->u64DPBase & DPBASE_ENABLED)
693 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState),
694 (pState->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm*8, pStreamDesc->pu32Lpib, sizeof(uint32_t));
695}
696static uint32_t inline hdaFifoWToSz(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc)
697{
698#if 0
699 switch(HDA_STREAM_REG2(pState, FIFOW, pStreamDesc->u8Strm))
700 {
701 case HDA_SDFIFOW_8B: return 8;
702 case HDA_SDFIFOW_16B: return 16;
703 case HDA_SDFIFOW_32B: return 32;
704 default:
705 AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pState, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
706 }
707#endif
708 return 0;
709}
710
711static int hdaProcessInterrupt(INTELHDLinkState* pState)
712{
713#define IS_INTERRUPT_OCCURED_AND_ENABLED(pState, num) \
714 ( INTCTL_SX((pState), num) \
715 && (SDSTS(pState, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
716 bool fIrq = false;
717 if ( INTCTL_CIE(pState)
718 && ( RIRBSTS_RINTFL(pState)
719 || RIRBSTS_RIRBOIS(pState)
720 || (STATESTS(pState) & WAKEEN(pState))))
721 fIrq = true;
722
723 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 0)
724 || IS_INTERRUPT_OCCURED_AND_ENABLED(pState, 4))
725 fIrq = true;
726
727 if (INTCTL_GIE(pState))
728 {
729 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
730 PDMDevHlpPCISetIrq(ICH6_HDASTATE_2_DEVINS(pState), 0 , fIrq);
731 }
732 return VINF_SUCCESS;
733}
734
735static int hdaLookup(INTELHDLinkState* pState, uint32_t u32Offset)
736{
737 int index = 0;
738 //** @todo r=michaln: A linear search of an array with over 100 elements is very inefficient.
739 for (;index < (int)(sizeof(s_ichIntelHDRegMap)/sizeof(s_ichIntelHDRegMap[0])); ++index)
740 {
741 if ( u32Offset >= s_ichIntelHDRegMap[index].offset
742 && u32Offset < s_ichIntelHDRegMap[index].offset + s_ichIntelHDRegMap[index].size)
743 {
744 return index;
745 }
746 }
747 /* Aliases HDA spec 3.3.45 */
748 switch(u32Offset)
749 {
750 case 0x2084:
751 return HDA_REG_IND_NAME(SD0LPIB);
752 case 0x20A4:
753 return HDA_REG_IND_NAME(SD1LPIB);
754 case 0x20C4:
755 return HDA_REG_IND_NAME(SD2LPIB);
756 case 0x20E4:
757 return HDA_REG_IND_NAME(SD3LPIB);
758 case 0x2104:
759 return HDA_REG_IND_NAME(SD4LPIB);
760 case 0x2124:
761 return HDA_REG_IND_NAME(SD5LPIB);
762 case 0x2144:
763 return HDA_REG_IND_NAME(SD6LPIB);
764 case 0x2164:
765 return HDA_REG_IND_NAME(SD7LPIB);
766 }
767 return -1;
768}
769
770static int hdaCmdSync(INTELHDLinkState *pState, bool fLocal)
771{
772 int rc = VINF_SUCCESS;
773 if (fLocal)
774 {
775 Assert((HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)));
776 rc = PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pState->u64CORBBase, pState->pu32CorbBuf, pState->cbCorbBuf);
777 if (RT_FAILURE(rc))
778 AssertRCReturn(rc, rc);
779#ifdef DEBUG_CMD_BUFFER
780 uint8_t i = 0;
781 do
782 {
783 Log(("hda: corb%02x: ", i));
784 uint8_t j = 0;
785 do
786 {
787 const char *prefix;
788 if ((i + j) == CORBRP(pState))
789 prefix = "[R]";
790 else if ((i + j) == CORBWP(pState))
791 prefix = "[W]";
792 else
793 prefix = " "; /* three spaces */
794 Log(("%s%08x", prefix, pState->pu32CorbBuf[i + j]));
795 j++;
796 } while (j < 8);
797 Log(("\n"));
798 i += 8;
799 } while(i != 0);
800#endif
801 }
802 else
803 {
804 Assert((HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA)));
805 rc = PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pState->u64RIRBBase, pState->pu64RirbBuf, pState->cbRirbBuf);
806 if (RT_FAILURE(rc))
807 AssertRCReturn(rc, rc);
808#ifdef DEBUG_CMD_BUFFER
809 uint8_t i = 0;
810 do {
811 Log(("hda: rirb%02x: ", i));
812 uint8_t j = 0;
813 do {
814 const char *prefix;
815 if ((i + j) == RIRBWP(pState))
816 prefix = "[W]";
817 else
818 prefix = " ";
819 Log((" %s%016lx", prefix, pState->pu64RirbBuf[i + j]));
820 } while (++j < 8);
821 Log(("\n"));
822 i += 8;
823 } while (i != 0);
824#endif
825 }
826 return rc;
827}
828
829static int hdaCORBCmdProcess(INTELHDLinkState *pState)
830{
831 int rc;
832 uint8_t corbRp;
833 uint8_t corbWp;
834 uint8_t rirbWp;
835
836 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
837
838 rc = hdaCmdSync(pState, true);
839 if (RT_FAILURE(rc))
840 AssertRCReturn(rc, rc);
841 corbRp = CORBRP(pState);
842 corbWp = CORBWP(pState);
843 rirbWp = RIRBWP(pState);
844 Assert((corbWp != corbRp));
845 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
846 while (corbRp != corbWp)
847 {
848 uint32_t cmd;
849 uint64_t resp;
850 corbRp++;
851 cmd = pState->pu32CorbBuf[corbRp];
852 rc = (pState)->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
853 if (RT_FAILURE(rc))
854 AssertRCReturn(rc, rc);
855 Assert(pfn);
856 (rirbWp)++;
857 rc = pfn(&pState->Codec, cmd, &resp);
858 if (RT_FAILURE(rc))
859 AssertRCReturn(rc, rc);
860 Log(("hda: verb:%08x->%016lx\n", cmd, resp));
861 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
862 && !HDA_REG_FLAG_VALUE(pState, GCTL, UR))
863 {
864 Log(("hda: unexpected unsolicited response.\n"));
865 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
866 return rc;
867 }
868 pState->pu64RirbBuf[rirbWp] = resp;
869 pState->u8Counter++;
870 if (pState->u8Counter == RINTCNT_N(pState))
871 break;
872 }
873 pState->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
874 pState->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
875 rc = hdaCmdSync(pState, false);
876 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pState), CORBWP(pState), RIRBWP(pState)));
877 if (RIRBCTL_RIRB_RIC(pState))
878 {
879 RIRBSTS((pState)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
880 pState->u8Counter = 0;
881 rc = hdaProcessInterrupt(pState);
882 }
883 if (RT_FAILURE(rc))
884 AssertRCReturn(rc, rc);
885 return rc;
886}
887
888static void hdaStreamReset(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
889{
890 Log(("hda: reset of stream (%d) started\n", u8Strm));
891 Assert(( pState
892 && pBdle
893 && pStreamDesc
894 && u8Strm <= 7));
895 memset(pBdle, 0, sizeof(HDABDLEDESC));
896 *pStreamDesc->pu32Lpib = 0;
897 *pStreamDesc->pu32Sts = 0;
898 /* According to ICH6 datasheet, 0x40000 is default value for stream descriptor register 23:20
899 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
900 HDA_STREAM_REG2(pState, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG2(pState, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
901
902 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
903 HDA_STREAM_REG2(pState, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
904 HDA_STREAM_REG2(pState, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
905 HDA_STREAM_REG2(pState, CBL, u8Strm) = 0;
906 HDA_STREAM_REG2(pState, LVI, u8Strm) = 0;
907 HDA_STREAM_REG2(pState, FMT, u8Strm) = 0;
908 HDA_STREAM_REG2(pState, BDPU, u8Strm) = 0;
909 HDA_STREAM_REG2(pState, BDPL, u8Strm) = 0;
910 Log(("hda: reset of stream (%d) finished\n", u8Strm));
911}
912
913
914DECLCALLBACK(int)hdaRegReadUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
915{
916 *pu32Value = 0;
917 return VINF_SUCCESS;
918}
919DECLCALLBACK(int)hdaRegWriteUnimplemented(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
920{
921 return VINF_SUCCESS;
922}
923/* U8 */
924DECLCALLBACK(int)hdaRegReadU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
925{
926 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffffff00) == 0);
927 return hdaRegReadU32(pState, offset, index, pu32Value);
928}
929
930DECLCALLBACK(int)hdaRegWriteU8(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
931{
932 Assert(((u32Value & 0xffffff00) == 0));
933 return hdaRegWriteU32(pState, offset, index, u32Value);
934}
935/* U16 */
936DECLCALLBACK(int)hdaRegReadU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
937{
938 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xffff0000) == 0);
939 return hdaRegReadU32(pState, offset, index, pu32Value);
940}
941
942DECLCALLBACK(int)hdaRegWriteU16(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
943{
944 Assert(((u32Value & 0xffff0000) == 0));
945 return hdaRegWriteU32(pState, offset, index, u32Value);
946}
947
948/* U24 */
949DECLCALLBACK(int)hdaRegReadU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
950{
951 Assert(((pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable) & 0xff000000) == 0);
952 return hdaRegReadU32(pState, offset, index, pu32Value);
953}
954
955DECLCALLBACK(int)hdaRegWriteU24(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
956{
957 Assert(((u32Value & 0xff000000) == 0));
958 return hdaRegWriteU32(pState, offset, index, u32Value);
959}
960/* U32 */
961DECLCALLBACK(int)hdaRegReadU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
962{
963 *pu32Value = pState->au32Regs[index] & s_ichIntelHDRegMap[index].readable;
964 return VINF_SUCCESS;
965}
966
967DECLCALLBACK(int)hdaRegWriteU32(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
968{
969 pState->au32Regs[index] = (u32Value & s_ichIntelHDRegMap[index].writable)
970 | (pState->au32Regs[index] & ~s_ichIntelHDRegMap[index].writable);
971 return VINF_SUCCESS;
972}
973
974DECLCALLBACK(int)hdaRegReadGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
975{
976 return hdaRegReadU32(pState, offset, index, pu32Value);
977}
978
979DECLCALLBACK(int)hdaRegWriteGCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
980{
981 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
982 {
983 /* exit reset state */
984 GCTL(pState) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
985 pState->fInReset = false;
986 }
987 else
988 {
989 /* enter reset state*/
990 if ( HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA)
991 || HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA))
992 {
993 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
994 HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) ? "on" : "off",
995 HDA_REG_FLAG_VALUE(pState, RIRBCTL, DMA) ? "on" : "off"));
996 }
997 hdaReset(ICH6_HDASTATE_2_DEVINS(pState));
998 GCTL(pState) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
999 pState->fInReset = true;
1000 }
1001 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1002 {
1003 /* Flush: GSTS:1 set, see 6.2.6*/
1004 GSTS(pState) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
1005 /* DPLBASE and DPUBASE, should be initialized with initial value (see 6.2.6)*/
1006 }
1007 return VINF_SUCCESS;
1008}
1009
1010DECLCALLBACK(int)hdaRegWriteSTATESTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1011{
1012 uint32_t v = pState->au32Regs[index];
1013 uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
1014 pState->au32Regs[index] &= ~(v & nv); /* write of 1 clears corresponding bit */
1015 return VINF_SUCCESS;
1016}
1017
1018DECLCALLBACK(int)hdaRegReadINTSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1019{
1020 uint32_t v = 0;
1021 if ( RIRBSTS_RIRBOIS(pState)
1022 || RIRBSTS_RINTFL(pState)
1023 || HDA_REG_FLAG_VALUE(pState, CORBSTS, CMEI)
1024 || STATESTS(pState))
1025 v |= RT_BIT(30);
1026#define HDA_IS_STREAM_EVENT(pState, stream) \
1027 ( (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1028 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1029 || (SDSTS((pState),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1030#define MARK_STREAM(pState, stream, v) do {(v) |= HDA_IS_STREAM_EVENT((pState),stream) ? RT_BIT((stream)) : 0;}while(0)
1031 MARK_STREAM(pState, 0, v);
1032 MARK_STREAM(pState, 1, v);
1033 MARK_STREAM(pState, 2, v);
1034 MARK_STREAM(pState, 3, v);
1035 MARK_STREAM(pState, 4, v);
1036 MARK_STREAM(pState, 5, v);
1037 MARK_STREAM(pState, 6, v);
1038 MARK_STREAM(pState, 7, v);
1039 v |= v ? RT_BIT(31) : 0;
1040 *pu32Value = v;
1041 return VINF_SUCCESS;
1042}
1043
1044DECLCALLBACK(int)hdaRegReadWALCLK(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1045{
1046 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1047 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(ICH6_HDASTATE_2_DEVINS(pState)) - pState->u64BaseTS, 24, 1000);
1048 return VINF_SUCCESS;
1049}
1050
1051DECLCALLBACK(int)hdaRegReadGCAP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1052{
1053 return hdaRegReadU16(pState, offset, index, pu32Value);
1054}
1055
1056DECLCALLBACK(int)hdaRegWriteCORBRP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1057{
1058 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1059 CORBRP(pState) = 0;
1060 else
1061 return hdaRegWriteU8(pState, offset, index, u32Value);
1062 return VINF_SUCCESS;
1063}
1064
1065DECLCALLBACK(int)hdaRegWriteCORBCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1066{
1067 int rc = hdaRegWriteU8(pState, offset, index, u32Value);
1068 AssertRC(rc);
1069 if ( CORBWP(pState) != CORBRP(pState)
1070 && HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA) != 0)
1071 return hdaCORBCmdProcess(pState);
1072 return rc;
1073}
1074
1075DECLCALLBACK(int)hdaRegWriteCORBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1076{
1077 uint32_t v = CORBSTS(pState);
1078 CORBSTS(pState) &= ~(v & u32Value);
1079 return VINF_SUCCESS;
1080}
1081
1082DECLCALLBACK(int)hdaRegWriteCORBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1083{
1084 int rc;
1085 rc = hdaRegWriteU16(pState, offset, index, u32Value);
1086 if (RT_FAILURE(rc))
1087 AssertRCReturn(rc, rc);
1088 if (CORBWP(pState) == CORBRP(pState))
1089 return VINF_SUCCESS;
1090 if (!HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1091 return VINF_SUCCESS;
1092 rc = hdaCORBCmdProcess(pState);
1093 return rc;
1094}
1095
1096DECLCALLBACK(int)hdaRegReadSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1097{
1098 return hdaRegReadU24(pState, offset, index, pu32Value);
1099}
1100
1101DECLCALLBACK(int)hdaRegWriteSDCTL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1102{
1103 bool fRun = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1104 bool fInRun = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)));
1105 bool fReset = RT_BOOL((u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1106 bool fInReset = RT_BOOL((HDA_REG_IND(pState, index) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
1107 int rc = VINF_SUCCESS;
1108 if (fInReset)
1109 {
1110 /* Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1111 * from reset
1112 */
1113 Assert((!fReset));
1114 Log(("hda: guest initiate exit of stream reset.\n"));
1115 goto done;
1116 }
1117 else if (fReset)
1118 {
1119 /*
1120 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1121 */
1122 uint8_t u8Strm = 0;
1123 PHDABDLEDESC pBdle = NULL;
1124 HDASTREAMTRANSFERDESC stStreamDesc;
1125 Assert((!fInRun && !fRun));
1126 switch (index)
1127 {
1128 case ICH6_HDA_REG_SD0CTL:
1129 u8Strm = 0;
1130 pBdle = &pState->stInBdle;
1131 break;
1132 case ICH6_HDA_REG_SD4CTL:
1133 u8Strm = 4;
1134 pBdle = &pState->stOutBdle;
1135 break;
1136 default:
1137 Log(("hda: changing SRST bit on non-attached stream\n"));
1138 goto done;
1139 }
1140 Log(("hda: guest initiate enter to stream reset.\n"));
1141 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &stStreamDesc);
1142 hdaStreamReset(pState, pBdle, &stStreamDesc, u8Strm);
1143 goto done;
1144 }
1145
1146 /* we enter here to change DMA states only */
1147 if ( (fInRun && !fRun)
1148 || (fRun && !fInRun))
1149 {
1150 Assert((!fReset && !fInReset));
1151 switch (index)
1152 {
1153 case ICH6_HDA_REG_SD0CTL:
1154 AUD_set_active_in(pState->Codec.SwVoiceIn, fRun);
1155 break;
1156 case ICH6_HDA_REG_SD4CTL:
1157 AUD_set_active_out(pState->Codec.SwVoiceOut, fRun);
1158 break;
1159 default:
1160 Log(("hda: changing RUN bit on non-attached stream\n"));
1161 goto done;
1162 }
1163 }
1164
1165 done:
1166 rc = hdaRegWriteU24(pState, offset, index, u32Value);
1167 if (RT_FAILURE(rc))
1168 AssertRCReturn(rc, VINF_SUCCESS);
1169 return rc;
1170}
1171
1172DECLCALLBACK(int)hdaRegWriteSDSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1173{
1174 uint32_t v = HDA_REG_IND(pState, index);
1175 v &= ~(u32Value & v);
1176 HDA_REG_IND(pState, index) = v;
1177 hdaProcessInterrupt(pState);
1178 return VINF_SUCCESS;
1179}
1180
1181DECLCALLBACK(int)hdaRegWriteSDLVI(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1182{
1183 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1184 if (RT_FAILURE(rc))
1185 AssertRCReturn(rc, VINF_SUCCESS);
1186 return rc;
1187}
1188
1189DECLCALLBACK(int)hdaRegWriteSDFIFOW(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1190{
1191 switch (u32Value)
1192 {
1193 case HDA_SDFIFOW_8B:
1194 case HDA_SDFIFOW_16B:
1195 case HDA_SDFIFOW_32B:
1196 return hdaRegWriteU16(pState, offset, index, u32Value);
1197 default:
1198 Log(("hda: Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1199 return hdaRegWriteU16(pState, offset, index, HDA_SDFIFOW_32B);
1200 }
1201 return VINF_SUCCESS;
1202}
1203/*
1204 * Note this method could be called for changing value on Output Streams only (ICH6 datacheet 18.2.39)
1205 *
1206 */
1207DECLCALLBACK(int)hdaRegWriteSDFIFOS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1208{
1209 switch (index)
1210 {
1211 /* SDInFIFOS is RO, n=0-3 */
1212 case ICH6_HDA_REG_SD0FIFOS:
1213 case ICH6_HDA_REG_SD1FIFOS:
1214 case ICH6_HDA_REG_SD2FIFOS:
1215 case ICH6_HDA_REG_SD3FIFOS:
1216 Log(("hda: Guest tries change value of FIFO size of Input Stream\n"));
1217 return VINF_SUCCESS;
1218 case ICH6_HDA_REG_SD4FIFOS:
1219 case ICH6_HDA_REG_SD5FIFOS:
1220 case ICH6_HDA_REG_SD6FIFOS:
1221 case ICH6_HDA_REG_SD7FIFOS:
1222 switch(u32Value)
1223 {
1224 case HDA_SDONFIFO_16B:
1225 case HDA_SDONFIFO_32B:
1226 case HDA_SDONFIFO_64B:
1227 case HDA_SDONFIFO_128B:
1228 case HDA_SDONFIFO_192B:
1229 return hdaRegWriteU16(pState, offset, index, u32Value);
1230
1231 case HDA_SDONFIFO_256B:
1232 Log(("hda: 256 bit is unsupported, HDA is switched into 192B mode\n"));
1233 default:
1234 return hdaRegWriteU16(pState, offset, index, HDA_SDONFIFO_192B);
1235 }
1236 return VINF_SUCCESS;
1237 default:
1238 AssertMsgFailed(("Something wierd happens with register lookup routine"));
1239 }
1240 return VINF_SUCCESS;
1241}
1242
1243static void inline hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pAudSetting)
1244{
1245 Assert((pAudSetting));
1246#define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1247 uint32_t u32Hz = (u32SdFmt & ICH6_HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1248 uint32_t u32HzMult = 1;
1249 uint32_t u32HzDiv = 1;
1250 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_MULT_MASK, ICH6_HDA_SDFMT_MULT_SHIFT))
1251 {
1252 case 0: u32HzMult = 1; break;
1253 case 1: u32HzMult = 2; break;
1254 case 2: u32HzMult = 3; break;
1255 case 3: u32HzMult = 4; break;
1256 default:
1257 Log(("hda: unsupported multiplier %x\n", u32SdFmt));
1258 }
1259 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_DIV_MASK, ICH6_HDA_SDFMT_DIV_SHIFT))
1260 {
1261 case 0: u32HzDiv = 1; break;
1262 case 1: u32HzDiv = 2; break;
1263 case 2: u32HzDiv = 3; break;
1264 case 3: u32HzDiv = 4; break;
1265 case 4: u32HzDiv = 5; break;
1266 case 5: u32HzDiv = 6; break;
1267 case 6: u32HzDiv = 7; break;
1268 case 7: u32HzDiv = 8; break;
1269 }
1270 pAudSetting->freq = u32Hz * u32HzMult / u32HzDiv;
1271
1272 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_BITS_MASK, ICH6_HDA_SDFMT_BITS_SHIFT))
1273 {
1274 case 0:
1275 Log(("hda: %s requested 8 bit\n", __FUNCTION__));
1276 pAudSetting->fmt = AUD_FMT_S8;
1277 break;
1278 case 1:
1279 Log(("hda: %s requested 16 bit\n", __FUNCTION__));
1280 pAudSetting->fmt = AUD_FMT_S16;
1281 break;
1282 case 2:
1283 Log(("hda: %s requested 20 bit\n", __FUNCTION__));
1284 break;
1285 case 3:
1286 Log(("hda: %s requested 24 bit\n", __FUNCTION__));
1287 break;
1288 case 4:
1289 Log(("hda: %s requested 32 bit\n", __FUNCTION__));
1290 pAudSetting->fmt = AUD_FMT_S32;
1291 break;
1292 default:
1293 AssertMsgFailed(("Unsupported"));
1294 }
1295 pAudSetting->nchannels = (u32SdFmt & 0xf) + 1;
1296 pAudSetting->fmt = AUD_FMT_S16;
1297 pAudSetting->endianness = 0;
1298#undef EXTRACT_VALUE
1299}
1300
1301DECLCALLBACK(int)hdaRegWriteSDFMT(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1302{
1303#ifdef VBOX_WITH_HDA_CODEC_EMU
1304 /* @todo here some more investigations are required. */
1305 int rc = 0;
1306 audsettings_t as;
1307 /* no reason to reopen voice with same settings */
1308 if (u32Value == HDA_REG_IND(pState, index))
1309 return VINF_SUCCESS;
1310 hdaSdFmtToAudSettings(u32Value, &as);
1311 switch (index)
1312 {
1313 case ICH6_HDA_REG_SD0FMT:
1314 rc = codecOpenVoice(&pState->Codec, PI_INDEX, &as);
1315 break;
1316 case ICH6_HDA_REG_SD4FMT:
1317 rc = codecOpenVoice(&pState->Codec, PO_INDEX, &as);
1318 break;
1319 default:
1320 Log(("HDA: attempt to change format on %d\n", index));
1321 rc = 0;
1322 }
1323 return hdaRegWriteU16(pState, offset, index, u32Value);
1324#else
1325 return hdaRegWriteU16(pState, offset, index, u32Value);
1326#endif
1327}
1328
1329DECLCALLBACK(int)hdaRegWriteSDBDPL(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1330{
1331 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1332 if (RT_FAILURE(rc))
1333 AssertRCReturn(rc, VINF_SUCCESS);
1334 return rc;
1335}
1336
1337DECLCALLBACK(int)hdaRegWriteSDBDPU(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1338{
1339 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1340 if (RT_FAILURE(rc))
1341 AssertRCReturn(rc, VINF_SUCCESS);
1342 return rc;
1343}
1344
1345DECLCALLBACK(int)hdaRegReadIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1346{
1347 int rc = VINF_SUCCESS;
1348 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1349 if ( CORBWP(pState) != CORBRP(pState)
1350 || HDA_REG_FLAG_VALUE(pState, CORBCTL, DMA))
1351 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1352
1353 rc = hdaRegReadU32(pState, offset, index, pu32Value);
1354 return rc;
1355}
1356
1357DECLCALLBACK(int)hdaRegWriteIRS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1358{
1359 int rc = VINF_SUCCESS;
1360 uint64_t resp;
1361 PFNCODECVERBPROCESSOR pfn = (PFNCODECVERBPROCESSOR)NULL;
1362 /*
1363 * if guest set ICB bit of IRS register HDA should process verb in IC register and
1364 * writes response in IR register and set IRV (valid in case of success) bit of IRS register.
1365 */
1366 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1367 && !IRS_ICB(pState))
1368 {
1369 uint32_t cmd = IC(pState);
1370 if (CORBWP(pState) != CORBRP(pState))
1371 {
1372 /*
1373 * 3.4.3 defines behaviour of immediate Command status register.
1374 */
1375 LogRel(("hda: guest has tried process immediate verb (%x) with active CORB\n", cmd));
1376 return rc;
1377 }
1378 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1379 Log(("hda: IC:%x\n", cmd));
1380 rc = pState->Codec.pfnLookup(&pState->Codec, cmd, &pfn);
1381 if (RT_FAILURE(rc))
1382 AssertRCReturn(rc, rc);
1383 rc = pfn(&pState->Codec, cmd, &resp);
1384 if (RT_FAILURE(rc))
1385 AssertRCReturn(rc, rc);
1386 IR(pState) = (uint32_t)resp;
1387 Log(("hda: IR:%x\n", IR(pState)));
1388 IRS(pState) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1389 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1390 return rc;
1391 }
1392 /*
1393 * when guest's read the response it should clean the IRV bit of the IRS register.
1394 */
1395 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1396 && IRS_IRV(pState))
1397 IRS(pState) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1398 return rc;
1399}
1400
1401DECLCALLBACK(int)hdaRegWriteRIRBWP(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1402{
1403 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1404 {
1405 RIRBWP(pState) = 0;
1406 }
1407 /*The rest of bits are O, see 6.2.22 */
1408 return VINF_SUCCESS;
1409}
1410
1411DECLCALLBACK(int)hdaRegWriteBase(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1412{
1413 int rc = hdaRegWriteU32(pState, offset, index, u32Value);
1414 if (RT_FAILURE(rc))
1415 AssertRCReturn(rc, rc);
1416 switch(index)
1417 {
1418 case ICH6_HDA_REG_CORBLBASE:
1419 pState->u64CORBBase &= 0xFFFFFFFF00000000ULL;
1420 pState->u64CORBBase |= pState->au32Regs[index];
1421 break;
1422 case ICH6_HDA_REG_CORBUBASE:
1423 pState->u64CORBBase &= 0x00000000FFFFFFFFULL;
1424 pState->u64CORBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1425 break;
1426 case ICH6_HDA_REG_RIRLBASE:
1427 pState->u64RIRBBase &= 0xFFFFFFFF00000000ULL;
1428 pState->u64RIRBBase |= pState->au32Regs[index];
1429 break;
1430 case ICH6_HDA_REG_RIRUBASE:
1431 pState->u64RIRBBase &= 0x00000000FFFFFFFFULL;
1432 pState->u64RIRBBase |= ((uint64_t)pState->au32Regs[index] << 32);
1433 break;
1434 case ICH6_HDA_REG_DPLBASE:
1435 /* @todo: first bit has special meaning */
1436 pState->u64DPBase &= 0xFFFFFFFF00000000ULL;
1437 pState->u64DPBase |= pState->au32Regs[index];
1438 break;
1439 case ICH6_HDA_REG_DPUBASE:
1440 pState->u64DPBase &= 0x00000000FFFFFFFFULL;
1441 pState->u64DPBase |= ((uint64_t)pState->au32Regs[index] << 32);
1442 break;
1443 default:
1444 AssertMsgFailed(("Invalid index"));
1445 }
1446 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pState->u64CORBBase, pState->u64RIRBBase, pState->u64DPBase));
1447 return rc;
1448}
1449
1450DECLCALLBACK(int)hdaRegWriteRIRBSTS(INTELHDLinkState* pState, uint32_t offset, uint32_t index, uint32_t u32Value)
1451{
1452 uint8_t v = RIRBSTS(pState);
1453 RIRBSTS(pState) &= ~(v & u32Value);
1454
1455 return hdaProcessInterrupt(pState);
1456}
1457
1458#ifdef LOG_ENABLED
1459static void dump_bd(INTELHDLinkState *pState, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1460{
1461#if 0
1462 uint64_t addr;
1463 uint32_t len;
1464 uint32_t ioc;
1465 uint8_t bdle[16];
1466 uint32_t counter;
1467 uint32_t i;
1468 uint32_t sum = 0;
1469 Assert(pBdle && pBdle->u32BdleMaxCvi);
1470 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1471 {
1472 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), u64BaseDMA + i*16, bdle, 16);
1473 addr = *(uint64_t *)bdle;
1474 len = *(uint32_t *)&bdle[8];
1475 ioc = *(uint32_t *)&bdle[12];
1476 Log(("hda: %s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1477 sum += len;
1478 }
1479 Log(("hda: sum: %d\n", sum));
1480 for (i = 0; i < 8; ++i)
1481 {
1482 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), (pState->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
1483 Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pState, 4) || i == SDCTL_NUM(pState, 0)? "[C]": " ",
1484 i , counter));
1485 }
1486#endif
1487}
1488#endif
1489
1490static void hdaFetchBdle(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1491{
1492 uint8_t bdle[16];
1493 Assert(( pStreamDesc->u64BaseDMA
1494 && pBdle
1495 && pBdle->u32BdleMaxCvi));
1496 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1497 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
1498 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
1499 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1500#ifdef LOG_ENABLED
1501 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1502#endif
1503}
1504
1505static inline uint32_t hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
1506{
1507 uint32_t cb2Copy;
1508 /*
1509 * Amounts of bytes depends on current position in buffer (u32BdleCviLen-u32BdleCviPos)
1510 */
1511 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
1512 cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1513 /*
1514 * we may increase the counter in range of [0, FIFOS + 1]
1515 */
1516 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
1517 Assert((u32SoundBackendBufferBytesAvail > 0));
1518
1519 /* sanity check to avoid overriding sound backend buffer */
1520 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
1521 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
1522
1523 if (cb2Copy <= pBdle->cbUnderFifoW)
1524 return 0;
1525 cb2Copy -= pBdle->cbUnderFifoW; /* forcely reserve amount of ureported bytes to copy */
1526 return cb2Copy;
1527}
1528
1529static inline void hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1530{
1531 Log(("hda:hdaBackendWriteTransferReported: cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1532 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1533 Assert((cbCopied));
1534 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
1535 /* Assertion!!! It was copied less than cbUnderFifoW
1536 * Probably we need to move the buffer, but it rather hard to imagine situation
1537 * why it may happen.
1538 */
1539 Assert((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy)); /* we assume that we write whole buffer including not reported bytes */
1540 if ( pBdle->cbUnderFifoW
1541 && pBdle->cbUnderFifoW <= cbCopied)
1542 Log(("hda:hdaBackendWriteTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1543
1544 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
1545 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Assumption failed */
1546
1547 /* We always increment position on DMA buffer counter because we're always reading to intermediate buffer */
1548 pBdle->u32BdleCviPos += cbArranged2Copy;
1549
1550 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
1551 /* We reports all bytes (including unreported previously) */
1552 *pu32DMACursor += cbCopied;
1553 /* reducing backend counter on amount of bytes we copied to backend */
1554 *pu32BackendBufferCapacity -= cbCopied;
1555 Log(("hda:hdaBackendWriteTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1556 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
1557}
1558
1559static inline void hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied, uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1560{
1561 Assert((cbCopied, cbArranged2Copy));
1562 *pu32BackendBufferCapacity -= cbCopied;
1563 pBdle->u32BdleCviPos += cbCopied;
1564 Log(("hda:hdaBackendReadTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1565 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
1566 pBdle->cbUnderFifoW = 0;
1567 Log(("hda:hdaBackendReadTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1568 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1569}
1570
1571static inline void hdaBackendTransferUnreported(INTELHDLinkState *pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
1572{
1573 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1574 pBdle->u32BdleCviPos += cbCopied;
1575 pBdle->cbUnderFifoW += cbCopied;
1576 /* In case of read transaction we're always coping from backend buffer */
1577 if (pu32BackendBufferCapacity)
1578 *pu32BackendBufferCapacity -= cbCopied;
1579 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1580 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pState, pStreamDesc)));
1581}
1582static inline bool hdaIsTransferCountersOverlapped(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1583{
1584 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
1585 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
1586
1587 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1588
1589 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1590 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
1591 hdaUpdatePosBuf(pState, pStreamDesc);
1592
1593 /* don't touch BdleCvi counter on uninitialized descriptor */
1594 if ( pBdle->u32BdleCviPos
1595 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
1596 {
1597 pBdle->u32BdleCviPos = 0;
1598 pBdle->u32BdleCvi++;
1599 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
1600 pBdle->u32BdleCvi = 0;
1601 }
1602 return fOnBufferEdge;
1603}
1604
1605static inline void hdaStreamCounterUpdate(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t cbInc)
1606{
1607 /*
1608 * if we're under FIFO Watermark it's expected that HDA doesn't fetch anything.
1609 * (ICH6 datasheet 18.2.38)
1610 */
1611 if (!pBdle->cbUnderFifoW)
1612 {
1613 *pStreamDesc->pu32Lpib += cbInc;
1614
1615 /*
1616 * Assert. Overlapping of buffer counter shouldn't happen.
1617 */
1618 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1619
1620 hdaUpdatePosBuf(pState, pStreamDesc);
1621
1622 }
1623}
1624
1625static inline bool hdaDoNextTransferCycle(PINTELHDLinkState pState, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1626{
1627 bool fDoNextTransferLoop = true;
1628 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
1629 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1630 {
1631 if ( !pBdle->cbUnderFifoW
1632 && pBdle->fBdleCviIoc)
1633 {
1634 /*
1635 * @todo - more carefully investigate BCIS flag.
1636 * Speech synthesis works fine on Mac Guest if this bit isn't set
1637 * but in general sound quality becomes lesser.
1638 */
1639 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1640
1641 /*
1642 * we should generate the interrupt if ICE bit of SDCTL register is set.
1643 */
1644 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
1645 hdaProcessInterrupt(pState);
1646 }
1647 fDoNextTransferLoop = false;
1648 }
1649 return fDoNextTransferLoop;
1650}
1651
1652/*
1653 * hdaReadAudio - copies samples from Qemu Sound back-end to DMA.
1654 * Note: this function writes immediately to DMA buffer, but "reports bytes" when all conditions meet (FIFOW)
1655 */
1656static uint32_t hdaReadAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1657{
1658 PHDABDLEDESC pBdle = &pState->stInBdle;
1659 uint32_t cbTransfered = 0;
1660 uint32_t cb2Copy = 0;
1661 uint32_t cbBackendCopy = 0;
1662
1663 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1664
1665 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1666 if (!cb2Copy)
1667 {
1668 /* if we enter here we can't report "unreported bits" */
1669 *fStop = true;
1670 goto done;
1671 }
1672
1673
1674 /*
1675 * read from backend input line to last ureported position or at the begining.
1676 */
1677 cbBackendCopy = AUD_read (pState->Codec.SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
1678 /*
1679 * write on the HDA DMA
1680 */
1681 PDMDevHlpPhysWrite(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
1682
1683 /* Don't see reasons why cb2Copy could differ from cbBackendCopy */
1684 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
1685
1686 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pState, 0))
1687 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransfered, pu32Avail);
1688 else
1689 {
1690 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
1691 *fStop = true;
1692 }
1693 done:
1694 Assert((cbTransfered <= (SDFIFOS(pState, 0) + 1)));
1695 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransfered: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransfered));
1696 return cbTransfered;
1697}
1698
1699static uint32_t hdaWriteAudio(INTELHDLinkState *pState, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1700{
1701 PHDABDLEDESC pBdle = &pState->stOutBdle;
1702 uint32_t cbTransfered = 0;
1703 uint32_t cb2Copy = 0; /* local byte counter (on local buffer) */
1704 uint32_t cbBackendCopy = 0; /* local byte counter, how many bytes copied to backend */
1705
1706 Log(("hda:wa: CVI(cvi:%d, pos:%d, len:%d)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1707
1708 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1709
1710 /*
1711 * Copy from DMA to the corresponding hdaBuffer (if there exists some bytes from the previous not reported transfer we write to ''pBdle->cbUnderFifoW'' offset)
1712 */
1713 if (!cb2Copy)
1714 {
1715 *fStop = true;
1716 goto done;
1717 }
1718
1719 PDMDevHlpPhysRead(ICH6_HDASTATE_2_DEVINS(pState), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
1720 /*
1721 * Write to audio backend. we should be sure whether we have enought bytes to copy to Audio backend.
1722 */
1723 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pState, pStreamDesc))
1724 {
1725 /*
1726 * We feed backend with new portion of fetched samples including not reported.
1727 */
1728 cbBackendCopy = AUD_write (pState->Codec.SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
1729 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransfered, pu32Avail);
1730 }
1731 else
1732 {
1733 /* Not enough bytes to be processed and reported, check luck on next enterence */
1734 hdaBackendTransferUnreported(pState, pBdle, pStreamDesc, cb2Copy, NULL);
1735 *fStop = true;
1736 }
1737
1738 done:
1739 Assert((cbTransfered <= (SDFIFOS(pState, 4) + 1)));
1740 Log(("hda:wa: CVI(pos:%d, len:%d, cbTransfered:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransfered));
1741 return cbTransfered;
1742}
1743
1744DECLCALLBACK(int) hdaCodecReset(CODECState *pCodecState)
1745{
1746 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1747 return VINF_SUCCESS;
1748}
1749
1750static inline void hdaInitTransferDescriptor(PINTELHDLinkState pState, PHDABDLEDESC pBdle, uint8_t u8Strm, PHDASTREAMTRANSFERDESC pStreamDesc)
1751{
1752 Assert(( pState
1753 && pBdle
1754 && pStreamDesc
1755 && u8Strm <= 7));
1756 memset(pStreamDesc, 0, sizeof(HDASTREAMTRANSFERDESC));
1757 pStreamDesc->u8Strm = u8Strm;
1758 pStreamDesc->u32Ctl = HDA_STREAM_REG2(pState, CTL, u8Strm);
1759 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG2(pState, BDPL, u8Strm),
1760 HDA_STREAM_REG2(pState, BDPU, u8Strm));
1761 pStreamDesc->pu32Lpib = &HDA_STREAM_REG2(pState, LPIB, u8Strm);
1762 pStreamDesc->pu32Sts = &HDA_STREAM_REG2(pState, STS, u8Strm);
1763 pStreamDesc->u32Cbl = HDA_STREAM_REG2(pState, CBL, u8Strm);
1764 pStreamDesc->u32Fifos = HDA_STREAM_REG2(pState, FIFOS, u8Strm);
1765
1766 pBdle->u32BdleMaxCvi = HDA_STREAM_REG2(pState, LVI, u8Strm);
1767#ifdef LOG_ENABLED
1768 if ( pBdle
1769 && pBdle->u32BdleMaxCvi)
1770 {
1771 Log(("Initialization of transfer descriptor:\n"));
1772 dump_bd(pState, pBdle, pStreamDesc->u64BaseDMA);
1773 }
1774#endif
1775}
1776
1777DECLCALLBACK(void) hdaTransfer(CODECState *pCodecState, ENMSOUNDSOURCE src, int avail)
1778{
1779 bool fStop = false;
1780 uint8_t u8Strm = 0;
1781 PHDABDLEDESC pBdle = NULL;
1782 INTELHDLinkState *pState = (INTELHDLinkState *)pCodecState->pHDAState;
1783 HDASTREAMTRANSFERDESC stStreamDesc;
1784 uint32_t nBytes;
1785 switch (src)
1786 {
1787 case PO_INDEX:
1788 {
1789 u8Strm = 4;
1790 pBdle = &pState->stOutBdle;
1791 break;
1792 }
1793 case PI_INDEX:
1794 {
1795 u8Strm = 0;
1796 pBdle = &pState->stInBdle;
1797 break;
1798 }
1799 default:
1800 return;
1801 }
1802 hdaInitTransferDescriptor(pState, pBdle, u8Strm, &stStreamDesc);
1803 while( avail && !fStop)
1804 {
1805 Assert ( (stStreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1806 && avail
1807 && stStreamDesc.u64BaseDMA);
1808
1809 /* Fetch the Buffer Descriptor Entry (BDE). */
1810
1811 if (hdaIsTransferCountersOverlapped(pState, pBdle, &stStreamDesc))
1812 hdaFetchBdle(pState, pBdle, &stStreamDesc);
1813 *stStreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1814 Assert((avail >= 0 && (stStreamDesc.u32Cbl >= (*stStreamDesc.pu32Lpib)))); /* sanity */
1815 uint32_t u32CblLimit = stStreamDesc.u32Cbl - (*stStreamDesc.pu32Lpib);
1816 Assert((u32CblLimit > hdaFifoWToSz(pState, &stStreamDesc)));
1817 Log(("hda: CBL=%d, LPIB=%d\n", stStreamDesc.u32Cbl, *stStreamDesc.pu32Lpib));
1818 switch (src)
1819 {
1820 case PO_INDEX:
1821 nBytes = hdaWriteAudio(pState, &stStreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1822 break;
1823 case PI_INDEX:
1824 nBytes = hdaReadAudio(pState, &stStreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
1825 break;
1826 default:
1827 nBytes = 0;
1828 fStop = true;
1829 AssertMsgFailed(("Unsupported"));
1830 }
1831 Assert(nBytes <= (stStreamDesc.u32Fifos + 1));
1832 *stStreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1833
1834 /* Process end of buffer condition. */
1835 hdaStreamCounterUpdate(pState, pBdle, &stStreamDesc, nBytes);
1836 fStop = !fStop ? !hdaDoNextTransferCycle(pState, pBdle, &stStreamDesc) : fStop;
1837 }
1838}
1839
1840/**
1841 * Handle register read operation.
1842 *
1843 * Looks up and calls appropriate handler.
1844 *
1845 * @note: while implementation was detected so called "forgotten" or "hole" registers
1846 * which description is missed in RPM, datasheet or spec.
1847 *
1848 * @returns VBox status code.
1849 *
1850 * @param pState The device state structure.
1851 * @param uOffset Register offset in memory-mapped frame.
1852 * @param pv Where to fetch the value.
1853 * @param cb Number of bytes to write.
1854 * @thread EMT
1855 */
1856PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1857{
1858 int rc = VINF_SUCCESS;
1859 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1860 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1861 int index = hdaLookup(&pThis->hda, u32Offset);
1862 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1863 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1864
1865 if ( index == -1
1866 || cb > 4)
1867 LogRel(("hda: Invalid read access @0x%x(of bytes:%d)\n", u32Offset, cb));
1868
1869 if (index != -1)
1870 {
1871 uint32_t mask = 0;
1872 uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1873 uint32_t v = 0;
1874 switch(cb)
1875 {
1876 case 1: mask = 0x000000ff; break;
1877 case 2: mask = 0x0000ffff; break;
1878 case 3: mask = 0x00ffffff; break;
1879 case 4: mask = 0xffffffff; break;
1880 }
1881 mask <<= shift;
1882 rc = s_ichIntelHDRegMap[index].pfnRead(&pThis->hda, u32Offset, index, &v);
1883 *(uint32_t *)pv = (v & mask) >> shift;
1884 Log(("hda: read %s[%x/%x]\n", s_ichIntelHDRegMap[index].abbrev, v, *(uint32_t *)pv));
1885 return rc;
1886 }
1887 *(uint32_t *)pv = 0xFF;
1888 Log(("hda: hole at %X is accessed for read\n", u32Offset));
1889 return rc;
1890}
1891
1892/**
1893 * Handle register write operation.
1894 *
1895 * Looks up and calls appropriate handler.
1896 *
1897 * @returns VBox status code.
1898 *
1899 * @param pState The device state structure.
1900 * @param uOffset Register offset in memory-mapped frame.
1901 * @param pv Where to fetch the value.
1902 * @param cb Number of bytes to write.
1903 * @thread EMT
1904 */
1905PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
1906{
1907 int rc = VINF_SUCCESS;
1908 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1909 uint32_t u32Offset = GCPhysAddr - pThis->hda.addrMMReg;
1910 int index = hdaLookup(&pThis->hda, u32Offset);
1911
1912 if (pThis->hda.fInReset && index != ICH6_HDA_REG_GCTL)
1913 Log(("hda: access to registers except GCTL is blocked while reset\n"));
1914
1915 if ( index == -1
1916 || cb > 4)
1917 LogRel(("hda: Invalid write access @0x%x(of bytes:%d)\n", u32Offset, cb));
1918
1919 if (index != -1)
1920 {
1921 /** @todo r=bird: What is all this masking and shifting about? And
1922 * WHY ON EARTH are you writing to the input data?!? */
1923 uint32_t v = pThis->hda.au32Regs[index];
1924 uint32_t mask = 0;
1925 uint32_t shift = (u32Offset - s_ichIntelHDRegMap[index].offset) % sizeof(uint32_t) * 8;
1926 switch(cb)
1927 {
1928 case 1: mask = 0xffffff00; break;
1929 case 2: mask = 0xffff0000; break;
1930 case 3: mask = 0xff000000; break;
1931 case 4: mask = 0x00000000; break;
1932 }
1933 mask <<= shift;
1934 *(uint32_t *)pv = ((v & mask) | (*(uint32_t *)pv & ~mask)) >> shift;
1935 rc = s_ichIntelHDRegMap[index].pfnWrite(&pThis->hda, u32Offset, index, *(uint32_t *)pv);
1936 Log(("hda: write %s:(%x) %x => %x\n", s_ichIntelHDRegMap[index].abbrev, *(uint32_t *)pv, v, pThis->hda.au32Regs[index]));
1937 return rc;
1938 }
1939 Log(("hda: hole at %X is accessed for write\n", u32Offset));
1940 return rc;
1941}
1942
1943/**
1944 * Callback function for mapping a PCI I/O region.
1945 *
1946 * @return VBox status code.
1947 * @param pPciDev Pointer to PCI device.
1948 * Use pPciDev->pDevIns to get the device instance.
1949 * @param iRegion The region number.
1950 * @param GCPhysAddress Physical address of the region.
1951 * If iType is PCI_ADDRESS_SPACE_IO, this is an
1952 * I/O port, else it's a physical address.
1953 * This address is *NOT* relative
1954 * to pci_mem_base like earlier!
1955 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
1956 */
1957static DECLCALLBACK(int) hdaMap (PPCIDEVICE pPciDev, int iRegion,
1958 RTGCPHYS GCPhysAddress, uint32_t cb,
1959 PCIADDRESSSPACE enmType)
1960{
1961 int rc;
1962 PPDMDEVINS pDevIns = pPciDev->pDevIns;
1963 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
1964 PCIINTELHDLinkState *pThis = PCIDEV_2_ICH6_HDASTATE(pPciDev);
1965
1966 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
1967 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, 0,
1968 hdaMMIOWrite, hdaMMIORead, NULL, "ICH6_HDA");
1969
1970 if (RT_FAILURE(rc))
1971 return rc;
1972
1973 pThis->hda.addrMMReg = GCPhysAddress;
1974 return VINF_SUCCESS;
1975}
1976
1977/**
1978 * Saves a state of the HDA device.
1979 *
1980 * @returns VBox status code.
1981 * @param pDevIns The device instance.
1982 * @param pSSMHandle The handle to save the state to.
1983 */
1984static DECLCALLBACK(int) hdaSaveExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1985{
1986 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
1987 /* Save Codec nodes states */
1988 codecSaveState(&pThis->hda.Codec, pSSMHandle);
1989 /* Save MMIO registers */
1990 SSMR3PutMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
1991 /* Save HDA dma counters */
1992 SSMR3PutStruct (pSSMHandle, &pThis->hda.stOutBdle, g_aHdaBDLEDescFields);
1993 SSMR3PutStruct (pSSMHandle, &pThis->hda.stMicBdle, g_aHdaBDLEDescFields);
1994 SSMR3PutStruct (pSSMHandle, &pThis->hda.stInBdle, g_aHdaBDLEDescFields);
1995 return VINF_SUCCESS;
1996}
1997
1998/**
1999 * Loads a saved HDA device state.
2000 *
2001 * @returns VBox status code.
2002 * @param pDevIns The device instance.
2003 * @param pSSMHandle The handle to the saved state.
2004 * @param uVersion The data unit version number.
2005 * @param uPass The data pass.
2006 */
2007static DECLCALLBACK(int) hdaLoadExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
2008 uint32_t uVersion, uint32_t uPass)
2009{
2010 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2011 /* Load Codec nodes states */
2012 Assert (uPass == SSM_PASS_FINAL); NOREF(uPass);
2013
2014 codecLoadState(&pThis->hda.Codec, pSSMHandle, uVersion);
2015 /* Load MMIO registers */
2016 SSMR3GetMem (pSSMHandle, pThis->hda.au32Regs, sizeof (pThis->hda.au32Regs));
2017 /* Load HDA dma counters */
2018 if ( uVersion == HDA_SSM_VERSION_1
2019 || uVersion == HDA_SSM_VERSION_2)
2020 {
2021 SSMR3GetMem (pSSMHandle, &pThis->hda.stOutBdle, sizeof (HDABDLEDESC));
2022 SSMR3GetMem (pSSMHandle, &pThis->hda.stMicBdle, sizeof (HDABDLEDESC));
2023 SSMR3GetMem (pSSMHandle, &pThis->hda.stInBdle, sizeof (HDABDLEDESC));
2024 }
2025 else
2026 {
2027 SSMR3GetStruct (pSSMHandle, &pThis->hda.stOutBdle, g_aHdaBDLEDescFields);
2028 SSMR3GetStruct (pSSMHandle, &pThis->hda.stMicBdle, g_aHdaBDLEDescFields);
2029 SSMR3GetStruct (pSSMHandle, &pThis->hda.stInBdle, g_aHdaBDLEDescFields);
2030 }
2031
2032
2033 AUD_set_active_in(pThis->hda.Codec.SwVoiceIn, SDCTL(&pThis->hda, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2034 AUD_set_active_out(pThis->hda.Codec.SwVoiceOut, SDCTL(&pThis->hda, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2035
2036 pThis->hda.u64CORBBase = CORBLBASE(&pThis->hda);
2037 pThis->hda.u64CORBBase |= ((uint64_t)CORBUBASE(&pThis->hda)) << 32;
2038 pThis->hda.u64RIRBBase = RIRLBASE(&pThis->hda);
2039 pThis->hda.u64RIRBBase |= ((uint64_t)RIRUBASE(&pThis->hda)) << 32;
2040 pThis->hda.u64DPBase = DPLBASE(&pThis->hda);
2041 pThis->hda.u64DPBase |= ((uint64_t)DPUBASE(&pThis->hda)) << 32;
2042 return VINF_SUCCESS;
2043}
2044
2045/**
2046 * Reset notification.
2047 *
2048 * @returns VBox status.
2049 * @param pDevIns The device instance data.
2050 *
2051 * @remark The original sources didn't install a reset handler, but it seems to
2052 * make sense to me so we'll do it.
2053 */
2054static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
2055{
2056 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2057 GCAP(&pThis->hda) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
2058 VMIN(&pThis->hda) = 0x00; /* see 6.2.2 */
2059 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
2060 VMAJ(&pThis->hda) = 0x01; /* see 6.2.3 */
2061 OUTPAY(&pThis->hda) = 0x003C; /* see 6.2.4 */
2062 INPAY(&pThis->hda) = 0x001D; /* see 6.2.5 */
2063 pThis->hda.au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
2064 pThis->hda.au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
2065 CORBRP(&pThis->hda) = 0x0;
2066 RIRBWP(&pThis->hda) = 0x0;
2067
2068 Log(("hda: inter HDA reset.\n"));
2069 pThis->hda.cbCorbBuf = 256 * sizeof(uint32_t);
2070
2071 if (pThis->hda.pu32CorbBuf)
2072 memset(pThis->hda.pu32CorbBuf, 0, pThis->hda.cbCorbBuf);
2073 else
2074 pThis->hda.pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->hda.cbCorbBuf);
2075
2076 pThis->hda.cbRirbBuf = 256 * sizeof(uint64_t);
2077 if (pThis->hda.pu64RirbBuf)
2078 memset(pThis->hda.pu64RirbBuf, 0, pThis->hda.cbRirbBuf);
2079 else
2080 pThis->hda.pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->hda.cbRirbBuf);
2081
2082 pThis->hda.u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
2083
2084 HDABDLEDESC stEmptyBdle;
2085 for(uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
2086 {
2087 HDASTREAMTRANSFERDESC stStreamDesc;
2088 PHDABDLEDESC pBdle = NULL;
2089 if (u8Strm == 0)
2090 pBdle = &pThis->hda.stInBdle;
2091 else if(u8Strm == 4)
2092 pBdle = &pThis->hda.stOutBdle;
2093 else
2094 {
2095 memset(&stEmptyBdle, 0, sizeof(HDABDLEDESC));
2096 pBdle = &stEmptyBdle;
2097 }
2098 hdaInitTransferDescriptor(&pThis->hda, pBdle, u8Strm, &stStreamDesc);
2099 /* hdaStreamReset prevents changing SRST bit, so we zerro it here forcely. */
2100 HDA_STREAM_REG2(&pThis->hda, CTL, u8Strm) = 0;
2101 hdaStreamReset(&pThis->hda, pBdle, &stStreamDesc, u8Strm);
2102 }
2103
2104 /* emulateion of codec "wake up" HDA spec (5.5.1 and 6.5)*/
2105 STATESTS(&pThis->hda) = 0x1;
2106
2107 Log(("hda: reset finished\n"));
2108}
2109
2110/**
2111 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2112 */
2113static DECLCALLBACK(void *) hdaQueryInterface (struct PDMIBASE *pInterface,
2114 const char *pszIID)
2115{
2116 PCIINTELHDLinkState *pThis = RT_FROM_MEMBER(pInterface, PCIINTELHDLinkState, hda.IBase);
2117 Assert(&pThis->hda.IBase == pInterface);
2118
2119 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->hda.IBase);
2120 return NULL;
2121}
2122
2123static inline int hdaLookUpRegisterByName(INTELHDLinkState *pState, const char *pszArgs)
2124{
2125 int iReg = 0;
2126 for (; iReg < HDA_NREGS; ++iReg)
2127 if (!RTStrICmp(s_ichIntelHDRegMap[iReg].abbrev, pszArgs))
2128 return iReg;
2129 return -1;
2130}
2131static inline void hdaDbgPrintRegister(INTELHDLinkState *pState, PCDBGFINFOHLP pHlp, int iHdaIndex)
2132{
2133 Assert( pState
2134 && iHdaIndex >= 0
2135 && iHdaIndex < HDA_NREGS);
2136 pHlp->pfnPrintf(pHlp, "hda: %s: 0x%x\n", s_ichIntelHDRegMap[iHdaIndex].abbrev, pState->au32Regs[iHdaIndex]);
2137}
2138static DECLCALLBACK(void) hdaDbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2139{
2140 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2141 INTELHDLinkState *hda = &pThis->hda;
2142 int iHdaRegisterIndex = hdaLookUpRegisterByName(hda, pszArgs);
2143 if (iHdaRegisterIndex != -1)
2144 hdaDbgPrintRegister(hda, pHlp, iHdaRegisterIndex);
2145 else
2146 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
2147 hdaDbgPrintRegister(hda, pHlp, iHdaRegisterIndex);
2148}
2149
2150static inline void hdaDbgPrintStream(INTELHDLinkState *pState, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
2151{
2152 Assert( pState
2153 && iHdaStrmIndex >= 0
2154 && iHdaStrmIndex < 7);
2155 pHlp->pfnPrintf(pHlp, "Dump of %d Hda Stream:\n", iHdaStrmIndex);
2156 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, CTL, iHdaStrmIndex));
2157 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, STS, iHdaStrmIndex));
2158 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOS, iHdaStrmIndex));
2159 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG2(pState, FIFOW, iHdaStrmIndex));
2160}
2161
2162static inline int hdaLookUpStreamIndex(INTELHDLinkState *pState, const char *pszArgs)
2163{
2164 /* todo: add args parsing */
2165 return -1;
2166}
2167static DECLCALLBACK(void) hdaDbgStreamInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2168{
2169 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2170 INTELHDLinkState *hda = &pThis->hda;
2171 int iHdaStrmIndex = hdaLookUpStreamIndex(hda, pszArgs);
2172 if (iHdaStrmIndex != -1)
2173 hdaDbgPrintStream(hda, pHlp, iHdaStrmIndex);
2174 else
2175 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
2176 hdaDbgPrintStream(hda, pHlp, iHdaStrmIndex);
2177}
2178
2179/* Codec debugger interface */
2180static DECLCALLBACK(void) hdaCodecDbgNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2181{
2182 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2183 INTELHDLinkState *hda = &pThis->hda;
2184 if (hda->Codec.pfnCodecDbgListNodes)
2185 hda->Codec.pfnCodecDbgListNodes(&hda->Codec, pHlp, pszArgs);
2186 else
2187 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2188}
2189
2190static DECLCALLBACK(void) hdaCodecDbgSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2191{
2192 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2193 INTELHDLinkState *hda = &pThis->hda;
2194 if (hda->Codec.pfnCodecDbgSelector)
2195 hda->Codec.pfnCodecDbgSelector(&hda->Codec, pHlp, pszArgs);
2196 else
2197 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2198}
2199
2200//#define HDA_AS_PCI_EXPRESS
2201/* Misc routines */
2202static inline bool printHdaIsValid(const char *pszType, const char *pszExpectedFlag)
2203{
2204 return (RTStrCmp(pszType, pszExpectedFlag) == 0);
2205}
2206static const char *printHdaYesNo(bool fFlag)
2207{
2208 return fFlag ? "yes" : "no";
2209}
2210static DECLCALLBACK(size_t)
2211printHdaStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2212 const char *pszType, void const *pvValue,
2213 int cchWidth, int cchPrecision, unsigned fFlags,
2214 void *pvUser)
2215{
2216 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
2217 size_t cb = 0;
2218 if (!printHdaIsValid(pszType, "sdctl"))
2219 return cb;
2220 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2221 "SDCTL(raw: %#0x, strm:0x%x, dir:%s, tp:%s strip:%x, deie:%s, ioce:%s, run:%s, srst:%s)",
2222 sdCtl,
2223 ((sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> ICH6_HDA_SDCTL_NUM_SHIFT),
2224 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR))),
2225 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP))),
2226 ((sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> ICH6_HDA_SDCTL_STRIPE_SHIFT),
2227 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE))),
2228 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))),
2229 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))),
2230 printHdaYesNo(RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST))));
2231 return cb;
2232}
2233
2234static DECLCALLBACK(size_t)
2235printHdaStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2236 const char *pszType, void const *pvValue,
2237 int cchWidth, int cchPrecision, unsigned fFlags,
2238 void *pvUser)
2239{
2240 uint32_t sdFifos = (uint32_t)(uintptr_t)pvValue;
2241 uint32_t u32Bytes = 0;
2242 size_t cb = 0;
2243 if (!printHdaIsValid(pszType, "sdfifos"))
2244 return cb;
2245 switch(sdFifos)
2246 {
2247 case HDA_SDONFIFO_16B: u32Bytes = 16; break;
2248 case HDA_SDONFIFO_32B: u32Bytes = 32; break;
2249 case HDA_SDONFIFO_64B: u32Bytes = 64; break;
2250 case HDA_SDONFIFO_128B: u32Bytes = 128; break;
2251 case HDA_SDONFIFO_192B: u32Bytes = 192; break;
2252 case HDA_SDONFIFO_256B: u32Bytes = 256; break;
2253 case HDA_SDINFIFO_120B: u32Bytes = 120; break;
2254 case HDA_SDINFIFO_160B: u32Bytes = 160; break;
2255 default:;
2256 }
2257 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2258 "SDFIFOS(raw: %#0x, sdfifos:%d B)",
2259 sdFifos,
2260 u32Bytes);
2261 return cb;
2262}
2263
2264static DECLCALLBACK(size_t)
2265printHdaStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2266 const char *pszType, void const *pvValue,
2267 int cchWidth, int cchPrecision, unsigned fFlags,
2268 void *pvUser)
2269{
2270 uint32_t sdFifow = (uint32_t)(uintptr_t)pvValue;
2271 uint32_t u32Bytes = 0;
2272 size_t cb = 0;
2273 if (!printHdaIsValid(pszType, "sdfifow"))
2274 return cb;
2275 switch(sdFifow)
2276 {
2277 case HDA_SDFIFOW_8B: u32Bytes = 8; break;
2278 case HDA_SDFIFOW_16B: u32Bytes = 16; break;
2279 case HDA_SDFIFOW_32B: u32Bytes = 32; break;
2280 }
2281 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2282 "SDFIFOW(raw: %#0x, sdfifow:%d B)",
2283 sdFifow,
2284 u32Bytes);
2285 return cb;
2286}
2287
2288static DECLCALLBACK(size_t)
2289printHdaStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2290 const char *pszType, void const *pvValue,
2291 int cchWidth, int cchPrecision, unsigned fFlags,
2292 void *pvUser)
2293{
2294 uint32_t sdSts = (uint32_t)(uintptr_t)pvValue;
2295 size_t cb = 0;
2296 if (!printHdaIsValid(pszType, "sdsts"))
2297 return cb;
2298 cb += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2299 "SDSTS(raw: %#0x, fifordy:%s, dese:%s, fifoe:%s, bcis:%s)",
2300 sdSts,
2301 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY))),
2302 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE))),
2303 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE))),
2304 printHdaYesNo(RT_BOOL(sdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS))));
2305 return cb;
2306}
2307/**
2308 * This routine registers debugger info extensions and custom printf formatters
2309 */
2310static inline int hdaInitMisc(PPDMDEVINS pDevIns)
2311{
2312 int rc;
2313 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaDbgInfo);
2314 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaDbgStreamInfo);
2315 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaCodecDbgNodes);
2316 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaCodecDbgSelector);
2317 rc = RTStrFormatTypeRegister("sdctl", printHdaStrmCtl, NULL);
2318 AssertRC(rc);
2319 rc = RTStrFormatTypeRegister("sdsts", printHdaStrmSts, NULL);
2320 AssertRC(rc);
2321 rc = RTStrFormatTypeRegister("sdfifos", printHdaStrmFifos, NULL);
2322 AssertRC(rc);
2323 rc = RTStrFormatTypeRegister("sdfifow", printHdaStrmFifow, NULL);
2324 AssertRC(rc);
2325#if 0
2326 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
2327 AssertRC(rc);
2328#endif
2329 return rc;
2330}
2331
2332/**
2333 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2334 */
2335static DECLCALLBACK(int) hdaConstruct (PPDMDEVINS pDevIns, int iInstance,
2336 PCFGMNODE pCfgHandle)
2337{
2338 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2339 INTELHDLinkState *s = &pThis->hda;
2340 int rc;
2341
2342 Assert(iInstance == 0);
2343 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2344
2345 /*
2346 * Validations.
2347 */
2348 if (!CFGMR3AreValuesValid (pCfgHandle, "\0"))
2349 return PDMDEV_SET_ERROR (pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2350 N_ ("Invalid configuration for the INTELHD device"));
2351
2352 // ** @todo r=michaln: This device may need R0/RC enabling, especially if guests
2353 // poll some register(s).
2354
2355 /*
2356 * Initialize data (most of it anyway).
2357 */
2358 s->pDevIns = pDevIns;
2359 /* IBase */
2360 s->IBase.pfnQueryInterface = hdaQueryInterface;
2361
2362 /* PCI Device (the assertions will be removed later) */
2363 PCIDevSetVendorId (&pThis->dev, HDA_PCI_VENDOR_ID); /* nVidia */
2364 PCIDevSetDeviceId (&pThis->dev, HDA_PCI_DEICE_ID); /* HDA */
2365
2366 PCIDevSetCommand (&pThis->dev, 0x0000); /* 04 rw,ro - pcicmd. */
2367 PCIDevSetStatus (&pThis->dev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
2368 PCIDevSetRevisionId (&pThis->dev, 0x01); /* 08 ro - rid. */
2369 PCIDevSetClassProg (&pThis->dev, 0x00); /* 09 ro - pi. */
2370 PCIDevSetClassSub (&pThis->dev, 0x03); /* 0a ro - scc; 03 == HDA. */
2371 PCIDevSetClassBase (&pThis->dev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
2372 PCIDevSetHeaderType (&pThis->dev, 0x00); /* 0e ro - headtyp. */
2373 PCIDevSetBaseAddress (&pThis->dev, 0, /* 10 rw - MMIO */
2374 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
2375 PCIDevSetInterruptLine (&pThis->dev, 0x00); /* 3c rw. */
2376 PCIDevSetInterruptPin (&pThis->dev, 0x01); /* 3d ro - INTA#. */
2377
2378#if defined(HDA_AS_PCI_EXPRESS)
2379 PCIDevSetCapabilityList (&pThis->dev, 0x80);
2380#elif defined(VBOX_WITH_MSI_DEVICES)
2381 PCIDevSetCapabilityList (&pThis->dev, 0x60);
2382#else
2383 PCIDevSetCapabilityList (&pThis->dev, 0x50); /* ICH6 datasheet 18.1.16 */
2384#endif
2385
2386 //** @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
2387 // of these values needs to be properly documented!
2388 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
2389 PCIDevSetByte(&pThis->dev, 0x40, 0x01);
2390
2391 /* Power Management */
2392 PCIDevSetByte(&pThis->dev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
2393 PCIDevSetByte(&pThis->dev, 0x50 + 1, 0x0); /* next */
2394 PCIDevSetWord(&pThis->dev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
2395
2396#ifdef HDA_AS_PCI_EXPRESS
2397 /* PCI Express */
2398 PCIDevSetByte (&pThis->dev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
2399 PCIDevSetByte (&pThis->dev, 0x80 + 1, 0x60); /* next */
2400 /* Device flags */
2401 PCIDevSetWord (&pThis->dev, 0x80 + 2,
2402 /* version */ 0x1 |
2403 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
2404 /* MSI */ (100) << 9
2405 );
2406 /* Device capabilities */
2407 PCIDevSetDWord (&pThis->dev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
2408 /* Device control */
2409 PCIDevSetWord (&pThis->dev, 0x80 + 8, 0);
2410 /* Device status */
2411 PCIDevSetWord (&pThis->dev, 0x80 + 10, 0);
2412 /* Link caps */
2413 PCIDevSetDWord (&pThis->dev, 0x80 + 12, 0);
2414 /* Link control */
2415 PCIDevSetWord (&pThis->dev, 0x80 + 16, 0);
2416 /* Link status */
2417 PCIDevSetWord (&pThis->dev, 0x80 + 18, 0);
2418 /* Slot capabilities */
2419 PCIDevSetDWord (&pThis->dev, 0x80 + 20, 0);
2420 /* Slot control */
2421 PCIDevSetWord (&pThis->dev, 0x80 + 24, 0);
2422 /* Slot status */
2423 PCIDevSetWord (&pThis->dev, 0x80 + 26, 0);
2424 /* Root control */
2425 PCIDevSetWord (&pThis->dev, 0x80 + 28, 0);
2426 /* Root capabilities */
2427 PCIDevSetWord (&pThis->dev, 0x80 + 30, 0);
2428 /* Root status */
2429 PCIDevSetDWord (&pThis->dev, 0x80 + 32, 0);
2430 /* Device capabilities 2 */
2431 PCIDevSetDWord (&pThis->dev, 0x80 + 36, 0);
2432 /* Device control 2 */
2433 PCIDevSetQWord (&pThis->dev, 0x80 + 40, 0);
2434 /* Link control 2 */
2435 PCIDevSetQWord (&pThis->dev, 0x80 + 48, 0);
2436 /* Slot control 2 */
2437 PCIDevSetWord (&pThis->dev, 0x80 + 56, 0);
2438#endif
2439
2440 /*
2441 * Register the PCI device.
2442 */
2443 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
2444 if (RT_FAILURE (rc))
2445 return rc;
2446
2447 rc = PDMDevHlpPCIIORegionRegister (pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM,
2448 hdaMap);
2449 if (RT_FAILURE (rc))
2450 return rc;
2451
2452#ifdef VBOX_WITH_MSI_DEVICES
2453 PDMMSIREG aMsiReg;
2454
2455 RT_ZERO(aMsiReg);
2456 aMsiReg.cMsiVectors = 1;
2457 aMsiReg.iMsiCapOffset = 0x60;
2458 aMsiReg.iMsiNextOffset = 0x50;
2459 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
2460 if (RT_FAILURE (rc))
2461 {
2462 LogRel(("Chipset cannot do MSI: %Rrc\n", rc));
2463 PCIDevSetCapabilityList (&pThis->dev, 0x50);
2464 }
2465#endif
2466
2467 rc = PDMDevHlpSSMRegister (pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
2468 if (RT_FAILURE (rc))
2469 return rc;
2470
2471 /*
2472 * Attach driver.
2473 */
2474 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase,
2475 &s->pDrvBase, "Audio Driver Port");
2476 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2477 Log (("hda: No attached driver!\n"));
2478 else if (RT_FAILURE (rc))
2479 {
2480 AssertMsgFailed (("Failed to attach INTELHD LUN #0! rc=%Rrc\n", rc));
2481 return rc;
2482 }
2483
2484
2485
2486 pThis->hda.Codec.pHDAState = (void *)&pThis->hda;
2487 rc = codecConstruct(pDevIns, &pThis->hda.Codec, pCfgHandle);
2488 if (RT_FAILURE(rc))
2489 AssertRCReturn(rc, rc);
2490
2491 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
2492 verb F20 should provide device/codec recognition. */
2493 Assert(pThis->hda.Codec.u16VendorId);
2494 Assert(pThis->hda.Codec.u16DeviceId);
2495 PCIDevSetSubSystemVendorId (&pThis->dev, pThis->hda.Codec.u16VendorId); /* 2c ro - intel.) */
2496 PCIDevSetSubSystemId (&pThis->dev, pThis->hda.Codec.u16DeviceId); /* 2e ro. */
2497
2498 hdaReset (pDevIns);
2499 pThis->hda.Codec.id = 0;
2500 pThis->hda.Codec.pfnTransfer = hdaTransfer;
2501 pThis->hda.Codec.pfnReset = hdaCodecReset;
2502 /*
2503 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
2504 * hdaReset shouldn't affects these registers.
2505 */
2506 WAKEEN(&pThis->hda) = 0x0;
2507 STATESTS(&pThis->hda) = 0x0;
2508 hdaInitMisc(pDevIns);
2509
2510 return VINF_SUCCESS;
2511}
2512
2513/**
2514 * @interface_method_impl{PDMDEVREG,pfnDestruct}
2515 */
2516static DECLCALLBACK(int) hdaDestruct (PPDMDEVINS pDevIns)
2517{
2518 PCIINTELHDLinkState *pThis = PDMINS_2_DATA(pDevIns, PCIINTELHDLinkState *);
2519
2520 int rc = codecDestruct(&pThis->hda.Codec);
2521 AssertRC(rc);
2522 if (pThis->hda.pu32CorbBuf)
2523 RTMemFree(pThis->hda.pu32CorbBuf);
2524 if (pThis->hda.pu64RirbBuf)
2525 RTMemFree(pThis->hda.pu64RirbBuf);
2526 return VINF_SUCCESS;
2527}
2528
2529/**
2530 * The device registration structure.
2531 */
2532const PDMDEVREG g_DeviceICH6_HDA =
2533{
2534 /* u32Version */
2535 PDM_DEVREG_VERSION,
2536 /* szName */
2537 "hda",
2538 /* szRCMod */
2539 "",
2540 /* szR0Mod */
2541 "",
2542 /* pszDescription */
2543 "ICH IntelHD Audio Controller",
2544 /* fFlags */
2545 PDM_DEVREG_FLAGS_DEFAULT_BITS,
2546 /* fClass */
2547 PDM_DEVREG_CLASS_AUDIO,
2548 /* cMaxInstances */
2549 1,
2550 /* cbInstance */
2551 sizeof(PCIINTELHDLinkState),
2552 /* pfnConstruct */
2553 hdaConstruct,
2554 /* pfnDestruct */
2555 hdaDestruct,
2556 /* pfnRelocate */
2557 NULL,
2558 /* pfnIOCtl */
2559 NULL,
2560 /* pfnPowerOn */
2561 NULL,
2562 /* pfnReset */
2563 hdaReset,
2564 /* pfnSuspend */
2565 NULL,
2566 /* pfnResume */
2567 NULL,
2568 /* pfnAttach */
2569 NULL,
2570 /* pfnDetach */
2571 NULL,
2572 /* pfnQueryInterface. */
2573 NULL,
2574 /* pfnInitComplete */
2575 NULL,
2576 /* pfnPowerOff */
2577 NULL,
2578 /* pfnSoftReset */
2579 NULL,
2580 /* u32VersionEnd */
2581 PDM_DEVREG_VERSION
2582};
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