VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 54234

Last change on this file since 54234 was 54234, checked in by vboxsync, 10 years ago

PDM/Audio: Make HDA emulation work w/ disabled backends.
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1/* $Id: DevIchHda.cpp 54234 2015-02-17 15:04:53Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2015 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/vmm/pdmaudioifs.h>
27#include <VBox/version.h>
28
29#include <iprt/assert.h>
30#include <iprt/asm.h>
31#include <iprt/asm-math.h>
32#ifdef IN_RING3
33# include <iprt/uuid.h>
34# include <iprt/string.h>
35# include <iprt/mem.h>
36#endif
37#include <iprt/list.h>
38
39#ifdef LOG_GROUP
40# undef LOG_GROUP
41#endif
42#define LOG_GROUP LOG_GROUP_DEV_AUDIO
43#include <VBox/log.h>
44
45#include "VBoxDD.h"
46
47#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
48# include "AudioMixer.h"
49#else
50 extern "C" {
51 #include "audio.h"
52 }
53#endif
54#include "DevIchHdaCodec.h"
55
56/*******************************************************************************
57* Defined Constants And Macros *
58*******************************************************************************/
59//#define HDA_AS_PCI_EXPRESS
60#define VBOX_WITH_INTEL_HDA
61
62#if (defined(DEBUG) && defined(DEBUG_andy))
63/* Enables experimental support for separate mic-in handling.
64 Do not enable this yet for regular builds, as this needs more testing first! */
65# define VBOX_WITH_HDA_MIC_IN
66#endif
67
68#if defined(VBOX_WITH_HP_HDA)
69/* HP Pavilion dv4t-1300 */
70# define HDA_PCI_VENDOR_ID 0x103c
71# define HDA_PCI_DEVICE_ID 0x30f7
72#elif defined(VBOX_WITH_INTEL_HDA)
73/* Intel HDA controller */
74# define HDA_PCI_VENDOR_ID 0x8086
75# define HDA_PCI_DEVICE_ID 0x2668
76#elif defined(VBOX_WITH_NVIDIA_HDA)
77/* nVidia HDA controller */
78# define HDA_PCI_VENDOR_ID 0x10de
79# define HDA_PCI_DEVICE_ID 0x0ac0
80#else
81# error "Please specify your HDA device vendor/device IDs"
82#endif
83
84/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
85 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
86 * is read only except for bit 15 like the HDA spec states.
87 *
88 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
89 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
90#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
91
92#define HDA_NREGS 114
93#define HDA_NREGS_SAVED 112
94
95/**
96 * NB: Register values stored in memory (au32Regs[]) are indexed through
97 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
98 * register descriptors in g_aHdaRegMap[] are indexed through the
99 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
100 *
101 * The au32Regs[] layout is kept unchanged for saved state
102 * compatibility. */
103
104/* Registers */
105#define HDA_REG_IND_NAME(x) HDA_REG_##x
106#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
107#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
108#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
109#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
110#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
111#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
112#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
113
114
115#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
116#define HDA_RMX_GCAP 0
117/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
118 * oss (15:12) - number of output streams supported
119 * iss (11:8) - number of input streams supported
120 * bss (7:3) - number of bidirectional streams supported
121 * bds (2:1) - number of serial data out signals supported
122 * b64sup (0) - 64 bit addressing supported.
123 */
124#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
125 ( (((oss) & 0xF) << 12) \
126 | (((iss) & 0xF) << 8) \
127 | (((bss) & 0x1F) << 3) \
128 | (((bds) & 0x3) << 2) \
129 | ((b64sup) & 1))
130
131#define HDA_REG_VMIN 1 /* 0x02 */
132#define HDA_RMX_VMIN 1
133
134#define HDA_REG_VMAJ 2 /* 0x03 */
135#define HDA_RMX_VMAJ 2
136
137#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
138#define HDA_RMX_OUTPAY 3
139
140#define HDA_REG_INPAY 4 /* 0x06-0x07 */
141#define HDA_RMX_INPAY 4
142
143#define HDA_REG_GCTL 5 /* 0x08-0x0B */
144#define HDA_RMX_GCTL 5
145#define HDA_GCTL_RST_SHIFT 0
146#define HDA_GCTL_FSH_SHIFT 1
147#define HDA_GCTL_UR_SHIFT 8
148
149#define HDA_REG_WAKEEN 6 /* 0x0C */
150#define HDA_RMX_WAKEEN 6
151
152#define HDA_REG_STATESTS 7 /* 0x0E */
153#define HDA_RMX_STATESTS 7
154#define HDA_STATES_SCSF 0x7
155
156#define HDA_REG_GSTS 8 /* 0x10-0x11*/
157#define HDA_RMX_GSTS 8
158#define HDA_GSTS_FSH_SHIFT 1
159
160#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
161#define HDA_RMX_OUTSTRMPAY 112
162
163#define HDA_REG_INSTRMPAY 10 /* 0x1a */
164#define HDA_RMX_INSTRMPAY 113
165
166#define HDA_REG_INTCTL 11 /* 0x20 */
167#define HDA_RMX_INTCTL 9
168#define HDA_INTCTL_GIE_SHIFT 31
169#define HDA_INTCTL_CIE_SHIFT 30
170#define HDA_INTCTL_S0_SHIFT 0
171#define HDA_INTCTL_S1_SHIFT 1
172#define HDA_INTCTL_S2_SHIFT 2
173#define HDA_INTCTL_S3_SHIFT 3
174#define HDA_INTCTL_S4_SHIFT 4
175#define HDA_INTCTL_S5_SHIFT 5
176#define HDA_INTCTL_S6_SHIFT 6
177#define HDA_INTCTL_S7_SHIFT 7
178#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
179
180#define HDA_REG_INTSTS 12 /* 0x24 */
181#define HDA_RMX_INTSTS 10
182#define HDA_INTSTS_GIS_SHIFT 31
183#define HDA_INTSTS_CIS_SHIFT 30
184#define HDA_INTSTS_S0_SHIFT 0
185#define HDA_INTSTS_S1_SHIFT 1
186#define HDA_INTSTS_S2_SHIFT 2
187#define HDA_INTSTS_S3_SHIFT 3
188#define HDA_INTSTS_S4_SHIFT 4
189#define HDA_INTSTS_S5_SHIFT 5
190#define HDA_INTSTS_S6_SHIFT 6
191#define HDA_INTSTS_S7_SHIFT 7
192#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
193
194#define HDA_REG_WALCLK 13 /* 0x24 */
195#define HDA_RMX_WALCLK /* Not defined! */
196
197/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
198 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
199 * the datasheet.
200 */
201#define HDA_REG_SSYNC 14 /* 0x34 */
202#define HDA_RMX_SSYNC 12
203
204#define HDA_REG_CORBLBASE 15 /* 0x40 */
205#define HDA_RMX_CORBLBASE 13
206
207#define HDA_REG_CORBUBASE 16 /* 0x44 */
208#define HDA_RMX_CORBUBASE 14
209
210#define HDA_REG_CORBWP 17 /* 0x48 */
211#define HDA_RMX_CORBWP 15
212
213#define HDA_REG_CORBRP 18 /* 0x4A */
214#define HDA_RMX_CORBRP 16
215#define HDA_CORBRP_RST_SHIFT 15
216#define HDA_CORBRP_WP_SHIFT 0
217#define HDA_CORBRP_WP_MASK 0xFF
218
219#define HDA_REG_CORBCTL 19 /* 0x4C */
220#define HDA_RMX_CORBCTL 17
221#define HDA_CORBCTL_DMA_SHIFT 1
222#define HDA_CORBCTL_CMEIE_SHIFT 0
223
224#define HDA_REG_CORBSTS 20 /* 0x4D */
225#define HDA_RMX_CORBSTS 18
226#define HDA_CORBSTS_CMEI_SHIFT 0
227
228#define HDA_REG_CORBSIZE 21 /* 0x4E */
229#define HDA_RMX_CORBSIZE 19
230#define HDA_CORBSIZE_SZ_CAP 0xF0
231#define HDA_CORBSIZE_SZ 0x3
232/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
233
234#define HDA_REG_RIRBLBASE 22 /* 0x50 */
235#define HDA_RMX_RIRBLBASE 20
236
237#define HDA_REG_RIRBUBASE 23 /* 0x54 */
238#define HDA_RMX_RIRBUBASE 21
239
240#define HDA_REG_RIRBWP 24 /* 0x58 */
241#define HDA_RMX_RIRBWP 22
242#define HDA_RIRBWP_RST_SHIFT 15
243#define HDA_RIRBWP_WP_MASK 0xFF
244
245#define HDA_REG_RINTCNT 25 /* 0x5A */
246#define HDA_RMX_RINTCNT 23
247#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
248
249#define HDA_REG_RIRBCTL 26 /* 0x5C */
250#define HDA_RMX_RIRBCTL 24
251#define HDA_RIRBCTL_RIC_SHIFT 0
252#define HDA_RIRBCTL_DMA_SHIFT 1
253#define HDA_ROI_DMA_SHIFT 2
254
255#define HDA_REG_RIRBSTS 27 /* 0x5D */
256#define HDA_RMX_RIRBSTS 25
257#define HDA_RIRBSTS_RINTFL_SHIFT 0
258#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
259
260#define HDA_REG_RIRBSIZE 28 /* 0x5E */
261#define HDA_RMX_RIRBSIZE 26
262#define HDA_RIRBSIZE_SZ_CAP 0xF0
263#define HDA_RIRBSIZE_SZ 0x3
264
265#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
266#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
267
268
269#define HDA_REG_IC 29 /* 0x60 */
270#define HDA_RMX_IC 27
271
272#define HDA_REG_IR 30 /* 0x64 */
273#define HDA_RMX_IR 28
274
275#define HDA_REG_IRS 31 /* 0x68 */
276#define HDA_RMX_IRS 29
277#define HDA_IRS_ICB_SHIFT 0
278#define HDA_IRS_IRV_SHIFT 1
279
280#define HDA_REG_DPLBASE 32 /* 0x70 */
281#define HDA_RMX_DPLBASE 30
282#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
283
284#define HDA_REG_DPUBASE 33 /* 0x74 */
285#define HDA_RMX_DPUBASE 31
286#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
287#define DPBASE_ENABLED 1
288#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
289
290#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
291#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
292/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
293#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
294
295#define HDA_REG_SD0CTL 34 /* 0x80 */
296#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
297#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
298#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
299#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
300#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
301#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
302#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
303#define HDA_RMX_SD0CTL 32
304#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
305#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
306#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
307#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
308#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
309#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
310#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
311
312#define SD(func, num) SD##num##func
313#define SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
314#define SDCTL_NUM(pThis, num) ((SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
315#define HDA_SDCTL_NUM_MASK 0xF
316#define HDA_SDCTL_NUM_SHIFT 20
317#define HDA_SDCTL_DIR_SHIFT 19
318#define HDA_SDCTL_TP_SHIFT 18
319#define HDA_SDCTL_STRIPE_MASK 0x3
320#define HDA_SDCTL_STRIPE_SHIFT 16
321#define HDA_SDCTL_DEIE_SHIFT 4
322#define HDA_SDCTL_FEIE_SHIFT 3
323#define HDA_SDCTL_ICE_SHIFT 2
324#define HDA_SDCTL_RUN_SHIFT 1
325#define HDA_SDCTL_SRST_SHIFT 0
326
327#define HDA_REG_SD0STS 35 /* 0x83 */
328#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
329#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
330#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
331#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
332#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
333#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
334#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
335#define HDA_RMX_SD0STS 33
336#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
337#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
338#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
339#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
340#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
341#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
342#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
343
344#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
345#define HDA_SDSTS_FIFORDY_SHIFT 5
346#define HDA_SDSTS_DE_SHIFT 4
347#define HDA_SDSTS_FE_SHIFT 3
348#define HDA_SDSTS_BCIS_SHIFT 2
349
350#define HDA_REG_SD0LPIB 36 /* 0x84 */
351#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
352#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
353#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
354#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
355#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
356#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
357#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
358#define HDA_RMX_SD0LPIB 34
359#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
360#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
361#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
362#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
363#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
364#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
365#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
366
367#define HDA_REG_SD0CBL 37 /* 0x88 */
368#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
369#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
370#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
371#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
372#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
373#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
374#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
375#define HDA_RMX_SD0CBL 35
376#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
377#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
378#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
379#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
380#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
381#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
382#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
383
384
385#define HDA_REG_SD0LVI 38 /* 0x8C */
386#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
387#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
388#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
389#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
390#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
391#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
392#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
393#define HDA_RMX_SD0LVI 36
394#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
395#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
396#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
397#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
398#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
399#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
400#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
401
402#define HDA_REG_SD0FIFOW 39 /* 0x8E */
403#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
404#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
405#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
406#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
407#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
408#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
409#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
410#define HDA_RMX_SD0FIFOW 37
411#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
412#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
413#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
414#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
415#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
416#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
417#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
418
419/*
420 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
421 */
422#define HDA_SDFIFOW_8B 0x2
423#define HDA_SDFIFOW_16B 0x3
424#define HDA_SDFIFOW_32B 0x4
425
426#define HDA_REG_SD0FIFOS 40 /* 0x90 */
427#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
428#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
429#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
430#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
431#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
432#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
433#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
434#define HDA_RMX_SD0FIFOS 38
435#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
436#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
437#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
438#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
439#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
440#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
441#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
442
443/*
444 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
445 * formula: size - 1
446 * Other values not listed are not supported.
447 */
448#define HDA_SDONFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
449#define HDA_SDONFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
450#define HDA_SDONFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
451#define HDA_SDONFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
452#define HDA_SDONFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
453#define HDA_SDONFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
454#define HDA_SDINFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
455#define HDA_SDINFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
456#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
457
458#define HDA_REG_SD0FMT 41 /* 0x92 */
459#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
460#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
461#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
462#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
463#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
464#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
465#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
466#define HDA_RMX_SD0FMT 39
467#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
468#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
469#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
470#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
471#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
472#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
473#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
474
475#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
476#define HDA_SDFMT_BASE_RATE_SHIFT 14
477#define HDA_SDFMT_MULT_SHIFT 11
478#define HDA_SDFMT_MULT_MASK 0x7
479#define HDA_SDFMT_DIV_SHIFT 8
480#define HDA_SDFMT_DIV_MASK 0x7
481#define HDA_SDFMT_BITS_SHIFT 4
482#define HDA_SDFMT_BITS_MASK 0x7
483#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
484#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
485#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
486
487#define HDA_REG_SD0BDPL 42 /* 0x98 */
488#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
489#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
490#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
491#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
492#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
493#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
494#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
495#define HDA_RMX_SD0BDPL 40
496#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
497#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
498#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
499#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
500#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
501#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
502#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
503
504#define HDA_REG_SD0BDPU 43 /* 0x9C */
505#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
506#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
507#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
508#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
509#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
510#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
511#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
512#define HDA_RMX_SD0BDPU 41
513#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
514#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
515#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
516#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
517#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
518#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
519#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
520
521#define HDA_CODEC_CAD_SHIFT 28
522/* Encodes the (required) LUN into a codec command. */
523#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
524
525
526
527/*******************************************************************************
528* Structures and Typedefs *
529*******************************************************************************/
530typedef struct HDABDLEDESC
531{
532 uint64_t u64BdleCviAddr;
533 uint32_t u32BdleMaxCvi;
534 uint32_t u32BdleCvi;
535 uint32_t u32BdleCviLen;
536 uint32_t u32BdleCviPos;
537 bool fBdleCviIoc;
538 uint32_t cbUnderFifoW;
539 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
540} HDABDLEDESC, *PHDABDLEDESC;
541
542typedef struct HDASTREAMTRANSFERDESC
543{
544 uint64_t u64BaseDMA;
545 uint32_t u32Ctl;
546 uint32_t *pu32Sts;
547 uint8_t u8Strm;
548 uint32_t *pu32Lpib;
549 uint32_t u32Cbl;
550 uint32_t u32Fifos;
551} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
552
553#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
554typedef struct HDAINPUTSTREAM
555{
556 /** PCM line input stream. */
557 R3PTRTYPE(PPDMAUDIOGSTSTRMIN) pStrmIn;
558 /** Mixer handle for line input stream. */
559 R3PTRTYPE(PAUDMIXSTREAM) phStrmIn;
560} HDAINPUTSTREAM, *PHDAINPUTSTREAM;
561
562typedef struct HDAOUTPUTSTREAM
563{
564 /** PCM output stream. */
565 R3PTRTYPE(PPDMAUDIOGSTSTRMOUT) pStrmOut;
566} HDAOUTPUTSTREAM, *PHDAOUTPUTSTREAM;
567
568/**
569 * Struct for maintaining a host backend driver.
570 * This driver must be associated to one, and only one,
571 * HDA codec. The HDA controller does the actual multiplexing
572 * of HDA codec data to various host backend drivers then.
573 *
574 * This HDA device uses a timer in order to synchronize all
575 * read/write accesses across all attached LUNs / backends.
576 */
577typedef struct HDADRIVER
578{
579 union
580 {
581 /** Node for storing this driver in our device driver
582 * list of HDASTATE. */
583 RTLISTNODE Node;
584 struct
585 {
586 R3PTRTYPE(void *) dummy1;
587 R3PTRTYPE(void *) dummy2;
588 } dummy;
589 };
590
591 /** Pointer to HDA controller (state). */
592 R3PTRTYPE(PHDASTATE) pHDAState;
593 /** Driver flags. */
594 PDMAUDIODRVFLAGS Flags;
595 uint8_t u32Padding0[3];
596 /** LUN to which this driver has been assigned. */
597 uint8_t uLUN;
598 /** Audio connector interface to the underlying
599 * host backend. */
600 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
601 /** Stream for line input. */
602 HDAINPUTSTREAM LineIn;
603 /** Stream for mic input. */
604 HDAINPUTSTREAM MicIn;
605 /** Stream for output. */
606 HDAOUTPUTSTREAM Out;
607 /** Number of samples to play (output), needed
608 * for the timer routine. */
609 uint32_t cSamplesLive;
610} HDADRIVER, *PHDADRIVER;
611#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
612
613/**
614 * ICH Intel HD Audio Controller state.
615 */
616typedef struct HDASTATE
617{
618 /** The PCI device structure. */
619 PCIDevice PciDev;
620 /** R3 Pointer to the device instance. */
621 PPDMDEVINSR3 pDevInsR3;
622 /** R0 Pointer to the device instance. */
623 PPDMDEVINSR0 pDevInsR0;
624 /** R0 Pointer to the device instance. */
625 PPDMDEVINSRC pDevInsRC;
626
627 uint32_t u32Padding;
628
629 /** Pointer to the attached audio driver. */
630 R3PTRTYPE(PPDMIBASE) pDrvBase;
631 /** The base interface for LUN\#0. */
632 PDMIBASE IBase;
633 RTGCPHYS MMIOBaseAddr;
634 uint32_t au32Regs[HDA_NREGS];
635 HDABDLEDESC StInBdle;
636 HDABDLEDESC StOutBdle;
637 HDABDLEDESC StMicBdle;
638 uint64_t u64CORBBase;
639 uint64_t u64RIRBBase;
640 uint64_t u64DPBase;
641 /** Pointer to CORB buffer. */
642 R3PTRTYPE(uint32_t *) pu32CorbBuf;
643 /** Size in bytes of CORB buffer. */
644 uint32_t cbCorbBuf;
645 uint32_t u32Padding2;
646 /** Pointer to RIRB buffer. */
647 R3PTRTYPE(uint64_t *) pu64RirbBuf;
648 /** Size in bytes of RIRB buffer. */
649 uint32_t cbRirbBuf;
650 /** Indicates if HDA is in reset. */
651 bool fInReset;
652 /** Interrupt on completion */
653 bool fCviIoc;
654 /** Flag whether the R0 part is enabled. */
655 bool fR0Enabled;
656 /** Flag whether the RC part is enabled. */
657 bool fRCEnabled;
658#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
659 /** The emulation timer for handling the attached
660 * LUN drivers. */
661 PTMTIMERR3 pTimer;
662 /** Timer ticks for handling the LUN drivers. */
663 uint64_t uTicks;
664# ifdef VBOX_WITH_STATISTICS
665 STAMPROFILE StatTimer;
666 STAMCOUNTER StatBytesRead;
667 STAMCOUNTER StatBytesWritten;
668# endif
669 /** Pointer to HDA codec to use. */
670 R3PTRTYPE(PHDACODEC) pCodec;
671 union
672 {
673 /** List of associated LUN drivers. */
674 RTLISTANCHOR lstDrv;
675 struct
676 {
677 R3PTRTYPE(void *) dummy1;
678 R3PTRTYPE(void *) dummy2;
679 } dummy;
680 };
681 /** The device' software mixer. */
682 R3PTRTYPE(PAUDIOMIXER) pMixer;
683 /** Audio mixer sink for line input. */
684 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
685 /** Audio mixer sink for microphone input. */
686 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
687#else /* !VBOX_WITH_PDM_AUDIO_DRIVER */
688 /** The HDA codec to use. */
689 R3PTRTYPE(PHDACODEC) pCodec;
690#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
691 uint64_t u64BaseTS;
692 /** 1.2.3.4.5.6.7. - someone please tell me what I'm counting! - .8.9.10... */
693 uint8_t u8Counter;
694#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
695 uint8_t au8Padding[7];
696#else
697 uint8_t au8Padding[7];
698#endif
699} HDASTATE;
700/** Pointer to the ICH Intel HD Audio Controller state. */
701typedef HDASTATE *PHDASTATE;
702
703#define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \
704 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, In, SDFMT_BASE_RATE(pThis, 0), SDFMT_MULT(pThis, 0), SDFMT_DIV(pThis, 0)) )
705#define OSD0FMT_TO_AUDIO_SELECTOR(pThis) \
706 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, Out, SDFMT_BASE_RATE(pThis, 4), SDFMT_MULT(pThis, 4), SDFMT_DIV(pThis, 4)) )
707
708
709/*******************************************************************************
710* Internal Functions *
711*******************************************************************************/
712#ifndef VBOX_DEVICE_STRUCT_TESTCASE
713static FNPDMDEVRESET hdaReset;
714
715static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
716static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
717static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
718static int hdaRegReadSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
719static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
720static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
721static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
722static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
723static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
724static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
725static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
726static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
727static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
728static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
729static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
730static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
731static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
732
733static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
734static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
735static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
736static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
737static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
738static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
739static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
740static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
741static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
742static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
743static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
744static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
745static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
746static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
747static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
748static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
749
750#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
751static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser);
752static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t cbAvail);
753#else
754static int hdaTransfer(PHDACODEC pCodec, ENMSOUNDSOURCE enmSource, int cbAvail);
755#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
756
757#ifdef IN_RING3
758DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
759 PHDASTREAMTRANSFERDESC pStreamDesc);
760static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
761#ifdef LOG_ENABLED
762static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
763#endif
764#endif
765
766
767/*******************************************************************************
768* Global Variables *
769*******************************************************************************/
770
771/* see 302349 p 6.2*/
772static const struct HDAREGDESC
773{
774 /** Register offset in the register space. */
775 uint32_t offset;
776 /** Size in bytes. Registers of size > 4 are in fact tables. */
777 uint32_t size;
778 /** Readable bits. */
779 uint32_t readable;
780 /** Writable bits. */
781 uint32_t writable;
782 /** Read callback. */
783 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
784 /** Write callback. */
785 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
786 /** Index into the register storage array. */
787 uint32_t mem_idx;
788 /** Abbreviated name. */
789 const char *abbrev;
790} g_aHdaRegMap[HDA_NREGS] =
791
792/* Turn a short register name into an memory index and a stringized name. */
793#define RA(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
794/* Same as above for an input stream ('I' prefixed). */
795#define IA(abbrev) HDA_MEM_IND_NAME(abbrev), "I"#abbrev
796/* Same as above for an output stream ('O' prefixed). */
797#define OA(abbrev) HDA_MEM_IND_NAME(abbrev), "O"#abbrev
798/* Same as above for a register *not* stored in memory. */
799#define UA(abbrev) 0, #abbrev
800
801{
802 /* offset size read mask write mask read callback write callback abbrev */
803 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- */
804 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(GCAP) }, /* Global Capabilities */
805 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMIN) }, /* Minor Version */
806 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMAJ) }, /* Major Version */
807 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTPAY) }, /* Output Payload Capabilities */
808 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INPAY) }, /* Input Payload Capabilities */
809 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , RA(GCTL) }, /* Global Control */
810 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , RA(WAKEEN) }, /* Wake Enable */
811 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , RA(STATESTS) }, /* State Change Status */
812 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , RA(GSTS) }, /* Global Status */
813 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTSTRMPAY)}, /* Output Stream Payload Capability */
814 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INSTRMPAY) }, /* Input Stream Payload Capability */
815 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(INTCTL) }, /* Interrupt Control */
816 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , RA(INTSTS) }, /* Interrupt Status */
817 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , UA(WALCLK) }, /* Wall Clock Counter */
818 /// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
819 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(SSYNC) }, /* Stream Synchronization */
820 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(CORBLBASE) }, /* CORB Lower Base Address */
821 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(CORBUBASE) }, /* CORB Upper Base Address */
822 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , RA(CORBWP) }, /* CORB Write Pointer */
823 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , RA(CORBRP) }, /* CORB Read Pointer */
824 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , RA(CORBCTL) }, /* CORB Control */
825 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , RA(CORBSTS) }, /* CORB Status */
826 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(CORBSIZE) }, /* CORB Size */
827 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBLBASE) }, /* RIRB Lower Base Address */
828 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBUBASE) }, /* RIRB Upper Base Address */
829 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , RA(RIRBWP) }, /* RIRB Write Pointer */
830 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , RA(RINTCNT) }, /* Response Interrupt Count */
831 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , RA(RIRBCTL) }, /* RIRB Control */
832 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , RA(RIRBSTS) }, /* RIRB Status */
833 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(RIRBSIZE) }, /* RIRB Size */
834 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , RA(IC) }, /* Immediate Command */
835 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , RA(IR) }, /* Immediate Response */
836 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , RA(IRS) }, /* Immediate Command Status */
837 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , RA(DPLBASE) }, /* MA Position Lower Base */
838 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(DPUBASE) }, /* DMA Position Upper Base */
839
840 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD0CTL) }, /* Input Stream Descriptor 0 (ICD0) Control */
841 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD0STS) }, /* ISD0 Status */
842 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0LPIB) }, /* ISD0 Link Position In Buffer */
843 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0CBL) }, /* ISD0 Cyclic Buffer Length */
844 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD0LVI) }, /* ISD0 Last Valid Index */
845 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD0FIFOW) }, /* ISD0 FIFO Watermark */
846 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD0FIFOS) }, /* ISD0 FIFO Size */
847 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD0FMT) }, /* ISD0 Format */
848 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD0BDPL) }, /* ISD0 Buffer Descriptor List Pointer-Lower Base Address */
849 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD0BDPU) }, /* ISD0 Buffer Descriptor List Pointer-Upper Base Address */
850
851 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD1CTL) }, /* Input Stream Descriptor 1 (ISD1) Control */
852 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD1STS) }, /* ISD1 Status */
853 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1LPIB) }, /* ISD1 Link Position In Buffer */
854 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1CBL) }, /* ISD1 Cyclic Buffer Length */
855 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD1LVI) }, /* ISD1 Last Valid Index */
856 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD1FIFOW) }, /* ISD1 FIFO Watermark */
857 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD1FIFOS) }, /* ISD1 FIFO Size */
858 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD1FMT) }, /* ISD1 Format */
859 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD1BDPL) }, /* ISD1 Buffer Descriptor List Pointer-Lower Base Address */
860 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD1BDPU) }, /* ISD1 Buffer Descriptor List Pointer-Upper Base Address */
861
862 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD2CTL) }, /* Input Stream Descriptor 2 (ISD2) Control */
863 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD2STS) }, /* ISD2 Status */
864 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2LPIB) }, /* ISD2 Link Position In Buffer */
865 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2CBL) }, /* ISD2 Cyclic Buffer Length */
866 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD2LVI) }, /* ISD2 Last Valid Index */
867 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD2FIFOW) }, /* ISD2 FIFO Watermark */
868 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD2FIFOS) }, /* ISD2 FIFO Size */
869 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD2FMT) }, /* ISD2 Format */
870 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD2BDPL) }, /* ISD2 Buffer Descriptor List Pointer-Lower Base Address */
871 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD2BDPU) }, /* ISD2 Buffer Descriptor List Pointer-Upper Base Address */
872
873 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD3CTL) }, /* Input Stream Descriptor 3 (ISD3) Control */
874 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD3STS) }, /* ISD3 Status */
875 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3LPIB) }, /* ISD3 Link Position In Buffer */
876 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3CBL) }, /* ISD3 Cyclic Buffer Length */
877 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD3LVI) }, /* ISD3 Last Valid Index */
878 { 0x000EE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD3FIFOW) }, /* ISD3 FIFO Watermark */
879 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD3FIFOS) }, /* ISD3 FIFO Size */
880 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD3FMT) }, /* ISD3 Format */
881 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD3BDPL) }, /* ISD3 Buffer Descriptor List Pointer-Lower Base Address */
882 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD3BDPU) }, /* ISD3 Buffer Descriptor List Pointer-Upper Base Address */
883
884 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD4CTL) }, /* Output Stream Descriptor 4 (OSD4) Control */
885 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD4STS) }, /* OSD4 Status */
886 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4LPIB) }, /* OSD4 Link Position In Buffer */
887 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4CBL) }, /* OSD4 Cyclic Buffer Length */
888 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD4LVI) }, /* OSD4 Last Valid Index */
889 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD4FIFOW) }, /* OSD4 FIFO Watermark */
890 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD4FIFOS) }, /* OSD4 FIFO Size */
891 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD4FMT) }, /* OSD4 Format */
892 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD4BDPL) }, /* OSD4 Buffer Descriptor List Pointer-Lower Base Address */
893 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD4BDPU) }, /* OSD4 Buffer Descriptor List Pointer-Upper Base Address */
894
895 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD5CTL) }, /* Output Stream Descriptor 5 (OSD5) Control */
896 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD5STS) }, /* OSD5 Status */
897 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5LPIB) }, /* OSD5 Link Position In Buffer */
898 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5CBL) }, /* OSD5 Cyclic Buffer Length */
899 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD5LVI) }, /* OSD5 Last Valid Index */
900 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD5FIFOW) }, /* OSD5 FIFO Watermark */
901 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD5FIFOS) }, /* OSD5 FIFO Size */
902 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD5FMT) }, /* OSD5 Format */
903 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD5BDPL) }, /* OSD5 Buffer Descriptor List Pointer-Lower Base Address */
904 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD5BDPU) }, /* OSD5 Buffer Descriptor List Pointer-Upper Base Address */
905
906 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD6CTL) }, /* Output Stream Descriptor 6 (OSD6) Control */
907 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD6STS) }, /* OSD6 Status */
908 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6LPIB) }, /* OSD6 Link Position In Buffer */
909 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6CBL) }, /* OSD6 Cyclic Buffer Length */
910 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD6LVI) }, /* OSD6 Last Valid Index */
911 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD6FIFOW) }, /* OSD6 FIFO Watermark */
912 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD6FIFOS) }, /* OSD6 FIFO Size */
913 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD6FMT) }, /* OSD6 Format */
914 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD6BDPL) }, /* OSD6 Buffer Descriptor List Pointer-Lower Base Address */
915 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD6BDPU) }, /* OSD6 Buffer Descriptor List Pointer-Upper Base Address */
916
917 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD7CTL) }, /* Output Stream Descriptor 7 (OSD7) Control */
918 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD7STS) }, /* OSD7 Status */
919 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7LPIB) }, /* OSD7 Link Position In Buffer */
920 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7CBL) }, /* OSD7 Cyclic Buffer Length */
921 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD7LVI) }, /* OSD7 Last Valid Index */
922 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD7FIFOW) }, /* OSD7 FIFO Watermark */
923 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD7FIFOS) }, /* OSD7 FIFO Size */
924 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD7FMT) }, /* OSD7 Format */
925 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD7BDPL) }, /* OSD7 Buffer Descriptor List Pointer-Lower Base Address */
926 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD7BDPU) }, /* OSD7 Buffer Descriptor List Pointer-Upper Base Address */
927};
928
929/**
930 * HDA register aliases (HDA spec 3.3.45).
931 * @remarks Sorted by offReg.
932 */
933static const struct
934{
935 /** The alias register offset. */
936 uint32_t offReg;
937 /** The register index. */
938 int idxAlias;
939} g_aHdaRegAliases[] =
940{
941 { 0x2084, HDA_REG_SD0LPIB },
942 { 0x20a4, HDA_REG_SD1LPIB },
943 { 0x20c4, HDA_REG_SD2LPIB },
944 { 0x20e4, HDA_REG_SD3LPIB },
945 { 0x2104, HDA_REG_SD4LPIB },
946 { 0x2124, HDA_REG_SD5LPIB },
947 { 0x2144, HDA_REG_SD6LPIB },
948 { 0x2164, HDA_REG_SD7LPIB },
949};
950
951#ifdef IN_RING3
952/** HDABDLEDESC field descriptors the v3+ saved state. */
953static SSMFIELD const g_aHdaBDLEDescFields[] =
954{
955 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
956 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
957 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
958 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
959 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
960 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
961 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
962 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
963 SSMFIELD_ENTRY_TERM()
964};
965
966/** HDABDLEDESC field descriptors the v1 and v2 saved state. */
967static SSMFIELD const g_aHdaBDLEDescFieldsOld[] =
968{
969 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
970 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
971 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
972 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
973 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
974 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
975 SSMFIELD_ENTRY_PAD_HC_AUTO(3, 3),
976 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
977 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
978 SSMFIELD_ENTRY_TERM()
979};
980#endif
981
982/**
983 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
984 */
985static uint32_t const g_afMasks[5] =
986{
987 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
988};
989
990#ifdef IN_RING3
991DECLINLINE(void) hdaUpdatePosBuf(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
992{
993 if (pThis->u64DPBase & DPBASE_ENABLED)
994 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
995 (pThis->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm * 8,
996 pStreamDesc->pu32Lpib, sizeof(uint32_t));
997}
998#endif
999
1000DECLINLINE(uint32_t) hdaFifoWToSz(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
1001{
1002#if 0
1003 switch(HDA_STREAM_REG(pThis, FIFOW, pStreamDesc->u8Strm))
1004 {
1005 case HDA_SDFIFOW_8B: return 8;
1006 case HDA_SDFIFOW_16B: return 16;
1007 case HDA_SDFIFOW_32B: return 32;
1008 default:
1009 AssertMsgFailed(("unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pThis, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
1010 }
1011#endif
1012 return 0;
1013}
1014
1015static int hdaProcessInterrupt(PHDASTATE pThis)
1016{
1017#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
1018 ( INTCTL_SX((pThis), num) \
1019 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1020 bool fIrq = false;
1021 if ( HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
1022 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1023 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1024 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1025 fIrq = true;
1026
1027 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1028 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
1029 fIrq = true;
1030
1031 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1032 {
1033 LogFunc(("irq %s\n", fIrq ? "asserted" : "deasserted"));
1034 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , fIrq);
1035 }
1036 return VINF_SUCCESS;
1037}
1038
1039/**
1040 * Looks up a register at the exact offset given by @a offReg.
1041 *
1042 * @returns Register index on success, -1 if not found.
1043 * @param pThis The HDA device state.
1044 * @param offReg The register offset.
1045 */
1046static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
1047{
1048 /*
1049 * Aliases.
1050 */
1051 if (offReg >= g_aHdaRegAliases[0].offReg)
1052 {
1053 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1054 if (offReg == g_aHdaRegAliases[i].offReg)
1055 return g_aHdaRegAliases[i].idxAlias;
1056 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1057 return -1;
1058 }
1059
1060 /*
1061 * Binary search the
1062 */
1063 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1064 int idxLow = 0;
1065 for (;;)
1066 {
1067 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1068 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1069 {
1070 if (idxLow == idxMiddle)
1071 break;
1072 idxEnd = idxMiddle;
1073 }
1074 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1075 {
1076 idxLow = idxMiddle + 1;
1077 if (idxLow >= idxEnd)
1078 break;
1079 }
1080 else
1081 return idxMiddle;
1082 }
1083
1084#ifdef RT_STRICT
1085 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1086 Assert(g_aHdaRegMap[i].offset != offReg);
1087#endif
1088 return -1;
1089}
1090
1091/**
1092 * Looks up a register covering the offset given by @a offReg.
1093 *
1094 * @returns Register index on success, -1 if not found.
1095 * @param pThis The HDA device state.
1096 * @param offReg The register offset.
1097 */
1098static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
1099{
1100 /*
1101 * Aliases.
1102 */
1103 if (offReg >= g_aHdaRegAliases[0].offReg)
1104 {
1105 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1106 {
1107 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1108 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1109 return g_aHdaRegAliases[i].idxAlias;
1110 }
1111 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1112 return -1;
1113 }
1114
1115 /*
1116 * Binary search the
1117 */
1118 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1119 int idxLow = 0;
1120 for (;;)
1121 {
1122 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1123 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1124 {
1125 if (idxLow == idxMiddle)
1126 break;
1127 idxEnd = idxMiddle;
1128 }
1129 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1130 {
1131 idxLow = idxMiddle + 1;
1132 if (idxLow >= idxEnd)
1133 break;
1134 }
1135 else
1136 return idxMiddle;
1137 }
1138
1139#ifdef RT_STRICT
1140 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1141 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1142#endif
1143 return -1;
1144}
1145
1146#ifdef IN_RING3
1147static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1148{
1149 int rc = VINF_SUCCESS;
1150 if (fLocal)
1151 {
1152 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1153 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1154 if (RT_FAILURE(rc))
1155 AssertRCReturn(rc, rc);
1156#ifdef DEBUG_CMD_BUFFER
1157 uint8_t i = 0;
1158 do
1159 {
1160 LogFunc(("corb%02x: ", i));
1161 uint8_t j = 0;
1162 do
1163 {
1164 const char *prefix;
1165 if ((i + j) == HDA_REG(pThis, CORBRP);
1166 prefix = "[R]";
1167 else if ((i + j) == HDA_REG(pThis, CORBWP);
1168 prefix = "[W]";
1169 else
1170 prefix = " "; /* three spaces */
1171 LogFunc(("%s%08x", prefix, pThis->pu32CorbBuf[i + j]));
1172 j++;
1173 } while (j < 8);
1174 LogFunc(("\n"));
1175 i += 8;
1176 } while(i != 0);
1177#endif
1178 }
1179 else
1180 {
1181 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1182 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1183 if (RT_FAILURE(rc))
1184 AssertRCReturn(rc, rc);
1185#ifdef DEBUG_CMD_BUFFER
1186 uint8_t i = 0;
1187 do {
1188 LogFunc(("rirb%02x: ", i));
1189 uint8_t j = 0;
1190 do {
1191 const char *prefix;
1192 if ((i + j) == HDA_REG(pThis, RIRBWP))
1193 prefix = "[W]";
1194 else
1195 prefix = " ";
1196 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1197 } while (++j < 8);
1198 LogFunc(("\n"));
1199 i += 8;
1200 } while (i != 0);
1201#endif
1202 }
1203 return rc;
1204}
1205
1206static int hdaCORBCmdProcess(PHDASTATE pThis)
1207{
1208 int rc;
1209 uint8_t corbRp;
1210 uint8_t corbWp;
1211 uint8_t rirbWp;
1212
1213 PFNHDACODECVERBPROCESSOR pfn = (PFNHDACODECVERBPROCESSOR)NULL;
1214
1215 rc = hdaCmdSync(pThis, true);
1216 if (RT_FAILURE(rc))
1217 AssertRCReturn(rc, rc);
1218 corbRp = HDA_REG(pThis, CORBRP);
1219 corbWp = HDA_REG(pThis, CORBWP);
1220 rirbWp = HDA_REG(pThis, RIRBWP);
1221 Assert((corbWp != corbRp));
1222 LogFlowFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1223 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1224 while (corbRp != corbWp)
1225 {
1226 uint32_t cmd;
1227 uint64_t resp;
1228 pfn = NULL;
1229 corbRp++;
1230 cmd = pThis->pu32CorbBuf[corbRp];
1231
1232 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
1233 HDA_CODEC_CMD(cmd, 0 /* Codec index */),
1234 &pfn);
1235 if (RT_SUCCESS(rc))
1236 {
1237 rc = pfn(pThis->pCodec,
1238 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1239 }
1240
1241 if (RT_FAILURE(rc))
1242 AssertRCReturn(rc, rc);
1243 Assert(pfn);
1244 (rirbWp)++;
1245
1246 LogFunc(("verb:%08x->%016lx\n", cmd, resp));
1247 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
1248 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1249 {
1250 LogFunc(("unexpected unsolicited response.\n"));
1251 HDA_REG(pThis, CORBRP) = corbRp;
1252 return rc;
1253 }
1254 pThis->pu64RirbBuf[rirbWp] = resp;
1255 pThis->u8Counter++;
1256 if (pThis->u8Counter == RINTCNT_N(pThis))
1257 break;
1258 }
1259 HDA_REG(pThis, CORBRP) = corbRp;
1260 HDA_REG(pThis, RIRBWP) = rirbWp;
1261 rc = hdaCmdSync(pThis, false);
1262 LogFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1263 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1264 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1265 {
1266 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1267 pThis->u8Counter = 0;
1268 rc = hdaProcessInterrupt(pThis);
1269 }
1270 if (RT_FAILURE(rc))
1271 AssertRCReturn(rc, rc);
1272 return rc;
1273}
1274#endif
1275
1276static void hdaStreamReset(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
1277{
1278 LogFunc(("reset of stream (%d) started\n", u8Strm));
1279 Assert(( pThis
1280 && pBdle
1281 && pStreamDesc
1282 && u8Strm <= 7));
1283 RT_BZERO(pBdle, sizeof(HDABDLEDESC));
1284 *pStreamDesc->pu32Lpib = 0;
1285 *pStreamDesc->pu32Sts = 0;
1286 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1287 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
1288 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1289
1290 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
1291 HDA_STREAM_REG(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
1292 HDA_STREAM_REG(pThis, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
1293 HDA_STREAM_REG(pThis, CBL, u8Strm) = 0;
1294 HDA_STREAM_REG(pThis, LVI, u8Strm) = 0;
1295 HDA_STREAM_REG(pThis, FMT, u8Strm) = 0;
1296 HDA_STREAM_REG(pThis, BDPU, u8Strm) = 0;
1297 HDA_STREAM_REG(pThis, BDPL, u8Strm) = 0;
1298 LogFunc(("reset of stream (%d) finished\n", u8Strm));
1299}
1300
1301/* Register access handlers. */
1302
1303static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1304{
1305 *pu32Value = 0;
1306 return VINF_SUCCESS;
1307}
1308
1309static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1310{
1311 return VINF_SUCCESS;
1312}
1313
1314/* U8 */
1315static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1316{
1317 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1318 return hdaRegReadU32(pThis, iReg, pu32Value);
1319}
1320
1321static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1322{
1323 Assert((u32Value & 0xffffff00) == 0);
1324 return hdaRegWriteU32(pThis, iReg, u32Value);
1325}
1326
1327/* U16 */
1328static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1329{
1330 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1331 return hdaRegReadU32(pThis, iReg, pu32Value);
1332}
1333
1334static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1335{
1336 Assert((u32Value & 0xffff0000) == 0);
1337 return hdaRegWriteU32(pThis, iReg, u32Value);
1338}
1339
1340/* U24 */
1341static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1342{
1343 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
1344 return hdaRegReadU32(pThis, iReg, pu32Value);
1345}
1346
1347static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1348{
1349 Assert((u32Value & 0xff000000) == 0);
1350 return hdaRegWriteU32(pThis, iReg, u32Value);
1351}
1352
1353/* U32 */
1354static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1355{
1356 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1357
1358 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
1359 return VINF_SUCCESS;
1360}
1361
1362static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1363{
1364 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1365
1366 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
1367 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
1368 return VINF_SUCCESS;
1369}
1370
1371static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1372{
1373 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1374 {
1375 /* exit reset state */
1376 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1377 pThis->fInReset = false;
1378 }
1379 else
1380 {
1381#ifdef IN_RING3
1382 /* enter reset state*/
1383 if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
1384 || HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
1385 {
1386 LogFunc(("HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1387 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
1388 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
1389 }
1390 hdaReset(pThis->CTX_SUFF(pDevIns));
1391 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1392 pThis->fInReset = true;
1393#else
1394 return VINF_IOM_R3_MMIO_WRITE;
1395#endif
1396 }
1397 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1398 {
1399 /* Flush: GSTS:1 set, see 6.2.6*/
1400 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
1401 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6)*/
1402 }
1403 return VINF_SUCCESS;
1404}
1405
1406static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1407{
1408 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1409
1410 uint32_t v = pThis->au32Regs[iRegMem];
1411 uint32_t nv = u32Value & HDA_STATES_SCSF;
1412 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
1413 return VINF_SUCCESS;
1414}
1415
1416static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1417{
1418 uint32_t v = 0;
1419 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1420 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1421 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
1422 || HDA_REG(pThis, STATESTS))
1423 v |= RT_BIT(30);
1424#define HDA_IS_STREAM_EVENT(pThis, stream) \
1425 ( (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1426 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1427 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1428#define MARK_STREAM(pThis, stream, v) do { (v) |= HDA_IS_STREAM_EVENT((pThis),stream) ? RT_BIT((stream)) : 0; } while(0)
1429 MARK_STREAM(pThis, 0, v);
1430 MARK_STREAM(pThis, 1, v);
1431 MARK_STREAM(pThis, 2, v);
1432 MARK_STREAM(pThis, 3, v);
1433 MARK_STREAM(pThis, 4, v);
1434 MARK_STREAM(pThis, 5, v);
1435 MARK_STREAM(pThis, 6, v);
1436 MARK_STREAM(pThis, 7, v);
1437 v |= v ? RT_BIT(31) : 0;
1438 *pu32Value = v;
1439 return VINF_SUCCESS;
1440}
1441
1442static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1443{
1444 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1445 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
1446 - pThis->u64BaseTS, 24, 1000);
1447 return VINF_SUCCESS;
1448}
1449
1450static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1451{
1452 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1453 HDA_REG(pThis, CORBRP) = 0;
1454#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
1455 else
1456 return hdaRegWriteU8(pThis, iReg, u32Value);
1457#endif
1458 return VINF_SUCCESS;
1459}
1460
1461static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1462{
1463#ifdef IN_RING3
1464 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1465 AssertRC(rc);
1466 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1467 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
1468 return hdaCORBCmdProcess(pThis);
1469 return rc;
1470#else
1471 return VINF_IOM_R3_MMIO_WRITE;
1472#endif
1473}
1474
1475static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1476{
1477 uint32_t v = HDA_REG(pThis, CORBSTS);
1478 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1479 return VINF_SUCCESS;
1480}
1481
1482static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1483{
1484#ifdef IN_RING3
1485 int rc;
1486 rc = hdaRegWriteU16(pThis, iReg, u32Value);
1487 if (RT_FAILURE(rc))
1488 AssertRCReturn(rc, rc);
1489 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
1490 return VINF_SUCCESS;
1491 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1492 return VINF_SUCCESS;
1493 rc = hdaCORBCmdProcess(pThis);
1494 return rc;
1495#else
1496 return VINF_IOM_R3_MMIO_WRITE;
1497#endif
1498}
1499
1500static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1501{
1502 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1503 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1504 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1505 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1506
1507 if (fInReset)
1508 {
1509 /*
1510 * Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1511 * from reset
1512 */
1513 Assert((!fReset));
1514 LogFunc(("guest initiated exit of stream reset.\n"));
1515 }
1516 else if (fReset)
1517 {
1518#ifdef IN_RING3
1519 /*
1520 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1521 */
1522 uint8_t u8Strm = 0;
1523 PHDABDLEDESC pBdle = NULL;
1524 HDASTREAMTRANSFERDESC StreamDesc;
1525 Assert((!fInRun && !fRun));
1526 switch (iReg)
1527 {
1528 case HDA_REG_SD0CTL:
1529 u8Strm = 0;
1530 pBdle = &pThis->StInBdle;
1531 break;
1532#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1533# ifdef VBOX_WITH_HDA_MIC_IN
1534 case HDA_REG_SD2CTL:
1535 u8Strm = 2;
1536 pBdle = &pThis->StMicBdle;
1537 break;
1538# endif
1539#endif
1540 case HDA_REG_SD4CTL:
1541 u8Strm = 4;
1542 pBdle = &pThis->StOutBdle;
1543 break;
1544 default:
1545 LogFunc(("changing SRST bit on non-attached stream\n"));
1546 return hdaRegWriteU24(pThis, iReg, u32Value);
1547 }
1548 LogFunc(("guest initiated enter to stream reset.\n"));
1549 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
1550 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
1551#else
1552 return VINF_IOM_R3_MMIO_WRITE;
1553#endif
1554 }
1555 else
1556 {
1557#ifdef IN_RING3
1558 /* we enter here to change DMA states only */
1559 if ( (fInRun && !fRun)
1560 || (fRun && !fInRun))
1561 {
1562 Assert((!fReset && !fInReset));
1563
1564# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1565 PHDADRIVER pDrv;
1566# endif
1567 switch (iReg)
1568 {
1569 case HDA_REG_SD0CTL:
1570# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1571 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1572 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1573 pDrv->LineIn.pStrmIn, fRun);
1574# else
1575 AUD_set_active_in(pThis->pCodec->SwVoiceIn, fRun);
1576# endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1577 break;
1578# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1579# ifdef VBOX_WITH_HDA_MIC_IN
1580 case HDA_REG_SD2CTL:
1581 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1582 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1583 pDrv->MicIn.pStrmIn, fRun);
1584# endif
1585# endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1586 break;
1587 case HDA_REG_SD4CTL:
1588# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1589 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1590 pDrv->pConnector->pfnEnableOut(pDrv->pConnector,
1591 pDrv->Out.pStrmOut, fRun);
1592# else
1593 AUD_set_active_out(pThis->pCodec->SwVoiceOut, fRun);
1594# endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1595 break;
1596 default:
1597 AssertMsgFailed(("Changing RUN bit on non-attached stream, register %RU32\n", iReg));
1598 break;
1599 }
1600 }
1601#else /* !IN_RING3 */
1602 return VINF_IOM_R3_MMIO_WRITE;
1603#endif /* IN_RING3 */
1604 }
1605
1606 return hdaRegWriteU24(pThis, iReg, u32Value);
1607}
1608
1609static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1610{
1611 uint32_t v = HDA_REG_IND(pThis, iReg);
1612 v &= ~(u32Value & v);
1613 HDA_REG_IND(pThis, iReg) = v;
1614 hdaProcessInterrupt(pThis);
1615 return VINF_SUCCESS;
1616}
1617
1618static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1619{
1620 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1621 if (RT_FAILURE(rc))
1622 AssertRCReturn(rc, VINF_SUCCESS);
1623 return rc;
1624}
1625
1626static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1627{
1628 switch (u32Value)
1629 {
1630 case HDA_SDFIFOW_8B:
1631 case HDA_SDFIFOW_16B:
1632 case HDA_SDFIFOW_32B:
1633 return hdaRegWriteU16(pThis, iReg, u32Value);
1634 default:
1635 LogFunc(("Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1636 return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);
1637 }
1638 return VINF_SUCCESS;
1639}
1640
1641/**
1642 * @note This method could be called for changing value on Output Streams
1643 * only (ICH6 datasheet 18.2.39)
1644 */
1645static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1646{
1647 switch (iReg)
1648 {
1649 /* SDInFIFOS is RO, n=0-3 */
1650 case HDA_REG_SD0FIFOS:
1651 case HDA_REG_SD1FIFOS:
1652 case HDA_REG_SD2FIFOS:
1653 case HDA_REG_SD3FIFOS:
1654 LogFunc(("Guest tries change value of FIFO size of input stream\n"));
1655 break;
1656 case HDA_REG_SD4FIFOS:
1657 case HDA_REG_SD5FIFOS:
1658 case HDA_REG_SD6FIFOS:
1659 case HDA_REG_SD7FIFOS:
1660 switch(u32Value)
1661 {
1662 case HDA_SDONFIFO_16B:
1663 case HDA_SDONFIFO_32B:
1664 case HDA_SDONFIFO_64B:
1665 case HDA_SDONFIFO_128B:
1666 case HDA_SDONFIFO_192B:
1667 return hdaRegWriteU16(pThis, iReg, u32Value);
1668
1669 case HDA_SDONFIFO_256B:
1670 LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
1671 default:
1672 return hdaRegWriteU16(pThis, iReg, HDA_SDONFIFO_192B);
1673 }
1674 break;
1675 default:
1676 AssertMsgFailed(("Something weird happened with register lookup routine\n"));
1677 }
1678
1679 return VINF_SUCCESS;
1680}
1681
1682#ifdef IN_RING3
1683#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1684static int hdaSdFmtToAudSettings(uint32_t u32SdFmt, PPDMAUDIOSTREAMCFG pCfg)
1685#else
1686static int hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pCfg)
1687#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1688{
1689 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1690
1691# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1692
1693 int rc = VINF_SUCCESS;
1694
1695 uint32_t u32Hz = (u32SdFmt & HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1696 uint32_t u32HzMult = 1;
1697 uint32_t u32HzDiv = 1;
1698
1699 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
1700 {
1701 case 0: u32HzMult = 1; break;
1702 case 1: u32HzMult = 2; break;
1703 case 2: u32HzMult = 3; break;
1704 case 3: u32HzMult = 4; break;
1705 default:
1706 LogFunc(("Unsupported multiplier %x\n",
1707 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
1708 rc = VERR_NOT_SUPPORTED;
1709 break;
1710 }
1711 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
1712 {
1713 case 0: u32HzDiv = 1; break;
1714 case 1: u32HzDiv = 2; break;
1715 case 2: u32HzDiv = 3; break;
1716 case 3: u32HzDiv = 4; break;
1717 case 4: u32HzDiv = 5; break;
1718 case 5: u32HzDiv = 6; break;
1719 case 6: u32HzDiv = 7; break;
1720 case 7: u32HzDiv = 8; break;
1721 default:
1722 LogFunc(("Unsupported divisor %x\n",
1723 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
1724 rc = VERR_NOT_SUPPORTED;
1725 break;
1726 }
1727
1728#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1729 PDMAUDIOFMT enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
1730#else
1731 audfmt_e enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
1732#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1733
1734 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
1735 {
1736 case 0:
1737 LogFunc(("%s requested 8-bit\n", __FUNCTION__));
1738#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1739 enmFmt = AUD_FMT_S8;
1740#else
1741 enmFmt = AUD_FMT_S8;
1742#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1743 break;
1744 case 1:
1745 LogFunc(("%s requested 16-bit\n", __FUNCTION__));
1746#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1747 enmFmt = AUD_FMT_S16;
1748#else
1749 enmFmt = AUD_FMT_S16;
1750#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1751 break;
1752 case 2:
1753 LogFunc(("%s requested 20-bit\n", __FUNCTION__));
1754 break;
1755 case 3:
1756 LogFunc(("%s requested 24-bit\n", __FUNCTION__));
1757 break;
1758 case 4:
1759 LogFunc(("%s requested 32-bit\n", __FUNCTION__));
1760#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1761 enmFmt = AUD_FMT_S32;
1762#else
1763 enmFmt = AUD_FMT_S32;
1764#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1765 break;
1766 default:
1767 AssertMsgFailed(("Unsupported bits shift %x\n",
1768 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
1769 rc = VERR_NOT_SUPPORTED;
1770 break;
1771 }
1772
1773 if (RT_SUCCESS(rc))
1774 {
1775#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1776 pCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
1777 pCfg->cChannels = (u32SdFmt & 0xf) + 1;
1778 pCfg->enmFormat = enmFmt;
1779 pCfg->enmEndianness = PDMAUDIOHOSTENDIANESS;
1780#else
1781 pCfg->nchannels = (u32SdFmt & 0xf) + 1;
1782 pCfg->fmt = enmFmt;
1783 pCfg->endianness = 0;
1784#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1785 }
1786
1787# undef EXTRACT_VALUE
1788
1789 return rc;
1790}
1791#endif
1792
1793static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1794{
1795#ifdef IN_RING3
1796# ifdef VBOX_WITH_HDA_CODEC_EMU
1797 /* No reason to reopen voice with same settings. */
1798 if (u32Value == HDA_REG_IND(pThis, iReg))
1799 return VINF_SUCCESS;
1800
1801 PDMAUDIOSTREAMCFG as;
1802 int rc = hdaSdFmtToAudSettings(u32Value, &as);
1803 if (RT_FAILURE(rc))
1804 return rc;
1805
1806 PHDADRIVER pDrv;
1807 switch (iReg)
1808 {
1809 case HDA_REG_SD0FMT:
1810 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1811 rc = hdaCodecOpenStream(pThis->pCodec, PI_INDEX, &as);
1812 break;
1813#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1814# ifdef VBOX_WITH_HDA_MIC_IN
1815 case HDA_REG_SD2FMT:
1816 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1817 rc = hdaCodecOpenStream(pThis->pCodec, MC_INDEX, &as);
1818 break;
1819# endif
1820#endif
1821 default:
1822 LogFunc(("Warning: Attempt to change format on register %d\n", iReg));
1823 break;
1824 }
1825
1826 /** @todo r=andy rc gets lost; needs fixing. */
1827 return hdaRegWriteU16(pThis, iReg, u32Value);
1828# else
1829 return hdaRegWriteU16(pThis, iReg, u32Value);
1830# endif
1831#else
1832 return VINF_IOM_R3_MMIO_WRITE;
1833#endif
1834}
1835
1836static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1837{
1838 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1839 if (RT_FAILURE(rc))
1840 AssertRCReturn(rc, VINF_SUCCESS);
1841 return rc;
1842}
1843
1844static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1845{
1846 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1847 if (RT_FAILURE(rc))
1848 AssertRCReturn(rc, VINF_SUCCESS);
1849 return rc;
1850}
1851
1852static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1853{
1854 int rc = VINF_SUCCESS;
1855 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1856 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1857 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1858 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1859
1860 rc = hdaRegReadU32(pThis, iReg, pu32Value);
1861 return rc;
1862}
1863
1864static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1865{
1866 int rc = VINF_SUCCESS;
1867
1868 /*
1869 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
1870 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
1871 */
1872 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1873 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
1874 {
1875#ifdef IN_RING3
1876 PFNHDACODECVERBPROCESSOR pfn = NULL;
1877 uint64_t resp;
1878 uint32_t cmd = HDA_REG(pThis, IC);
1879 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
1880 {
1881 /*
1882 * 3.4.3 defines behavior of immediate Command status register.
1883 */
1884 LogRel(("guest attempted process immediate verb (%x) with active CORB\n", cmd));
1885 return rc;
1886 }
1887 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1888 LogFunc(("IC:%x\n", cmd));
1889
1890 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
1891 HDA_CODEC_CMD(cmd, 0 /* LUN */),
1892 &pfn);
1893 if (RT_FAILURE(rc))
1894 AssertRCReturn(rc, rc);
1895 rc = pfn(pThis->pCodec,
1896 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1897 if (RT_FAILURE(rc))
1898 AssertRCReturn(rc, rc);
1899
1900 HDA_REG(pThis, IR) = (uint32_t)resp;
1901 LogFunc(("IR:%x\n", HDA_REG(pThis, IR)));
1902 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1903 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1904#else /* !IN_RING3 */
1905 rc = VINF_IOM_R3_MMIO_WRITE;
1906#endif
1907 return rc;
1908 }
1909 /*
1910 * Once the guest read the response, it should clean the IRV bit of the IRS register.
1911 */
1912 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1913 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
1914 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1915 return rc;
1916}
1917
1918static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1919{
1920 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1921 {
1922 HDA_REG(pThis, RIRBWP) = 0;
1923 }
1924 /* The remaining bits are O, see 6.2.22 */
1925 return VINF_SUCCESS;
1926}
1927
1928static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1929{
1930 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1931 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1932 if (RT_FAILURE(rc))
1933 AssertRCReturn(rc, rc);
1934
1935 switch(iReg)
1936 {
1937 case HDA_REG_CORBLBASE:
1938 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
1939 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
1940 break;
1941 case HDA_REG_CORBUBASE:
1942 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
1943 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1944 break;
1945 case HDA_REG_RIRBLBASE:
1946 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
1947 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
1948 break;
1949 case HDA_REG_RIRBUBASE:
1950 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
1951 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1952 break;
1953 case HDA_REG_DPLBASE:
1954 /** @todo: first bit has special meaning */
1955 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
1956 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
1957 break;
1958 case HDA_REG_DPUBASE:
1959 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
1960 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1961 break;
1962 default:
1963 AssertMsgFailed(("Invalid index"));
1964 break;
1965 }
1966
1967 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
1968 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
1969 return rc;
1970}
1971
1972static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1973{
1974 uint8_t v = HDA_REG(pThis, RIRBSTS);
1975 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
1976
1977 return hdaProcessInterrupt(pThis);
1978}
1979
1980#ifdef IN_RING3
1981#ifdef LOG_ENABLED
1982static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1983{
1984#if 0
1985 uint64_t addr;
1986 uint32_t len;
1987 uint32_t ioc;
1988 uint8_t bdle[16];
1989 uint32_t counter;
1990 uint32_t i;
1991 uint32_t sum = 0;
1992 Assert(pBdle && pBdle->u32BdleMaxCvi);
1993 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1994 {
1995 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i*16, bdle, 16);
1996 addr = *(uint64_t *)bdle;
1997 len = *(uint32_t *)&bdle[8];
1998 ioc = *(uint32_t *)&bdle[12];
1999 LogFunc(("%s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
2000 sum += len;
2001 }
2002 LogFunc(("sum: %d\n", sum));
2003 for (i = 0; i < 8; ++i)
2004 {
2005 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
2006 LogFunc(("%s stream[%d] counter=%x\n", i == SDCTL_NUM(pThis, 4) || i == SDCTL_NUM(pThis, 0)? "[C]": " ",
2007 i , counter));
2008 }
2009#endif
2010}
2011#endif
2012
2013static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2014{
2015 uint8_t bdle[16];
2016 Assert(( pStreamDesc->u64BaseDMA
2017 && pBdle
2018 && pBdle->u32BdleMaxCvi));
2019 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
2020 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
2021 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
2022 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
2023#ifdef LOG_ENABLED
2024 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
2025#endif
2026}
2027
2028DECLINLINE(uint32_t) hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2029 uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
2030{
2031 /*
2032 * Number of bytes depends on the current position in buffer (u32BdleCviLen-u32BdleCviPos)
2033 */
2034 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
2035 uint32_t cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
2036 /*
2037 * we may increase the counter in range of [0, FIFOS + 1]
2038 */
2039 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
2040 Assert((u32SoundBackendBufferBytesAvail > 0));
2041
2042 /* sanity check to avoid overriding the backend audio buffer */
2043 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
2044 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
2045
2046 if (cb2Copy <= pBdle->cbUnderFifoW)
2047 return 0;
2048 cb2Copy -= pBdle->cbUnderFifoW; /* forcibly reserve the amount of unreported bytes to copy */
2049 return cb2Copy;
2050}
2051
2052DECLINLINE(void) hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
2053 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
2054{
2055 LogFunc(("cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2056 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
2057 Assert((cbCopied));
2058 AssertPtr(pu32DMACursor);
2059 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
2060 /* Assertion!!! Fewer than cbUnderFifoW bytes were copied.
2061 * Probably we need to move the buffer, but it is rather hard to imagine a situation
2062 * where it might happen.
2063 */
2064 AssertMsg((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy), /* we assume that we write the entire buffer including unreported bytes */
2065 ("cbCopied=%RU32 != pBdle->cbUnderFifoW=%RU32 + cbArranged2Copy=%RU32\n",
2066 cbCopied, pBdle->cbUnderFifoW, cbArranged2Copy));
2067 if ( pBdle->cbUnderFifoW
2068 && pBdle->cbUnderFifoW <= cbCopied)
2069 {
2070 LogFunc(("CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n",
2071 pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2072 }
2073
2074 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
2075 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Incorrect assumption */
2076
2077 /* We always increment the position of DMA buffer counter because we're always reading into an intermediate buffer */
2078 pBdle->u32BdleCviPos += cbArranged2Copy;
2079
2080 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
2081 /* We report all bytes (including previously unreported bytes) */
2082 *pu32DMACursor += cbCopied;
2083 /* Decrease the backend counter by the number of bytes we copied to the backend */
2084 *pu32BackendBufferCapacity -= cbCopied;
2085 LogFunc(("CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2086 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
2087}
2088
2089DECLINLINE(void) hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
2090 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
2091{
2092 Assert((cbCopied, cbArranged2Copy));
2093 *pu32BackendBufferCapacity -= cbCopied;
2094 pBdle->u32BdleCviPos += cbCopied;
2095 LogFunc(("CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2096 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
2097 pBdle->cbUnderFifoW = 0;
2098 LogFunc(("CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2099 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
2100}
2101
2102DECLINLINE(void) hdaBackendTransferUnreported(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2103 uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
2104{
2105 LogFunc(("CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2106 pBdle->u32BdleCviPos += cbCopied;
2107 pBdle->cbUnderFifoW += cbCopied;
2108 /* In case of a read transaction we're always copying from the backend buffer */
2109 if (pu32BackendBufferCapacity)
2110 *pu32BackendBufferCapacity -= cbCopied;
2111 LogFunc(("CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2112 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pThis, pStreamDesc)));
2113}
2114
2115DECLINLINE(bool) hdaIsTransferCountersOverlapped(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2116{
2117 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
2118 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
2119
2120 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
2121
2122 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
2123 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
2124 hdaUpdatePosBuf(pThis, pStreamDesc);
2125
2126 /* don't touch BdleCvi counter on uninitialized descriptor */
2127 if ( pBdle->u32BdleCviPos
2128 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
2129 {
2130 pBdle->u32BdleCviPos = 0;
2131 pBdle->u32BdleCvi++;
2132 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
2133 pBdle->u32BdleCvi = 0;
2134 }
2135 return fOnBufferEdge;
2136}
2137
2138DECLINLINE(void) hdaStreamCounterUpdate(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2139 uint32_t cbInc)
2140{
2141 /*
2142 * if we're below the FIFO Watermark, it's expected that HDA doesn't fetch anything.
2143 * (ICH6 datasheet 18.2.38)
2144 */
2145 if (!pBdle->cbUnderFifoW)
2146 {
2147 *pStreamDesc->pu32Lpib += cbInc;
2148
2149 /*
2150 * Assert. The buffer counters should never overlap.
2151 */
2152 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
2153
2154 hdaUpdatePosBuf(pThis, pStreamDesc);
2155 }
2156}
2157
2158static bool hdaDoNextTransferCycle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2159{
2160 bool fDoNextTransferLoop = true;
2161 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
2162 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
2163 {
2164 if ( !pBdle->cbUnderFifoW
2165 && pBdle->fBdleCviIoc)
2166 {
2167 /**
2168 * @todo - more carefully investigate BCIS flag.
2169 * Speech synthesis works fine on Mac Guest if this bit isn't set
2170 * but in general sound quality gets worse.
2171 */
2172 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
2173
2174 /*
2175 * we should generate the interrupt if ICE bit of SDCTL register is set.
2176 */
2177 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
2178 hdaProcessInterrupt(pThis);
2179 }
2180 fDoNextTransferLoop = false;
2181 }
2182 return fDoNextTransferLoop;
2183}
2184
2185#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2186/**
2187 * hdaReadAudio - copies samples from audio backend to DMA.
2188 * Note: This function writes to the DMA buffer immediately,
2189 * but "reports bytes" when all conditions are met (FIFOW).
2190 */
2191static int hdaReadAudio(PHDASTATE pThis, PAUDMIXSINK pSink,
2192 PHDASTREAMTRANSFERDESC pStreamDesc,
2193 uint32_t u32CblLimit, uint32_t *pcbAvail, uint32_t *pcbRead)
2194{
2195 PHDABDLEDESC pBdle = &pThis->StInBdle; /** @todo Add support for mic in. */
2196
2197 int rc;
2198 uint32_t cbTransferred = 0;
2199
2200 LogFlowFunc(("CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2201
2202 uint32_t cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pcbAvail, u32CblLimit);
2203 if (!cb2Copy)
2204 {
2205 /* If we enter here we can't report "unreported bits". */
2206 rc = VERR_NO_DATA;
2207 }
2208 else
2209 {
2210 uint32_t cbRead = 0;
2211 rc = audioMixerProcessSinkIn(pSink, pBdle->au8HdaBuffer, cb2Copy, &cbRead);
2212 if (RT_SUCCESS(rc))
2213 {
2214 Assert(cbRead);
2215
2216 /*
2217 * Write the HDA DMA buffer.
2218 */
2219 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2220 pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos,
2221 pBdle->au8HdaBuffer, cbRead);
2222
2223 /* Don't see any reason why cb2Copy would differ from cbRead. */
2224 Assert((cbRead == cb2Copy && (*pcbAvail) >= cb2Copy)); /* sanity */
2225
2226 if (pBdle->cbUnderFifoW + cbRead > hdaFifoWToSz(pThis, 0))
2227 hdaBackendReadTransferReported(pBdle, cb2Copy, cbRead, &cbTransferred, pcbAvail);
2228 else
2229 {
2230 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cbRead, pcbAvail);
2231 rc = VERR_NO_DATA;
2232 }
2233 }
2234 }
2235
2236 Assert((cbTransferred <= (SDFIFOS(pThis, 0) + 1)));
2237 LogFunc(("CVI(pos:%RU32, len:%RU32), cbTransferred=%RU32, rc=%Rrc\n",
2238 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred, rc));
2239
2240 if (RT_SUCCESS(rc))
2241 *pcbRead = cbTransferred;
2242
2243 return rc;
2244}
2245#else
2246static int hdaReadAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc,
2247 uint32_t u32CblLimit, uint32_t *pu32Avail, uint32_t *pcbRead)
2248{
2249 PHDABDLEDESC pBdle = &pThis->StInBdle;
2250
2251 uint32_t cbTransferred = 0;
2252 uint32_t cb2Copy = 0;
2253 uint32_t cbBackendCopy = 0;
2254
2255 int rc;
2256
2257 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2258
2259 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
2260 if (!cb2Copy)
2261 {
2262 /* if we enter here we can't report "unreported bits" */
2263 rc = VINF_EOF;
2264 }
2265 else
2266 {
2267 /*
2268 * read from backend input line to the last unreported position or at the begining.
2269 */
2270 cbBackendCopy = AUD_read(pThis->pCodec->SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
2271
2272 /*
2273 * write the HDA DMA buffer
2274 */
2275 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer,
2276 cbBackendCopy);
2277
2278 /* Don't see any reason why cb2Copy would differ from cbBackendCopy */
2279 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
2280
2281 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pThis, 0))
2282 {
2283 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
2284 rc = VINF_SUCCESS;
2285 }
2286 else
2287 {
2288 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
2289 rc = VINF_EOF;
2290 }
2291 }
2292
2293 Assert((cbTransferred <= (SDFIFOS(pThis, 0) + 1)));
2294 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransferred: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
2295
2296 if (pcbRead)
2297 *pcbRead = cbTransferred;
2298
2299 return rc;
2300}
2301#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2302
2303static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t u32CblLimit,
2304 uint32_t *pcbAvail, uint32_t *pcbWritten)
2305{
2306 PHDABDLEDESC pBdle = &pThis->StOutBdle;
2307
2308 int rc = VINF_SUCCESS;
2309
2310 uint32_t cbTransferred = 0;
2311 uint32_t cbWrittenMin = 0; /* local byte counter, how many bytes copied to backend */
2312
2313 LogFunc(("CVI(cvi:%RU32, pos:%RU32, len:%RU32)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2314
2315 /* Local byte counter (on local buffer). */
2316 uint32_t cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pcbAvail, u32CblLimit);
2317
2318 /*
2319 * Copy from DMA to the corresponding hdaBuffer (if there are any bytes from the
2320 * previous unreported transfer we write at offset 'pBdle->cbUnderFifoW').
2321 */
2322 if (!cb2Copy)
2323 {
2324 rc = VINF_EOF;
2325 }
2326 else
2327 {
2328 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2329 pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos,
2330 pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
2331#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2332 STAM_COUNTER_ADD(&pThis->StatBytesRead, cb2Copy);
2333#endif
2334
2335 /*
2336 * Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
2337 */
2338 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pThis, pStreamDesc))
2339 {
2340#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2341 uint32_t cbWritten;
2342 cbWrittenMin = UINT32_MAX;
2343
2344 PHDADRIVER pDrv;
2345 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2346 {
2347 if (pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut))
2348 {
2349 int rc2 = pDrv->pConnector->pfnWrite(pDrv->pConnector, pDrv->Out.pStrmOut,
2350 pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW,
2351 &cbWritten);
2352 if (RT_FAILURE(rc2))
2353 continue;
2354 }
2355 else /* Stream disabled, just assume all was copied. */
2356 cbWritten = cb2Copy;
2357
2358 cbWrittenMin = RT_MIN(cbWrittenMin, cbWritten);
2359 LogFlowFunc(("\tLUN#%RU8: cbWritten=%RU32, cWrittenMin=%RU32\n", pDrv->uLUN, cbWritten, cbWrittenMin));
2360 }
2361
2362 if (cbWrittenMin == UINT32_MAX)
2363 cbWrittenMin = 0;
2364#else
2365 cbWrittenMin = AUD_write (pThis->pCodec->SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
2366#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2367
2368 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbWrittenMin, &cbTransferred, pcbAvail);
2369 }
2370 else
2371 {
2372 /* Not enough bytes to be processed and reported, we'll try our luck next time around. */
2373 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cb2Copy, NULL);
2374 rc = VINF_EOF;
2375 }
2376 }
2377
2378 Assert(cbTransferred <= SDFIFOS(pThis, 4) + 1);
2379 LogFunc(("CVI(pos:%RU32, len:%RU32, cbTransferred:%RU32), rc=%Rrc\n",
2380 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred, rc));
2381
2382 if (RT_SUCCESS(rc))
2383 *pcbWritten = cbTransferred;
2384
2385 return rc;
2386}
2387
2388/**
2389 * @interface_method_impl{HDACODEC,pfnReset}
2390 */
2391DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
2392{
2393 PHDASTATE pThis = pCodec->pHDAState;
2394 NOREF(pThis);
2395 return VINF_SUCCESS;
2396}
2397
2398DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
2399 PHDASTREAMTRANSFERDESC pStreamDesc)
2400{
2401 Assert(pThis); Assert(pBdle); Assert(pStreamDesc); Assert(u8Strm <= 7);
2402
2403 RT_BZERO(pStreamDesc, sizeof(HDASTREAMTRANSFERDESC));
2404 pStreamDesc->u8Strm = u8Strm;
2405 pStreamDesc->u32Ctl = HDA_STREAM_REG(pThis, CTL, u8Strm);
2406 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
2407 HDA_STREAM_REG(pThis, BDPU, u8Strm));
2408 pStreamDesc->pu32Lpib = &HDA_STREAM_REG(pThis, LPIB, u8Strm);
2409 pStreamDesc->pu32Sts = &HDA_STREAM_REG(pThis, STS, u8Strm);
2410 pStreamDesc->u32Cbl = HDA_STREAM_REG(pThis, CBL, u8Strm);
2411 pStreamDesc->u32Fifos = HDA_STREAM_REG(pThis, FIFOS, u8Strm);
2412
2413 pBdle->u32BdleMaxCvi = HDA_STREAM_REG(pThis, LVI, u8Strm);
2414
2415#ifdef LOG_ENABLED
2416 if ( pBdle
2417 && pBdle->u32BdleMaxCvi)
2418 {
2419 LogFunc(("Initialization of transfer descriptor:\n"));
2420 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
2421 }
2422#endif
2423}
2424
2425static DECLCALLBACK(void) hdaCloseIn(PHDASTATE pThis, PDMAUDIORECSOURCE enmRecSource)
2426{
2427 NOREF(pThis);
2428 NOREF(enmRecSource);
2429 LogFlowFuncEnter();
2430}
2431
2432static DECLCALLBACK(void) hdaCloseOut(PHDASTATE pThis)
2433{
2434 NOREF(pThis);
2435 LogFlowFuncEnter();
2436}
2437
2438#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2439static DECLCALLBACK(int) hdaOpenIn(PHDASTATE pThis,
2440 const char *pszName, PDMAUDIORECSOURCE enmRecSource,
2441 PPDMAUDIOSTREAMCFG pCfg)
2442{
2443 PAUDMIXSINK pSink;
2444
2445 switch (enmRecSource)
2446 {
2447# ifdef VBOX_WITH_HDA_MIC_IN
2448 case PDMAUDIORECSOURCE_MIC:
2449 pSink = pThis->pSinkMicIn;
2450 break;
2451# endif
2452 case PDMAUDIORECSOURCE_LINE_IN:
2453 pSink = pThis->pSinkLineIn;
2454 break;
2455 default:
2456 AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
2457 return VERR_NOT_SUPPORTED;
2458 }
2459
2460 int rc;
2461 char *pszDesc;
2462
2463 PHDADRIVER pDrv;
2464 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2465 {
2466 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2467 {
2468 rc = VERR_NO_MEMORY;
2469 break;
2470 }
2471
2472 rc = pDrv->pConnector->pfnOpenIn(pDrv->pConnector, pszDesc, enmRecSource, pCfg, &pDrv->LineIn.pStrmIn);
2473 LogFlowFunc(("LUN#%RU8: Opened input \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2474 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2475 {
2476 audioMixerRemoveStream(pSink, pDrv->LineIn.phStrmIn);
2477 rc = audioMixerAddStreamIn(pSink,
2478 pDrv->pConnector, pDrv->LineIn.pStrmIn,
2479 0 /* uFlags */, &pDrv->LineIn.phStrmIn);
2480 }
2481
2482 RTStrFree(pszDesc);
2483 }
2484
2485 LogFlowFuncLeaveRC(rc);
2486 return rc;
2487}
2488
2489static DECLCALLBACK(int) hdaOpenOut(PHDASTATE pThis,
2490 const char *pszName, PPDMAUDIOSTREAMCFG pCfg)
2491{
2492 int rc = VINF_SUCCESS;
2493
2494 PHDADRIVER pDrv;
2495 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2496 {
2497 int rc2 = pDrv->pConnector->pfnOpenOut(pDrv->pConnector, pszName, pCfg, &pDrv->Out.pStrmOut);
2498 if (RT_FAILURE(rc2))
2499 {
2500 LogFunc(("LUN#%RU8: Opening stream \"%s\" failed, rc=%Rrc\n", pDrv->uLUN, pszName, rc2));
2501 if (RT_SUCCESS(rc))
2502 rc = rc2;
2503 /* Keep going. */
2504 }
2505 }
2506
2507 LogFlowFuncLeaveRC(rc);
2508 return rc;
2509}
2510
2511static DECLCALLBACK(int) hdaSetVolume(PHDASTATE pThis,
2512 bool fMute, uint8_t uVolLeft, uint8_t uVolRight)
2513{
2514 int rc = VINF_SUCCESS;
2515
2516 PHDADRIVER pDrv;
2517 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2518 {
2519 int rc2 = pDrv->pConnector->pfnSetVolume(pDrv->pConnector,
2520 fMute, uVolLeft, uVolRight);
2521 if (RT_FAILURE(rc2))
2522 {
2523 LogFunc(("Failed for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
2524 if (RT_SUCCESS(rc))
2525 rc = rc2;
2526 /* Keep going. */
2527 }
2528 }
2529
2530 LogFlowFuncLeaveRC(rc);
2531 return rc;
2532}
2533#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2534
2535#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2536static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2537{
2538 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2539 AssertPtr(pThis);
2540
2541 STAM_PROFILE_START(&pThis->StatTimer, a);
2542
2543 int rc = VINF_SUCCESS;
2544
2545 uint32_t cbInMax = 0;
2546 uint32_t cbOutMin = UINT32_MAX;
2547
2548 PHDADRIVER pDrv;
2549
2550 LogFlowFuncEnter();
2551
2552 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2553 {
2554 uint32_t cbIn, cbOut;
2555 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2556 &cbIn, &cbOut, &pDrv->cSamplesLive);
2557 if (RT_SUCCESS(rc))
2558 {
2559 LogFlowFunc(("\tLUN#%RU8: [1] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2560
2561 if (pDrv->cSamplesLive)
2562 {
2563 uint32_t cSamplesPlayed;
2564 int rc2 = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, &cSamplesPlayed);
2565 if (RT_SUCCESS(rc2))
2566 {
2567 LogFlowFunc(("LUN#%RU8: cSamplesLive=%RU32, cSamplesPlayed=%RU32\n",
2568 pDrv->uLUN, pDrv->cSamplesLive, cSamplesPlayed));
2569 Assert(pDrv->cSamplesLive >= cSamplesPlayed);
2570 pDrv->cSamplesLive -= cSamplesPlayed;
2571 }
2572
2573 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2574 &cbIn, &cbOut, &pDrv->cSamplesLive);
2575 if (RT_SUCCESS(rc))
2576 LogFlowFunc(("\tLUN#%RU8: [2] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2577 }
2578
2579 cbInMax = RT_MAX(cbInMax, cbIn);
2580 cbOutMin = RT_MIN(cbOutMin, cbOut);
2581 }
2582 else
2583 pDrv->cSamplesLive = 0;
2584 }
2585
2586 LogFlowFunc(("cbInMax=%RU32, cbOutMin=%RU32\n", cbInMax, cbOutMin));
2587
2588 if (cbOutMin == UINT32_MAX)
2589 cbOutMin = 0;
2590
2591 /*
2592 * Playback.
2593 */
2594 if (cbOutMin)
2595 {
2596 Assert(cbOutMin != UINT32_MAX);
2597 hdaTransfer(pThis, PO_INDEX, cbOutMin); /** @todo Add rc! */
2598 }
2599
2600 /*
2601 * Recording.
2602 */
2603 if (cbInMax)
2604 hdaTransfer(pThis, PI_INDEX, cbInMax); /** @todo Add rc! */
2605
2606 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
2607
2608 LogFlowFuncLeave();
2609
2610 STAM_PROFILE_STOP(&pThis->StatTimer, a);
2611}
2612
2613static DECLCALLBACK(int) hdaTransfer(PHDASTATE pThis,
2614 ENMSOUNDSOURCE enmSrc, uint32_t cbAvail)
2615{
2616 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2617
2618 LogFlowFunc(("pThis=%p, cbAvail=%RU32\n", pThis, cbAvail));
2619#else
2620static DECLCALLBACK(int) hdaTransfer(PHDACODEC pCodec, ENMSOUNDSOURCE enmSrc, uint32_t cbAvail)
2621{
2622 AssertPtrReturn(pCodec, VERR_INVALID_POINTER);
2623 PHDASTATE pThis = pCodec->pHDAState;
2624 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2625#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2626 int rc;
2627
2628 uint8_t u8Strm;
2629 PHDABDLEDESC pBdle;
2630
2631 switch (enmSrc)
2632 {
2633 case PI_INDEX:
2634 {
2635 u8Strm = 0;
2636 pBdle = &pThis->StInBdle;
2637 break;
2638 }
2639
2640#ifdef VBOX_WITH_HDA_MIC_IN
2641 case MC_INDEX:
2642 {
2643 u8Strm = 2;
2644 pBdle = &pThis->StMicBdle;
2645 break;
2646 }
2647#endif
2648 case PO_INDEX:
2649 {
2650 u8Strm = 4;
2651 pBdle = &pThis->StOutBdle;
2652 break;
2653 }
2654
2655 default:
2656 AssertMsgFailed(("Unknown source index %ld\n", enmSrc));
2657 return VERR_NOT_SUPPORTED;
2658 }
2659
2660 HDASTREAMTRANSFERDESC StreamDesc;
2661 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
2662
2663 while (cbAvail)
2664 {
2665 Assert( (StreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
2666 && cbAvail
2667 && StreamDesc.u64BaseDMA);
2668
2669 /* Fetch the Buffer Descriptor Entry (BDE). */
2670 if (hdaIsTransferCountersOverlapped(pThis, pBdle, &StreamDesc))
2671 hdaFetchBdle(pThis, pBdle, &StreamDesc);
2672
2673 *StreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2674 Assert((StreamDesc.u32Cbl >= (*StreamDesc.pu32Lpib))); /* sanity */
2675 uint32_t u32CblLimit = StreamDesc.u32Cbl - (*StreamDesc.pu32Lpib);
2676 Assert((u32CblLimit > hdaFifoWToSz(pThis, &StreamDesc)));
2677
2678 LogFunc(("CBL=%RU32, LPIB=%RU32\n", StreamDesc.u32Cbl, *StreamDesc.pu32Lpib));
2679
2680#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2681 PAUDMIXSINK pSink;
2682#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2683 uint32_t cbWritten;
2684 switch (enmSrc)
2685 {
2686 case PI_INDEX:
2687#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2688 pSink = pThis->pSinkLineIn;
2689 rc = hdaReadAudio(pThis, pSink, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2690#else
2691 rc = hdaReadAudio(pThis, &StreamDesc, u32CblLimit, (uint32_t *)&cbAvail, &cbWritten);
2692#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2693 break;
2694 case PO_INDEX:
2695 rc = hdaWriteAudio(pThis, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2696 break;
2697#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2698# ifdef VBOX_WITH_HDA_MIC_IN
2699 case MC_INDEX:
2700 pSink = pThis->pSinkMicIn;
2701 rc = hdaReadAudio(pThis, pSink, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2702 break;
2703# endif
2704#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2705 default:
2706 AssertMsgFailed(("Unsupported source index %ld\n", enmSrc));
2707 rc = VERR_NOT_SUPPORTED;
2708 break;
2709 }
2710 Assert(cbWritten <= StreamDesc.u32Fifos + 1);
2711 *StreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2712
2713 /* Process end of buffer condition. */
2714 hdaStreamCounterUpdate(pThis, pBdle, &StreamDesc, cbWritten);
2715
2716 if (!hdaDoNextTransferCycle(pThis, pBdle, &StreamDesc))
2717 break;
2718
2719 if ( RT_FAILURE(rc)
2720 || rc == VINF_EOF) /* All data processed? */
2721 {
2722 break;
2723 }
2724 }
2725
2726 return rc;
2727}
2728#endif /* IN_RING3 */
2729
2730/* MMIO callbacks */
2731
2732/**
2733 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
2734 *
2735 * @note During implementation, we discovered so-called "forgotten" or "hole"
2736 * registers whose description is not listed in the RPM, datasheet, or
2737 * spec.
2738 */
2739PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2740{
2741 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2742 int rc;
2743
2744 /*
2745 * Look up and log.
2746 */
2747 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2748 int idxRegDsc = hdaRegLookup(pThis, offReg); /* Register descriptor index. */
2749#ifdef LOG_ENABLED
2750 unsigned const cbLog = cb;
2751 uint32_t offRegLog = offReg;
2752#endif
2753
2754 LogFunc(("offReg=%#x cb=%#x\n", offReg, cb));
2755#define NEW_READ_CODE
2756#ifdef NEW_READ_CODE
2757 Assert(cb == 4); Assert((offReg & 3) == 0);
2758
2759 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
2760 LogFunc(("access to registers except GCTL is blocked while reset\n"));
2761
2762 if (idxRegDsc == -1)
2763 LogRel(("Invalid read access @0x%x(of bytes:%d)\n", offReg, cb));
2764
2765 if (idxRegDsc != -1)
2766 {
2767 /* ASSUMES gapless DWORD at end of map. */
2768 if (g_aHdaRegMap[idxRegDsc].size == 4)
2769 {
2770 /*
2771 * Straight forward DWORD access.
2772 */
2773 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
2774 LogFunc(("read %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
2775 }
2776 else
2777 {
2778 /*
2779 * Multi register read (unless there are trailing gaps).
2780 * ASSUMES that only DWORD reads have sideeffects.
2781 */
2782 uint32_t u32Value = 0;
2783 unsigned cbLeft = 4;
2784 do
2785 {
2786 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
2787 uint32_t u32Tmp = 0;
2788
2789 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
2790 LogFunc(("read %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
2791 if (rc != VINF_SUCCESS)
2792 break;
2793 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
2794
2795 cbLeft -= cbReg;
2796 offReg += cbReg;
2797 idxRegDsc++;
2798 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
2799
2800 if (rc == VINF_SUCCESS)
2801 *(uint32_t *)pv = u32Value;
2802 else
2803 Assert(!IOM_SUCCESS(rc));
2804 }
2805 }
2806 else
2807 {
2808 rc = VINF_IOM_MMIO_UNUSED_FF;
2809 LogFunc(("hole at %x is accessed for read\n", offReg));
2810 }
2811#else
2812 if (idxRegDsc != -1)
2813 {
2814 /** @todo r=bird: Accesses crossing register boundraries aren't handled
2815 * right from what I can tell? If they are, please explain
2816 * what the rules are. */
2817 uint32_t mask = 0;
2818 uint32_t shift = (g_aHdaRegMap[idxRegDsc].offset - offReg) % sizeof(uint32_t) * 8;
2819 uint32_t u32Value = 0;
2820 switch(cb)
2821 {
2822 case 1: mask = 0x000000ff; break;
2823 case 2: mask = 0x0000ffff; break;
2824 case 4:
2825 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2826 case 8:
2827 mask = 0xffffffff;
2828 cb = 4;
2829 break;
2830 }
2831#if 0
2832 /* Cross-register access. Mac guest hits this assert doing assumption 4 byte access to 3 byte registers e.g. {I,O}SDnCTL
2833 */
2834 //Assert((cb <= g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset)));
2835 if (cb > g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset))
2836 {
2837 int off = cb - (g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset));
2838 rc = hdaMMIORead(pDevIns, pvUser, GCPhysAddr + cb - off, (char *)pv + cb - off, off);
2839 if (RT_FAILURE(rc))
2840 AssertRCReturn (rc, rc);
2841 }
2842 //Assert(((offReg - g_aHdaRegMap[idxRegDsc].offset) == 0));
2843#endif
2844 mask <<= shift;
2845 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Value);
2846 *(uint32_t *)pv |= (u32Value & mask);
2847 LogFunc(("read %s[%x/%x]\n", g_aHdaRegMap[idxRegDsc].abbrev, u32Value, *(uint32_t *)pv));
2848 }
2849 else
2850 {
2851 *(uint32_t *)pv = 0xFF;
2852 LogFunc(("hole at %x is accessed for read\n", offReg));
2853 rc = VINF_SUCCESS;
2854 }
2855#endif
2856
2857 /*
2858 * Log the outcome.
2859 */
2860#ifdef LOG_ENABLED
2861 if (cbLog == 4)
2862 LogFunc(("@%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
2863 else if (cbLog == 2)
2864 LogFunc(("@%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
2865 else if (cbLog == 1)
2866 LogFunc(("@%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
2867#endif
2868 return rc;
2869}
2870
2871
2872DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
2873{
2874 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
2875 LogFunc(("access to registers except GCTL is blocked while reset\n")); /** @todo where is this enforced? */
2876
2877 uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2878#ifdef LOG_ENABLED
2879 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
2880#endif
2881 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
2882 LogFunc(("write %#x -> %s[%db]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
2883 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
2884 return rc;
2885}
2886
2887
2888/**
2889 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
2890 */
2891PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
2892{
2893 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2894 int rc;
2895
2896 /*
2897 * The behavior of accesses that aren't aligned on natural boundraries is
2898 * undefined. Just reject them outright.
2899 */
2900 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
2901 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
2902 if (GCPhysAddr & (cb - 1))
2903 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
2904
2905 /*
2906 * Look up and log the access.
2907 */
2908 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2909 int idxRegDsc = hdaRegLookup(pThis, offReg);
2910 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
2911 uint64_t u64Value;
2912 if (cb == 4) u64Value = *(uint32_t const *)pv;
2913 else if (cb == 2) u64Value = *(uint16_t const *)pv;
2914 else if (cb == 1) u64Value = *(uint8_t const *)pv;
2915 else if (cb == 8) u64Value = *(uint64_t const *)pv;
2916 else
2917 {
2918 u64Value = 0; /* shut up gcc. */
2919 AssertReleaseMsgFailed(("%d\n", cb));
2920 }
2921
2922#ifdef LOG_ENABLED
2923 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
2924 uint32_t const offRegLog = offReg;
2925 int const idxRegLog = idxRegMem;
2926 if (idxRegDsc == -1)
2927 LogFunc(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
2928 else if (cb == 4)
2929 LogFunc(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2930 else if (cb == 2)
2931 LogFunc(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2932 else if (cb == 1)
2933 LogFunc(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2934 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
2935 LogFunc(("size=%d != cb=%d!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
2936#endif
2937
2938#define NEW_WRITE_CODE
2939#ifdef NEW_WRITE_CODE
2940 /*
2941 * Try for a direct hit first.
2942 */
2943 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
2944 {
2945 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
2946 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldValue,
2947 idxRegLog != -1 ? pThis->au32Regs[idxRegLog] : UINT32_MAX));
2948 }
2949 /*
2950 * Partial or multiple register access, loop thru the requested memory.
2951 */
2952 else
2953 {
2954 /* If it's an access beyond the start of the register, shift the input
2955 value and fill in missing bits. Natural alignment rules means we
2956 will only see 1 or 2 byte accesses of this kind, so no risk of
2957 shifting out input values. */
2958 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(pThis, offReg)) != -1)
2959 {
2960 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
2961 offReg -= cbBefore;
2962 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2963 u64Value <<= cbBefore * 8;
2964 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
2965 LogFunc(("Within register, supplied %u leading bits: %#llx -> %#llx ...\n",
2966 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
2967 }
2968
2969 /* Loop thru the write area, it may cover multiple registers. */
2970 rc = VINF_SUCCESS;
2971 for (;;)
2972 {
2973 uint32_t cbReg;
2974 if (idxRegDsc != -1)
2975 {
2976 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2977 cbReg = g_aHdaRegMap[idxRegDsc].size;
2978 if (cb < cbReg)
2979 {
2980 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
2981 LogFunc(("Supplying missing bits (%#x): %#llx -> %#llx ...\n",
2982 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
2983 }
2984 uint32_t u32LogOldVal = pThis->au32Regs[idxRegMem];
2985 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
2986 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldVal,
2987 pThis->au32Regs[idxRegMem]));
2988 }
2989 else
2990 {
2991 LogRel(("HDA: Invalid write access @0x%x!\n", offReg));
2992 cbReg = 1;
2993 }
2994 if (rc != VINF_SUCCESS)
2995 break;
2996 if (cbReg >= cb)
2997 break;
2998
2999 /* advance */
3000 offReg += cbReg;
3001 cb -= cbReg;
3002 u64Value >>= cbReg * 8;
3003 if (idxRegDsc == -1)
3004 idxRegDsc = hdaRegLookup(pThis, offReg);
3005 else
3006 {
3007 idxRegDsc++;
3008 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
3009 || g_aHdaRegMap[idxRegDsc].offset != offReg)
3010 idxRegDsc = -1;
3011 }
3012 }
3013 }
3014#else
3015 if (idxRegDsc != -1)
3016 {
3017 /** @todo r=bird: This looks like code for handling unaligned register
3018 * accesses. If it isn't, then add a comment explaining what you're
3019 * trying to do here. OTOH, if it is then it has the following
3020 * issues:
3021 * -# You're calculating the wrong new value for the register.
3022 * -# You're not handling cross register accesses. Imagine a
3023 * 4-byte write starting at CORBCTL, or a 8-byte write.
3024 *
3025 * PS! consider dropping the 'offset' argument to pfnWrite/pfnRead as
3026 * nobody seems to be using it and it just adds complexity when reading
3027 * the code.
3028 *
3029 */
3030 uint32_t u32CurValue = pThis->au32Regs[idxRegMem];
3031 uint32_t u32NewValue;
3032 uint32_t mask;
3033 switch (cb)
3034 {
3035 case 1:
3036 u32NewValue = *(uint8_t const *)pv;
3037 mask = 0xff;
3038 break;
3039 case 2:
3040 u32NewValue = *(uint16_t const *)pv;
3041 mask = 0xffff;
3042 break;
3043 case 4:
3044 case 8:
3045 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
3046 u32NewValue = *(uint32_t const *)pv;
3047 mask = 0xffffffff;
3048 cb = 4;
3049 break;
3050 default:
3051 AssertFailedReturn(VERR_INTERNAL_ERROR_4); /* shall not happen. */
3052 }
3053 /* cross-register access, see corresponding comment in hdaMMIORead */
3054 uint32_t shift = (g_aHdaRegMap[idxRegDsc].offset - offReg) % sizeof(uint32_t) * 8;
3055 mask <<= shift;
3056 u32NewValue <<= shift;
3057 u32NewValue &= mask;
3058 u32NewValue |= (u32CurValue & ~mask);
3059
3060 rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32NewValue);
3061 LogFunc(("write %s:(%x) %x => %x\n", g_aHdaRegMap[idxRegDsc].abbrev, u32NewValue,
3062 u32CurValue, pThis->au32Regs[idxRegMem]));
3063 }
3064 else
3065 rc = VINF_SUCCESS;
3066
3067 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldValue,
3068 idxRegLog != -1 ? pThis->au32Regs[idxRegLog] : UINT32_MAX));
3069#endif
3070 return rc;
3071}
3072
3073
3074/* PCI callback. */
3075
3076#ifdef IN_RING3
3077/**
3078 * @callback_method_impl{FNPCIIOREGIONMAP}
3079 */
3080static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
3081 PCIADDRESSSPACE enmType)
3082{
3083 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3084 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
3085 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
3086 int rc;
3087
3088 /*
3089 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
3090 *
3091 * Let IOM talk DWORDs when reading, saves a lot of complications. On
3092 * writing though, we have to do it all ourselves because of sideeffects.
3093 */
3094 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
3095 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
3096#ifdef NEW_READ_CODE
3097 IOMMMIO_FLAGS_READ_DWORD |
3098#else
3099 IOMMMIO_FLAGS_READ_PASSTHRU |
3100#endif
3101 IOMMMIO_FLAGS_WRITE_PASSTHRU,
3102 hdaMMIOWrite, hdaMMIORead, "HDA");
3103
3104 if (RT_FAILURE(rc))
3105 return rc;
3106
3107 if (pThis->fR0Enabled)
3108 {
3109 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
3110 "hdaMMIOWrite", "hdaMMIORead");
3111 if (RT_FAILURE(rc))
3112 return rc;
3113 }
3114
3115 if (pThis->fRCEnabled)
3116 {
3117 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
3118 "hdaMMIOWrite", "hdaMMIORead");
3119 if (RT_FAILURE(rc))
3120 return rc;
3121 }
3122
3123 pThis->MMIOBaseAddr = GCPhysAddress;
3124 return VINF_SUCCESS;
3125}
3126
3127
3128/* Saved state callbacks. */
3129
3130/**
3131 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3132 */
3133static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3134{
3135 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3136
3137 /* Save Codec nodes states */
3138 hdaCodecSaveState(pThis->pCodec, pSSM);
3139
3140 /* Save MMIO registers */
3141 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3142 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3143 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3144
3145 /* Save HDA dma counters */
3146 SSMR3PutStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3147 SSMR3PutStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3148 SSMR3PutStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3149 return VINF_SUCCESS;
3150}
3151
3152
3153/**
3154 * @callback_method_impl{FNSSMDEVLOADEXEC}
3155 */
3156static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3157{
3158 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3159
3160 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3161
3162 /*
3163 * Load Codec nodes states.
3164 */
3165 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
3166 if (RT_FAILURE(rc))
3167 return rc;
3168
3169 /*
3170 * Load MMIO registers.
3171 */
3172 uint32_t cRegs;
3173 switch (uVersion)
3174 {
3175 case HDA_SSM_VERSION_1:
3176 /* Starting with r71199, we would save 112 instead of 113
3177 registers due to some code cleanups. This only affected trunk
3178 builds in the 4.1 development period. */
3179 cRegs = 113;
3180 if (SSMR3HandleRevision(pSSM) >= 71199)
3181 {
3182 uint32_t uVer = SSMR3HandleVersion(pSSM);
3183 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3184 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3185 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3186 cRegs = 112;
3187 }
3188 break;
3189
3190 case HDA_SSM_VERSION_2:
3191 case HDA_SSM_VERSION_3:
3192 cRegs = 112;
3193 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3194 break;
3195
3196 case HDA_SSM_VERSION:
3197 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3198 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3199 LogRel(("cRegs is %d, expected %d\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3200 break;
3201
3202 default:
3203 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3204 }
3205
3206 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3207 {
3208 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3209 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3210 }
3211 else
3212 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3213
3214 /*
3215 * Load HDA DMA counters.
3216 */
3217 uint32_t fFlags = uVersion <= HDA_SSM_VERSION_2 ? SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED : 0;
3218 PCSSMFIELD paFields = uVersion <= HDA_SSM_VERSION_2 ? g_aHdaBDLEDescFieldsOld : g_aHdaBDLEDescFields;
3219 rc = SSMR3GetStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), fFlags, paFields, NULL);
3220 AssertRCReturn(rc, rc);
3221 rc = SSMR3GetStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), fFlags, paFields, NULL);
3222 AssertRCReturn(rc, rc);
3223 rc = SSMR3GetStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), fFlags, paFields, NULL);
3224 AssertRCReturn(rc, rc);
3225
3226 /*
3227 * Update stuff after the state changes.
3228 */
3229 bool fEnableIn = RT_BOOL(SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3230#ifdef VBOX_WITH_HDA_MIC_IN
3231 bool fEnableMicIn = RT_BOOL(SDCTL(pThis, 2) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3232#endif
3233 bool fEnableOut = RT_BOOL(SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3234
3235#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3236 PHDADRIVER pDrv;
3237 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3238 {
3239 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn,
3240 fEnableIn);
3241 if (RT_FAILURE(rc))
3242 break;
3243# ifdef VBOX_WITH_HDA_MIC_IN
3244 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn,
3245 fEnableMicIn);
3246 if (RT_FAILURE(rc))
3247 break;
3248# endif
3249 rc = pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut,
3250 fEnableOut);
3251 if (RT_FAILURE(rc))
3252 break;
3253 }
3254#else
3255 AUD_set_active_in(pThis->pCodec->SwVoiceIn, SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3256 AUD_set_active_out(pThis->pCodec->SwVoiceOut, SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3257#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3258
3259 if (RT_SUCCESS(rc))
3260 {
3261 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3262 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3263 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
3264 }
3265
3266 LogFlowFuncLeaveRC(rc);
3267 return rc;
3268}
3269
3270
3271/* Debug and log type formatters. */
3272
3273/**
3274 * @callback_method_impl{FNRTSTRFORMATTYPE}
3275 */
3276static DECLCALLBACK(size_t)
3277hdaFormatStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3278 const char *pszType, void const *pvValue,
3279 int cchWidth, int cchPrecision, unsigned fFlags,
3280 void *pvUser)
3281{
3282 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
3283 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3284 "SDCTL(raw: %#x, strm:%#x, dir:%RTbool, tp:%RTbool strip:%x, deie:%RTbool, ioce:%RTbool, run:%RTbool, srst:%RTbool)",
3285 sdCtl,
3286 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> HDA_SDCTL_NUM_SHIFT,
3287 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)),
3288 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
3289 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
3290 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
3291 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
3292 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
3293 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
3294}
3295
3296/**
3297 * @callback_method_impl{FNRTSTRFORMATTYPE}
3298 */
3299static DECLCALLBACK(size_t)
3300hdaFormatStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3301 const char *pszType, void const *pvValue,
3302 int cchWidth, int cchPrecision, unsigned fFlags,
3303 void *pvUser)
3304{
3305 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
3306 uint32_t cb;
3307 switch (uSdFifos)
3308 {
3309 case HDA_SDONFIFO_16B: cb = 16; break;
3310 case HDA_SDONFIFO_32B: cb = 32; break;
3311 case HDA_SDONFIFO_64B: cb = 64; break;
3312 case HDA_SDONFIFO_128B: cb = 128; break;
3313 case HDA_SDONFIFO_192B: cb = 192; break;
3314 case HDA_SDONFIFO_256B: cb = 256; break;
3315 case HDA_SDINFIFO_120B: cb = 120; break;
3316 case HDA_SDINFIFO_160B: cb = 160; break;
3317 default: cb = 0; break;
3318 }
3319 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw: %#x, sdfifos:%u B)", uSdFifos, cb);
3320}
3321
3322/**
3323 * @callback_method_impl{FNRTSTRFORMATTYPE}
3324 */
3325static DECLCALLBACK(size_t)
3326hdaFormatStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3327 const char *pszType, void const *pvValue,
3328 int cchWidth, int cchPrecision, unsigned fFlags,
3329 void *pvUser)
3330{
3331 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
3332 uint32_t cb;
3333 switch (uSdFifos)
3334 {
3335 case HDA_SDFIFOW_8B: cb = 8; break;
3336 case HDA_SDFIFOW_16B: cb = 16; break;
3337 case HDA_SDFIFOW_32B: cb = 32; break;
3338 default: cb = 0; break;
3339 }
3340 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSdFifos, cb);
3341}
3342
3343/**
3344 * @callback_method_impl{FNRTSTRFORMATTYPE}
3345 */
3346static DECLCALLBACK(size_t)
3347hdaFormatStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3348 const char *pszType, void const *pvValue,
3349 int cchWidth, int cchPrecision, unsigned fFlags,
3350 void *pvUser)
3351{
3352 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
3353 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3354 "SDSTS(raw: %#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
3355 uSdSts,
3356 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
3357 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
3358 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
3359 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
3360}
3361
3362
3363static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
3364{
3365 int iReg = 0;
3366 for (; iReg < HDA_NREGS; ++iReg)
3367 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
3368 return iReg;
3369 return -1;
3370}
3371
3372
3373static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
3374{
3375 Assert( pThis
3376 && iHdaIndex >= 0
3377 && iHdaIndex < HDA_NREGS);
3378 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
3379}
3380
3381
3382/**
3383 * @callback_method_impl{FNDBGFHANDLERDEV}
3384 */
3385static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3386{
3387 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3388 int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
3389 if (iHdaRegisterIndex != -1)
3390 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3391 else
3392 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
3393 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3394}
3395
3396
3397static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
3398{
3399 Assert( pThis
3400 && iHdaStrmIndex >= 0
3401 && iHdaStrmIndex < 7);
3402 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
3403 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, CTL, iHdaStrmIndex));
3404 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, STS, iHdaStrmIndex));
3405 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOS, iHdaStrmIndex));
3406 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOW, iHdaStrmIndex));
3407}
3408
3409
3410static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
3411{
3412 /* todo: add args parsing */
3413 return -1;
3414}
3415
3416
3417/**
3418 * @callback_method_impl{FNDBGFHANDLERDEV}
3419 */
3420static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3421{
3422 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3423 int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
3424 if (iHdaStrmIndex != -1)
3425 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3426 else
3427 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
3428 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3429}
3430
3431
3432/**
3433 * @callback_method_impl{FNDBGFHANDLERDEV}
3434 */
3435static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3436{
3437 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3438
3439 if (pThis->pCodec->pfnCodecDbgListNodes)
3440 pThis->pCodec->pfnCodecDbgListNodes(pThis->pCodec, pHlp, pszArgs);
3441 else
3442 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3443}
3444
3445
3446/**
3447 * @callback_method_impl{FNDBGFHANDLERDEV}
3448 */
3449static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3450{
3451 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3452
3453 if (pThis->pCodec->pfnCodecDbgSelector)
3454 pThis->pCodec->pfnCodecDbgSelector(pThis->pCodec, pHlp, pszArgs);
3455 else
3456 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3457}
3458
3459
3460/* PDMIBASE */
3461
3462/**
3463 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
3464 */
3465static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
3466{
3467 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
3468 Assert(&pThis->IBase == pInterface);
3469
3470 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
3471 return NULL;
3472}
3473
3474
3475/* PDMDEVREG */
3476
3477/**
3478 * Reset notification.
3479 *
3480 * @returns VBox status.
3481 * @param pDevIns The device instance data.
3482 *
3483 * @remark The original sources didn't install a reset handler, but it seems to
3484 * make sense to me so we'll do it.
3485 */
3486static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
3487{
3488 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3489 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
3490 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
3491 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
3492 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
3493 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
3494 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
3495 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
3496 HDA_REG(pThis, CORBRP) = 0x0;
3497 HDA_REG(pThis, RIRBWP) = 0x0;
3498
3499 LogFunc(("Resetting ...\n"));
3500
3501#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3502 /* Stop any audio currently playing. */
3503 PHDADRIVER pDrv;
3504 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3505 {
3506 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, false /* Disable */);
3507 /* Ignore rc. */
3508 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, false /* Disable */);
3509 /* Ditto. */
3510 pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, false /* Disable */);
3511 /* Ditto. */
3512 }
3513#else
3514 AUD_set_active_in(pThis->pCodec->SwVoiceIn, false);
3515 AUD_set_active_out(pThis->pCodec->SwVoiceOut, false);
3516#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3517
3518 pThis->cbCorbBuf = 256 * sizeof(uint32_t);
3519
3520 if (pThis->pu32CorbBuf)
3521 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
3522 else
3523 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
3524
3525 pThis->cbRirbBuf = 256 * sizeof(uint64_t);
3526 if (pThis->pu64RirbBuf)
3527 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
3528 else
3529 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
3530
3531 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
3532
3533 HDABDLEDESC StEmptyBdle;
3534 for (uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
3535 {
3536 HDASTREAMTRANSFERDESC StreamDesc;
3537 PHDABDLEDESC pBdle = NULL;
3538 if (u8Strm == 0)
3539 pBdle = &pThis->StInBdle;
3540# ifdef VBOX_WITH_HDA_MIC_IN
3541 else if (u8Strm == 2)
3542 pBdle = &pThis->StMicBdle;
3543# endif
3544 else if(u8Strm == 4)
3545 pBdle = &pThis->StOutBdle;
3546 else
3547 {
3548 RT_ZERO(StEmptyBdle);
3549 pBdle = &StEmptyBdle;
3550 }
3551 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
3552 /* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
3553 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0;
3554 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
3555 }
3556
3557 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
3558 HDA_REG(pThis, STATESTS) = 0x1;
3559
3560 LogRel(("HDA: Reset\n"));
3561}
3562
3563/**
3564 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3565 */
3566static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
3567{
3568 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3569
3570#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3571 PHDADRIVER pDrv;
3572 while (!RTListIsEmpty(&pThis->lstDrv))
3573 {
3574 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
3575
3576 RTListNodeRemove(&pDrv->Node);
3577 RTMemFree(pDrv);
3578 }
3579
3580 if (pThis->pMixer)
3581 {
3582 audioMixerDestroy(pThis->pMixer);
3583 pThis->pMixer = NULL;
3584 }
3585#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3586
3587 if (pThis->pCodec)
3588 {
3589 int rc = hdaCodecDestruct(pThis->pCodec);
3590 AssertRC(rc);
3591
3592 RTMemFree(pThis->pCodec);
3593 pThis->pCodec = NULL;
3594 }
3595
3596 RTMemFree(pThis->pu32CorbBuf);
3597 pThis->pu32CorbBuf = NULL;
3598
3599 RTMemFree(pThis->pu64RirbBuf);
3600 pThis->pu64RirbBuf = NULL;
3601
3602 return VINF_SUCCESS;
3603}
3604
3605#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3606/**
3607 * Attach command.
3608 *
3609 * This is called to let the device attach to a driver for a specified LUN
3610 * during runtime. This is not called during VM construction, the device
3611 * constructor have to attach to all the available drivers.
3612 *
3613 * @returns VBox status code.
3614 * @param pDevIns The device instance.
3615 * @param uLUN The logical unit which is being detached.
3616 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3617 */
3618static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
3619{
3620 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3621
3622 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
3623 ("HDA device does not support hotplugging\n"),
3624 VERR_INVALID_PARAMETER);
3625
3626 /*
3627 * Attach driver.
3628 */
3629 char *pszDesc = NULL;
3630 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
3631 AssertMsgReturn(pszDesc,
3632 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
3633 VERR_NO_MEMORY);
3634
3635 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
3636 &pThis->IBase, &pThis->pDrvBase, pszDesc);
3637 if (RT_SUCCESS(rc))
3638 {
3639 PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
3640 if (pDrv)
3641 {
3642 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIAUDIOCONNECTOR);
3643 AssertMsg(pDrv->pConnector != NULL,
3644 ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n",
3645 uLUN, rc));
3646 pDrv->pHDAState = pThis;
3647 pDrv->uLUN = uLUN;
3648
3649 /*
3650 * For now we always set the driver at LUN 0 as our primary
3651 * host backend. This might change in the future.
3652 */
3653 if (pDrv->uLUN == 0)
3654 pDrv->Flags |= PDMAUDIODRVFLAG_PRIMARY;
3655
3656 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
3657
3658 /* Attach to driver list. */
3659 RTListAppend(&pThis->lstDrv, &pDrv->Node);
3660 }
3661 else
3662 rc = VERR_NO_MEMORY;
3663 }
3664 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
3665 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
3666 {
3667 LogFunc(("No attached driver for LUN #%u\n", uLUN));
3668 }
3669 else if (RT_FAILURE(rc))
3670 AssertMsgFailed(("Failed to attach HDA LUN #%u (\"%s\"), rc=%Rrc\n",
3671 uLUN, pszDesc, rc));
3672
3673 RTStrFree(pszDesc);
3674
3675 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
3676 return rc;
3677}
3678
3679static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3680{
3681 NOREF(pDevIns); NOREF(iLUN); NOREF(fFlags);
3682
3683 LogFlowFuncEnter();
3684}
3685#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3686
3687/**
3688 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3689 */
3690static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
3691{
3692 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3693 Assert(iInstance == 0);
3694 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3695
3696 /*
3697 * Validations.
3698 */
3699 if (!CFGMR3AreValuesValid(pCfgHandle, "R0Enabled\0"
3700 "RCEnabled\0"))
3701 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
3702 N_ ("Invalid configuration for the Intel HDA device"));
3703
3704 int rc = CFGMR3QueryBoolDef(pCfgHandle, "RCEnabled", &pThis->fRCEnabled, false);
3705 if (RT_FAILURE(rc))
3706 return PDMDEV_SET_ERROR(pDevIns, rc,
3707 N_("HDA configuration error: failed to read RCEnabled as boolean"));
3708 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &pThis->fR0Enabled, false);
3709 if (RT_FAILURE(rc))
3710 return PDMDEV_SET_ERROR(pDevIns, rc,
3711 N_("HDA configuration error: failed to read R0Enabled as boolean"));
3712
3713 /*
3714 * Initialize data (most of it anyway).
3715 */
3716 pThis->pDevInsR3 = pDevIns;
3717 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3718 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3719 /* IBase */
3720 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
3721
3722 /* PCI Device */
3723 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
3724 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
3725
3726 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
3727 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
3728 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
3729 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
3730 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
3731 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
3732 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
3733 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
3734 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
3735 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
3736 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
3737
3738#if defined(HDA_AS_PCI_EXPRESS)
3739 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
3740#elif defined(VBOX_WITH_MSI_DEVICES)
3741 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
3742#else
3743 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
3744#endif
3745
3746 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
3747 /// of these values needs to be properly documented!
3748 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
3749 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
3750
3751 /* Power Management */
3752 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
3753 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
3754 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
3755
3756#ifdef HDA_AS_PCI_EXPRESS
3757 /* PCI Express */
3758 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
3759 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
3760 /* Device flags */
3761 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
3762 /* version */ 0x1 |
3763 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
3764 /* MSI */ (100) << 9 );
3765 /* Device capabilities */
3766 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
3767 /* Device control */
3768 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
3769 /* Device status */
3770 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
3771 /* Link caps */
3772 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
3773 /* Link control */
3774 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
3775 /* Link status */
3776 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
3777 /* Slot capabilities */
3778 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
3779 /* Slot control */
3780 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
3781 /* Slot status */
3782 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
3783 /* Root control */
3784 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
3785 /* Root capabilities */
3786 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
3787 /* Root status */
3788 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
3789 /* Device capabilities 2 */
3790 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
3791 /* Device control 2 */
3792 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
3793 /* Link control 2 */
3794 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
3795 /* Slot control 2 */
3796 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
3797#endif
3798
3799 /*
3800 * Register the PCI device.
3801 */
3802 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
3803 if (RT_FAILURE(rc))
3804 return rc;
3805
3806 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
3807 if (RT_FAILURE(rc))
3808 return rc;
3809
3810#ifdef VBOX_WITH_MSI_DEVICES
3811 PDMMSIREG MsiReg;
3812 RT_ZERO(MsiReg);
3813 MsiReg.cMsiVectors = 1;
3814 MsiReg.iMsiCapOffset = 0x60;
3815 MsiReg.iMsiNextOffset = 0x50;
3816 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
3817 if (RT_FAILURE(rc))
3818 {
3819 /* That's OK, we can work without MSI */
3820 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
3821 }
3822#endif
3823
3824 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
3825 if (RT_FAILURE(rc))
3826 return rc;
3827
3828#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3829 RTListInit(&pThis->lstDrv);
3830
3831 uint8_t uLUN;
3832 for (uLUN = 0; uLUN < UINT8_MAX; uLUN)
3833 {
3834 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
3835 rc = hdaAttach(pDevIns, uLUN, PDM_TACH_FLAGS_NOT_HOT_PLUG);
3836 if (RT_FAILURE(rc))
3837 {
3838 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3839 rc = VINF_SUCCESS;
3840
3841 break;
3842 }
3843
3844 uLUN++;
3845 }
3846
3847 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
3848
3849 if (RT_SUCCESS(rc))
3850 {
3851 rc = audioMixerCreate("HDA Mixer", 0 /* uFlags */,
3852 &pThis->pMixer);
3853 if (RT_SUCCESS(rc))
3854 {
3855 PDMAUDIOSTREAMCFG streamCfg;
3856 streamCfg.uHz = 48000;
3857 streamCfg.cChannels = 2;
3858 streamCfg.enmFormat = AUD_FMT_S16;
3859 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANESS;
3860
3861 rc = audioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
3862 AssertRC(rc);
3863
3864 /* Add all required audio sinks. */
3865 rc = audioMixerAddSink(pThis->pMixer, "[Recording] Line In",
3866 &pThis->pSinkLineIn);
3867 AssertRC(rc);
3868
3869 rc = audioMixerAddSink(pThis->pMixer, "[Recording] Microphone In",
3870 &pThis->pSinkMicIn);
3871 AssertRC(rc);
3872 }
3873 }
3874
3875 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
3876#else
3877 /*
3878 * Attach driver.
3879 */
3880 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Audio Driver Port");
3881 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3882 Log(("hda: No attached driver!\n"));
3883 else if (RT_FAILURE(rc))
3884 {
3885 AssertMsgFailed(("Failed to attach Intel HDA LUN #0! rc=%Rrc\n", rc));
3886 return rc;
3887 }
3888#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3889
3890 if (RT_SUCCESS(rc))
3891 {
3892 /* Construct codec. */
3893 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
3894 if (!pThis->pCodec)
3895 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
3896
3897#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3898 /* Audio driver callbacks for multiplexing. */
3899 pThis->pCodec->pfnCloseIn = hdaCloseIn;
3900 pThis->pCodec->pfnCloseOut = hdaCloseOut;
3901 pThis->pCodec->pfnOpenIn = hdaOpenIn;
3902 pThis->pCodec->pfnOpenOut = hdaOpenOut;
3903 pThis->pCodec->pfnSetVolume = hdaSetVolume;
3904#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3905
3906 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
3907
3908 /* Construct the codec. */
3909 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfgHandle);
3910 if (RT_FAILURE(rc))
3911 AssertRCReturn(rc, rc);
3912
3913 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
3914 verb F20 should provide device/codec recognition. */
3915 Assert(pThis->pCodec->u16VendorId);
3916 Assert(pThis->pCodec->u16DeviceId);
3917 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
3918 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
3919
3920#ifndef VBOX_WITH_PDM_AUDIO_DRIVER
3921 pThis->pCodec->pfnTransfer = hdaTransfer;
3922#endif
3923 pThis->pCodec->pfnReset = hdaCodecReset;
3924 }
3925
3926 if (RT_SUCCESS(rc))
3927 {
3928 hdaReset(pDevIns);
3929
3930 /*
3931 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
3932 * hdaReset shouldn't affects these registers.
3933 */
3934 HDA_REG(pThis, WAKEEN) = 0x0;
3935 HDA_REG(pThis, STATESTS) = 0x0;
3936
3937 /*
3938 * Debug and string formatter types.
3939 */
3940 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
3941 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
3942 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
3943 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
3944
3945 rc = RTStrFormatTypeRegister("sdctl", hdaFormatStrmCtl, NULL);
3946 AssertRC(rc);
3947 rc = RTStrFormatTypeRegister("sdsts", hdaFormatStrmSts, NULL);
3948 AssertRC(rc);
3949 rc = RTStrFormatTypeRegister("sdfifos", hdaFormatStrmFifos, NULL);
3950 AssertRC(rc);
3951 rc = RTStrFormatTypeRegister("sdfifow", hdaFormatStrmFifow, NULL);
3952 AssertRC(rc);
3953 #if 0
3954 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
3955 AssertRC(rc);
3956 #endif
3957
3958 /*
3959 * Some debug assertions.
3960 */
3961 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
3962 {
3963 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
3964 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
3965
3966 /* binary search order. */
3967 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
3968 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3969 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
3970
3971 /* alignment. */
3972 AssertReleaseMsg( pReg->size == 1
3973 || (pReg->size == 2 && (pReg->offset & 1) == 0)
3974 || (pReg->size == 3 && (pReg->offset & 3) == 0)
3975 || (pReg->size == 4 && (pReg->offset & 3) == 0),
3976 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3977
3978 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
3979 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
3980 if (pReg->offset & 3)
3981 {
3982 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
3983 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3984 if (pPrevReg)
3985 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
3986 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3987 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
3988 }
3989 #if 0
3990 if ((pReg->offset + pReg->size) & 3)
3991 {
3992 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3993 if (pNextReg)
3994 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
3995 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3996 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
3997 }
3998 #endif
3999
4000 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
4001 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
4002 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
4003 }
4004 }
4005
4006#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
4007 if (RT_SUCCESS(rc))
4008 {
4009 /* Start the emulation timer. */
4010 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
4011 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
4012 AssertRCReturn(rc, rc);
4013
4014 if (RT_SUCCESS(rc))
4015 {
4016 /** @todo Investigate why sounds is getting corrupted if the "ticks" value is too
4017 * low, e.g. "PDMDevHlpTMTimeVirtGetFreq / 200". */
4018 pThis->uTicks = PDMDevHlpTMTimeVirtGetFreq(pDevIns) / 500; /** @todo Make this configurable! */
4019 if (pThis->uTicks < 100)
4020 pThis->uTicks = 100;
4021 LogFunc(("Timer ticks=%RU64\n", pThis->uTicks));
4022
4023 /* Fire off timer. */
4024 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
4025 }
4026 }
4027
4028# ifdef VBOX_WITH_STATISTICS
4029 if (RT_SUCCESS(rc))
4030 {
4031 /*
4032 * Register statistics.
4033 */
4034 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
4035 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
4036 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
4037 }
4038# endif
4039
4040#endif
4041
4042 LogFlowFuncLeaveRC(rc);
4043 return rc;
4044}
4045
4046/**
4047 * The device registration structure.
4048 */
4049const PDMDEVREG g_DeviceICH6_HDA =
4050{
4051 /* u32Version */
4052 PDM_DEVREG_VERSION,
4053 /* szName */
4054 "hda",
4055 /* szRCMod */
4056 "VBoxDDGC.gc",
4057 /* szR0Mod */
4058 "VBoxDDR0.r0",
4059 /* pszDescription */
4060 "Intel HD Audio Controller",
4061 /* fFlags */
4062 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
4063 /* fClass */
4064 PDM_DEVREG_CLASS_AUDIO,
4065 /* cMaxInstances */
4066 1,
4067 /* cbInstance */
4068 sizeof(HDASTATE),
4069 /* pfnConstruct */
4070 hdaConstruct,
4071 /* pfnDestruct */
4072 hdaDestruct,
4073 /* pfnRelocate */
4074 NULL,
4075 /* pfnMemSetup */
4076 NULL,
4077 /* pfnPowerOn */
4078 NULL,
4079 /* pfnReset */
4080 hdaReset,
4081 /* pfnSuspend */
4082 NULL,
4083 /* pfnResume */
4084 NULL,
4085 /* pfnAttach */
4086 NULL,
4087 /* pfnDetach */
4088 NULL,
4089 /* pfnQueryInterface. */
4090 NULL,
4091 /* pfnInitComplete */
4092 NULL,
4093 /* pfnPowerOff */
4094 NULL,
4095 /* pfnSoftReset */
4096 NULL,
4097 /* u32VersionEnd */
4098 PDM_DEVREG_VERSION
4099};
4100
4101#endif /* IN_RING3 */
4102#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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