VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 54266

Last change on this file since 54266 was 54235, checked in by vboxsync, 10 years ago

PDM/Audio: Remove unused code.
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File size: 160.8 KB
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1/* $Id: DevIchHda.cpp 54235 2015-02-17 15:08:51Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2015 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/vmm/pdmaudioifs.h>
27#include <VBox/version.h>
28
29#include <iprt/assert.h>
30#include <iprt/asm.h>
31#include <iprt/asm-math.h>
32#ifdef IN_RING3
33# include <iprt/uuid.h>
34# include <iprt/string.h>
35# include <iprt/mem.h>
36#endif
37#include <iprt/list.h>
38
39#ifdef LOG_GROUP
40# undef LOG_GROUP
41#endif
42#define LOG_GROUP LOG_GROUP_DEV_AUDIO
43#include <VBox/log.h>
44
45#include "VBoxDD.h"
46
47#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
48# include "AudioMixer.h"
49#else
50 extern "C" {
51 #include "audio.h"
52 }
53#endif
54#include "DevIchHdaCodec.h"
55
56/*******************************************************************************
57* Defined Constants And Macros *
58*******************************************************************************/
59//#define HDA_AS_PCI_EXPRESS
60#define VBOX_WITH_INTEL_HDA
61
62#if (defined(DEBUG) && defined(DEBUG_andy))
63/* Enables experimental support for separate mic-in handling.
64 Do not enable this yet for regular builds, as this needs more testing first! */
65# define VBOX_WITH_HDA_MIC_IN
66#endif
67
68#if defined(VBOX_WITH_HP_HDA)
69/* HP Pavilion dv4t-1300 */
70# define HDA_PCI_VENDOR_ID 0x103c
71# define HDA_PCI_DEVICE_ID 0x30f7
72#elif defined(VBOX_WITH_INTEL_HDA)
73/* Intel HDA controller */
74# define HDA_PCI_VENDOR_ID 0x8086
75# define HDA_PCI_DEVICE_ID 0x2668
76#elif defined(VBOX_WITH_NVIDIA_HDA)
77/* nVidia HDA controller */
78# define HDA_PCI_VENDOR_ID 0x10de
79# define HDA_PCI_DEVICE_ID 0x0ac0
80#else
81# error "Please specify your HDA device vendor/device IDs"
82#endif
83
84/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
85 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
86 * is read only except for bit 15 like the HDA spec states.
87 *
88 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
89 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
90#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
91
92#define HDA_NREGS 114
93#define HDA_NREGS_SAVED 112
94
95/**
96 * NB: Register values stored in memory (au32Regs[]) are indexed through
97 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
98 * register descriptors in g_aHdaRegMap[] are indexed through the
99 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
100 *
101 * The au32Regs[] layout is kept unchanged for saved state
102 * compatibility. */
103
104/* Registers */
105#define HDA_REG_IND_NAME(x) HDA_REG_##x
106#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
107#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
108#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
109#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
110#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
111#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
112#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
113
114
115#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
116#define HDA_RMX_GCAP 0
117/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
118 * oss (15:12) - number of output streams supported
119 * iss (11:8) - number of input streams supported
120 * bss (7:3) - number of bidirectional streams supported
121 * bds (2:1) - number of serial data out signals supported
122 * b64sup (0) - 64 bit addressing supported.
123 */
124#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
125 ( (((oss) & 0xF) << 12) \
126 | (((iss) & 0xF) << 8) \
127 | (((bss) & 0x1F) << 3) \
128 | (((bds) & 0x3) << 2) \
129 | ((b64sup) & 1))
130
131#define HDA_REG_VMIN 1 /* 0x02 */
132#define HDA_RMX_VMIN 1
133
134#define HDA_REG_VMAJ 2 /* 0x03 */
135#define HDA_RMX_VMAJ 2
136
137#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
138#define HDA_RMX_OUTPAY 3
139
140#define HDA_REG_INPAY 4 /* 0x06-0x07 */
141#define HDA_RMX_INPAY 4
142
143#define HDA_REG_GCTL 5 /* 0x08-0x0B */
144#define HDA_RMX_GCTL 5
145#define HDA_GCTL_RST_SHIFT 0
146#define HDA_GCTL_FSH_SHIFT 1
147#define HDA_GCTL_UR_SHIFT 8
148
149#define HDA_REG_WAKEEN 6 /* 0x0C */
150#define HDA_RMX_WAKEEN 6
151
152#define HDA_REG_STATESTS 7 /* 0x0E */
153#define HDA_RMX_STATESTS 7
154#define HDA_STATES_SCSF 0x7
155
156#define HDA_REG_GSTS 8 /* 0x10-0x11*/
157#define HDA_RMX_GSTS 8
158#define HDA_GSTS_FSH_SHIFT 1
159
160#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
161#define HDA_RMX_OUTSTRMPAY 112
162
163#define HDA_REG_INSTRMPAY 10 /* 0x1a */
164#define HDA_RMX_INSTRMPAY 113
165
166#define HDA_REG_INTCTL 11 /* 0x20 */
167#define HDA_RMX_INTCTL 9
168#define HDA_INTCTL_GIE_SHIFT 31
169#define HDA_INTCTL_CIE_SHIFT 30
170#define HDA_INTCTL_S0_SHIFT 0
171#define HDA_INTCTL_S1_SHIFT 1
172#define HDA_INTCTL_S2_SHIFT 2
173#define HDA_INTCTL_S3_SHIFT 3
174#define HDA_INTCTL_S4_SHIFT 4
175#define HDA_INTCTL_S5_SHIFT 5
176#define HDA_INTCTL_S6_SHIFT 6
177#define HDA_INTCTL_S7_SHIFT 7
178#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
179
180#define HDA_REG_INTSTS 12 /* 0x24 */
181#define HDA_RMX_INTSTS 10
182#define HDA_INTSTS_GIS_SHIFT 31
183#define HDA_INTSTS_CIS_SHIFT 30
184#define HDA_INTSTS_S0_SHIFT 0
185#define HDA_INTSTS_S1_SHIFT 1
186#define HDA_INTSTS_S2_SHIFT 2
187#define HDA_INTSTS_S3_SHIFT 3
188#define HDA_INTSTS_S4_SHIFT 4
189#define HDA_INTSTS_S5_SHIFT 5
190#define HDA_INTSTS_S6_SHIFT 6
191#define HDA_INTSTS_S7_SHIFT 7
192#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
193
194#define HDA_REG_WALCLK 13 /* 0x24 */
195#define HDA_RMX_WALCLK /* Not defined! */
196
197/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
198 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
199 * the datasheet.
200 */
201#define HDA_REG_SSYNC 14 /* 0x34 */
202#define HDA_RMX_SSYNC 12
203
204#define HDA_REG_CORBLBASE 15 /* 0x40 */
205#define HDA_RMX_CORBLBASE 13
206
207#define HDA_REG_CORBUBASE 16 /* 0x44 */
208#define HDA_RMX_CORBUBASE 14
209
210#define HDA_REG_CORBWP 17 /* 0x48 */
211#define HDA_RMX_CORBWP 15
212
213#define HDA_REG_CORBRP 18 /* 0x4A */
214#define HDA_RMX_CORBRP 16
215#define HDA_CORBRP_RST_SHIFT 15
216#define HDA_CORBRP_WP_SHIFT 0
217#define HDA_CORBRP_WP_MASK 0xFF
218
219#define HDA_REG_CORBCTL 19 /* 0x4C */
220#define HDA_RMX_CORBCTL 17
221#define HDA_CORBCTL_DMA_SHIFT 1
222#define HDA_CORBCTL_CMEIE_SHIFT 0
223
224#define HDA_REG_CORBSTS 20 /* 0x4D */
225#define HDA_RMX_CORBSTS 18
226#define HDA_CORBSTS_CMEI_SHIFT 0
227
228#define HDA_REG_CORBSIZE 21 /* 0x4E */
229#define HDA_RMX_CORBSIZE 19
230#define HDA_CORBSIZE_SZ_CAP 0xF0
231#define HDA_CORBSIZE_SZ 0x3
232/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
233
234#define HDA_REG_RIRBLBASE 22 /* 0x50 */
235#define HDA_RMX_RIRBLBASE 20
236
237#define HDA_REG_RIRBUBASE 23 /* 0x54 */
238#define HDA_RMX_RIRBUBASE 21
239
240#define HDA_REG_RIRBWP 24 /* 0x58 */
241#define HDA_RMX_RIRBWP 22
242#define HDA_RIRBWP_RST_SHIFT 15
243#define HDA_RIRBWP_WP_MASK 0xFF
244
245#define HDA_REG_RINTCNT 25 /* 0x5A */
246#define HDA_RMX_RINTCNT 23
247#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
248
249#define HDA_REG_RIRBCTL 26 /* 0x5C */
250#define HDA_RMX_RIRBCTL 24
251#define HDA_RIRBCTL_RIC_SHIFT 0
252#define HDA_RIRBCTL_DMA_SHIFT 1
253#define HDA_ROI_DMA_SHIFT 2
254
255#define HDA_REG_RIRBSTS 27 /* 0x5D */
256#define HDA_RMX_RIRBSTS 25
257#define HDA_RIRBSTS_RINTFL_SHIFT 0
258#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
259
260#define HDA_REG_RIRBSIZE 28 /* 0x5E */
261#define HDA_RMX_RIRBSIZE 26
262#define HDA_RIRBSIZE_SZ_CAP 0xF0
263#define HDA_RIRBSIZE_SZ 0x3
264
265#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
266#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
267
268
269#define HDA_REG_IC 29 /* 0x60 */
270#define HDA_RMX_IC 27
271
272#define HDA_REG_IR 30 /* 0x64 */
273#define HDA_RMX_IR 28
274
275#define HDA_REG_IRS 31 /* 0x68 */
276#define HDA_RMX_IRS 29
277#define HDA_IRS_ICB_SHIFT 0
278#define HDA_IRS_IRV_SHIFT 1
279
280#define HDA_REG_DPLBASE 32 /* 0x70 */
281#define HDA_RMX_DPLBASE 30
282#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
283
284#define HDA_REG_DPUBASE 33 /* 0x74 */
285#define HDA_RMX_DPUBASE 31
286#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
287#define DPBASE_ENABLED 1
288#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
289
290#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
291#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
292/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
293#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
294
295#define HDA_REG_SD0CTL 34 /* 0x80 */
296#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
297#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
298#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
299#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
300#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
301#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
302#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
303#define HDA_RMX_SD0CTL 32
304#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
305#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
306#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
307#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
308#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
309#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
310#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
311
312#define SD(func, num) SD##num##func
313#define SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
314#define SDCTL_NUM(pThis, num) ((SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
315#define HDA_SDCTL_NUM_MASK 0xF
316#define HDA_SDCTL_NUM_SHIFT 20
317#define HDA_SDCTL_DIR_SHIFT 19
318#define HDA_SDCTL_TP_SHIFT 18
319#define HDA_SDCTL_STRIPE_MASK 0x3
320#define HDA_SDCTL_STRIPE_SHIFT 16
321#define HDA_SDCTL_DEIE_SHIFT 4
322#define HDA_SDCTL_FEIE_SHIFT 3
323#define HDA_SDCTL_ICE_SHIFT 2
324#define HDA_SDCTL_RUN_SHIFT 1
325#define HDA_SDCTL_SRST_SHIFT 0
326
327#define HDA_REG_SD0STS 35 /* 0x83 */
328#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
329#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
330#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
331#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
332#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
333#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
334#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
335#define HDA_RMX_SD0STS 33
336#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
337#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
338#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
339#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
340#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
341#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
342#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
343
344#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
345#define HDA_SDSTS_FIFORDY_SHIFT 5
346#define HDA_SDSTS_DE_SHIFT 4
347#define HDA_SDSTS_FE_SHIFT 3
348#define HDA_SDSTS_BCIS_SHIFT 2
349
350#define HDA_REG_SD0LPIB 36 /* 0x84 */
351#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
352#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
353#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
354#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
355#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
356#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
357#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
358#define HDA_RMX_SD0LPIB 34
359#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
360#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
361#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
362#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
363#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
364#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
365#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
366
367#define HDA_REG_SD0CBL 37 /* 0x88 */
368#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
369#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
370#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
371#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
372#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
373#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
374#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
375#define HDA_RMX_SD0CBL 35
376#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
377#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
378#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
379#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
380#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
381#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
382#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
383
384
385#define HDA_REG_SD0LVI 38 /* 0x8C */
386#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
387#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
388#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
389#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
390#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
391#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
392#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
393#define HDA_RMX_SD0LVI 36
394#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
395#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
396#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
397#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
398#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
399#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
400#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
401
402#define HDA_REG_SD0FIFOW 39 /* 0x8E */
403#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
404#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
405#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
406#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
407#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
408#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
409#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
410#define HDA_RMX_SD0FIFOW 37
411#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
412#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
413#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
414#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
415#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
416#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
417#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
418
419/*
420 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
421 */
422#define HDA_SDFIFOW_8B 0x2
423#define HDA_SDFIFOW_16B 0x3
424#define HDA_SDFIFOW_32B 0x4
425
426#define HDA_REG_SD0FIFOS 40 /* 0x90 */
427#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
428#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
429#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
430#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
431#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
432#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
433#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
434#define HDA_RMX_SD0FIFOS 38
435#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
436#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
437#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
438#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
439#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
440#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
441#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
442
443/*
444 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
445 * formula: size - 1
446 * Other values not listed are not supported.
447 */
448#define HDA_SDONFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
449#define HDA_SDONFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
450#define HDA_SDONFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
451#define HDA_SDONFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
452#define HDA_SDONFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
453#define HDA_SDONFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
454#define HDA_SDINFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
455#define HDA_SDINFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
456#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
457
458#define HDA_REG_SD0FMT 41 /* 0x92 */
459#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
460#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
461#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
462#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
463#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
464#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
465#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
466#define HDA_RMX_SD0FMT 39
467#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
468#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
469#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
470#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
471#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
472#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
473#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
474
475#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
476#define HDA_SDFMT_BASE_RATE_SHIFT 14
477#define HDA_SDFMT_MULT_SHIFT 11
478#define HDA_SDFMT_MULT_MASK 0x7
479#define HDA_SDFMT_DIV_SHIFT 8
480#define HDA_SDFMT_DIV_MASK 0x7
481#define HDA_SDFMT_BITS_SHIFT 4
482#define HDA_SDFMT_BITS_MASK 0x7
483#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
484#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
485#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
486
487#define HDA_REG_SD0BDPL 42 /* 0x98 */
488#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
489#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
490#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
491#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
492#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
493#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
494#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
495#define HDA_RMX_SD0BDPL 40
496#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
497#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
498#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
499#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
500#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
501#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
502#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
503
504#define HDA_REG_SD0BDPU 43 /* 0x9C */
505#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
506#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
507#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
508#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
509#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
510#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
511#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
512#define HDA_RMX_SD0BDPU 41
513#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
514#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
515#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
516#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
517#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
518#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
519#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
520
521#define HDA_CODEC_CAD_SHIFT 28
522/* Encodes the (required) LUN into a codec command. */
523#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
524
525
526
527/*******************************************************************************
528* Structures and Typedefs *
529*******************************************************************************/
530typedef struct HDABDLEDESC
531{
532 uint64_t u64BdleCviAddr;
533 uint32_t u32BdleMaxCvi;
534 uint32_t u32BdleCvi;
535 uint32_t u32BdleCviLen;
536 uint32_t u32BdleCviPos;
537 bool fBdleCviIoc;
538 uint32_t cbUnderFifoW;
539 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
540} HDABDLEDESC, *PHDABDLEDESC;
541
542typedef struct HDASTREAMTRANSFERDESC
543{
544 uint64_t u64BaseDMA;
545 uint32_t u32Ctl;
546 uint32_t *pu32Sts;
547 uint8_t u8Strm;
548 uint32_t *pu32Lpib;
549 uint32_t u32Cbl;
550 uint32_t u32Fifos;
551} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
552
553#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
554typedef struct HDAINPUTSTREAM
555{
556 /** PCM line input stream. */
557 R3PTRTYPE(PPDMAUDIOGSTSTRMIN) pStrmIn;
558 /** Mixer handle for line input stream. */
559 R3PTRTYPE(PAUDMIXSTREAM) phStrmIn;
560} HDAINPUTSTREAM, *PHDAINPUTSTREAM;
561
562typedef struct HDAOUTPUTSTREAM
563{
564 /** PCM output stream. */
565 R3PTRTYPE(PPDMAUDIOGSTSTRMOUT) pStrmOut;
566} HDAOUTPUTSTREAM, *PHDAOUTPUTSTREAM;
567
568/**
569 * Struct for maintaining a host backend driver.
570 * This driver must be associated to one, and only one,
571 * HDA codec. The HDA controller does the actual multiplexing
572 * of HDA codec data to various host backend drivers then.
573 *
574 * This HDA device uses a timer in order to synchronize all
575 * read/write accesses across all attached LUNs / backends.
576 */
577typedef struct HDADRIVER
578{
579 union
580 {
581 /** Node for storing this driver in our device driver
582 * list of HDASTATE. */
583 RTLISTNODE Node;
584 struct
585 {
586 R3PTRTYPE(void *) dummy1;
587 R3PTRTYPE(void *) dummy2;
588 } dummy;
589 };
590
591 /** Pointer to HDA controller (state). */
592 R3PTRTYPE(PHDASTATE) pHDAState;
593 /** Driver flags. */
594 PDMAUDIODRVFLAGS Flags;
595 uint8_t u32Padding0[3];
596 /** LUN to which this driver has been assigned. */
597 uint8_t uLUN;
598 /** Audio connector interface to the underlying
599 * host backend. */
600 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
601 /** Stream for line input. */
602 HDAINPUTSTREAM LineIn;
603 /** Stream for mic input. */
604 HDAINPUTSTREAM MicIn;
605 /** Stream for output. */
606 HDAOUTPUTSTREAM Out;
607} HDADRIVER, *PHDADRIVER;
608#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
609
610/**
611 * ICH Intel HD Audio Controller state.
612 */
613typedef struct HDASTATE
614{
615 /** The PCI device structure. */
616 PCIDevice PciDev;
617 /** R3 Pointer to the device instance. */
618 PPDMDEVINSR3 pDevInsR3;
619 /** R0 Pointer to the device instance. */
620 PPDMDEVINSR0 pDevInsR0;
621 /** R0 Pointer to the device instance. */
622 PPDMDEVINSRC pDevInsRC;
623
624 uint32_t u32Padding;
625
626 /** Pointer to the attached audio driver. */
627 R3PTRTYPE(PPDMIBASE) pDrvBase;
628 /** The base interface for LUN\#0. */
629 PDMIBASE IBase;
630 RTGCPHYS MMIOBaseAddr;
631 uint32_t au32Regs[HDA_NREGS];
632 HDABDLEDESC StInBdle;
633 HDABDLEDESC StOutBdle;
634 HDABDLEDESC StMicBdle;
635 uint64_t u64CORBBase;
636 uint64_t u64RIRBBase;
637 uint64_t u64DPBase;
638 /** Pointer to CORB buffer. */
639 R3PTRTYPE(uint32_t *) pu32CorbBuf;
640 /** Size in bytes of CORB buffer. */
641 uint32_t cbCorbBuf;
642 uint32_t u32Padding2;
643 /** Pointer to RIRB buffer. */
644 R3PTRTYPE(uint64_t *) pu64RirbBuf;
645 /** Size in bytes of RIRB buffer. */
646 uint32_t cbRirbBuf;
647 /** Indicates if HDA is in reset. */
648 bool fInReset;
649 /** Interrupt on completion */
650 bool fCviIoc;
651 /** Flag whether the R0 part is enabled. */
652 bool fR0Enabled;
653 /** Flag whether the RC part is enabled. */
654 bool fRCEnabled;
655#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
656 /** The emulation timer for handling the attached
657 * LUN drivers. */
658 PTMTIMERR3 pTimer;
659 /** Timer ticks for handling the LUN drivers. */
660 uint64_t uTicks;
661# ifdef VBOX_WITH_STATISTICS
662 STAMPROFILE StatTimer;
663 STAMCOUNTER StatBytesRead;
664 STAMCOUNTER StatBytesWritten;
665# endif
666 /** Pointer to HDA codec to use. */
667 R3PTRTYPE(PHDACODEC) pCodec;
668 union
669 {
670 /** List of associated LUN drivers. */
671 RTLISTANCHOR lstDrv;
672 struct
673 {
674 R3PTRTYPE(void *) dummy1;
675 R3PTRTYPE(void *) dummy2;
676 } dummy;
677 };
678 /** The device' software mixer. */
679 R3PTRTYPE(PAUDIOMIXER) pMixer;
680 /** Audio mixer sink for line input. */
681 R3PTRTYPE(PAUDMIXSINK) pSinkLineIn;
682 /** Audio mixer sink for microphone input. */
683 R3PTRTYPE(PAUDMIXSINK) pSinkMicIn;
684#else /* !VBOX_WITH_PDM_AUDIO_DRIVER */
685 /** The HDA codec to use. */
686 R3PTRTYPE(PHDACODEC) pCodec;
687#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
688 uint64_t u64BaseTS;
689 /** 1.2.3.4.5.6.7. - someone please tell me what I'm counting! - .8.9.10... */
690 uint8_t u8Counter;
691#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
692 uint8_t au8Padding[7];
693#else
694 uint8_t au8Padding[7];
695#endif
696} HDASTATE;
697/** Pointer to the ICH Intel HD Audio Controller state. */
698typedef HDASTATE *PHDASTATE;
699
700#define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \
701 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, In, SDFMT_BASE_RATE(pThis, 0), SDFMT_MULT(pThis, 0), SDFMT_DIV(pThis, 0)) )
702#define OSD0FMT_TO_AUDIO_SELECTOR(pThis) \
703 ( AUDIO_FORMAT_SELECTOR((pThis)->pCodec, Out, SDFMT_BASE_RATE(pThis, 4), SDFMT_MULT(pThis, 4), SDFMT_DIV(pThis, 4)) )
704
705
706/*******************************************************************************
707* Internal Functions *
708*******************************************************************************/
709#ifndef VBOX_DEVICE_STRUCT_TESTCASE
710static FNPDMDEVRESET hdaReset;
711
712static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
713static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
714static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
715static int hdaRegReadSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
716static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
717static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
718static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
719static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
720static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
721static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
722static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
723static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
724static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
725static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
726static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
727static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
728static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
729
730static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
731static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
732static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
733static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
734static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
735static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
736static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
737static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
738static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
739static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
740static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
741static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
742static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
743static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
744static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
745static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
746
747#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
748static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser);
749static int hdaTransfer(PHDASTATE pThis, ENMSOUNDSOURCE enmSrc, uint32_t cbAvail);
750#else
751static int hdaTransfer(PHDACODEC pCodec, ENMSOUNDSOURCE enmSource, int cbAvail);
752#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
753
754#ifdef IN_RING3
755DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
756 PHDASTREAMTRANSFERDESC pStreamDesc);
757static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
758#ifdef LOG_ENABLED
759static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
760#endif
761#endif
762
763
764/*******************************************************************************
765* Global Variables *
766*******************************************************************************/
767
768/* see 302349 p 6.2*/
769static const struct HDAREGDESC
770{
771 /** Register offset in the register space. */
772 uint32_t offset;
773 /** Size in bytes. Registers of size > 4 are in fact tables. */
774 uint32_t size;
775 /** Readable bits. */
776 uint32_t readable;
777 /** Writable bits. */
778 uint32_t writable;
779 /** Read callback. */
780 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
781 /** Write callback. */
782 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
783 /** Index into the register storage array. */
784 uint32_t mem_idx;
785 /** Abbreviated name. */
786 const char *abbrev;
787} g_aHdaRegMap[HDA_NREGS] =
788
789/* Turn a short register name into an memory index and a stringized name. */
790#define RA(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
791/* Same as above for an input stream ('I' prefixed). */
792#define IA(abbrev) HDA_MEM_IND_NAME(abbrev), "I"#abbrev
793/* Same as above for an output stream ('O' prefixed). */
794#define OA(abbrev) HDA_MEM_IND_NAME(abbrev), "O"#abbrev
795/* Same as above for a register *not* stored in memory. */
796#define UA(abbrev) 0, #abbrev
797
798{
799 /* offset size read mask write mask read callback write callback abbrev */
800 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- */
801 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(GCAP) }, /* Global Capabilities */
802 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMIN) }, /* Minor Version */
803 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(VMAJ) }, /* Major Version */
804 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTPAY) }, /* Output Payload Capabilities */
805 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INPAY) }, /* Input Payload Capabilities */
806 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , RA(GCTL) }, /* Global Control */
807 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , RA(WAKEEN) }, /* Wake Enable */
808 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , RA(STATESTS) }, /* State Change Status */
809 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , RA(GSTS) }, /* Global Status */
810 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(OUTSTRMPAY)}, /* Output Stream Payload Capability */
811 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , RA(INSTRMPAY) }, /* Input Stream Payload Capability */
812 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(INTCTL) }, /* Interrupt Control */
813 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimpl , RA(INTSTS) }, /* Interrupt Status */
814 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , UA(WALCLK) }, /* Wall Clock Counter */
815 /// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
816 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , RA(SSYNC) }, /* Stream Synchronization */
817 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(CORBLBASE) }, /* CORB Lower Base Address */
818 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(CORBUBASE) }, /* CORB Upper Base Address */
819 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , RA(CORBWP) }, /* CORB Write Pointer */
820 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , RA(CORBRP) }, /* CORB Read Pointer */
821 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , RA(CORBCTL) }, /* CORB Control */
822 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , RA(CORBSTS) }, /* CORB Status */
823 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(CORBSIZE) }, /* CORB Size */
824 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBLBASE) }, /* RIRB Lower Base Address */
825 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(RIRBUBASE) }, /* RIRB Upper Base Address */
826 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , RA(RIRBWP) }, /* RIRB Write Pointer */
827 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , RA(RINTCNT) }, /* Response Interrupt Count */
828 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , RA(RIRBCTL) }, /* RIRB Control */
829 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , RA(RIRBSTS) }, /* RIRB Status */
830 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , RA(RIRBSIZE) }, /* RIRB Size */
831 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , RA(IC) }, /* Immediate Command */
832 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , RA(IR) }, /* Immediate Response */
833 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , RA(IRS) }, /* Immediate Command Status */
834 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , RA(DPLBASE) }, /* MA Position Lower Base */
835 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , RA(DPUBASE) }, /* DMA Position Upper Base */
836
837 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD0CTL) }, /* Input Stream Descriptor 0 (ICD0) Control */
838 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD0STS) }, /* ISD0 Status */
839 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0LPIB) }, /* ISD0 Link Position In Buffer */
840 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD0CBL) }, /* ISD0 Cyclic Buffer Length */
841 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD0LVI) }, /* ISD0 Last Valid Index */
842 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD0FIFOW) }, /* ISD0 FIFO Watermark */
843 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD0FIFOS) }, /* ISD0 FIFO Size */
844 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD0FMT) }, /* ISD0 Format */
845 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD0BDPL) }, /* ISD0 Buffer Descriptor List Pointer-Lower Base Address */
846 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD0BDPU) }, /* ISD0 Buffer Descriptor List Pointer-Upper Base Address */
847
848 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD1CTL) }, /* Input Stream Descriptor 1 (ISD1) Control */
849 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD1STS) }, /* ISD1 Status */
850 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1LPIB) }, /* ISD1 Link Position In Buffer */
851 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD1CBL) }, /* ISD1 Cyclic Buffer Length */
852 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD1LVI) }, /* ISD1 Last Valid Index */
853 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD1FIFOW) }, /* ISD1 FIFO Watermark */
854 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD1FIFOS) }, /* ISD1 FIFO Size */
855 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD1FMT) }, /* ISD1 Format */
856 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD1BDPL) }, /* ISD1 Buffer Descriptor List Pointer-Lower Base Address */
857 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD1BDPU) }, /* ISD1 Buffer Descriptor List Pointer-Upper Base Address */
858
859 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD2CTL) }, /* Input Stream Descriptor 2 (ISD2) Control */
860 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD2STS) }, /* ISD2 Status */
861 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2LPIB) }, /* ISD2 Link Position In Buffer */
862 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD2CBL) }, /* ISD2 Cyclic Buffer Length */
863 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD2LVI) }, /* ISD2 Last Valid Index */
864 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD2FIFOW) }, /* ISD2 FIFO Watermark */
865 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD2FIFOS) }, /* ISD2 FIFO Size */
866 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD2FMT) }, /* ISD2 Format */
867 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD2BDPL) }, /* ISD2 Buffer Descriptor List Pointer-Lower Base Address */
868 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD2BDPU) }, /* ISD2 Buffer Descriptor List Pointer-Upper Base Address */
869
870 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , IA(SD3CTL) }, /* Input Stream Descriptor 3 (ISD3) Control */
871 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , IA(SD3STS) }, /* ISD3 Status */
872 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3LPIB) }, /* ISD3 Link Position In Buffer */
873 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , IA(SD3CBL) }, /* ISD3 Cyclic Buffer Length */
874 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , IA(SD3LVI) }, /* ISD3 Last Valid Index */
875 { 0x000EE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , IA(SD3FIFOW) }, /* ISD3 FIFO Watermark */
876 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , IA(SD3FIFOS) }, /* ISD3 FIFO Size */
877 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , IA(SD3FMT) }, /* ISD3 Format */
878 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , IA(SD3BDPL) }, /* ISD3 Buffer Descriptor List Pointer-Lower Base Address */
879 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , IA(SD3BDPU) }, /* ISD3 Buffer Descriptor List Pointer-Upper Base Address */
880
881 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD4CTL) }, /* Output Stream Descriptor 4 (OSD4) Control */
882 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD4STS) }, /* OSD4 Status */
883 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4LPIB) }, /* OSD4 Link Position In Buffer */
884 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD4CBL) }, /* OSD4 Cyclic Buffer Length */
885 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD4LVI) }, /* OSD4 Last Valid Index */
886 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD4FIFOW) }, /* OSD4 FIFO Watermark */
887 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD4FIFOS) }, /* OSD4 FIFO Size */
888 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD4FMT) }, /* OSD4 Format */
889 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD4BDPL) }, /* OSD4 Buffer Descriptor List Pointer-Lower Base Address */
890 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD4BDPU) }, /* OSD4 Buffer Descriptor List Pointer-Upper Base Address */
891
892 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD5CTL) }, /* Output Stream Descriptor 5 (OSD5) Control */
893 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD5STS) }, /* OSD5 Status */
894 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5LPIB) }, /* OSD5 Link Position In Buffer */
895 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD5CBL) }, /* OSD5 Cyclic Buffer Length */
896 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD5LVI) }, /* OSD5 Last Valid Index */
897 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD5FIFOW) }, /* OSD5 FIFO Watermark */
898 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD5FIFOS) }, /* OSD5 FIFO Size */
899 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD5FMT) }, /* OSD5 Format */
900 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD5BDPL) }, /* OSD5 Buffer Descriptor List Pointer-Lower Base Address */
901 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD5BDPU) }, /* OSD5 Buffer Descriptor List Pointer-Upper Base Address */
902
903 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD6CTL) }, /* Output Stream Descriptor 6 (OSD6) Control */
904 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD6STS) }, /* OSD6 Status */
905 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6LPIB) }, /* OSD6 Link Position In Buffer */
906 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD6CBL) }, /* OSD6 Cyclic Buffer Length */
907 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD6LVI) }, /* OSD6 Last Valid Index */
908 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD6FIFOW) }, /* OSD6 FIFO Watermark */
909 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD6FIFOS) }, /* OSD6 FIFO Size */
910 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD6FMT) }, /* OSD6 Format */
911 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD6BDPL) }, /* OSD6 Buffer Descriptor List Pointer-Lower Base Address */
912 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD6BDPU) }, /* OSD6 Buffer Descriptor List Pointer-Upper Base Address */
913
914 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , OA(SD7CTL) }, /* Output Stream Descriptor 7 (OSD7) Control */
915 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , OA(SD7STS) }, /* OSD7 Status */
916 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7LPIB) }, /* OSD7 Link Position In Buffer */
917 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , OA(SD7CBL) }, /* OSD7 Cyclic Buffer Length */
918 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , OA(SD7LVI) }, /* OSD7 Last Valid Index */
919 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , OA(SD7FIFOW) }, /* OSD7 FIFO Watermark */
920 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , OA(SD7FIFOS) }, /* OSD7 FIFO Size */
921 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , OA(SD7FMT) }, /* OSD7 Format */
922 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , OA(SD7BDPL) }, /* OSD7 Buffer Descriptor List Pointer-Lower Base Address */
923 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , OA(SD7BDPU) }, /* OSD7 Buffer Descriptor List Pointer-Upper Base Address */
924};
925
926/**
927 * HDA register aliases (HDA spec 3.3.45).
928 * @remarks Sorted by offReg.
929 */
930static const struct
931{
932 /** The alias register offset. */
933 uint32_t offReg;
934 /** The register index. */
935 int idxAlias;
936} g_aHdaRegAliases[] =
937{
938 { 0x2084, HDA_REG_SD0LPIB },
939 { 0x20a4, HDA_REG_SD1LPIB },
940 { 0x20c4, HDA_REG_SD2LPIB },
941 { 0x20e4, HDA_REG_SD3LPIB },
942 { 0x2104, HDA_REG_SD4LPIB },
943 { 0x2124, HDA_REG_SD5LPIB },
944 { 0x2144, HDA_REG_SD6LPIB },
945 { 0x2164, HDA_REG_SD7LPIB },
946};
947
948#ifdef IN_RING3
949/** HDABDLEDESC field descriptors the v3+ saved state. */
950static SSMFIELD const g_aHdaBDLEDescFields[] =
951{
952 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
953 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
954 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
955 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
956 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
957 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
958 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
959 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
960 SSMFIELD_ENTRY_TERM()
961};
962
963/** HDABDLEDESC field descriptors the v1 and v2 saved state. */
964static SSMFIELD const g_aHdaBDLEDescFieldsOld[] =
965{
966 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
967 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
968 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
969 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
970 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
971 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
972 SSMFIELD_ENTRY_PAD_HC_AUTO(3, 3),
973 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
974 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
975 SSMFIELD_ENTRY_TERM()
976};
977#endif
978
979/**
980 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
981 */
982static uint32_t const g_afMasks[5] =
983{
984 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
985};
986
987#ifdef IN_RING3
988DECLINLINE(void) hdaUpdatePosBuf(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
989{
990 if (pThis->u64DPBase & DPBASE_ENABLED)
991 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
992 (pThis->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm * 8,
993 pStreamDesc->pu32Lpib, sizeof(uint32_t));
994}
995#endif
996
997DECLINLINE(uint32_t) hdaFifoWToSz(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
998{
999#if 0
1000 switch(HDA_STREAM_REG(pThis, FIFOW, pStreamDesc->u8Strm))
1001 {
1002 case HDA_SDFIFOW_8B: return 8;
1003 case HDA_SDFIFOW_16B: return 16;
1004 case HDA_SDFIFOW_32B: return 32;
1005 default:
1006 AssertMsgFailed(("unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pThis, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
1007 }
1008#endif
1009 return 0;
1010}
1011
1012static int hdaProcessInterrupt(PHDASTATE pThis)
1013{
1014#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
1015 ( INTCTL_SX((pThis), num) \
1016 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1017 bool fIrq = false;
1018 if ( HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE)
1019 && ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1020 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1021 || (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))))
1022 fIrq = true;
1023
1024 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
1025 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
1026 fIrq = true;
1027
1028 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1029 {
1030 LogFunc(("irq %s\n", fIrq ? "asserted" : "deasserted"));
1031 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0 , fIrq);
1032 }
1033 return VINF_SUCCESS;
1034}
1035
1036/**
1037 * Looks up a register at the exact offset given by @a offReg.
1038 *
1039 * @returns Register index on success, -1 if not found.
1040 * @param pThis The HDA device state.
1041 * @param offReg The register offset.
1042 */
1043static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
1044{
1045 /*
1046 * Aliases.
1047 */
1048 if (offReg >= g_aHdaRegAliases[0].offReg)
1049 {
1050 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1051 if (offReg == g_aHdaRegAliases[i].offReg)
1052 return g_aHdaRegAliases[i].idxAlias;
1053 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1054 return -1;
1055 }
1056
1057 /*
1058 * Binary search the
1059 */
1060 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1061 int idxLow = 0;
1062 for (;;)
1063 {
1064 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1065 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1066 {
1067 if (idxLow == idxMiddle)
1068 break;
1069 idxEnd = idxMiddle;
1070 }
1071 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1072 {
1073 idxLow = idxMiddle + 1;
1074 if (idxLow >= idxEnd)
1075 break;
1076 }
1077 else
1078 return idxMiddle;
1079 }
1080
1081#ifdef RT_STRICT
1082 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1083 Assert(g_aHdaRegMap[i].offset != offReg);
1084#endif
1085 return -1;
1086}
1087
1088/**
1089 * Looks up a register covering the offset given by @a offReg.
1090 *
1091 * @returns Register index on success, -1 if not found.
1092 * @param pThis The HDA device state.
1093 * @param offReg The register offset.
1094 */
1095static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
1096{
1097 /*
1098 * Aliases.
1099 */
1100 if (offReg >= g_aHdaRegAliases[0].offReg)
1101 {
1102 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1103 {
1104 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1105 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1106 return g_aHdaRegAliases[i].idxAlias;
1107 }
1108 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1109 return -1;
1110 }
1111
1112 /*
1113 * Binary search the
1114 */
1115 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1116 int idxLow = 0;
1117 for (;;)
1118 {
1119 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1120 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1121 {
1122 if (idxLow == idxMiddle)
1123 break;
1124 idxEnd = idxMiddle;
1125 }
1126 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1127 {
1128 idxLow = idxMiddle + 1;
1129 if (idxLow >= idxEnd)
1130 break;
1131 }
1132 else
1133 return idxMiddle;
1134 }
1135
1136#ifdef RT_STRICT
1137 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1138 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1139#endif
1140 return -1;
1141}
1142
1143#ifdef IN_RING3
1144static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1145{
1146 int rc = VINF_SUCCESS;
1147 if (fLocal)
1148 {
1149 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1150 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1151 if (RT_FAILURE(rc))
1152 AssertRCReturn(rc, rc);
1153#ifdef DEBUG_CMD_BUFFER
1154 uint8_t i = 0;
1155 do
1156 {
1157 LogFunc(("corb%02x: ", i));
1158 uint8_t j = 0;
1159 do
1160 {
1161 const char *prefix;
1162 if ((i + j) == HDA_REG(pThis, CORBRP);
1163 prefix = "[R]";
1164 else if ((i + j) == HDA_REG(pThis, CORBWP);
1165 prefix = "[W]";
1166 else
1167 prefix = " "; /* three spaces */
1168 LogFunc(("%s%08x", prefix, pThis->pu32CorbBuf[i + j]));
1169 j++;
1170 } while (j < 8);
1171 LogFunc(("\n"));
1172 i += 8;
1173 } while(i != 0);
1174#endif
1175 }
1176 else
1177 {
1178 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1179 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1180 if (RT_FAILURE(rc))
1181 AssertRCReturn(rc, rc);
1182#ifdef DEBUG_CMD_BUFFER
1183 uint8_t i = 0;
1184 do {
1185 LogFunc(("rirb%02x: ", i));
1186 uint8_t j = 0;
1187 do {
1188 const char *prefix;
1189 if ((i + j) == HDA_REG(pThis, RIRBWP))
1190 prefix = "[W]";
1191 else
1192 prefix = " ";
1193 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1194 } while (++j < 8);
1195 LogFunc(("\n"));
1196 i += 8;
1197 } while (i != 0);
1198#endif
1199 }
1200 return rc;
1201}
1202
1203static int hdaCORBCmdProcess(PHDASTATE pThis)
1204{
1205 int rc;
1206 uint8_t corbRp;
1207 uint8_t corbWp;
1208 uint8_t rirbWp;
1209
1210 PFNHDACODECVERBPROCESSOR pfn = (PFNHDACODECVERBPROCESSOR)NULL;
1211
1212 rc = hdaCmdSync(pThis, true);
1213 if (RT_FAILURE(rc))
1214 AssertRCReturn(rc, rc);
1215 corbRp = HDA_REG(pThis, CORBRP);
1216 corbWp = HDA_REG(pThis, CORBWP);
1217 rirbWp = HDA_REG(pThis, RIRBWP);
1218 Assert((corbWp != corbRp));
1219 LogFlowFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1220 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1221 while (corbRp != corbWp)
1222 {
1223 uint32_t cmd;
1224 uint64_t resp;
1225 pfn = NULL;
1226 corbRp++;
1227 cmd = pThis->pu32CorbBuf[corbRp];
1228
1229 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
1230 HDA_CODEC_CMD(cmd, 0 /* Codec index */),
1231 &pfn);
1232 if (RT_SUCCESS(rc))
1233 {
1234 rc = pfn(pThis->pCodec,
1235 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1236 }
1237
1238 if (RT_FAILURE(rc))
1239 AssertRCReturn(rc, rc);
1240 Assert(pfn);
1241 (rirbWp)++;
1242
1243 LogFunc(("verb:%08x->%016lx\n", cmd, resp));
1244 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
1245 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1246 {
1247 LogFunc(("unexpected unsolicited response.\n"));
1248 HDA_REG(pThis, CORBRP) = corbRp;
1249 return rc;
1250 }
1251 pThis->pu64RirbBuf[rirbWp] = resp;
1252 pThis->u8Counter++;
1253 if (pThis->u8Counter == RINTCNT_N(pThis))
1254 break;
1255 }
1256 HDA_REG(pThis, CORBRP) = corbRp;
1257 HDA_REG(pThis, RIRBWP) = rirbWp;
1258 rc = hdaCmdSync(pThis, false);
1259 LogFunc(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP),
1260 HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1261 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1262 {
1263 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1264 pThis->u8Counter = 0;
1265 rc = hdaProcessInterrupt(pThis);
1266 }
1267 if (RT_FAILURE(rc))
1268 AssertRCReturn(rc, rc);
1269 return rc;
1270}
1271#endif
1272
1273static void hdaStreamReset(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
1274{
1275 LogFunc(("reset of stream (%d) started\n", u8Strm));
1276 Assert(( pThis
1277 && pBdle
1278 && pStreamDesc
1279 && u8Strm <= 7));
1280 RT_BZERO(pBdle, sizeof(HDABDLEDESC));
1281 *pStreamDesc->pu32Lpib = 0;
1282 *pStreamDesc->pu32Sts = 0;
1283 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1284 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
1285 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1286
1287 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
1288 HDA_STREAM_REG(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
1289 HDA_STREAM_REG(pThis, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
1290 HDA_STREAM_REG(pThis, CBL, u8Strm) = 0;
1291 HDA_STREAM_REG(pThis, LVI, u8Strm) = 0;
1292 HDA_STREAM_REG(pThis, FMT, u8Strm) = 0;
1293 HDA_STREAM_REG(pThis, BDPU, u8Strm) = 0;
1294 HDA_STREAM_REG(pThis, BDPL, u8Strm) = 0;
1295 LogFunc(("reset of stream (%d) finished\n", u8Strm));
1296}
1297
1298/* Register access handlers. */
1299
1300static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1301{
1302 *pu32Value = 0;
1303 return VINF_SUCCESS;
1304}
1305
1306static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1307{
1308 return VINF_SUCCESS;
1309}
1310
1311/* U8 */
1312static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1313{
1314 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1315 return hdaRegReadU32(pThis, iReg, pu32Value);
1316}
1317
1318static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1319{
1320 Assert((u32Value & 0xffffff00) == 0);
1321 return hdaRegWriteU32(pThis, iReg, u32Value);
1322}
1323
1324/* U16 */
1325static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1326{
1327 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1328 return hdaRegReadU32(pThis, iReg, pu32Value);
1329}
1330
1331static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1332{
1333 Assert((u32Value & 0xffff0000) == 0);
1334 return hdaRegWriteU32(pThis, iReg, u32Value);
1335}
1336
1337/* U24 */
1338static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1339{
1340 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
1341 return hdaRegReadU32(pThis, iReg, pu32Value);
1342}
1343
1344static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1345{
1346 Assert((u32Value & 0xff000000) == 0);
1347 return hdaRegWriteU32(pThis, iReg, u32Value);
1348}
1349
1350/* U32 */
1351static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1352{
1353 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1354
1355 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
1356 return VINF_SUCCESS;
1357}
1358
1359static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1360{
1361 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1362
1363 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
1364 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
1365 return VINF_SUCCESS;
1366}
1367
1368static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1369{
1370 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1371 {
1372 /* exit reset state */
1373 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1374 pThis->fInReset = false;
1375 }
1376 else
1377 {
1378#ifdef IN_RING3
1379 /* enter reset state*/
1380 if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
1381 || HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
1382 {
1383 LogFunc(("HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1384 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
1385 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
1386 }
1387 hdaReset(pThis->CTX_SUFF(pDevIns));
1388 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1389 pThis->fInReset = true;
1390#else
1391 return VINF_IOM_R3_MMIO_WRITE;
1392#endif
1393 }
1394 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1395 {
1396 /* Flush: GSTS:1 set, see 6.2.6*/
1397 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
1398 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6)*/
1399 }
1400 return VINF_SUCCESS;
1401}
1402
1403static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1404{
1405 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1406
1407 uint32_t v = pThis->au32Regs[iRegMem];
1408 uint32_t nv = u32Value & HDA_STATES_SCSF;
1409 pThis->au32Regs[iRegMem] &= ~(v & nv); /* write of 1 clears corresponding bit */
1410 return VINF_SUCCESS;
1411}
1412
1413static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1414{
1415 uint32_t v = 0;
1416 if ( HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1417 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1418 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
1419 || HDA_REG(pThis, STATESTS))
1420 v |= RT_BIT(30);
1421#define HDA_IS_STREAM_EVENT(pThis, stream) \
1422 ( (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1423 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1424 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1425#define MARK_STREAM(pThis, stream, v) do { (v) |= HDA_IS_STREAM_EVENT((pThis),stream) ? RT_BIT((stream)) : 0; } while(0)
1426 MARK_STREAM(pThis, 0, v);
1427 MARK_STREAM(pThis, 1, v);
1428 MARK_STREAM(pThis, 2, v);
1429 MARK_STREAM(pThis, 3, v);
1430 MARK_STREAM(pThis, 4, v);
1431 MARK_STREAM(pThis, 5, v);
1432 MARK_STREAM(pThis, 6, v);
1433 MARK_STREAM(pThis, 7, v);
1434 v |= v ? RT_BIT(31) : 0;
1435 *pu32Value = v;
1436 return VINF_SUCCESS;
1437}
1438
1439static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1440{
1441 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1442 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
1443 - pThis->u64BaseTS, 24, 1000);
1444 return VINF_SUCCESS;
1445}
1446
1447static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1448{
1449 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1450 HDA_REG(pThis, CORBRP) = 0;
1451#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
1452 else
1453 return hdaRegWriteU8(pThis, iReg, u32Value);
1454#endif
1455 return VINF_SUCCESS;
1456}
1457
1458static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1459{
1460#ifdef IN_RING3
1461 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1462 AssertRC(rc);
1463 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1464 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
1465 return hdaCORBCmdProcess(pThis);
1466 return rc;
1467#else
1468 return VINF_IOM_R3_MMIO_WRITE;
1469#endif
1470}
1471
1472static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1473{
1474 uint32_t v = HDA_REG(pThis, CORBSTS);
1475 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1476 return VINF_SUCCESS;
1477}
1478
1479static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1480{
1481#ifdef IN_RING3
1482 int rc;
1483 rc = hdaRegWriteU16(pThis, iReg, u32Value);
1484 if (RT_FAILURE(rc))
1485 AssertRCReturn(rc, rc);
1486 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
1487 return VINF_SUCCESS;
1488 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1489 return VINF_SUCCESS;
1490 rc = hdaCORBCmdProcess(pThis);
1491 return rc;
1492#else
1493 return VINF_IOM_R3_MMIO_WRITE;
1494#endif
1495}
1496
1497static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1498{
1499 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1500 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1501 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1502 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1503
1504 if (fInReset)
1505 {
1506 /*
1507 * Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1508 * from reset
1509 */
1510 Assert((!fReset));
1511 LogFunc(("guest initiated exit of stream reset.\n"));
1512 }
1513 else if (fReset)
1514 {
1515#ifdef IN_RING3
1516 /*
1517 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1518 */
1519 uint8_t u8Strm = 0;
1520 PHDABDLEDESC pBdle = NULL;
1521 HDASTREAMTRANSFERDESC StreamDesc;
1522 Assert((!fInRun && !fRun));
1523 switch (iReg)
1524 {
1525 case HDA_REG_SD0CTL:
1526 u8Strm = 0;
1527 pBdle = &pThis->StInBdle;
1528 break;
1529#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1530# ifdef VBOX_WITH_HDA_MIC_IN
1531 case HDA_REG_SD2CTL:
1532 u8Strm = 2;
1533 pBdle = &pThis->StMicBdle;
1534 break;
1535# endif
1536#endif
1537 case HDA_REG_SD4CTL:
1538 u8Strm = 4;
1539 pBdle = &pThis->StOutBdle;
1540 break;
1541 default:
1542 LogFunc(("changing SRST bit on non-attached stream\n"));
1543 return hdaRegWriteU24(pThis, iReg, u32Value);
1544 }
1545 LogFunc(("guest initiated enter to stream reset.\n"));
1546 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
1547 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
1548#else
1549 return VINF_IOM_R3_MMIO_WRITE;
1550#endif
1551 }
1552 else
1553 {
1554#ifdef IN_RING3
1555 /* we enter here to change DMA states only */
1556 if ( (fInRun && !fRun)
1557 || (fRun && !fInRun))
1558 {
1559 Assert((!fReset && !fInReset));
1560
1561# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1562 PHDADRIVER pDrv;
1563# endif
1564 switch (iReg)
1565 {
1566 case HDA_REG_SD0CTL:
1567# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1568 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1569 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1570 pDrv->LineIn.pStrmIn, fRun);
1571# else
1572 AUD_set_active_in(pThis->pCodec->SwVoiceIn, fRun);
1573# endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1574 break;
1575# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1576# ifdef VBOX_WITH_HDA_MIC_IN
1577 case HDA_REG_SD2CTL:
1578 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1579 pDrv->pConnector->pfnEnableIn(pDrv->pConnector,
1580 pDrv->MicIn.pStrmIn, fRun);
1581# endif
1582# endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1583 break;
1584 case HDA_REG_SD4CTL:
1585# ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1586 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1587 pDrv->pConnector->pfnEnableOut(pDrv->pConnector,
1588 pDrv->Out.pStrmOut, fRun);
1589# else
1590 AUD_set_active_out(pThis->pCodec->SwVoiceOut, fRun);
1591# endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1592 break;
1593 default:
1594 AssertMsgFailed(("Changing RUN bit on non-attached stream, register %RU32\n", iReg));
1595 break;
1596 }
1597 }
1598#else /* !IN_RING3 */
1599 return VINF_IOM_R3_MMIO_WRITE;
1600#endif /* IN_RING3 */
1601 }
1602
1603 return hdaRegWriteU24(pThis, iReg, u32Value);
1604}
1605
1606static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1607{
1608 uint32_t v = HDA_REG_IND(pThis, iReg);
1609 v &= ~(u32Value & v);
1610 HDA_REG_IND(pThis, iReg) = v;
1611 hdaProcessInterrupt(pThis);
1612 return VINF_SUCCESS;
1613}
1614
1615static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1616{
1617 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1618 if (RT_FAILURE(rc))
1619 AssertRCReturn(rc, VINF_SUCCESS);
1620 return rc;
1621}
1622
1623static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1624{
1625 switch (u32Value)
1626 {
1627 case HDA_SDFIFOW_8B:
1628 case HDA_SDFIFOW_16B:
1629 case HDA_SDFIFOW_32B:
1630 return hdaRegWriteU16(pThis, iReg, u32Value);
1631 default:
1632 LogFunc(("Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1633 return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);
1634 }
1635 return VINF_SUCCESS;
1636}
1637
1638/**
1639 * @note This method could be called for changing value on Output Streams
1640 * only (ICH6 datasheet 18.2.39)
1641 */
1642static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1643{
1644 switch (iReg)
1645 {
1646 /* SDInFIFOS is RO, n=0-3 */
1647 case HDA_REG_SD0FIFOS:
1648 case HDA_REG_SD1FIFOS:
1649 case HDA_REG_SD2FIFOS:
1650 case HDA_REG_SD3FIFOS:
1651 LogFunc(("Guest tries change value of FIFO size of input stream\n"));
1652 break;
1653 case HDA_REG_SD4FIFOS:
1654 case HDA_REG_SD5FIFOS:
1655 case HDA_REG_SD6FIFOS:
1656 case HDA_REG_SD7FIFOS:
1657 switch(u32Value)
1658 {
1659 case HDA_SDONFIFO_16B:
1660 case HDA_SDONFIFO_32B:
1661 case HDA_SDONFIFO_64B:
1662 case HDA_SDONFIFO_128B:
1663 case HDA_SDONFIFO_192B:
1664 return hdaRegWriteU16(pThis, iReg, u32Value);
1665
1666 case HDA_SDONFIFO_256B:
1667 LogFunc(("256-bit is unsupported, HDA is switched into 192-bit mode\n"));
1668 default:
1669 return hdaRegWriteU16(pThis, iReg, HDA_SDONFIFO_192B);
1670 }
1671 break;
1672 default:
1673 AssertMsgFailed(("Something weird happened with register lookup routine\n"));
1674 }
1675
1676 return VINF_SUCCESS;
1677}
1678
1679#ifdef IN_RING3
1680#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1681static int hdaSdFmtToAudSettings(uint32_t u32SdFmt, PPDMAUDIOSTREAMCFG pCfg)
1682#else
1683static int hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pCfg)
1684#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1685{
1686 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1687
1688# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1689
1690 int rc = VINF_SUCCESS;
1691
1692 uint32_t u32Hz = (u32SdFmt & HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1693 uint32_t u32HzMult = 1;
1694 uint32_t u32HzDiv = 1;
1695
1696 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
1697 {
1698 case 0: u32HzMult = 1; break;
1699 case 1: u32HzMult = 2; break;
1700 case 2: u32HzMult = 3; break;
1701 case 3: u32HzMult = 4; break;
1702 default:
1703 LogFunc(("Unsupported multiplier %x\n",
1704 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
1705 rc = VERR_NOT_SUPPORTED;
1706 break;
1707 }
1708 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
1709 {
1710 case 0: u32HzDiv = 1; break;
1711 case 1: u32HzDiv = 2; break;
1712 case 2: u32HzDiv = 3; break;
1713 case 3: u32HzDiv = 4; break;
1714 case 4: u32HzDiv = 5; break;
1715 case 5: u32HzDiv = 6; break;
1716 case 6: u32HzDiv = 7; break;
1717 case 7: u32HzDiv = 8; break;
1718 default:
1719 LogFunc(("Unsupported divisor %x\n",
1720 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
1721 rc = VERR_NOT_SUPPORTED;
1722 break;
1723 }
1724
1725#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1726 PDMAUDIOFMT enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
1727#else
1728 audfmt_e enmFmt = AUD_FMT_S16; /* Default to 16-bit signed. */
1729#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1730
1731 switch (EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
1732 {
1733 case 0:
1734 LogFunc(("%s requested 8-bit\n", __FUNCTION__));
1735#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1736 enmFmt = AUD_FMT_S8;
1737#else
1738 enmFmt = AUD_FMT_S8;
1739#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1740 break;
1741 case 1:
1742 LogFunc(("%s requested 16-bit\n", __FUNCTION__));
1743#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1744 enmFmt = AUD_FMT_S16;
1745#else
1746 enmFmt = AUD_FMT_S16;
1747#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1748 break;
1749 case 2:
1750 LogFunc(("%s requested 20-bit\n", __FUNCTION__));
1751 break;
1752 case 3:
1753 LogFunc(("%s requested 24-bit\n", __FUNCTION__));
1754 break;
1755 case 4:
1756 LogFunc(("%s requested 32-bit\n", __FUNCTION__));
1757#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1758 enmFmt = AUD_FMT_S32;
1759#else
1760 enmFmt = AUD_FMT_S32;
1761#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1762 break;
1763 default:
1764 AssertMsgFailed(("Unsupported bits shift %x\n",
1765 EXTRACT_VALUE(u32SdFmt, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
1766 rc = VERR_NOT_SUPPORTED;
1767 break;
1768 }
1769
1770 if (RT_SUCCESS(rc))
1771 {
1772#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1773 pCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
1774 pCfg->cChannels = (u32SdFmt & 0xf) + 1;
1775 pCfg->enmFormat = enmFmt;
1776 pCfg->enmEndianness = PDMAUDIOHOSTENDIANESS;
1777#else
1778 pCfg->nchannels = (u32SdFmt & 0xf) + 1;
1779 pCfg->fmt = enmFmt;
1780 pCfg->endianness = 0;
1781#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
1782 }
1783
1784# undef EXTRACT_VALUE
1785
1786 return rc;
1787}
1788#endif
1789
1790static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1791{
1792#ifdef IN_RING3
1793# ifdef VBOX_WITH_HDA_CODEC_EMU
1794 /* No reason to reopen voice with same settings. */
1795 if (u32Value == HDA_REG_IND(pThis, iReg))
1796 return VINF_SUCCESS;
1797
1798 PDMAUDIOSTREAMCFG as;
1799 int rc = hdaSdFmtToAudSettings(u32Value, &as);
1800 if (RT_FAILURE(rc))
1801 return rc;
1802
1803 PHDADRIVER pDrv;
1804 switch (iReg)
1805 {
1806 case HDA_REG_SD0FMT:
1807 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1808 rc = hdaCodecOpenStream(pThis->pCodec, PI_INDEX, &as);
1809 break;
1810#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
1811# ifdef VBOX_WITH_HDA_MIC_IN
1812 case HDA_REG_SD2FMT:
1813 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
1814 rc = hdaCodecOpenStream(pThis->pCodec, MC_INDEX, &as);
1815 break;
1816# endif
1817#endif
1818 default:
1819 LogFunc(("Warning: Attempt to change format on register %d\n", iReg));
1820 break;
1821 }
1822
1823 /** @todo r=andy rc gets lost; needs fixing. */
1824 return hdaRegWriteU16(pThis, iReg, u32Value);
1825# else
1826 return hdaRegWriteU16(pThis, iReg, u32Value);
1827# endif
1828#else
1829 return VINF_IOM_R3_MMIO_WRITE;
1830#endif
1831}
1832
1833static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1834{
1835 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1836 if (RT_FAILURE(rc))
1837 AssertRCReturn(rc, VINF_SUCCESS);
1838 return rc;
1839}
1840
1841static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1842{
1843 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1844 if (RT_FAILURE(rc))
1845 AssertRCReturn(rc, VINF_SUCCESS);
1846 return rc;
1847}
1848
1849static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1850{
1851 int rc = VINF_SUCCESS;
1852 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1853 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
1854 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1855 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1856
1857 rc = hdaRegReadU32(pThis, iReg, pu32Value);
1858 return rc;
1859}
1860
1861static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1862{
1863 int rc = VINF_SUCCESS;
1864
1865 /*
1866 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
1867 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
1868 */
1869 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1870 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
1871 {
1872#ifdef IN_RING3
1873 PFNHDACODECVERBPROCESSOR pfn = NULL;
1874 uint64_t resp;
1875 uint32_t cmd = HDA_REG(pThis, IC);
1876 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
1877 {
1878 /*
1879 * 3.4.3 defines behavior of immediate Command status register.
1880 */
1881 LogRel(("guest attempted process immediate verb (%x) with active CORB\n", cmd));
1882 return rc;
1883 }
1884 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1885 LogFunc(("IC:%x\n", cmd));
1886
1887 rc = pThis->pCodec->pfnLookup(pThis->pCodec,
1888 HDA_CODEC_CMD(cmd, 0 /* LUN */),
1889 &pfn);
1890 if (RT_FAILURE(rc))
1891 AssertRCReturn(rc, rc);
1892 rc = pfn(pThis->pCodec,
1893 HDA_CODEC_CMD(cmd, 0 /* LUN */), &resp);
1894 if (RT_FAILURE(rc))
1895 AssertRCReturn(rc, rc);
1896
1897 HDA_REG(pThis, IR) = (uint32_t)resp;
1898 LogFunc(("IR:%x\n", HDA_REG(pThis, IR)));
1899 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1900 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1901#else /* !IN_RING3 */
1902 rc = VINF_IOM_R3_MMIO_WRITE;
1903#endif
1904 return rc;
1905 }
1906 /*
1907 * Once the guest read the response, it should clean the IRV bit of the IRS register.
1908 */
1909 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1910 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
1911 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1912 return rc;
1913}
1914
1915static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1916{
1917 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1918 {
1919 HDA_REG(pThis, RIRBWP) = 0;
1920 }
1921 /* The remaining bits are O, see 6.2.22 */
1922 return VINF_SUCCESS;
1923}
1924
1925static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1926{
1927 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
1928 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1929 if (RT_FAILURE(rc))
1930 AssertRCReturn(rc, rc);
1931
1932 switch(iReg)
1933 {
1934 case HDA_REG_CORBLBASE:
1935 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
1936 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
1937 break;
1938 case HDA_REG_CORBUBASE:
1939 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
1940 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1941 break;
1942 case HDA_REG_RIRBLBASE:
1943 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
1944 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
1945 break;
1946 case HDA_REG_RIRBUBASE:
1947 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
1948 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1949 break;
1950 case HDA_REG_DPLBASE:
1951 /** @todo: first bit has special meaning */
1952 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
1953 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
1954 break;
1955 case HDA_REG_DPUBASE:
1956 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
1957 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
1958 break;
1959 default:
1960 AssertMsgFailed(("Invalid index"));
1961 break;
1962 }
1963
1964 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
1965 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
1966 return rc;
1967}
1968
1969static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1970{
1971 uint8_t v = HDA_REG(pThis, RIRBSTS);
1972 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
1973
1974 return hdaProcessInterrupt(pThis);
1975}
1976
1977#ifdef IN_RING3
1978#ifdef LOG_ENABLED
1979static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1980{
1981#if 0
1982 uint64_t addr;
1983 uint32_t len;
1984 uint32_t ioc;
1985 uint8_t bdle[16];
1986 uint32_t counter;
1987 uint32_t i;
1988 uint32_t sum = 0;
1989 Assert(pBdle && pBdle->u32BdleMaxCvi);
1990 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1991 {
1992 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i*16, bdle, 16);
1993 addr = *(uint64_t *)bdle;
1994 len = *(uint32_t *)&bdle[8];
1995 ioc = *(uint32_t *)&bdle[12];
1996 LogFunc(("%s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1997 sum += len;
1998 }
1999 LogFunc(("sum: %d\n", sum));
2000 for (i = 0; i < 8; ++i)
2001 {
2002 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
2003 LogFunc(("%s stream[%d] counter=%x\n", i == SDCTL_NUM(pThis, 4) || i == SDCTL_NUM(pThis, 0)? "[C]": " ",
2004 i , counter));
2005 }
2006#endif
2007}
2008#endif
2009
2010static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2011{
2012 uint8_t bdle[16];
2013 Assert(( pStreamDesc->u64BaseDMA
2014 && pBdle
2015 && pBdle->u32BdleMaxCvi));
2016 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
2017 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
2018 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
2019 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
2020#ifdef LOG_ENABLED
2021 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
2022#endif
2023}
2024
2025DECLINLINE(uint32_t) hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2026 uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
2027{
2028 /*
2029 * Number of bytes depends on the current position in buffer (u32BdleCviLen-u32BdleCviPos)
2030 */
2031 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
2032 uint32_t cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
2033 /*
2034 * we may increase the counter in range of [0, FIFOS + 1]
2035 */
2036 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
2037 Assert((u32SoundBackendBufferBytesAvail > 0));
2038
2039 /* sanity check to avoid overriding the backend audio buffer */
2040 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
2041 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
2042
2043 if (cb2Copy <= pBdle->cbUnderFifoW)
2044 return 0;
2045 cb2Copy -= pBdle->cbUnderFifoW; /* forcibly reserve the amount of unreported bytes to copy */
2046 return cb2Copy;
2047}
2048
2049DECLINLINE(void) hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
2050 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
2051{
2052 LogFunc(("cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2053 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
2054 Assert((cbCopied));
2055 AssertPtr(pu32DMACursor);
2056 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
2057 /* Assertion!!! Fewer than cbUnderFifoW bytes were copied.
2058 * Probably we need to move the buffer, but it is rather hard to imagine a situation
2059 * where it might happen.
2060 */
2061 AssertMsg((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy), /* we assume that we write the entire buffer including unreported bytes */
2062 ("cbCopied=%RU32 != pBdle->cbUnderFifoW=%RU32 + cbArranged2Copy=%RU32\n",
2063 cbCopied, pBdle->cbUnderFifoW, cbArranged2Copy));
2064 if ( pBdle->cbUnderFifoW
2065 && pBdle->cbUnderFifoW <= cbCopied)
2066 {
2067 LogFunc(("CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n",
2068 pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2069 }
2070
2071 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
2072 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Incorrect assumption */
2073
2074 /* We always increment the position of DMA buffer counter because we're always reading into an intermediate buffer */
2075 pBdle->u32BdleCviPos += cbArranged2Copy;
2076
2077 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
2078 /* We report all bytes (including previously unreported bytes) */
2079 *pu32DMACursor += cbCopied;
2080 /* Decrease the backend counter by the number of bytes we copied to the backend */
2081 *pu32BackendBufferCapacity -= cbCopied;
2082 LogFunc(("CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2083 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
2084}
2085
2086DECLINLINE(void) hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
2087 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
2088{
2089 Assert((cbCopied, cbArranged2Copy));
2090 *pu32BackendBufferCapacity -= cbCopied;
2091 pBdle->u32BdleCviPos += cbCopied;
2092 LogFunc(("CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2093 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
2094 pBdle->cbUnderFifoW = 0;
2095 LogFunc(("CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
2096 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
2097}
2098
2099DECLINLINE(void) hdaBackendTransferUnreported(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2100 uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
2101{
2102 LogFunc(("CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2103 pBdle->u32BdleCviPos += cbCopied;
2104 pBdle->cbUnderFifoW += cbCopied;
2105 /* In case of a read transaction we're always copying from the backend buffer */
2106 if (pu32BackendBufferCapacity)
2107 *pu32BackendBufferCapacity -= cbCopied;
2108 LogFunc(("CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2109 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pThis, pStreamDesc)));
2110}
2111
2112DECLINLINE(bool) hdaIsTransferCountersOverlapped(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2113{
2114 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
2115 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
2116
2117 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
2118
2119 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
2120 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
2121 hdaUpdatePosBuf(pThis, pStreamDesc);
2122
2123 /* don't touch BdleCvi counter on uninitialized descriptor */
2124 if ( pBdle->u32BdleCviPos
2125 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
2126 {
2127 pBdle->u32BdleCviPos = 0;
2128 pBdle->u32BdleCvi++;
2129 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
2130 pBdle->u32BdleCvi = 0;
2131 }
2132 return fOnBufferEdge;
2133}
2134
2135DECLINLINE(void) hdaStreamCounterUpdate(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
2136 uint32_t cbInc)
2137{
2138 /*
2139 * if we're below the FIFO Watermark, it's expected that HDA doesn't fetch anything.
2140 * (ICH6 datasheet 18.2.38)
2141 */
2142 if (!pBdle->cbUnderFifoW)
2143 {
2144 *pStreamDesc->pu32Lpib += cbInc;
2145
2146 /*
2147 * Assert. The buffer counters should never overlap.
2148 */
2149 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
2150
2151 hdaUpdatePosBuf(pThis, pStreamDesc);
2152 }
2153}
2154
2155static bool hdaDoNextTransferCycle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
2156{
2157 bool fDoNextTransferLoop = true;
2158 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
2159 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
2160 {
2161 if ( !pBdle->cbUnderFifoW
2162 && pBdle->fBdleCviIoc)
2163 {
2164 /**
2165 * @todo - more carefully investigate BCIS flag.
2166 * Speech synthesis works fine on Mac Guest if this bit isn't set
2167 * but in general sound quality gets worse.
2168 */
2169 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
2170
2171 /*
2172 * we should generate the interrupt if ICE bit of SDCTL register is set.
2173 */
2174 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
2175 hdaProcessInterrupt(pThis);
2176 }
2177 fDoNextTransferLoop = false;
2178 }
2179 return fDoNextTransferLoop;
2180}
2181
2182#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2183/**
2184 * hdaReadAudio - copies samples from audio backend to DMA.
2185 * Note: This function writes to the DMA buffer immediately,
2186 * but "reports bytes" when all conditions are met (FIFOW).
2187 */
2188static int hdaReadAudio(PHDASTATE pThis, PAUDMIXSINK pSink,
2189 PHDASTREAMTRANSFERDESC pStreamDesc,
2190 uint32_t u32CblLimit, uint32_t *pcbAvail, uint32_t *pcbRead)
2191{
2192 PHDABDLEDESC pBdle = &pThis->StInBdle; /** @todo Add support for mic in. */
2193
2194 int rc;
2195 uint32_t cbTransferred = 0;
2196
2197 LogFlowFunc(("CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2198
2199 uint32_t cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pcbAvail, u32CblLimit);
2200 if (!cb2Copy)
2201 {
2202 /* If we enter here we can't report "unreported bits". */
2203 rc = VERR_NO_DATA;
2204 }
2205 else
2206 {
2207 uint32_t cbRead = 0;
2208 rc = audioMixerProcessSinkIn(pSink, pBdle->au8HdaBuffer, cb2Copy, &cbRead);
2209 if (RT_SUCCESS(rc))
2210 {
2211 Assert(cbRead);
2212
2213 /*
2214 * Write the HDA DMA buffer.
2215 */
2216 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2217 pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos,
2218 pBdle->au8HdaBuffer, cbRead);
2219
2220 /* Don't see any reason why cb2Copy would differ from cbRead. */
2221 Assert((cbRead == cb2Copy && (*pcbAvail) >= cb2Copy)); /* sanity */
2222
2223 if (pBdle->cbUnderFifoW + cbRead > hdaFifoWToSz(pThis, 0))
2224 hdaBackendReadTransferReported(pBdle, cb2Copy, cbRead, &cbTransferred, pcbAvail);
2225 else
2226 {
2227 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cbRead, pcbAvail);
2228 rc = VERR_NO_DATA;
2229 }
2230 }
2231 }
2232
2233 Assert((cbTransferred <= (SDFIFOS(pThis, 0) + 1)));
2234 LogFunc(("CVI(pos:%RU32, len:%RU32), cbTransferred=%RU32, rc=%Rrc\n",
2235 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred, rc));
2236
2237 if (RT_SUCCESS(rc))
2238 *pcbRead = cbTransferred;
2239
2240 return rc;
2241}
2242#else
2243static int hdaReadAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc,
2244 uint32_t u32CblLimit, uint32_t *pu32Avail, uint32_t *pcbRead)
2245{
2246 PHDABDLEDESC pBdle = &pThis->StInBdle;
2247
2248 uint32_t cbTransferred = 0;
2249 uint32_t cb2Copy = 0;
2250 uint32_t cbBackendCopy = 0;
2251
2252 int rc;
2253
2254 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2255
2256 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
2257 if (!cb2Copy)
2258 {
2259 /* if we enter here we can't report "unreported bits" */
2260 rc = VINF_EOF;
2261 }
2262 else
2263 {
2264 /*
2265 * read from backend input line to the last unreported position or at the begining.
2266 */
2267 cbBackendCopy = AUD_read(pThis->pCodec->SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
2268
2269 /*
2270 * write the HDA DMA buffer
2271 */
2272 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer,
2273 cbBackendCopy);
2274
2275 /* Don't see any reason why cb2Copy would differ from cbBackendCopy */
2276 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
2277
2278 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pThis, 0))
2279 {
2280 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
2281 rc = VINF_SUCCESS;
2282 }
2283 else
2284 {
2285 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
2286 rc = VINF_EOF;
2287 }
2288 }
2289
2290 Assert((cbTransferred <= (SDFIFOS(pThis, 0) + 1)));
2291 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransferred: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
2292
2293 if (pcbRead)
2294 *pcbRead = cbTransferred;
2295
2296 return rc;
2297}
2298#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2299
2300static int hdaWriteAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t u32CblLimit,
2301 uint32_t *pcbAvail, uint32_t *pcbWritten)
2302{
2303 PHDABDLEDESC pBdle = &pThis->StOutBdle;
2304
2305 int rc = VINF_SUCCESS;
2306
2307 uint32_t cbTransferred = 0;
2308 uint32_t cbWrittenMin = 0; /* local byte counter, how many bytes copied to backend */
2309
2310 LogFunc(("CVI(cvi:%RU32, pos:%RU32, len:%RU32)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
2311
2312 /* Local byte counter (on local buffer). */
2313 uint32_t cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pcbAvail, u32CblLimit);
2314
2315 /*
2316 * Copy from DMA to the corresponding hdaBuffer (if there are any bytes from the
2317 * previous unreported transfer we write at offset 'pBdle->cbUnderFifoW').
2318 */
2319 if (!cb2Copy)
2320 {
2321 rc = VINF_EOF;
2322 }
2323 else
2324 {
2325 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2326 pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos,
2327 pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
2328#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2329 STAM_COUNTER_ADD(&pThis->StatBytesRead, cb2Copy);
2330#endif
2331
2332 /*
2333 * Write to audio backend. We should ensure that we have enough bytes to copy to the backend.
2334 */
2335 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pThis, pStreamDesc))
2336 {
2337#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2338 uint32_t cbWritten;
2339 cbWrittenMin = UINT32_MAX;
2340
2341 PHDADRIVER pDrv;
2342 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2343 {
2344 if (pDrv->pConnector->pfnIsActiveOut(pDrv->pConnector, pDrv->Out.pStrmOut))
2345 {
2346 int rc2 = pDrv->pConnector->pfnWrite(pDrv->pConnector, pDrv->Out.pStrmOut,
2347 pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW,
2348 &cbWritten);
2349 if (RT_FAILURE(rc2))
2350 continue;
2351 }
2352 else /* Stream disabled, just assume all was copied. */
2353 cbWritten = cb2Copy;
2354
2355 cbWrittenMin = RT_MIN(cbWrittenMin, cbWritten);
2356 LogFlowFunc(("\tLUN#%RU8: cbWritten=%RU32, cWrittenMin=%RU32\n", pDrv->uLUN, cbWritten, cbWrittenMin));
2357 }
2358
2359 if (cbWrittenMin == UINT32_MAX)
2360 cbWrittenMin = 0;
2361#else
2362 cbWrittenMin = AUD_write (pThis->pCodec->SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
2363#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2364
2365 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbWrittenMin, &cbTransferred, pcbAvail);
2366 }
2367 else
2368 {
2369 /* Not enough bytes to be processed and reported, we'll try our luck next time around. */
2370 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cb2Copy, NULL);
2371 rc = VINF_EOF;
2372 }
2373 }
2374
2375 Assert(cbTransferred <= SDFIFOS(pThis, 4) + 1);
2376 LogFunc(("CVI(pos:%RU32, len:%RU32, cbTransferred:%RU32), rc=%Rrc\n",
2377 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred, rc));
2378
2379 if (RT_SUCCESS(rc))
2380 *pcbWritten = cbTransferred;
2381
2382 return rc;
2383}
2384
2385/**
2386 * @interface_method_impl{HDACODEC,pfnReset}
2387 */
2388DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
2389{
2390 PHDASTATE pThis = pCodec->pHDAState;
2391 NOREF(pThis);
2392 return VINF_SUCCESS;
2393}
2394
2395DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
2396 PHDASTREAMTRANSFERDESC pStreamDesc)
2397{
2398 Assert(pThis); Assert(pBdle); Assert(pStreamDesc); Assert(u8Strm <= 7);
2399
2400 RT_BZERO(pStreamDesc, sizeof(HDASTREAMTRANSFERDESC));
2401 pStreamDesc->u8Strm = u8Strm;
2402 pStreamDesc->u32Ctl = HDA_STREAM_REG(pThis, CTL, u8Strm);
2403 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
2404 HDA_STREAM_REG(pThis, BDPU, u8Strm));
2405 pStreamDesc->pu32Lpib = &HDA_STREAM_REG(pThis, LPIB, u8Strm);
2406 pStreamDesc->pu32Sts = &HDA_STREAM_REG(pThis, STS, u8Strm);
2407 pStreamDesc->u32Cbl = HDA_STREAM_REG(pThis, CBL, u8Strm);
2408 pStreamDesc->u32Fifos = HDA_STREAM_REG(pThis, FIFOS, u8Strm);
2409
2410 pBdle->u32BdleMaxCvi = HDA_STREAM_REG(pThis, LVI, u8Strm);
2411
2412#ifdef LOG_ENABLED
2413 if ( pBdle
2414 && pBdle->u32BdleMaxCvi)
2415 {
2416 LogFunc(("Initialization of transfer descriptor:\n"));
2417 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
2418 }
2419#endif
2420}
2421
2422static DECLCALLBACK(void) hdaCloseIn(PHDASTATE pThis, PDMAUDIORECSOURCE enmRecSource)
2423{
2424 NOREF(pThis);
2425 NOREF(enmRecSource);
2426 LogFlowFuncEnter();
2427}
2428
2429static DECLCALLBACK(void) hdaCloseOut(PHDASTATE pThis)
2430{
2431 NOREF(pThis);
2432 LogFlowFuncEnter();
2433}
2434
2435#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2436static DECLCALLBACK(int) hdaOpenIn(PHDASTATE pThis,
2437 const char *pszName, PDMAUDIORECSOURCE enmRecSource,
2438 PPDMAUDIOSTREAMCFG pCfg)
2439{
2440 PAUDMIXSINK pSink;
2441
2442 switch (enmRecSource)
2443 {
2444# ifdef VBOX_WITH_HDA_MIC_IN
2445 case PDMAUDIORECSOURCE_MIC:
2446 pSink = pThis->pSinkMicIn;
2447 break;
2448# endif
2449 case PDMAUDIORECSOURCE_LINE_IN:
2450 pSink = pThis->pSinkLineIn;
2451 break;
2452 default:
2453 AssertMsgFailed(("Audio source %ld not supported\n", enmRecSource));
2454 return VERR_NOT_SUPPORTED;
2455 }
2456
2457 int rc;
2458 char *pszDesc;
2459
2460 PHDADRIVER pDrv;
2461 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2462 {
2463 if (RTStrAPrintf(&pszDesc, "[LUN#%RU8] %s", pDrv->uLUN, pszName) <= 0)
2464 {
2465 rc = VERR_NO_MEMORY;
2466 break;
2467 }
2468
2469 rc = pDrv->pConnector->pfnOpenIn(pDrv->pConnector, pszDesc, enmRecSource, pCfg, &pDrv->LineIn.pStrmIn);
2470 LogFlowFunc(("LUN#%RU8: Opened input \"%s\", with rc=%Rrc\n", pDrv->uLUN, pszDesc, rc));
2471 if (rc == VINF_SUCCESS) /* Note: Could return VWRN_ALREADY_EXISTS. */
2472 {
2473 audioMixerRemoveStream(pSink, pDrv->LineIn.phStrmIn);
2474 rc = audioMixerAddStreamIn(pSink,
2475 pDrv->pConnector, pDrv->LineIn.pStrmIn,
2476 0 /* uFlags */, &pDrv->LineIn.phStrmIn);
2477 }
2478
2479 RTStrFree(pszDesc);
2480 }
2481
2482 LogFlowFuncLeaveRC(rc);
2483 return rc;
2484}
2485
2486static DECLCALLBACK(int) hdaOpenOut(PHDASTATE pThis,
2487 const char *pszName, PPDMAUDIOSTREAMCFG pCfg)
2488{
2489 int rc = VINF_SUCCESS;
2490
2491 PHDADRIVER pDrv;
2492 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2493 {
2494 int rc2 = pDrv->pConnector->pfnOpenOut(pDrv->pConnector, pszName, pCfg, &pDrv->Out.pStrmOut);
2495 if (RT_FAILURE(rc2))
2496 {
2497 LogFunc(("LUN#%RU8: Opening stream \"%s\" failed, rc=%Rrc\n", pDrv->uLUN, pszName, rc2));
2498 if (RT_SUCCESS(rc))
2499 rc = rc2;
2500 /* Keep going. */
2501 }
2502 }
2503
2504 LogFlowFuncLeaveRC(rc);
2505 return rc;
2506}
2507
2508static DECLCALLBACK(int) hdaSetVolume(PHDASTATE pThis,
2509 bool fMute, uint8_t uVolLeft, uint8_t uVolRight)
2510{
2511 int rc = VINF_SUCCESS;
2512
2513 PHDADRIVER pDrv;
2514 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2515 {
2516 int rc2 = pDrv->pConnector->pfnSetVolume(pDrv->pConnector,
2517 fMute, uVolLeft, uVolRight);
2518 if (RT_FAILURE(rc2))
2519 {
2520 LogFunc(("Failed for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
2521 if (RT_SUCCESS(rc))
2522 rc = rc2;
2523 /* Keep going. */
2524 }
2525 }
2526
2527 LogFlowFuncLeaveRC(rc);
2528 return rc;
2529}
2530#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2531
2532#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2533static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2534{
2535 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2536 AssertPtr(pThis);
2537
2538 STAM_PROFILE_START(&pThis->StatTimer, a);
2539
2540 int rc = VINF_SUCCESS;
2541
2542 uint32_t cbInMax = 0;
2543 uint32_t cbOutMin = UINT32_MAX;
2544
2545 PHDADRIVER pDrv;
2546
2547 LogFlowFuncEnter();
2548
2549 uint32_t cbIn, cbOut, cSamplesLive;
2550 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2551 {
2552 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2553 &cbIn, &cbOut, &cSamplesLive);
2554 if (RT_SUCCESS(rc))
2555 {
2556 LogFlowFunc(("\tLUN#%RU8: [1] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2557
2558 if (cSamplesLive)
2559 {
2560 uint32_t cSamplesPlayed;
2561 int rc2 = pDrv->pConnector->pfnPlayOut(pDrv->pConnector, &cSamplesPlayed);
2562 if (RT_SUCCESS(rc2))
2563 LogFlowFunc(("LUN#%RU8: cSamplesLive=%RU32, cSamplesPlayed=%RU32\n",
2564 pDrv->uLUN, cSamplesLive, cSamplesPlayed));
2565
2566 rc = pDrv->pConnector->pfnQueryStatus(pDrv->pConnector,
2567 &cbIn, &cbOut, &cSamplesLive);
2568 if (RT_SUCCESS(rc))
2569 LogFlowFunc(("\tLUN#%RU8: [2] cbIn=%RU32, cbOut=%RU32\n", pDrv->uLUN, cbIn, cbOut));
2570 }
2571
2572 cbInMax = RT_MAX(cbInMax, cbIn);
2573 cbOutMin = RT_MIN(cbOutMin, cbOut);
2574 }
2575 }
2576
2577 LogFlowFunc(("cbInMax=%RU32, cbOutMin=%RU32\n", cbInMax, cbOutMin));
2578
2579 if (cbOutMin == UINT32_MAX)
2580 cbOutMin = 0;
2581
2582 /*
2583 * Playback.
2584 */
2585 if (cbOutMin)
2586 {
2587 Assert(cbOutMin != UINT32_MAX);
2588 hdaTransfer(pThis, PO_INDEX, cbOutMin); /** @todo Add rc! */
2589 }
2590
2591 /*
2592 * Recording.
2593 */
2594 if (cbInMax)
2595 hdaTransfer(pThis, PI_INDEX, cbInMax); /** @todo Add rc! */
2596
2597 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
2598
2599 LogFlowFuncLeave();
2600
2601 STAM_PROFILE_STOP(&pThis->StatTimer, a);
2602}
2603
2604static DECLCALLBACK(int) hdaTransfer(PHDASTATE pThis,
2605 ENMSOUNDSOURCE enmSrc, uint32_t cbAvail)
2606{
2607 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2608
2609 LogFlowFunc(("pThis=%p, cbAvail=%RU32\n", pThis, cbAvail));
2610#else
2611static DECLCALLBACK(int) hdaTransfer(PHDACODEC pCodec, ENMSOUNDSOURCE enmSrc, uint32_t cbAvail)
2612{
2613 AssertPtrReturn(pCodec, VERR_INVALID_POINTER);
2614 PHDASTATE pThis = pCodec->pHDAState;
2615 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2616#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2617 int rc;
2618
2619 uint8_t u8Strm;
2620 PHDABDLEDESC pBdle;
2621
2622 switch (enmSrc)
2623 {
2624 case PI_INDEX:
2625 {
2626 u8Strm = 0;
2627 pBdle = &pThis->StInBdle;
2628 break;
2629 }
2630
2631#ifdef VBOX_WITH_HDA_MIC_IN
2632 case MC_INDEX:
2633 {
2634 u8Strm = 2;
2635 pBdle = &pThis->StMicBdle;
2636 break;
2637 }
2638#endif
2639 case PO_INDEX:
2640 {
2641 u8Strm = 4;
2642 pBdle = &pThis->StOutBdle;
2643 break;
2644 }
2645
2646 default:
2647 AssertMsgFailed(("Unknown source index %ld\n", enmSrc));
2648 return VERR_NOT_SUPPORTED;
2649 }
2650
2651 HDASTREAMTRANSFERDESC StreamDesc;
2652 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
2653
2654 while (cbAvail)
2655 {
2656 Assert( (StreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
2657 && cbAvail
2658 && StreamDesc.u64BaseDMA);
2659
2660 /* Fetch the Buffer Descriptor Entry (BDE). */
2661 if (hdaIsTransferCountersOverlapped(pThis, pBdle, &StreamDesc))
2662 hdaFetchBdle(pThis, pBdle, &StreamDesc);
2663
2664 *StreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2665 Assert((StreamDesc.u32Cbl >= (*StreamDesc.pu32Lpib))); /* sanity */
2666 uint32_t u32CblLimit = StreamDesc.u32Cbl - (*StreamDesc.pu32Lpib);
2667 Assert((u32CblLimit > hdaFifoWToSz(pThis, &StreamDesc)));
2668
2669 LogFunc(("CBL=%RU32, LPIB=%RU32\n", StreamDesc.u32Cbl, *StreamDesc.pu32Lpib));
2670
2671#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2672 PAUDMIXSINK pSink;
2673#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2674 uint32_t cbWritten;
2675 switch (enmSrc)
2676 {
2677 case PI_INDEX:
2678#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2679 pSink = pThis->pSinkLineIn;
2680 rc = hdaReadAudio(pThis, pSink, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2681#else
2682 rc = hdaReadAudio(pThis, &StreamDesc, u32CblLimit, (uint32_t *)&cbAvail, &cbWritten);
2683#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2684 break;
2685 case PO_INDEX:
2686 rc = hdaWriteAudio(pThis, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2687 break;
2688#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
2689# ifdef VBOX_WITH_HDA_MIC_IN
2690 case MC_INDEX:
2691 pSink = pThis->pSinkMicIn;
2692 rc = hdaReadAudio(pThis, pSink, &StreamDesc, u32CblLimit, &cbAvail, &cbWritten);
2693 break;
2694# endif
2695#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
2696 default:
2697 AssertMsgFailed(("Unsupported source index %ld\n", enmSrc));
2698 rc = VERR_NOT_SUPPORTED;
2699 break;
2700 }
2701 Assert(cbWritten <= StreamDesc.u32Fifos + 1);
2702 *StreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2703
2704 /* Process end of buffer condition. */
2705 hdaStreamCounterUpdate(pThis, pBdle, &StreamDesc, cbWritten);
2706
2707 if (!hdaDoNextTransferCycle(pThis, pBdle, &StreamDesc))
2708 break;
2709
2710 if ( RT_FAILURE(rc)
2711 || rc == VINF_EOF) /* All data processed? */
2712 {
2713 break;
2714 }
2715 }
2716
2717 return rc;
2718}
2719#endif /* IN_RING3 */
2720
2721/* MMIO callbacks */
2722
2723/**
2724 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
2725 *
2726 * @note During implementation, we discovered so-called "forgotten" or "hole"
2727 * registers whose description is not listed in the RPM, datasheet, or
2728 * spec.
2729 */
2730PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2731{
2732 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2733 int rc;
2734
2735 /*
2736 * Look up and log.
2737 */
2738 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2739 int idxRegDsc = hdaRegLookup(pThis, offReg); /* Register descriptor index. */
2740#ifdef LOG_ENABLED
2741 unsigned const cbLog = cb;
2742 uint32_t offRegLog = offReg;
2743#endif
2744
2745 LogFunc(("offReg=%#x cb=%#x\n", offReg, cb));
2746#define NEW_READ_CODE
2747#ifdef NEW_READ_CODE
2748 Assert(cb == 4); Assert((offReg & 3) == 0);
2749
2750 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
2751 LogFunc(("access to registers except GCTL is blocked while reset\n"));
2752
2753 if (idxRegDsc == -1)
2754 LogRel(("Invalid read access @0x%x(of bytes:%d)\n", offReg, cb));
2755
2756 if (idxRegDsc != -1)
2757 {
2758 /* ASSUMES gapless DWORD at end of map. */
2759 if (g_aHdaRegMap[idxRegDsc].size == 4)
2760 {
2761 /*
2762 * Straight forward DWORD access.
2763 */
2764 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
2765 LogFunc(("read %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
2766 }
2767 else
2768 {
2769 /*
2770 * Multi register read (unless there are trailing gaps).
2771 * ASSUMES that only DWORD reads have sideeffects.
2772 */
2773 uint32_t u32Value = 0;
2774 unsigned cbLeft = 4;
2775 do
2776 {
2777 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
2778 uint32_t u32Tmp = 0;
2779
2780 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
2781 LogFunc(("read %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
2782 if (rc != VINF_SUCCESS)
2783 break;
2784 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
2785
2786 cbLeft -= cbReg;
2787 offReg += cbReg;
2788 idxRegDsc++;
2789 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
2790
2791 if (rc == VINF_SUCCESS)
2792 *(uint32_t *)pv = u32Value;
2793 else
2794 Assert(!IOM_SUCCESS(rc));
2795 }
2796 }
2797 else
2798 {
2799 rc = VINF_IOM_MMIO_UNUSED_FF;
2800 LogFunc(("hole at %x is accessed for read\n", offReg));
2801 }
2802#else
2803 if (idxRegDsc != -1)
2804 {
2805 /** @todo r=bird: Accesses crossing register boundraries aren't handled
2806 * right from what I can tell? If they are, please explain
2807 * what the rules are. */
2808 uint32_t mask = 0;
2809 uint32_t shift = (g_aHdaRegMap[idxRegDsc].offset - offReg) % sizeof(uint32_t) * 8;
2810 uint32_t u32Value = 0;
2811 switch(cb)
2812 {
2813 case 1: mask = 0x000000ff; break;
2814 case 2: mask = 0x0000ffff; break;
2815 case 4:
2816 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2817 case 8:
2818 mask = 0xffffffff;
2819 cb = 4;
2820 break;
2821 }
2822#if 0
2823 /* Cross-register access. Mac guest hits this assert doing assumption 4 byte access to 3 byte registers e.g. {I,O}SDnCTL
2824 */
2825 //Assert((cb <= g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset)));
2826 if (cb > g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset))
2827 {
2828 int off = cb - (g_aHdaRegMap[idxRegDsc].size - (offReg - g_aHdaRegMap[idxRegDsc].offset));
2829 rc = hdaMMIORead(pDevIns, pvUser, GCPhysAddr + cb - off, (char *)pv + cb - off, off);
2830 if (RT_FAILURE(rc))
2831 AssertRCReturn (rc, rc);
2832 }
2833 //Assert(((offReg - g_aHdaRegMap[idxRegDsc].offset) == 0));
2834#endif
2835 mask <<= shift;
2836 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Value);
2837 *(uint32_t *)pv |= (u32Value & mask);
2838 LogFunc(("read %s[%x/%x]\n", g_aHdaRegMap[idxRegDsc].abbrev, u32Value, *(uint32_t *)pv));
2839 }
2840 else
2841 {
2842 *(uint32_t *)pv = 0xFF;
2843 LogFunc(("hole at %x is accessed for read\n", offReg));
2844 rc = VINF_SUCCESS;
2845 }
2846#endif
2847
2848 /*
2849 * Log the outcome.
2850 */
2851#ifdef LOG_ENABLED
2852 if (cbLog == 4)
2853 LogFunc(("@%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
2854 else if (cbLog == 2)
2855 LogFunc(("@%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
2856 else if (cbLog == 1)
2857 LogFunc(("@%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
2858#endif
2859 return rc;
2860}
2861
2862
2863DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
2864{
2865 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
2866 LogFunc(("access to registers except GCTL is blocked while reset\n")); /** @todo where is this enforced? */
2867
2868 uint32_t idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2869#ifdef LOG_ENABLED
2870 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
2871#endif
2872 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
2873 LogFunc(("write %#x -> %s[%db]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
2874 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
2875 return rc;
2876}
2877
2878
2879/**
2880 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
2881 */
2882PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
2883{
2884 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2885 int rc;
2886
2887 /*
2888 * The behavior of accesses that aren't aligned on natural boundraries is
2889 * undefined. Just reject them outright.
2890 */
2891 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
2892 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
2893 if (GCPhysAddr & (cb - 1))
2894 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
2895
2896 /*
2897 * Look up and log the access.
2898 */
2899 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2900 int idxRegDsc = hdaRegLookup(pThis, offReg);
2901 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
2902 uint64_t u64Value;
2903 if (cb == 4) u64Value = *(uint32_t const *)pv;
2904 else if (cb == 2) u64Value = *(uint16_t const *)pv;
2905 else if (cb == 1) u64Value = *(uint8_t const *)pv;
2906 else if (cb == 8) u64Value = *(uint64_t const *)pv;
2907 else
2908 {
2909 u64Value = 0; /* shut up gcc. */
2910 AssertReleaseMsgFailed(("%d\n", cb));
2911 }
2912
2913#ifdef LOG_ENABLED
2914 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
2915 uint32_t const offRegLog = offReg;
2916 int const idxRegLog = idxRegMem;
2917 if (idxRegDsc == -1)
2918 LogFunc(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
2919 else if (cb == 4)
2920 LogFunc(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2921 else if (cb == 2)
2922 LogFunc(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2923 else if (cb == 1)
2924 LogFunc(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
2925 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
2926 LogFunc(("size=%d != cb=%d!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
2927#endif
2928
2929#define NEW_WRITE_CODE
2930#ifdef NEW_WRITE_CODE
2931 /*
2932 * Try for a direct hit first.
2933 */
2934 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
2935 {
2936 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
2937 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldValue,
2938 idxRegLog != -1 ? pThis->au32Regs[idxRegLog] : UINT32_MAX));
2939 }
2940 /*
2941 * Partial or multiple register access, loop thru the requested memory.
2942 */
2943 else
2944 {
2945 /* If it's an access beyond the start of the register, shift the input
2946 value and fill in missing bits. Natural alignment rules means we
2947 will only see 1 or 2 byte accesses of this kind, so no risk of
2948 shifting out input values. */
2949 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(pThis, offReg)) != -1)
2950 {
2951 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
2952 offReg -= cbBefore;
2953 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2954 u64Value <<= cbBefore * 8;
2955 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
2956 LogFunc(("Within register, supplied %u leading bits: %#llx -> %#llx ...\n",
2957 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
2958 }
2959
2960 /* Loop thru the write area, it may cover multiple registers. */
2961 rc = VINF_SUCCESS;
2962 for (;;)
2963 {
2964 uint32_t cbReg;
2965 if (idxRegDsc != -1)
2966 {
2967 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
2968 cbReg = g_aHdaRegMap[idxRegDsc].size;
2969 if (cb < cbReg)
2970 {
2971 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
2972 LogFunc(("Supplying missing bits (%#x): %#llx -> %#llx ...\n",
2973 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
2974 }
2975 uint32_t u32LogOldVal = pThis->au32Regs[idxRegMem];
2976 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
2977 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldVal,
2978 pThis->au32Regs[idxRegMem]));
2979 }
2980 else
2981 {
2982 LogRel(("HDA: Invalid write access @0x%x!\n", offReg));
2983 cbReg = 1;
2984 }
2985 if (rc != VINF_SUCCESS)
2986 break;
2987 if (cbReg >= cb)
2988 break;
2989
2990 /* advance */
2991 offReg += cbReg;
2992 cb -= cbReg;
2993 u64Value >>= cbReg * 8;
2994 if (idxRegDsc == -1)
2995 idxRegDsc = hdaRegLookup(pThis, offReg);
2996 else
2997 {
2998 idxRegDsc++;
2999 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
3000 || g_aHdaRegMap[idxRegDsc].offset != offReg)
3001 idxRegDsc = -1;
3002 }
3003 }
3004 }
3005#else
3006 if (idxRegDsc != -1)
3007 {
3008 /** @todo r=bird: This looks like code for handling unaligned register
3009 * accesses. If it isn't, then add a comment explaining what you're
3010 * trying to do here. OTOH, if it is then it has the following
3011 * issues:
3012 * -# You're calculating the wrong new value for the register.
3013 * -# You're not handling cross register accesses. Imagine a
3014 * 4-byte write starting at CORBCTL, or a 8-byte write.
3015 *
3016 * PS! consider dropping the 'offset' argument to pfnWrite/pfnRead as
3017 * nobody seems to be using it and it just adds complexity when reading
3018 * the code.
3019 *
3020 */
3021 uint32_t u32CurValue = pThis->au32Regs[idxRegMem];
3022 uint32_t u32NewValue;
3023 uint32_t mask;
3024 switch (cb)
3025 {
3026 case 1:
3027 u32NewValue = *(uint8_t const *)pv;
3028 mask = 0xff;
3029 break;
3030 case 2:
3031 u32NewValue = *(uint16_t const *)pv;
3032 mask = 0xffff;
3033 break;
3034 case 4:
3035 case 8:
3036 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
3037 u32NewValue = *(uint32_t const *)pv;
3038 mask = 0xffffffff;
3039 cb = 4;
3040 break;
3041 default:
3042 AssertFailedReturn(VERR_INTERNAL_ERROR_4); /* shall not happen. */
3043 }
3044 /* cross-register access, see corresponding comment in hdaMMIORead */
3045 uint32_t shift = (g_aHdaRegMap[idxRegDsc].offset - offReg) % sizeof(uint32_t) * 8;
3046 mask <<= shift;
3047 u32NewValue <<= shift;
3048 u32NewValue &= mask;
3049 u32NewValue |= (u32CurValue & ~mask);
3050
3051 rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32NewValue);
3052 LogFunc(("write %s:(%x) %x => %x\n", g_aHdaRegMap[idxRegDsc].abbrev, u32NewValue,
3053 u32CurValue, pThis->au32Regs[idxRegMem]));
3054 }
3055 else
3056 rc = VINF_SUCCESS;
3057
3058 LogFunc(("@%#05x %#x -> %#x\n", offRegLog, u32LogOldValue,
3059 idxRegLog != -1 ? pThis->au32Regs[idxRegLog] : UINT32_MAX));
3060#endif
3061 return rc;
3062}
3063
3064
3065/* PCI callback. */
3066
3067#ifdef IN_RING3
3068/**
3069 * @callback_method_impl{FNPCIIOREGIONMAP}
3070 */
3071static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
3072 PCIADDRESSSPACE enmType)
3073{
3074 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3075 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
3076 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
3077 int rc;
3078
3079 /*
3080 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
3081 *
3082 * Let IOM talk DWORDs when reading, saves a lot of complications. On
3083 * writing though, we have to do it all ourselves because of sideeffects.
3084 */
3085 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
3086 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
3087#ifdef NEW_READ_CODE
3088 IOMMMIO_FLAGS_READ_DWORD |
3089#else
3090 IOMMMIO_FLAGS_READ_PASSTHRU |
3091#endif
3092 IOMMMIO_FLAGS_WRITE_PASSTHRU,
3093 hdaMMIOWrite, hdaMMIORead, "HDA");
3094
3095 if (RT_FAILURE(rc))
3096 return rc;
3097
3098 if (pThis->fR0Enabled)
3099 {
3100 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
3101 "hdaMMIOWrite", "hdaMMIORead");
3102 if (RT_FAILURE(rc))
3103 return rc;
3104 }
3105
3106 if (pThis->fRCEnabled)
3107 {
3108 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
3109 "hdaMMIOWrite", "hdaMMIORead");
3110 if (RT_FAILURE(rc))
3111 return rc;
3112 }
3113
3114 pThis->MMIOBaseAddr = GCPhysAddress;
3115 return VINF_SUCCESS;
3116}
3117
3118
3119/* Saved state callbacks. */
3120
3121/**
3122 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3123 */
3124static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3125{
3126 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3127
3128 /* Save Codec nodes states */
3129 hdaCodecSaveState(pThis->pCodec, pSSM);
3130
3131 /* Save MMIO registers */
3132 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3133 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3134 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3135
3136 /* Save HDA dma counters */
3137 SSMR3PutStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3138 SSMR3PutStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3139 SSMR3PutStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
3140 return VINF_SUCCESS;
3141}
3142
3143
3144/**
3145 * @callback_method_impl{FNSSMDEVLOADEXEC}
3146 */
3147static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3148{
3149 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3150
3151 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3152
3153 /*
3154 * Load Codec nodes states.
3155 */
3156 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
3157 if (RT_FAILURE(rc))
3158 return rc;
3159
3160 /*
3161 * Load MMIO registers.
3162 */
3163 uint32_t cRegs;
3164 switch (uVersion)
3165 {
3166 case HDA_SSM_VERSION_1:
3167 /* Starting with r71199, we would save 112 instead of 113
3168 registers due to some code cleanups. This only affected trunk
3169 builds in the 4.1 development period. */
3170 cRegs = 113;
3171 if (SSMR3HandleRevision(pSSM) >= 71199)
3172 {
3173 uint32_t uVer = SSMR3HandleVersion(pSSM);
3174 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3175 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3176 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3177 cRegs = 112;
3178 }
3179 break;
3180
3181 case HDA_SSM_VERSION_2:
3182 case HDA_SSM_VERSION_3:
3183 cRegs = 112;
3184 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= HDA_NREGS_SAVED);
3185 break;
3186
3187 case HDA_SSM_VERSION:
3188 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3189 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3190 LogRel(("cRegs is %d, expected %d\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3191 break;
3192
3193 default:
3194 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3195 }
3196
3197 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3198 {
3199 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3200 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3201 }
3202 else
3203 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3204
3205 /*
3206 * Load HDA DMA counters.
3207 */
3208 uint32_t fFlags = uVersion <= HDA_SSM_VERSION_2 ? SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED : 0;
3209 PCSSMFIELD paFields = uVersion <= HDA_SSM_VERSION_2 ? g_aHdaBDLEDescFieldsOld : g_aHdaBDLEDescFields;
3210 rc = SSMR3GetStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), fFlags, paFields, NULL);
3211 AssertRCReturn(rc, rc);
3212 rc = SSMR3GetStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), fFlags, paFields, NULL);
3213 AssertRCReturn(rc, rc);
3214 rc = SSMR3GetStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), fFlags, paFields, NULL);
3215 AssertRCReturn(rc, rc);
3216
3217 /*
3218 * Update stuff after the state changes.
3219 */
3220 bool fEnableIn = RT_BOOL(SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3221#ifdef VBOX_WITH_HDA_MIC_IN
3222 bool fEnableMicIn = RT_BOOL(SDCTL(pThis, 2) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3223#endif
3224 bool fEnableOut = RT_BOOL(SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3225
3226#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3227 PHDADRIVER pDrv;
3228 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3229 {
3230 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn,
3231 fEnableIn);
3232 if (RT_FAILURE(rc))
3233 break;
3234# ifdef VBOX_WITH_HDA_MIC_IN
3235 rc = pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn,
3236 fEnableMicIn);
3237 if (RT_FAILURE(rc))
3238 break;
3239# endif
3240 rc = pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut,
3241 fEnableOut);
3242 if (RT_FAILURE(rc))
3243 break;
3244 }
3245#else
3246 AUD_set_active_in(pThis->pCodec->SwVoiceIn, SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3247 AUD_set_active_out(pThis->pCodec->SwVoiceOut, SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3248#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3249
3250 if (RT_SUCCESS(rc))
3251 {
3252 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3253 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3254 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
3255 }
3256
3257 LogFlowFuncLeaveRC(rc);
3258 return rc;
3259}
3260
3261
3262/* Debug and log type formatters. */
3263
3264/**
3265 * @callback_method_impl{FNRTSTRFORMATTYPE}
3266 */
3267static DECLCALLBACK(size_t)
3268hdaFormatStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3269 const char *pszType, void const *pvValue,
3270 int cchWidth, int cchPrecision, unsigned fFlags,
3271 void *pvUser)
3272{
3273 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
3274 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3275 "SDCTL(raw: %#x, strm:%#x, dir:%RTbool, tp:%RTbool strip:%x, deie:%RTbool, ioce:%RTbool, run:%RTbool, srst:%RTbool)",
3276 sdCtl,
3277 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> HDA_SDCTL_NUM_SHIFT,
3278 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)),
3279 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
3280 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
3281 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
3282 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
3283 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
3284 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
3285}
3286
3287/**
3288 * @callback_method_impl{FNRTSTRFORMATTYPE}
3289 */
3290static DECLCALLBACK(size_t)
3291hdaFormatStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3292 const char *pszType, void const *pvValue,
3293 int cchWidth, int cchPrecision, unsigned fFlags,
3294 void *pvUser)
3295{
3296 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
3297 uint32_t cb;
3298 switch (uSdFifos)
3299 {
3300 case HDA_SDONFIFO_16B: cb = 16; break;
3301 case HDA_SDONFIFO_32B: cb = 32; break;
3302 case HDA_SDONFIFO_64B: cb = 64; break;
3303 case HDA_SDONFIFO_128B: cb = 128; break;
3304 case HDA_SDONFIFO_192B: cb = 192; break;
3305 case HDA_SDONFIFO_256B: cb = 256; break;
3306 case HDA_SDINFIFO_120B: cb = 120; break;
3307 case HDA_SDINFIFO_160B: cb = 160; break;
3308 default: cb = 0; break;
3309 }
3310 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw: %#x, sdfifos:%u B)", uSdFifos, cb);
3311}
3312
3313/**
3314 * @callback_method_impl{FNRTSTRFORMATTYPE}
3315 */
3316static DECLCALLBACK(size_t)
3317hdaFormatStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3318 const char *pszType, void const *pvValue,
3319 int cchWidth, int cchPrecision, unsigned fFlags,
3320 void *pvUser)
3321{
3322 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
3323 uint32_t cb;
3324 switch (uSdFifos)
3325 {
3326 case HDA_SDFIFOW_8B: cb = 8; break;
3327 case HDA_SDFIFOW_16B: cb = 16; break;
3328 case HDA_SDFIFOW_32B: cb = 32; break;
3329 default: cb = 0; break;
3330 }
3331 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSdFifos, cb);
3332}
3333
3334/**
3335 * @callback_method_impl{FNRTSTRFORMATTYPE}
3336 */
3337static DECLCALLBACK(size_t)
3338hdaFormatStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3339 const char *pszType, void const *pvValue,
3340 int cchWidth, int cchPrecision, unsigned fFlags,
3341 void *pvUser)
3342{
3343 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
3344 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
3345 "SDSTS(raw: %#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
3346 uSdSts,
3347 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
3348 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
3349 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
3350 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
3351}
3352
3353
3354static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
3355{
3356 int iReg = 0;
3357 for (; iReg < HDA_NREGS; ++iReg)
3358 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
3359 return iReg;
3360 return -1;
3361}
3362
3363
3364static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
3365{
3366 Assert( pThis
3367 && iHdaIndex >= 0
3368 && iHdaIndex < HDA_NREGS);
3369 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
3370}
3371
3372
3373/**
3374 * @callback_method_impl{FNDBGFHANDLERDEV}
3375 */
3376static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3377{
3378 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3379 int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
3380 if (iHdaRegisterIndex != -1)
3381 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3382 else
3383 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
3384 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
3385}
3386
3387
3388static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
3389{
3390 Assert( pThis
3391 && iHdaStrmIndex >= 0
3392 && iHdaStrmIndex < 7);
3393 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
3394 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, CTL, iHdaStrmIndex));
3395 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, STS, iHdaStrmIndex));
3396 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOS, iHdaStrmIndex));
3397 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG(pThis, FIFOW, iHdaStrmIndex));
3398}
3399
3400
3401static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
3402{
3403 /* todo: add args parsing */
3404 return -1;
3405}
3406
3407
3408/**
3409 * @callback_method_impl{FNDBGFHANDLERDEV}
3410 */
3411static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3412{
3413 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3414 int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
3415 if (iHdaStrmIndex != -1)
3416 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3417 else
3418 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
3419 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
3420}
3421
3422
3423/**
3424 * @callback_method_impl{FNDBGFHANDLERDEV}
3425 */
3426static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3427{
3428 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3429
3430 if (pThis->pCodec->pfnCodecDbgListNodes)
3431 pThis->pCodec->pfnCodecDbgListNodes(pThis->pCodec, pHlp, pszArgs);
3432 else
3433 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3434}
3435
3436
3437/**
3438 * @callback_method_impl{FNDBGFHANDLERDEV}
3439 */
3440static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3441{
3442 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3443
3444 if (pThis->pCodec->pfnCodecDbgSelector)
3445 pThis->pCodec->pfnCodecDbgSelector(pThis->pCodec, pHlp, pszArgs);
3446 else
3447 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
3448}
3449
3450
3451/* PDMIBASE */
3452
3453/**
3454 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
3455 */
3456static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
3457{
3458 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
3459 Assert(&pThis->IBase == pInterface);
3460
3461 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
3462 return NULL;
3463}
3464
3465
3466/* PDMDEVREG */
3467
3468/**
3469 * Reset notification.
3470 *
3471 * @returns VBox status.
3472 * @param pDevIns The device instance data.
3473 *
3474 * @remark The original sources didn't install a reset handler, but it seems to
3475 * make sense to me so we'll do it.
3476 */
3477static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
3478{
3479 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3480 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
3481 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
3482 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
3483 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
3484 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
3485 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
3486 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
3487 HDA_REG(pThis, CORBRP) = 0x0;
3488 HDA_REG(pThis, RIRBWP) = 0x0;
3489
3490 LogFunc(("Resetting ...\n"));
3491
3492#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3493 /* Stop any audio currently playing. */
3494 PHDADRIVER pDrv;
3495 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3496 {
3497 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->LineIn.pStrmIn, false /* Disable */);
3498 /* Ignore rc. */
3499 pDrv->pConnector->pfnEnableIn(pDrv->pConnector, pDrv->MicIn.pStrmIn, false /* Disable */);
3500 /* Ditto. */
3501 pDrv->pConnector->pfnEnableOut(pDrv->pConnector, pDrv->Out.pStrmOut, false /* Disable */);
3502 /* Ditto. */
3503 }
3504#else
3505 AUD_set_active_in(pThis->pCodec->SwVoiceIn, false);
3506 AUD_set_active_out(pThis->pCodec->SwVoiceOut, false);
3507#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3508
3509 pThis->cbCorbBuf = 256 * sizeof(uint32_t);
3510
3511 if (pThis->pu32CorbBuf)
3512 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
3513 else
3514 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
3515
3516 pThis->cbRirbBuf = 256 * sizeof(uint64_t);
3517 if (pThis->pu64RirbBuf)
3518 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
3519 else
3520 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
3521
3522 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
3523
3524 HDABDLEDESC StEmptyBdle;
3525 for (uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
3526 {
3527 HDASTREAMTRANSFERDESC StreamDesc;
3528 PHDABDLEDESC pBdle = NULL;
3529 if (u8Strm == 0)
3530 pBdle = &pThis->StInBdle;
3531# ifdef VBOX_WITH_HDA_MIC_IN
3532 else if (u8Strm == 2)
3533 pBdle = &pThis->StMicBdle;
3534# endif
3535 else if(u8Strm == 4)
3536 pBdle = &pThis->StOutBdle;
3537 else
3538 {
3539 RT_ZERO(StEmptyBdle);
3540 pBdle = &StEmptyBdle;
3541 }
3542 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
3543 /* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
3544 HDA_STREAM_REG(pThis, CTL, u8Strm) = 0;
3545 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
3546 }
3547
3548 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
3549 HDA_REG(pThis, STATESTS) = 0x1;
3550
3551 LogRel(("HDA: Reset\n"));
3552}
3553
3554/**
3555 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3556 */
3557static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
3558{
3559 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3560
3561#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3562 PHDADRIVER pDrv;
3563 while (!RTListIsEmpty(&pThis->lstDrv))
3564 {
3565 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
3566
3567 RTListNodeRemove(&pDrv->Node);
3568 RTMemFree(pDrv);
3569 }
3570
3571 if (pThis->pMixer)
3572 {
3573 audioMixerDestroy(pThis->pMixer);
3574 pThis->pMixer = NULL;
3575 }
3576#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3577
3578 if (pThis->pCodec)
3579 {
3580 int rc = hdaCodecDestruct(pThis->pCodec);
3581 AssertRC(rc);
3582
3583 RTMemFree(pThis->pCodec);
3584 pThis->pCodec = NULL;
3585 }
3586
3587 RTMemFree(pThis->pu32CorbBuf);
3588 pThis->pu32CorbBuf = NULL;
3589
3590 RTMemFree(pThis->pu64RirbBuf);
3591 pThis->pu64RirbBuf = NULL;
3592
3593 return VINF_SUCCESS;
3594}
3595
3596#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3597/**
3598 * Attach command.
3599 *
3600 * This is called to let the device attach to a driver for a specified LUN
3601 * during runtime. This is not called during VM construction, the device
3602 * constructor have to attach to all the available drivers.
3603 *
3604 * @returns VBox status code.
3605 * @param pDevIns The device instance.
3606 * @param uLUN The logical unit which is being detached.
3607 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3608 */
3609static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
3610{
3611 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3612
3613 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
3614 ("HDA device does not support hotplugging\n"),
3615 VERR_INVALID_PARAMETER);
3616
3617 /*
3618 * Attach driver.
3619 */
3620 char *pszDesc = NULL;
3621 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
3622 AssertMsgReturn(pszDesc,
3623 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
3624 VERR_NO_MEMORY);
3625
3626 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
3627 &pThis->IBase, &pThis->pDrvBase, pszDesc);
3628 if (RT_SUCCESS(rc))
3629 {
3630 PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
3631 if (pDrv)
3632 {
3633 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIAUDIOCONNECTOR);
3634 AssertMsg(pDrv->pConnector != NULL,
3635 ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n",
3636 uLUN, rc));
3637 pDrv->pHDAState = pThis;
3638 pDrv->uLUN = uLUN;
3639
3640 /*
3641 * For now we always set the driver at LUN 0 as our primary
3642 * host backend. This might change in the future.
3643 */
3644 if (pDrv->uLUN == 0)
3645 pDrv->Flags |= PDMAUDIODRVFLAG_PRIMARY;
3646
3647 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
3648
3649 /* Attach to driver list. */
3650 RTListAppend(&pThis->lstDrv, &pDrv->Node);
3651 }
3652 else
3653 rc = VERR_NO_MEMORY;
3654 }
3655 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
3656 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
3657 {
3658 LogFunc(("No attached driver for LUN #%u\n", uLUN));
3659 }
3660 else if (RT_FAILURE(rc))
3661 AssertMsgFailed(("Failed to attach HDA LUN #%u (\"%s\"), rc=%Rrc\n",
3662 uLUN, pszDesc, rc));
3663
3664 RTStrFree(pszDesc);
3665
3666 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
3667 return rc;
3668}
3669
3670static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3671{
3672 NOREF(pDevIns); NOREF(iLUN); NOREF(fFlags);
3673
3674 LogFlowFuncEnter();
3675}
3676#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3677
3678/**
3679 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3680 */
3681static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
3682{
3683 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3684 Assert(iInstance == 0);
3685 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3686
3687 /*
3688 * Validations.
3689 */
3690 if (!CFGMR3AreValuesValid(pCfgHandle, "R0Enabled\0"
3691 "RCEnabled\0"))
3692 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
3693 N_ ("Invalid configuration for the Intel HDA device"));
3694
3695 int rc = CFGMR3QueryBoolDef(pCfgHandle, "RCEnabled", &pThis->fRCEnabled, false);
3696 if (RT_FAILURE(rc))
3697 return PDMDEV_SET_ERROR(pDevIns, rc,
3698 N_("HDA configuration error: failed to read RCEnabled as boolean"));
3699 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &pThis->fR0Enabled, false);
3700 if (RT_FAILURE(rc))
3701 return PDMDEV_SET_ERROR(pDevIns, rc,
3702 N_("HDA configuration error: failed to read R0Enabled as boolean"));
3703
3704 /*
3705 * Initialize data (most of it anyway).
3706 */
3707 pThis->pDevInsR3 = pDevIns;
3708 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3709 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3710 /* IBase */
3711 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
3712
3713 /* PCI Device */
3714 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
3715 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
3716
3717 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
3718 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
3719 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
3720 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
3721 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
3722 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
3723 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
3724 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
3725 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
3726 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
3727 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
3728
3729#if defined(HDA_AS_PCI_EXPRESS)
3730 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
3731#elif defined(VBOX_WITH_MSI_DEVICES)
3732 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
3733#else
3734 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
3735#endif
3736
3737 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
3738 /// of these values needs to be properly documented!
3739 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
3740 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
3741
3742 /* Power Management */
3743 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
3744 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
3745 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
3746
3747#ifdef HDA_AS_PCI_EXPRESS
3748 /* PCI Express */
3749 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
3750 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
3751 /* Device flags */
3752 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
3753 /* version */ 0x1 |
3754 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
3755 /* MSI */ (100) << 9 );
3756 /* Device capabilities */
3757 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
3758 /* Device control */
3759 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
3760 /* Device status */
3761 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
3762 /* Link caps */
3763 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
3764 /* Link control */
3765 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
3766 /* Link status */
3767 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
3768 /* Slot capabilities */
3769 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
3770 /* Slot control */
3771 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
3772 /* Slot status */
3773 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
3774 /* Root control */
3775 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
3776 /* Root capabilities */
3777 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
3778 /* Root status */
3779 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
3780 /* Device capabilities 2 */
3781 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
3782 /* Device control 2 */
3783 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
3784 /* Link control 2 */
3785 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
3786 /* Slot control 2 */
3787 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
3788#endif
3789
3790 /*
3791 * Register the PCI device.
3792 */
3793 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
3794 if (RT_FAILURE(rc))
3795 return rc;
3796
3797 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
3798 if (RT_FAILURE(rc))
3799 return rc;
3800
3801#ifdef VBOX_WITH_MSI_DEVICES
3802 PDMMSIREG MsiReg;
3803 RT_ZERO(MsiReg);
3804 MsiReg.cMsiVectors = 1;
3805 MsiReg.iMsiCapOffset = 0x60;
3806 MsiReg.iMsiNextOffset = 0x50;
3807 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
3808 if (RT_FAILURE(rc))
3809 {
3810 /* That's OK, we can work without MSI */
3811 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
3812 }
3813#endif
3814
3815 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
3816 if (RT_FAILURE(rc))
3817 return rc;
3818
3819#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3820 RTListInit(&pThis->lstDrv);
3821
3822 uint8_t uLUN;
3823 for (uLUN = 0; uLUN < UINT8_MAX; uLUN)
3824 {
3825 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
3826 rc = hdaAttach(pDevIns, uLUN, PDM_TACH_FLAGS_NOT_HOT_PLUG);
3827 if (RT_FAILURE(rc))
3828 {
3829 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3830 rc = VINF_SUCCESS;
3831
3832 break;
3833 }
3834
3835 uLUN++;
3836 }
3837
3838 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
3839
3840 if (RT_SUCCESS(rc))
3841 {
3842 rc = audioMixerCreate("HDA Mixer", 0 /* uFlags */,
3843 &pThis->pMixer);
3844 if (RT_SUCCESS(rc))
3845 {
3846 PDMAUDIOSTREAMCFG streamCfg;
3847 streamCfg.uHz = 48000;
3848 streamCfg.cChannels = 2;
3849 streamCfg.enmFormat = AUD_FMT_S16;
3850 streamCfg.enmEndianness = PDMAUDIOHOSTENDIANESS;
3851
3852 rc = audioMixerSetDeviceFormat(pThis->pMixer, &streamCfg);
3853 AssertRC(rc);
3854
3855 /* Add all required audio sinks. */
3856 rc = audioMixerAddSink(pThis->pMixer, "[Recording] Line In",
3857 &pThis->pSinkLineIn);
3858 AssertRC(rc);
3859
3860 rc = audioMixerAddSink(pThis->pMixer, "[Recording] Microphone In",
3861 &pThis->pSinkMicIn);
3862 AssertRC(rc);
3863 }
3864 }
3865
3866 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
3867#else
3868 /*
3869 * Attach driver.
3870 */
3871 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Audio Driver Port");
3872 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3873 Log(("hda: No attached driver!\n"));
3874 else if (RT_FAILURE(rc))
3875 {
3876 AssertMsgFailed(("Failed to attach Intel HDA LUN #0! rc=%Rrc\n", rc));
3877 return rc;
3878 }
3879#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3880
3881 if (RT_SUCCESS(rc))
3882 {
3883 /* Construct codec. */
3884 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
3885 if (!pThis->pCodec)
3886 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
3887
3888#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3889 /* Audio driver callbacks for multiplexing. */
3890 pThis->pCodec->pfnCloseIn = hdaCloseIn;
3891 pThis->pCodec->pfnCloseOut = hdaCloseOut;
3892 pThis->pCodec->pfnOpenIn = hdaOpenIn;
3893 pThis->pCodec->pfnOpenOut = hdaOpenOut;
3894 pThis->pCodec->pfnSetVolume = hdaSetVolume;
3895#endif /* VBOX_WITH_PDM_AUDIO_DRIVER */
3896
3897 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
3898
3899 /* Construct the codec. */
3900 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfgHandle);
3901 if (RT_FAILURE(rc))
3902 AssertRCReturn(rc, rc);
3903
3904 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
3905 verb F20 should provide device/codec recognition. */
3906 Assert(pThis->pCodec->u16VendorId);
3907 Assert(pThis->pCodec->u16DeviceId);
3908 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
3909 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
3910
3911#ifndef VBOX_WITH_PDM_AUDIO_DRIVER
3912 pThis->pCodec->pfnTransfer = hdaTransfer;
3913#endif
3914 pThis->pCodec->pfnReset = hdaCodecReset;
3915 }
3916
3917 if (RT_SUCCESS(rc))
3918 {
3919 hdaReset(pDevIns);
3920
3921 /*
3922 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
3923 * hdaReset shouldn't affects these registers.
3924 */
3925 HDA_REG(pThis, WAKEEN) = 0x0;
3926 HDA_REG(pThis, STATESTS) = 0x0;
3927
3928 /*
3929 * Debug and string formatter types.
3930 */
3931 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
3932 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
3933 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
3934 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
3935
3936 rc = RTStrFormatTypeRegister("sdctl", hdaFormatStrmCtl, NULL);
3937 AssertRC(rc);
3938 rc = RTStrFormatTypeRegister("sdsts", hdaFormatStrmSts, NULL);
3939 AssertRC(rc);
3940 rc = RTStrFormatTypeRegister("sdfifos", hdaFormatStrmFifos, NULL);
3941 AssertRC(rc);
3942 rc = RTStrFormatTypeRegister("sdfifow", hdaFormatStrmFifow, NULL);
3943 AssertRC(rc);
3944 #if 0
3945 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
3946 AssertRC(rc);
3947 #endif
3948
3949 /*
3950 * Some debug assertions.
3951 */
3952 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
3953 {
3954 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
3955 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
3956
3957 /* binary search order. */
3958 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
3959 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3960 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
3961
3962 /* alignment. */
3963 AssertReleaseMsg( pReg->size == 1
3964 || (pReg->size == 2 && (pReg->offset & 1) == 0)
3965 || (pReg->size == 3 && (pReg->offset & 3) == 0)
3966 || (pReg->size == 4 && (pReg->offset & 3) == 0),
3967 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3968
3969 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
3970 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
3971 if (pReg->offset & 3)
3972 {
3973 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
3974 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3975 if (pPrevReg)
3976 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
3977 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3978 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
3979 }
3980 #if 0
3981 if ((pReg->offset + pReg->size) & 3)
3982 {
3983 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3984 if (pNextReg)
3985 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
3986 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3987 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
3988 }
3989 #endif
3990
3991 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
3992 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
3993 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3994 }
3995 }
3996
3997#ifdef VBOX_WITH_PDM_AUDIO_DRIVER
3998 if (RT_SUCCESS(rc))
3999 {
4000 /* Start the emulation timer. */
4001 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
4002 TMTIMER_FLAGS_NO_CRIT_SECT, "DevIchHda", &pThis->pTimer);
4003 AssertRCReturn(rc, rc);
4004
4005 if (RT_SUCCESS(rc))
4006 {
4007 /** @todo Investigate why sounds is getting corrupted if the "ticks" value is too
4008 * low, e.g. "PDMDevHlpTMTimeVirtGetFreq / 200". */
4009 pThis->uTicks = PDMDevHlpTMTimeVirtGetFreq(pDevIns) / 500; /** @todo Make this configurable! */
4010 if (pThis->uTicks < 100)
4011 pThis->uTicks = 100;
4012 LogFunc(("Timer ticks=%RU64\n", pThis->uTicks));
4013
4014 /* Fire off timer. */
4015 TMTimerSet(pThis->pTimer, TMTimerGet(pThis->pTimer) + pThis->uTicks);
4016 }
4017 }
4018
4019# ifdef VBOX_WITH_STATISTICS
4020 if (RT_SUCCESS(rc))
4021 {
4022 /*
4023 * Register statistics.
4024 */
4025 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
4026 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
4027 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
4028 }
4029# endif
4030
4031#endif
4032
4033 LogFlowFuncLeaveRC(rc);
4034 return rc;
4035}
4036
4037/**
4038 * The device registration structure.
4039 */
4040const PDMDEVREG g_DeviceICH6_HDA =
4041{
4042 /* u32Version */
4043 PDM_DEVREG_VERSION,
4044 /* szName */
4045 "hda",
4046 /* szRCMod */
4047 "VBoxDDGC.gc",
4048 /* szR0Mod */
4049 "VBoxDDR0.r0",
4050 /* pszDescription */
4051 "Intel HD Audio Controller",
4052 /* fFlags */
4053 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
4054 /* fClass */
4055 PDM_DEVREG_CLASS_AUDIO,
4056 /* cMaxInstances */
4057 1,
4058 /* cbInstance */
4059 sizeof(HDASTATE),
4060 /* pfnConstruct */
4061 hdaConstruct,
4062 /* pfnDestruct */
4063 hdaDestruct,
4064 /* pfnRelocate */
4065 NULL,
4066 /* pfnMemSetup */
4067 NULL,
4068 /* pfnPowerOn */
4069 NULL,
4070 /* pfnReset */
4071 hdaReset,
4072 /* pfnSuspend */
4073 NULL,
4074 /* pfnResume */
4075 NULL,
4076 /* pfnAttach */
4077 NULL,
4078 /* pfnDetach */
4079 NULL,
4080 /* pfnQueryInterface. */
4081 NULL,
4082 /* pfnInitComplete */
4083 NULL,
4084 /* pfnPowerOff */
4085 NULL,
4086 /* pfnSoftReset */
4087 NULL,
4088 /* u32VersionEnd */
4089 PDM_DEVREG_VERSION
4090};
4091
4092#endif /* IN_RING3 */
4093#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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