VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevIchHda.cpp@ 44824

Last change on this file since 44824 was 44761, checked in by vboxsync, 12 years ago

DevIchHda.cpp: Make Dijkstra happy.
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1/* $Id: DevIchHda.cpp 44761 2013-02-20 13:10:28Z vboxsync $ */
2/** @file
3 * DevIchHda - VBox ICH Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2013 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_DEV_AUDIO
26#include <VBox/vmm/pdmdev.h>
27#include <VBox/version.h>
28
29#include <iprt/assert.h>
30#include <iprt/uuid.h>
31#include <iprt/string.h>
32#include <iprt/mem.h>
33#include <iprt/asm.h>
34#include <iprt/asm-math.h>
35
36#include "VBoxDD.h"
37
38extern "C" {
39#include "audio.h"
40}
41#include "DevIchHdaCodec.h"
42
43
44/*******************************************************************************
45* Defined Constants And Macros *
46*******************************************************************************/
47//#define HDA_AS_PCI_EXPRESS
48#define VBOX_WITH_INTEL_HDA
49
50#if defined(VBOX_WITH_HP_HDA)
51/* HP Pavilion dv4t-1300 */
52# define HDA_PCI_VENDOR_ID 0x103c
53# define HDA_PCI_DEICE_ID 0x30f7
54#elif defined(VBOX_WITH_INTEL_HDA)
55/* Intel HDA controller */
56# define HDA_PCI_VENDOR_ID 0x8086
57# define HDA_PCI_DEICE_ID 0x2668
58#elif defined(VBOX_WITH_NVIDIA_HDA)
59/* nVidia HDA controller */
60# define HDA_PCI_VENDOR_ID 0x10de
61# define HDA_PCI_DEICE_ID 0x0ac0
62#else
63# error "Please specify your HDA device vendor/device IDs"
64#endif
65
66/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
67 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
68 * is read only except for bit 15 like the HDA spec states.
69 *
70 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
71 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
72#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
73
74#define HDA_NREGS 112
75/* Registers */
76#define HDA_REG_IND_NAME(x) ICH6_HDA_REG_##x
77#define HDA_REG_FIELD_NAME(reg, x) ICH6_HDA_##reg##_##x
78#define HDA_REG_FIELD_MASK(reg, x) ICH6_HDA_##reg##_##x##_MASK
79#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(ICH6_HDA_##reg##_##x##_SHIFT)
80#define HDA_REG_FIELD_SHIFT(reg, x) ICH6_HDA_##reg##_##x##_SHIFT
81#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[(x)])
82#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
83#define HDA_REG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_MASK(reg, val))) << (HDA_REG_FIELD_SHIFT(reg, val))))
84#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
85#define HDA_REG_SVALUE(pThis, reg, val) (HDA_REG_VALUE(pThis, reg, val) >> (HDA_REG_FIELD_SHIFT(reg, val)))
86
87#define ICH6_HDA_REG_GCAP 0 /* range 0x00-0x01*/
88#define GCAP(pThis) (HDA_REG((pThis), GCAP))
89/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
90 * oss (15:12) - number of output streams supported
91 * iss (11:8) - number of input streams supported
92 * bss (7:3) - number of bidirectional streams supported
93 * bds (2:1) - number of serial data out signals supported
94 * b64sup (0) - 64 bit addressing supported.
95 */
96#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
97 ( (((oss) & 0xF) << 12) \
98 | (((iss) & 0xF) << 8) \
99 | (((bss) & 0x1F) << 3) \
100 | (((bds) & 0x3) << 2) \
101 | ((b64sup) & 1))
102#define ICH6_HDA_REG_VMIN 1 /* range 0x02 */
103#define VMIN(pThis) (HDA_REG((pThis), VMIN))
104
105#define ICH6_HDA_REG_VMAJ 2 /* range 0x03 */
106#define VMAJ(pThis) (HDA_REG((pThis), VMAJ))
107
108#define ICH6_HDA_REG_OUTPAY 3 /* range 0x04-0x05 */
109#define OUTPAY(pThis) (HDA_REG((pThis), OUTPAY))
110
111#define ICH6_HDA_REG_INPAY 4 /* range 0x06-0x07 */
112#define INPAY(pThis) (HDA_REG((pThis), INPAY))
113
114#define ICH6_HDA_REG_GCTL (5)
115#define ICH6_HDA_GCTL_RST_SHIFT (0)
116#define ICH6_HDA_GCTL_FSH_SHIFT (1)
117#define ICH6_HDA_GCTL_UR_SHIFT (8)
118#define GCTL(pThis) (HDA_REG((pThis), GCTL))
119
120#define ICH6_HDA_REG_WAKEEN 6 /* 0x0C */
121#define WAKEEN(pThis) (HDA_REG((pThis), WAKEEN))
122
123#define ICH6_HDA_REG_STATESTS 7 /* range 0x0E */
124#define STATESTS(pThis) (HDA_REG((pThis), STATESTS))
125#define ICH6_HDA_STATES_SCSF 0x7
126
127#define ICH6_HDA_REG_GSTS 8 /* range 0x10-0x11*/
128#define ICH6_HDA_GSTS_FSH_SHIFT (1)
129#define GSTS(pThis) (HDA_REG(pThis, GSTS))
130
131#define ICH6_HDA_REG_INTCTL 9 /* 0x20 */
132#define ICH6_HDA_INTCTL_GIE_SHIFT 31
133#define ICH6_HDA_INTCTL_CIE_SHIFT 30
134#define ICH6_HDA_INTCTL_S0_SHIFT (0)
135#define ICH6_HDA_INTCTL_S1_SHIFT (1)
136#define ICH6_HDA_INTCTL_S2_SHIFT (2)
137#define ICH6_HDA_INTCTL_S3_SHIFT (3)
138#define ICH6_HDA_INTCTL_S4_SHIFT (4)
139#define ICH6_HDA_INTCTL_S5_SHIFT (5)
140#define ICH6_HDA_INTCTL_S6_SHIFT (6)
141#define ICH6_HDA_INTCTL_S7_SHIFT (7)
142#define INTCTL(pThis) (HDA_REG((pThis), INTCTL))
143#define INTCTL_GIE(pThis) (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
144#define INTCTL_CIE(pThis) (HDA_REG_FLAG_VALUE(pThis, INTCTL, CIE))
145#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
146#define INTCTL_SALL(pThis) (INTCTL((pThis)) & 0xFF)
147
148/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
149 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
150 * the datasheet.
151 */
152#define ICH6_HDA_REG_SSYNC 12 /* 0x34 */
153#define SSYNC(pThis) (HDA_REG((pThis), SSYNC))
154
155#define ICH6_HDA_REG_INTSTS 10 /* 0x24 */
156#define ICH6_HDA_INTSTS_GIS_SHIFT (31)
157#define ICH6_HDA_INTSTS_CIS_SHIFT (30)
158#define ICH6_HDA_INTSTS_S0_SHIFT (0)
159#define ICH6_HDA_INTSTS_S1_SHIFT (1)
160#define ICH6_HDA_INTSTS_S2_SHIFT (2)
161#define ICH6_HDA_INTSTS_S3_SHIFT (3)
162#define ICH6_HDA_INTSTS_S4_SHIFT (4)
163#define ICH6_HDA_INTSTS_S5_SHIFT (5)
164#define ICH6_HDA_INTSTS_S6_SHIFT (6)
165#define ICH6_HDA_INTSTS_S7_SHIFT (7)
166#define ICH6_HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
167#define INTSTS(pThis) (HDA_REG((pThis), INTSTS))
168#define INTSTS_GIS(pThis) (HDA_REG_FLAG_VALUE((pThis), INTSTS, GIS)
169#define INTSTS_CIS(pThis) (HDA_REG_FLAG_VALUE((pThis), INTSTS, CIS)
170#define INTSTS_SX(pThis, X) (HDA_REG_FLAG_VALUE(pThis), INTSTS, S##X)
171#define INTSTS_SANY(pThis) (INTSTS((pThis)) & 0xFF)
172
173#define ICH6_HDA_REG_CORBLBASE 13 /* 0x40 */
174#define CORBLBASE(pThis) (HDA_REG((pThis), CORBLBASE))
175#define ICH6_HDA_REG_CORBUBASE 14 /* 0x44 */
176#define CORBUBASE(pThis) (HDA_REG((pThis), CORBUBASE))
177#define ICH6_HDA_REG_CORBWP 15 /* 48 */
178#define ICH6_HDA_REG_CORBRP 16 /* 4A */
179#define ICH6_HDA_CORBRP_RST_SHIFT 15
180#define ICH6_HDA_CORBRP_WP_SHIFT 0
181#define ICH6_HDA_CORBRP_WP_MASK 0xFF
182
183#define CORBRP(pThis) (HDA_REG(pThis, CORBRP))
184#define CORBWP(pThis) (HDA_REG(pThis, CORBWP))
185
186#define ICH6_HDA_REG_CORBCTL 17 /* 0x4C */
187#define ICH6_HDA_CORBCTL_DMA_SHIFT (1)
188#define ICH6_HDA_CORBCTL_CMEIE_SHIFT (0)
189
190#define CORBCTL(pThis) (HDA_REG(pThis, CORBCTL))
191
192
193#define ICH6_HDA_REG_CORBSTS 18 /* 0x4D */
194#define CORBSTS(pThis) (HDA_REG(pThis, CORBSTS))
195#define ICH6_HDA_CORBSTS_CMEI_SHIFT (0)
196
197#define ICH6_HDA_REG_CORBSIZE 19 /* 0x4E */
198#define ICH6_HDA_CORBSIZE_SZ_CAP 0xF0
199#define ICH6_HDA_CORBSIZE_SZ 0x3
200#define CORBSIZE_SZ(pThis) (HDA_REG(pThis, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ)
201#define CORBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, ICH6_HDA_REG_CORBSIZE) & ICH6_HDA_CORBSIZE_SZ_CAP)
202/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
203
204#define ICH6_HDA_REG_RIRLBASE 20 /* 0x50 */
205#define RIRLBASE(pThis) (HDA_REG((pThis), RIRLBASE))
206
207#define ICH6_HDA_REG_RIRUBASE 21 /* 0x54 */
208#define RIRUBASE(pThis) (HDA_REG((pThis), RIRUBASE))
209
210#define ICH6_HDA_REG_RIRBWP 22 /* 0x58 */
211#define ICH6_HDA_RIRBWP_RST_SHIFT (15)
212#define ICH6_HDA_RIRBWP_WP_MASK 0xFF
213#define RIRBWP(pThis) (HDA_REG(pThis, RIRBWP))
214
215#define ICH6_HDA_REG_RINTCNT 23 /* 0x5A */
216#define RINTCNT(pThis) (HDA_REG((pThis), RINTCNT))
217#define RINTCNT_N(pThis) (RINTCNT((pThis)) & 0xff)
218
219#define ICH6_HDA_REG_RIRBCTL 24 /* 0x5C */
220#define ICH6_HDA_RIRBCTL_RIC_SHIFT (0)
221#define ICH6_HDA_RIRBCTL_DMA_SHIFT (1)
222#define ICH6_HDA_ROI_DMA_SHIFT (2)
223#define RIRBCTL(pThis) (HDA_REG((pThis), RIRBCTL))
224#define RIRBCTL_RIRB_RIC(pThis) (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
225#define RIRBCTL_RIRB_DMA(pThis) (HDA_REG_FLAG_VALUE((pThis), RIRBCTL, DMA)
226#define RIRBCTL_ROI(pThis) (HDA_REG_FLAG_VALUE((pThis), RIRBCTL, ROI))
227
228#define ICH6_HDA_REG_RIRBSTS 25 /* 0x5D */
229#define ICH6_HDA_RIRBSTS_RINTFL_SHIFT (0)
230#define ICH6_HDA_RIRBSTS_RIRBOIS_SHIFT (2)
231#define RIRBSTS(pThis) (HDA_REG(pThis, RIRBSTS))
232#define RIRBSTS_RINTFL(pThis) (HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL))
233#define RIRBSTS_RIRBOIS(pThis) (HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS))
234
235#define ICH6_HDA_REG_RIRBSIZE 26 /* 0x5E */
236#define ICH6_HDA_RIRBSIZE_SZ_CAP 0xF0
237#define ICH6_HDA_RIRBSIZE_SZ 0x3
238
239#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ)
240#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, ICH6_HDA_REG_RIRBSIZE) & ICH6_HDA_RIRBSIZE_SZ_CAP)
241
242
243#define ICH6_HDA_REG_IC 27 /* 0x60 */
244#define IC(pThis) (HDA_REG(pThis, IC))
245#define ICH6_HDA_REG_IR 28 /* 0x64 */
246#define IR(pThis) (HDA_REG(pThis, IR))
247#define ICH6_HDA_REG_IRS 29 /* 0x68 */
248#define ICH6_HDA_IRS_ICB_SHIFT (0)
249#define ICH6_HDA_IRS_IRV_SHIFT (1)
250#define IRS(pThis) (HDA_REG(pThis, IRS))
251#define IRS_ICB(pThis) (HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
252#define IRS_IRV(pThis) (HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
253
254#define ICH6_HDA_REG_DPLBASE 30 /* 0x70 */
255#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
256#define ICH6_HDA_REG_DPUBASE 31 /* 0x74 */
257#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
258#define DPBASE_ENABLED 1
259#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
260
261#define HDA_STREAM_REG_DEF(name, num) (ICH6_HDA_REG_SD##num##name)
262#define HDA_STREAM_REG(pThis, name, num) (HDA_REG((pThis), N_(HDA_STREAM_REG_DEF(name, num))))
263/* Note: sdnum here _MUST_ be stream reg number [0,7] */
264#define HDA_STREAM_REG2(pThis, name, sdnum) (HDA_REG_IND((pThis), ICH6_HDA_REG_SD0##name + (sdnum) * 10))
265
266#define ICH6_HDA_REG_SD0CTL 32 /* 0x80 */
267#define ICH6_HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
268#define ICH6_HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
269#define ICH6_HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
270#define ICH6_HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
271#define ICH6_HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
272#define ICH6_HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
273#define ICH6_HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
274
275#define SD(func, num) SD##num##func
276#define SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
277#define SDCTL_NUM(pThis, num) ((SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
278#define ICH6_HDA_SDCTL_NUM_MASK (0xF)
279#define ICH6_HDA_SDCTL_NUM_SHIFT (20)
280#define ICH6_HDA_SDCTL_DIR_SHIFT (19)
281#define ICH6_HDA_SDCTL_TP_SHIFT (18)
282#define ICH6_HDA_SDCTL_STRIPE_MASK (0x3)
283#define ICH6_HDA_SDCTL_STRIPE_SHIFT (16)
284#define ICH6_HDA_SDCTL_DEIE_SHIFT (4)
285#define ICH6_HDA_SDCTL_FEIE_SHIFT (3)
286#define ICH6_HDA_SDCTL_ICE_SHIFT (2)
287#define ICH6_HDA_SDCTL_RUN_SHIFT (1)
288#define ICH6_HDA_SDCTL_SRST_SHIFT (0)
289
290#define ICH6_HDA_REG_SD0STS 33 /* 0x83 */
291#define ICH6_HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
292#define ICH6_HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
293#define ICH6_HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
294#define ICH6_HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
295#define ICH6_HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
296#define ICH6_HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
297#define ICH6_HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
298
299#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
300#define ICH6_HDA_SDSTS_FIFORDY_SHIFT (5)
301#define ICH6_HDA_SDSTS_DE_SHIFT (4)
302#define ICH6_HDA_SDSTS_FE_SHIFT (3)
303#define ICH6_HDA_SDSTS_BCIS_SHIFT (2)
304
305#define ICH6_HDA_REG_SD0LPIB 34 /* 0x84 */
306#define ICH6_HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
307#define ICH6_HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
308#define ICH6_HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
309#define ICH6_HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
310#define ICH6_HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
311#define ICH6_HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
312#define ICH6_HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
313
314#define SDLPIB(pThis, num) HDA_REG((pThis), SD(LPIB, num))
315
316#define ICH6_HDA_REG_SD0CBL 35 /* 0x88 */
317#define ICH6_HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
318#define ICH6_HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
319#define ICH6_HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
320#define ICH6_HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
321#define ICH6_HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
322#define ICH6_HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
323#define ICH6_HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
324
325#define SDLCBL(pThis, num) HDA_REG((pThis), SD(CBL, num))
326
327#define ICH6_HDA_REG_SD0LVI 36 /* 0x8C */
328#define ICH6_HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
329#define ICH6_HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
330#define ICH6_HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
331#define ICH6_HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
332#define ICH6_HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
333#define ICH6_HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
334#define ICH6_HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
335
336#define SDLVI(pThis, num) HDA_REG((pThis), SD(LVI, num))
337
338#define ICH6_HDA_REG_SD0FIFOW 37 /* 0x8E */
339#define ICH6_HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
340#define ICH6_HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
341#define ICH6_HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
342#define ICH6_HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
343#define ICH6_HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
344#define ICH6_HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
345#define ICH6_HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
346
347/*
348 * ICH6 datasheet defined limits for FIFOW values (18.2.38)
349 */
350#define HDA_SDFIFOW_8B (0x2)
351#define HDA_SDFIFOW_16B (0x3)
352#define HDA_SDFIFOW_32B (0x4)
353#define SDFIFOW(pThis, num) HDA_REG((pThis), SD(FIFOW, num))
354
355#define ICH6_HDA_REG_SD0FIFOS 38 /* 0x90 */
356#define ICH6_HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
357#define ICH6_HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
358#define ICH6_HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
359#define ICH6_HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
360#define ICH6_HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
361#define ICH6_HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
362#define ICH6_HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
363
364/*
365 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
366 * formula: size - 1
367 * Other values not listed are not supported.
368 */
369#define HDA_SDONFIFO_16B (0x0F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
370#define HDA_SDONFIFO_32B (0x1F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
371#define HDA_SDONFIFO_64B (0x3F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
372#define HDA_SDONFIFO_128B (0x7F) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
373#define HDA_SDONFIFO_192B (0xBF) /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
374#define HDA_SDONFIFO_256B (0xFF) /* 20-, 24-bit Output Streams */
375#define HDA_SDINFIFO_120B (0x77) /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
376#define HDA_SDINFIFO_160B (0x9F) /* 20-, 24-bit Input Streams Streams */
377#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
378
379#define ICH6_HDA_REG_SD0FMT 39 /* 0x92 */
380#define ICH6_HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
381#define ICH6_HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
382#define ICH6_HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
383#define ICH6_HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
384#define ICH6_HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
385#define ICH6_HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
386#define ICH6_HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
387
388#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
389#define ICH6_HDA_SDFMT_BASE_RATE_SHIFT (14)
390#define ICH6_HDA_SDFMT_MULT_SHIFT (11)
391#define ICH6_HDA_SDFMT_MULT_MASK (0x7)
392#define ICH6_HDA_SDFMT_DIV_SHIFT (8)
393#define ICH6_HDA_SDFMT_DIV_MASK (0x7)
394#define ICH6_HDA_SDFMT_BITS_SHIFT (4)
395#define ICH6_HDA_SDFMT_BITS_MASK (0x7)
396#define SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
397#define SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
398#define SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
399
400#define ICH6_HDA_REG_SD0BDPL 40 /* 0x98 */
401#define ICH6_HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
402#define ICH6_HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
403#define ICH6_HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
404#define ICH6_HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
405#define ICH6_HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
406#define ICH6_HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
407#define ICH6_HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
408
409#define SDBDPL(pThis, num) HDA_REG((pThis), SD(BDPL, num))
410
411#define ICH6_HDA_REG_SD0BDPU 41 /* 0x9C */
412#define ICH6_HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
413#define ICH6_HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
414#define ICH6_HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
415#define ICH6_HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
416#define ICH6_HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
417#define ICH6_HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
418#define ICH6_HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
419
420#define SDBDPU(pThis, num) HDA_REG((pThis), SD(BDPU, num))
421
422
423/*******************************************************************************
424* Structures and Typedefs *
425*******************************************************************************/
426typedef struct HDABDLEDESC
427{
428 uint64_t u64BdleCviAddr;
429 uint32_t u32BdleMaxCvi;
430 uint32_t u32BdleCvi;
431 uint32_t u32BdleCviLen;
432 uint32_t u32BdleCviPos;
433 bool fBdleCviIoc;
434 uint32_t cbUnderFifoW;
435 uint8_t au8HdaBuffer[HDA_SDONFIFO_256B + 1];
436} HDABDLEDESC, *PHDABDLEDESC;
437
438typedef struct HDASTREAMTRANSFERDESC
439{
440 uint64_t u64BaseDMA;
441 uint32_t u32Ctl;
442 uint32_t *pu32Sts;
443 uint8_t u8Strm;
444 uint32_t *pu32Lpib;
445 uint32_t u32Cbl;
446 uint32_t u32Fifos;
447} HDASTREAMTRANSFERDESC, *PHDASTREAMTRANSFERDESC;
448
449/**
450 * ICH Intel HD Audio Controller state.
451 */
452typedef struct HDASTATE
453{
454 /** The PCI device structure. */
455 PCIDevice PciDev;
456 /** Pointer to the device instance. */
457 PPDMDEVINSR3 pDevIns;
458 /** Pointer to the connector of the attached audio driver. */
459 PPDMIAUDIOCONNECTOR pDrv;
460 /** Pointer to the attached audio driver. */
461 PPDMIBASE pDrvBase;
462 /** The base interface for LUN\#0. */
463 PDMIBASE IBase;
464 RTGCPHYS MMIOBaseAddr;
465 uint32_t au32Regs[HDA_NREGS];
466 HDABDLEDESC StInBdle;
467 HDABDLEDESC StOutBdle;
468 HDABDLEDESC StMicBdle;
469 /** Interrupt on completion */
470 bool fCviIoc;
471 uint64_t u64CORBBase;
472 uint64_t u64RIRBBase;
473 uint64_t u64DPBase;
474 /** pointer to CORB buf */
475 uint32_t *pu32CorbBuf;
476 /** size in bytes of CORB buf */
477 uint32_t cbCorbBuf;
478 /** pointer on RIRB buf */
479 uint64_t *pu64RirbBuf;
480 /** size in bytes of RIRB buf */
481 uint32_t cbRirbBuf;
482 /** indicates if HDA in reset. */
483 bool fInReset;
484 /** The HDA codec state. */
485 HDACODEC Codec;
486 /** 1.2.3.4.5.6.7. - someone please tell me what I'm counting! - .8.9.10... */
487 uint8_t u8Counter;
488 uint64_t u64BaseTS;
489} HDASTATE;
490/** Pointer to the ICH Intel HD Audio Controller state. */
491typedef HDASTATE *PHDASTATE;
492
493#define ISD0FMT_TO_AUDIO_SELECTOR(pThis) \
494 ( AUDIO_FORMAT_SELECTOR(&(pThis)->Codec, In, SDFMT_BASE_RATE(pThis, 0), SDFMT_MULT(pThis, 0), SDFMT_DIV(pThis, 0)) )
495#define OSD0FMT_TO_AUDIO_SELECTOR(pThis) \
496 ( AUDIO_FORMAT_SELECTOR(&(pThis)->Codec, Out, SDFMT_BASE_RATE(pThis, 4), SDFMT_MULT(pThis, 4), SDFMT_DIV(pThis, 4)) )
497
498
499/*******************************************************************************
500* Internal Functions *
501*******************************************************************************/
502static FNPDMDEVRESET hdaReset;
503
504static int hdaRegReadUnimplemented(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
505static int hdaRegWriteUnimplemented(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
506static int hdaRegReadGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
507static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
508static int hdaRegReadSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
509static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
510static int hdaRegReadGCAP(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
511static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
512static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
513static int hdaRegWriteINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
514static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
515static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
516static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
517static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
518static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
519static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
520static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
521static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
522static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
523static int hdaRegReadSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
524
525static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
526static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
527static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
528static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
529static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
530static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
531static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
532static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
533static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
534static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
535static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
536static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
537static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
538static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
539static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
540static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
541
542DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
543 PHDASTREAMTRANSFERDESC pStreamDesc);
544static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc);
545#ifdef LOG_ENABLED
546static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA);
547#endif
548
549
550/*******************************************************************************
551* Global Variables *
552*******************************************************************************/
553/* see 302349 p 6.2*/
554static const struct HDAREGDESC
555{
556 /** Register offset in the register space. */
557 uint32_t offset;
558 /** Size in bytes. Registers of size > 4 are in fact tables. */
559 uint32_t size;
560 /** Readable bits. */
561 uint32_t readable;
562 /** Writable bits. */
563 uint32_t writable;
564 /** Read callback. */
565 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
566 /** Write callback. */
567 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
568 /** Abbreviated name. */
569 const char *abbrev;
570 /** Full name. */
571 const char *name;
572} g_aHdaRegMap[HDA_NREGS] =
573{
574 /* offset size read mask write mask read callback write callback abbrev full name */
575 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
576 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadGCAP , hdaRegWriteUnimplemented, "GCAP" , "Global Capabilities" },
577 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMIN" , "Minor Version" },
578 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "VMAJ" , "Major Version" },
579 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "OUTPAY" , "Output Payload Capabilities" },
580 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimplemented, "INPAY" , "Input Payload Capabilities" },
581 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadGCTL , hdaRegWriteGCTL , "GCTL" , "Global Control" },
582 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , "WAKEEN" , "Wake Enable" },
583 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , "STATESTS" , "State Change Status" },
584 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimplemented, hdaRegWriteUnimplemented, "GSTS" , "Global Status" },
585 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteU32 , "INTCTL" , "Interrupt Control" },
586 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadINTSTS , hdaRegWriteUnimplemented, "INTSTS" , "Interrupt Status" },
587 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimplemented, "WALCLK" , "Wall Clock Counter" },
588 /// @todo r=michaln: Doesn't the SSYNC register need to actually stop the stream(s)?
589 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , "SSYNC" , "Stream Synchronization" },
590 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "CORBLBASE" , "CORB Lower Base Address" },
591 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "CORBUBASE" , "CORB Upper Base Address" },
592 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , "CORBWP" , "CORB Write Pointer" },
593#ifdef OLD_REGISTER_TABLE
594 { 0x0004A, 0x00002, 0x000000FF, 0x000080FF, hdaRegReadU8 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
595#else /** @todo 18.2.17 indicates that the 15th bit can be read as well as and written. hdaRegReadU8 is wrong, a special reader should be used. */
596 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , "CORBRP" , "CORB Read Pointer" },
597#endif
598 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , "CORBCTL" , "CORB Control" },
599 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , "CORBSTS" , "CORB Status" },
600 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "CORBSIZE" , "CORB Size" },
601 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , "RIRBLBASE" , "RIRB Lower Base Address" },
602 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "RIRBUBASE" , "RIRB Upper Base Address" },
603 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , "RIRBWP" , "RIRB Write Pointer" },
604 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , "RINTCNT" , "Response Interrupt Count" },
605 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , "RIRBCTL" , "RIRB Control" },
606 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , "RIRBSTS" , "RIRB Status" },
607 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimplemented, "RIRBSIZE" , "RIRB Size" },
608 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "IC" , "Immediate Command" },
609 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimplemented, "IR" , "Immediate Response" },
610#ifdef OLD_REGISTER_TABLE
611 { 0x00068, 0x00004, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
612#else /* 18.2.30 as well as the table says 16-bit. Linux accesses it as a 16-bit register. */
613 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , "IRS" , "Immediate Command Status" },
614#endif
615 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , "DPLBASE" , "DMA Position Lower Base" },
616 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , "DPUBASE" , "DMA Position Upper Base" },
617
618 { 0x00080, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD0CTL" , "Input Stream Descriptor 0 (ICD0) Control" },
619 { 0x00083, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD0STS" , "ISD0 Status" },
620 { 0x00084, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD0LPIB" , "ISD0 Link Position In Buffer" },
621 { 0x00088, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD0CBL" , "ISD0 Cyclic Buffer Length" },
622 { 0x0008C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD0LVI" , "ISD0 Last Valid Index" },
623 { 0x0008E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD0FIFOW", "ISD0 FIFO Watermark" },
624 { 0x00090, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD0FIFOS", "ISD0 FIFO Size" },
625 { 0x00092, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD0FMT" , "ISD0 Format" },
626 { 0x00098, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD0BDPL" , "ISD0 Buffer Descriptor List Pointer-Lower Base Address" },
627 { 0x0009C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD0BDPU" , "ISD0 Buffer Descriptor List Pointer-Upper Base Address" },
628
629 { 0x000A0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD1CTL" , "Input Stream Descriptor 1 (ISD1) Control" },
630 { 0x000A3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD1STS" , "ISD1 Status" },
631 { 0x000A4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD1LPIB" , "ISD1 Link Position In Buffer" },
632 { 0x000A8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD1CBL" , "ISD1 Cyclic Buffer Length" },
633 { 0x000AC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD1LVI" , "ISD1 Last Valid Index" },
634 { 0x000AE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD1FIFOW", "ISD1 FIFO Watermark" },
635 { 0x000B0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD1FIFOS", "ISD1 FIFO Size" },
636 { 0x000B2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD1FMT" , "ISD1 Format" },
637 { 0x000B8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD1BDPL" , "ISD1 Buffer Descriptor List Pointer-Lower Base Address" },
638 { 0x000BC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD1BDPU" , "ISD1 Buffer Descriptor List Pointer-Upper Base Address" },
639
640 { 0x000C0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD2CTL" , "Input Stream Descriptor 2 (ISD2) Control" },
641 { 0x000C3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD2STS" , "ISD2 Status" },
642 { 0x000C4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD2LPIB" , "ISD2 Link Position In Buffer" },
643 { 0x000C8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD2CBL" , "ISD2 Cyclic Buffer Length" },
644 { 0x000CC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD2LVI" , "ISD2 Last Valid Index" },
645 { 0x000CE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "ISD2FIFOW", "ISD2 FIFO Watermark" },
646 { 0x000D0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD2FIFOS", "ISD2 FIFO Size" },
647 { 0x000D2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD2FMT" , "ISD2 Format" },
648 { 0x000D8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD2BDPL" , "ISD2 Buffer Descriptor List Pointer-Lower Base Address" },
649 { 0x000DC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD2BDPU" , "ISD2 Buffer Descriptor List Pointer-Upper Base Address" },
650
651 { 0x000E0, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "ISD3CTL" , "Input Stream Descriptor 3 (ISD3) Control" },
652 { 0x000E3, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "ISD3STS" , "ISD3 Status" },
653 { 0x000E4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "ISD3LPIB" , "ISD3 Link Position In Buffer" },
654 { 0x000E8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "ISD3CBL" , "ISD3 Cyclic Buffer Length" },
655 { 0x000EC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "ISD3LVI" , "ISD3 Last Valid Index" },
656 { 0x000EE, 0x00002, 0x00000005, 0x00000005, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOW", "ISD3 FIFO Watermark" },
657 { 0x000F0, 0x00002, 0x000000FF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , "ISD3FIFOS", "ISD3 FIFO Size" },
658 { 0x000F2, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "ISD3FMT" , "ISD3 Format" },
659 { 0x000F8, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "ISD3BDPL" , "ISD3 Buffer Descriptor List Pointer-Lower Base Address" },
660 { 0x000FC, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "ISD3BDPU" , "ISD3 Buffer Descriptor List Pointer-Upper Base Address" },
661
662 { 0x00100, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadSDCTL , hdaRegWriteSDCTL , "OSD0CTL" , "Input Stream Descriptor 0 (OSD0) Control" },
663 { 0x00103, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD0STS" , "OSD0 Status" },
664 { 0x00104, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD0LPIB" , "OSD0 Link Position In Buffer" },
665 { 0x00108, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD0CBL" , "OSD0 Cyclic Buffer Length" },
666 { 0x0010C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD0LVI" , "OSD0 Last Valid Index" },
667 { 0x0010E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD0FIFOW", "OSD0 FIFO Watermark" },
668 { 0x00110, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD0FIFOS", "OSD0 FIFO Size" },
669 { 0x00112, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD0FMT" , "OSD0 Format" },
670 { 0x00118, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD0BDPL" , "OSD0 Buffer Descriptor List Pointer-Lower Base Address" },
671 { 0x0011C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD0BDPU" , "OSD0 Buffer Descriptor List Pointer-Upper Base Address" },
672
673 { 0x00120, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD1CTL" , "Input Stream Descriptor 0 (OSD1) Control" },
674 { 0x00123, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD1STS" , "OSD1 Status" },
675 { 0x00124, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD1LPIB" , "OSD1 Link Position In Buffer" },
676 { 0x00128, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD1CBL" , "OSD1 Cyclic Buffer Length" },
677 { 0x0012C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD1LVI" , "OSD1 Last Valid Index" },
678 { 0x0012E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD1FIFOW", "OSD1 FIFO Watermark" },
679 { 0x00130, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD1FIFOS", "OSD1 FIFO Size" },
680 { 0x00132, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD1FMT" , "OSD1 Format" },
681 { 0x00138, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD1BDPL" , "OSD1 Buffer Descriptor List Pointer-Lower Base Address" },
682 { 0x0013C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD1BDPU" , "OSD1 Buffer Descriptor List Pointer-Upper Base Address" },
683
684 { 0x00140, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD2CTL" , "Input Stream Descriptor 0 (OSD2) Control" },
685 { 0x00143, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD2STS" , "OSD2 Status" },
686 { 0x00144, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD2LPIB" , "OSD2 Link Position In Buffer" },
687 { 0x00148, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD2CBL" , "OSD2 Cyclic Buffer Length" },
688 { 0x0014C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD2LVI" , "OSD2 Last Valid Index" },
689 { 0x0014E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD2FIFOW", "OSD2 FIFO Watermark" },
690 { 0x00150, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD2FIFOS", "OSD2 FIFO Size" },
691 { 0x00152, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD2FMT" , "OSD2 Format" },
692 { 0x00158, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD2BDPL" , "OSD2 Buffer Descriptor List Pointer-Lower Base Address" },
693 { 0x0015C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD2BDPU" , "OSD2 Buffer Descriptor List Pointer-Upper Base Address" },
694
695 { 0x00160, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , "OSD3CTL" , "Input Stream Descriptor 0 (OSD3) Control" },
696 { 0x00163, 0x00001, 0x0000001C, 0x0000003C, hdaRegReadU8 , hdaRegWriteSDSTS , "OSD3STS" , "OSD3 Status" },
697 { 0x00164, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadU32 , hdaRegWriteU32 , "OSD3LPIB" , "OSD3 Link Position In Buffer" },
698 { 0x00168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , "OSD3CBL" , "OSD3 Cyclic Buffer Length" },
699 { 0x0016C, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16 , hdaRegWriteSDLVI , "OSD3LVI" , "OSD3 Last Valid Index" },
700 { 0x0016E, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16 , hdaRegWriteSDFIFOW , "OSD3FIFOW", "OSD3 FIFO Watermark" },
701 { 0x00170, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteSDFIFOS , "OSD3FIFOS", "OSD3 FIFO Size" },
702 { 0x00172, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16 , hdaRegWriteSDFMT , "OSD3FMT" , "OSD3 Format" },
703 { 0x00178, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteSDBDPL , "OSD3BDPL" , "OSD3 Buffer Descriptor List Pointer-Lower Base Address" },
704 { 0x0017C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteSDBDPU , "OSD3BDPU" , "OSD3 Buffer Descriptor List Pointer-Upper Base Address" },
705};
706
707/**
708 * HDA register aliases (HDA spec 3.3.45).
709 * @remarks Sorted by offReg.
710 */
711static const struct
712{
713 /** The alias register offset. */
714 uint32_t offReg;
715 /** The register index. */
716 int idxAlias;
717} g_aHdaRegAliases[] =
718{
719 { 0x2084, HDA_REG_IND_NAME(SD0LPIB) },
720 { 0x20a4, HDA_REG_IND_NAME(SD1LPIB) },
721 { 0x20c4, HDA_REG_IND_NAME(SD2LPIB) },
722 { 0x20e4, HDA_REG_IND_NAME(SD3LPIB) },
723 { 0x2104, HDA_REG_IND_NAME(SD4LPIB) },
724 { 0x2124, HDA_REG_IND_NAME(SD5LPIB) },
725 { 0x2144, HDA_REG_IND_NAME(SD6LPIB) },
726 { 0x2164, HDA_REG_IND_NAME(SD7LPIB) },
727};
728
729
730/** HDABDLEDESC field descriptors the v3+ saved state. */
731static SSMFIELD const g_aHdaBDLEDescFields[] =
732{
733 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
734 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
735 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
736 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
737 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
738 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
739 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
740 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
741 SSMFIELD_ENTRY_TERM()
742};
743
744/** HDABDLEDESC field descriptors the v1 and v2 saved state. */
745static SSMFIELD const g_aHdaBDLEDescFieldsOld[] =
746{
747 SSMFIELD_ENTRY( HDABDLEDESC, u64BdleCviAddr),
748 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleMaxCvi),
749 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCvi),
750 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviLen),
751 SSMFIELD_ENTRY( HDABDLEDESC, u32BdleCviPos),
752 SSMFIELD_ENTRY( HDABDLEDESC, fBdleCviIoc),
753 SSMFIELD_ENTRY_PAD_HC_AUTO(3, 3),
754 SSMFIELD_ENTRY( HDABDLEDESC, cbUnderFifoW),
755 SSMFIELD_ENTRY( HDABDLEDESC, au8HdaBuffer),
756 SSMFIELD_ENTRY_TERM()
757};
758
759/**
760 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
761 */
762static uint32_t const g_afMasks[5] =
763{
764 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
765};
766
767
768DECLINLINE(void) hdaUpdatePosBuf(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
769{
770 if (pThis->u64DPBase & DPBASE_ENABLED)
771 PDMDevHlpPhysWrite(pThis->pDevIns,
772 (pThis->u64DPBase & DPBASE_ADDR_MASK) + pStreamDesc->u8Strm * 8,
773 pStreamDesc->pu32Lpib, sizeof(uint32_t));
774}
775DECLINLINE(uint32_t) hdaFifoWToSz(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc)
776{
777#if 0
778 switch(HDA_STREAM_REG2(pThis, FIFOW, pStreamDesc->u8Strm))
779 {
780 case HDA_SDFIFOW_8B: return 8;
781 case HDA_SDFIFOW_16B: return 16;
782 case HDA_SDFIFOW_32B: return 32;
783 default:
784 AssertMsgFailed(("hda: unsupported value (%x) in SDFIFOW(,%d)\n", HDA_REG_IND(pThis, pStreamDesc->u8Strm), pStreamDesc->u8Strm));
785 }
786#endif
787 return 0;
788}
789
790static int hdaProcessInterrupt(PHDASTATE pThis)
791{
792#define IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, num) \
793 ( INTCTL_SX((pThis), num) \
794 && (SDSTS(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
795 bool fIrq = false;
796 if ( INTCTL_CIE(pThis)
797 && ( RIRBSTS_RINTFL(pThis)
798 || RIRBSTS_RIRBOIS(pThis)
799 || (STATESTS(pThis) & WAKEEN(pThis))))
800 fIrq = true;
801
802 if ( IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 0)
803 || IS_INTERRUPT_OCCURED_AND_ENABLED(pThis, 4))
804 fIrq = true;
805
806 if (INTCTL_GIE(pThis))
807 {
808 Log(("hda: irq %s\n", fIrq ? "asserted" : "deasserted"));
809 PDMDevHlpPCISetIrq(pThis->pDevIns, 0 , fIrq);
810 }
811 return VINF_SUCCESS;
812}
813
814/**
815 * Looks up a register at the exact offset given by @a offReg.
816 *
817 * @returns Register index on success, -1 if not found.
818 * @param pThis The HDA device state.
819 * @param offReg The register offset.
820 */
821static int hdaRegLookup(PHDASTATE pThis, uint32_t offReg)
822{
823 /*
824 * Aliases.
825 */
826 if (offReg >= g_aHdaRegAliases[0].offReg)
827 {
828 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
829 if (offReg == g_aHdaRegAliases[i].offReg)
830 return g_aHdaRegAliases[i].idxAlias;
831 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
832 return -1;
833 }
834
835 /*
836 * Binary search the
837 */
838 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
839 int idxLow = 0;
840 for (;;)
841 {
842 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
843 if (offReg < g_aHdaRegMap[idxMiddle].offset)
844 {
845 if (idxLow == idxMiddle)
846 break;
847 idxEnd = idxMiddle;
848 }
849 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
850 {
851 idxLow = idxMiddle + 1;
852 if (idxLow >= idxEnd)
853 break;
854 }
855 else
856 return idxMiddle;
857 }
858
859#ifdef RT_STRICT
860 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
861 Assert(g_aHdaRegMap[i].offset != offReg);
862#endif
863 return -1;
864}
865
866/**
867 * Looks up a register covering the offset given by @a offReg.
868 *
869 * @returns Register index on success, -1 if not found.
870 * @param pThis The HDA device state.
871 * @param offReg The register offset.
872 */
873static int hdaRegLookupWithin(PHDASTATE pThis, uint32_t offReg)
874{
875 /*
876 * Aliases.
877 */
878 if (offReg >= g_aHdaRegAliases[0].offReg)
879 {
880 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
881 {
882 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
883 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
884 return g_aHdaRegAliases[i].idxAlias;
885 }
886 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
887 return -1;
888 }
889
890 /*
891 * Binary search the
892 */
893 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
894 int idxLow = 0;
895 for (;;)
896 {
897 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
898 if (offReg < g_aHdaRegMap[idxMiddle].offset)
899 {
900 if (idxLow == idxMiddle)
901 break;
902 idxEnd = idxMiddle;
903 }
904 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
905 {
906 idxLow = idxMiddle + 1;
907 if (idxLow >= idxEnd)
908 break;
909 }
910 else
911 return idxMiddle;
912 }
913
914#ifdef RT_STRICT
915 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
916 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
917#endif
918 return -1;
919}
920
921
922static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
923{
924 int rc = VINF_SUCCESS;
925 if (fLocal)
926 {
927 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
928 rc = PDMDevHlpPhysRead(pThis->pDevIns, pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
929 if (RT_FAILURE(rc))
930 AssertRCReturn(rc, rc);
931#ifdef DEBUG_CMD_BUFFER
932 uint8_t i = 0;
933 do
934 {
935 Log(("hda: corb%02x: ", i));
936 uint8_t j = 0;
937 do
938 {
939 const char *prefix;
940 if ((i + j) == CORBRP(pThis))
941 prefix = "[R]";
942 else if ((i + j) == CORBWP(pThis))
943 prefix = "[W]";
944 else
945 prefix = " "; /* three spaces */
946 Log(("%s%08x", prefix, pThis->pu32CorbBuf[i + j]));
947 j++;
948 } while (j < 8);
949 Log(("\n"));
950 i += 8;
951 } while(i != 0);
952#endif
953 }
954 else
955 {
956 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
957 rc = PDMDevHlpPhysWrite(pThis->pDevIns, pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
958 if (RT_FAILURE(rc))
959 AssertRCReturn(rc, rc);
960#ifdef DEBUG_CMD_BUFFER
961 uint8_t i = 0;
962 do {
963 Log(("hda: rirb%02x: ", i));
964 uint8_t j = 0;
965 do {
966 const char *prefix;
967 if ((i + j) == RIRBWP(pThis))
968 prefix = "[W]";
969 else
970 prefix = " ";
971 Log((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
972 } while (++j < 8);
973 Log(("\n"));
974 i += 8;
975 } while (i != 0);
976#endif
977 }
978 return rc;
979}
980
981static int hdaCORBCmdProcess(PHDASTATE pThis)
982{
983 int rc;
984 uint8_t corbRp;
985 uint8_t corbWp;
986 uint8_t rirbWp;
987
988 PFNHDACODECVERBPROCESSOR pfn = (PFNHDACODECVERBPROCESSOR)NULL;
989
990 rc = hdaCmdSync(pThis, true);
991 if (RT_FAILURE(rc))
992 AssertRCReturn(rc, rc);
993 corbRp = CORBRP(pThis);
994 corbWp = CORBWP(pThis);
995 rirbWp = RIRBWP(pThis);
996 Assert((corbWp != corbRp));
997 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pThis), CORBWP(pThis), RIRBWP(pThis)));
998 while (corbRp != corbWp)
999 {
1000 uint32_t cmd;
1001 uint64_t resp;
1002 pfn = NULL;
1003 corbRp++;
1004 cmd = pThis->pu32CorbBuf[corbRp];
1005 rc = pThis->Codec.pfnLookup(&pThis->Codec, cmd, &pfn);
1006 if (RT_FAILURE(rc))
1007 AssertRCReturn(rc, rc);
1008 Assert(pfn);
1009 (rirbWp)++;
1010
1011 if (RT_LIKELY(pfn))
1012 rc = pfn(&pThis->Codec, cmd, &resp);
1013 else
1014 rc = VERR_INVALID_FUNCTION;
1015
1016 if (RT_FAILURE(rc))
1017 AssertRCReturn(rc, rc);
1018 Log(("hda: verb:%08x->%016lx\n", cmd, resp));
1019 if ( (resp & CODEC_RESPONSE_UNSOLICITED)
1020 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1021 {
1022 Log(("hda: unexpected unsolicited response.\n"));
1023 pThis->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
1024 return rc;
1025 }
1026 pThis->pu64RirbBuf[rirbWp] = resp;
1027 pThis->u8Counter++;
1028 if (pThis->u8Counter == RINTCNT_N(pThis))
1029 break;
1030 }
1031 pThis->au32Regs[ICH6_HDA_REG_CORBRP] = corbRp;
1032 pThis->au32Regs[ICH6_HDA_REG_RIRBWP] = rirbWp;
1033 rc = hdaCmdSync(pThis, false);
1034 Log(("hda: CORB(RP:%x, WP:%x) RIRBWP:%x\n", CORBRP(pThis), CORBWP(pThis), RIRBWP(pThis)));
1035 if (RIRBCTL_RIRB_RIC(pThis))
1036 {
1037 RIRBSTS((pThis)) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1038 pThis->u8Counter = 0;
1039 rc = hdaProcessInterrupt(pThis);
1040 }
1041 if (RT_FAILURE(rc))
1042 AssertRCReturn(rc, rc);
1043 return rc;
1044}
1045
1046static void hdaStreamReset(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc, uint8_t u8Strm)
1047{
1048 Log(("hda: reset of stream (%d) started\n", u8Strm));
1049 Assert(( pThis
1050 && pBdle
1051 && pStreamDesc
1052 && u8Strm <= 7));
1053 memset(pBdle, 0, sizeof(HDABDLEDESC));
1054 *pStreamDesc->pu32Lpib = 0;
1055 *pStreamDesc->pu32Sts = 0;
1056 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1057 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRCT bit */
1058 HDA_STREAM_REG2(pThis, CTL, u8Strm) = 0x40000 | (HDA_STREAM_REG2(pThis, CTL, u8Strm) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1059
1060 /* ICH6 defines default values (0x77 for input and 0xBF for output descriptors) of FIFO size. 18.2.39 */
1061 HDA_STREAM_REG2(pThis, FIFOS, u8Strm) = u8Strm < 4 ? HDA_SDINFIFO_120B : HDA_SDONFIFO_192B;
1062 HDA_STREAM_REG2(pThis, FIFOW, u8Strm) = u8Strm < 4 ? HDA_SDFIFOW_8B : HDA_SDFIFOW_32B;
1063 HDA_STREAM_REG2(pThis, CBL, u8Strm) = 0;
1064 HDA_STREAM_REG2(pThis, LVI, u8Strm) = 0;
1065 HDA_STREAM_REG2(pThis, FMT, u8Strm) = 0;
1066 HDA_STREAM_REG2(pThis, BDPU, u8Strm) = 0;
1067 HDA_STREAM_REG2(pThis, BDPL, u8Strm) = 0;
1068 Log(("hda: reset of stream (%d) finished\n", u8Strm));
1069}
1070
1071
1072/* Register access handlers. */
1073
1074static int hdaRegReadUnimplemented(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1075{
1076 *pu32Value = 0;
1077 return VINF_SUCCESS;
1078}
1079
1080static int hdaRegWriteUnimplemented(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1081{
1082 return VINF_SUCCESS;
1083}
1084
1085/* U8 */
1086static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1087{
1088 Assert(((pThis->au32Regs[iReg] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1089 return hdaRegReadU32(pThis, iReg, pu32Value);
1090}
1091
1092static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1093{
1094 Assert((u32Value & 0xffffff00) == 0);
1095 return hdaRegWriteU32(pThis, iReg, u32Value);
1096}
1097
1098/* U16 */
1099static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1100{
1101 Assert(((pThis->au32Regs[iReg] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1102 return hdaRegReadU32(pThis, iReg, pu32Value);
1103}
1104
1105static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1106{
1107 Assert((u32Value & 0xffff0000) == 0);
1108 return hdaRegWriteU32(pThis, iReg, u32Value);
1109}
1110
1111/* U24 */
1112static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1113{
1114 Assert(((pThis->au32Regs[iReg] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
1115 return hdaRegReadU32(pThis, iReg, pu32Value);
1116}
1117
1118static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1119{
1120 Assert((u32Value & 0xff000000) == 0);
1121 return hdaRegWriteU32(pThis, iReg, u32Value);
1122}
1123
1124/* U32 */
1125static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1126{
1127 *pu32Value = pThis->au32Regs[iReg] & g_aHdaRegMap[iReg].readable;
1128 return VINF_SUCCESS;
1129}
1130
1131static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1132{
1133 pThis->au32Regs[iReg] = (u32Value & g_aHdaRegMap[iReg].writable)
1134 | (pThis->au32Regs[iReg] & ~g_aHdaRegMap[iReg].writable);
1135 return VINF_SUCCESS;
1136}
1137
1138static int hdaRegReadGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1139{
1140 return hdaRegReadU32(pThis, iReg, pu32Value);
1141}
1142
1143static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1144{
1145 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
1146 {
1147 /* exit reset state */
1148 GCTL(pThis) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1149 pThis->fInReset = false;
1150 }
1151 else
1152 {
1153 /* enter reset state*/
1154 if ( HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)
1155 || HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA))
1156 {
1157 Log(("hda: HDA enters in reset with DMA(RIRB:%s, CORB:%s)\n",
1158 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
1159 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
1160 }
1161 hdaReset(pThis->pDevIns);
1162 GCTL(pThis) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
1163 pThis->fInReset = true;
1164 }
1165 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
1166 {
1167 /* Flush: GSTS:1 set, see 6.2.6*/
1168 GSTS(pThis) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* set the flush state */
1169 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6)*/
1170 }
1171 return VINF_SUCCESS;
1172}
1173
1174static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1175{
1176 uint32_t v = pThis->au32Regs[iReg];
1177 uint32_t nv = u32Value & ICH6_HDA_STATES_SCSF;
1178 pThis->au32Regs[iReg] &= ~(v & nv); /* write of 1 clears corresponding bit */
1179 return VINF_SUCCESS;
1180}
1181
1182static int hdaRegReadINTSTS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1183{
1184 uint32_t v = 0;
1185 if ( RIRBSTS_RIRBOIS(pThis)
1186 || RIRBSTS_RINTFL(pThis)
1187 || HDA_REG_FLAG_VALUE(pThis, CORBSTS, CMEI)
1188 || STATESTS(pThis))
1189 v |= RT_BIT(30);
1190#define HDA_IS_STREAM_EVENT(pThis, stream) \
1191 ( (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1192 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1193 || (SDSTS((pThis),stream) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
1194#define MARK_STREAM(pThis, stream, v) do { (v) |= HDA_IS_STREAM_EVENT((pThis),stream) ? RT_BIT((stream)) : 0; } while(0)
1195 MARK_STREAM(pThis, 0, v);
1196 MARK_STREAM(pThis, 1, v);
1197 MARK_STREAM(pThis, 2, v);
1198 MARK_STREAM(pThis, 3, v);
1199 MARK_STREAM(pThis, 4, v);
1200 MARK_STREAM(pThis, 5, v);
1201 MARK_STREAM(pThis, 6, v);
1202 MARK_STREAM(pThis, 7, v);
1203 v |= v ? RT_BIT(31) : 0;
1204 *pu32Value = v;
1205 return VINF_SUCCESS;
1206}
1207
1208static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1209{
1210 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
1211 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->pDevIns)
1212 - pThis->u64BaseTS, 24, 1000);
1213 return VINF_SUCCESS;
1214}
1215
1216static int hdaRegReadGCAP(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1217{
1218 return hdaRegReadU16(pThis, iReg, pu32Value);
1219}
1220
1221static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1222{
1223 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
1224 CORBRP(pThis) = 0;
1225#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
1226 else
1227 return hdaRegWriteU8(pThis, iReg, u32Value);
1228#endif
1229 return VINF_SUCCESS;
1230}
1231
1232static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1233{
1234 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1235 AssertRC(rc);
1236 if ( CORBWP(pThis) != CORBRP(pThis)
1237 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
1238 return hdaCORBCmdProcess(pThis);
1239 return rc;
1240}
1241
1242static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1243{
1244 uint32_t v = CORBSTS(pThis);
1245 CORBSTS(pThis) &= ~(v & u32Value);
1246 return VINF_SUCCESS;
1247}
1248
1249static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1250{
1251 int rc;
1252 rc = hdaRegWriteU16(pThis, iReg, u32Value);
1253 if (RT_FAILURE(rc))
1254 AssertRCReturn(rc, rc);
1255 if (CORBWP(pThis) == CORBRP(pThis))
1256 return VINF_SUCCESS;
1257 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1258 return VINF_SUCCESS;
1259 rc = hdaCORBCmdProcess(pThis);
1260 return rc;
1261}
1262
1263static int hdaRegReadSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1264{
1265 return hdaRegReadU24(pThis, iReg, pu32Value);
1266}
1267
1268static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1269{
1270 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1271 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
1272 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1273 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1274
1275 if (fInReset)
1276 {
1277 /*
1278 * Assert!!! Guest is resetting HDA's stream, we're expecting guest will mark stream as exit
1279 * from reset
1280 */
1281 Assert((!fReset));
1282 Log(("hda: guest initiated exit of stream reset.\n"));
1283 }
1284 else if (fReset)
1285 {
1286 /*
1287 * Assert!!! ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset.
1288 */
1289 uint8_t u8Strm = 0;
1290 PHDABDLEDESC pBdle = NULL;
1291 HDASTREAMTRANSFERDESC StreamDesc;
1292 Assert((!fInRun && !fRun));
1293 switch (iReg)
1294 {
1295 case ICH6_HDA_REG_SD0CTL:
1296 u8Strm = 0;
1297 pBdle = &pThis->StInBdle;
1298 break;
1299 case ICH6_HDA_REG_SD4CTL:
1300 u8Strm = 4;
1301 pBdle = &pThis->StOutBdle;
1302 break;
1303 default:
1304 Log(("hda: changing SRST bit on non-attached stream\n"));
1305 return hdaRegWriteU24(pThis, iReg, u32Value);
1306 }
1307 Log(("hda: guest initiated enter to stream reset.\n"));
1308 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
1309 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
1310 }
1311 else
1312 {
1313 /* we enter here to change DMA states only */
1314 if ( (fInRun && !fRun)
1315 || (fRun && !fInRun))
1316 {
1317 Assert((!fReset && !fInReset));
1318 switch (iReg)
1319 {
1320 case ICH6_HDA_REG_SD0CTL:
1321 AUD_set_active_in(pThis->Codec.SwVoiceIn, fRun);
1322 break;
1323 case ICH6_HDA_REG_SD4CTL:
1324 AUD_set_active_out(pThis->Codec.SwVoiceOut, fRun);
1325 break;
1326 default:
1327 Log(("hda: changing RUN bit on non-attached stream\n"));
1328 break;
1329 }
1330 }
1331 }
1332
1333 return hdaRegWriteU24(pThis, iReg, u32Value);
1334}
1335
1336static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1337{
1338 uint32_t v = HDA_REG_IND(pThis, iReg);
1339 v &= ~(u32Value & v);
1340 HDA_REG_IND(pThis, iReg) = v;
1341 hdaProcessInterrupt(pThis);
1342 return VINF_SUCCESS;
1343}
1344
1345static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1346{
1347 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1348 if (RT_FAILURE(rc))
1349 AssertRCReturn(rc, VINF_SUCCESS);
1350 return rc;
1351}
1352
1353static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1354{
1355 switch (u32Value)
1356 {
1357 case HDA_SDFIFOW_8B:
1358 case HDA_SDFIFOW_16B:
1359 case HDA_SDFIFOW_32B:
1360 return hdaRegWriteU16(pThis, iReg, u32Value);
1361 default:
1362 Log(("hda: Attempt to store unsupported value(%x) in SDFIFOW\n", u32Value));
1363 return hdaRegWriteU16(pThis, iReg, HDA_SDFIFOW_32B);
1364 }
1365 return VINF_SUCCESS;
1366}
1367
1368/**
1369 * @note This method could be called for changing value on Output Streams
1370 * only (ICH6 datasheet 18.2.39)
1371 */
1372static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1373{
1374 switch (iReg)
1375 {
1376 /* SDInFIFOS is RO, n=0-3 */
1377 case ICH6_HDA_REG_SD0FIFOS:
1378 case ICH6_HDA_REG_SD1FIFOS:
1379 case ICH6_HDA_REG_SD2FIFOS:
1380 case ICH6_HDA_REG_SD3FIFOS:
1381 Log(("hda: Guest tries change value of FIFO size of Input Stream\n"));
1382 return VINF_SUCCESS;
1383 case ICH6_HDA_REG_SD4FIFOS:
1384 case ICH6_HDA_REG_SD5FIFOS:
1385 case ICH6_HDA_REG_SD6FIFOS:
1386 case ICH6_HDA_REG_SD7FIFOS:
1387 switch(u32Value)
1388 {
1389 case HDA_SDONFIFO_16B:
1390 case HDA_SDONFIFO_32B:
1391 case HDA_SDONFIFO_64B:
1392 case HDA_SDONFIFO_128B:
1393 case HDA_SDONFIFO_192B:
1394 return hdaRegWriteU16(pThis, iReg, u32Value);
1395
1396 case HDA_SDONFIFO_256B:
1397 Log(("hda: 256-bit is unsupported, HDA is switched into 192-bit mode\n"));
1398 default:
1399 return hdaRegWriteU16(pThis, iReg, HDA_SDONFIFO_192B);
1400 }
1401 return VINF_SUCCESS;
1402 default:
1403 AssertMsgFailed(("Something weird happened with register lookup routine"));
1404 }
1405 return VINF_SUCCESS;
1406}
1407
1408static void hdaSdFmtToAudSettings(uint32_t u32SdFmt, audsettings_t *pAudSetting)
1409{
1410 Assert((pAudSetting));
1411#define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
1412 uint32_t u32Hz = (u32SdFmt & ICH6_HDA_SDFMT_BASE_RATE_SHIFT) ? 44100 : 48000;
1413 uint32_t u32HzMult = 1;
1414 uint32_t u32HzDiv = 1;
1415 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_MULT_MASK, ICH6_HDA_SDFMT_MULT_SHIFT))
1416 {
1417 case 0: u32HzMult = 1; break;
1418 case 1: u32HzMult = 2; break;
1419 case 2: u32HzMult = 3; break;
1420 case 3: u32HzMult = 4; break;
1421 default:
1422 Log(("hda: unsupported multiplier %x\n", u32SdFmt));
1423 }
1424 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_DIV_MASK, ICH6_HDA_SDFMT_DIV_SHIFT))
1425 {
1426 case 0: u32HzDiv = 1; break;
1427 case 1: u32HzDiv = 2; break;
1428 case 2: u32HzDiv = 3; break;
1429 case 3: u32HzDiv = 4; break;
1430 case 4: u32HzDiv = 5; break;
1431 case 5: u32HzDiv = 6; break;
1432 case 6: u32HzDiv = 7; break;
1433 case 7: u32HzDiv = 8; break;
1434 }
1435 pAudSetting->freq = u32Hz * u32HzMult / u32HzDiv;
1436
1437 switch (EXTRACT_VALUE(u32SdFmt, ICH6_HDA_SDFMT_BITS_MASK, ICH6_HDA_SDFMT_BITS_SHIFT))
1438 {
1439 case 0:
1440 Log(("hda: %s requested 8-bit\n", __FUNCTION__));
1441 pAudSetting->fmt = AUD_FMT_S8;
1442 break;
1443 case 1:
1444 Log(("hda: %s requested 16-bit\n", __FUNCTION__));
1445 pAudSetting->fmt = AUD_FMT_S16;
1446 break;
1447 case 2:
1448 Log(("hda: %s requested 20-bit\n", __FUNCTION__));
1449 break;
1450 case 3:
1451 Log(("hda: %s requested 24-bit\n", __FUNCTION__));
1452 break;
1453 case 4:
1454 Log(("hda: %s requested 32-bit\n", __FUNCTION__));
1455 pAudSetting->fmt = AUD_FMT_S32;
1456 break;
1457 default:
1458 AssertMsgFailed(("Unsupported"));
1459 }
1460 pAudSetting->nchannels = (u32SdFmt & 0xf) + 1;
1461 pAudSetting->fmt = AUD_FMT_S16;
1462 pAudSetting->endianness = 0;
1463#undef EXTRACT_VALUE
1464}
1465
1466static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1467{
1468#ifdef VBOX_WITH_HDA_CODEC_EMU
1469 /** @todo a bit more investigation is required here. */
1470 int rc = 0;
1471 audsettings_t as;
1472 /* no reason to reopen voice with same settings */
1473 if (u32Value == HDA_REG_IND(pThis, iReg))
1474 return VINF_SUCCESS;
1475 hdaSdFmtToAudSettings(u32Value, &as);
1476 switch (iReg)
1477 {
1478 case ICH6_HDA_REG_SD0FMT:
1479 rc = hdaCodecOpenVoice(&pThis->Codec, PI_INDEX, &as);
1480 break;
1481 case ICH6_HDA_REG_SD4FMT:
1482 rc = hdaCodecOpenVoice(&pThis->Codec, PO_INDEX, &as);
1483 break;
1484 default:
1485 Log(("HDA: attempt to change format on %d\n", iReg));
1486 rc = 0;
1487 }
1488 return hdaRegWriteU16(pThis, iReg, u32Value);
1489#else
1490 return hdaRegWriteU16(pThis, iReg, u32Value);
1491#endif
1492}
1493
1494static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1495{
1496 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1497 if (RT_FAILURE(rc))
1498 AssertRCReturn(rc, VINF_SUCCESS);
1499 return rc;
1500}
1501
1502static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1503{
1504 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1505 if (RT_FAILURE(rc))
1506 AssertRCReturn(rc, VINF_SUCCESS);
1507 return rc;
1508}
1509
1510static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1511{
1512 int rc = VINF_SUCCESS;
1513 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
1514 if ( CORBWP(pThis) != CORBRP(pThis)
1515 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
1516 IRS(pThis) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1517
1518 rc = hdaRegReadU32(pThis, iReg, pu32Value);
1519 return rc;
1520}
1521
1522static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1523{
1524 int rc = VINF_SUCCESS;
1525 PFNHDACODECVERBPROCESSOR pfn = NULL;
1526 uint64_t resp;
1527
1528 /*
1529 * if guest set the ICB bit of IRS register, HDA should process the verb in IC register,
1530 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
1531 */
1532 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
1533 && !IRS_ICB(pThis))
1534 {
1535 uint32_t cmd = IC(pThis);
1536 if (CORBWP(pThis) != CORBRP(pThis))
1537 {
1538 /*
1539 * 3.4.3 defines behavior of immediate Command status register.
1540 */
1541 LogRel(("hda: guest attempted process immediate verb (%x) with active CORB\n", cmd));
1542 return rc;
1543 }
1544 IRS(pThis) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
1545 Log(("hda: IC:%x\n", cmd));
1546 rc = pThis->Codec.pfnLookup(&pThis->Codec, cmd, &pfn);
1547 if (RT_FAILURE(rc))
1548 AssertRCReturn(rc, rc);
1549 rc = pfn(&pThis->Codec, cmd, &resp);
1550 if (RT_FAILURE(rc))
1551 AssertRCReturn(rc, rc);
1552 IR(pThis) = (uint32_t)resp;
1553 Log(("hda: IR:%x\n", IR(pThis)));
1554 IRS(pThis) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
1555 IRS(pThis) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
1556 return rc;
1557 }
1558 /*
1559 * Once the guest read the response, it should clean the IRV bit of the IRS register.
1560 */
1561 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
1562 && IRS_IRV(pThis))
1563 IRS(pThis) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
1564 return rc;
1565}
1566
1567static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1568{
1569 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
1570 {
1571 RIRBWP(pThis) = 0;
1572 }
1573 /* The remaining bits are O, see 6.2.22 */
1574 return VINF_SUCCESS;
1575}
1576
1577static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1578{
1579 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1580 if (RT_FAILURE(rc))
1581 AssertRCReturn(rc, rc);
1582 switch(iReg)
1583 {
1584 case ICH6_HDA_REG_CORBLBASE:
1585 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
1586 pThis->u64CORBBase |= pThis->au32Regs[iReg];
1587 break;
1588 case ICH6_HDA_REG_CORBUBASE:
1589 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
1590 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iReg] << 32);
1591 break;
1592 case ICH6_HDA_REG_RIRLBASE:
1593 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
1594 pThis->u64RIRBBase |= pThis->au32Regs[iReg];
1595 break;
1596 case ICH6_HDA_REG_RIRUBASE:
1597 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
1598 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iReg] << 32);
1599 break;
1600 case ICH6_HDA_REG_DPLBASE:
1601 /** @todo: first bit has special meaning */
1602 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
1603 pThis->u64DPBase |= pThis->au32Regs[iReg];
1604 break;
1605 case ICH6_HDA_REG_DPUBASE:
1606 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
1607 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iReg] << 32);
1608 break;
1609 default:
1610 AssertMsgFailed(("Invalid index"));
1611 }
1612 Log(("hda: CORB base:%llx RIRB base: %llx DP base: %llx\n", pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
1613 return rc;
1614}
1615
1616static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1617{
1618 uint8_t v = RIRBSTS(pThis);
1619 RIRBSTS(pThis) &= ~(v & u32Value);
1620
1621 return hdaProcessInterrupt(pThis);
1622}
1623
1624#ifdef LOG_ENABLED
1625static void dump_bd(PHDASTATE pThis, PHDABDLEDESC pBdle, uint64_t u64BaseDMA)
1626{
1627#if 0
1628 uint64_t addr;
1629 uint32_t len;
1630 uint32_t ioc;
1631 uint8_t bdle[16];
1632 uint32_t counter;
1633 uint32_t i;
1634 uint32_t sum = 0;
1635 Assert(pBdle && pBdle->u32BdleMaxCvi);
1636 for (i = 0; i <= pBdle->u32BdleMaxCvi; ++i)
1637 {
1638 PDMDevHlpPhysRead(pThis->pDevIns, u64BaseDMA + i*16, bdle, 16);
1639 addr = *(uint64_t *)bdle;
1640 len = *(uint32_t *)&bdle[8];
1641 ioc = *(uint32_t *)&bdle[12];
1642 Log(("hda: %s bdle[%d] a:%llx, len:%d, ioc:%d\n", (i == pBdle->u32BdleCvi? "[C]": " "), i, addr, len, ioc & 0x1));
1643 sum += len;
1644 }
1645 Log(("hda: sum: %d\n", sum));
1646 for (i = 0; i < 8; ++i)
1647 {
1648 PDMDevHlpPhysRead(pThis->pDevIns, (pThis->u64DPBase & DPBASE_ADDR_MASK) + i*8, &counter, sizeof(&counter));
1649 Log(("hda: %s stream[%d] counter=%x\n", i == SDCTL_NUM(pThis, 4) || i == SDCTL_NUM(pThis, 0)? "[C]": " ",
1650 i , counter));
1651 }
1652#endif
1653}
1654#endif
1655
1656static void hdaFetchBdle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1657{
1658 uint8_t bdle[16];
1659 Assert(( pStreamDesc->u64BaseDMA
1660 && pBdle
1661 && pBdle->u32BdleMaxCvi));
1662 PDMDevHlpPhysRead(pThis->pDevIns, pStreamDesc->u64BaseDMA + pBdle->u32BdleCvi*16, bdle, 16);
1663 pBdle->u64BdleCviAddr = *(uint64_t *)bdle;
1664 pBdle->u32BdleCviLen = *(uint32_t *)&bdle[8];
1665 pBdle->fBdleCviIoc = (*(uint32_t *)&bdle[12]) & 0x1;
1666#ifdef LOG_ENABLED
1667 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
1668#endif
1669}
1670
1671DECLINLINE(uint32_t) hdaCalculateTransferBufferLength(PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1672 uint32_t u32SoundBackendBufferBytesAvail, uint32_t u32CblLimit)
1673{
1674 uint32_t cb2Copy;
1675 /*
1676 * Number of bytes depends on the current position in buffer (u32BdleCviLen-u32BdleCviPos)
1677 */
1678 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos)); /* sanity */
1679 cb2Copy = pBdle->u32BdleCviLen - pBdle->u32BdleCviPos;
1680 /*
1681 * we may increase the counter in range of [0, FIFOS + 1]
1682 */
1683 cb2Copy = RT_MIN(cb2Copy, pStreamDesc->u32Fifos + 1);
1684 Assert((u32SoundBackendBufferBytesAvail > 0));
1685
1686 /* sanity check to avoid overriding the backend audio buffer */
1687 cb2Copy = RT_MIN(cb2Copy, u32SoundBackendBufferBytesAvail);
1688 cb2Copy = RT_MIN(cb2Copy, u32CblLimit);
1689
1690 if (cb2Copy <= pBdle->cbUnderFifoW)
1691 return 0;
1692 cb2Copy -= pBdle->cbUnderFifoW; /* forcibly reserve the amount of unreported bytes to copy */
1693 return cb2Copy;
1694}
1695
1696DECLINLINE(void) hdaBackendWriteTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
1697 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1698{
1699 Log(("hda:hdaBackendWriteTransferReported: cbArranged2Copy: %d, cbCopied: %d, pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1700 cbArranged2Copy, cbCopied, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1701 Assert((cbCopied));
1702 Assert((pu32BackendBufferCapacity && *pu32BackendBufferCapacity));
1703 /* Assertion!!! Fewer than cbUnderFifoW bytes were copied.
1704 * Probably we need to move the buffer, but it is rather hard to imagine a situation
1705 * where it might happen.
1706 */
1707 Assert((cbCopied == pBdle->cbUnderFifoW + cbArranged2Copy)); /* we assume that we write the entire buffer including unreported bytes */
1708 if ( pBdle->cbUnderFifoW
1709 && pBdle->cbUnderFifoW <= cbCopied)
1710 Log(("hda:hdaBackendWriteTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1711
1712 pBdle->cbUnderFifoW -= RT_MIN(pBdle->cbUnderFifoW, cbCopied);
1713 Assert((!pBdle->cbUnderFifoW)); /* Assert!!! Incorrect assumption */
1714
1715 /* We always increment the position of DMA buffer counter because we're always reading into an intermediate buffer */
1716 pBdle->u32BdleCviPos += cbArranged2Copy;
1717
1718 Assert((pBdle->u32BdleCviLen >= pBdle->u32BdleCviPos && *pu32BackendBufferCapacity >= cbCopied)); /* sanity */
1719 /* We report all bytes (including previously unreported bytes) */
1720 *pu32DMACursor += cbCopied;
1721 /* Decrease the backend counter by the number of bytes we copied to the backend */
1722 *pu32BackendBufferCapacity -= cbCopied;
1723 Log(("hda:hdaBackendWriteTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1724 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, *pu32DMACursor, *pu32BackendBufferCapacity));
1725}
1726
1727DECLINLINE(void) hdaBackendReadTransferReported(PHDABDLEDESC pBdle, uint32_t cbArranged2Copy, uint32_t cbCopied,
1728 uint32_t *pu32DMACursor, uint32_t *pu32BackendBufferCapacity)
1729{
1730 Assert((cbCopied, cbArranged2Copy));
1731 *pu32BackendBufferCapacity -= cbCopied;
1732 pBdle->u32BdleCviPos += cbCopied;
1733 Log(("hda:hdaBackendReadTransferReported: CVI resetting cbUnderFifoW:%d(pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1734 *pu32DMACursor += cbCopied + pBdle->cbUnderFifoW;
1735 pBdle->cbUnderFifoW = 0;
1736 Log(("hda:hdaBackendReadTransferReported: CVI(pos:%d, len:%d), pu32DMACursor: %d, pu32BackendBufferCapacity:%d\n",
1737 pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, pu32DMACursor ? *pu32DMACursor : 0, pu32BackendBufferCapacity ? *pu32BackendBufferCapacity : 0));
1738}
1739
1740DECLINLINE(void) hdaBackendTransferUnreported(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1741 uint32_t cbCopied, uint32_t *pu32BackendBufferCapacity)
1742{
1743 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1744 pBdle->u32BdleCviPos += cbCopied;
1745 pBdle->cbUnderFifoW += cbCopied;
1746 /* In case of a read transaction we're always copying from the backend buffer */
1747 if (pu32BackendBufferCapacity)
1748 *pu32BackendBufferCapacity -= cbCopied;
1749 Log(("hda:hdaBackendTransferUnreported: CVI (cbUnderFifoW:%d, pos:%d, len:%d)\n", pBdle->cbUnderFifoW, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1750 Assert((pBdle->cbUnderFifoW <= hdaFifoWToSz(pThis, pStreamDesc)));
1751}
1752
1753DECLINLINE(bool) hdaIsTransferCountersOverlapped(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1754{
1755 bool fOnBufferEdge = ( *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl
1756 || pBdle->u32BdleCviPos == pBdle->u32BdleCviLen);
1757
1758 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1759
1760 if (*pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1761 *pStreamDesc->pu32Lpib -= pStreamDesc->u32Cbl;
1762 hdaUpdatePosBuf(pThis, pStreamDesc);
1763
1764 /* don't touch BdleCvi counter on uninitialized descriptor */
1765 if ( pBdle->u32BdleCviPos
1766 && pBdle->u32BdleCviPos == pBdle->u32BdleCviLen)
1767 {
1768 pBdle->u32BdleCviPos = 0;
1769 pBdle->u32BdleCvi++;
1770 if (pBdle->u32BdleCvi == pBdle->u32BdleMaxCvi + 1)
1771 pBdle->u32BdleCvi = 0;
1772 }
1773 return fOnBufferEdge;
1774}
1775
1776DECLINLINE(void) hdaStreamCounterUpdate(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc,
1777 uint32_t cbInc)
1778{
1779 /*
1780 * if we're below the FIFO Watermark, it's expected that HDA doesn't fetch anything.
1781 * (ICH6 datasheet 18.2.38)
1782 */
1783 if (!pBdle->cbUnderFifoW)
1784 {
1785 *pStreamDesc->pu32Lpib += cbInc;
1786
1787 /*
1788 * Assert. The buffer counters should never overlap.
1789 */
1790 Assert((*pStreamDesc->pu32Lpib <= pStreamDesc->u32Cbl));
1791
1792 hdaUpdatePosBuf(pThis, pStreamDesc);
1793
1794 }
1795}
1796
1797static bool hdaDoNextTransferCycle(PHDASTATE pThis, PHDABDLEDESC pBdle, PHDASTREAMTRANSFERDESC pStreamDesc)
1798{
1799 bool fDoNextTransferLoop = true;
1800 if ( pBdle->u32BdleCviPos == pBdle->u32BdleCviLen
1801 || *pStreamDesc->pu32Lpib == pStreamDesc->u32Cbl)
1802 {
1803 if ( !pBdle->cbUnderFifoW
1804 && pBdle->fBdleCviIoc)
1805 {
1806 /**
1807 * @todo - more carefully investigate BCIS flag.
1808 * Speech synthesis works fine on Mac Guest if this bit isn't set
1809 * but in general sound quality gets worse.
1810 */
1811 *pStreamDesc->pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
1812
1813 /*
1814 * we should generate the interrupt if ICE bit of SDCTL register is set.
1815 */
1816 if (pStreamDesc->u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE))
1817 hdaProcessInterrupt(pThis);
1818 }
1819 fDoNextTransferLoop = false;
1820 }
1821 return fDoNextTransferLoop;
1822}
1823
1824/*
1825 * hdaReadAudio - copies samples from audio backend to DMA.
1826 * Note: this function writes to the DMA buffer immediately, but "reports bytes" when all conditions are met (FIFOW)
1827 */
1828static uint32_t hdaReadAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1829{
1830 PHDABDLEDESC pBdle = &pThis->StInBdle;
1831 uint32_t cbTransferred = 0;
1832 uint32_t cb2Copy = 0;
1833 uint32_t cbBackendCopy = 0;
1834
1835 Log(("hda:ra: CVI(pos:%d, len:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1836
1837 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1838 if (!cb2Copy)
1839 /* if we enter here we can't report "unreported bits" */
1840 *fStop = true;
1841 else
1842 {
1843 /*
1844 * read from backend input line to the last unreported position or at the begining.
1845 */
1846 cbBackendCopy = AUD_read(pThis->Codec.SwVoiceIn, pBdle->au8HdaBuffer, cb2Copy);
1847 /*
1848 * write the HDA DMA buffer
1849 */
1850 PDMDevHlpPhysWrite(pThis->pDevIns, pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer, cbBackendCopy);
1851
1852 /* Don't see any reason why cb2Copy would differ from cbBackendCopy */
1853 Assert((cbBackendCopy == cb2Copy && (*pu32Avail) >= cb2Copy)); /* sanity */
1854
1855 if (pBdle->cbUnderFifoW + cbBackendCopy > hdaFifoWToSz(pThis, 0))
1856 hdaBackendReadTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
1857 else
1858 {
1859 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cbBackendCopy, pu32Avail);
1860 *fStop = true;
1861 }
1862 }
1863
1864 Assert((cbTransferred <= (SDFIFOS(pThis, 0) + 1)));
1865 Log(("hda:ra: CVI(pos:%d, len:%d) cbTransferred: %d\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
1866 return cbTransferred;
1867}
1868
1869static uint32_t hdaWriteAudio(PHDASTATE pThis, PHDASTREAMTRANSFERDESC pStreamDesc, uint32_t *pu32Avail, bool *fStop, uint32_t u32CblLimit)
1870{
1871 PHDABDLEDESC pBdle = &pThis->StOutBdle;
1872 uint32_t cbTransferred = 0;
1873 uint32_t cb2Copy = 0; /* local byte counter (on local buffer) */
1874 uint32_t cbBackendCopy = 0; /* local byte counter, how many bytes copied to backend */
1875
1876 Log(("hda:wa: CVI(cvi:%d, pos:%d, len:%d)\n", pBdle->u32BdleCvi, pBdle->u32BdleCviPos, pBdle->u32BdleCviLen));
1877
1878 cb2Copy = hdaCalculateTransferBufferLength(pBdle, pStreamDesc, *pu32Avail, u32CblLimit);
1879
1880 /*
1881 * Copy from DMA to the corresponding hdaBuffer (if there are any bytes from the
1882 * previous unreported transfer we write at offset 'pBdle->cbUnderFifoW').
1883 */
1884 if (!cb2Copy)
1885 *fStop = true;
1886 else
1887 {
1888 PDMDevHlpPhysRead(pThis->pDevIns, pBdle->u64BdleCviAddr + pBdle->u32BdleCviPos, pBdle->au8HdaBuffer + pBdle->cbUnderFifoW, cb2Copy);
1889 /*
1890 * Write to audio backend. we should ensure that we have enough bytes to copy to the backend.
1891 */
1892 if (cb2Copy + pBdle->cbUnderFifoW >= hdaFifoWToSz(pThis, pStreamDesc))
1893 {
1894 /*
1895 * Feed the newly fetched samples, including unreported ones, to the backend.
1896 */
1897 cbBackendCopy = AUD_write (pThis->Codec.SwVoiceOut, pBdle->au8HdaBuffer, cb2Copy + pBdle->cbUnderFifoW);
1898 hdaBackendWriteTransferReported(pBdle, cb2Copy, cbBackendCopy, &cbTransferred, pu32Avail);
1899 }
1900 else
1901 {
1902 /* Not enough bytes to be processed and reported, we'll try our luck next time around */
1903 hdaBackendTransferUnreported(pThis, pBdle, pStreamDesc, cb2Copy, NULL);
1904 *fStop = true;
1905 }
1906 }
1907
1908 Assert(cbTransferred <= SDFIFOS(pThis, 4) + 1);
1909 Log(("hda:wa: CVI(pos:%d, len:%d, cbTransferred:%d)\n", pBdle->u32BdleCviPos, pBdle->u32BdleCviLen, cbTransferred));
1910 return cbTransferred;
1911}
1912
1913/**
1914 * @interface_method_impl{HDACODEC,pfnReset}
1915 */
1916DECLCALLBACK(int) hdaCodecReset(PHDACODEC pCodec)
1917{
1918 PHDASTATE pThis = (PHDASTATE)pCodec->pvHDAState;
1919 NOREF(pThis);
1920 return VINF_SUCCESS;
1921}
1922
1923DECLINLINE(void) hdaInitTransferDescriptor(PHDASTATE pThis, PHDABDLEDESC pBdle, uint8_t u8Strm,
1924 PHDASTREAMTRANSFERDESC pStreamDesc)
1925{
1926 Assert(pThis); Assert(pBdle); Assert(pStreamDesc); Assert(u8Strm <= 7);
1927
1928 memset(pStreamDesc, 0, sizeof(HDASTREAMTRANSFERDESC));
1929 pStreamDesc->u8Strm = u8Strm;
1930 pStreamDesc->u32Ctl = HDA_STREAM_REG2(pThis, CTL, u8Strm);
1931 pStreamDesc->u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG2(pThis, BDPL, u8Strm),
1932 HDA_STREAM_REG2(pThis, BDPU, u8Strm));
1933 pStreamDesc->pu32Lpib = &HDA_STREAM_REG2(pThis, LPIB, u8Strm);
1934 pStreamDesc->pu32Sts = &HDA_STREAM_REG2(pThis, STS, u8Strm);
1935 pStreamDesc->u32Cbl = HDA_STREAM_REG2(pThis, CBL, u8Strm);
1936 pStreamDesc->u32Fifos = HDA_STREAM_REG2(pThis, FIFOS, u8Strm);
1937
1938 pBdle->u32BdleMaxCvi = HDA_STREAM_REG2(pThis, LVI, u8Strm);
1939
1940#ifdef LOG_ENABLED
1941 if ( pBdle
1942 && pBdle->u32BdleMaxCvi)
1943 {
1944 Log(("Initialization of transfer descriptor:\n"));
1945 dump_bd(pThis, pBdle, pStreamDesc->u64BaseDMA);
1946 }
1947#endif
1948}
1949
1950
1951/**
1952 * @interface_method_impl{HDACODEC,pfnTransfer}
1953 */
1954static DECLCALLBACK(void) hdaTransfer(PHDACODEC pCodec, ENMSOUNDSOURCE src, int avail)
1955{
1956 PHDASTATE pThis = (PHDASTATE)pCodec->pvHDAState;
1957 uint8_t u8Strm = 0;
1958 PHDABDLEDESC pBdle = NULL;
1959
1960 switch (src)
1961 {
1962 case PO_INDEX:
1963 {
1964 u8Strm = 4;
1965 pBdle = &pThis->StOutBdle;
1966 break;
1967 }
1968 case PI_INDEX:
1969 {
1970 u8Strm = 0;
1971 pBdle = &pThis->StInBdle;
1972 break;
1973 }
1974 default:
1975 return;
1976 }
1977
1978 HDASTREAMTRANSFERDESC StreamDesc;
1979 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
1980
1981 bool fStop = false;
1982 while (avail && !fStop)
1983 {
1984 Assert( (StreamDesc.u32Ctl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
1985 && avail
1986 && StreamDesc.u64BaseDMA);
1987
1988 /* Fetch the Buffer Descriptor Entry (BDE). */
1989
1990 if (hdaIsTransferCountersOverlapped(pThis, pBdle, &StreamDesc))
1991 hdaFetchBdle(pThis, pBdle, &StreamDesc);
1992 *StreamDesc.pu32Sts |= HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1993 Assert((avail >= 0 && (StreamDesc.u32Cbl >= (*StreamDesc.pu32Lpib)))); /* sanity */
1994 uint32_t u32CblLimit = StreamDesc.u32Cbl - (*StreamDesc.pu32Lpib);
1995 Assert((u32CblLimit > hdaFifoWToSz(pThis, &StreamDesc)));
1996 Log(("hda: CBL=%d, LPIB=%d\n", StreamDesc.u32Cbl, *StreamDesc.pu32Lpib));
1997 uint32_t cb;
1998 switch (src)
1999 {
2000 case PO_INDEX:
2001 cb = hdaWriteAudio(pThis, &StreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
2002 break;
2003 case PI_INDEX:
2004 cb = hdaReadAudio(pThis, &StreamDesc, (uint32_t *)&avail, &fStop, u32CblLimit);
2005 break;
2006 default:
2007 cb = 0;
2008 fStop = true;
2009 AssertMsgFailed(("Unsupported"));
2010 }
2011 Assert(cb <= StreamDesc.u32Fifos + 1);
2012 *StreamDesc.pu32Sts &= ~HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
2013
2014 /* Process end of buffer condition. */
2015 hdaStreamCounterUpdate(pThis, pBdle, &StreamDesc, cb);
2016 fStop = !fStop ? !hdaDoNextTransferCycle(pThis, pBdle, &StreamDesc) : fStop;
2017 }
2018}
2019
2020
2021/* MMIO callbacks */
2022
2023/**
2024 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
2025 *
2026 * @note During implementation, we discovered so-called "forgotten" or "hole"
2027 * registers whose description is not listed in the RPM, datasheet, or
2028 * spec.
2029 */
2030PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2031{
2032 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2033 int rc;
2034
2035 /*
2036 * Look up and log.
2037 */
2038 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2039 int idxReg = hdaRegLookup(pThis, offReg);
2040#ifdef LOG_ENABLED
2041 unsigned const cbLog = cb;
2042 uint32_t offRegLog = offReg;
2043#endif
2044
2045 Log(("hdaMMIORead: offReg=%#x cb=%#x\n", offReg, cb));
2046#define NEW_READ_CODE
2047#ifdef NEW_READ_CODE
2048 Assert(cb == 4); Assert((offReg & 3) == 0);
2049
2050 if (pThis->fInReset && idxReg != ICH6_HDA_REG_GCTL)
2051 Log(("hda: access to registers except GCTL is blocked while reset\n"));
2052
2053 if (idxReg == -1)
2054 LogRel(("hda: Invalid read access @0x%x(of bytes:%d)\n", offReg, cb));
2055
2056 if (idxReg != -1)
2057 {
2058 /* ASSUMES gapless DWORD at end of map. */
2059 if (g_aHdaRegMap[idxReg].size == 4)
2060 {
2061 /*
2062 * Straight forward DWORD access.
2063 */
2064 rc = g_aHdaRegMap[idxReg].pfnRead(pThis, idxReg, (uint32_t *)pv);
2065 Log(("hda: read %s => %x (%Rrc)\n", g_aHdaRegMap[idxReg].abbrev, *(uint32_t *)pv, rc));
2066 }
2067 else
2068 {
2069 /*
2070 * Multi register read (unless there are trailing gaps).
2071 * ASSUMES that only DWORD reads have sideeffects.
2072 */
2073 uint32_t u32Value = 0;
2074 unsigned cbLeft = 4;
2075 do
2076 {
2077 uint32_t const cbReg = g_aHdaRegMap[idxReg].size;
2078 uint32_t u32Tmp = 0;
2079
2080 rc = g_aHdaRegMap[idxReg].pfnRead(pThis, idxReg, &u32Tmp);
2081 Log(("hda: read %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxReg].abbrev, cbReg, u32Tmp, rc));
2082 if (rc != VINF_SUCCESS)
2083 break;
2084 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
2085
2086 cbLeft -= cbReg;
2087 offReg += cbReg;
2088 idxReg++;
2089 } while (cbLeft > 0 && g_aHdaRegMap[idxReg].offset == offReg);
2090
2091 if (rc == VINF_SUCCESS)
2092 *(uint32_t *)pv = u32Value;
2093 else
2094 Assert(!IOM_SUCCESS(rc));
2095 }
2096 }
2097 else
2098 {
2099 rc = VINF_IOM_MMIO_UNUSED_FF;
2100 Log(("hda: hole at %x is accessed for read\n", offReg));
2101 }
2102#else
2103 if (idxReg != -1)
2104 {
2105 /** @todo r=bird: Accesses crossing register boundraries aren't handled
2106 * right from what I can tell? If they are, please explain
2107 * what the rules are. */
2108 uint32_t mask = 0;
2109 uint32_t shift = (g_aHdaRegMap[idxReg].offset - offReg) % sizeof(uint32_t) * 8;
2110 uint32_t u32Value = 0;
2111 switch(cb)
2112 {
2113 case 1: mask = 0x000000ff; break;
2114 case 2: mask = 0x0000ffff; break;
2115 case 4:
2116 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2117 case 8:
2118 mask = 0xffffffff;
2119 cb = 4;
2120 break;
2121 }
2122#if 0
2123 /* Cross-register access. Mac guest hits this assert doing assumption 4 byte access to 3 byte registers e.g. {I,O}SDnCTL
2124 */
2125 //Assert((cb <= g_aHdaRegMap[idxReg].size - (offReg - g_aHdaRegMap[idxReg].offset)));
2126 if (cb > g_aHdaRegMap[idxReg].size - (offReg - g_aHdaRegMap[idxReg].offset))
2127 {
2128 int off = cb - (g_aHdaRegMap[idxReg].size - (offReg - g_aHdaRegMap[idxReg].offset));
2129 rc = hdaMMIORead(pDevIns, pvUser, GCPhysAddr + cb - off, (char *)pv + cb - off, off);
2130 if (RT_FAILURE(rc))
2131 AssertRCReturn (rc, rc);
2132 }
2133 //Assert(((offReg - g_aHdaRegMap[idxReg].offset) == 0));
2134#endif
2135 mask <<= shift;
2136 rc = g_aHdaRegMap[idxReg].pfnRead(pThis, idxReg, &u32Value);
2137 *(uint32_t *)pv |= (u32Value & mask);
2138 Log(("hda: read %s[%x/%x]\n", g_aHdaRegMap[idxReg].abbrev, u32Value, *(uint32_t *)pv));
2139 }
2140 else
2141 {
2142 *(uint32_t *)pv = 0xFF;
2143 Log(("hda: hole at %x is accessed for read\n", offReg));
2144 rc = VINF_SUCCESS;
2145 }
2146#endif
2147
2148 /*
2149 * Log the outcome.
2150 */
2151#ifdef LOG_ENABLED
2152 if (cbLog == 4)
2153 Log(("hdaMMIORead: @%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
2154 else if (cbLog == 2)
2155 Log(("hdaMMIORead: @%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
2156 else if (cbLog == 1)
2157 Log(("hdaMMIORead: @%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
2158#endif
2159 return rc;
2160}
2161
2162
2163DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxReg, uint32_t u32Value, char const *pszLog)
2164{
2165 if (pThis->fInReset && idxReg != ICH6_HDA_REG_GCTL)
2166 Log(("hda: access to registers except GCTL is blocked while reset\n")); /** @todo where is this enforced? */
2167
2168#ifdef LOG_ENABLED
2169 uint32_t const u32CurValue = pThis->au32Regs[idxReg];
2170#endif
2171 int rc = g_aHdaRegMap[idxReg].pfnWrite(pThis, idxReg, u32Value);
2172 Log(("hda: write %#x -> %s[%db]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxReg].abbrev,
2173 g_aHdaRegMap[idxReg].size, u32CurValue, pThis->au32Regs[idxReg], pszLog));
2174 return rc;
2175}
2176
2177
2178/**
2179 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
2180 */
2181PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
2182{
2183 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2184 int rc;
2185
2186 /*
2187 * The behavior of accesses that aren't aligned on natural boundraries is
2188 * undefined. Just reject them out right.
2189 */
2190 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
2191 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
2192 if (GCPhysAddr & (cb - 1))
2193 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
2194
2195 /*
2196 * Lookup and log the access.
2197 */
2198 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
2199 int idxReg = hdaRegLookup(pThis, offReg);
2200 uint64_t u64Value;
2201 if (cb == 4) u64Value = *(uint32_t const *)pv;
2202 else if (cb == 2) u64Value = *(uint16_t const *)pv;
2203 else if (cb == 1) u64Value = *(uint8_t const *)pv;
2204 else if (cb == 8) u64Value = *(uint64_t const *)pv;
2205 else
2206 AssertReleaseMsgFailed(("%d\n", cb));
2207
2208#ifdef LOG_ENABLED
2209 uint32_t const u32LogOldValue = idxReg != -1 ? pThis->au32Regs[idxReg] : UINT32_MAX;
2210 uint32_t const offRegLog = offReg;
2211 int const idxRegLog = idxReg;
2212 if (idxReg == -1)
2213 Log(("hdaMMIOWrite: @%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
2214 else if (cb == 4)
2215 Log(("hdaMMIOWrite: @%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxReg].abbrev));
2216 else if (cb == 2)
2217 Log(("hdaMMIOWrite: @%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxReg].abbrev));
2218 else if (cb == 1)
2219 Log(("hdaMMIOWrite: @%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxReg].abbrev));
2220 if (idxReg != -1 && g_aHdaRegMap[idxReg].size != cb)
2221 Log(("hdaMMIOWrite: size=%d != cb=%d!!\n", g_aHdaRegMap[idxReg].size, cb));
2222#endif
2223
2224#define NEW_WRITE_CODE
2225#ifdef NEW_WRITE_CODE
2226 /*
2227 * Try for a direct hit first.
2228 */
2229 if (idxReg != -1 && g_aHdaRegMap[idxReg].size == cb)
2230 rc = hdaWriteReg(pThis, idxReg, u64Value, "");
2231 /*
2232 * Partial or multiple register access, loop thru the requested memory.
2233 */
2234 else
2235 {
2236 /* If it's an access beyond the start of the register, shift the input
2237 value and fill in missing bits. Natural alignment rules means we
2238 will only see 1 or 2 byte accesses of this kind, so no risk of
2239 shifting out input values. */
2240 if (idxReg == -1 && (idxReg = hdaRegLookupWithin(pThis, offReg)) != -1)
2241 {
2242 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxReg].offset; Assert(cbBefore > 0 && cbBefore < 4);
2243 offReg -= cbBefore;
2244 u64Value <<= cbBefore * 8;
2245 u64Value |= pThis->au32Regs[idxReg] & g_afMasks[cbBefore];
2246 Log(("hdaMMIOWrite: Within register, supplied %u leading bits: %#llx -> %#llx ...\n",
2247 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
2248 }
2249
2250 /* Loop thru the write area, it may covert multiple registers. */
2251 rc = VINF_SUCCESS;
2252 for (;;)
2253 {
2254 uint32_t cbReg;
2255 if (idxReg != -1)
2256 {
2257 cbReg = g_aHdaRegMap[idxReg].size;
2258 if (cb < cbReg)
2259 {
2260 u64Value |= pThis->au32Regs[idxReg] & g_afMasks[cbReg] & ~g_afMasks[cb];
2261 Log(("hdaMMIOWrite: Supplying missing bits (%#x): %#llx -> %#llx ...\n",
2262 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
2263 }
2264 rc = hdaWriteReg(pThis, idxReg, u64Value, "*");
2265 }
2266 else
2267 {
2268 LogRel(("hda: Invalid write access @0x%x!\n", offReg));
2269 cbReg = 1;
2270 }
2271 if (cbReg >= cb)
2272 break;
2273
2274 /* advance */
2275 offReg += cbReg;
2276 cb -= cbReg;
2277 u64Value >>= cbReg * 8;
2278 if (idxReg == -1)
2279 idxReg = hdaRegLookup(pThis, offReg);
2280 else
2281 {
2282 idxReg++;
2283 if ( (unsigned)idxReg >= RT_ELEMENTS(g_aHdaRegMap)
2284 || g_aHdaRegMap[idxReg].offset != offReg)
2285 idxReg = -1;
2286 }
2287 }
2288 }
2289#else
2290 if (idxReg != -1)
2291 {
2292 /** @todo r=bird: This looks like code for handling unaligned register
2293 * accesses. If it isn't, then add a comment explaining what you're
2294 * trying to do here. OTOH, if it is then it has the following
2295 * issues:
2296 * -# You're calculating the wrong new value for the register.
2297 * -# You're not handling cross register accesses. Imagine a
2298 * 4-byte write starting at CORBCTL, or a 8-byte write.
2299 *
2300 * PS! consider dropping the 'offset' argument to pfnWrite/pfnRead as
2301 * nobody seems to be using it and it just adds complexity when reading
2302 * the code.
2303 *
2304 */
2305 uint32_t u32CurValue = pThis->au32Regs[idxReg];
2306 uint32_t u32NewValue;
2307 uint32_t mask;
2308 switch (cb)
2309 {
2310 case 1:
2311 u32NewValue = *(uint8_t const *)pv;
2312 mask = 0xff;
2313 break;
2314 case 2:
2315 u32NewValue = *(uint16_t const *)pv;
2316 mask = 0xffff;
2317 break;
2318 case 4:
2319 case 8:
2320 /* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word */
2321 u32NewValue = *(uint32_t const *)pv;
2322 mask = 0xffffffff;
2323 cb = 4;
2324 break;
2325 default:
2326 AssertFailedReturn(VERR_INTERNAL_ERROR_4); /* shall not happen. */
2327 }
2328 /* cross-register access, see corresponding comment in hdaMMIORead */
2329 uint32_t shift = (g_aHdaRegMap[idxReg].offset - offReg) % sizeof(uint32_t) * 8;
2330 mask <<= shift;
2331 u32NewValue <<= shift;
2332 u32NewValue &= mask;
2333 u32NewValue |= (u32CurValue & ~mask);
2334
2335 rc = g_aHdaRegMap[idxReg].pfnWrite(pThis, idxReg, u32NewValue);
2336 Log(("hda: write %s:(%x) %x => %x\n", g_aHdaRegMap[idxReg].abbrev, u32NewValue,
2337 u32CurValue, pThis->au32Regs[idxReg]));
2338 }
2339 else
2340 rc = VINF_SUCCESS;
2341#endif
2342 Log(("hdaMMIOWrite: @%#05x %#x -> %#x\n", offRegLog, u32LogOldValue,
2343 idxRegLog != -1 ? pThis->au32Regs[idxRegLog] : UINT32_MAX));
2344 return rc;
2345}
2346
2347
2348/* PCI callback. */
2349
2350/**
2351 * @callback_method_impl{FNPCIIOREGIONMAP}
2352 */
2353static DECLCALLBACK(int) hdaPciIoRegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb,
2354 PCIADDRESSSPACE enmType)
2355{
2356 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2357 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
2358 RTIOPORT Port = (RTIOPORT)GCPhysAddress;
2359 int rc;
2360
2361 /*
2362 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
2363 *
2364 * Let IOM talk DWORDs when reading, saves a lot of complications. On
2365 * writing though, we have to do it all ourselves because of sideeffects.
2366 */
2367 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
2368 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
2369#ifdef NEW_READ_CODE
2370 IOMMMIO_FLAGS_READ_DWORD |
2371#else
2372 IOMMMIO_FLAGS_READ_PASSTHRU |
2373#endif
2374 IOMMMIO_FLAGS_WRITE_PASSTHRU,
2375 hdaMMIOWrite, hdaMMIORead, "ICH6_HDA");
2376
2377 if (RT_FAILURE(rc))
2378 return rc;
2379
2380 pThis->MMIOBaseAddr = GCPhysAddress;
2381 return VINF_SUCCESS;
2382}
2383
2384
2385/* Saved state callbacks. */
2386
2387/**
2388 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2389 */
2390static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2391{
2392 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2393 /* Save Codec nodes states */
2394 hdaCodecSaveState(&pThis->Codec, pSSM);
2395
2396 /* Save MMIO registers */
2397 AssertCompile(RT_ELEMENTS(pThis->au32Regs) == 112);
2398 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
2399 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
2400
2401 /* Save HDA dma counters */
2402 SSMR3PutStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2403 SSMR3PutStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2404 SSMR3PutStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), 0 /*fFlags*/, g_aHdaBDLEDescFields, NULL);
2405 return VINF_SUCCESS;
2406}
2407
2408
2409/**
2410 * @callback_method_impl{FNSSMDEVLOADEXEC}
2411 */
2412static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2413{
2414 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2415
2416 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2417
2418 /*
2419 * Load Codec nodes states.
2420 */
2421 int rc = hdaCodecLoadState(&pThis->Codec, pSSM, uVersion);
2422 if (RT_FAILURE(rc))
2423 return rc;
2424
2425 /*
2426 * Load MMIO registers.
2427 */
2428 uint32_t cRegs;
2429 switch (uVersion)
2430 {
2431 case HDA_SSM_VERSION_1:
2432 /* Starting with r71199, we would save 112 instead of 113
2433 registers due to some code cleanups. This only affected trunk
2434 builds in the 4.1 development period. */
2435 cRegs = 113;
2436 if (SSMR3HandleRevision(pSSM) >= 71199)
2437 {
2438 uint32_t uVer = SSMR3HandleVersion(pSSM);
2439 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
2440 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
2441 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
2442 cRegs = 112;
2443 }
2444 break;
2445
2446 case HDA_SSM_VERSION_2:
2447 case HDA_SSM_VERSION_3:
2448 cRegs = 112;
2449 AssertCompile(RT_ELEMENTS(pThis->au32Regs) == 112);
2450 break;
2451
2452 case HDA_SSM_VERSION:
2453 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
2454 AssertLogRelMsgReturn(cRegs == RT_ELEMENTS(pThis->au32Regs),
2455 ("cRegs is %d, expected %d\n", cRegs, RT_ELEMENTS(pThis->au32Regs)),
2456 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2457 break;
2458
2459 default:
2460 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2461 }
2462
2463 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
2464 {
2465 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
2466 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
2467 }
2468 else
2469 {
2470 RT_ZERO(pThis->au32Regs);
2471 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
2472 }
2473
2474 /*
2475 * Load HDA dma counters.
2476 */
2477 uint32_t fFlags = uVersion <= HDA_SSM_VERSION_2 ? SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED : 0;
2478 PCSSMFIELD paFields = uVersion <= HDA_SSM_VERSION_2 ? g_aHdaBDLEDescFieldsOld : g_aHdaBDLEDescFields;
2479 SSMR3GetStructEx(pSSM, &pThis->StOutBdle, sizeof(pThis->StOutBdle), fFlags, paFields, NULL);
2480 SSMR3GetStructEx(pSSM, &pThis->StMicBdle, sizeof(pThis->StMicBdle), fFlags, paFields, NULL);
2481 rc = SSMR3GetStructEx(pSSM, &pThis->StInBdle, sizeof(pThis->StInBdle), fFlags, paFields, NULL);
2482 AssertRCReturn(rc, rc);
2483
2484 /*
2485 * Update stuff after the state changes.
2486 */
2487 AUD_set_active_in(pThis->Codec.SwVoiceIn, SDCTL(pThis, 0) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2488 AUD_set_active_out(pThis->Codec.SwVoiceOut, SDCTL(pThis, 4) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2489
2490 pThis->u64CORBBase = RT_MAKE_U64(CORBLBASE(pThis), CORBUBASE(pThis));
2491 pThis->u64RIRBBase = RT_MAKE_U64(RIRLBASE(pThis), RIRUBASE(pThis));
2492 pThis->u64DPBase = RT_MAKE_U64(DPLBASE(pThis), DPUBASE(pThis));
2493 return VINF_SUCCESS;
2494}
2495
2496
2497/* Debug and log type formatters. */
2498
2499/**
2500 * @callback_method_impl{FNRTSTRFORMATTYPE}
2501 */
2502static DECLCALLBACK(size_t)
2503hdaFormatStrmCtl(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2504 const char *pszType, void const *pvValue,
2505 int cchWidth, int cchPrecision, unsigned fFlags,
2506 void *pvUser)
2507{
2508 uint32_t sdCtl = (uint32_t)(uintptr_t)pvValue;
2509 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2510 "SDCTL(raw: %#x, strm:%#x, dir:%RTbool, tp:%RTbool strip:%x, deie:%RTbool, ioce:%RTbool, run:%RTbool, srst:%RTbool)",
2511 sdCtl,
2512 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, NUM)) >> ICH6_HDA_SDCTL_NUM_SHIFT,
2513 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)),
2514 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
2515 (sdCtl & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> ICH6_HDA_SDCTL_STRIPE_SHIFT,
2516 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
2517 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
2518 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
2519 RT_BOOL(sdCtl & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
2520}
2521
2522/**
2523 * @callback_method_impl{FNRTSTRFORMATTYPE}
2524 */
2525static DECLCALLBACK(size_t)
2526hdaFormatStrmFifos(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2527 const char *pszType, void const *pvValue,
2528 int cchWidth, int cchPrecision, unsigned fFlags,
2529 void *pvUser)
2530{
2531 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
2532 uint32_t cb;
2533 switch (uSdFifos)
2534 {
2535 case HDA_SDONFIFO_16B: cb = 16; break;
2536 case HDA_SDONFIFO_32B: cb = 32; break;
2537 case HDA_SDONFIFO_64B: cb = 64; break;
2538 case HDA_SDONFIFO_128B: cb = 128; break;
2539 case HDA_SDONFIFO_192B: cb = 192; break;
2540 case HDA_SDONFIFO_256B: cb = 256; break;
2541 case HDA_SDINFIFO_120B: cb = 120; break;
2542 case HDA_SDINFIFO_160B: cb = 160; break;
2543 default: cb = 0; break;
2544 }
2545 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw: %#x, sdfifos:%u B)", uSdFifos, cb);
2546}
2547
2548/**
2549 * @callback_method_impl{FNRTSTRFORMATTYPE}
2550 */
2551static DECLCALLBACK(size_t)
2552hdaFormatStrmFifow(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2553 const char *pszType, void const *pvValue,
2554 int cchWidth, int cchPrecision, unsigned fFlags,
2555 void *pvUser)
2556{
2557 uint32_t uSdFifos = (uint32_t)(uintptr_t)pvValue;
2558 uint32_t cb;
2559 switch (uSdFifos)
2560 {
2561 case HDA_SDFIFOW_8B: cb = 8; break;
2562 case HDA_SDFIFOW_16B: cb = 16; break;
2563 case HDA_SDFIFOW_32B: cb = 32; break;
2564 default: cb = 0; break;
2565 }
2566 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSdFifos, cb);
2567}
2568
2569/**
2570 * @callback_method_impl{FNRTSTRFORMATTYPE}
2571 */
2572static DECLCALLBACK(size_t)
2573hdaFormatStrmSts(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2574 const char *pszType, void const *pvValue,
2575 int cchWidth, int cchPrecision, unsigned fFlags,
2576 void *pvUser)
2577{
2578 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
2579 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
2580 "SDSTS(raw: %#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
2581 uSdSts,
2582 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
2583 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
2584 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
2585 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
2586}
2587
2588
2589static int hdaLookUpRegisterByName(PHDASTATE pThis, const char *pszArgs)
2590{
2591 int iReg = 0;
2592 for (; iReg < HDA_NREGS; ++iReg)
2593 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
2594 return iReg;
2595 return -1;
2596}
2597
2598
2599static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
2600{
2601 Assert( pThis
2602 && iHdaIndex >= 0
2603 && iHdaIndex < HDA_NREGS);
2604 pHlp->pfnPrintf(pHlp, "hda: %s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[iHdaIndex]);
2605}
2606
2607
2608/**
2609 * @callback_method_impl{FNDBGFHANDLERDEV}
2610 */
2611static DECLCALLBACK(void) hdaInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2612{
2613 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2614 int iHdaRegisterIndex = hdaLookUpRegisterByName(pThis, pszArgs);
2615 if (iHdaRegisterIndex != -1)
2616 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
2617 else
2618 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NREGS; ++iHdaRegisterIndex)
2619 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
2620}
2621
2622
2623static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaStrmIndex)
2624{
2625 Assert( pThis
2626 && iHdaStrmIndex >= 0
2627 && iHdaStrmIndex < 7);
2628 pHlp->pfnPrintf(pHlp, "Dump of %d HDA Stream:\n", iHdaStrmIndex);
2629 pHlp->pfnPrintf(pHlp, "SD%dCTL: %R[sdctl]\n", iHdaStrmIndex, HDA_STREAM_REG2(pThis, CTL, iHdaStrmIndex));
2630 pHlp->pfnPrintf(pHlp, "SD%dCTS: %R[sdsts]\n", iHdaStrmIndex, HDA_STREAM_REG2(pThis, STS, iHdaStrmIndex));
2631 pHlp->pfnPrintf(pHlp, "SD%dFIFOS: %R[sdfifos]\n", iHdaStrmIndex, HDA_STREAM_REG2(pThis, FIFOS, iHdaStrmIndex));
2632 pHlp->pfnPrintf(pHlp, "SD%dFIFOW: %R[sdfifow]\n", iHdaStrmIndex, HDA_STREAM_REG2(pThis, FIFOW, iHdaStrmIndex));
2633}
2634
2635
2636static int hdaLookUpStreamIndex(PHDASTATE pThis, const char *pszArgs)
2637{
2638 /* todo: add args parsing */
2639 return -1;
2640}
2641
2642
2643/**
2644 * @callback_method_impl{FNDBGFHANDLERDEV}
2645 */
2646static DECLCALLBACK(void) hdaInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2647{
2648 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2649 int iHdaStrmIndex = hdaLookUpStreamIndex(pThis, pszArgs);
2650 if (iHdaStrmIndex != -1)
2651 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
2652 else
2653 for(iHdaStrmIndex = 0; iHdaStrmIndex < 7; ++iHdaStrmIndex)
2654 hdaDbgPrintStream(pThis, pHlp, iHdaStrmIndex);
2655}
2656
2657/**
2658 * @callback_method_impl{FNDBGFHANDLERDEV}
2659 */
2660static DECLCALLBACK(void) hdaInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2661{
2662 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2663 if (pThis->Codec.pfnCodecDbgListNodes)
2664 pThis->Codec.pfnCodecDbgListNodes(&pThis->Codec, pHlp, pszArgs);
2665 else
2666 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2667}
2668
2669
2670/**
2671 * @callback_method_impl{FNDBGFHANDLERDEV}
2672 */
2673static DECLCALLBACK(void) hdaInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2674{
2675 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2676 if (pThis->Codec.pfnCodecDbgSelector)
2677 pThis->Codec.pfnCodecDbgSelector(&pThis->Codec, pHlp, pszArgs);
2678 else
2679 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback.\n");
2680}
2681
2682
2683/* PDMIBASE */
2684
2685/**
2686 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2687 */
2688static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
2689{
2690 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
2691 Assert(&pThis->IBase == pInterface);
2692
2693 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
2694 return NULL;
2695}
2696
2697
2698/* PDMDEVREG */
2699
2700/**
2701 * Reset notification.
2702 *
2703 * @returns VBox status.
2704 * @param pDevIns The device instance data.
2705 *
2706 * @remark The original sources didn't install a reset handler, but it seems to
2707 * make sense to me so we'll do it.
2708 */
2709static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
2710{
2711 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2712 GCAP(pThis) = HDA_MAKE_GCAP(4,4,0,0,1); /* see 6.2.1 */
2713 VMIN(pThis) = 0x00; /* see 6.2.2 */
2714 VMAJ(pThis) = 0x01; /* see 6.2.3 */
2715 VMAJ(pThis) = 0x01; /* see 6.2.3 */
2716 OUTPAY(pThis) = 0x003C; /* see 6.2.4 */
2717 INPAY(pThis) = 0x001D; /* see 6.2.5 */
2718 pThis->au32Regs[ICH6_HDA_REG_CORBSIZE] = 0x42; /* see 6.2.1 */
2719 pThis->au32Regs[ICH6_HDA_REG_RIRBSIZE] = 0x42; /* see 6.2.1 */
2720 CORBRP(pThis) = 0x0;
2721 RIRBWP(pThis) = 0x0;
2722
2723 Log(("hda: inter HDA reset.\n"));
2724 pThis->cbCorbBuf = 256 * sizeof(uint32_t);
2725
2726 if (pThis->pu32CorbBuf)
2727 memset(pThis->pu32CorbBuf, 0, pThis->cbCorbBuf);
2728 else
2729 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
2730
2731 pThis->cbRirbBuf = 256 * sizeof(uint64_t);
2732 if (pThis->pu64RirbBuf)
2733 memset(pThis->pu64RirbBuf, 0, pThis->cbRirbBuf);
2734 else
2735 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
2736
2737 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
2738
2739 HDABDLEDESC StEmptyBdle;
2740 for (uint8_t u8Strm = 0; u8Strm < 8; ++u8Strm)
2741 {
2742 HDASTREAMTRANSFERDESC StreamDesc;
2743 PHDABDLEDESC pBdle = NULL;
2744 if (u8Strm == 0)
2745 pBdle = &pThis->StInBdle;
2746 else if(u8Strm == 4)
2747 pBdle = &pThis->StOutBdle;
2748 else
2749 {
2750 memset(&StEmptyBdle, 0, sizeof(HDABDLEDESC));
2751 pBdle = &StEmptyBdle;
2752 }
2753 hdaInitTransferDescriptor(pThis, pBdle, u8Strm, &StreamDesc);
2754 /* hdaStreamReset prevents changing the SRST bit, so we force it to zero here. */
2755 HDA_STREAM_REG2(pThis, CTL, u8Strm) = 0;
2756 hdaStreamReset(pThis, pBdle, &StreamDesc, u8Strm);
2757 }
2758
2759 /* emulation of codec "wake up" (HDA spec 5.5.1 and 6.5)*/
2760 STATESTS(pThis) = 0x1;
2761
2762 Log(("hda: reset finished\n"));
2763}
2764
2765
2766/**
2767 * @interface_method_impl{PDMDEVREG,pfnDestruct}
2768 */
2769static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
2770{
2771 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2772
2773 int rc = hdaCodecDestruct(&pThis->Codec);
2774 AssertRC(rc);
2775
2776 RTMemFree(pThis->pu32CorbBuf);
2777 pThis->pu32CorbBuf = NULL;
2778
2779 RTMemFree(pThis->pu64RirbBuf);
2780 pThis->pu64RirbBuf = NULL;
2781
2782 return VINF_SUCCESS;
2783}
2784
2785/**
2786 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2787 */
2788static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2789{
2790 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
2791 int rc;
2792
2793 Assert(iInstance == 0);
2794 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2795
2796 /*
2797 * Validations.
2798 */
2799 if (!CFGMR3AreValuesValid(pCfgHandle, "\0"))
2800 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2801 N_ ("Invalid configuration for the Intel HDA device"));
2802
2803 /// @todo r=michaln: This device may need R0/RC enabling, especially if guests
2804 /// poll some register(pThis).
2805
2806 /*
2807 * Initialize data (most of it anyway).
2808 */
2809 pThis->pDevIns = pDevIns;
2810 /* IBase */
2811 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
2812
2813 /* PCI Device */
2814 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
2815 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEICE_ID); /* HDA */
2816
2817 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
2818 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
2819 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
2820 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
2821 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
2822 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
2823 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
2824 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
2825 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
2826 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
2827 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
2828
2829#if defined(HDA_AS_PCI_EXPRESS)
2830 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
2831#elif defined(VBOX_WITH_MSI_DEVICES)
2832 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
2833#else
2834 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
2835#endif
2836
2837 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
2838 /// of these values needs to be properly documented!
2839 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
2840 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
2841
2842 /* Power Management */
2843 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
2844 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
2845 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
2846
2847#ifdef HDA_AS_PCI_EXPRESS
2848 /* PCI Express */
2849 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
2850 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
2851 /* Device flags */
2852 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
2853 /* version */ 0x1 |
2854 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
2855 /* MSI */ (100) << 9 );
2856 /* Device capabilities */
2857 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
2858 /* Device control */
2859 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
2860 /* Device status */
2861 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
2862 /* Link caps */
2863 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
2864 /* Link control */
2865 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
2866 /* Link status */
2867 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
2868 /* Slot capabilities */
2869 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
2870 /* Slot control */
2871 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
2872 /* Slot status */
2873 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
2874 /* Root control */
2875 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
2876 /* Root capabilities */
2877 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
2878 /* Root status */
2879 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
2880 /* Device capabilities 2 */
2881 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
2882 /* Device control 2 */
2883 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
2884 /* Link control 2 */
2885 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
2886 /* Slot control 2 */
2887 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
2888#endif
2889
2890 /*
2891 * Register the PCI device.
2892 */
2893 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
2894 if (RT_FAILURE(rc))
2895 return rc;
2896
2897 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
2898 if (RT_FAILURE(rc))
2899 return rc;
2900
2901#ifdef VBOX_WITH_MSI_DEVICES
2902 PDMMSIREG MsiReg;
2903 RT_ZERO(MsiReg);
2904 MsiReg.cMsiVectors = 1;
2905 MsiReg.iMsiCapOffset = 0x60;
2906 MsiReg.iMsiNextOffset = 0x50;
2907 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
2908 if (RT_FAILURE(rc))
2909 {
2910 LogRel(("Chipset cannot do MSI: %Rrc\n", rc));
2911 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
2912 }
2913#endif
2914
2915 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
2916 if (RT_FAILURE(rc))
2917 return rc;
2918
2919 /*
2920 * Attach driver.
2921 */
2922 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Audio Driver Port");
2923 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2924 Log(("hda: No attached driver!\n"));
2925 else if (RT_FAILURE(rc))
2926 {
2927 AssertMsgFailed(("Failed to attach Intel HDA LUN #0! rc=%Rrc\n", rc));
2928 return rc;
2929 }
2930
2931 pThis->Codec.pvHDAState = pThis;
2932 rc = hdaCodecConstruct(pDevIns, &pThis->Codec, pCfgHandle);
2933 if (RT_FAILURE(rc))
2934 AssertRCReturn(rc, rc);
2935
2936 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
2937 verb F20 should provide device/codec recognition. */
2938 Assert(pThis->Codec.u16VendorId);
2939 Assert(pThis->Codec.u16DeviceId);
2940 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->Codec.u16VendorId); /* 2c ro - intel.) */
2941 PCIDevSetSubSystemId( &pThis->PciDev, pThis->Codec.u16DeviceId); /* 2e ro. */
2942
2943 hdaReset(pDevIns);
2944 pThis->Codec.id = 0;
2945 pThis->Codec.pfnTransfer = hdaTransfer;
2946 pThis->Codec.pfnReset = hdaCodecReset;
2947
2948 /*
2949 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
2950 * hdaReset shouldn't affects these registers.
2951 */
2952 WAKEEN(pThis) = 0x0;
2953 STATESTS(pThis) = 0x0;
2954
2955 /*
2956 * Debug and string formatter types.
2957 */
2958 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaInfo);
2959 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaInfoStream);
2960 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaInfoCodecNodes);
2961 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaInfoCodecSelector);
2962
2963 rc = RTStrFormatTypeRegister("sdctl", hdaFormatStrmCtl, NULL);
2964 AssertRC(rc);
2965 rc = RTStrFormatTypeRegister("sdsts", hdaFormatStrmSts, NULL);
2966 AssertRC(rc);
2967 rc = RTStrFormatTypeRegister("sdfifos", hdaFormatStrmFifos, NULL);
2968 AssertRC(rc);
2969 rc = RTStrFormatTypeRegister("sdfifow", hdaFormatStrmFifow, NULL);
2970 AssertRC(rc);
2971#if 0
2972 rc = RTStrFormatTypeRegister("sdfmt", printHdaStrmFmt, NULL);
2973 AssertRC(rc);
2974#endif
2975
2976 /*
2977 * Some debug assertions.
2978 */
2979 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
2980 {
2981 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
2982 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
2983
2984 /* binary search order. */
2985 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
2986 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
2987 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
2988
2989 /* alignment. */
2990 AssertReleaseMsg( pReg->size == 1
2991 || (pReg->size == 2 && (pReg->offset & 1) == 0)
2992 || (pReg->size == 3 && (pReg->offset & 3) == 0)
2993 || (pReg->size == 4 && (pReg->offset & 3) == 0),
2994 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
2995
2996 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
2997 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
2998 if (pReg->offset & 3)
2999 {
3000 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
3001 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3002 if (pPrevReg)
3003 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
3004 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3005 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
3006 }
3007#if 0
3008 if ((pReg->offset + pReg->size) & 3)
3009 {
3010 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3011 if (pNextReg)
3012 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
3013 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
3014 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
3015 }
3016#endif
3017
3018 /* The final entry is a full dword, no gaps! Allows shortcuts. */
3019 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
3020 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
3021 }
3022
3023 return VINF_SUCCESS;
3024}
3025
3026/**
3027 * The device registration structure.
3028 */
3029const PDMDEVREG g_DeviceICH6_HDA =
3030{
3031 /* u32Version */
3032 PDM_DEVREG_VERSION,
3033 /* szName */
3034 "hda",
3035 /* szRCMod */
3036 "",
3037 /* szR0Mod */
3038 "",
3039 /* pszDescription */
3040 "Intel HD Audio Controller",
3041 /* fFlags */
3042 PDM_DEVREG_FLAGS_DEFAULT_BITS,
3043 /* fClass */
3044 PDM_DEVREG_CLASS_AUDIO,
3045 /* cMaxInstances */
3046 1,
3047 /* cbInstance */
3048 sizeof(HDASTATE),
3049 /* pfnConstruct */
3050 hdaConstruct,
3051 /* pfnDestruct */
3052 hdaDestruct,
3053 /* pfnRelocate */
3054 NULL,
3055 /* pfnIOCtl */
3056 NULL,
3057 /* pfnPowerOn */
3058 NULL,
3059 /* pfnReset */
3060 hdaReset,
3061 /* pfnSuspend */
3062 NULL,
3063 /* pfnResume */
3064 NULL,
3065 /* pfnAttach */
3066 NULL,
3067 /* pfnDetach */
3068 NULL,
3069 /* pfnQueryInterface. */
3070 NULL,
3071 /* pfnInitComplete */
3072 NULL,
3073 /* pfnPowerOff */
3074 NULL,
3075 /* pfnSoftReset */
3076 NULL,
3077 /* u32VersionEnd */
3078 PDM_DEVREG_VERSION
3079};
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