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source: vbox/trunk/src/VBox/Devices/Audio/DevHdaStream.cpp@ 94368

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1/* $Id: DevHdaStream.cpp 93115 2022-01-01 11:31:46Z vboxsync $ */
2/** @file
3 * Intel HD Audio Controller Emulation - Streams.
4 */
5
6/*
7 * Copyright (C) 2017-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_HDA
23#include <VBox/log.h>
24
25#include <iprt/mem.h>
26#include <iprt/semaphore.h>
27#include <iprt/zero.h>
28
29#include <VBox/AssertGuest.h>
30#include <VBox/vmm/pdmdev.h>
31#include <VBox/vmm/pdmaudioifs.h>
32#include <VBox/vmm/pdmaudioinline.h>
33
34#include "AudioHlp.h"
35
36#include "DevHda.h"
37
38#ifdef VBOX_WITH_DTRACE
39# include "dtrace/VBoxDD.h"
40#endif
41
42
43/*********************************************************************************************************************************
44* Internal Functions *
45*********************************************************************************************************************************/
46#if defined(IN_RING3) || defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
47static void hdaStreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB);
48#endif
49#ifdef IN_RING3
50# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
51static void hdaR3StreamFlushDmaBounceBufferOutput(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
52# endif
53static uint32_t hdaR3StreamHandleDmaBufferOverrun(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink,
54 uint32_t cbNeeded, uint64_t nsNow,
55 const char *pszCaller, uint32_t const cbStreamFree);
56static void hdaR3StreamUpdateDma(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
57 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
58#endif
59
60
61#ifdef IN_RING3
62
63/**
64 * Creates an HDA stream.
65 *
66 * @returns VBox status code.
67 * @param pStreamShared The HDA stream to construct - shared bits.
68 * @param pStreamR3 The HDA stream to construct - ring-3 bits.
69 * @param pThis The shared HDA device instance.
70 * @param pThisCC The ring-3 HDA device instance.
71 * @param uSD Stream descriptor number to assign.
72 */
73int hdaR3StreamConstruct(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PHDASTATE pThis, PHDASTATER3 pThisCC, uint8_t uSD)
74{
75 pStreamR3->u8SD = uSD;
76 pStreamShared->u8SD = uSD;
77 pStreamR3->pMixSink = NULL;
78 pStreamR3->pHDAStateShared = pThis;
79 pStreamR3->pHDAStateR3 = pThisCC;
80 Assert(pStreamShared->hTimer != NIL_TMTIMERHANDLE); /* hdaR3Construct initalized this one already. */
81
82 pStreamShared->State.fInReset = false;
83 pStreamShared->State.fRunning = false;
84
85 AssertPtr(pStreamR3->pHDAStateR3);
86 AssertPtr(pStreamR3->pHDAStateR3->pDevIns);
87
88 const bool fIsInput = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN;
89
90 if (fIsInput)
91 {
92 pStreamShared->State.Cfg.enmPath = PDMAUDIOPATH_UNKNOWN;
93 pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_IN;
94 }
95 else
96 {
97 pStreamShared->State.Cfg.enmPath = PDMAUDIOPATH_UNKNOWN;
98 pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_OUT;
99 }
100
101 pStreamR3->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
102
103 if (pStreamR3->Dbg.Runtime.fEnabled)
104 {
105 int rc2 = AudioHlpFileCreateF(&pStreamR3->Dbg.Runtime.pFileStream, AUDIOHLPFILE_FLAGS_NONE, AUDIOHLPFILETYPE_WAV,
106 pThisCC->Dbg.pszOutPath, AUDIOHLPFILENAME_FLAGS_NONE, 0 /*uInstance*/,
107 fIsInput ? "hdaStreamWriteSD%RU8" : "hdaStreamReadSD%RU8", uSD);
108 AssertRC(rc2);
109
110 /* pFileDMARaw */
111 rc2 = AudioHlpFileCreateF(&pStreamR3->Dbg.Runtime.pFileDMARaw, AUDIOHLPFILE_FLAGS_NONE, AUDIOHLPFILETYPE_WAV,
112 pThisCC->Dbg.pszOutPath, AUDIOHLPFILENAME_FLAGS_NONE, 0 /*uInstance*/,
113 fIsInput ? "hdaDMARawWriteSD%RU8" : "hdaDMARawReadSD%RU8", uSD);
114 AssertRC(rc2);
115
116 /* pFileDMAMapped */
117 rc2 = AudioHlpFileCreateF(&pStreamR3->Dbg.Runtime.pFileDMAMapped, AUDIOHLPFILE_FLAGS_NONE, AUDIOHLPFILETYPE_WAV,
118 pThisCC->Dbg.pszOutPath, AUDIOHLPFILENAME_FLAGS_NONE, 0 /*uInstance*/,
119 fIsInput ? "hdaDMAWriteMappedSD%RU8" : "hdaDMAReadMappedSD%RU8", uSD);
120 AssertRC(rc2);
121
122 /* Delete stale debugging files from a former run. */
123 AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileStream);
124 AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMARaw);
125 AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMAMapped);
126 }
127
128 return VINF_SUCCESS;
129}
130
131/**
132 * Destroys an HDA stream.
133 *
134 * @param pStreamR3 The HDA stream to destroy - ring-3 bits.
135 */
136void hdaR3StreamDestroy(PHDASTREAMR3 pStreamR3)
137{
138 LogFlowFunc(("[SD%RU8] Destroying ...\n", pStreamR3->u8SD));
139 int rc2;
140
141 if (pStreamR3->State.pAioRegSink)
142 {
143 rc2 = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
144 AssertRC(rc2);
145 pStreamR3->State.pAioRegSink = NULL;
146 }
147
148 if (pStreamR3->State.pCircBuf)
149 {
150 RTCircBufDestroy(pStreamR3->State.pCircBuf);
151 pStreamR3->State.pCircBuf = NULL;
152 pStreamR3->State.StatDmaBufSize = 0;
153 pStreamR3->State.StatDmaBufUsed = 0;
154 }
155
156 if (pStreamR3->Dbg.Runtime.fEnabled)
157 {
158 AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileStream);
159 pStreamR3->Dbg.Runtime.pFileStream = NULL;
160
161 AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMARaw);
162 pStreamR3->Dbg.Runtime.pFileDMARaw = NULL;
163
164 AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMAMapped);
165 pStreamR3->Dbg.Runtime.pFileDMAMapped = NULL;
166 }
167
168 LogFlowFuncLeave();
169}
170
171
172/**
173 * Converts an HDA stream's SDFMT register into a given PCM properties structure.
174 *
175 * @returns VBox status code.
176 * @param u16SDFMT The HDA stream's SDFMT value to convert.
177 * @param pProps PCM properties structure to hold converted result on success.
178 */
179int hdaR3SDFMTToPCMProps(uint16_t u16SDFMT, PPDMAUDIOPCMPROPS pProps)
180{
181 AssertPtrReturn(pProps, VERR_INVALID_POINTER);
182
183# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
184
185 int rc = VINF_SUCCESS;
186
187 uint32_t u32Hz = EXTRACT_VALUE(u16SDFMT, HDA_SDFMT_BASE_RATE_MASK, HDA_SDFMT_BASE_RATE_SHIFT)
188 ? 44100 : 48000;
189 uint32_t u32HzMult = 1;
190 uint32_t u32HzDiv = 1;
191
192 switch (EXTRACT_VALUE(u16SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
193 {
194 case 0: u32HzMult = 1; break;
195 case 1: u32HzMult = 2; break;
196 case 2: u32HzMult = 3; break;
197 case 3: u32HzMult = 4; break;
198 default:
199 LogFunc(("Unsupported multiplier %x\n",
200 EXTRACT_VALUE(u16SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
201 rc = VERR_NOT_SUPPORTED;
202 break;
203 }
204 switch (EXTRACT_VALUE(u16SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
205 {
206 case 0: u32HzDiv = 1; break;
207 case 1: u32HzDiv = 2; break;
208 case 2: u32HzDiv = 3; break;
209 case 3: u32HzDiv = 4; break;
210 case 4: u32HzDiv = 5; break;
211 case 5: u32HzDiv = 6; break;
212 case 6: u32HzDiv = 7; break;
213 case 7: u32HzDiv = 8; break;
214 default:
215 LogFunc(("Unsupported divisor %x\n",
216 EXTRACT_VALUE(u16SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
217 rc = VERR_NOT_SUPPORTED;
218 break;
219 }
220
221 uint8_t cbSample = 0;
222 switch (EXTRACT_VALUE(u16SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
223 {
224 case 0:
225 cbSample = 1;
226 break;
227 case 1:
228 cbSample = 2;
229 break;
230 case 4:
231 cbSample = 4;
232 break;
233 default:
234 AssertMsgFailed(("Unsupported bits per sample %x\n",
235 EXTRACT_VALUE(u16SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
236 rc = VERR_NOT_SUPPORTED;
237 break;
238 }
239
240 if (RT_SUCCESS(rc))
241 {
242 PDMAudioPropsInit(pProps, cbSample, true /*fSigned*/, (u16SDFMT & 0xf) + 1 /*cChannels*/, u32Hz * u32HzMult / u32HzDiv);
243 /** @todo is there anything we need to / can do about channel assignments? */
244 }
245
246# undef EXTRACT_VALUE
247 return rc;
248}
249
250# ifdef LOG_ENABLED
251void hdaR3BDLEDumpAll(PPDMDEVINS pDevIns, PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE)
252{
253 LogFlowFunc(("BDLEs @ 0x%x (%RU16):\n", u64BDLBase, cBDLE));
254 if (!u64BDLBase)
255 return;
256
257 uint32_t cbBDLE = 0;
258 for (uint16_t i = 0; i < cBDLE; i++)
259 {
260 HDABDLEDESC bd;
261 PDMDevHlpPhysRead(pDevIns, u64BDLBase + i * sizeof(HDABDLEDESC), &bd, sizeof(bd));
262
263 LogFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
264 i, bd.u64BufAddr, bd.u32BufSize, bd.fFlags & HDA_BDLE_F_IOC));
265
266 cbBDLE += bd.u32BufSize;
267 }
268
269 LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
270
271 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
272 return;
273
274 LogFlowFunc(("DMA counters:\n"));
275
276 for (int i = 0; i < cBDLE; i++)
277 {
278 uint32_t uDMACnt;
279 PDMDevHlpPhysRead(pDevIns, (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
280 &uDMACnt, sizeof(uDMACnt));
281
282 LogFlowFunc(("\t#%03d DMA @ 0x%x\n", i , uDMACnt));
283 }
284}
285# endif /* LOG_ENABLED */
286
287
288/**
289 * Appends a item to the scheduler.
290 *
291 * @returns VBox status code.
292 * @param pStreamShared The stream which scheduler should be modified.
293 * @param cbCur The period length in guest bytes.
294 * @param cbMaxPeriod The max period in guest bytes.
295 * @param idxLastBdle The last BDLE in the period.
296 * @param pProps The PCM properties.
297 * @param pcbBorrow Where to account for bytes borrowed across buffers
298 * to align scheduling items on frame boundraries.
299 */
300static int hdaR3StreamAddScheduleItem(PHDASTREAM pStreamShared, uint32_t cbCur, uint32_t cbMaxPeriod,
301 uint32_t idxLastBdle, PCPDMAUDIOPCMPROPS pProps, uint32_t *pcbBorrow)
302{
303 /* Check that we've got room (shouldn't ever be a problem). */
304 size_t idx = pStreamShared->State.cSchedule;
305 AssertLogRelReturn(idx + 1 < RT_ELEMENTS(pStreamShared->State.aSchedule), VERR_INTERNAL_ERROR_5);
306
307 /* Figure out the BDLE range for this period. */
308 uint32_t const idxFirstBdle = idx == 0 ? 0
309 : RT_MIN((uint32_t)( pStreamShared->State.aSchedule[idx - 1].idxFirst
310 + pStreamShared->State.aSchedule[idx - 1].cEntries),
311 idxLastBdle);
312
313 pStreamShared->State.aSchedule[idx].idxFirst = (uint8_t)idxFirstBdle;
314 pStreamShared->State.aSchedule[idx].cEntries = idxLastBdle >= idxFirstBdle
315 ? idxLastBdle - idxFirstBdle + 1
316 : pStreamShared->State.cBdles - idxFirstBdle + idxLastBdle + 1;
317
318 /* Deal with borrowing due to unaligned IOC buffers. */
319 uint32_t const cbBorrowed = *pcbBorrow;
320 if (cbBorrowed < cbCur)
321 cbCur -= cbBorrowed;
322 else
323 {
324 /* Note. We can probably gloss over this, but it's not a situation a sane guest would put us, so don't bother for now. */
325 ASSERT_GUEST_MSG_FAILED(("#%u: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
326 pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
327 LogRelMax(32, ("HDA: Stream #%u has a scheduling error: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
328 pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
329 return VERR_OUT_OF_RANGE;
330 }
331
332 uint32_t cbCurAligned = PDMAudioPropsRoundUpBytesToFrame(pProps, cbCur);
333 *pcbBorrow = cbCurAligned - cbCur;
334
335 /* Do we need to split up the period? */
336 if (cbCurAligned <= cbMaxPeriod)
337 {
338 pStreamShared->State.aSchedule[idx].cbPeriod = cbCurAligned;
339 pStreamShared->State.aSchedule[idx].cLoops = 1;
340 }
341 else
342 {
343 /* Reduce till we've below the threshold. */
344 uint32_t cbLoop = cbCurAligned;
345 do
346 cbLoop = cbLoop / 2;
347 while (cbLoop > cbMaxPeriod);
348 cbLoop = PDMAudioPropsRoundUpBytesToFrame(pProps, cbLoop);
349
350 /* Complete the scheduling item. */
351 pStreamShared->State.aSchedule[idx].cbPeriod = cbLoop;
352 pStreamShared->State.aSchedule[idx].cLoops = cbCurAligned / cbLoop;
353
354 /* If there is a remainder, add it as a separate entry (this is
355 why the schedule must be more than twice the size of the BDL).*/
356 cbCurAligned %= cbLoop;
357 if (cbCurAligned)
358 {
359 pStreamShared->State.aSchedule[idx + 1] = pStreamShared->State.aSchedule[idx];
360 idx++;
361 pStreamShared->State.aSchedule[idx].cbPeriod = cbCurAligned;
362 pStreamShared->State.aSchedule[idx].cLoops = 1;
363 }
364 }
365
366 /* Done. */
367 pStreamShared->State.cSchedule = (uint16_t)(idx + 1);
368
369 return VINF_SUCCESS;
370}
371
372/**
373 * Creates the DMA timer schedule for the stream
374 *
375 * This is called from the stream setup code.
376 *
377 * @returns VBox status code.
378 * @param pStreamShared The stream to create a schedule for. The BDL
379 * must be loaded.
380 * @param cSegments Number of BDL segments.
381 * @param cBufferIrqs Number of the BDLEs with IOC=1.
382 * @param cbTotal The total BDL length in guest bytes.
383 * @param cbMaxPeriod Max period in guest bytes. This is in case the
384 * guest want to play the whole "Der Ring des
385 * Nibelungen" cycle in one go.
386 * @param cTimerTicksPerSec The DMA timer frequency.
387 * @param pProps The PCM properties.
388 */
389static int hdaR3StreamCreateSchedule(PHDASTREAM pStreamShared, uint32_t cSegments, uint32_t cBufferIrqs, uint32_t cbTotal,
390 uint32_t cbMaxPeriod, uint64_t cTimerTicksPerSec, PCPDMAUDIOPCMPROPS pProps)
391{
392 int rc;
393
394 /*
395 * Reset scheduling state.
396 */
397 RT_ZERO(pStreamShared->State.aSchedule);
398 pStreamShared->State.cSchedule = 0;
399 pStreamShared->State.cSchedulePrologue = 0;
400 pStreamShared->State.idxSchedule = 0;
401 pStreamShared->State.idxScheduleLoop = 0;
402
403 /*
404 * Do the basic schedule compilation.
405 */
406 uint32_t cPotentialPrologue = 0;
407 uint32_t cbBorrow = 0;
408 uint32_t cbCur = 0;
409 uint32_t cbMin = UINT32_MAX;
410 pStreamShared->State.aSchedule[0].idxFirst = 0;
411 for (uint32_t i = 0; i < cSegments; i++)
412 {
413 cbCur += pStreamShared->State.aBdl[i].cb;
414 if (pStreamShared->State.aBdl[i].cb < cbMin)
415 cbMin = pStreamShared->State.aBdl[i].cb;
416 if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
417 {
418 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pProps, &cbBorrow);
419 ASSERT_GUEST_RC_RETURN(rc, rc);
420
421 if (cPotentialPrologue == 0)
422 cPotentialPrologue = pStreamShared->State.cSchedule;
423 cbCur = 0;
424 }
425 }
426
427 /*
428 * Deal with any loose ends.
429 */
430 if (cbCur && cBufferIrqs == 0)
431 {
432 /*
433 * No IOC. Vista ends up here, typically with three buffers configured.
434 *
435 * The perferred option here is to aim at processing one average BDLE with
436 * each DMA timer period, since that best matches how we update LPIB at
437 * present.
438 *
439 * The second alternative is to divide the whole span up into 3-4 periods
440 * to try increase our chances of keeping ahead of the guest. We may need
441 * to pick this if there are too few buffer descriptor or they are too small.
442 *
443 * However, what we probably should be doing is to do real DMA work whenever
444 * the guest reads a DMA related register (like LPIB) and just do 3-4 DMA
445 * timer periods, however we'll be postponing the DMA timer every time we
446 * return to ring-3 and signal the AIO, so in the end we'd probably not use
447 * the timer callback at all. (This is assuming a small shared per-stream
448 * buffer for keeping the DMA data in and that it's size will force a return
449 * to ring-3 often enough to keep the AIO thread going at a reasonable rate.)
450 */
451 Assert(cbCur == cbTotal);
452
453 /* Match the BDLEs 1:1 if there are 3 or more and that the smallest one
454 is at least 5ms big. */
455 if (cSegments >= 3 && PDMAudioPropsBytesToMilli(pProps, cbMin) >= 5 /*ms*/)
456 {
457 for (uint32_t i = 0; i < cSegments; i++)
458 {
459 rc = hdaR3StreamAddScheduleItem(pStreamShared, pStreamShared->State.aBdl[i].cb, cbMaxPeriod, i, pProps, &cbBorrow);
460 ASSERT_GUEST_RC_RETURN(rc, rc);
461 }
462 }
463 /* Otherwise, just divide the work into 3 or 4 portions and hope for the best.
464 It seems, though, that this only really work for windows vista if we avoid
465 working accross buffer lines. */
466 /** @todo This can be simplified/relaxed/uncluttered if we do DMA work when LPIB
467 * is read, assuming ofc that LPIB is read before each buffer update. */
468 else
469 {
470 uint32_t const cPeriods = cSegments != 3 && PDMAudioPropsBytesToMilli(pProps, cbCur) >= 4 * 5 /*ms*/
471 ? 4 : cSegments != 2 ? 3 : 2;
472 uint32_t const cbPeriod = PDMAudioPropsFloorBytesToFrame(pProps, cbCur / cPeriods);
473 uint32_t iBdle = 0;
474 uint32_t offBdle = 0;
475 for (uint32_t iPeriod = 0; iPeriod < cPeriods; iPeriod++)
476 {
477 if (iPeriod + 1 < cPeriods)
478 {
479 offBdle += cbPeriod;
480 while (iBdle < cSegments && offBdle >= pStreamShared->State.aBdl[iBdle].cb)
481 offBdle -= pStreamShared->State.aBdl[iBdle++].cb;
482 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbPeriod, cbMaxPeriod, offBdle != 0 ? iBdle : iBdle - 1,
483 pProps, &cbBorrow);
484 }
485 else
486 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur - iPeriod * cbPeriod, cbMaxPeriod, cSegments - 1,
487 pProps, &cbBorrow);
488 ASSERT_GUEST_RC_RETURN(rc, rc);
489 }
490
491 }
492 }
493 else if (cbCur)
494 {
495 /* The last BDLE didn't have IOC set, so we must continue processing
496 from the start till we hit one that has. */
497 uint32_t i;
498 for (i = 0; i < cSegments; i++)
499 {
500 cbCur += pStreamShared->State.aBdl[i].cb;
501 if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
502 break;
503 }
504 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pProps, &cbBorrow);
505 ASSERT_GUEST_RC_RETURN(rc, rc);
506
507 /* The initial scheduling items covering the wrap around area are
508 considered a prologue and must not repeated later. */
509 Assert(cPotentialPrologue);
510 pStreamShared->State.cSchedulePrologue = (uint8_t)cPotentialPrologue;
511 }
512
513 AssertLogRelMsgReturn(cbBorrow == 0, ("HDA: Internal scheduling error on stream #%u: cbBorrow=%#x cbTotal=%#x cbCur=%#x\n",
514 pStreamShared->u8SD, cbBorrow, cbTotal, cbCur),
515 VERR_INTERNAL_ERROR_3);
516
517 /*
518 * If there is just one BDLE with IOC set, we have to make sure
519 * we've got at least two periods scheduled, otherwise there is
520 * a very good chance the guest will overwrite the start of the
521 * buffer before we ever get around to reading it.
522 */
523 if (cBufferIrqs == 1)
524 {
525 uint32_t i = pStreamShared->State.cSchedulePrologue;
526 Assert(i < pStreamShared->State.cSchedule);
527 if ( i + 1 == pStreamShared->State.cSchedule
528 && pStreamShared->State.aSchedule[i].cLoops == 1)
529 {
530 uint32_t const cbFirstHalf = PDMAudioPropsFloorBytesToFrame(pProps, pStreamShared->State.aSchedule[i].cbPeriod / 2);
531 uint32_t const cbOtherHalf = pStreamShared->State.aSchedule[i].cbPeriod - cbFirstHalf;
532 pStreamShared->State.aSchedule[i].cbPeriod = cbFirstHalf;
533 if (cbFirstHalf == cbOtherHalf)
534 pStreamShared->State.aSchedule[i].cLoops = 2;
535 else
536 {
537 pStreamShared->State.aSchedule[i + 1] = pStreamShared->State.aSchedule[i];
538 pStreamShared->State.aSchedule[i].cbPeriod = cbOtherHalf;
539 pStreamShared->State.cSchedule++;
540 }
541 }
542 }
543
544 /*
545 * Go over the schduling entries and calculate the timer ticks for each period.
546 */
547 LogRel2(("HDA: Stream #%u schedule: %u items, %u prologue\n",
548 pStreamShared->u8SD, pStreamShared->State.cSchedule, pStreamShared->State.cSchedulePrologue));
549 uint64_t const cbPerSec = PDMAudioPropsFramesToBytes(pProps, pProps->uHz);
550 for (uint32_t i = 0; i < pStreamShared->State.cSchedule; i++)
551 {
552 uint64_t const cTicks = ASMMultU64ByU32DivByU32(cTimerTicksPerSec, pStreamShared->State.aSchedule[i].cbPeriod, cbPerSec);
553 AssertLogRelMsgReturn((uint32_t)cTicks == cTicks, ("cTicks=%RU64 (%#RX64)\n", cTicks, cTicks), VERR_INTERNAL_ERROR_4);
554 pStreamShared->State.aSchedule[i].cPeriodTicks = RT_MAX((uint32_t)cTicks, 16);
555 LogRel2(("HDA: #%u: %u ticks / %u bytes, %u loops, BDLE%u L %u\n", i, pStreamShared->State.aSchedule[i].cPeriodTicks,
556 pStreamShared->State.aSchedule[i].cbPeriod, pStreamShared->State.aSchedule[i].cLoops,
557 pStreamShared->State.aSchedule[i].idxFirst, pStreamShared->State.aSchedule[i].cEntries));
558 }
559
560 return VINF_SUCCESS;
561}
562
563
564/**
565 * Sets up ((re-)iniitalizes) an HDA stream.
566 *
567 * @returns VBox status code. VINF_NO_CHANGE if the stream does not need
568 * be set-up again because the stream's (hardware) parameters did
569 * not change.
570 * @param pDevIns The device instance.
571 * @param pThis The shared HDA device state (for HW register
572 * parameters).
573 * @param pStreamShared HDA stream to set up, shared portion.
574 * @param pStreamR3 HDA stream to set up, ring-3 portion.
575 * @param uSD Stream descriptor number to assign it.
576 */
577int hdaR3StreamSetUp(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
578{
579 /* This must be valid all times. */
580 AssertReturn(uSD < HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
581
582 /* These member can only change on data corruption, despite what the code does further down (bird). */
583 AssertReturn(pStreamShared->u8SD == uSD, VERR_WRONG_ORDER);
584 AssertReturn(pStreamR3->u8SD == uSD, VERR_WRONG_ORDER);
585
586 const uint64_t u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
587 HDA_STREAM_REG(pThis, BDPU, uSD));
588 const uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, uSD);
589 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, uSD);
590 const uint8_t u8FIFOS = HDA_STREAM_REG(pThis, FIFOS, uSD) + 1;
591 uint8_t u8FIFOW = hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, uSD));
592 const uint16_t u16FMT = HDA_STREAM_REG(pThis, FMT, uSD);
593
594 /* Is the bare minimum set of registers configured for the stream?
595 * If not, bail out early, as there's nothing to do here for us (yet). */
596 if ( !u64BDLBase
597 || !u16LVI
598 || !u32CBL
599 || !u8FIFOS
600 || !u8FIFOW
601 || !u16FMT)
602 {
603 LogFunc(("[SD%RU8] Registers not set up yet, skipping (re-)initialization\n", uSD));
604 return VINF_SUCCESS;
605 }
606
607 /*
608 * Convert the config to PDM PCM properties and configure the stream.
609 */
610 PPDMAUDIOSTREAMCFG pCfg = &pStreamShared->State.Cfg;
611 int rc = hdaR3SDFMTToPCMProps(u16FMT, &pCfg->Props);
612 if (RT_SUCCESS(rc))
613 pCfg->enmDir = hdaGetDirFromSD(uSD);
614 else
615 {
616 LogRelMax(32, ("HDA: Warning: Format 0x%x for stream #%RU8 not supported\n", HDA_STREAM_REG(pThis, FMT, uSD), uSD));
617 return rc;
618 }
619
620 ASSERT_GUEST_LOGREL_MSG_RETURN( PDMAudioPropsFrameSize(&pCfg->Props) > 0
621 && u32CBL % PDMAudioPropsFrameSize(&pCfg->Props) == 0,
622 ("CBL for stream #%RU8 does not align to frame size (u32CBL=%u cbFrameSize=%u)\n",
623 uSD, u32CBL, PDMAudioPropsFrameSize(&pCfg->Props)),
624 VERR_INVALID_PARAMETER);
625
626 /* Make sure the guest behaves regarding the stream's FIFO. */
627 ASSERT_GUEST_LOGREL_MSG_STMT(u8FIFOW <= u8FIFOS,
628 ("Guest tried setting a bigger FIFOW (%RU8) than FIFOS (%RU8), limiting\n", u8FIFOW, u8FIFOS),
629 u8FIFOW = u8FIFOS /* ASSUMES that u8FIFOS has been validated. */);
630
631 pStreamShared->u8SD = uSD;
632
633 /* Update all register copies so that we later know that something has changed. */
634 pStreamShared->u64BDLBase = u64BDLBase;
635 pStreamShared->u16LVI = u16LVI;
636 pStreamShared->u32CBL = u32CBL;
637 pStreamShared->u8FIFOS = u8FIFOS;
638 pStreamShared->u8FIFOW = u8FIFOW;
639 pStreamShared->u16FMT = u16FMT;
640
641 /* The the stream's name, based on the direction. */
642 switch (pCfg->enmDir)
643 {
644 case PDMAUDIODIR_IN:
645# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
646# error "Implement me!"
647# else
648 pCfg->enmPath = PDMAUDIOPATH_IN_LINE;
649 RTStrCopy(pCfg->szName, sizeof(pCfg->szName), "Line In");
650# endif
651 break;
652
653 case PDMAUDIODIR_OUT:
654 /* Destination(s) will be set in hdaR3AddStreamOut(),
655 * based on the channels / stream layout. */
656 break;
657
658 default:
659 AssertFailedReturn(VERR_NOT_SUPPORTED);
660 break;
661 }
662
663 LogRel2(("HDA: Stream #%RU8 DMA @ 0x%x (%RU32 bytes = %RU64ms total)\n", uSD, pStreamShared->u64BDLBase,
664 pStreamShared->u32CBL, PDMAudioPropsBytesToMilli(&pCfg->Props, pStreamShared->u32CBL)));
665
666 /*
667 * Load the buffer descriptor list.
668 *
669 * Section 3.6.2 states that "the BDL should not be modified unless the RUN
670 * bit is 0", so it should be within the specs to read it once here and not
671 * re-read any BDLEs later.
672 */
673 /* Reset BDL state. */
674 RT_ZERO(pStreamShared->State.aBdl);
675 pStreamShared->State.offCurBdle = 0;
676 pStreamShared->State.idxCurBdle = 0;
677
678 uint32_t /*const*/ cTransferFragments = (pStreamShared->u16LVI & 0xff) + 1;
679 if (cTransferFragments <= 1)
680 LogRel(("HDA: Warning: Stream #%RU8 transfer buffer count invalid: (%RU16)! Buggy guest audio driver!\n", uSD, pStreamShared->u16LVI));
681 AssertLogRelReturn(cTransferFragments <= RT_ELEMENTS(pStreamShared->State.aBdl), VERR_INTERNAL_ERROR_5);
682 pStreamShared->State.cBdles = cTransferFragments;
683
684 /* Load them. */
685 rc = PDMDevHlpPCIPhysRead(pDevIns, u64BDLBase, pStreamShared->State.aBdl,
686 sizeof(pStreamShared->State.aBdl[0]) * cTransferFragments);
687 AssertRC(rc);
688
689 /* Check what we just loaded. Refuse overly large buffer lists. */
690 uint64_t cbTotal = 0;
691 uint32_t cBufferIrqs = 0;
692 for (uint32_t i = 0; i < cTransferFragments; i++)
693 {
694 if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
695 cBufferIrqs++;
696 cbTotal += pStreamShared->State.aBdl[i].cb;
697 }
698 ASSERT_GUEST_STMT_RETURN(cbTotal < _2G,
699 LogRelMax(32, ("HDA: Error: Stream #%u is configured with an insane amount of buffer space - refusing do work with it: %RU64 (%#RX64) bytes.\n",
700 uSD, cbTotal, cbTotal)),
701 VERR_NOT_SUPPORTED);
702 ASSERT_GUEST_STMT_RETURN(cbTotal == u32CBL,
703 LogRelMax(32, ("HDA: Warning: Stream #%u has a mismatch between CBL and configured buffer space: %RU32 (%#RX32) vs %RU64 (%#RX64)\n",
704 uSD, u32CBL, u32CBL, cbTotal, cbTotal)),
705 VERR_NOT_SUPPORTED);
706
707 /*
708 * Create a DMA timer schedule.
709 */
710 rc = hdaR3StreamCreateSchedule(pStreamShared, cTransferFragments, cBufferIrqs, (uint32_t)cbTotal,
711 PDMAudioPropsMilliToBytes(&pCfg->Props, 100 /** @todo make configurable */),
712 PDMDevHlpTimerGetFreq(pDevIns, pStreamShared->hTimer), &pCfg->Props);
713 if (RT_FAILURE(rc))
714 return rc;
715
716 pStreamShared->State.cbCurDmaPeriod = pStreamShared->State.aSchedule[0].cbPeriod;
717
718 /*
719 * Calculate the transfer Hz for use in the circular buffer calculation
720 * and the average period for the scheduling hint.
721 */
722 uint32_t cbMaxPeriod = 0;
723 uint32_t cbMinPeriod = UINT32_MAX;
724 uint64_t cTicks = 0;
725 uint32_t cPeriods = 0;
726 for (uint32_t i = pStreamShared->State.cSchedulePrologue; i < pStreamShared->State.cSchedule; i++)
727 {
728 uint32_t cbPeriod = pStreamShared->State.aSchedule[i].cbPeriod;
729 cbMaxPeriod = RT_MAX(cbMaxPeriod, cbPeriod);
730 cbMinPeriod = RT_MIN(cbMinPeriod, cbPeriod);
731 cPeriods += pStreamShared->State.aSchedule[i].cLoops;
732 cTicks += pStreamShared->State.aSchedule[i].cPeriodTicks * pStreamShared->State.aSchedule[i].cLoops;
733 }
734 /* Only consider the prologue in relation to the max period. */
735 for (uint32_t i = 0; i < pStreamShared->State.cSchedulePrologue; i++)
736 cbMaxPeriod = RT_MAX(cbMaxPeriod, pStreamShared->State.aSchedule[i].cbPeriod);
737
738 AssertLogRelReturn(cPeriods > 0, VERR_INTERNAL_ERROR_3);
739 uint64_t const cbTransferPerSec = RT_MAX(PDMAudioPropsFramesToBytes(&pCfg->Props, pCfg->Props.uHz),
740 4096 /* zero div prevention: min is 6kHz, picked 4k in case I'm mistaken */);
741 unsigned uTransferHz = cbTransferPerSec * 1000 / cbMaxPeriod;
742 LogRel2(("HDA: Stream #%RU8 needs a %u.%03u Hz timer rate (period: %u..%u host bytes)\n",
743 uSD, uTransferHz / 1000, uTransferHz % 1000, cbMinPeriod, cbMaxPeriod));
744 uTransferHz /= 1000;
745
746 if (uTransferHz > 400) /* Anything above 400 Hz looks fishy -- tell the user. */
747 LogRelMax(32, ("HDA: Warning: Calculated transfer Hz rate for stream #%RU8 looks incorrect (%u), please re-run with audio debug mode and report a bug\n",
748 uSD, uTransferHz));
749
750 pStreamShared->State.cbAvgTransfer = (uint32_t)(cbTotal + cPeriods - 1) / cPeriods;
751
752 /* Calculate the average scheduling period length in nanoseconds. */
753 uint64_t const cTimerResolution = PDMDevHlpTimerGetFreq(pDevIns, pStreamShared->hTimer);
754 Assert(cTimerResolution <= UINT32_MAX);
755 uint64_t const cNsPerPeriod = ASMMultU64ByU32DivByU32(cTicks / cPeriods, RT_NS_1SEC, cTimerResolution);
756 AssertLogRelReturn(cNsPerPeriod > 0, VERR_INTERNAL_ERROR_3);
757
758 /* For input streams we must determin a pre-buffering requirement.
759 We use the initial delay as a basis here, though we must have at
760 least two max periods worth of data queued up due to the way we
761 work the AIO thread. */
762 pStreamShared->State.fInputPreBuffered = false;
763 pStreamShared->State.cbInputPreBuffer = cbMaxPeriod * 2;
764
765 /*
766 * Set up data transfer stuff.
767 */
768 /* Set I/O scheduling hint for the backends. */
769 pCfg->Device.cMsSchedulingHint = cNsPerPeriod > RT_NS_1MS ? (cNsPerPeriod + RT_NS_1MS / 2) / RT_NS_1MS : 1;
770 LogRel2(("HDA: Stream #%RU8 set scheduling hint for the backends to %RU32ms\n", uSD, pCfg->Device.cMsSchedulingHint));
771
772 /* Make sure to also update the stream's DMA counter (based on its current LPIB value). */
773 /** @todo r=bird: We use LPIB as-is here, so if it's not zero we have to
774 * locate the right place in the schedule and whatnot...
775 *
776 * This is a similar scenario as when loading state saved, btw.
777 */
778 if (HDA_STREAM_REG(pThis, LPIB, uSD) != 0)
779 LogRel2(("HDA: Warning! Stream #%RU8 is set up with LPIB=%#RX32 instead of zero!\n", uSD, HDA_STREAM_REG(pThis, LPIB, uSD)));
780 hdaStreamSetPositionAbs(pStreamShared, pDevIns, pThis, HDA_STREAM_REG(pThis, LPIB, uSD));
781
782# ifdef LOG_ENABLED
783 hdaR3BDLEDumpAll(pDevIns, pThis, pStreamShared->u64BDLBase, pStreamShared->u16LVI + 1);
784# endif
785
786 /*
787 * Set up internal ring buffer.
788 */
789
790 /* (Re-)Allocate the stream's internal DMA buffer,
791 * based on the timing *and* PCM properties we just got above. */
792 if (pStreamR3->State.pCircBuf)
793 {
794 RTCircBufDestroy(pStreamR3->State.pCircBuf);
795 pStreamR3->State.pCircBuf = NULL;
796 pStreamR3->State.StatDmaBufSize = 0;
797 pStreamR3->State.StatDmaBufUsed = 0;
798 }
799 pStreamShared->State.offWrite = 0;
800 pStreamShared->State.offRead = 0;
801
802 /*
803 * The default internal ring buffer size must be:
804 *
805 * - Large enough for at least three periodic DMA transfers.
806 *
807 * It is critically important that we don't experience underruns
808 * in the DMA OUT code, because it will cause the buffer processing
809 * to get skewed and possibly overlap with what the guest is updating.
810 * At the time of writing (2021-03-05) there is no code for getting
811 * back into sync there.
812 *
813 * - Large enough for at least three I/O scheduling hints.
814 *
815 * We want to lag behind a DMA period or two, but there must be
816 * sufficent space for the AIO thread to get schedule and shuffle
817 * data thru the mixer and onto the host audio hardware.
818 *
819 * - Both above with plenty to spare.
820 *
821 * So, just take the longest of the two periods and multipling it by 6.
822 * We aren't not talking about very large base buffers heres, so size isn't
823 * an issue.
824 *
825 * Note: Use pCfg->Props as PCM properties here, as we only want to store the
826 * samples we actually need, in other words, skipping the interleaved
827 * channels we don't support / need to save space.
828 */
829 uint32_t cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, RT_MS_1SEC * 6 / uTransferHz);
830 LogRel2(("HDA: Stream #%RU8 default ring buffer size is %RU32 bytes / %RU64 ms\n",
831 uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
832
833 uint32_t msCircBufCfg = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? pThis->cMsCircBufIn : pThis->cMsCircBufOut;
834 if (msCircBufCfg) /* Anything set via CFGM? */
835 {
836 cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, msCircBufCfg);
837 LogRel2(("HDA: Stream #%RU8 is using a custom ring buffer size of %RU32 bytes / %RU64 ms\n",
838 uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
839 }
840
841 /* Serious paranoia: */
842 ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf % PDMAudioPropsFrameSize(&pCfg->Props) == 0,
843 ("Ring buffer size (%RU32) for stream #%RU8 not aligned to the (host) frame size (%RU8)\n",
844 cbCircBuf, uSD, PDMAudioPropsFrameSize(&pCfg->Props)),
845 rc = VERR_INVALID_PARAMETER);
846 ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf, ("Ring buffer size for stream #%RU8 is invalid\n", uSD),
847 rc = VERR_INVALID_PARAMETER);
848 if (RT_SUCCESS(rc))
849 {
850 rc = RTCircBufCreate(&pStreamR3->State.pCircBuf, cbCircBuf);
851 if (RT_SUCCESS(rc))
852 {
853 pStreamR3->State.StatDmaBufSize = cbCircBuf;
854
855 /*
856 * Forward the timer frequency hint to TM as well for better accuracy on
857 * systems w/o preemption timers (also good for 'info timers').
858 */
859 PDMDevHlpTimerSetFrequencyHint(pDevIns, pStreamShared->hTimer, uTransferHz);
860 }
861 }
862
863 if (RT_FAILURE(rc))
864 LogRelMax(32, ("HDA: Initializing stream #%RU8 failed with %Rrc\n", uSD, rc));
865
866# ifdef VBOX_WITH_DTRACE
867 VBOXDD_HDA_STREAM_SETUP((uint32_t)uSD, rc, pStreamShared->State.Cfg.Props.uHz,
868 pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cPeriodTicks,
869 pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cbPeriod);
870# endif
871 return rc;
872}
873
874
875/**
876 * Worker for hdaR3StreamReset().
877 *
878 * @returns The default mixer sink, NULL if none found.
879 * @param pThisCC The ring-3 HDA device state.
880 * @param uSD SD# to return mixer sink for.
881 * NULL if not found / handled.
882 */
883static PHDAMIXERSINK hdaR3GetDefaultSink(PHDASTATER3 pThisCC, uint8_t uSD)
884{
885 if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN)
886 {
887 const uint8_t uFirstSDI = 0;
888
889 if (uSD == uFirstSDI) /* First SDI. */
890 return &pThisCC->SinkLineIn;
891# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
892 if (uSD == uFirstSDI + 1)
893 return &pThisCC->SinkMicIn;
894# else
895 /* If we don't have a dedicated Mic-In sink, use the always present Line-In sink. */
896 return &pThisCC->SinkLineIn;
897# endif
898 }
899 else
900 {
901 const uint8_t uFirstSDO = HDA_MAX_SDI;
902
903 if (uSD == uFirstSDO)
904 return &pThisCC->SinkFront;
905# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
906 if (uSD == uFirstSDO + 1)
907 return &pThisCC->SinkCenterLFE;
908 if (uSD == uFirstSDO + 2)
909 return &pThisCC->SinkRear;
910# endif
911 }
912
913 return NULL;
914}
915
916
917/**
918 * Resets an HDA stream.
919 *
920 * @param pThis The shared HDA device state.
921 * @param pThisCC The ring-3 HDA device state.
922 * @param pStreamShared HDA stream to reset (shared).
923 * @param pStreamR3 HDA stream to reset (ring-3).
924 * @param uSD Stream descriptor (SD) number to use for this stream.
925 */
926void hdaR3StreamReset(PHDASTATE pThis, PHDASTATER3 pThisCC, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
927{
928 LogFunc(("[SD%RU8] Reset\n", uSD));
929
930 /*
931 * Assert some sanity.
932 */
933 AssertPtr(pThis);
934 AssertPtr(pStreamShared);
935 AssertPtr(pStreamR3);
936 Assert(uSD < HDA_MAX_STREAMS);
937 Assert(pStreamShared->u8SD == uSD);
938 Assert(pStreamR3->u8SD == uSD);
939 AssertMsg(!pStreamShared->State.fRunning, ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
940
941 /*
942 * Set reset state.
943 */
944 Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false); /* No nested calls. */
945 ASMAtomicXchgBool(&pStreamShared->State.fInReset, true);
946
947 /*
948 * Second, initialize the registers.
949 */
950 /* See 6.2.33: Clear on reset. */
951 HDA_STREAM_REG(pThis, STS, uSD) = 0;
952 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
953 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
954 HDA_STREAM_REG(pThis, CTL, uSD) = HDA_SDCTL_TP | (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_SDCTL_SRST);
955 /* ICH6 defines default values (120 bytes for input and 192 bytes for output descriptors) of FIFO size. 18.2.39. */
956 HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_192B;
957 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
958 HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
959 HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
960 HDA_STREAM_REG(pThis, CBL, uSD) = 0;
961 HDA_STREAM_REG(pThis, LVI, uSD) = 0;
962 HDA_STREAM_REG(pThis, FMT, uSD) = 0;
963 HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
964 HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
965
966 /* Assign the default mixer sink to the stream. */
967 pStreamR3->pMixSink = hdaR3GetDefaultSink(pThisCC, uSD);
968 if (pStreamR3->State.pAioRegSink)
969 {
970 int rc2 = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
971 AssertRC(rc2);
972 pStreamR3->State.pAioRegSink = NULL;
973 }
974
975 /* Reset transfer stuff. */
976 pStreamShared->State.cTransferPendingInterrupts = 0;
977 pStreamShared->State.tsTransferLast = 0;
978 pStreamShared->State.tsTransferNext = 0;
979
980 /* Initialize timestamps. */
981 pStreamShared->State.tsLastTransferNs = 0;
982 pStreamShared->State.tsLastReadNs = 0;
983 pStreamShared->State.tsStart = 0;
984
985 RT_ZERO(pStreamShared->State.aBdl);
986 RT_ZERO(pStreamShared->State.aSchedule);
987 pStreamShared->State.offCurBdle = 0;
988 pStreamShared->State.cBdles = 0;
989 pStreamShared->State.idxCurBdle = 0;
990 pStreamShared->State.cSchedulePrologue = 0;
991 pStreamShared->State.cSchedule = 0;
992 pStreamShared->State.idxSchedule = 0;
993 pStreamShared->State.idxScheduleLoop = 0;
994 pStreamShared->State.fInputPreBuffered = false;
995
996 if (pStreamR3->State.pCircBuf)
997 RTCircBufReset(pStreamR3->State.pCircBuf);
998 pStreamShared->State.offWrite = 0;
999 pStreamShared->State.offRead = 0;
1000
1001 /* Report that we're done resetting this stream. */
1002 HDA_STREAM_REG(pThis, CTL, uSD) = 0;
1003
1004# ifdef VBOX_WITH_DTRACE
1005 VBOXDD_HDA_STREAM_RESET((uint32_t)uSD);
1006# endif
1007 LogFunc(("[SD%RU8] Reset\n", uSD));
1008
1009 /* Exit reset mode. */
1010 ASMAtomicXchgBool(&pStreamShared->State.fInReset, false);
1011}
1012
1013/**
1014 * Enables or disables an HDA audio stream.
1015 *
1016 * @returns VBox status code.
1017 * @param pThis The shared HDA device state.
1018 * @param pStreamShared HDA stream to enable or disable - shared bits.
1019 * @param pStreamR3 HDA stream to enable or disable - ring-3 bits.
1020 * @param fEnable Whether to enable or disble the stream.
1021 */
1022int hdaR3StreamEnable(PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fEnable)
1023{
1024 AssertPtr(pStreamR3);
1025 AssertPtr(pStreamShared);
1026
1027 LogFunc(("[SD%RU8] fEnable=%RTbool, pMixSink=%p\n", pStreamShared->u8SD, fEnable, pStreamR3->pMixSink));
1028
1029 /* First, enable or disable the stream and the stream's sink, if any. */
1030 int rc = VINF_SUCCESS;
1031 PAUDMIXSINK const pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
1032 if (pSink)
1033 {
1034 if (fEnable)
1035 {
1036 if (pStreamR3->State.pAioRegSink != pSink)
1037 {
1038 if (pStreamR3->State.pAioRegSink)
1039 {
1040 rc = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
1041 AssertRC(rc);
1042 }
1043 rc = AudioMixerSinkAddUpdateJob(pSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3,
1044 pStreamShared->State.Cfg.Device.cMsSchedulingHint);
1045 AssertLogRelRC(rc);
1046 pStreamR3->State.pAioRegSink = RT_SUCCESS(rc) ? pSink : NULL;
1047 }
1048 rc = AudioMixerSinkStart(pSink);
1049 }
1050 else
1051 rc = AudioMixerSinkDrainAndStop(pSink,
1052 pStreamR3->State.pCircBuf ? (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf) : 0);
1053 }
1054 if ( RT_SUCCESS(rc)
1055 && fEnable
1056 && pStreamR3->Dbg.Runtime.fEnabled)
1057 {
1058 Assert(AudioHlpPcmPropsAreValid(&pStreamShared->State.Cfg.Props));
1059
1060 if (fEnable)
1061 {
1062 if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileStream))
1063 {
1064 int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileStream, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
1065 &pStreamShared->State.Cfg.Props);
1066 AssertRC(rc2);
1067 }
1068
1069 if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMARaw))
1070 {
1071 int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMARaw, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
1072 &pStreamShared->State.Cfg.Props);
1073 AssertRC(rc2);
1074 }
1075
1076 if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped))
1077 {
1078 int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
1079 &pStreamShared->State.Cfg.Props);
1080 AssertRC(rc2);
1081 }
1082 }
1083 }
1084
1085 if (RT_SUCCESS(rc))
1086 {
1087 if (fEnable)
1088 pStreamShared->State.tsTransferLast = 0; /* Make sure it's not stale and messes up WALCLK calculations. */
1089 pStreamShared->State.fRunning = fEnable;
1090
1091 /*
1092 * Set the FIFORDY bit when we start running and clear it when stopping.
1093 *
1094 * This prevents Linux from timing out in snd_hdac_stream_sync when starting
1095 * a stream. Technically, Linux also uses the SSYNC feature there, but we
1096 * can get away with just setting the FIFORDY bit for now.
1097 */
1098 if (fEnable)
1099 HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) |= HDA_SDSTS_FIFORDY;
1100 else
1101 HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) &= ~HDA_SDSTS_FIFORDY;
1102 }
1103
1104 LogFunc(("[SD%RU8] rc=%Rrc\n", pStreamShared->u8SD, rc));
1105 return rc;
1106}
1107
1108/**
1109 * Marks the stream as started.
1110 *
1111 * Used after the stream has been enabled and the DMA timer has been armed.
1112 */
1113void hdaR3StreamMarkStarted(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow)
1114{
1115 pStreamShared->State.tsLastReadNs = RTTimeNanoTS();
1116 pStreamShared->State.tsStart = tsNow;
1117 Log3Func(("#%u: tsStart=%RU64 tsLastReadNs=%RU64\n",
1118 pStreamShared->u8SD, pStreamShared->State.tsStart, pStreamShared->State.tsLastReadNs));
1119 RT_NOREF(pDevIns, pThis);
1120}
1121
1122/**
1123 * Marks the stream as stopped.
1124 */
1125void hdaR3StreamMarkStopped(PHDASTREAM pStreamShared)
1126{
1127 Log3Func(("#%u\n", pStreamShared->u8SD));
1128 RT_NOREF(pStreamShared);
1129}
1130
1131#endif /* IN_RING3 */
1132#if defined(IN_RING3) || defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
1133
1134/**
1135 * Updates an HDA stream's current read or write buffer position (depending on the stream type) by
1136 * setting its associated LPIB register and DMA position buffer (if enabled) to an absolute value.
1137 *
1138 * @param pStreamShared HDA stream to update read / write position for (shared).
1139 * @param pDevIns The device instance.
1140 * @param pThis The shared HDA device state.
1141 * @param uLPIB Absolute position (in bytes) to set current read / write position to.
1142 */
1143static void hdaStreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB)
1144{
1145 AssertPtrReturnVoid(pStreamShared);
1146 AssertMsgStmt(uLPIB <= pStreamShared->u32CBL, ("%#x\n", uLPIB), uLPIB = pStreamShared->u32CBL);
1147
1148 Log3Func(("[SD%RU8] LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n", pStreamShared->u8SD, uLPIB, pThis->fDMAPosition));
1149
1150 /* Update LPIB in any case. */
1151 HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) = uLPIB;
1152
1153 /* Do we need to tell the current DMA position? */
1154 if (pThis->fDMAPosition)
1155 {
1156 /*
1157 * Linux switched to using the position buffers some time during 2.6.x.
1158 * 2.6.12 used LPIB, 2.6.17 defaulted to DMA position buffers, between
1159 * the two version things were being changing quite a bit.
1160 *
1161 * Since 2.6.17, they will treat a zero DMA position value during the first
1162 * period/IRQ as reason to fall back to LPIB mode (see azx_position_ok in
1163 * 2.6.27+, and azx_pcm_pointer before that). They later also added
1164 * UINT32_MAX to the values causing same.
1165 *
1166 * Since 2.6.35 azx_position_ok will read the wall clock register before
1167 * determining the position.
1168 */
1169 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns,
1170 pThis->u64DPBase + (pStreamShared->u8SD * 2 * sizeof(uint32_t)),
1171 (void *)&uLPIB, sizeof(uint32_t));
1172 AssertRC(rc2);
1173 }
1174}
1175
1176
1177/**
1178 * Updates an HDA stream's current read or write buffer position (depending on the stream type) by
1179 * adding a value to its associated LPIB register and DMA position buffer (if enabled).
1180 *
1181 * @note Handles automatic CBL wrap-around.
1182 *
1183 * @param pStreamShared HDA stream to update read / write position for (shared).
1184 * @param pDevIns The device instance.
1185 * @param pThis The shared HDA device state.
1186 * @param cbToAdd Position (in bytes) to add to the current read / write position.
1187 */
1188static void hdaStreamSetPositionAdd(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t cbToAdd)
1189{
1190 if (cbToAdd) /* No need to update anything if 0. */
1191 {
1192 uint32_t const uCBL = pStreamShared->u32CBL;
1193 if (uCBL) /* paranoia */
1194 {
1195 uint32_t uNewLpid = HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) + cbToAdd;
1196# if 1 /** @todo r=bird: this is wrong according to the spec */
1197 uNewLpid %= uCBL;
1198# else
1199 /* The spec says it goes to CBL then wraps arpimd to 1, not back to zero. See 3.3.37. */
1200 if (uNewLpid > uCBL)
1201 uNewLpid %= uCBL;
1202# endif
1203 hdaStreamSetPositionAbs(pStreamShared, pDevIns, pThis, uNewLpid);
1204 }
1205 }
1206}
1207
1208#endif /* IN_RING3 || VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
1209#ifdef IN_RING3
1210
1211/**
1212 * Retrieves the available size of (buffered) audio data (in bytes) of a given HDA stream.
1213 *
1214 * @returns Available data (in bytes).
1215 * @param pStreamR3 HDA stream to retrieve size for (ring-3).
1216 */
1217static uint32_t hdaR3StreamGetUsed(PHDASTREAMR3 pStreamR3)
1218{
1219 AssertPtrReturn(pStreamR3, 0);
1220
1221 if (pStreamR3->State.pCircBuf)
1222 return (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1223 return 0;
1224}
1225
1226/**
1227 * Retrieves the free size of audio data (in bytes) of a given HDA stream.
1228 *
1229 * @returns Free data (in bytes).
1230 * @param pStreamR3 HDA stream to retrieve size for (ring-3).
1231 */
1232static uint32_t hdaR3StreamGetFree(PHDASTREAMR3 pStreamR3)
1233{
1234 AssertPtrReturn(pStreamR3, 0);
1235
1236 if (pStreamR3->State.pCircBuf)
1237 return (uint32_t)RTCircBufFree(pStreamR3->State.pCircBuf);
1238 return 0;
1239}
1240
1241#endif /* IN_RING3 */
1242#if defined(IN_RING3) || defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
1243
1244/**
1245 * Get the current address and number of bytes left in the current BDLE.
1246 *
1247 * @returns The current physical address.
1248 * @param pStreamShared The stream to check.
1249 * @param pcbLeft The number of bytes left at the returned address.
1250 */
1251DECLINLINE(RTGCPHYS) hdaStreamDmaBufGet(PHDASTREAM pStreamShared, uint32_t *pcbLeft)
1252{
1253 uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1254 AssertStmt(idxBdle < pStreamShared->State.cBdles, idxBdle = 0);
1255
1256 uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1257 uint32_t offCurBdle = pStreamShared->State.offCurBdle;
1258 AssertStmt(pStreamShared->State.offCurBdle <= cbCurBdl, offCurBdle = cbCurBdl);
1259
1260 *pcbLeft = cbCurBdl - offCurBdle;
1261 return pStreamShared->State.aBdl[idxBdle].GCPhys + offCurBdle;
1262}
1263
1264/**
1265 * Checks if the current BDLE is completed.
1266 *
1267 * @retval true if complete
1268 * @retval false if not.
1269 * @param pStreamShared The stream to check.
1270 */
1271DECLINLINE(bool) hdaStreamDmaBufIsComplete(PHDASTREAM pStreamShared)
1272{
1273 uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1274 AssertReturn(idxBdle < pStreamShared->State.cBdles, true);
1275
1276 uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1277 uint32_t const offCurBdle = pStreamShared->State.offCurBdle;
1278 Assert(offCurBdle <= cbCurBdl);
1279 return offCurBdle >= cbCurBdl;
1280}
1281
1282/**
1283 * Checks if the current BDLE needs a completion IRQ.
1284 *
1285 * @retval true if IRQ is needed.
1286 * @retval false if not.
1287 * @param pStreamShared The stream to check.
1288 */
1289DECLINLINE(bool) hdaStreamDmaBufNeedsIrq(PHDASTREAM pStreamShared)
1290{
1291 uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1292 AssertReturn(idxBdle < pStreamShared->State.cBdles, false);
1293 return (pStreamShared->State.aBdl[idxBdle].fFlags & HDA_BDLE_F_IOC) != 0;
1294}
1295
1296/**
1297 * Advances the DMA engine to the next BDLE.
1298 *
1299 * @param pStreamShared The stream which DMA engine is to be updated.
1300 */
1301DECLINLINE(void) hdaStreamDmaBufAdvanceToNext(PHDASTREAM pStreamShared)
1302{
1303 uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1304 Assert(pStreamShared->State.offCurBdle == pStreamShared->State.aBdl[idxBdle].cb);
1305
1306 if (idxBdle < pStreamShared->State.cBdles - 1)
1307 idxBdle++;
1308 else
1309 idxBdle = 0;
1310 pStreamShared->State.idxCurBdle = idxBdle;
1311 pStreamShared->State.offCurBdle = 0;
1312}
1313
1314#endif /* defined(IN_RING3) || defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA) */
1315#ifdef IN_RING3
1316
1317/**
1318 * Common do-DMA prologue code.
1319 *
1320 * @retval true if DMA processing can take place
1321 * @retval false if caller should return immediately.
1322 * @param pThis The shared HDA device state.
1323 * @param pStreamShared HDA stream to update (shared).
1324 * @param pStreamR3 HDA stream to update (ring-3).
1325 * @param uSD The stream ID (for asserting).
1326 * @param tsNowNs The current RTTimeNano() value.
1327 * @param pszFunction The function name (for logging).
1328 */
1329DECLINLINE(bool) hdaR3StreamDoDmaPrologue(PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD,
1330 uint64_t tsNowNs, const char *pszFunction)
1331{
1332 RT_NOREF(uSD, pszFunction);
1333
1334 /*
1335 * Check if we should skip town...
1336 */
1337 /* Stream not running (anymore)? */
1338 if (pStreamShared->State.fRunning)
1339 { /* likely */ }
1340 else
1341 {
1342 Log3(("%s: [SD%RU8] Not running, skipping transfer\n", pszFunction, uSD));
1343 return false;
1344 }
1345
1346 if (!(HDA_STREAM_REG(pThis, STS, uSD) & HDA_SDSTS_BCIS))
1347 { /* likely */ }
1348 else
1349 {
1350 /** @todo r=bird: This is a bit fishy. We should make effort the reschedule
1351 * the transfer immediately after the guest clears the interrupt.
1352 * The same fishy code is present in AC'97 with just a little
1353 * explanation as here, see @bugref{9890#c95}.
1354 *
1355 * The reasoning is probably that the developer noticed some windows
1356 * versions don't like having their BCIS interrupts bundled. There were
1357 * comments to that effect elsewhere, probably as a result of a fixed
1358 * uTimerHz approach to DMA scheduling. However, pausing DMA for a
1359 * period isn't going to help us with the host backends, as they don't
1360 * pause and will want samples ASAP. So, we should at least unpause
1361 * DMA as quickly as we possible when BCIS is cleared. We might even
1362 * not skip it iff the DMA work here doesn't involve raising any IOC,
1363 * which is possible although unlikely. */
1364 Log3(("%s: [SD%RU8] BCIS bit set, skipping transfer\n", pszFunction, uSD));
1365 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaSkippedPendingBcis);
1366 Log(("%s: [SD%RU8] BCIS bit set, skipping transfer\n", pszFunction, uSD));
1367# ifdef HDA_STRICT
1368 /* Timing emulation bug or guest is misbehaving -- let me know. */
1369 AssertMsgFailed(("%s: BCIS bit for stream #%RU8 still set when it shouldn't\n", pszFunction, uSD));
1370# endif
1371 return false;
1372 }
1373
1374 /*
1375 * Stream sanity checks.
1376 */
1377 /* Register sanity checks. */
1378 Assert(uSD < HDA_MAX_STREAMS);
1379 Assert(pStreamShared->u64BDLBase);
1380 Assert(pStreamShared->u32CBL);
1381 Assert(pStreamShared->u8FIFOS);
1382
1383 /* State sanity checks. */
1384 Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false);
1385 Assert(ASMAtomicReadBool(&pStreamShared->State.fRunning));
1386
1387 /*
1388 * Some timestamp stuff for logging/debugging.
1389 */
1390 /*const uint64_t tsNowNs = RTTimeNanoTS();*/
1391 Log3(("%s: [SD%RU8] tsDeltaNs=%'RU64 ns\n", pszFunction, uSD, tsNowNs - pStreamShared->State.tsLastTransferNs));
1392 pStreamShared->State.tsLastTransferNs = tsNowNs;
1393
1394 return true;
1395}
1396
1397/**
1398 * Common do-DMA epilogue.
1399 *
1400 * @param pDevIns The device instance.
1401 * @param pStreamShared The HDA stream (shared).
1402 * @param pStreamR3 The HDA stream (ring-3).
1403 */
1404DECLINLINE(void) hdaR3StreamDoDmaEpilogue(PPDMDEVINS pDevIns, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
1405{
1406 /*
1407 * We must update this in the epilogue rather than in the prologue
1408 * as it is used for WALCLK calculation and we must make sure the
1409 * guest doesn't think we've processed the current period till we
1410 * actually have.
1411 */
1412 pStreamShared->State.tsTransferLast = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer);
1413
1414 /*
1415 * Update the buffer statistics.
1416 */
1417 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1418}
1419
1420#endif /* IN_RING3 */
1421
1422#if defined(IN_RING3) || defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
1423/**
1424 * Completes a BDLE at the end of a DMA loop iteration, if possible.
1425 *
1426 * @retval true if buffer completed and new loaded.
1427 * @retval false if buffer not completed.
1428 * @param pDevIns The device instance.
1429 * @param pThis The shared HDA device state.
1430 * @param pStreamShared HDA stream to update (shared).
1431 * @param pszFunction The function name (for logging).
1432 */
1433DECLINLINE(bool) hdaStreamDoDmaMaybeCompleteBuffer(PPDMDEVINS pDevIns, PHDASTATE pThis,
1434 PHDASTREAM pStreamShared, const char *pszFunction)
1435{
1436 RT_NOREF(pszFunction);
1437
1438 /*
1439 * Is the buffer descriptor complete.
1440 */
1441 if (hdaStreamDmaBufIsComplete(pStreamShared))
1442 {
1443 Log3(("%s: [SD%RU8] Completed BDLE%u %#RX64 LB %#RX32 fFlags=%#x\n", pszFunction, pStreamShared->u8SD,
1444 pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1445 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1446 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags));
1447
1448 /* Does the current BDLE require an interrupt to be sent? */
1449 if (hdaStreamDmaBufNeedsIrq(pStreamShared))
1450 {
1451 /* If the IOCE ("Interrupt On Completion Enable") bit of the SDCTL
1452 register is set we need to generate an interrupt. */
1453 if (HDA_STREAM_REG(pThis, CTL, pStreamShared->u8SD) & HDA_SDCTL_IOCE)
1454 {
1455 /* Assert the interrupt before actually fetching the next BDLE below. */
1456 pStreamShared->State.cTransferPendingInterrupts = 1;
1457 Log3(("%s: [SD%RU8] Scheduling interrupt\n", pszFunction, pStreamShared->u8SD));
1458
1459 /* Trigger an interrupt first and let hdaRegWriteSDSTS() deal with
1460 * ending / beginning of a period. */
1461 /** @todo r=bird: What does the above comment mean? */
1462 HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) |= HDA_SDSTS_BCIS;
1463 HDA_PROCESS_INTERRUPT(pDevIns, pThis);
1464 }
1465 }
1466
1467 /*
1468 * Advance to the next BDLE.
1469 */
1470 hdaStreamDmaBufAdvanceToNext(pStreamShared);
1471 return true;
1472 }
1473
1474 Log3(("%s: [SD%RU8] Incomplete BDLE%u %#RX64 LB %#RX32 fFlags=%#x: off=%#RX32\n", pszFunction, pStreamShared->u8SD,
1475 pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1476 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1477 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags, pStreamShared->State.offCurBdle));
1478 return false;
1479}
1480#endif /* IN_RING3 || VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
1481
1482#ifdef IN_RING3
1483
1484/**
1485 * Does DMA transfer for an HDA input stream.
1486 *
1487 * Reads audio data from the HDA stream's internal DMA buffer and writing to
1488 * guest memory.
1489 *
1490 * @param pDevIns The device instance.
1491 * @param pThis The shared HDA device state.
1492 * @param pStreamShared HDA stream to update (shared).
1493 * @param pStreamR3 HDA stream to update (ring-3).
1494 * @param cbToConsume The max amount of data to consume from the
1495 * internal DMA buffer. The caller will make sure
1496 * this is always the transfer size fo the current
1497 * period (unless something is seriously wrong).
1498 * @param fWriteSilence Whether to feed the guest silence rather than
1499 * fetching bytes from the internal DMA buffer.
1500 * This is set initially while we pre-buffer a
1501 * little bit of input, so we can better handle
1502 * time catch-ups and other schduling fun.
1503 * @param tsNowNs The current RTTimeNano() value.
1504 *
1505 * @remarks Caller owns the stream lock.
1506 */
1507static void hdaR3StreamDoDmaInput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1508 PHDASTREAMR3 pStreamR3, uint32_t const cbToConsume, bool fWriteSilence, uint64_t tsNowNs)
1509{
1510 uint8_t const uSD = pStreamShared->u8SD;
1511 LogFlowFunc(("ENTER - #%u cbToConsume=%#x%s\n", uSD, cbToConsume, fWriteSilence ? " silence" : ""));
1512
1513 /*
1514 * Common prologue.
1515 */
1516 if (hdaR3StreamDoDmaPrologue(pThis, pStreamShared, pStreamR3, uSD, tsNowNs, "hdaR3StreamDoDmaInput"))
1517 { /* likely */ }
1518 else
1519 return;
1520
1521 /*
1522 *
1523 * The DMA copy loop.
1524 *
1525 * Note! Unaligned BDLEs shouldn't be a problem since the circular buffer
1526 * doesn't care about alignment. Only, we have to read the rest
1527 * of the incomplete frame from it ASAP.
1528 */
1529 PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1530 uint32_t cbLeft = cbToConsume;
1531 Assert(cbLeft == pStreamShared->State.cbCurDmaPeriod);
1532 Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1533
1534 while (cbLeft > 0)
1535 {
1536 STAM_PROFILE_START(&pThis->StatIn, a);
1537
1538 /*
1539 * Figure out how much we can read & write in this iteration.
1540 */
1541 uint32_t cbChunk = 0;
1542 RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1543
1544 if (cbChunk <= cbLeft)
1545 { /* very likely */ }
1546 else
1547 cbChunk = cbLeft;
1548
1549 uint32_t cbWritten = 0;
1550 if (!fWriteSilence)
1551 {
1552 /*
1553 * Write the host data directly into the guest buffers.
1554 */
1555 while (cbChunk > 0)
1556 {
1557 /* Grab internal DMA buffer space and read into it. */
1558 void /*const*/ *pvBufSrc;
1559 size_t cbBufSrc;
1560 RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvBufSrc, &cbBufSrc);
1561 AssertBreakStmt(cbBufSrc, RTCircBufReleaseReadBlock(pCircBuf, 0));
1562
1563 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, pvBufSrc, cbBufSrc);
1564 AssertRC(rc2);
1565
1566# ifdef HDA_DEBUG_SILENCE
1567 fix me if relevant;
1568# endif
1569 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.pFileDMARaw))
1570 { /* likely */ }
1571 else
1572 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufSrc, cbBufSrc);
1573
1574# ifdef VBOX_WITH_DTRACE
1575 VBOXDD_HDA_STREAM_DMA_IN((uint32_t)uSD, (uint32_t)cbBufSrc, pStreamShared->State.offRead);
1576# endif
1577 pStreamShared->State.offRead += cbBufSrc;
1578 RTCircBufReleaseReadBlock(pCircBuf, cbBufSrc);
1579 STAM_COUNTER_ADD(&pThis->StatBytesWritten, cbBufSrc);
1580
1581 /* advance */
1582 cbChunk -= (uint32_t)cbBufSrc;
1583 cbWritten += (uint32_t)cbBufSrc;
1584 GCPhys += cbBufSrc;
1585 pStreamShared->State.offCurBdle += (uint32_t)cbBufSrc;
1586 }
1587 }
1588 /*
1589 * Write silence. Since we only do signed formats, we can use the zero
1590 * buffers from IPRT as source here.
1591 */
1592 else
1593 {
1594 Assert(PDMAudioPropsIsSigned(&pStreamShared->State.Cfg.Props));
1595 while (cbChunk > 0)
1596 {
1597 /* Write it to the guest buffer. */
1598 uint32_t cbToWrite = RT_MIN(sizeof(g_abRTZero64K), cbChunk);
1599 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, g_abRTZero64K, cbToWrite);
1600 AssertRC(rc2);
1601 STAM_COUNTER_ADD(&pThis->StatBytesWritten, cbToWrite);
1602
1603 /* advance */
1604 cbWritten += cbToWrite;
1605 cbChunk -= cbToWrite;
1606 GCPhys += cbToWrite;
1607 pStreamShared->State.offCurBdle += cbToWrite;
1608 }
1609 }
1610
1611 cbLeft -= cbWritten;
1612 STAM_PROFILE_STOP(&pThis->StatIn, a);
1613
1614 /*
1615 * Complete the buffer if necessary (common with the output DMA code).
1616 *
1617 * Must update the DMA position before we do this as the buffer IRQ may
1618 * fire on another vCPU and run in parallel to us, although it is very
1619 * unlikely it can make much progress as long as we're sitting on the
1620 * lock, it could still read the DMA position (Linux won't, as it reads
1621 * WALCLK and possibly SDnSTS before the DMA position).
1622 */
1623 hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbWritten);
1624 hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaR3StreamDoDmaInput");
1625 }
1626
1627 Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1628
1629 /*
1630 * Common epilogue.
1631 */
1632 hdaR3StreamDoDmaEpilogue(pDevIns, pStreamShared, pStreamR3);
1633
1634 /*
1635 * Log and leave.
1636 */
1637 Log3Func(("LEAVE - [SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1638 uSD, cbToConsume, pStreamShared->State.cbCurDmaPeriod, pStreamShared->State.offRead - cbToConsume,
1639 pStreamShared->State.cTransferPendingInterrupts));
1640}
1641
1642
1643/**
1644 * Input streams: Pulls data from the mixer, putting it in the internal DMA
1645 * buffer.
1646 *
1647 * @param pStreamShared HDA stream to update (shared).
1648 * @param pStreamR3 HDA stream to update (ring-3 bits).
1649 * @param pSink The mixer sink to pull from.
1650 */
1651static void hdaR3StreamPullFromMixer(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink)
1652{
1653# ifdef LOG_ENABLED
1654 uint64_t const offWriteOld = pStreamShared->State.offWrite;
1655# endif
1656 pStreamShared->State.offWrite = AudioMixerSinkTransferToCircBuf(pSink,
1657 pStreamR3->State.pCircBuf,
1658 pStreamShared->State.offWrite,
1659 pStreamR3->u8SD,
1660 pStreamR3->Dbg.Runtime.fEnabled
1661 ? pStreamR3->Dbg.Runtime.pFileStream : NULL);
1662
1663 Log3Func(("[SD%RU8] transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
1664 pStreamShared->State.offWrite - offWriteOld, pStreamShared->State.offWrite));
1665
1666 /* Update buffer stats. */
1667 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1668}
1669
1670
1671/**
1672 * Does DMA transfer for an HDA output stream.
1673 *
1674 * This transfers one DMA timer period worth of data from the guest and into the
1675 * internal DMA buffer.
1676 *
1677 * @param pDevIns The device instance.
1678 * @param pThis The shared HDA device state.
1679 * @param pStreamShared HDA stream to update (shared).
1680 * @param pStreamR3 HDA stream to update (ring-3).
1681 * @param cbToProduce The max amount of data to produce (i.e. put into
1682 * the circular buffer). Unless something is going
1683 * seriously wrong, this will always be transfer
1684 * size for the current period.
1685 * @param tsNowNs The current RTTimeNano() value.
1686 *
1687 * @remarks Caller owns the stream lock.
1688 */
1689static void hdaR3StreamDoDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1690 PHDASTREAMR3 pStreamR3, uint32_t const cbToProduce, uint64_t tsNowNs)
1691{
1692 uint8_t const uSD = pStreamShared->u8SD;
1693 LogFlowFunc(("ENTER - #%u cbToProduce=%#x\n", uSD, cbToProduce));
1694
1695 /*
1696 * Common prologue.
1697 */
1698 if (hdaR3StreamDoDmaPrologue(pThis, pStreamShared, pStreamR3, uSD, tsNowNs, "hdaR3StreamDoDmaOutput"))
1699 { /* likely */ }
1700 else
1701 return;
1702
1703 /*
1704 *
1705 * The DMA copy loop.
1706 *
1707 * Note! Unaligned BDLEs shouldn't be a problem since the circular buffer
1708 * doesn't care about alignment. Only, we have to write the rest
1709 * of the incomplete frame to it ASAP.
1710 */
1711 PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1712 uint32_t cbLeft = cbToProduce;
1713# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
1714 Assert(cbLeft <= pStreamShared->State.cbCurDmaPeriod); /* a little pointless with the DMA'ing on LPIB read. */
1715# else
1716 Assert(cbLeft == pStreamShared->State.cbCurDmaPeriod);
1717# endif
1718 Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1719
1720 while (cbLeft > 0)
1721 {
1722 STAM_PROFILE_START(&pThis->StatOut, a);
1723
1724 /*
1725 * Figure out how much we can read & write in this iteration.
1726 */
1727 uint32_t cbChunk = 0;
1728 RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1729
1730 if (cbChunk <= cbLeft)
1731 { /* very likely */ }
1732 else
1733 cbChunk = cbLeft;
1734
1735 /*
1736 * Read the guest data directly into the internal DMA buffer.
1737 */
1738 uint32_t cbRead = 0;
1739 while (cbChunk > 0)
1740 {
1741 /* Grab internal DMA buffer space and read into it. */
1742 void *pvBufDst;
1743 size_t cbBufDst;
1744 RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvBufDst, &cbBufDst);
1745 AssertBreakStmt(cbBufDst, RTCircBufReleaseWriteBlock(pCircBuf, 0));
1746
1747 int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, pvBufDst, cbBufDst);
1748 AssertRC(rc2);
1749
1750# ifdef HDA_DEBUG_SILENCE
1751 fix me if relevant;
1752# endif
1753 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.pFileDMARaw))
1754 { /* likely */ }
1755 else
1756 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst);
1757
1758# ifdef VBOX_WITH_DTRACE
1759 VBOXDD_HDA_STREAM_DMA_OUT((uint32_t)uSD, (uint32_t)cbBufDst, pStreamShared->State.offWrite);
1760# endif
1761 pStreamShared->State.offWrite += cbBufDst;
1762 RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
1763 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufDst);
1764
1765 /* advance */
1766 cbChunk -= (uint32_t)cbBufDst;
1767 cbRead += (uint32_t)cbBufDst;
1768 GCPhys += cbBufDst;
1769 pStreamShared->State.offCurBdle += (uint32_t)cbBufDst;
1770 }
1771
1772 cbLeft -= cbRead;
1773 STAM_PROFILE_STOP(&pThis->StatOut, a);
1774
1775 /*
1776 * Complete the buffer if necessary (common with the input DMA code).
1777 *
1778 * Must update the DMA position before we do this as the buffer IRQ may
1779 * fire on another vCPU and run in parallel to us, although it is very
1780 * unlikely it can make much progress as long as we're sitting on the
1781 * lock, it could still read the DMA position (Linux won't, as it reads
1782 * WALCLK and possibly SDnSTS before the DMA position).
1783 */
1784 hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbRead);
1785 hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaR3StreamDoDmaOutput");
1786 }
1787
1788 Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1789
1790 /*
1791 * Common epilogue.
1792 */
1793 hdaR3StreamDoDmaEpilogue(pDevIns, pStreamShared, pStreamR3);
1794
1795 /*
1796 * Log and leave.
1797 */
1798 Log3Func(("LEAVE - [SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1799 uSD, cbToProduce, pStreamShared->State.cbCurDmaPeriod, pStreamShared->State.offWrite - cbToProduce,
1800 pStreamShared->State.cTransferPendingInterrupts));
1801}
1802
1803#endif /* IN_RING3 */
1804#ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
1805
1806/**
1807 * Do DMA output transfer on LPIB/WALCLK register access.
1808 *
1809 * @returns VINF_SUCCESS or VINF_IOM_R3_MMIO_READ.
1810 * @param pDevIns The device instance.
1811 * @param pThis The shared instance data.
1812 * @param pStreamShared The shared stream data.
1813 * @param tsNow The current time on the timer clock.
1814 * @param cbToTransfer How much to transfer.
1815 */
1816VBOXSTRICTRC hdaStreamDoOnAccessDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1817 uint64_t tsNow, uint32_t cbToTransfer)
1818{
1819 AssertReturn(cbToTransfer > 0, VINF_SUCCESS);
1820 int rc = VINF_SUCCESS;
1821
1822 /*
1823 * Check if we're exceeding the available buffer, go to ring-3 to
1824 * handle that (we would perhaps always take this path when in ring-3).
1825 */
1826 uint32_t cbDma = pStreamShared->State.cbDma;
1827 ASMCompilerBarrier();
1828 if ( cbDma >= sizeof(pStreamShared->State.abDma) /* paranoia */
1829 || cbToTransfer >= sizeof(pStreamShared->State.abDma) /* paranoia */
1830 || cbDma + cbToTransfer > sizeof(pStreamShared->State.abDma))
1831 {
1832# ifndef IN_RING3
1833 STAM_REL_COUNTER_INC(&pThis->StatAccessDmaOutputToR3);
1834 LogFlowFunc(("[SD%RU8] out of DMA buffer space (%#x, need %#x) -> VINF_IOM_R3_MMIO_READ\n",
1835 pStreamShared->u8SD, sizeof(pStreamShared->State.abDma) - pStreamShared->State.cbDma, cbToTransfer));
1836 return VINF_IOM_R3_MMIO_READ;
1837# else /* IN_RING3 */
1838 /*
1839 * Flush the bounce buffer, then do direct transfers to the
1840 * internal DMA buffer (updates LPIB).
1841 */
1842 PHDASTATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
1843 uintptr_t const idxStream = pStreamShared->u8SD;
1844 AssertReturn(idxStream < RT_ELEMENTS(pThisCC->aStreams), VERR_INTERNAL_ERROR_4);
1845 PHDASTREAMR3 const pStreamR3 = &pThisCC->aStreams[idxStream];
1846
1847 hdaR3StreamFlushDmaBounceBufferOutput(pStreamShared, pStreamR3);
1848
1849 uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
1850 if (cbStreamFree >= cbToTransfer)
1851 { /* likely */ }
1852 else
1853 {
1854 PAUDMIXSINK pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
1855 if (pSink)
1856 cbStreamFree = hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbToTransfer, RTTimeNanoTS(),
1857 "hdaStreamDoOnAccessDmaOutput", cbStreamFree);
1858 else
1859 {
1860 LogFunc(("[SD%RU8] No sink and insufficient internal DMA buffer space (%#x) - won't do anything\n",
1861 pStreamShared->u8SD, cbStreamFree));
1862 return VINF_SUCCESS;
1863 }
1864 cbToTransfer = RT_MIN(cbToTransfer, cbStreamFree);
1865 if (cbToTransfer < PDMAudioPropsFrameSize(&pStreamShared->State.Cfg.Props))
1866 {
1867 LogFunc(("[SD%RU8] No internal DMA buffer space (%#x) - won't do anything\n", pStreamShared->u8SD, cbStreamFree));
1868 return VINF_SUCCESS;
1869 }
1870 }
1871 hdaR3StreamDoDmaOutput(pDevIns, pThis, pStreamShared, pStreamR3, cbToTransfer, RTTimeNanoTS());
1872 pStreamShared->State.cbDmaTotal += cbToTransfer;
1873# endif /* IN_RING3 */
1874 }
1875 else
1876 {
1877 /*
1878 * Transfer into the DMA bounce buffer.
1879 */
1880 LogFlowFunc(("[SD%RU8] Transfering %#x bytes to DMA bounce buffer (cbDma=%#x cbDmaTotal=%#x) (%p/%u)\n",
1881 pStreamShared->u8SD, cbToTransfer, cbDma, pStreamShared->State.cbDmaTotal, pStreamShared, pStreamShared->u8SD));
1882 uint32_t cbLeft = cbToTransfer;
1883 do
1884 {
1885 uint32_t cbChunk = 0;
1886 RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1887
1888 bool fMustAdvanceBuffer;
1889 if (cbLeft < cbChunk)
1890 {
1891 fMustAdvanceBuffer = false;
1892 cbChunk = cbLeft;
1893 }
1894 else
1895 fMustAdvanceBuffer = true;
1896
1897 /* Read the guest data directly into the DMA bounce buffer. */
1898 int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &pStreamShared->State.abDma[cbDma], cbChunk);
1899 AssertRC(rc2);
1900
1901 /* We update offWrite and StatBytesRead here even if we haven't moved the data
1902 to the internal DMA buffer yet, because we want the dtrace even to fire here. */
1903# ifdef VBOX_WITH_DTRACE
1904 VBOXDD_HDA_STREAM_DMA_OUT((uint32_t)pStreamShared->u8SD, cbChunk, pStreamShared->State.offWrite);
1905# endif
1906 pStreamShared->State.offWrite += cbChunk;
1907 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbChunk);
1908
1909 /* advance */
1910 pStreamShared->State.offCurBdle += cbChunk;
1911 pStreamShared->State.cbDmaTotal += cbChunk;
1912 cbDma += cbChunk;
1913 pStreamShared->State.cbDma = cbDma;
1914 cbLeft -= cbChunk;
1915 Log6Func(("cbLeft=%#x cbDma=%#x cbDmaTotal=%#x offCurBdle=%#x idxCurBdle=%#x (%p/%u)\n",
1916 cbLeft, cbDma, pStreamShared->State.cbDmaTotal, pStreamShared->State.offCurBdle,
1917 pStreamShared->State.idxCurBdle, pStreamShared, pStreamShared->u8SD));
1918
1919 /* Next buffer. */
1920 bool fAdvanced = hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaStreamDoOnAccessDmaOutput");
1921 AssertMsgStmt(fMustAdvanceBuffer == fAdvanced, ("%d %d\n", fMustAdvanceBuffer, fAdvanced), rc = VERR_INTERNAL_ERROR_3);
1922 } while (cbLeft > 0);
1923
1924 /*
1925 * Advance LPIB and update the last transfer time (for WALCLK).
1926 */
1927 pStreamShared->State.tsTransferLast = tsNow;
1928 hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbToTransfer - cbLeft);
1929 }
1930
1931# ifdef VBOX_STRICT
1932 uint32_t idxSched = pStreamShared->State.idxSchedule;
1933 AssertStmt(idxSched < RT_MIN(RT_ELEMENTS(pStreamShared->State.aSchedule), pStreamShared->State.cSchedule), idxSched = 0);
1934 uint32_t const cbPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
1935 AssertMsg(pStreamShared->State.cbDmaTotal < cbPeriod, ("%#x vs %#x\n", pStreamShared->State.cbDmaTotal, cbPeriod));
1936# endif
1937
1938 STAM_REL_COUNTER_INC(&pThis->StatAccessDmaOutput);
1939 return rc;
1940}
1941
1942
1943/**
1944 * Consider doing DMA output transfer on LPIB/WALCLK register access.
1945 *
1946 * @returns VINF_SUCCESS or VINF_IOM_R3_MMIO_READ.
1947 * @param pDevIns The device instance.
1948 * @param pThis The shared instance data.
1949 * @param pStreamShared The shared stream data.
1950 * @param tsNow The current time on the timer clock. Used to do the
1951 * calculation.
1952 */
1953VBOXSTRICTRC hdaStreamMaybeDoOnAccessDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow)
1954{
1955 Assert(pStreamShared->State.fRunning); /* caller should check this */
1956
1957 /*
1958 * Calculate where the DMA engine should be according to the clock, if we can.
1959 */
1960 uint32_t const cbFrame = PDMAudioPropsFrameSize(&pStreamShared->State.Cfg.Props);
1961 uint32_t const cbPeriod = pStreamShared->State.cbCurDmaPeriod;
1962 if (cbPeriod > cbFrame)
1963 {
1964 AssertMsg(pStreamShared->State.cbDmaTotal < cbPeriod, ("%#x vs %#x\n", pStreamShared->State.cbDmaTotal, cbPeriod));
1965 uint64_t const tsTransferNext = pStreamShared->State.tsTransferNext;
1966 uint32_t cbFuture;
1967 if (tsNow < tsTransferNext)
1968 {
1969 /** @todo ASSUMES nanosecond clock ticks, need to make this
1970 * resolution independent. */
1971 cbFuture = PDMAudioPropsNanoToBytes(&pStreamShared->State.Cfg.Props, tsTransferNext - tsNow);
1972 cbFuture = RT_MIN(cbFuture, cbPeriod - cbFrame);
1973 }
1974 else
1975 {
1976 /* We've hit/overshot the timer deadline. Return to ring-3 if we're
1977 not already there to increase the chance that we'll help expidite
1978 the timer. If we're already in ring-3, do all but the last frame. */
1979# ifndef IN_RING3
1980 LogFunc(("[SD%RU8] DMA period expired: tsNow=%RU64 >= tsTransferNext=%RU64 -> VINF_IOM_R3_MMIO_READ\n",
1981 tsNow, tsTransferNext));
1982 return VINF_IOM_R3_MMIO_READ;
1983# else
1984 cbFuture = cbPeriod - cbFrame;
1985 LogFunc(("[SD%RU8] DMA period expired: tsNow=%RU64 >= tsTransferNext=%RU64 -> cbFuture=%#x (cbPeriod=%#x - cbFrame=%#x)\n",
1986 tsNow, tsTransferNext, cbFuture, cbPeriod, cbFrame));
1987# endif
1988 }
1989 uint32_t const offNow = PDMAudioPropsFloorBytesToFrame(&pStreamShared->State.Cfg.Props, cbPeriod - cbFuture);
1990
1991 /*
1992 * Should we transfer a little? Minimum is 64 bytes (semi-random,
1993 * suspect real hardware might be doing some cache aligned stuff,
1994 * which might soon get complicated if you take unaligned buffers
1995 * into consideration and which cache line size (128 bytes is just
1996 * as likely as 64 or 32 bytes)).
1997 */
1998 uint32_t cbDmaTotal = pStreamShared->State.cbDmaTotal;
1999 if (cbDmaTotal + 64 <= offNow)
2000 {
2001# ifdef LOG_ENABLED
2002 uint32_t const uOldLpib = HDA_STREAM_REG(pThis, CBL, pStreamShared->u8SD);
2003# endif
2004 VBOXSTRICTRC rcStrict = hdaStreamDoOnAccessDmaOutput(pDevIns, pThis, pStreamShared, tsNow, offNow - cbDmaTotal);
2005 LogFlowFunc(("[SD%RU8] LPIB=%#RX32 -> LPIB=%#RX32 offNow=%#x rcStrict=%Rrc\n", pStreamShared->u8SD,
2006 uOldLpib, HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD), offNow, VBOXSTRICTRC_VAL(rcStrict) ));
2007 return rcStrict;
2008 }
2009
2010 /*
2011 * Do nothing.
2012 */
2013 LogFlowFunc(("[SD%RU8] Skipping DMA transfer: cbDmaTotal=%#x offNow=%#x\n", pStreamShared->u8SD, cbDmaTotal, offNow));
2014 }
2015 else
2016 LogFunc(("[SD%RU8] cbPeriod=%#x <= cbFrame=%#x\n", pStreamShared->u8SD, cbPeriod, cbFrame));
2017 return VINF_SUCCESS;
2018}
2019
2020#endif /* VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
2021#ifdef IN_RING3
2022
2023/**
2024 * Output streams: Pushes data to the mixer.
2025 *
2026 * @param pStreamShared HDA stream to update (shared bits).
2027 * @param pStreamR3 HDA stream to update (ring-3 bits).
2028 * @param pSink The mixer sink to push to.
2029 * @param nsNow The current RTTimeNanoTS() value.
2030 */
2031static void hdaR3StreamPushToMixer(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink, uint64_t nsNow)
2032{
2033# ifdef LOG_ENABLED
2034 uint64_t const offReadOld = pStreamShared->State.offRead;
2035# endif
2036 pStreamShared->State.offRead = AudioMixerSinkTransferFromCircBuf(pSink,
2037 pStreamR3->State.pCircBuf,
2038 pStreamShared->State.offRead,
2039 pStreamR3->u8SD,
2040 pStreamR3->Dbg.Runtime.fEnabled
2041 ? pStreamR3->Dbg.Runtime.pFileStream : NULL);
2042
2043 Assert(nsNow >= pStreamShared->State.tsLastReadNs);
2044 Log3Func(("[SD%RU8] nsDeltaLastRead=%RI64 transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
2045 nsNow - pStreamShared->State.tsLastReadNs, pStreamShared->State.offRead - offReadOld, pStreamShared->State.offRead));
2046 RT_NOREF(pStreamShared, nsNow);
2047
2048 /* Update buffer stats. */
2049 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
2050}
2051
2052
2053/**
2054 * Deals with a DMA buffer overrun.
2055 *
2056 * Makes sure we return with @a cbNeeded bytes of free space in pCircBuf.
2057 *
2058 * @returns Number of bytes free in the internal DMA buffer.
2059 * @param pStreamShared The shared data for the HDA stream.
2060 * @param pStreamR3 The ring-3 data for the HDA stream.
2061 * @param pSink The mixer sink (valid).
2062 * @param cbNeeded How much space we need (in bytes).
2063 * @param nsNow Current RTNanoTimeTS() timestamp.
2064 * @param cbStreamFree The current amount of free buffer space.
2065 * @param pszCaller The caller (for logging).
2066 */
2067static uint32_t hdaR3StreamHandleDmaBufferOverrun(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink,
2068 uint32_t cbNeeded, uint64_t nsNow,
2069 const char *pszCaller, uint32_t const cbStreamFree)
2070{
2071 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
2072 Log(("%s: Warning! Stream #%u has insufficient space free: %#x bytes, need %#x. Will try move data out of the buffer...\n",
2073 pszCaller, pStreamShared->u8SD, cbStreamFree, cbNeeded));
2074 RT_NOREF(pszCaller, cbStreamFree);
2075
2076 int rc = AudioMixerSinkTryLock(pSink);
2077 if (RT_SUCCESS(rc))
2078 {
2079 hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, nsNow);
2080 AudioMixerSinkUpdate(pSink, 0, 0);
2081 AudioMixerSinkUnlock(pSink);
2082 }
2083 else
2084 RTThreadYield();
2085
2086 uint32_t const cbRet = hdaR3StreamGetFree(pStreamR3);
2087 Log(("%s: Gained %u bytes.\n", pszCaller, cbRet - cbStreamFree));
2088 if (cbRet >= cbNeeded)
2089 return cbRet;
2090
2091 /*
2092 * Unable to make sufficient space. Drop the whole buffer content.
2093 *
2094 * This is needed in order to keep the device emulation running at a
2095 * constant rate, at the cost of losing valid (but too much) data.
2096 */
2097 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
2098 LogRel2(("HDA: Warning: Hit stream #%RU8 overflow, dropping %u bytes of audio data (%s)\n",
2099 pStreamShared->u8SD, hdaR3StreamGetUsed(pStreamR3), pszCaller));
2100# ifdef HDA_STRICT
2101 AssertMsgFailed(("Hit stream #%RU8 overflow -- timing bug?\n", pStreamShared->u8SD));
2102# endif
2103/**
2104 *
2105 * @todo r=bird: I don't think RTCircBufReset is entirely safe w/o
2106 * owning the AIO lock. See the note in the documentation about it not being
2107 * multi-threading aware (safe). Wish I'd verified this code much earlier.
2108 * Sigh^3!
2109 *
2110 */
2111 RTCircBufReset(pStreamR3->State.pCircBuf);
2112 pStreamShared->State.offWrite = 0;
2113 pStreamShared->State.offRead = 0;
2114 return hdaR3StreamGetFree(pStreamR3);
2115}
2116
2117
2118# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
2119/**
2120 * Flushes the DMA bounce buffer content to the internal DMA buffer.
2121 *
2122 * @param pStreamShared The shared data of the stream to have its DMA bounce
2123 * buffer flushed.
2124 * @param pStreamR3 The ring-3 stream data for same.
2125 */
2126static void hdaR3StreamFlushDmaBounceBufferOutput(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2127{
2128 uint32_t cbDma = pStreamShared->State.cbDma;
2129 LogFlowFunc(("cbDma=%#x\n", cbDma));
2130 if (cbDma)
2131 {
2132 AssertReturnVoid(cbDma <= sizeof(pStreamShared->State.abDma));
2133 PRTCIRCBUF const pCircBuf = pStreamR3->State.pCircBuf;
2134 if (pCircBuf)
2135 {
2136 uint32_t offDma = 0;
2137 while (offDma < cbDma)
2138 {
2139 uint32_t const cbSrcLeft = cbDma - offDma;
2140
2141 /*
2142 * Grab a chunk of the internal DMA buffer.
2143 */
2144 void *pvBufDst = NULL;
2145 size_t cbBufDst = 0;
2146 RTCircBufAcquireWriteBlock(pCircBuf, cbSrcLeft, &pvBufDst, &cbBufDst);
2147 if (cbBufDst > 0)
2148 { /* likely */ }
2149 else
2150 {
2151 /* We've got buffering trouble. */
2152 RTCircBufReleaseWriteBlock(pCircBuf, 0);
2153
2154 PAUDMIXSINK pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
2155 if (pSink)
2156 hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbSrcLeft, RTTimeNanoTS(),
2157 "hdaR3StreamFlushDmaBounceBufferOutput", 0 /*cbStreamFree*/);
2158 else
2159 {
2160 LogFunc(("Stream #%u has no sink. Dropping the rest of the data\n", pStreamR3->u8SD));
2161 break;
2162 }
2163
2164 RTCircBufAcquireWriteBlock(pCircBuf, cbSrcLeft, &pvBufDst, &cbBufDst);
2165 AssertBreakStmt(cbBufDst, RTCircBufReleaseWriteBlock(pCircBuf, 0));
2166 }
2167
2168 /*
2169 * Copy the samples into it and write it to the debug file if open.
2170 *
2171 * We do not fire the dtrace probe here nor update offRead as that was
2172 * done already (not sure that was a good idea?).
2173 */
2174 memcpy(pvBufDst, &pStreamShared->State.abDma[offDma], cbBufDst);
2175
2176 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.pFileDMARaw))
2177 { /* likely */ }
2178 else
2179 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst);
2180
2181 RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
2182
2183 offDma += (uint32_t)cbBufDst;
2184 }
2185 }
2186
2187 /*
2188 * Mark the buffer empty.
2189 */
2190 pStreamShared->State.cbDma = 0;
2191 }
2192}
2193# endif /* VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
2194
2195
2196/**
2197 * The stream's main function when called by the timer.
2198 *
2199 * @note This function also will be called without timer invocation when
2200 * starting (enabling) the stream to minimize startup latency.
2201 *
2202 * @returns Current timer time if the timer is enabled, otherwise zero.
2203 * @param pDevIns The device instance.
2204 * @param pThis The shared HDA device state.
2205 * @param pThisCC The ring-3 HDA device state.
2206 * @param pStreamShared HDA stream to update (shared bits).
2207 * @param pStreamR3 HDA stream to update (ring-3 bits).
2208 */
2209uint64_t hdaR3StreamTimerMain(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
2210 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2211{
2212 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2213 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pStreamShared->hTimer));
2214
2215 /* Do the work: */
2216 hdaR3StreamUpdateDma(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3);
2217
2218 /* Re-arm the timer if the sink is still active: */
2219 if ( pStreamShared->State.fRunning
2220 && pStreamR3->pMixSink
2221 && AudioMixerSinkIsActive(pStreamR3->pMixSink->pMixSink))
2222 {
2223 /* Advance the schduling: */
2224 uint32_t idxSched = pStreamShared->State.idxSchedule;
2225 AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
2226 uint32_t idxLoop = pStreamShared->State.idxScheduleLoop + 1;
2227 if (idxLoop >= pStreamShared->State.aSchedule[idxSched].cLoops)
2228 {
2229 idxSched += 1;
2230 if ( idxSched >= pStreamShared->State.cSchedule
2231 || idxSched >= RT_ELEMENTS(pStreamShared->State.aSchedule) /*paranoia^2*/)
2232 {
2233 idxSched = pStreamShared->State.cSchedulePrologue;
2234 AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
2235 }
2236 pStreamShared->State.idxSchedule = idxSched;
2237 idxLoop = 0;
2238 }
2239 pStreamShared->State.idxScheduleLoop = (uint16_t)idxLoop;
2240
2241 /* Do the actual timer re-arming. */
2242 uint64_t const tsNow = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer); /* (For virtual sync this remains the same for the whole callout IIRC) */
2243 uint64_t const tsTransferNext = tsNow + pStreamShared->State.aSchedule[idxSched].cPeriodTicks;
2244 Log3Func(("[SD%RU8] fSinkActive=true, tsTransferNext=%RU64 (in %RU64)\n",
2245 pStreamShared->u8SD, tsTransferNext, tsTransferNext - tsNow));
2246 int rc = PDMDevHlpTimerSet(pDevIns, pStreamShared->hTimer, tsTransferNext);
2247 AssertRC(rc);
2248
2249 /* Some legacy stuff: */
2250 pStreamShared->State.tsTransferNext = tsTransferNext;
2251 pStreamShared->State.cbCurDmaPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
2252
2253 return tsNow;
2254 }
2255
2256 Log3Func(("[SD%RU8] fSinkActive=false\n", pStreamShared->u8SD));
2257 return 0;
2258}
2259
2260
2261/**
2262 * Updates a HDA stream by doing DMA transfers.
2263 *
2264 * Will do mixer transfers too to try fix an overrun/underrun situation.
2265 *
2266 * The host sink(s) set the overall pace (bird: no it doesn't, the DMA timer
2267 * does - we just hope like heck it matches the speed at which the *backend*
2268 * host audio driver processes samples).
2269 *
2270 * @param pDevIns The device instance.
2271 * @param pThis The shared HDA device state.
2272 * @param pThisCC The ring-3 HDA device state.
2273 * @param pStreamShared HDA stream to update (shared bits).
2274 * @param pStreamR3 HDA stream to update (ring-3 bits).
2275 */
2276static void hdaR3StreamUpdateDma(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
2277 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2278{
2279 RT_NOREF(pThisCC);
2280 int rc2;
2281
2282 /*
2283 * Make sure we're running and got an active mixer sink.
2284 */
2285 if (RT_LIKELY(pStreamShared->State.fRunning))
2286 { /* likely */ }
2287 else
2288 return;
2289
2290 PAUDMIXSINK pSink = NULL;
2291 if (pStreamR3->pMixSink)
2292 pSink = pStreamR3->pMixSink->pMixSink;
2293 if (RT_LIKELY(AudioMixerSinkIsActive(pSink)))
2294 { /* likely */ }
2295 else
2296 return;
2297
2298 /*
2299 * Get scheduling info common to both input and output streams.
2300 */
2301 const uint64_t tsNowNs = RTTimeNanoTS();
2302 uint32_t idxSched = pStreamShared->State.idxSchedule;
2303 AssertStmt(idxSched < RT_MIN(RT_ELEMENTS(pStreamShared->State.aSchedule), pStreamShared->State.cSchedule), idxSched = 0);
2304 uint32_t cbPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
2305
2306 /*
2307 * Output streams (SDO).
2308 */
2309 if (hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_OUT)
2310 {
2311# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
2312 /* Subtract already transferred bytes and flush the DMA bounce buffer. */
2313 uint32_t cbDmaTotal = pStreamShared->State.cbDmaTotal;
2314 if (cbDmaTotal > 0)
2315 {
2316 AssertStmt(cbDmaTotal < cbPeriod, cbDmaTotal = cbPeriod);
2317 cbPeriod -= cbDmaTotal;
2318 pStreamShared->State.cbDmaTotal = 0;
2319 hdaR3StreamFlushDmaBounceBufferOutput(pStreamShared, pStreamR3);
2320 }
2321 else
2322 Assert(pStreamShared->State.cbDma == 0);
2323# endif
2324
2325 /*
2326 * Check how much room we have in our DMA buffer. There should be at
2327 * least one period worth of space there or we're in an overflow situation.
2328 */
2329 uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
2330 if (cbStreamFree >= cbPeriod)
2331 { /* likely */ }
2332 else
2333 cbStreamFree = hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbPeriod, tsNowNs,
2334 "hdaR3StreamUpdateDma", cbStreamFree);
2335
2336 /*
2337 * Do the DMA transfer.
2338 */
2339 uint64_t const offWriteBefore = pStreamShared->State.offWrite;
2340 hdaR3StreamDoDmaOutput(pDevIns, pThis, pStreamShared, pStreamR3, RT_MIN(cbStreamFree, cbPeriod), tsNowNs);
2341
2342 /*
2343 * Should we push data to down thru the mixer to and to the host drivers?
2344 */
2345 bool fKickAioThread = pStreamShared->State.offWrite > offWriteBefore
2346 || hdaR3StreamGetFree(pStreamR3) < pStreamShared->State.cbAvgTransfer * 2;
2347
2348 Log3Func(("msDelta=%RU64 (vs %u) cbStreamFree=%#x (vs %#x) => fKickAioThread=%RTbool\n",
2349 (tsNowNs - pStreamShared->State.tsLastReadNs) / RT_NS_1MS,
2350 pStreamShared->State.Cfg.Device.cMsSchedulingHint, cbStreamFree,
2351 pStreamShared->State.cbAvgTransfer * 2, fKickAioThread));
2352
2353 if (fKickAioThread)
2354 {
2355 /* Notify the async I/O worker thread that there's work to do. */
2356 Log5Func(("Notifying AIO thread\n"));
2357 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
2358 AssertRC(rc2);
2359 /* Update last read timestamp for logging/debugging. */
2360 pStreamShared->State.tsLastReadNs = tsNowNs;
2361 }
2362 }
2363 /*
2364 * Input stream (SDI).
2365 */
2366 else
2367 {
2368 Assert(hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_IN);
2369
2370 /*
2371 * See how much data we've got buffered...
2372 */
2373 bool fWriteSilence = false;
2374 uint32_t cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2375 if (pStreamShared->State.fInputPreBuffered && cbStreamUsed >= cbPeriod)
2376 { /*likely*/ }
2377 /*
2378 * Because it may take a while for the input stream to get going (at
2379 * least with pulseaudio), we feed the guest silence till we've
2380 * pre-buffer a reasonable amount of audio.
2381 */
2382 else if (!pStreamShared->State.fInputPreBuffered)
2383 {
2384 if (cbStreamUsed < pStreamShared->State.cbInputPreBuffer)
2385 {
2386 Log3(("hdaR3StreamUpdateDma: Pre-buffering (got %#x out of %#x bytes)...\n",
2387 cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2388 fWriteSilence = true;
2389 }
2390 else
2391 {
2392 Log3(("hdaR3StreamUpdateDma: Completed pre-buffering (got %#x, needed %#x bytes).\n",
2393 cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2394 pStreamShared->State.fInputPreBuffered = true;
2395 fWriteSilence = true; /* For now, just do the most conservative thing. */
2396 }
2397 cbStreamUsed = cbPeriod;
2398 }
2399 /*
2400 * When we're low on data, we must really try fetch some ourselves
2401 * as buffer underruns must not happen.
2402 */
2403 else
2404 {
2405 /** @todo We're ending up here to frequently with pulse audio at least (just
2406 * watch the stream stats in the statistcs viewer, and way to often we
2407 * have to inject silence bytes. I suspect part of the problem is
2408 * that the HDA device require a much better latency than what the
2409 * pulse audio is configured for by default (10 ms vs 150ms). */
2410 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
2411 Log(("hdaR3StreamUpdateDma: Warning! Stream #%u has insufficient data available: %u bytes, need %u. Will try move pull more data into the buffer...\n",
2412 pStreamShared->u8SD, cbStreamUsed, cbPeriod));
2413 int rc = AudioMixerSinkTryLock(pSink);
2414 if (RT_SUCCESS(rc))
2415 {
2416 AudioMixerSinkUpdate(pSink, cbStreamUsed, cbPeriod);
2417 hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2418 AudioMixerSinkUnlock(pSink);
2419 }
2420 else
2421 RTThreadYield();
2422 Log(("hdaR3StreamUpdateDma: Gained %u bytes.\n", hdaR3StreamGetUsed(pStreamR3) - cbStreamUsed));
2423 cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2424 if (cbStreamUsed < cbPeriod)
2425 {
2426 /* Unable to find sufficient input data by simple prodding.
2427 In order to keep a constant byte stream following thru the DMA
2428 engine into the guest, we will try again and then fall back on
2429 filling the gap with silence. */
2430 uint32_t cbSilence = 0;
2431 do
2432 {
2433 AudioMixerSinkLock(pSink);
2434
2435 cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2436 if (cbStreamUsed < cbPeriod)
2437 {
2438 hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2439 cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2440 while (cbStreamUsed < cbPeriod)
2441 {
2442 void *pvDstBuf;
2443 size_t cbDstBuf;
2444 RTCircBufAcquireWriteBlock(pStreamR3->State.pCircBuf, cbPeriod - cbStreamUsed,
2445 &pvDstBuf, &cbDstBuf);
2446 RT_BZERO(pvDstBuf, cbDstBuf);
2447 RTCircBufReleaseWriteBlock(pStreamR3->State.pCircBuf, cbDstBuf);
2448 cbSilence += (uint32_t)cbDstBuf;
2449 cbStreamUsed += (uint32_t)cbDstBuf;
2450 }
2451 }
2452
2453 AudioMixerSinkUnlock(pSink);
2454 } while (cbStreamUsed < cbPeriod);
2455 if (cbSilence > 0)
2456 {
2457 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
2458 STAM_REL_COUNTER_ADD(&pStreamR3->State.StatDmaFlowErrorBytes, cbSilence);
2459 LogRel2(("HDA: Warning: Stream #%RU8 underrun, added %u bytes of silence (%u us)\n", pStreamShared->u8SD,
2460 cbSilence, PDMAudioPropsBytesToMicro(&pStreamShared->State.Cfg.Props, cbSilence)));
2461 }
2462 }
2463 }
2464
2465 /*
2466 * Do the DMA'ing.
2467 */
2468 if (cbStreamUsed)
2469 hdaR3StreamDoDmaInput(pDevIns, pThis, pStreamShared, pStreamR3,
2470 RT_MIN(cbStreamUsed, cbPeriod), fWriteSilence, tsNowNs);
2471
2472 /*
2473 * We should always kick the AIO thread.
2474 */
2475 /** @todo This isn't entirely ideal. If we get into an underrun situation,
2476 * we ideally want the AIO thread to run right before the DMA timer
2477 * rather than right after it ran. */
2478 Log5Func(("Notifying AIO thread\n"));
2479 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
2480 AssertRC(rc2);
2481 pStreamShared->State.tsLastReadNs = tsNowNs;
2482 }
2483}
2484
2485
2486/**
2487 * @callback_method_impl{FNAUDMIXSINKUPDATE}
2488 *
2489 * For output streams this moves data from the internal DMA buffer (in which
2490 * hdaR3StreamUpdateDma put it), thru the mixer and to the various backend audio
2491 * devices.
2492 *
2493 * For input streams this pulls data from the backend audio device(s), thru the
2494 * mixer and puts it in the internal DMA buffer ready for hdaR3StreamUpdateDma
2495 * to pump into guest memory.
2496 */
2497DECLCALLBACK(void) hdaR3StreamUpdateAsyncIoJob(PPDMDEVINS pDevIns, PAUDMIXSINK pSink, void *pvUser)
2498{
2499 PHDASTATE const pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
2500 PHDASTATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
2501 PHDASTREAMR3 const pStreamR3 = (PHDASTREAMR3)pvUser;
2502 PHDASTREAM const pStreamShared = &pThis->aStreams[pStreamR3 - &pThisCC->aStreams[0]];
2503 Assert(pStreamR3 - &pThisCC->aStreams[0] == pStreamR3->u8SD);
2504 Assert(pStreamShared->u8SD == pStreamR3->u8SD);
2505 RT_NOREF(pSink);
2506
2507 /*
2508 * Make sure we haven't change sink and that it's still active (it
2509 * should be or we wouldn't have been called).
2510 */
2511 AssertReturnVoid(pStreamR3->pMixSink && pSink == pStreamR3->pMixSink->pMixSink);
2512 AssertReturnVoid(AudioMixerSinkIsActive(pSink));
2513
2514 /*
2515 * Output streams (SDO).
2516 */
2517 if (hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_OUT)
2518 hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, RTTimeNanoTS());
2519 /*
2520 * Input stream (SDI).
2521 */
2522 else
2523 {
2524 Assert(hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_IN);
2525 hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2526 }
2527}
2528
2529#endif /* IN_RING3 */
2530
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