DevHdaCodec.h@ 90148

Last change on this file since 90148 was 90148, checked in by vboxsync, 3 years ago
DevHdaCodec: Renamed a couple of variables. bugref:9890
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 39.1 KB

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1	/* $Id: DevHdaCodec.h 90148 2021-07-10 00:40:31Z vboxsync $ */
2	/** @file
3	* Intel HD Audio Controller Emulation - Codec, Sigmatel/IDT STAC9220.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VBOX_INCLUDED_SRC_Audio_DevHdaCodec_h
19	#define VBOX_INCLUDED_SRC_Audio_DevHdaCodec_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#ifndef VBOX_INCLUDED_SRC_Audio_DevHda_h
25	# error "Only include DevHda.h!"
26	#endif
27
28	#include <iprt/list.h>
29	#include "AudioMixer.h"
30
31
32	/** The ICH HDA (Intel) ring-3 codec state. */
33	typedef struct HDACODECR3 *PHDACODECR3;
34
35	/**
36	* Enumeration specifying the codec type to use.
37	*/
38	typedef enum CODECTYPE
39	{
40	/** Invalid, do not use. */
41	CODECTYPE_INVALID = 0,
42	/** SigmaTel 9220 (922x). */
43	CODECTYPE_STAC9220,
44	/** Hack to blow the type up to 32-bit. */
45	CODECTYPE_32BIT_HACK = 0x7fffffff
46	} CODECTYPE;
47
48	/* PRM 5.3.1 */
49	/** Codec address mask. */
50	#define CODEC_CAD_MASK 0xF0000000
51	/** Codec address shift. */
52	#define CODEC_CAD_SHIFT 28
53	#define CODEC_DIRECT_MASK RT_BIT(27)
54	/** Node ID mask. */
55	#define CODEC_NID_MASK 0x07F00000
56	/** Node ID shift. */
57	#define CODEC_NID_SHIFT 20
58	#define CODEC_VERBDATA_MASK 0x000FFFFF
59	#define CODEC_VERB_4BIT_CMD 0x000FFFF0
60	#define CODEC_VERB_4BIT_DATA 0x0000000F
61	#define CODEC_VERB_8BIT_CMD 0x000FFF00
62	#define CODEC_VERB_8BIT_DATA 0x000000FF
63	#define CODEC_VERB_16BIT_CMD 0x000F0000
64	#define CODEC_VERB_16BIT_DATA 0x0000FFFF
65
66	#define CODEC_CAD(cmd) (((cmd) & CODEC_CAD_MASK) >> CODEC_CAD_SHIFT)
67	#define CODEC_DIRECT(cmd) ((cmd) & CODEC_DIRECT_MASK)
68	#define CODEC_NID(cmd) ((((cmd) & CODEC_NID_MASK)) >> CODEC_NID_SHIFT)
69	#define CODEC_VERBDATA(cmd) ((cmd) & CODEC_VERBDATA_MASK)
70	#define CODEC_VERB_CMD(cmd, mask, x) (((cmd) & (mask)) >> (x))
71	#define CODEC_VERB_CMD4(cmd) (CODEC_VERB_CMD((cmd), CODEC_VERB_4BIT_CMD, 4))
72	#define CODEC_VERB_CMD8(cmd) (CODEC_VERB_CMD((cmd), CODEC_VERB_8BIT_CMD, 8))
73	#define CODEC_VERB_CMD16(cmd) (CODEC_VERB_CMD((cmd), CODEC_VERB_16BIT_CMD, 16))
74	#define CODEC_VERB_PAYLOAD4(cmd) ((cmd) & CODEC_VERB_4BIT_DATA)
75	#define CODEC_VERB_PAYLOAD8(cmd) ((cmd) & CODEC_VERB_8BIT_DATA)
76	#define CODEC_VERB_PAYLOAD16(cmd) ((cmd) & CODEC_VERB_16BIT_DATA)
77
78	#define CODEC_VERB_GET_AMP_DIRECTION RT_BIT(15)
79	#define CODEC_VERB_GET_AMP_SIDE RT_BIT(13)
80	#define CODEC_VERB_GET_AMP_INDEX 0x7
81
82	/* HDA spec 7.3.3.7 NoteA */
83	#define CODEC_GET_AMP_DIRECTION(cmd) (((cmd) & CODEC_VERB_GET_AMP_DIRECTION) >> 15)
84	#define CODEC_GET_AMP_SIDE(cmd) (((cmd) & CODEC_VERB_GET_AMP_SIDE) >> 13)
85	#define CODEC_GET_AMP_INDEX(cmd) (CODEC_GET_AMP_DIRECTION(cmd) ? 0 : ((cmd) & CODEC_VERB_GET_AMP_INDEX))
86
87	/* HDA spec 7.3.3.7 NoteC */
88	#define CODEC_VERB_SET_AMP_OUT_DIRECTION RT_BIT(15)
89	#define CODEC_VERB_SET_AMP_IN_DIRECTION RT_BIT(14)
90	#define CODEC_VERB_SET_AMP_LEFT_SIDE RT_BIT(13)
91	#define CODEC_VERB_SET_AMP_RIGHT_SIDE RT_BIT(12)
92	#define CODEC_VERB_SET_AMP_INDEX (0x7 << 8)
93	#define CODEC_VERB_SET_AMP_MUTE RT_BIT(7)
94	/** Note: 7-bit value [6:0]. */
95	#define CODEC_VERB_SET_AMP_GAIN 0x7F
96
97	#define CODEC_SET_AMP_IS_OUT_DIRECTION(cmd) (((cmd) & CODEC_VERB_SET_AMP_OUT_DIRECTION) != 0)
98	#define CODEC_SET_AMP_IS_IN_DIRECTION(cmd) (((cmd) & CODEC_VERB_SET_AMP_IN_DIRECTION) != 0)
99	#define CODEC_SET_AMP_IS_LEFT_SIDE(cmd) (((cmd) & CODEC_VERB_SET_AMP_LEFT_SIDE) != 0)
100	#define CODEC_SET_AMP_IS_RIGHT_SIDE(cmd) (((cmd) & CODEC_VERB_SET_AMP_RIGHT_SIDE) != 0)
101	#define CODEC_SET_AMP_INDEX(cmd) (((cmd) & CODEC_VERB_SET_AMP_INDEX) >> 7)
102	#define CODEC_SET_AMP_MUTE(cmd) ((cmd) & CODEC_VERB_SET_AMP_MUTE)
103	#define CODEC_SET_AMP_GAIN(cmd) ((cmd) & CODEC_VERB_SET_AMP_GAIN)
104
105	/* HDA spec 7.3.3.1 defines layout of configuration registers/verbs (0xF00) */
106	/* VendorID (7.3.4.1) */
107	#define CODEC_MAKE_F00_00(vendorID, deviceID) (((vendorID) << 16) \| (deviceID))
108	#define CODEC_F00_00_VENDORID(f00_00) (((f00_00) >> 16) & 0xFFFF)
109	#define CODEC_F00_00_DEVICEID(f00_00) ((f00_00) & 0xFFFF)
110
111	/** RevisionID (7.3.4.2). */
112	#define CODEC_MAKE_F00_02(majRev, minRev, venFix, venProg, stepFix, stepProg) \
113	( (((majRev) & 0xF) << 20) \
114	\| (((minRev) & 0xF) << 16) \
115	\| (((venFix) & 0xF) << 12) \
116	\| (((venProg) & 0xF) << 8) \
117	\| (((stepFix) & 0xF) << 4) \
118	\| ((stepProg) & 0xF))
119
120	/** Subordinate node count (7.3.4.3). */
121	#define CODEC_MAKE_F00_04(startNodeNumber, totalNodeNumber) ((((startNodeNumber) & 0xFF) << 16)\|((totalNodeNumber) & 0xFF))
122	#define CODEC_F00_04_TO_START_NODE_NUMBER(f00_04) (((f00_04) >> 16) & 0xFF)
123	#define CODEC_F00_04_TO_NODE_COUNT(f00_04) ((f00_04) & 0xFF)
124	/*
125	* Function Group Type (7.3.4.4)
126	* 0 & [0x3-0x7f] are reserved types
127	* [0x80 - 0xff] are vendor defined function groups
128	*/
129	#define CODEC_MAKE_F00_05(UnSol, NodeType) (((UnSol) << 8)\|(NodeType))
130	#define CODEC_F00_05_UNSOL RT_BIT(8)
131	#define CODEC_F00_05_AFG (0x1)
132	#define CODEC_F00_05_MFG (0x2)
133	#define CODEC_F00_05_IS_UNSOL(f00_05) RT_BOOL((f00_05) & RT_BIT(8))
134	#define CODEC_F00_05_GROUP(f00_05) ((f00_05) & 0xff)
135	/* Audio Function Group capabilities (7.3.4.5). */
136	#define CODEC_MAKE_F00_08(BeepGen, InputDelay, OutputDelay) ((((BeepGen) & 0x1) << 16)\| (((InputDelay) & 0xF) << 8) \| ((OutputDelay) & 0xF))
137	#define CODEC_F00_08_BEEP_GEN(f00_08) ((f00_08) & RT_BIT(16)
138
139	/* Converter Stream, Channel (7.3.3.11). */
140	#define CODEC_F00_06_GET_STREAM_ID(cmd) (((cmd) >> 4) & 0x0F)
141	#define CODEC_F00_06_GET_CHANNEL_ID(cmd) (((cmd) & 0x0F))
142
143	/* Widget Capabilities (7.3.4.6). */
144	#define CODEC_MAKE_F00_09(type, delay, chan_ext) \
145	( (((type) & 0xF) << 20) \
146	\| (((delay) & 0xF) << 16) \
147	\| (((chan_ext) & 0xF) << 13))
148	/* note: types 0x8-0xe are reserved */
149	#define CODEC_F00_09_TYPE_AUDIO_OUTPUT (0x0)
150	#define CODEC_F00_09_TYPE_AUDIO_INPUT (0x1)
151	#define CODEC_F00_09_TYPE_AUDIO_MIXER (0x2)
152	#define CODEC_F00_09_TYPE_AUDIO_SELECTOR (0x3)
153	#define CODEC_F00_09_TYPE_PIN_COMPLEX (0x4)
154	#define CODEC_F00_09_TYPE_POWER_WIDGET (0x5)
155	#define CODEC_F00_09_TYPE_VOLUME_KNOB (0x6)
156	#define CODEC_F00_09_TYPE_BEEP_GEN (0x7)
157	#define CODEC_F00_09_TYPE_VENDOR_DEFINED (0xF)
158
159	#define CODEC_F00_09_CAP_CP RT_BIT(12)
160	#define CODEC_F00_09_CAP_L_R_SWAP RT_BIT(11)
161	#define CODEC_F00_09_CAP_POWER_CTRL RT_BIT(10)
162	#define CODEC_F00_09_CAP_DIGITAL RT_BIT(9)
163	#define CODEC_F00_09_CAP_CONNECTION_LIST RT_BIT(8)
164	#define CODEC_F00_09_CAP_UNSOL RT_BIT(7)
165	#define CODEC_F00_09_CAP_PROC_WIDGET RT_BIT(6)
166	#define CODEC_F00_09_CAP_STRIPE RT_BIT(5)
167	#define CODEC_F00_09_CAP_FMT_OVERRIDE RT_BIT(4)
168	#define CODEC_F00_09_CAP_AMP_FMT_OVERRIDE RT_BIT(3)
169	#define CODEC_F00_09_CAP_OUT_AMP_PRESENT RT_BIT(2)
170	#define CODEC_F00_09_CAP_IN_AMP_PRESENT RT_BIT(1)
171	#define CODEC_F00_09_CAP_STEREO RT_BIT(0)
172
173	#define CODEC_F00_09_TYPE(f00_09) (((f00_09) >> 20) & 0xF)
174
175	#define CODEC_F00_09_IS_CAP_CP(f00_09) RT_BOOL((f00_09) & RT_BIT(12))
176	#define CODEC_F00_09_IS_CAP_L_R_SWAP(f00_09) RT_BOOL((f00_09) & RT_BIT(11))
177	#define CODEC_F00_09_IS_CAP_POWER_CTRL(f00_09) RT_BOOL((f00_09) & RT_BIT(10))
178	#define CODEC_F00_09_IS_CAP_DIGITAL(f00_09) RT_BOOL((f00_09) & RT_BIT(9))
179	#define CODEC_F00_09_IS_CAP_CONNECTION_LIST(f00_09) RT_BOOL((f00_09) & RT_BIT(8))
180	#define CODEC_F00_09_IS_CAP_UNSOL(f00_09) RT_BOOL((f00_09) & RT_BIT(7))
181	#define CODEC_F00_09_IS_CAP_PROC_WIDGET(f00_09) RT_BOOL((f00_09) & RT_BIT(6))
182	#define CODEC_F00_09_IS_CAP_STRIPE(f00_09) RT_BOOL((f00_09) & RT_BIT(5))
183	#define CODEC_F00_09_IS_CAP_FMT_OVERRIDE(f00_09) RT_BOOL((f00_09) & RT_BIT(4))
184	#define CODEC_F00_09_IS_CAP_AMP_OVERRIDE(f00_09) RT_BOOL((f00_09) & RT_BIT(3))
185	#define CODEC_F00_09_IS_CAP_OUT_AMP_PRESENT(f00_09) RT_BOOL((f00_09) & RT_BIT(2))
186	#define CODEC_F00_09_IS_CAP_IN_AMP_PRESENT(f00_09) RT_BOOL((f00_09) & RT_BIT(1))
187	#define CODEC_F00_09_IS_CAP_LSB(f00_09) RT_BOOL((f00_09) & RT_BIT(0))
188
189	/* Supported PCM size, rates (7.3.4.7) */
190	#define CODEC_F00_0A_32_BIT RT_BIT(19)
191	#define CODEC_F00_0A_24_BIT RT_BIT(18)
192	#define CODEC_F00_0A_16_BIT RT_BIT(17)
193	#define CODEC_F00_0A_8_BIT RT_BIT(16)
194
195	#define CODEC_F00_0A_48KHZ_MULT_8X RT_BIT(11)
196	#define CODEC_F00_0A_48KHZ_MULT_4X RT_BIT(10)
197	#define CODEC_F00_0A_44_1KHZ_MULT_4X RT_BIT(9)
198	#define CODEC_F00_0A_48KHZ_MULT_2X RT_BIT(8)
199	#define CODEC_F00_0A_44_1KHZ_MULT_2X RT_BIT(7)
200	#define CODEC_F00_0A_48KHZ RT_BIT(6)
201	#define CODEC_F00_0A_44_1KHZ RT_BIT(5)
202	/* 2/3 * 48kHz */
203	#define CODEC_F00_0A_48KHZ_2_3X RT_BIT(4)
204	/* 1/2 * 44.1kHz */
205	#define CODEC_F00_0A_44_1KHZ_1_2X RT_BIT(3)
206	/* 1/3 * 48kHz */
207	#define CODEC_F00_0A_48KHZ_1_3X RT_BIT(2)
208	/* 1/4 * 44.1kHz */
209	#define CODEC_F00_0A_44_1KHZ_1_4X RT_BIT(1)
210	/* 1/6 * 48kHz */
211	#define CODEC_F00_0A_48KHZ_1_6X RT_BIT(0)
212
213	/* Supported streams formats (7.3.4.8) */
214	#define CODEC_F00_0B_AC3 RT_BIT(2)
215	#define CODEC_F00_0B_FLOAT32 RT_BIT(1)
216	#define CODEC_F00_0B_PCM RT_BIT(0)
217
218	/* Pin Capabilities (7.3.4.9)*/
219	#define CODEC_MAKE_F00_0C(vref_ctrl) (((vref_ctrl) & 0xFF) << 8)
220	#define CODEC_F00_0C_CAP_HBR RT_BIT(27)
221	#define CODEC_F00_0C_CAP_DP RT_BIT(24)
222	#define CODEC_F00_0C_CAP_EAPD RT_BIT(16)
223	#define CODEC_F00_0C_CAP_HDMI RT_BIT(7)
224	#define CODEC_F00_0C_CAP_BALANCED_IO RT_BIT(6)
225	#define CODEC_F00_0C_CAP_INPUT RT_BIT(5)
226	#define CODEC_F00_0C_CAP_OUTPUT RT_BIT(4)
227	#define CODEC_F00_0C_CAP_HEADPHONE_AMP RT_BIT(3)
228	#define CODEC_F00_0C_CAP_PRESENCE_DETECT RT_BIT(2)
229	#define CODEC_F00_0C_CAP_TRIGGER_REQUIRED RT_BIT(1)
230	#define CODEC_F00_0C_CAP_IMPENDANCE_SENSE RT_BIT(0)
231
232	#define CODEC_F00_0C_IS_CAP_HBR(f00_0c) ((f00_0c) & RT_BIT(27))
233	#define CODEC_F00_0C_IS_CAP_DP(f00_0c) ((f00_0c) & RT_BIT(24))
234	#define CODEC_F00_0C_IS_CAP_EAPD(f00_0c) ((f00_0c) & RT_BIT(16))
235	#define CODEC_F00_0C_IS_CAP_HDMI(f00_0c) ((f00_0c) & RT_BIT(7))
236	#define CODEC_F00_0C_IS_CAP_BALANCED_IO(f00_0c) ((f00_0c) & RT_BIT(6))
237	#define CODEC_F00_0C_IS_CAP_INPUT(f00_0c) ((f00_0c) & RT_BIT(5))
238	#define CODEC_F00_0C_IS_CAP_OUTPUT(f00_0c) ((f00_0c) & RT_BIT(4))
239	#define CODEC_F00_0C_IS_CAP_HP(f00_0c) ((f00_0c) & RT_BIT(3))
240	#define CODEC_F00_0C_IS_CAP_PRESENCE_DETECT(f00_0c) ((f00_0c) & RT_BIT(2))
241	#define CODEC_F00_0C_IS_CAP_TRIGGER_REQUIRED(f00_0c) ((f00_0c) & RT_BIT(1))
242	#define CODEC_F00_0C_IS_CAP_IMPENDANCE_SENSE(f00_0c) ((f00_0c) & RT_BIT(0))
243
244	/* Input Amplifier capabilities (7.3.4.10). */
245	#define CODEC_MAKE_F00_0D(mute_cap, step_size, num_steps, offset) \
246	( (((mute_cap) & UINT32_C(0x1)) << 31) \
247	\| (((step_size) & UINT32_C(0xFF)) << 16) \
248	\| (((num_steps) & UINT32_C(0xFF)) << 8) \
249	\| ((offset) & UINT32_C(0xFF)))
250
251	#define CODEC_F00_0D_CAP_MUTE RT_BIT(7)
252
253	#define CODEC_F00_0D_IS_CAP_MUTE(f00_0d) ( ( f00_0d) & RT_BIT(31))
254	#define CODEC_F00_0D_STEP_SIZE(f00_0d) ((( f00_0d) & (0x7F << 16)) >> 16)
255	#define CODEC_F00_0D_NUM_STEPS(f00_0d) ((((f00_0d) & (0x7F << 8)) >> 8) + 1)
256	#define CODEC_F00_0D_OFFSET(f00_0d) ( (f00_0d) & 0x7F)
257
258	/** Indicates that the amplifier can be muted. */
259	#define CODEC_AMP_CAP_MUTE 0x1
260	/** The amplifier's maximum number of steps. We want
261	* a ~90dB dynamic range, so 64 steps with 1.25dB each
262	* should do the trick.
263	*
264	* As we want to map our range to [0..128] values we can avoid
265	* multiplication and simply doing a shift later.
266	*
267	* Produces -96dB to +0dB.
268	* "0" indicates a step of 0.25dB, "127" indicates a step of 32dB.
269	*/
270	#define CODEC_AMP_NUM_STEPS 0x7F
271	/** The initial gain offset (and when doing a node reset). */
272	#define CODEC_AMP_OFF_INITIAL 0x7F
273	/** The amplifier's gain step size. */
274	#define CODEC_AMP_STEP_SIZE 0x2
275
276	/* Output Amplifier capabilities (7.3.4.10) */
277	#define CODEC_MAKE_F00_12 CODEC_MAKE_F00_0D
278
279	#define CODEC_F00_12_IS_CAP_MUTE(f00_12) CODEC_F00_0D_IS_CAP_MUTE(f00_12)
280	#define CODEC_F00_12_STEP_SIZE(f00_12) CODEC_F00_0D_STEP_SIZE(f00_12)
281	#define CODEC_F00_12_NUM_STEPS(f00_12) CODEC_F00_0D_NUM_STEPS(f00_12)
282	#define CODEC_F00_12_OFFSET(f00_12) CODEC_F00_0D_OFFSET(f00_12)
283
284	/* Connection list lenght (7.3.4.11). */
285	#define CODEC_MAKE_F00_0E(long_form, length) \
286	( (((long_form) & 0x1) << 7) \
287	\| ((length) & 0x7F))
288	/* Indicates short-form NIDs. */
289	#define CODEC_F00_0E_LIST_NID_SHORT 0
290	/* Indicates long-form NIDs. */
291	#define CODEC_F00_0E_LIST_NID_LONG 1
292	#define CODEC_F00_0E_IS_LONG(f00_0e) RT_BOOL((f00_0e) & RT_BIT(7))
293	#define CODEC_F00_0E_COUNT(f00_0e) ((f00_0e) & 0x7F)
294	/* Supported Power States (7.3.4.12) */
295	#define CODEC_F00_0F_EPSS RT_BIT(31)
296	#define CODEC_F00_0F_CLKSTOP RT_BIT(30)
297	#define CODEC_F00_0F_S3D3 RT_BIT(29)
298	#define CODEC_F00_0F_D3COLD RT_BIT(4)
299	#define CODEC_F00_0F_D3 RT_BIT(3)
300	#define CODEC_F00_0F_D2 RT_BIT(2)
301	#define CODEC_F00_0F_D1 RT_BIT(1)
302	#define CODEC_F00_0F_D0 RT_BIT(0)
303
304	/* Processing capabilities 7.3.4.13 */
305	#define CODEC_MAKE_F00_10(num, benign) ((((num) & 0xFF) << 8) \| ((benign) & 0x1))
306	#define CODEC_F00_10_NUM(f00_10) (((f00_10) & (0xFF << 8)) >> 8)
307	#define CODEC_F00_10_BENING(f00_10) ((f00_10) & 0x1)
308
309	/* GPIO count (7.3.4.14). */
310	#define CODEC_MAKE_F00_11(wake, unsol, numgpi, numgpo, numgpio) \
311	( (((wake) & UINT32_C(0x1)) << 31) \
312	\| (((unsol) & UINT32_C(0x1)) << 30) \
313	\| (((numgpi) & UINT32_C(0xFF)) << 16) \
314	\| (((numgpo) & UINT32_C(0xFF)) << 8) \
315	\| ((numgpio) & UINT32_C(0xFF)))
316
317	/* Processing States (7.3.3.4). */
318	#define CODEC_F03_OFF (0)
319	#define CODEC_F03_ON RT_BIT(0)
320	#define CODEC_F03_BENING RT_BIT(1)
321	/* Power States (7.3.3.10). */
322	#define CODEC_MAKE_F05(reset, stopok, error, act, set) \
323	( (((reset) & 0x1) << 10) \
324	\| (((stopok) & 0x1) << 9) \
325	\| (((error) & 0x1) << 8) \
326	\| (((act) & 0xF) << 4) \
327	\| ((set) & 0xF))
328	#define CODEC_F05_D3COLD (4)
329	#define CODEC_F05_D3 (3)
330	#define CODEC_F05_D2 (2)
331	#define CODEC_F05_D1 (1)
332	#define CODEC_F05_D0 (0)
333
334	#define CODEC_F05_IS_RESET(value) (((value) & RT_BIT(10)) != 0)
335	#define CODEC_F05_IS_STOPOK(value) (((value) & RT_BIT(9)) != 0)
336	#define CODEC_F05_IS_ERROR(value) (((value) & RT_BIT(8)) != 0)
337	#define CODEC_F05_ACT(value) (((value) & 0xF0) >> 4)
338	#define CODEC_F05_SET(value) (((value) & 0xF))
339
340	#define CODEC_F05_GE(p0, p1) ((p0) <= (p1))
341	#define CODEC_F05_LE(p0, p1) ((p0) >= (p1))
342
343	/* Converter Stream, Channel (7.3.3.11). */
344	#define CODEC_MAKE_F06(stream, channel) \
345	( (((stream) & 0xF) << 4) \
346	\| ((channel) & 0xF))
347	#define CODEC_F06_STREAM(value) ((value) & 0xF0)
348	#define CODEC_F06_CHANNEL(value) ((value) & 0xF)
349
350	/* Pin Widged Control (7.3.3.13). */
351	#define CODEC_F07_VREF_HIZ (0)
352	#define CODEC_F07_VREF_50 (0x1)
353	#define CODEC_F07_VREF_GROUND (0x2)
354	#define CODEC_F07_VREF_80 (0x4)
355	#define CODEC_F07_VREF_100 (0x5)
356	#define CODEC_F07_IN_ENABLE RT_BIT(5)
357	#define CODEC_F07_OUT_ENABLE RT_BIT(6)
358	#define CODEC_F07_OUT_H_ENABLE RT_BIT(7)
359
360	/* Volume Knob Control (7.3.3.29). */
361	#define CODEC_F0F_IS_DIRECT RT_BIT(7)
362	#define CODEC_F0F_VOLUME (0x7F)
363
364	/* Unsolicited enabled (7.3.3.14). */
365	#define CODEC_MAKE_F08(enable, tag) ((((enable) & 1) << 7) \| ((tag) & 0x3F))
366
367	/* Converter formats (7.3.3.8) and (3.7.1). */
368	/* This is the same format as SDnFMT. */
369	#define CODEC_MAKE_A HDA_SDFMT_MAKE
370
371	#define CODEC_A_TYPE HDA_SDFMT_TYPE
372	#define CODEC_A_TYPE_PCM HDA_SDFMT_TYPE_PCM
373	#define CODEC_A_TYPE_NON_PCM HDA_SDFMT_TYPE_NON_PCM
374
375	#define CODEC_A_BASE HDA_SDFMT_BASE
376	#define CODEC_A_BASE_48KHZ HDA_SDFMT_BASE_48KHZ
377	#define CODEC_A_BASE_44KHZ HDA_SDFMT_BASE_44KHZ
378
379	/* Pin Sense (7.3.3.15). */
380	#define CODEC_MAKE_F09_ANALOG(fPresent, impedance) \
381	( (((fPresent) & 0x1) << 31) \
382	\| (((impedance) & UINT32_C(0x7FFFFFFF))))
383	#define CODEC_F09_ANALOG_NA UINT32_C(0x7FFFFFFF)
384	#define CODEC_MAKE_F09_DIGITAL(fPresent, fELDValid) \
385	( (((fPresent) & UINT32_C(0x1)) << 31) \
386	\| (((fELDValid) & UINT32_C(0x1)) << 30))
387
388	#define CODEC_MAKE_F0C(lrswap, eapd, btl) ((((lrswap) & 1) << 2) \| (((eapd) & 1) << 1) \| ((btl) & 1))
389	#define CODEC_FOC_IS_LRSWAP(f0c) RT_BOOL((f0c) & RT_BIT(2))
390	#define CODEC_FOC_IS_EAPD(f0c) RT_BOOL((f0c) & RT_BIT(1))
391	#define CODEC_FOC_IS_BTL(f0c) RT_BOOL((f0c) & RT_BIT(0))
392	/* HDA spec 7.3.3.31 defines layout of configuration registers/verbs (0xF1C) */
393	/* Configuration's port connection */
394	#define CODEC_F1C_PORT_MASK (0x3)
395	#define CODEC_F1C_PORT_SHIFT (30)
396
397	#define CODEC_F1C_PORT_COMPLEX (0x0)
398	#define CODEC_F1C_PORT_NO_PHYS (0x1)
399	#define CODEC_F1C_PORT_FIXED (0x2)
400	#define CODEC_F1C_BOTH (0x3)
401
402	/* Configuration default: connection */
403	#define CODEC_F1C_PORT_MASK (0x3)
404	#define CODEC_F1C_PORT_SHIFT (30)
405
406	/* Connected to a jack (1/8", ATAPI, ...). */
407	#define CODEC_F1C_PORT_COMPLEX (0x0)
408	/* No physical connection. */
409	#define CODEC_F1C_PORT_NO_PHYS (0x1)
410	/* Fixed function device (integrated speaker, integrated mic, ...). */
411	#define CODEC_F1C_PORT_FIXED (0x2)
412	/* Both, a jack and an internal device are attached. */
413	#define CODEC_F1C_BOTH (0x3)
414
415	/* Configuration default: Location */
416	#define CODEC_F1C_LOCATION_MASK (0x3F)
417	#define CODEC_F1C_LOCATION_SHIFT (24)
418
419	/* [4:5] bits of location region means chassis attachment */
420	#define CODEC_F1C_LOCATION_PRIMARY_CHASSIS (0)
421	#define CODEC_F1C_LOCATION_INTERNAL RT_BIT(4)
422	#define CODEC_F1C_LOCATION_SECONDRARY_CHASSIS RT_BIT(5)
423	#define CODEC_F1C_LOCATION_OTHER RT_BIT(5)
424
425	/* [0:3] bits of location region means geometry location attachment */
426	#define CODEC_F1C_LOCATION_NA (0)
427	#define CODEC_F1C_LOCATION_REAR (0x1)
428	#define CODEC_F1C_LOCATION_FRONT (0x2)
429	#define CODEC_F1C_LOCATION_LEFT (0x3)
430	#define CODEC_F1C_LOCATION_RIGTH (0x4)
431	#define CODEC_F1C_LOCATION_TOP (0x5)
432	#define CODEC_F1C_LOCATION_BOTTOM (0x6)
433	#define CODEC_F1C_LOCATION_SPECIAL_0 (0x7)
434	#define CODEC_F1C_LOCATION_SPECIAL_1 (0x8)
435	#define CODEC_F1C_LOCATION_SPECIAL_2 (0x9)
436
437	/* Configuration default: Device type */
438	#define CODEC_F1C_DEVICE_MASK (0xF)
439	#define CODEC_F1C_DEVICE_SHIFT (20)
440	#define CODEC_F1C_DEVICE_LINE_OUT (0)
441	#define CODEC_F1C_DEVICE_SPEAKER (0x1)
442	#define CODEC_F1C_DEVICE_HP (0x2)
443	#define CODEC_F1C_DEVICE_CD (0x3)
444	#define CODEC_F1C_DEVICE_SPDIF_OUT (0x4)
445	#define CODEC_F1C_DEVICE_DIGITAL_OTHER_OUT (0x5)
446	#define CODEC_F1C_DEVICE_MODEM_LINE_SIDE (0x6)
447	#define CODEC_F1C_DEVICE_MODEM_HANDSET_SIDE (0x7)
448	#define CODEC_F1C_DEVICE_LINE_IN (0x8)
449	#define CODEC_F1C_DEVICE_AUX (0x9)
450	#define CODEC_F1C_DEVICE_MIC (0xA)
451	#define CODEC_F1C_DEVICE_PHONE (0xB)
452	#define CODEC_F1C_DEVICE_SPDIF_IN (0xC)
453	#define CODEC_F1C_DEVICE_RESERVED (0xE)
454	#define CODEC_F1C_DEVICE_OTHER (0xF)
455
456	/* Configuration default: Connection type */
457	#define CODEC_F1C_CONNECTION_TYPE_MASK (0xF)
458	#define CODEC_F1C_CONNECTION_TYPE_SHIFT (16)
459
460	#define CODEC_F1C_CONNECTION_TYPE_UNKNOWN (0)
461	#define CODEC_F1C_CONNECTION_TYPE_1_8INCHES (0x1)
462	#define CODEC_F1C_CONNECTION_TYPE_1_4INCHES (0x2)
463	#define CODEC_F1C_CONNECTION_TYPE_ATAPI (0x3)
464	#define CODEC_F1C_CONNECTION_TYPE_RCA (0x4)
465	#define CODEC_F1C_CONNECTION_TYPE_OPTICAL (0x5)
466	#define CODEC_F1C_CONNECTION_TYPE_OTHER_DIGITAL (0x6)
467	#define CODEC_F1C_CONNECTION_TYPE_ANALOG (0x7)
468	#define CODEC_F1C_CONNECTION_TYPE_DIN (0x8)
469	#define CODEC_F1C_CONNECTION_TYPE_XLR (0x9)
470	#define CODEC_F1C_CONNECTION_TYPE_RJ_11 (0xA)
471	#define CODEC_F1C_CONNECTION_TYPE_COMBO (0xB)
472	#define CODEC_F1C_CONNECTION_TYPE_OTHER (0xF)
473
474	/* Configuration's color */
475	#define CODEC_F1C_COLOR_MASK (0xF)
476	#define CODEC_F1C_COLOR_SHIFT (12)
477	#define CODEC_F1C_COLOR_UNKNOWN (0)
478	#define CODEC_F1C_COLOR_BLACK (0x1)
479	#define CODEC_F1C_COLOR_GREY (0x2)
480	#define CODEC_F1C_COLOR_BLUE (0x3)
481	#define CODEC_F1C_COLOR_GREEN (0x4)
482	#define CODEC_F1C_COLOR_RED (0x5)
483	#define CODEC_F1C_COLOR_ORANGE (0x6)
484	#define CODEC_F1C_COLOR_YELLOW (0x7)
485	#define CODEC_F1C_COLOR_PURPLE (0x8)
486	#define CODEC_F1C_COLOR_PINK (0x9)
487	#define CODEC_F1C_COLOR_RESERVED_0 (0xA)
488	#define CODEC_F1C_COLOR_RESERVED_1 (0xB)
489	#define CODEC_F1C_COLOR_RESERVED_2 (0xC)
490	#define CODEC_F1C_COLOR_RESERVED_3 (0xD)
491	#define CODEC_F1C_COLOR_WHITE (0xE)
492	#define CODEC_F1C_COLOR_OTHER (0xF)
493
494	/* Configuration's misc */
495	#define CODEC_F1C_MISC_MASK (0xF)
496	#define CODEC_F1C_MISC_SHIFT (8)
497	#define CODEC_F1C_MISC_NONE 0
498	#define CODEC_F1C_MISC_JACK_NO_PRESENCE_DETECT RT_BIT(0)
499	#define CODEC_F1C_MISC_RESERVED_0 RT_BIT(1)
500	#define CODEC_F1C_MISC_RESERVED_1 RT_BIT(2)
501	#define CODEC_F1C_MISC_RESERVED_2 RT_BIT(3)
502
503	/* Configuration default: Association */
504	#define CODEC_F1C_ASSOCIATION_MASK (0xF)
505	#define CODEC_F1C_ASSOCIATION_SHIFT (4)
506
507	/** Reserved; don't use. */
508	#define CODEC_F1C_ASSOCIATION_INVALID 0x0
509	#define CODEC_F1C_ASSOCIATION_GROUP_0 0x1
510	#define CODEC_F1C_ASSOCIATION_GROUP_1 0x2
511	#define CODEC_F1C_ASSOCIATION_GROUP_2 0x3
512	#define CODEC_F1C_ASSOCIATION_GROUP_3 0x4
513	#define CODEC_F1C_ASSOCIATION_GROUP_4 0x5
514	#define CODEC_F1C_ASSOCIATION_GROUP_5 0x6
515	#define CODEC_F1C_ASSOCIATION_GROUP_6 0x7
516	#define CODEC_F1C_ASSOCIATION_GROUP_7 0x8
517	/* Note: Windows OSes will treat group 15 (0xF) as single PIN devices.
518	* The sequence number associated with that group then will be ignored. */
519	#define CODEC_F1C_ASSOCIATION_GROUP_15 0xF
520
521	/* Configuration default: Association Sequence. */
522	#define CODEC_F1C_SEQ_MASK (0xF)
523	#define CODEC_F1C_SEQ_SHIFT (0)
524
525	/* Implementation identification (7.3.3.30). */
526	#define CODEC_MAKE_F20(bmid, bsku, aid) \
527	( (((bmid) & 0xFFFF) << 16) \
528	\| (((bsku) & 0xFF) << 8) \
529	\| (((aid) & 0xFF)) \
530	)
531
532	/* Macro definition helping in filling the configuration registers. */
533	#define CODEC_MAKE_F1C(port_connectivity, location, device, connection_type, color, misc, association, sequence) \
534	( (((port_connectivity) & 0xF) << CODEC_F1C_PORT_SHIFT) \
535	\| (((location) & 0xF) << CODEC_F1C_LOCATION_SHIFT) \
536	\| (((device) & 0xF) << CODEC_F1C_DEVICE_SHIFT) \
537	\| (((connection_type) & 0xF) << CODEC_F1C_CONNECTION_TYPE_SHIFT) \
538	\| (((color) & 0xF) << CODEC_F1C_COLOR_SHIFT) \
539	\| (((misc) & 0xF) << CODEC_F1C_MISC_SHIFT) \
540	\| (((association) & 0xF) << CODEC_F1C_ASSOCIATION_SHIFT) \
541	\| (((sequence) & 0xF)))
542
543
544	/*********************************************************************************************************************************
545	* Structures and Typedefs *
546	*********************************************************************************************************************************/
547	/** The F00 parameter length (in dwords). */
548	#define CODECNODE_F00_PARAM_LENGTH 20
549	/** The F02 parameter length (in dwords). */
550	#define CODECNODE_F02_PARAM_LENGTH 16
551
552	/* PRM 5.3.1 */
553	#define CODEC_RESPONSE_UNSOLICITED RT_BIT_64(34)
554
555	#define AMPLIFIER_SIZE 60
556
557	typedef uint32_t AMPLIFIER[AMPLIFIER_SIZE];
558
559	/**
560	* Common (or core) codec node structure.
561	*/
562	typedef struct CODECCOMMONNODE
563	{
564	/** The node's ID. */
565	uint8_t uID;
566	/** The node's name. */
567	/** The SDn ID this node is assigned to.
568	* 0 means not assigned, 1 is SDn0. */
569	uint8_t uSD;
570	/** The SDn's channel to use.
571	* Only valid if a valid SDn ID is set. */
572	uint8_t uChannel;
573	/* PRM 5.3.6 */
574	uint32_t au32F00_param[CODECNODE_F00_PARAM_LENGTH];
575	uint32_t au32F02_param[CODECNODE_F02_PARAM_LENGTH];
576	} CODECCOMMONNODE;
577	AssertCompile(CODECNODE_F00_PARAM_LENGTH == 20); /* saved state */
578	AssertCompile(CODECNODE_F02_PARAM_LENGTH == 16); /* saved state */
579	AssertCompileSize(CODECCOMMONNODE, (1 + 20 + 16) * sizeof(uint32_t));
580	typedef CODECCOMMONNODE *PCODECCOMMONNODE;
581
582	/**
583	* Compile time assertion on the expected node size.
584	*/
585	#define AssertNodeSize(a_Node, a_cParams) \
586	AssertCompile((a_cParams) <= (60 + 6)); /* the max size - saved state */ \
587	AssertCompile( sizeof(a_Node) - sizeof(CODECCOMMONNODE) \
588	== ((a_cParams) * sizeof(uint32_t)) )
589
590	typedef struct ROOTCODECNODE
591	{
592	CODECCOMMONNODE node;
593	} ROOTCODECNODE, *PROOTCODECNODE;
594	AssertNodeSize(ROOTCODECNODE, 0);
595
596	typedef struct DACNODE
597	{
598	CODECCOMMONNODE node;
599	uint32_t u32F0d_param;
600	uint32_t u32F04_param;
601	uint32_t u32F05_param;
602	uint32_t u32F06_param;
603	uint32_t u32F0c_param;
604
605	uint32_t u32A_param;
606	AMPLIFIER B_params;
607
608	} DACNODE, *PDACNODE;
609	AssertNodeSize(DACNODE, 6 + 60);
610
611	typedef struct ADCNODE
612	{
613	CODECCOMMONNODE node;
614	uint32_t u32F01_param;
615	uint32_t u32F03_param;
616	uint32_t u32F05_param;
617	uint32_t u32F06_param;
618	uint32_t u32F09_param;
619
620	uint32_t u32A_param;
621	AMPLIFIER B_params;
622	} ADCNODE, *PADCNODE;
623	AssertNodeSize(DACNODE, 6 + 60);
624
625	typedef struct SPDIFOUTNODE
626	{
627	CODECCOMMONNODE node;
628	uint32_t u32F05_param;
629	uint32_t u32F06_param;
630	uint32_t u32F09_param;
631	uint32_t u32F0d_param;
632
633	uint32_t u32A_param;
634	AMPLIFIER B_params;
635	} SPDIFOUTNODE, *PSPDIFOUTNODE;
636	AssertNodeSize(SPDIFOUTNODE, 5 + 60);
637
638	typedef struct SPDIFINNODE
639	{
640	CODECCOMMONNODE node;
641	uint32_t u32F05_param;
642	uint32_t u32F06_param;
643	uint32_t u32F09_param;
644	uint32_t u32F0d_param;
645
646	uint32_t u32A_param;
647	AMPLIFIER B_params;
648	} SPDIFINNODE, *PSPDIFINNODE;
649	AssertNodeSize(SPDIFINNODE, 5 + 60);
650
651	typedef struct AFGCODECNODE
652	{
653	CODECCOMMONNODE node;
654	uint32_t u32F05_param;
655	uint32_t u32F08_param;
656	uint32_t u32F17_param;
657	uint32_t u32F20_param;
658	} AFGCODECNODE, *PAFGCODECNODE;
659	AssertNodeSize(AFGCODECNODE, 4);
660
661	typedef struct PORTNODE
662	{
663	CODECCOMMONNODE node;
664	uint32_t u32F01_param;
665	uint32_t u32F07_param;
666	uint32_t u32F08_param;
667	uint32_t u32F09_param;
668	uint32_t u32F1c_param;
669	AMPLIFIER B_params;
670	} PORTNODE, *PPORTNODE;
671	AssertNodeSize(PORTNODE, 5 + 60);
672
673	typedef struct DIGOUTNODE
674	{
675	CODECCOMMONNODE node;
676	uint32_t u32F01_param;
677	uint32_t u32F05_param;
678	uint32_t u32F07_param;
679	uint32_t u32F08_param;
680	uint32_t u32F09_param;
681	uint32_t u32F1c_param;
682	} DIGOUTNODE, *PDIGOUTNODE;
683	AssertNodeSize(DIGOUTNODE, 6);
684
685	typedef struct DIGINNODE
686	{
687	CODECCOMMONNODE node;
688	uint32_t u32F05_param;
689	uint32_t u32F07_param;
690	uint32_t u32F08_param;
691	uint32_t u32F09_param;
692	uint32_t u32F0c_param;
693	uint32_t u32F1c_param;
694	uint32_t u32F1e_param;
695	} DIGINNODE, *PDIGINNODE;
696	AssertNodeSize(DIGINNODE, 7);
697
698	typedef struct ADCMUXNODE
699	{
700	CODECCOMMONNODE node;
701	uint32_t u32F01_param;
702
703	uint32_t u32A_param;
704	AMPLIFIER B_params;
705	} ADCMUXNODE, *PADCMUXNODE;
706	AssertNodeSize(ADCMUXNODE, 2 + 60);
707
708	typedef struct PCBEEPNODE
709	{
710	CODECCOMMONNODE node;
711	uint32_t u32F07_param;
712	uint32_t u32F0a_param;
713
714	uint32_t u32A_param;
715	AMPLIFIER B_params;
716	uint32_t u32F1c_param;
717	} PCBEEPNODE, *PPCBEEPNODE;
718	AssertNodeSize(PCBEEPNODE, 3 + 60 + 1);
719
720	typedef struct CDNODE
721	{
722	CODECCOMMONNODE node;
723	uint32_t u32F07_param;
724	uint32_t u32F1c_param;
725	} CDNODE, *PCDNODE;
726	AssertNodeSize(CDNODE, 2);
727
728	typedef struct VOLUMEKNOBNODE
729	{
730	CODECCOMMONNODE node;
731	uint32_t u32F08_param;
732	uint32_t u32F0f_param;
733	} VOLUMEKNOBNODE, *PVOLUMEKNOBNODE;
734	AssertNodeSize(VOLUMEKNOBNODE, 2);
735
736	typedef struct ADCVOLNODE
737	{
738	CODECCOMMONNODE node;
739	uint32_t u32F0c_param;
740	uint32_t u32F01_param;
741	uint32_t u32A_params;
742	AMPLIFIER B_params;
743	} ADCVOLNODE, *PADCVOLNODE;
744	AssertNodeSize(ADCVOLNODE, 3 + 60);
745
746	typedef struct RESNODE
747	{
748	CODECCOMMONNODE node;
749	uint32_t u32F05_param;
750	uint32_t u32F06_param;
751	uint32_t u32F07_param;
752	uint32_t u32F1c_param;
753
754	uint32_t u32A_param;
755	} RESNODE, *PRESNODE;
756	AssertNodeSize(RESNODE, 5);
757
758	/**
759	* Used for the saved state.
760	*/
761	typedef struct CODECSAVEDSTATENODE
762	{
763	CODECCOMMONNODE Core;
764	uint32_t au32Params[60 + 6];
765	} CODECSAVEDSTATENODE;
766	AssertNodeSize(CODECSAVEDSTATENODE, 60 + 6);
767
768	typedef union CODECNODE
769	{
770	CODECCOMMONNODE node;
771	ROOTCODECNODE root;
772	AFGCODECNODE afg;
773	DACNODE dac;
774	ADCNODE adc;
775	SPDIFOUTNODE spdifout;
776	SPDIFINNODE spdifin;
777	PORTNODE port;
778	DIGOUTNODE digout;
779	DIGINNODE digin;
780	ADCMUXNODE adcmux;
781	PCBEEPNODE pcbeep;
782	CDNODE cdnode;
783	VOLUMEKNOBNODE volumeKnob;
784	ADCVOLNODE adcvol;
785	RESNODE reserved;
786	CODECSAVEDSTATENODE SavedState;
787	} CODECNODE, *PCODECNODE;
788	AssertNodeSize(CODECNODE, 60 + 6);
789
790	#define CODEC_NODES_MAX 32
791
792	/** @name CODEC_NODE_CLS_XXX - node classification flags.
793	* @{ */
794	#define CODEC_NODE_CLS_Port UINT16_C(0x0001)
795	#define CODEC_NODE_CLS_Dac UINT16_C(0x0002)
796	#define CODEC_NODE_CLS_AdcVol UINT16_C(0x0004)
797	#define CODEC_NODE_CLS_Adc UINT16_C(0x0008)
798	#define CODEC_NODE_CLS_AdcMux UINT16_C(0x0010)
799	#define CODEC_NODE_CLS_Pcbeep UINT16_C(0x0020)
800	#define CODEC_NODE_CLS_SpdifIn UINT16_C(0x0040)
801	#define CODEC_NODE_CLS_SpdifOut UINT16_C(0x0080)
802	#define CODEC_NODE_CLS_DigInPin UINT16_C(0x0100)
803	#define CODEC_NODE_CLS_DigOutPin UINT16_C(0x0200)
804	#define CODEC_NODE_CLS_Cd UINT16_C(0x0400)
805	#define CODEC_NODE_CLS_VolKnob UINT16_C(0x0800)
806	#define CODEC_NODE_CLS_Reserved UINT16_C(0x1000)
807	/** @} */
808
809	/**
810	* Codec configuration.
811	*
812	* This will not change after construction and is therefore kept in a const
813	* member of HDACODECR3 to encourage compiler optimizations and avoid accidental
814	* modification.
815	*/
816	typedef struct HDACODECCFG
817	{
818	/** Codec implementation type. */
819	CODECTYPE enmType;
820	/** Codec ID. */
821	uint16_t id;
822	uint16_t idVendor;
823	uint16_t idDevice;
824	uint8_t bBSKU;
825	uint8_t idAssembly;
826
827	uint8_t cTotalNodes;
828	uint8_t idxAdcVolsLineIn;
829	uint8_t idxDacLineOut;
830
831	/** Align the lists below so they don't cross cache lines (assumes
832	* CODEC_NODES_MAX is 32). */
833	uint8_t const abPadding1[CODEC_NODES_MAX - 15];
834
835	/** @name Node classifications.
836	* @note These are copies of the g_abStac9220Xxxx arrays in DevHdaCodec.cpp.
837	* They are used both for classifying a node and for processing a class of
838	* nodes.
839	* @{ */
840	uint8_t abPorts[CODEC_NODES_MAX];
841	uint8_t abDacs[CODEC_NODES_MAX];
842	uint8_t abAdcVols[CODEC_NODES_MAX];
843	uint8_t abAdcs[CODEC_NODES_MAX];
844	uint8_t abAdcMuxs[CODEC_NODES_MAX];
845	uint8_t abPcbeeps[CODEC_NODES_MAX];
846	uint8_t abSpdifIns[CODEC_NODES_MAX];
847	uint8_t abSpdifOuts[CODEC_NODES_MAX];
848	uint8_t abDigInPins[CODEC_NODES_MAX];
849	uint8_t abDigOutPins[CODEC_NODES_MAX];
850	uint8_t abCds[CODEC_NODES_MAX];
851	uint8_t abVolKnobs[CODEC_NODES_MAX];
852	uint8_t abReserveds[CODEC_NODES_MAX];
853	/** @} */
854
855	/** The CODEC_NODE_CLS_XXX flags for each node. */
856	uint16_t afNodeClassifications[CODEC_NODES_MAX];
857	} HDACODECCFG;
858	AssertCompileMemberAlignment(HDACODECCFG, abPorts, CODEC_NODES_MAX);
859	AssertCompileSizeAlignment(HDACODECCFG, 64);
860
861
862	/**
863	* HDA codec state (ring-3, no shared state).
864	*/
865	typedef struct HDACODECR3
866	{
867	/** The codec configuration - initialized at construction time. */
868	HDACODECCFG const Cfg;
869	/** The state data for each node. */
870	CODECNODE aNodes[CODEC_NODES_MAX];
871	/** Statistics. */
872	STAMCOUNTER StatLookupsR3;
873	/** Size alignment padding. */
874	uint64_t const au64Padding1[7];
875	} HDACODECR3;
876	AssertCompile(RT_IS_POWER_OF_TWO(CODEC_NODES_MAX));
877	AssertCompileMemberAlignment(HDACODECR3, aNodes, 64);
878	AssertCompileSizeAlignment(HDACODECR3, 64);
879
880
881	/** @name HDA Codec API used by the device emulation.
882	* @{ */
883	int hdaR3CodecConstruct(PPDMDEVINS pDevIns, PHDACODECR3 pThis, uint16_t uLUN, PCFGMNODE pCfg);
884	void hdaR3CodecPowerOff(PHDACODECR3 pThis);
885	int hdaR3CodecLoadState(PPDMDEVINS pDevIns, PHDACODECR3 pThis, PSSMHANDLE pSSM, uint32_t uVersion);
886	int hdaR3CodecAddStream(PHDACODECR3 pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOSTREAMCFG pCfg);
887	int hdaR3CodecRemoveStream(PHDACODECR3 pThis, PDMAUDIOMIXERCTL enmMixerCtl, bool fImmediate);
888
889	int hdaCodecSaveState(PPDMDEVINS pDevIns, PHDACODECR3 pThis, PSSMHANDLE pSSM);
890	void hdaCodecDestruct(PHDACODECR3 pThis);
891	void hdaCodecReset(PHDACODECR3 pThis);
892
893	DECLHIDDEN(int) hdaR3CodecLookup(PHDACODECR3 pThis, uint32_t uCmd, uint64_t *puResp);
894	DECLHIDDEN(void) hdaR3CodecDbgListNodes(PHDACODECR3 pThis, PCDBGFINFOHLP pHlp, const char *pszArgs);
895	DECLHIDDEN(void) hdaR3CodecDbgSelector(PHDACODECR3 pThis, PCDBGFINFOHLP pHlp, const char *pszArgs);
896	/** @} */
897
898	#endif /* !VBOX_INCLUDED_SRC_Audio_DevHdaCodec_h */
899

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source: vbox/trunk/src/VBox/Devices/Audio/DevHdaCodec.h@ 90148

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