VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevCodec.h@ 39417

Last change on this file since 39417 was 39368, checked in by vboxsync, 13 years ago

VBOX_FULL_VERSION_MAKE: fixed copy & past bug messing up the build part.
SSM: Return VERR_SSM_LOADED_TOO_LITTLE if there is data in the buffer, not only if there are more records before the unit end.
HDA: Fixed the saved state loading stuff again. Canged the saved state to mark up arrays with lengths and serialize using structure puts.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 23.9 KB
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1/* $Id: DevCodec.h 39368 2011-11-18 15:19:35Z vboxsync $ */
2/** @file
3 * DevCodec - VBox ICH Intel HD Audio Codec.
4 */
5
6/*
7 * Copyright (C) 2006-2008 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17#ifndef DEV_CODEC_H
18#define DEV_CODEC_H
19struct CODECState;
20struct INTELHDLinkState;
21
22typedef DECLCALLBACK(int) FNCODECVERBPROCESSOR(struct CODECState *pState, uint32_t cmd, uint64_t *pResp);
23typedef FNCODECVERBPROCESSOR *PFNCODECVERBPROCESSOR;
24typedef FNCODECVERBPROCESSOR **PPFNCODECVERBPROCESSOR;
25
26/* RPM 5.3.1 */
27#define CODEC_RESPONSE_UNSOLICITED RT_BIT_64(34)
28
29#define CODEC_CAD_MASK 0xF0000000
30#define CODEC_CAD_SHIFT 28
31#define CODEC_DIRECT_MASK RT_BIT(27)
32#define CODEC_NID_MASK 0x07F00000
33#define CODEC_NID_SHIFT 20
34#define CODEC_VERBDATA_MASK 0x000FFFFF
35#define CODEC_VERB_4BIT_CMD 0x000FFFF0
36#define CODEC_VERB_4BIT_DATA 0x0000000F
37#define CODEC_VERB_8BIT_CMD 0x000FFF00
38#define CODEC_VERB_8BIT_DATA 0x000000FF
39#define CODEC_VERB_16BIT_CMD 0x000F0000
40#define CODEC_VERB_16BIT_DATA 0x0000FFFF
41
42#define CODEC_CAD(cmd) ((cmd) & CODEC_CAD_MASK)
43#define CODEC_DIRECT(cmd) ((cmd) & CODEC_DIRECT_MASK)
44#define CODEC_NID(cmd) ((((cmd) & CODEC_NID_MASK)) >> CODEC_NID_SHIFT)
45#define CODEC_VERBDATA(cmd) ((cmd) & CODEC_VERBDATA_MASK)
46#define CODEC_VERB_CMD(cmd, mask, x) (((cmd) & (mask)) >> (x))
47#define CODEC_VERB_CMD4(cmd) (CODEC_VERB_CMD((cmd), CODEC_VERB_4BIT_CMD, 4))
48#define CODEC_VERB_CMD8(cmd) (CODEC_VERB_CMD((cmd), CODEC_VERB_8BIT_CMD, 8))
49#define CODEC_VERB_CMD16(cmd) (CODEC_VERB_CMD((cmd), CODEC_VERB_16BIT_CMD, 16))
50#define CODEC_VERB_PAYLOAD4(cmd) ((cmd) & CODEC_VERB_4BIT_DATA)
51#define CODEC_VERB_PAYLOAD8(cmd) ((cmd) & CODEC_VERB_8BIT_DATA)
52#define CODEC_VERB_PAYLOAD16(cmd) ((cmd) & CODEC_VERB_16BIT_DATA)
53
54#define CODEC_VERB_GET_AMP_DIRECTION RT_BIT(15)
55#define CODEC_VERB_GET_AMP_SIDE RT_BIT(13)
56#define CODEC_VERB_GET_AMP_INDEX 0x7
57
58/* HDA spec 7.3.3.7 NoteA */
59#define CODEC_GET_AMP_DIRECTION(cmd) (((cmd) & CODEC_VERB_GET_AMP_DIRECTION) >> 15)
60#define CODEC_GET_AMP_SIDE(cmd) (((cmd) & CODEC_VERB_GET_AMP_SIDE) >> 13)
61#define CODEC_GET_AMP_INDEX(cmd) (CODEC_GET_AMP_DIRECTION(cmd) ? 0 : ((cmd) & CODEC_VERB_GET_AMP_INDEX))
62
63/* HDA spec 7.3.3.7 NoteC */
64#define CODEC_VERB_SET_AMP_OUT_DIRECTION RT_BIT(15)
65#define CODEC_VERB_SET_AMP_IN_DIRECTION RT_BIT(14)
66#define CODEC_VERB_SET_AMP_LEFT_SIDE RT_BIT(13)
67#define CODEC_VERB_SET_AMP_RIGHT_SIDE RT_BIT(12)
68#define CODEC_VERB_SET_AMP_INDEX (0x7 << 8)
69
70#define CODEC_SET_AMP_IS_OUT_DIRECTION(cmd) (((cmd) & CODEC_VERB_SET_AMP_OUT_DIRECTION) != 0)
71#define CODEC_SET_AMP_IS_IN_DIRECTION(cmd) (((cmd) & CODEC_VERB_SET_AMP_IN_DIRECTION) != 0)
72#define CODEC_SET_AMP_IS_LEFT_SIDE(cmd) (((cmd) & CODEC_VERB_SET_AMP_LEFT_SIDE) != 0)
73#define CODEC_SET_AMP_IS_RIGHT_SIDE(cmd) (((cmd) & CODEC_VERB_SET_AMP_RIGHT_SIDE) != 0)
74#define CODEC_SET_AMP_INDEX(cmd) (((cmd) & CODEC_VERB_SET_AMP_INDEX) >> 7)
75
76/* HDA spec 7.3.3.1 defines layout of configuration registers/verbs (0xF00) */
77/* VendorID (7.3.4.1) */
78#define CODEC_MAKE_F00_00(vendorID, deviceID) (((vendorID) << 16) | (deviceID))
79#define CODEC_F00_00_VENDORID(f00_00) (((f00_00) >> 16) & 0xFFFF)
80#define CODEC_F00_00_DEVICEID(f00_00) ((f00_00) & 0xFFFF)
81/* RevisionID (7.3.4.2)*/
82#define CODEC_MAKE_F00_02(MajRev, MinRev, RevisionID, SteppingID) (((MajRev) << 20)|((MinRev) << 16)|((RevisionID) << 8)|(SteppingID))
83/* Subordinate node count (7.3.4.3)*/
84#define CODEC_MAKE_F00_04(startNodeNumber, totalNodeNumber) ((((startNodeNumber) & 0xFF) << 16)|((totalNodeNumber) & 0xFF))
85#define CODEC_F00_04_TO_START_NODE_NUMBER(f00_04) (((f00_04) >> 16) & 0xFF)
86#define CODEC_F00_04_TO_NODE_COUNT(f00_04) ((f00_04) & 0xFF)
87/*
88 * Function Group Type (7.3.4.4)
89 * 0 & [0x3-0x7f] are reserved types
90 * [0x80 - 0xff] are vendor defined function groups
91 */
92#define CODEC_MAKE_F00_05(UnSol, NodeType) (((UnSol) << 8)|(NodeType))
93#define CODEC_F00_05_UNSOL RT_BIT(8)
94#define CODEC_F00_05_AFG (0x1)
95#define CODEC_F00_05_MFG (0x2)
96#define CODEC_F00_05_IS_UNSOL(f00_05) RT_BOOL((f00_05) & RT_BIT(8))
97#define CODEC_F00_05_GROUP(f00_05) ((f00_05) & 0xff)
98/* Audio Function Group capabilities (7.3.4.5) */
99#define CODEC_MAKE_F00_08(BeepGen, InputDelay, OutputDelay) ((((BeepGen) & 0x1) << 16)| (((InputDelay) & 0xF) << 8) | ((OutputDelay) & 0xF))
100#define CODEC_F00_08_BEEP_GEN(f00_08) ((f00_08) & RT_BIT(16)
101
102/* Widget Capabilities (7.3.4.6) */
103#define CODEC_MAKE_F00_09(type, delay, chanel_count) \
104 ( (((type) & 0xF) << 20) \
105 | (((delay) & 0xF) << 16) \
106 | (((chanel_count) & 0xF) << 13))
107/* note: types 0x8-0xe are reserved */
108#define CODEC_F00_09_TYPE_AUDIO_OUTPUT (0x0)
109#define CODEC_F00_09_TYPE_AUDIO_INPUT (0x1)
110#define CODEC_F00_09_TYPE_AUDIO_MIXER (0x2)
111#define CODEC_F00_09_TYPE_AUDIO_SELECTOR (0x3)
112#define CODEC_F00_09_TYPE_PIN_COMPLEX (0x4)
113#define CODEC_F00_09_TYPE_POWER_WIDGET (0x5)
114#define CODEC_F00_09_TYPE_VOLUME_KNOB (0x6)
115#define CODEC_F00_09_TYPE_BEEP_GEN (0x7)
116#define CODEC_F00_09_TYPE_VENDOR_DEFINED (0xF)
117
118#define CODEC_F00_09_CAP_CP RT_BIT(12)
119#define CODEC_F00_09_CAP_L_R_SWAP RT_BIT(11)
120#define CODEC_F00_09_CAP_POWER_CTRL RT_BIT(10)
121#define CODEC_F00_09_CAP_DIGITAL RT_BIT(9)
122#define CODEC_F00_09_CAP_CONNECTION_LIST RT_BIT(8)
123#define CODEC_F00_09_CAP_UNSOL RT_BIT(7)
124#define CODEC_F00_09_CAP_PROC_WIDGET RT_BIT(6)
125#define CODEC_F00_09_CAP_STRIPE RT_BIT(5)
126#define CODEC_F00_09_CAP_FMT_OVERRIDE RT_BIT(4)
127#define CODEC_F00_09_CAP_AMP_FMT_OVERRIDE RT_BIT(3)
128#define CODEC_F00_09_CAP_OUT_AMP_PRESENT RT_BIT(2)
129#define CODEC_F00_09_CAP_IN_AMP_PRESENT RT_BIT(1)
130#define CODEC_F00_09_CAP_LSB RT_BIT(0)
131
132#define CODEC_F00_09_TYPE(f00_09) (((f00_09) >> 20) & 0xF)
133
134#define CODEC_F00_09_IS_CAP_CP(f00_09) RT_BOOL((f00_09) & RT_BIT(12))
135#define CODEC_F00_09_IS_CAP_L_R_SWAP(f00_09) RT_BOOL((f00_09) & RT_BIT(11))
136#define CODEC_F00_09_IS_CAP_POWER_CTRL(f00_09) RT_BOOL((f00_09) & RT_BIT(10))
137#define CODEC_F00_09_IS_CAP_DIGITAL(f00_09) RT_BOOL((f00_09) & RT_BIT(9))
138#define CODEC_F00_09_IS_CAP_CONNECTION_LIST(f00_09) RT_BOOL((f00_09) & RT_BIT(8))
139#define CODEC_F00_09_IS_CAP_UNSOL(f00_09) RT_BOOL((f00_09) & RT_BIT(7))
140#define CODEC_F00_09_IS_CAP_PROC_WIDGET(f00_09) RT_BOOL((f00_09) & RT_BIT(6))
141#define CODEC_F00_09_IS_CAP_STRIPE(f00_09) RT_BOOL((f00_09) & RT_BIT(5))
142#define CODEC_F00_09_IS_CAP_FMT_OVERRIDE(f00_09) RT_BOOL((f00_09) & RT_BIT(4))
143#define CODEC_F00_09_IS_CAP_AMP_OVERRIDE(f00_09) RT_BOOL((f00_09) & RT_BIT(3))
144#define CODEC_F00_09_IS_CAP_OUT_AMP_PRESENT(f00_09) RT_BOOL((f00_09) & RT_BIT(2))
145#define CODEC_F00_09_IS_CAP_IN_AMP_PRESENT(f00_09) RT_BOOL((f00_09) & RT_BIT(1))
146#define CODEC_F00_09_IS_CAP_LSB(f00_09) RT_BOOL((f00_09) & RT_BIT(0))
147
148/* Supported PCM size, rates (7.3.4.7) */
149#define CODEC_F00_0A_32_BIT RT_BIT(19)
150#define CODEC_F00_0A_24_BIT RT_BIT(18)
151#define CODEC_F00_0A_16_BIT RT_BIT(17)
152#define CODEC_F00_0A_8_BIT RT_BIT(16)
153
154#define CODEC_F00_0A_48KHZ_MULT_8X RT_BIT(11)
155#define CODEC_F00_0A_48KHZ_MULT_4X RT_BIT(10)
156#define CODEC_F00_0A_44_1KHZ_MULT_4X RT_BIT(9)
157#define CODEC_F00_0A_48KHZ_MULT_2X RT_BIT(8)
158#define CODEC_F00_0A_44_1KHZ_MULT_2X RT_BIT(7)
159#define CODEC_F00_0A_48KHZ RT_BIT(6)
160#define CODEC_F00_0A_44_1KHZ RT_BIT(5)
161/* 2/3 * 48kHz */
162#define CODEC_F00_0A_48KHZ_2_3X RT_BIT(4)
163/* 1/2 * 44.1kHz */
164#define CODEC_F00_0A_44_1KHZ_1_2X RT_BIT(3)
165/* 1/3 * 48kHz */
166#define CODEC_F00_0A_48KHZ_1_3X RT_BIT(2)
167/* 1/4 * 44.1kHz */
168#define CODEC_F00_0A_44_1KHZ_1_4X RT_BIT(1)
169/* 1/6 * 48kHz */
170#define CODEC_F00_0A_48KHZ_1_6X RT_BIT(0)
171
172/* Supported streams formats (7.3.4.8) */
173#define CODEC_F00_0B_AC3 RT_BIT(2)
174#define CODEC_F00_0B_FLOAT32 RT_BIT(1)
175#define CODEC_F00_0B_PCM RT_BIT(0)
176
177/* Pin Capabilities (7.3.4.9)*/
178#define CODEC_MAKE_F00_0C(vref_ctrl) (((vref_ctrl) & 0xFF) << 8)
179#define CODEC_F00_0C_CAP_HBR RT_BIT(27)
180#define CODEC_F00_0C_CAP_DP RT_BIT(24)
181#define CODEC_F00_0C_CAP_EAPD RT_BIT(16)
182#define CODEC_F00_0C_CAP_HDMI RT_BIT(7)
183#define CODEC_F00_0C_CAP_BALANCED_IO RT_BIT(6)
184#define CODEC_F00_0C_CAP_INPUT RT_BIT(5)
185#define CODEC_F00_0C_CAP_OUTPUT RT_BIT(4)
186#define CODEC_F00_0C_CAP_HP RT_BIT(3)
187#define CODEC_F00_0C_CAP_PRESENSE_DETECT RT_BIT(2)
188#define CODEC_F00_0C_CAP_TRIGGER_REQUIRED RT_BIT(1)
189#define CODEC_F00_0C_CAP_IMPENDANCE_SENSE RT_BIT(0)
190
191#define CODEC_F00_0C_IS_CAP_HBR(f00_0c) ((f00_0c) & RT_BIT(27))
192#define CODEC_F00_0C_IS_CAP_DP(f00_0c) ((f00_0c) & RT_BIT(24))
193#define CODEC_F00_0C_IS_CAP_EAPD(f00_0c) ((f00_0c) & RT_BIT(16))
194#define CODEC_F00_0C_IS_CAP_HDMI(f00_0c) ((f00_0c) & RT_BIT(7))
195#define CODEC_F00_0C_IS_CAP_BALANCED_IO(f00_0c) ((f00_0c) & RT_BIT(6))
196#define CODEC_F00_0C_IS_CAP_INPUT(f00_0c) ((f00_0c) & RT_BIT(5))
197#define CODEC_F00_0C_IS_CAP_OUTPUT(f00_0c) ((f00_0c) & RT_BIT(4))
198#define CODEC_F00_0C_IS_CAP_HP(f00_0c) ((f00_0c) & RT_BIT(3))
199#define CODEC_F00_0C_IS_CAP_PRESENSE_DETECT(f00_0c) ((f00_0c) & RT_BIT(2))
200#define CODEC_F00_0C_IS_CAP_TRIGGER_REQUIRED(f00_0c) ((f00_0c) & RT_BIT(1))
201#define CODEC_F00_0C_IS_CAP_IMPENDANCE_SENSE(f00_0c) ((f00_0c) & RT_BIT(0))
202
203/* Input Amplifier capabilities (7.3.4.10) */
204#define CODEC_MAKE_F00_0D(mute_cap, step_size, num_steps, offset) \
205 ( (((mute_cap) & 0x1) << 31) \
206 | (((step_size) & 0xFF) << 16) \
207 | (((num_steps) & 0xFF) << 8) \
208 | ((offset) & 0xFF))
209
210/* Output Amplifier capabilities (7.3.4.10) */
211#define CODEC_MAKE_F00_12 CODEC_MAKE_F00_0D
212
213/* Connection list lenght (7.3.4.11) */
214#define CODEC_MAKE_F00_0E(long_form, length) \
215 ( (((long_form) & 0x1) << 7) \
216 | ((length) & 0x7F))
217#define CODEC_F00_0E_IS_LONG(f00_0e) RT_BOOL((f00_0e) & RT_BIT(7))
218#define CODEC_F00_0E_COUNT(f00_0e) ((f00_0e) & 0x7F)
219/* Supported Power States (7.3.4.12) */
220#define CODEC_F00_0F_EPSS RT_BIT(31)
221#define CODEC_F00_0F_CLKSTOP RT_BIT(30)
222#define CODEC_F00_0F_S3D3 RT_BIT(29)
223#define CODEC_F00_0F_D3COLD RT_BIT(4)
224#define CODEC_F00_0F_D3 RT_BIT(3)
225#define CODEC_F00_0F_D2 RT_BIT(2)
226#define CODEC_F00_0F_D1 RT_BIT(1)
227#define CODEC_F00_0F_D0 RT_BIT(0)
228
229/* Processing capabilities 7.3.4.13 */
230#define CODEC_MAKE_F00_10(num, benign) ((((num) & 0xFF) << 8) | ((benign) & 0x1))
231#define CODEC_F00_10_NUM(f00_10) (((f00_10) & (0xFF << 8)) >> 8)
232#define CODEC_F00_10_BENING(f00_10) ((f00_10) & 0x1)
233
234/* CP/IO Count (7.3.4.14) */
235#define CODEC_MAKE_F00_11(wake, unsol, numgpi, numgpo, numgpio) \
236 ( (((wake) & 0x1) << 31) \
237 | (((unsol) & 0x1) << 30) \
238 | (((numgpi) & 0xFF) << 16) \
239 | (((numgpo) & 0xFF) << 8) \
240 | ((numgpio) & 0xFF))
241
242/* Processing States (7.3.3.4) */
243#define CODEC_F03_OFF (0)
244#define CODEC_F03_ON RT_BIT(0)
245#define CODEC_F03_BENING RT_BIT(1)
246/* Power States (7.3.3.10) */
247#define CODEC_MAKE_F05(reset, stopok, error, act, set) \
248 ( (((reset) & 0x1) << 10) \
249 | (((stopok) & 0x1) << 9) \
250 | (((error) & 0x1) << 8) \
251 | (((act) & 0x7) << 4) \
252 | ((set) & 0x7))
253#define CODEC_F05_D3COLD (4)
254#define CODEC_F05_D3 (3)
255#define CODEC_F05_D2 (2)
256#define CODEC_F05_D1 (1)
257#define CODEC_F05_D0 (0)
258
259#define CODEC_F05_IS_RESET(value) (((value) & RT_BIT(10)) != 0)
260#define CODEC_F05_IS_STOPOK(value) (((value) & RT_BIT(9)) != 0)
261#define CODEC_F05_IS_ERROR(value) (((value) & RT_BIT(8)) != 0)
262#define CODEC_F05_ACT(value) (((value) & 0x7) >> 4)
263#define CODEC_F05_SET(value) (((value) & 0x7))
264
265#define CODEC_F05_GE(p0, p1) ((p0) <= (p1))
266#define CODEC_F05_LE(p0, p1) ((p0) >= (p1))
267
268/* Pin Widged Control (7.3.3.13) */
269#define CODEC_F07_VREF_HIZ (0)
270#define CODEC_F07_VREF_50 (0x1)
271#define CODEC_F07_VREF_GROUND (0x2)
272#define CODEC_F07_VREF_80 (0x4)
273#define CODEC_F07_VREF_100 (0x5)
274#define CODEC_F07_IN_ENABLE RT_BIT(5)
275#define CODEC_F07_OUT_ENABLE RT_BIT(6)
276#define CODEC_F07_OUT_H_ENABLE RT_BIT(7)
277
278/* Unsolicited enabled (7.3.3.14) */
279#define CODEC_MAKE_F08(enable, tag) ((((enable) & 1) << 7) | ((tag) & 0x3F))
280
281/* Converter formats (7.3.3.8) and (3.7.1) */
282#define CODEC_MAKE_A(fNonPCM, f44_1BaseRate, mult, div, bits, chan) \
283 ( (((fNonPCM) & 0x1) << 15) \
284 | (((f44_1BaseRate) & 0x1) << 14) \
285 | (((mult) & 0x7) << 11) \
286 | (((div) & 0x7) << 8) \
287 | (((bits) & 0x7) << 4) \
288 | ((chan) & 0xF))
289
290#define CODEC_A_MULT_1X (0)
291#define CODEC_A_MULT_2X (1)
292#define CODEC_A_MULT_3X (2)
293#define CODEC_A_MULT_4X (3)
294
295#define CODEC_A_DIV_1X (0)
296#define CODEC_A_DIV_2X (1)
297#define CODEC_A_DIV_3X (2)
298#define CODEC_A_DIV_4X (3)
299#define CODEC_A_DIV_5X (4)
300#define CODEC_A_DIV_6X (5)
301#define CODEC_A_DIV_7X (6)
302#define CODEC_A_DIV_8X (7)
303
304#define CODEC_A_8_BIT (0)
305#define CODEC_A_16_BIT (1)
306#define CODEC_A_20_BIT (2)
307#define CODEC_A_24_BIT (3)
308#define CODEC_A_32_BIT (4)
309
310/* Pin Sense (7.3.3.15) */
311#define CODEC_MAKE_F09_ANALOG(fPresent, impedance) \
312( (((fPresent) & 0x1) << 31) \
313 | (((impedance) & 0x7FFFFFFF)))
314#define CODEC_F09_ANALOG_NA 0x7FFFFFFF
315#define CODEC_MAKE_F09_DIGITAL(fPresent, fELDValid) \
316( (((fPresent) & 0x1) << 31) \
317 | (((fELDValid) & 0x1) << 30))
318
319#define CODEC_MAKE_F0C(lrswap, eapd, btl) ((((lrswap) & 1) << 2) | (((eapd) & 1) << 1) | ((btl) & 1))
320#define CODEC_FOC_IS_LRSWAP(f0c) RT_BOOL((f0c) & RT_BIT(2))
321#define CODEC_FOC_IS_EAPD(f0c) RT_BOOL((f0c) & RT_BIT(1))
322#define CODEC_FOC_IS_BTL(f0c) RT_BOOL((f0c) & RT_BIT(0))
323/* HDA spec 7.3.3.31 defines layout of configuration registers/verbs (0xF1C) */
324/* Configuration's port connection */
325#define CODEC_F1C_PORT_MASK (0x3)
326#define CODEC_F1C_PORT_SHIFT (30)
327
328#define CODEC_F1C_PORT_COMPLEX (0x0)
329#define CODEC_F1C_PORT_NO_PHYS (0x1)
330#define CODEC_F1C_PORT_FIXED (0x2)
331#define CODEC_F1C_BOTH (0x3)
332
333/* Configuration's location */
334#define CODEC_F1C_LOCATION_MASK (0x3F)
335#define CODEC_F1C_LOCATION_SHIFT (24)
336/* [4:5] bits of location region means chassis attachment */
337#define CODEC_F1C_LOCATION_PRIMARY_CHASSIS (0)
338#define CODEC_F1C_LOCATION_INTERNAL RT_BIT(4)
339#define CODEC_F1C_LOCATION_SECONDRARY_CHASSIS RT_BIT(5)
340#define CODEC_F1C_LOCATION_OTHER (RT_BIT(5))
341
342/* [0:3] bits of location region means geometry location attachment */
343#define CODEC_F1C_LOCATION_NA (0)
344#define CODEC_F1C_LOCATION_REAR (0x1)
345#define CODEC_F1C_LOCATION_FRONT (0x2)
346#define CODEC_F1C_LOCATION_LEFT (0x3)
347#define CODEC_F1C_LOCATION_RIGTH (0x4)
348#define CODEC_F1C_LOCATION_TOP (0x5)
349#define CODEC_F1C_LOCATION_BOTTOM (0x6)
350#define CODEC_F1C_LOCATION_SPECIAL_0 (0x7)
351#define CODEC_F1C_LOCATION_SPECIAL_1 (0x8)
352#define CODEC_F1C_LOCATION_SPECIAL_2 (0x9)
353
354/* Configuration's devices */
355#define CODEC_F1C_DEVICE_MASK (0xF)
356#define CODEC_F1C_DEVICE_SHIFT (20)
357#define CODEC_F1C_DEVICE_LINE_OUT (0)
358#define CODEC_F1C_DEVICE_SPEAKER (0x1)
359#define CODEC_F1C_DEVICE_HP (0x2)
360#define CODEC_F1C_DEVICE_CD (0x3)
361#define CODEC_F1C_DEVICE_SPDIF_OUT (0x4)
362#define CODEC_F1C_DEVICE_DIGITAL_OTHER_OUT (0x5)
363#define CODEC_F1C_DEVICE_MODEM_LINE_SIDE (0x6)
364#define CODEC_F1C_DEVICE_MODEM_HANDSET_SIDE (0x7)
365#define CODEC_F1C_DEVICE_LINE_IN (0x8)
366#define CODEC_F1C_DEVICE_AUX (0x9)
367#define CODEC_F1C_DEVICE_MIC (0xA)
368#define CODEC_F1C_DEVICE_PHONE (0xB)
369#define CODEC_F1C_DEVICE_SPDIF_IN (0xC)
370#define CODEC_F1C_DEVICE_RESERVED (0xE)
371#define CODEC_F1C_DEVICE_OTHER (0xF)
372
373/* Configuration's Connection type */
374#define CODEC_F1C_CONNECTION_TYPE_MASK (0xF)
375#define CODEC_F1C_CONNECTION_TYPE_SHIFT (16)
376
377#define CODEC_F1C_CONNECTION_TYPE_UNKNOWN (0)
378#define CODEC_F1C_CONNECTION_TYPE_1_8INCHES (0x1)
379#define CODEC_F1C_CONNECTION_TYPE_1_4INCHES (0x2)
380#define CODEC_F1C_CONNECTION_TYPE_ATAPI (0x3)
381#define CODEC_F1C_CONNECTION_TYPE_RCA (0x4)
382#define CODEC_F1C_CONNECTION_TYPE_OPTICAL (0x5)
383#define CODEC_F1C_CONNECTION_TYPE_OTHER_DIGITAL (0x6)
384#define CODEC_F1C_CONNECTION_TYPE_ANALOG (0x7)
385#define CODEC_F1C_CONNECTION_TYPE_DIN (0x8)
386#define CODEC_F1C_CONNECTION_TYPE_XLR (0x9)
387#define CODEC_F1C_CONNECTION_TYPE_RJ_11 (0xA)
388#define CODEC_F1C_CONNECTION_TYPE_COMBO (0xB)
389#define CODEC_F1C_CONNECTION_TYPE_OTHER (0xF)
390
391/* Configuration's color */
392#define CODEC_F1C_COLOR_MASK (0xF)
393#define CODEC_F1C_COLOR_SHIFT (12)
394#define CODEC_F1C_COLOR_UNKNOWN (0)
395#define CODEC_F1C_COLOR_BLACK (0x1)
396#define CODEC_F1C_COLOR_GREY (0x2)
397#define CODEC_F1C_COLOR_BLUE (0x3)
398#define CODEC_F1C_COLOR_GREEN (0x4)
399#define CODEC_F1C_COLOR_RED (0x5)
400#define CODEC_F1C_COLOR_ORANGE (0x6)
401#define CODEC_F1C_COLOR_YELLOW (0x7)
402#define CODEC_F1C_COLOR_PURPLE (0x8)
403#define CODEC_F1C_COLOR_PINK (0x9)
404#define CODEC_F1C_COLOR_RESERVED_0 (0xA)
405#define CODEC_F1C_COLOR_RESERVED_1 (0xB)
406#define CODEC_F1C_COLOR_RESERVED_2 (0xC)
407#define CODEC_F1C_COLOR_RESERVED_3 (0xD)
408#define CODEC_F1C_COLOR_WHITE (0xE)
409#define CODEC_F1C_COLOR_OTHER (0xF)
410
411/* Configuration's misc */
412#define CODEC_F1C_MISC_MASK (0xF)
413#define CODEC_F1C_MISC_SHIFT (8)
414#define CODEC_F1C_MISC_JACK_DETECT (0)
415#define CODEC_F1C_MISC_RESERVED_0 (1)
416#define CODEC_F1C_MISC_RESERVED_1 (2)
417#define CODEC_F1C_MISC_RESERVED_2 (3)
418
419/* Configuration's association */
420#define CODEC_F1C_ASSOCIATION_MASK (0xF)
421#define CODEC_F1C_ASSOCIATION_SHIFT (4)
422/* Connection's sequence */
423#define CODEC_F1C_SEQ_MASK (0xF)
424#define CODEC_F1C_SEQ_SHIFT (0)
425
426/* Implementation identification (7.3.3.30) */
427#define CODEC_MAKE_F20(bmid, bsku, aid) \
428 ( (((bmid) & 0xFFFF) << 16) \
429 | (((bsku) & 0xFF) << 8) \
430 | (((aid) & 0xFF)) \
431 )
432
433/* macro definition helping in filling the configuration registers. */
434#define CODEC_MAKE_F1C(port_connectivity, location, device, connection_type, color, misc, association, sequence) \
435 ( ((port_connectivity) << CODEC_F1C_PORT_SHIFT) \
436 | ((location) << CODEC_F1C_LOCATION_SHIFT) \
437 | ((device) << CODEC_F1C_DEVICE_SHIFT) \
438 | ((connection_type) << CODEC_F1C_CONNECTION_TYPE_SHIFT) \
439 | ((color) << CODEC_F1C_COLOR_SHIFT) \
440 | ((misc) << CODEC_F1C_MISC_SHIFT) \
441 | ((association) << CODEC_F1C_ASSOCIATION_SHIFT) \
442 | ((sequence)))
443
444
445#ifndef VBOX_WITH_HDA_CODEC_EMU
446typedef struct CODECVERB
447{
448 uint32_t verb;
449 /* operation bitness mask */
450 uint32_t mask;
451 PFNCODECVERBPROCESSOR pfn;
452} CODECVERB;
453#endif
454
455#ifndef VBOX_WITH_HDA_CODEC_EMU
456# define TYPE union
457#else
458# define TYPE struct
459typedef struct CODECEMU CODECEMU;
460typedef CODECEMU *PCODECEMU;
461#endif
462TYPE CODECNODE;
463typedef TYPE CODECNODE CODECNODE;
464typedef TYPE CODECNODE *PCODECNODE;
465
466
467typedef enum
468{
469 PI_INDEX = 0, /* PCM in */
470 PO_INDEX, /* PCM out */
471 MC_INDEX, /* Mic in */
472 LAST_INDEX
473} ENMSOUNDSOURCE;
474
475
476typedef struct CODECState
477{
478 uint16_t id;
479 uint16_t u16VendorId;
480 uint16_t u16DeviceId;
481 uint8_t u8BSKU;
482 uint8_t u8AssemblyId;
483#ifndef VBOX_WITH_HDA_CODEC_EMU
484 CODECVERB *pVerbs;
485 int cVerbs;
486#else
487 PCODECEMU pCodecBackend;
488#endif
489 PCODECNODE pNodes;
490 QEMUSoundCard card;
491 /** PCM in */
492 SWVoiceIn *SwVoiceIn;
493 /** PCM out */
494 SWVoiceOut *SwVoiceOut;
495 void *pHDAState;
496 bool fInReset;
497#ifndef VBOX_WITH_HDA_CODEC_EMU
498 const uint8_t cTotalNodes;
499 const uint8_t *au8Ports;
500 const uint8_t *au8Dacs;
501 const uint8_t *au8AdcVols;
502 const uint8_t *au8Adcs;
503 const uint8_t *au8AdcMuxs;
504 const uint8_t *au8Pcbeeps;
505 const uint8_t *au8SpdifIns;
506 const uint8_t *au8SpdifOuts;
507 const uint8_t *au8DigInPins;
508 const uint8_t *au8DigOutPins;
509 const uint8_t *au8Cds;
510 const uint8_t *au8VolKnobs;
511 const uint8_t *au8Reserveds;
512 const uint8_t u8AdcVolsLineIn;
513 const uint8_t u8DacLineOut;
514#endif
515 DECLR3CALLBACKMEMBER(int, pfnProcess, (struct CODECState *));
516 DECLR3CALLBACKMEMBER(void, pfnTransfer, (struct CODECState *pState, ENMSOUNDSOURCE, int avail));
517 /* These callbacks are set by Codec implementation */
518 DECLR3CALLBACKMEMBER(int, pfnLookup, (struct CODECState *pState, uint32_t verb, PPFNCODECVERBPROCESSOR));
519 DECLR3CALLBACKMEMBER(int, pfnReset, (struct CODECState *pState));
520 DECLR3CALLBACKMEMBER(int, pfnCodecNodeReset, (struct CODECState *pState, uint8_t, PCODECNODE));
521 /* These callbacks are set by codec implementation to answer debugger requests */
522 DECLR3CALLBACKMEMBER(void, pfnCodecDbgListNodes, (CODECState *pState, PCDBGFINFOHLP pHlp, const char *pszArgs));
523 DECLR3CALLBACKMEMBER(void, pfnCodecDbgSelector, (CODECState *pState, PCDBGFINFOHLP pHlp, const char *pszArgs));
524} CODECState, *PCODECState;
525
526int codecConstruct(PPDMDEVINS pDevIns, CODECState *pCodecState, PCFGMNODE pCfgHandle);
527int codecDestruct(CODECState *pCodecState);
528int codecSaveState(CODECState *pCodecState, PSSMHANDLE pSSMHandle);
529int codecLoadState(CODECState *pCodecState, PSSMHANDLE pSSMHandle, uint32_t uVersion);
530int codecOpenVoice(CODECState *pCodecState, ENMSOUNDSOURCE enmSoundSource, audsettings_t *pAudioSettings);
531
532#define HDA_SSM_VERSION 4
533#define HDA_SSM_VERSION_1 1
534#define HDA_SSM_VERSION_2 2
535#define HDA_SSM_VERSION_3 3
536
537# ifdef VBOX_WITH_HDA_CODEC_EMU
538/* */
539struct CODECEMU
540{
541 DECLR3CALLBACKMEMBER(int, pfnCodecEmuConstruct, (PCODECState pState));
542 DECLR3CALLBACKMEMBER(int, pfnCodecEmuDestruct, (PCODECState pState));
543 DECLR3CALLBACKMEMBER(int, pfnCodecEmuReset, (PCODECState pState, bool fInit));
544};
545# endif
546#endif
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