VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevCodec.h@ 35487

Last change on this file since 35487 was 35487, checked in by vboxsync, 14 years ago

Devices/Audio: fixed fallback to nul host audio driver. Added the fallback to HDA audio device. (xTracker 5404).

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File size: 20.2 KB
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1/* $Id: DevCodec.h 35487 2011-01-11 13:45:20Z vboxsync $ */
2/** @file
3 * DevCodec - VBox ICH Intel HD Audio Codec.
4 */
5
6/*
7 * Copyright (C) 2006-2008 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17#ifndef DEV_CODEC_H
18#define DEV_CODEC_H
19struct CODECState;
20struct INTELHDLinkState;
21
22typedef DECLCALLBACK(int) FNCODECVERBPROCESSOR(struct CODECState *pState, uint32_t cmd, uint64_t *pResp);
23typedef FNCODECVERBPROCESSOR *PFNCODECVERBPROCESSOR;
24typedef FNCODECVERBPROCESSOR **PPFNCODECVERBPROCESSOR;
25
26/* RPM 5.3.1 */
27#define CODEC_RESPONSE_UNSOLICITED RT_BIT_64(34)
28
29#define CODEC_CAD_MASK 0xF0000000
30#define CODEC_CAD_SHIFT 28
31#define CODEC_DIRECT_MASK RT_BIT(27)
32#define CODEC_NID_MASK 0x07F00000
33#define CODEC_NID_SHIFT 20
34#define CODEC_VERBDATA_MASK 0x000FFFFF
35#define CODEC_VERB_4BIT_CMD 0x000FFFF0
36#define CODEC_VERB_4BIT_DATA 0x0000000F
37#define CODEC_VERB_8BIT_CMD 0x000FFF00
38#define CODEC_VERB_8BIT_DATA 0x000000FF
39#define CODEC_VERB_16BIT_CMD 0x000F0000
40#define CODEC_VERB_16BIT_DATA 0x0000FFFF
41
42#define CODEC_CAD(cmd) ((cmd) & CODEC_CAD_MASK)
43#define CODEC_DIRECT(cmd) ((cmd) & CODEC_DIRECT_MASK)
44#define CODEC_NID(cmd) ((((cmd) & CODEC_NID_MASK)) >> CODEC_NID_SHIFT)
45#define CODEC_VERBDATA(cmd) ((cmd) & CODEC_VERBDATA_MASK)
46#define CODEC_VERB_CMD(cmd, mask, x) (((cmd) & (mask)) >> (x))
47#define CODEC_VERB_CMD4(cmd) (CODEC_VERB_CMD((cmd), CODEC_VERB_4BIT_CMD, 4))
48#define CODEC_VERB_CMD8(cmd) (CODEC_VERB_CMD((cmd), CODEC_VERB_8BIT_CMD, 8))
49#define CODEC_VERB_CMD16(cmd) (CODEC_VERB_CMD((cmd), CODEC_VERB_16BIT_CMD, 16))
50
51#define CODEC_VERB_GET_AMP_DIRECTION RT_BIT(15)
52#define CODEC_VERB_GET_AMP_SIDE RT_BIT(13)
53#define CODEC_VERB_GET_AMP_INDEX 0x7
54
55/* HDA spec 7.3.3.7 NoteA */
56#define CODEC_GET_AMP_DIRECTION(cmd) (((cmd) & CODEC_VERB_GET_AMP_DIRECTION) >> 15)
57#define CODEC_GET_AMP_SIDE(cmd) (((cmd) & CODEC_VERB_GET_AMP_SIDE) >> 13)
58#define CODEC_GET_AMP_INDEX(cmd) (CODEC_GET_AMP_DIRECTION(cmd) ? 0 : ((cmd) & CODEC_VERB_GET_AMP_INDEX))
59
60/* HDA spec 7.3.3.7 NoteC */
61#define CODEC_VERB_SET_AMP_OUT_DIRECTION RT_BIT(15)
62#define CODEC_VERB_SET_AMP_IN_DIRECTION RT_BIT(14)
63#define CODEC_VERB_SET_AMP_LEFT_SIDE RT_BIT(13)
64#define CODEC_VERB_SET_AMP_RIGHT_SIDE RT_BIT(12)
65#define CODEC_VERB_SET_AMP_INDEX (0x7 << 8)
66
67#define CODEC_SET_AMP_IS_OUT_DIRECTION(cmd) (((cmd) & CODEC_VERB_SET_AMP_OUT_DIRECTION) != 0)
68#define CODEC_SET_AMP_IS_IN_DIRECTION(cmd) (((cmd) & CODEC_VERB_SET_AMP_IN_DIRECTION) != 0)
69#define CODEC_SET_AMP_IS_LEFT_SIDE(cmd) (((cmd) & CODEC_VERB_SET_AMP_LEFT_SIDE) != 0)
70#define CODEC_SET_AMP_IS_RIGHT_SIDE(cmd) (((cmd) & CODEC_VERB_SET_AMP_RIGHT_SIDE) != 0)
71#define CODEC_SET_AMP_INDEX(cmd) (((cmd) & CODEC_VERB_SET_AMP_INDEX) >> 7)
72
73/* HDA spec 7.3.3.1 defines layout of configuration registers/verbs (0xF00) */
74/* VendorID (7.3.4.1) */
75#define CODEC_MAKE_F00_00(vendorID, deviceID) (((vendorID) << 16) | (deviceID))
76/* RevisionID (7.3.4.2)*/
77#define CODEC_MAKE_F00_02(MajRev, MinRev, RevisionID, SteppingID) (((MajRev) << 20)|((MinRev) << 16)|((RevisionID) << 8)|(SteppingID))
78/* Subordinate node count (7.3.4.3)*/
79#define CODEC_MAKE_F00_04(startNodeNumber, totalNodeNumber) ((((startNodeNumber) & 0xFF) << 16)|((totalNodeNumber) & 0xFF))
80/*
81 * Function Group Type (7.3.4.4)
82 * 0 & [0x3-0x7f] are reserved types
83 * [0x80 - 0xff] are vendor defined function groups
84 */
85#define CODEC_MAKE_F00_05(UnSol, NodeType) ((UnSol)|(NodeType))
86#define CODEC_F00_05_UNSOL RT_BIT(8)
87#define CODEC_F00_05_AFG (0x1)
88#define CODEC_F00_05_MFG (0x2)
89/* Audio Function Group capabilities (7.3.4.5) */
90#define CODEC_MAKE_F00_08(BeepGen, InputDelay, OutputDelay) ((BeepGen)| (((InputDelay) & 0xF) << 8) | ((OutputDelay) & 0xF))
91#define CODEC_F00_08_BEEP_GEN RT_BIT(16)
92
93/* Widget Capabilities (7.3.4.6) */
94#define CODEC_MAKE_F00_09(type, delay, chanel_count) \
95 ( (((type) & 0xF) << 20) \
96 | (((delay) & 0xF) << 16) \
97 | (((chanel_count) & 0xF) << 13))
98/* note: types 0x8-0xe are reserved */
99#define CODEC_F00_09_TYPE_AUDIO_OUTPUT (0x0)
100#define CODEC_F00_09_TYPE_AUDIO_INPUT (0x1)
101#define CODEC_F00_09_TYPE_AUDIO_MIXER (0x2)
102#define CODEC_F00_09_TYPE_AUDIO_SELECTOR (0x3)
103#define CODEC_F00_09_TYPE_PIN_COMPLEX (0x4)
104#define CODEC_F00_09_TYPE_POWER_WIDGET (0x5)
105#define CODEC_F00_09_TYPE_VOLUME_KNOB (0x6)
106#define CODEC_F00_09_TYPE_BEEP_GEN (0x7)
107#define CODEC_F00_09_TYPE_VENDOR_DEFINED (0xF)
108
109#define CODEC_F00_09_CAP_CP RT_BIT(12)
110#define CODEC_F00_09_CAP_L_R_SWAP RT_BIT(11)
111#define CODEC_F00_09_CAP_POWER_CTRL RT_BIT(10)
112#define CODEC_F00_09_CAP_DIGITAL RT_BIT(9)
113#define CODEC_F00_09_CAP_CONNECTION_LIST RT_BIT(8)
114#define CODEC_F00_09_CAP_UNSOL RT_BIT(7)
115#define CODEC_F00_09_CAP_PROC_WIDGET RT_BIT(6)
116#define CODEC_F00_09_CAP_STRIPE RT_BIT(5)
117#define CODEC_F00_09_CAP_FMT_OVERRIDE RT_BIT(4)
118#define CODEC_F00_09_CAP_AMP_FMT_OVERRIDE RT_BIT(3)
119#define CODEC_F00_09_CAP_OUT_AMP_PRESENT RT_BIT(2)
120#define CODEC_F00_09_CAP_IN_AMP_PRESENT RT_BIT(1)
121#define CODEC_F00_09_CAP_LSB RT_BIT(0)
122
123/* Supported PCM size, rates (7.3.4.7) */
124#define CODEC_F00_0A_32_BIT RT_BIT(19)
125#define CODEC_F00_0A_24_BIT RT_BIT(18)
126#define CODEC_F00_0A_16_BIT RT_BIT(17)
127#define CODEC_F00_0A_8_BIT RT_BIT(16)
128
129#define CODEC_F00_0A_48KHZ_MULT_8X RT_BIT(11)
130#define CODEC_F00_0A_48KHZ_MULT_4X RT_BIT(10)
131#define CODEC_F00_0A_44_1KHZ_MULT_4X RT_BIT(9)
132#define CODEC_F00_0A_48KHZ_MULT_2X RT_BIT(8)
133#define CODEC_F00_0A_44_1KHZ_MULT_2X RT_BIT(7)
134#define CODEC_F00_0A_48KHZ RT_BIT(6)
135#define CODEC_F00_0A_44_1KHZ RT_BIT(5)
136/* 2/3 * 48kHz */
137#define CODEC_F00_0A_48KHZ_2_3X RT_BIT(4)
138/* 1/2 * 44.1kHz */
139#define CODEC_F00_0A_44_1KHZ_1_2X RT_BIT(3)
140/* 1/3 * 48kHz */
141#define CODEC_F00_0A_48KHZ_1_3X RT_BIT(2)
142/* 1/4 * 44.1kHz */
143#define CODEC_F00_0A_44_1KHZ_1_4X RT_BIT(1)
144/* 1/6 * 48kHz */
145#define CODEC_F00_0A_48KHZ_1_6X RT_BIT(0)
146
147/* Supported streams formats (7.3.4.8) */
148#define CODEC_F00_0B_AC3 RT_BIT(2)
149#define CODEC_F00_0B_FLOAT32 RT_BIT(1)
150#define CODEC_F00_0B_PCM RT_BIT(0)
151
152/* Pin Capabilities (7.3.4.9)*/
153#define CODEC_MAKE_F00_0C(vref_ctrl) (((vref_ctrl) & 0xFF) << 8)
154#define CODEC_F00_0C_CAP_HBR RT_BIT(27)
155#define CODEC_F00_0C_CAP_DP RT_BIT(24)
156#define CODEC_F00_0C_CAP_EAPD RT_BIT(16)
157#define CODEC_F00_0C_CAP_HDMI RT_BIT(7)
158#define CODEC_F00_0C_CAP_BALANCED_IO RT_BIT(6)
159#define CODEC_F00_0C_CAP_INPUT RT_BIT(5)
160#define CODEC_F00_0C_CAP_OUTPUT RT_BIT(4)
161#define CODEC_F00_0C_CAP_HP RT_BIT(3)
162#define CODEC_F00_0C_CAP_PRESENSE_DETECT RT_BIT(2)
163#define CODEC_F00_0C_CAP_TRIGGER_REQUIRED RT_BIT(1)
164#define CODEC_F00_0C_CAP_IMPENDANCE_SENSE RT_BIT(0)
165
166/* Amplifier capabilities (7.3.4.10) */
167#define CODEC_MAKE_F00_0D(mute_cap, step_size, num_steps, offset) \
168 ( (((mute_cap) & 0x1) << 31) \
169 | (((step_size) & 0xFF) << 16) \
170 | (((num_steps) & 0xFF) << 8) \
171 | ((offset) & 0xFF))
172
173/* Connection list lenght (7.3.4.11) */
174#define CODEC_MAKE_F00_0E(long_form, length) \
175 ( (((long_form) & 0x1) << 7) \
176 | ((length) & 0x7F))
177/* Supported Power States (7.3.4.12) */
178#define CODEC_F00_0F_EPSS RT_BIT(31)
179#define CODEC_F00_0F_CLKSTOP RT_BIT(30)
180#define CODEC_F00_0F_S3D3 RT_BIT(29)
181#define CODEC_F00_0F_D3COLD RT_BIT(4)
182#define CODEC_F00_0F_D3 RT_BIT(3)
183#define CODEC_F00_0F_D2 RT_BIT(2)
184#define CODEC_F00_0F_D1 RT_BIT(1)
185#define CODEC_F00_0F_D0 RT_BIT(0)
186
187/* CP/IO Count (7.3.4.14) */
188#define CODEC_MAKE_F00_11(wake, unsol, numgpi, numgpo, numgpio) \
189 ( (((wake) & 0x1) << 31) \
190 | (((unsol) & 0x1) << 30) \
191 | (((numgpi) & 0xFF) << 16) \
192 | (((numgpo) & 0xFF) << 8) \
193 | ((numgpio) & 0xFF))
194
195/* Power States (7.3.3.10) */
196#define CODEC_MAKE_F05(reset, stopok, error, act, set) \
197 ( (((reset) & 0x1) << 10) \
198 | (((stopok) & 0x1) << 9) \
199 | (((error) & 0x1) << 8) \
200 | (((act) & 0x7) << 4) \
201 | ((set) & 0x7))
202#define CODEC_F05_D3COLD (4)
203#define CODEC_F05_D3 (3)
204#define CODEC_F05_D2 (2)
205#define CODEC_F05_D1 (1)
206#define CODEC_F05_D0 (0)
207
208#define CODEC_F05_IS_RESET(value) (((value) & RT_BIT(10)) != 0)
209#define CODEC_F05_IS_STOPOK(value) (((value) & RT_BIT(9)) != 0)
210#define CODEC_F05_IS_ERROR(value) (((value) & RT_BIT(8)) != 0)
211#define CODEC_F05_ACT(value) (((value) & 0x7) >> 4)
212#define CODEC_F05_SET(value) (((value) & 0x7))
213
214/* Pin Widged Control (7.3.3.13) */
215#define CODEC_F07_VREF_HIZ (0)
216#define CODEC_F07_VREF_50 (0x1)
217#define CODEC_F07_VREF_GROUND (0x2)
218#define CODEC_F07_VREF_80 (0x4)
219#define CODEC_F07_VREF_100 (0x5)
220#define CODEC_F07_IN_ENABLE RT_BIT(5)
221#define CODEC_F07_OUT_ENABLE RT_BIT(6)
222#define CODEC_F07_OUT_H_ENABLE RT_BIT(7)
223
224/* Converter formats (7.3.3.8) and (3.7.1) */
225#define CODEC_MAKE_A(fNonPCM, f44_1BaseRate, mult, div, bits, chan) \
226 ( (((fNonPCM) & 0x1) << 15) \
227 | (((f44_1BaseRate) & 0x1) << 14) \
228 | (((mult) & 0x7) << 11) \
229 | (((div) & 0x7) << 8) \
230 | (((bits) & 0x7) << 4) \
231 | ((chan) & 0xF))
232
233#define CODEC_A_MULT_1X (0)
234#define CODEC_A_MULT_2X (1)
235#define CODEC_A_MULT_3X (2)
236#define CODEC_A_MULT_4X (3)
237
238#define CODEC_A_DIV_1X (0)
239#define CODEC_A_DIV_2X (1)
240#define CODEC_A_DIV_3X (2)
241#define CODEC_A_DIV_4X (3)
242#define CODEC_A_DIV_5X (4)
243#define CODEC_A_DIV_6X (5)
244#define CODEC_A_DIV_7X (6)
245#define CODEC_A_DIV_8X (7)
246
247#define CODEC_A_8_BIT (0)
248#define CODEC_A_16_BIT (1)
249#define CODEC_A_20_BIT (2)
250#define CODEC_A_24_BIT (3)
251#define CODEC_A_32_BIT (4)
252
253/* Pin Sense (7.3.3.15) */
254#define CODEC_MAKE_F09_ANALOG(fPresent, impedance) \
255( (((fPresent) & 0x1) << 31) \
256 | (((impedance) & 0x7FFFFFFF)))
257#define CODEC_F09_ANALOG_NA 0x7FFFFFFF
258#define CODEC_MAKE_F09_DIGITAL(fPresent, fELDValid) \
259( (((fPresent) & 0x1) << 31) \
260 | (((fELDValid) & 0x1) << 30))
261
262/* HDA spec 7.3.3.31 defines layout of configuration registers/verbs (0xF1C) */
263/* Configuration's port connection */
264#define CODEC_F1C_PORT_MASK (0x3)
265#define CODEC_F1C_PORT_SHIFT (30)
266
267#define CODEC_F1C_PORT_COMPLEX (0x0)
268#define CODEC_F1C_PORT_NO_PHYS (0x1)
269#define CODEC_F1C_PORT_FIXED (0x2)
270#define CODEC_F1C_BOTH (0x3)
271
272/* Configuration's location */
273#define CODEC_F1C_LOCATION_MASK (0x3F)
274#define CODEC_F1C_LOCATION_SHIFT (24)
275/* [4:5] bits of location region means chassis attachment */
276#define CODEC_F1C_LOCATION_PRIMARY_CHASSIS (0)
277#define CODEC_F1C_LOCATION_INTERNAL RT_BIT(4)
278#define CODEC_F1C_LOCATION_SECONDRARY_CHASSIS RT_BIT(5)
279#define CODEC_F1C_LOCATION_OTHER (RT_BIT(5))
280
281/* [0:3] bits of location region means geometry location attachment */
282#define CODEC_F1C_LOCATION_NA (0)
283#define CODEC_F1C_LOCATION_REAR (0x1)
284#define CODEC_F1C_LOCATION_FRONT (0x2)
285#define CODEC_F1C_LOCATION_LEFT (0x3)
286#define CODEC_F1C_LOCATION_RIGTH (0x4)
287#define CODEC_F1C_LOCATION_TOP (0x5)
288#define CODEC_F1C_LOCATION_BOTTOM (0x6)
289#define CODEC_F1C_LOCATION_SPECIAL_0 (0x7)
290#define CODEC_F1C_LOCATION_SPECIAL_1 (0x8)
291#define CODEC_F1C_LOCATION_SPECIAL_3 (0x9)
292
293/* Configuration's devices */
294#define CODEC_F1C_DEVICE_MASK (0xF)
295#define CODEC_F1C_DEVICE_SHIFT (20)
296#define CODEC_F1C_DEVICE_LINE_OUT (0)
297#define CODEC_F1C_DEVICE_SPEAKER (0x1)
298#define CODEC_F1C_DEVICE_HP (0x2)
299#define CODEC_F1C_DEVICE_CD (0x3)
300#define CODEC_F1C_DEVICE_SPDIF_OUT (0x4)
301#define CODEC_F1C_DEVICE_DIGITAL_OTHER_OUT (0x5)
302#define CODEC_F1C_DEVICE_MODEM_LINE_SIDE (0x6)
303#define CODEC_F1C_DEVICE_MODEM_HANDSET_SIDE (0x7)
304#define CODEC_F1C_DEVICE_LINE_IN (0x8)
305#define CODEC_F1C_DEVICE_AUX (0x9)
306#define CODEC_F1C_DEVICE_MIC (0xA)
307#define CODEC_F1C_DEVICE_PHONE (0xB)
308#define CODEC_F1C_DEVICE_SPDIF_IN (0xC)
309#define CODEC_F1C_DEVICE_RESERVED (0xE)
310#define CODEC_F1C_DEVICE_OTHER (0xF)
311
312/* Configuration's Connection type */
313#define CODEC_F1C_CONNECTION_TYPE_MASK (0xF)
314#define CODEC_F1C_CONNECTION_TYPE_SHIFT (16)
315
316#define CODEC_F1C_CONNECTION_TYPE_UNKNOWN (0)
317#define CODEC_F1C_CONNECTION_TYPE_1_8INCHES (0x1)
318#define CODEC_F1C_CONNECTION_TYPE_1_4INCHES (0x2)
319#define CODEC_F1C_CONNECTION_TYPE_ATAPI (0x3)
320#define CODEC_F1C_CONNECTION_TYPE_RCA (0x4)
321#define CODEC_F1C_CONNECTION_TYPE_OPTICAL (0x5)
322#define CODEC_F1C_CONNECTION_TYPE_OTHER_DIGITAL (0x6)
323#define CODEC_F1C_CONNECTION_TYPE_ANALOG (0x7)
324#define CODEC_F1C_CONNECTION_TYPE_DIN (0x8)
325#define CODEC_F1C_CONNECTION_TYPE_XLR (0x9)
326#define CODEC_F1C_CONNECTION_TYPE_RJ_11 (0xA)
327#define CODEC_F1C_CONNECTION_TYPE_COMBO (0xB)
328#define CODEC_F1C_CONNECTION_TYPE_OTHER (0xF)
329
330/* Configuration's color */
331#define CODEC_F1C_COLOR_MASK (0xF)
332#define CODEC_F1C_COLOR_SHIFT (12)
333#define CODEC_F1C_COLOR_UNKNOWN (0)
334#define CODEC_F1C_COLOR_BLACK (0x1)
335#define CODEC_F1C_COLOR_GREY (0x2)
336#define CODEC_F1C_COLOR_BLUE (0x3)
337#define CODEC_F1C_COLOR_GREEN (0x4)
338#define CODEC_F1C_COLOR_RED (0x5)
339#define CODEC_F1C_COLOR_ORANGE (0x6)
340#define CODEC_F1C_COLOR_YELLOW (0x7)
341#define CODEC_F1C_COLOR_PURPLE (0x8)
342#define CODEC_F1C_COLOR_PINK (0x9)
343#define CODEC_F1C_COLOR_RESERVED_0 (0xA)
344#define CODEC_F1C_COLOR_RESERVED_1 (0xB)
345#define CODEC_F1C_COLOR_RESERVED_2 (0xC)
346#define CODEC_F1C_COLOR_RESERVED_3 (0xD)
347#define CODEC_F1C_COLOR_WHITE (0xE)
348#define CODEC_F1C_COLOR_OTHER (0xF)
349
350/* Configuration's misc */
351#define CODEC_F1C_MISC_MASK (0xF)
352#define CODEC_F1C_MISC_SHIFT (8)
353#define CODEC_F1C_MISC_JACK_DETECT RT_BIT(0)
354#define CODEC_F1C_MISC_RESERVED_0 RT_BIT(1)
355#define CODEC_F1C_MISC_RESERVED_1 RT_BIT(2)
356#define CODEC_F1C_MISC_RESERVED_2 RT_BIT(3)
357
358/* Configuration's association */
359#define CODEC_F1C_ASSOCIATION_MASK (0xF)
360#define CODEC_F1C_ASSOCIATION_SHIFT (4)
361/* Connection's sequence */
362#define CODEC_F1C_SEQ_MASK (0xF)
363#define CODEC_F1C_SEQ_SHIFT (0)
364
365/* Implementation identification (7.3.3.30) */
366#define CODEC_MAKE_F20(bmid, bsku, aid) \
367 ( (((bmid) & 0xFFFF) << 16) \
368 | (((bsku) & 0xFF) << 8) \
369 | (((aid) & 0xFF)) \
370 )
371
372/* macro definition helping in filling the configuration registers. */
373#define CODEC_MAKE_F1C(port_connectivity, location, device, connection_type, color, misc, association, sequence) \
374 ( ((port_connectivity) << CODEC_F1C_PORT_SHIFT) \
375 | ((location) << CODEC_F1C_LOCATION_SHIFT) \
376 | ((device) << CODEC_F1C_DEVICE_SHIFT) \
377 | ((connection_type) << CODEC_F1C_CONNECTION_TYPE_SHIFT) \
378 | ((color) << CODEC_F1C_COLOR_SHIFT) \
379 | ((misc) << CODEC_F1C_MISC_SHIFT) \
380 | ((association) << CODEC_F1C_ASSOCIATION_SHIFT) \
381 | ((sequence)))
382
383
384typedef struct CODECVERB
385{
386 uint32_t verb;
387 /* operation bitness mask */
388 uint32_t mask;
389 PFNCODECVERBPROCESSOR pfn;
390} CODECVERB;
391
392#ifndef VBOX_HDA_CODEC_EMU
393# define TYPE union
394#else
395# define TYPE struct
396#endif
397TYPE CODECNODE;
398typedef TYPE CODECNODE CODECNODE;
399typedef TYPE CODECNODE *PCODECNODE;
400
401
402typedef enum
403{
404 PI_INDEX = 0, /* PCM in */
405 PO_INDEX, /* PCM out */
406 MC_INDEX, /* Mic in */
407 LAST_INDEX
408} ENMSOUNDSOURCE;
409
410typedef enum
411{
412 STAC9220_CODEC,
413 ALC885_CODEC
414} ENMCODEC;
415
416#define AFMT_IN In
417#define AFMT_OUT Out
418
419#ifdef VBOX_WITH_AUDIO_FLEXIBLE_FORMAT
420# define MAX_AUDIO_FORMAT 64
421typedef SWVoiceIn *CODECAUDIOINFORMAT[MAX_AUDIO_FORMAT];
422typedef SWVoiceOut *CODECAUDIOOUTFORMAT[MAX_AUDIO_FORMAT];
423# define AUDIO_FORMAT_SELECTOR(pState, dir, hz, mult, divizor) ((pState)->aSwVoice##dir[(hz)*24 + (mult)*8 + (divizor)])
424# define AFMT_HZ_48K 0
425# define AFMT_HZ_44_1K 1
426# define AFMT_MULT_X1 0
427# define AFMT_MULT_X2 1
428# define AFMT_MULT_X3 2 /* reserved for stac9220 */
429# define AFMT_MULT_X4 3
430# define AFMT_DIV_X1 0
431# define AFMT_DIV_X2 1
432# define AFMT_DIV_X3 2
433# define AFMT_DIV_X4 3
434# define AFMT_DIV_X5 4
435# define AFMT_DIV_X6 5
436# define AFMT_DIV_X7 6
437# define AFMT_DIV_X8 7
438#else
439# define AUDIO_FORMAT_SELECTOR(pState, dir, hz, mult, divizor) ((pState)->SwVoice##dir)
440#endif
441
442
443typedef struct CODECState
444{
445 uint16_t id;
446 uint16_t u16VendorId;
447 uint16_t u16DeviceId;
448 uint8_t u8BSKU;
449 uint8_t u8AssemblyId;
450 CODECVERB *pVerbs;
451 int cVerbs;
452 PCODECNODE pNodes;
453 QEMUSoundCard card;
454#ifndef VBOX_WITH_AUDIO_FLEXIBLE_FORMAT
455 /** PCM in */
456 SWVoiceIn *SwVoiceIn;
457 /** PCM out */
458 SWVoiceOut *SwVoiceOut;
459 /** Mic in */
460 SWVoiceIn *voice_mc;
461#else
462 CODECAUDIOOUTFORMAT aSwVoiceOut;
463 CODECAUDIOINFORMAT aSwVoiceIn;
464#endif
465 ENMCODEC enmCodec;
466 void *pHDAState;
467 bool fInReset;
468 const uint8_t cTotalNodes;
469 const uint8_t *au8Ports;
470 const uint8_t *au8Dacs;
471 const uint8_t *au8AdcVols;
472 const uint8_t *au8Adcs;
473 const uint8_t *au8AdcMuxs;
474 const uint8_t *au8Pcbeeps;
475 const uint8_t *au8SpdifIns;
476 const uint8_t *au8SpdifOuts;
477 const uint8_t *au8DigInPins;
478 const uint8_t *au8DigOutPins;
479 const uint8_t *au8Cds;
480 const uint8_t *au8VolKnobs;
481 const uint8_t *au8Reserveds;
482 const uint8_t u8AdcVolsLineIn;
483 const uint8_t u8DacLineOut;
484 DECLR3CALLBACKMEMBER(int, pfnProcess, (struct CODECState *));
485 DECLR3CALLBACKMEMBER(int, pfnLookup, (struct CODECState *pState, uint32_t verb, PPFNCODECVERBPROCESSOR));
486 DECLR3CALLBACKMEMBER(int, pfnReset, (struct CODECState *pState));
487 DECLR3CALLBACKMEMBER(void, pfnTransfer, (struct CODECState *pState, ENMSOUNDSOURCE, int avail));
488 DECLR3CALLBACKMEMBER(int, pfnCodecNodeReset, (struct CODECState *pState, uint8_t, PCODECNODE));
489
490} CODECState;
491
492int codecConstruct(PPDMDEVINS pDevIns, CODECState *pCodecState, ENMCODEC enmCodec);
493int codecDestruct(CODECState *pCodecState);
494int codecSaveState(CODECState *pCodecState, PSSMHANDLE pSSMHandle);
495int codecLoadState(CODECState *pCodecState, PSSMHANDLE pSSMHandle);
496
497#endif
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