| 1 | /*
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| 2 | * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
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| 3 | * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
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| 4 | *
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 6 | * copy of this software and associated documentation files (the "Software"),
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| 7 | * to deal in the Software without restriction, including without limitation
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| 8 | * the rights to use, copy, modify, merge, publish, distribute, sub license,
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| 9 | * and/or sell copies of the Software, and to permit persons to whom the
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| 10 | * Software is furnished to do so, subject to the following conditions:
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| 11 | *
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| 12 | * The above copyright notice and this permission notice (including the
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| 13 | * next paragraph) shall be included in all copies or substantial portions
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| 14 | * of the Software.
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| 15 | *
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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| 19 | * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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| 22 | * DEALINGS IN THE SOFTWARE.
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| 23 | */
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| 24 | #ifndef _VIA_DRM_H_
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| 25 | #define _VIA_DRM_H_
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| 26 |
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| 27 | /* WARNING: These defines must be the same as what the Xserver uses.
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| 28 | * if you change them, you must change the defines in the Xserver.
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| 29 | */
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| 30 |
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| 31 | #ifndef _VIA_DEFINES_
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| 32 | #define _VIA_DEFINES_
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| 33 |
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| 34 | #if !defined(__KERNEL__) && !defined(_KERNEL)
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| 35 | #include "via_drmclient.h"
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| 36 | #endif
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| 37 |
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| 38 | #define VIA_NR_SAREA_CLIPRECTS 8
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| 39 | #define VIA_NR_XVMC_PORTS 10
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| 40 | #define VIA_NR_XVMC_LOCKS 5
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| 41 | #define VIA_MAX_CACHELINE_SIZE 64
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| 42 | #define XVMCLOCKPTR(saPriv,lockNo) \
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| 43 | ((volatile drm_hw_lock_t *)(((((unsigned long) (saPriv)->XvMCLockArea) + \
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| 44 | (VIA_MAX_CACHELINE_SIZE - 1)) & \
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| 45 | ~(VIA_MAX_CACHELINE_SIZE - 1)) + \
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| 46 | VIA_MAX_CACHELINE_SIZE*(lockNo)))
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| 47 |
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| 48 | /* Each region is a minimum of 64k, and there are at most 64 of them.
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| 49 | */
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| 50 | #define VIA_NR_TEX_REGIONS 64
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| 51 | #define VIA_LOG_MIN_TEX_REGION_SIZE 16
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| 52 | #endif
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| 53 |
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| 54 | #define VIA_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */
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| 55 | #define VIA_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */
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| 56 | #define VIA_UPLOAD_CTX 0x4
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| 57 | #define VIA_UPLOAD_BUFFERS 0x8
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| 58 | #define VIA_UPLOAD_TEX0 0x10
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| 59 | #define VIA_UPLOAD_TEX1 0x20
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| 60 | #define VIA_UPLOAD_CLIPRECTS 0x40
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| 61 | #define VIA_UPLOAD_ALL 0xff
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| 62 |
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| 63 | /* VIA specific ioctls */
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| 64 | #define DRM_VIA_ALLOCMEM 0x00
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| 65 | #define DRM_VIA_FREEMEM 0x01
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| 66 | #define DRM_VIA_AGP_INIT 0x02
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| 67 | #define DRM_VIA_FB_INIT 0x03
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| 68 | #define DRM_VIA_MAP_INIT 0x04
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| 69 | #define DRM_VIA_DEC_FUTEX 0x05
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| 70 | #define NOT_USED
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| 71 | #define DRM_VIA_DMA_INIT 0x07
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| 72 | #define DRM_VIA_CMDBUFFER 0x08
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| 73 | #define DRM_VIA_FLUSH 0x09
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| 74 | #define DRM_VIA_PCICMD 0x0a
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| 75 | #define DRM_VIA_CMDBUF_SIZE 0x0b
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| 76 | #define NOT_USED
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| 77 | #define DRM_VIA_WAIT_IRQ 0x0d
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| 78 | #define DRM_VIA_DMA_BLIT 0x0e
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| 79 | #define DRM_VIA_BLIT_SYNC 0x0f
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| 80 |
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| 81 | #define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t)
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| 82 | #define DRM_IOCTL_VIA_FREEMEM DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
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| 83 | #define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t)
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| 84 | #define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t)
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| 85 | #define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t)
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| 86 | #define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
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| 87 | #define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t)
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| 88 | #define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
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| 89 | #define DRM_IOCTL_VIA_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_VIA_FLUSH)
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| 90 | #define DRM_IOCTL_VIA_PCICMD DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
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| 91 | #define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \
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| 92 | drm_via_cmdbuf_size_t)
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| 93 | #define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t)
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| 94 | #define DRM_IOCTL_VIA_DMA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t)
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| 95 | #define DRM_IOCTL_VIA_BLIT_SYNC DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t)
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| 96 |
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| 97 | /* Indices into buf.Setup where various bits of state are mirrored per
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| 98 | * context and per buffer. These can be fired at the card as a unit,
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| 99 | * or in a piecewise fashion as required.
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| 100 | */
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| 101 |
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| 102 | #define VIA_TEX_SETUP_SIZE 8
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| 103 |
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| 104 | /* Flags for clear ioctl
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| 105 | */
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| 106 | #define VIA_FRONT 0x1
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| 107 | #define VIA_BACK 0x2
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| 108 | #define VIA_DEPTH 0x4
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| 109 | #define VIA_STENCIL 0x8
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| 110 |
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| 111 | #define VIA_MEM_VIDEO 0 /* matches drm constant */
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| 112 | #define VIA_MEM_AGP 1 /* matches drm constant */
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| 113 | #define VIA_MEM_SYSTEM 2
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| 114 | #define VIA_MEM_MIXED 3
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| 115 | #define VIA_MEM_UNKNOWN 4
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| 116 |
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| 117 | typedef struct {
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| 118 | uint32_t offset;
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| 119 | uint32_t size;
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| 120 | } drm_via_agp_t;
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| 121 |
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| 122 | typedef struct {
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| 123 | uint32_t offset;
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| 124 | uint32_t size;
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| 125 | } drm_via_fb_t;
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| 126 |
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| 127 | typedef struct {
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| 128 | uint32_t context;
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| 129 | uint32_t type;
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| 130 | uint32_t size;
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| 131 | unsigned long index;
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| 132 | unsigned long offset;
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| 133 | } drm_via_mem_t;
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| 134 |
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| 135 | typedef struct _drm_via_init {
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| 136 | enum {
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| 137 | VIA_INIT_MAP = 0x01,
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| 138 | VIA_CLEANUP_MAP = 0x02
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| 139 | } func;
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| 140 |
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| 141 | unsigned long sarea_priv_offset;
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| 142 | unsigned long fb_offset;
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| 143 | unsigned long mmio_offset;
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| 144 | unsigned long agpAddr;
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| 145 | } drm_via_init_t;
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| 146 |
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| 147 | typedef struct _drm_via_futex {
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| 148 | enum {
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| 149 | VIA_FUTEX_WAIT = 0x00,
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| 150 | VIA_FUTEX_WAKE = 0X01
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| 151 | } func;
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| 152 | uint32_t ms;
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| 153 | uint32_t lock;
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| 154 | uint32_t val;
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| 155 | } drm_via_futex_t;
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| 156 |
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| 157 | typedef struct _drm_via_dma_init {
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| 158 | enum {
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| 159 | VIA_INIT_DMA = 0x01,
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| 160 | VIA_CLEANUP_DMA = 0x02,
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| 161 | VIA_DMA_INITIALIZED = 0x03
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| 162 | } func;
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| 163 |
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| 164 | unsigned long offset;
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| 165 | unsigned long size;
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| 166 | unsigned long reg_pause_addr;
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| 167 | } drm_via_dma_init_t;
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| 168 |
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| 169 | typedef struct _drm_via_cmdbuffer {
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| 170 | char __user *buf;
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| 171 | unsigned long size;
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| 172 | } drm_via_cmdbuffer_t;
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| 173 |
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| 174 | /* Warning: If you change the SAREA structure you must change the Xserver
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| 175 | * structure as well */
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| 176 |
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| 177 | typedef struct _drm_via_tex_region {
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| 178 | unsigned char next, prev; /* indices to form a circular LRU */
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| 179 | unsigned char inUse; /* owned by a client, or free? */
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| 180 | int age; /* tracked by clients to update local LRU's */
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| 181 | } drm_via_tex_region_t;
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| 182 |
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| 183 | typedef struct _drm_via_sarea {
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| 184 | unsigned int dirty;
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| 185 | unsigned int nbox;
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| 186 | drm_clip_rect_t boxes[VIA_NR_SAREA_CLIPRECTS];
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| 187 | drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
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| 188 | int texAge; /* last time texture was uploaded */
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| 189 | int ctxOwner; /* last context to upload state */
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| 190 | int vertexPrim;
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| 191 |
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| 192 | /*
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| 193 | * Below is for XvMC.
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| 194 | * We want the lock integers alone on, and aligned to, a cache line.
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| 195 | * Therefore this somewhat strange construct.
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| 196 | */
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| 197 |
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| 198 | char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
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| 199 |
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| 200 | unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
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| 201 | unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
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| 202 | unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */
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| 203 |
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| 204 | /* Used by the 3d driver only at this point, for pageflipping:
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| 205 | */
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| 206 |
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| 207 | unsigned int pfCurrentOffset;
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| 208 | } drm_via_sarea_t;
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| 209 |
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| 210 | typedef struct _drm_via_cmdbuf_size {
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| 211 | enum {
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| 212 | VIA_CMDBUF_SPACE = 0x01,
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| 213 | VIA_CMDBUF_LAG = 0x02
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| 214 | } func;
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| 215 | int wait;
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| 216 | uint32_t size;
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| 217 | } drm_via_cmdbuf_size_t;
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| 218 |
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| 219 | typedef enum {
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| 220 | VIA_IRQ_ABSOLUTE = 0x0,
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| 221 | VIA_IRQ_RELATIVE = 0x1,
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| 222 | VIA_IRQ_SIGNAL = 0x10000000,
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| 223 | VIA_IRQ_FORCE_SEQUENCE = 0x20000000
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| 224 | } via_irq_seq_type_t;
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| 225 |
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| 226 | #define VIA_IRQ_FLAGS_MASK 0xF0000000
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| 227 |
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| 228 | enum drm_via_irqs{drm_via_irq_hqv0 = 0,
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| 229 | drm_via_irq_hqv1,
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| 230 | drm_via_irq_dma0_dd,
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| 231 | drm_via_irq_dma0_td,
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| 232 | drm_via_irq_dma1_dd,
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| 233 | drm_via_irq_dma1_td,
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| 234 | drm_via_irq_num};
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| 235 |
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| 236 | struct drm_via_wait_irq_request{
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| 237 | unsigned irq;
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| 238 | via_irq_seq_type_t type;
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| 239 | uint32_t sequence;
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| 240 | uint32_t signal;
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| 241 | };
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| 242 |
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| 243 | typedef union drm_via_irqwait {
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| 244 | struct drm_via_wait_irq_request request;
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| 245 | struct drm_wait_vblank_reply reply;
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| 246 | } drm_via_irqwait_t;
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| 247 |
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| 248 | typedef struct drm_via_blitsync {
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| 249 | uint32_t sync_handle;
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| 250 | unsigned engine;
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| 251 | } drm_via_blitsync_t;
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| 252 |
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| 253 | typedef struct drm_via_dmablit {
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| 254 | uint32_t num_lines;
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| 255 | uint32_t line_length;
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| 256 |
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| 257 | uint32_t fb_addr;
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| 258 | uint32_t fb_stride;
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| 259 |
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| 260 | unsigned char *mem_addr;
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| 261 | uint32_t mem_stride;
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| 262 |
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| 263 | int bounce_buffer;
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| 264 | int to_fb;
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| 265 |
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| 266 | drm_via_blitsync_t sync;
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| 267 | } drm_via_dmablit_t;
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| 268 |
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| 269 |
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| 270 | #endif /* _VIA_DRM_H_ */
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