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1/*++ BUILD Version: 0011 // Increment this if a change has global effects
2
3Copyright (c) 1991-2001 Microsoft Corporation
4
5Module Name:
6
7 mce.h
8
9Abstract:
10
11 This header file defines the Machine Check Errors definitions.
12
13Author:
14
15 David N. Cutler (davec)
16
17
18Revision History:
19
20 Creation: 04-Apr-2001
21
22--*/
23
24#ifndef _MCE_
25#define _MCE_
26
27//
28// HalMcaLogInformation
29//
30
31#if defined(_X86_) || defined(_IA64_) || defined(_AMD64_)
32
33//
34// ADDR register for each MCA bank
35//
36
37typedef union _MCI_ADDR{
38 struct {
39 ULONG Address;
40 ULONG Reserved;
41 };
42
43 ULONGLONG QuadPart;
44} MCI_ADDR, *PMCI_ADDR;
45
46
47typedef enum {
48 HAL_MCE_RECORD,
49 HAL_MCA_RECORD
50} MCA_EXCEPTION_TYPE;
51
52
53#if defined(_AMD64_)
54
55//
56// STATUS register for each MCA bank.
57//
58
59typedef union _MCI_STATS {
60 struct {
61 USHORT McaErrorCode;
62 USHORT ModelErrorCode;
63 ULONG OtherInformation : 25;
64 ULONG ContextCorrupt : 1;
65 ULONG AddressValid : 1;
66 ULONG MiscValid : 1;
67 ULONG ErrorEnabled : 1;
68 ULONG UncorrectedError : 1;
69 ULONG StatusOverFlow : 1;
70 ULONG Valid : 1;
71 } MciStatus;
72
73 ULONG64 QuadPart;
74} MCI_STATS, *PMCI_STATS;
75
76#endif // _AMD64_
77
78#if defined(_X86_)
79
80//
81// STATUS register for each MCA bank.
82//
83
84typedef union _MCI_STATS {
85 struct {
86 USHORT McaCod;
87 USHORT MsCod;
88 ULONG OtherInfo : 25;
89 ULONG Damage : 1;
90 ULONG AddressValid : 1;
91 ULONG MiscValid : 1;
92 ULONG Enabled : 1;
93 ULONG UnCorrected : 1;
94 ULONG OverFlow : 1;
95 ULONG Valid : 1;
96 } MciStats;
97
98 ULONGLONG QuadPart;
99
100} MCI_STATS, *PMCI_STATS;
101
102#endif // _X86_
103
104//
105// MCA exception log entry
106// Defined as a union to contain MCA specific log or Pentium style MCE info.
107//
108
109#define MCA_EXTREG_V2MAX 24 // X86: Max. Number of extended registers
110
111#if defined(_X86_) || defined(_AMD64_)
112
113typedef struct _MCA_EXCEPTION {
114
115 // Begin Version 1 stuff
116 ULONG VersionNumber; // Version number of this record type
117 MCA_EXCEPTION_TYPE ExceptionType; // MCA or MCE
118 LARGE_INTEGER TimeStamp; // exception recording timestamp
119 ULONG ProcessorNumber;
120 ULONG Reserved1;
121
122 union {
123 struct {
124 UCHAR BankNumber;
125 UCHAR Reserved2[7];
126 MCI_STATS Status;
127 MCI_ADDR Address;
128 ULONGLONG Misc;
129 } Mca;
130
131 struct {
132 ULONGLONG Address; // physical addr of cycle causing the error
133 ULONGLONG Type; // cycle specification causing the error
134 } Mce;
135 } u;
136 // End Version 1 stuff
137
138#if defined(_X86_)
139
140 // Begin Version 2 stuff
141 ULONG ExtCnt;
142 ULONG Reserved3;
143 ULONGLONG ExtReg[MCA_EXTREG_V2MAX];
144 // End Version 2 stuff
145
146#endif
147
148} MCA_EXCEPTION, *PMCA_EXCEPTION;
149
150typedef MCA_EXCEPTION CMC_EXCEPTION, *PCMC_EXCEPTION; // Corrected Machine Check
151typedef MCA_EXCEPTION CPE_EXCEPTION, *PCPE_EXCEPTION; // Corrected Platform Error
152
153#if defined(_X86_)
154
155#define MCA_EXCEPTION_V1_SIZE FIELD_OFFSET(MCA_EXCEPTION, ExtCnt)
156#define MCA_EXCEPTION_V2_SIZE sizeof(struct _MCA_EXCEPTION)
157
158#endif
159
160#endif // _X86_ || _AMD64_
161
162//
163// ERRORS: ERROR_SEVERITY definitions
164//
165// One day the MS compiler will support typed enums with type != int so this
166// type of enums (UCHAR, __int64) could be defined...
167//
168
169#if defined(_AMD64_) || defined(_IA64_)
170
171typedef UCHAR ERROR_SEVERITY, *PERROR_SEVERITY;
172
173typedef enum _ERROR_SEVERITY_VALUE {
174 ErrorRecoverable = 0,
175 ErrorFatal = 1,
176 ErrorCorrected = 2,
177 ErrorOthers = 3, // [3,...] values are reserved
178} ERROR_SEVERITY_VALUE;
179
180#endif
181
182#if defined(_IA64_)
183
184#if 0
185// FIXFIX: This should not be required for IA64.
186//
187// STATUS register for each MCA bank.
188//
189
190typedef union _MCI_STATS {
191 struct {
192 USHORT McaCod;
193 USHORT MsCod;
194 ULONG OtherInfo : 25;
195 ULONG Damage : 1;
196 ULONG AddressValid : 1;
197 ULONG MiscValid : 1;
198 ULONG Enabled : 1;
199 ULONG UnCorrected : 1;
200 ULONG OverFlow : 1;
201 ULONG Valid : 1;
202 } MciStats;
203
204 ULONGLONG QuadPart;
205
206} MCI_STATS, *PMCI_STATS;
207
208#endif // 0
209
210//
211// IA64 ERRORS: ERROR_REVISION definitions
212//
213
214typedef union _ERROR_REVISION {
215 USHORT Revision; // Major and Minor revision number of the record:
216 struct {
217 UCHAR Minor; // Byte0: Minor.
218 UCHAR Major; // Byte1: Major.
219 };
220} ERROR_REVISION, *PERROR_REVISION;
221
222// For Info:
223#define ERROR_MAJOR_REVISION_SAL_03_00 0
224#define ERROR_MINOR_REVISION_SAL_03_00 2
225#define ERROR_REVISION_SAL_03_00 { ERROR_MINOR_REVISION_SAL_03_00, \
226 ERROR_MAJOR_REVISION_SAL_03_00 }
227
228//
229// Section Header revision is fixed at Major == 2 and Minor == 0
230//
231#define ERROR_FIXED_SECTION_REVISION { 2,\
232 0 }
233
234//
235// IA64 ERRORS: ERROR_TIMESTAMP definitions
236//
237
238typedef union _ERROR_TIMESTAMP {
239 ULONGLONG TimeStamp;
240 struct {
241 UCHAR Seconds; // Byte0: Seconds
242 UCHAR Minutes; // Byte1: Minutes
243 UCHAR Hours; // Byte2: Hours
244 UCHAR Reserved; // Byte3: Reserved
245 UCHAR Day; // Byte4: Day
246 UCHAR Month; // Byte5: Month
247 UCHAR Year; // Byte6: Year
248 UCHAR Century; // Byte7: Century
249 };
250} ERROR_TIMESTAMP, *PERROR_TIMESTAMP;
251
252//
253// IA64 ERRORS: ERROR_GUID definitions
254//
255
256typedef struct _ERROR_GUID {
257 ULONG Data1;
258 USHORT Data2;
259 USHORT Data3;
260 UCHAR Data4[8];
261} ERROR_GUID, *PERROR_GUID;
262
263//
264// IA64 ERRORS: ERROR GUIDs definitions
265//
266
267typedef ERROR_GUID _ERROR_DEVICE_GUID;
268typedef _ERROR_DEVICE_GUID ERROR_DEVICE_GUID, *PERROR_DEVICE_GUID;
269
270typedef ERROR_GUID _ERROR_PLATFORM_GUID;
271typedef _ERROR_PLATFORM_GUID ERROR_PLATFORM_GUID, *PERROR_PLATFORM_GUID;
272
273//
274// IA64 ERRORS: ERROR_RECORD_HEADER definitions
275//
276
277typedef union _ERROR_RECORD_VALID {
278 UCHAR Valid;
279 struct { // Bits
280 UCHAR OemPlatformID:1; // 0: OEM Platform Id is present in the record header
281 UCHAR Reserved:7; // 1-7: Reserved
282 };
283} ERROR_RECORD_VALID, *PERROR_RECORD_VALID;
284
285typedef struct _ERROR_RECORD_HEADER { // Offsets:
286 ULONGLONG Id; // 0: Unique identifier
287 ERROR_REVISION Revision; // 8: Major and Minor revision number of the record
288 ERROR_SEVERITY ErrorSeverity; // 10: Error Severity
289 ERROR_RECORD_VALID Valid; // 11: Validation bits
290 ULONG Length; // 12: Length of this record in bytes, including the header
291 ERROR_TIMESTAMP TimeStamp; // 16: Timestamp recorded when event occured
292 UCHAR OemPlatformId[16]; // 24: Unique platform identifier. OEM defined.
293} ERROR_RECORD_HEADER, *PERROR_RECORD_HEADER;
294
295//
296// IA64 ERRORS: ERROR_SECTION_HEADER definitions
297//
298
299typedef union _ERROR_RECOVERY_INFO {
300 UCHAR RecoveryInfo;
301 struct { // Bits:
302 UCHAR Corrected:1; // 0: Corrected
303 UCHAR NotContained:1; // 1: Containment Warning
304 UCHAR Reset:1; // 2: Reset
305 UCHAR Reserved:4; // 6-3: Reserved
306 UCHAR Valid:1; // 7: Valid Recovery Information
307 };
308} ERROR_RECOVERY_INFO, *PERROR_RECOVERY_INFO;
309
310typedef struct _ERROR_SECTION_HEADER {
311 ERROR_DEVICE_GUID Guid; // Unique identifier
312 ERROR_REVISION Revision; // Major and Minor revision number of the section
313 ERROR_RECOVERY_INFO RecoveryInfo; // Recovery Information
314 UCHAR Reserved;
315 ULONG Length; // Length of this error device section in bytes,
316 // including the header.
317} ERROR_SECTION_HEADER, *PERROR_SECTION_HEADER;
318
319//
320// IA64 Machine Check Error Logs:
321// WMI requires processor LID being stored in the Log.
322// This LID corresponds to the processor on which the SAL_PROC was executed on.
323//
324// TEMPTEMP: Implementation is temporary, until we implement HAL SW Error Section.
325// Note that the current FW builds do not update the _ERROR_PROCESSOR.CRLid field,
326// assuming there is a _ERROR_PROCESSOR section in the record.
327//
328
329#if !defined(__midl)
330__inline
331USHORT
332GetFwMceLogProcessorNumber(
333 PERROR_RECORD_HEADER Log
334 )
335{
336 PERROR_SECTION_HEADER section = (PERROR_SECTION_HEADER)((ULONG64)Log + sizeof(*Log));
337 USHORT lid = (USHORT)((UCHAR)(section->Reserved));
338 lid |= (USHORT)((UCHAR)(Log->TimeStamp.Reserved) << 8);
339 return( lid );
340} // GetFwMceLogProcessorNumber()
341#endif // !__midl
342
343//
344// IA64 ERRORS: ERROR_PROCESSOR device definitions
345//
346// The MCA architecture supports five different types of error reporting functional units
347// with the associated error records and its error severity.
348// At any point in time, a processor could encounter an MCA/CMC event due to errors detected
349// in one or more of the following units:
350// - Cache Check
351// - TLB Check
352// - Bus Check
353// - Register File
354// - Micro Architectural
355//
356// Terminology:
357//
358// - Target Address:
359// 64-bit integer containing the physical address where the data was to be delivered or
360// obtained. This could also be the incoming address for external snoops and TLB shoot-downs.
361//
362// - Requestor Identifier:
363// 64-bit integer specifying the bus agent that generated the transaction responsible for
364// the Machine Check event.
365//
366// - Responder Identifier:
367// 64-bit integer specifying the bus agent that responded to a transaction responsible for
368// the Machine Check event.
369//
370// - Precise Instruction Pointer:
371// 64-bit integer specifying the virtual address that points to the IA-64 bundle that
372// contained the instruction responsible for the Machine Check event.
373//
374
375#define ERROR_PROCESSOR_GUID \
376 { 0xe429faf1, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 }}
377
378typedef union _ERROR_MODINFO_VALID {
379 ULONGLONG Valid;
380 struct { // Bits
381 ULONGLONG CheckInfo: 1; // 0:
382 ULONGLONG RequestorIdentifier: 1; // 1:
383 ULONGLONG ResponderIdentifier: 1; // 2:
384 ULONGLONG TargetIdentifier: 1; // 3:
385 ULONGLONG PreciseIP: 1; // 4:
386 ULONGLONG Reserved: 59; // 5-63:
387 };
388} ERROR_MODINFO_VALID, *PERROR_MODINFO_VALID;
389
390typedef enum _ERROR_CHECK_IS {
391 isIA64 = 0,
392 isIA32 = 1,
393} ERROR_CHECK_IS;
394
395typedef enum _ERROR_CACHE_CHECK_OPERATION {
396 CacheUnknownOp = 0,
397 CacheLoad = 1,
398 CacheStore = 2,
399 CacheInstructionFetch = 3,
400 CacheDataPrefetch = 4,
401 CacheSnoop = 5,
402 CacheCastOut = 6,
403 CacheMoveIn = 7,
404} ERROR_CACHE_CHECK_OPERATION;
405
406typedef enum _ERROR_CACHE_CHECK_MESI {
407 CacheInvalid = 0,
408 CacheHeldShared = 1,
409 CacheHeldExclusive = 2,
410 CacheModified = 3,
411} ERROR_CACHE_CHECK_MESI;
412
413typedef union _ERROR_CACHE_CHECK {
414 ULONGLONG CacheCheck;
415 struct
416 {
417 ULONGLONG Operation:4; // bits 0- 3: Cache operation
418 ULONGLONG Level:2; // 4- 5: Cache Level
419 ULONGLONG Reserved1:2; // 6- 7
420 ULONGLONG DataLine:1; // 8 : Failure data part of cache line
421 ULONGLONG TagLine:1; // 9 : Failure tag part of cache line
422 ULONGLONG DataCache:1; // 10 : Failure in data cache
423 ULONGLONG InstructionCache:1; // 11 : Failure in instruction cache
424 ULONGLONG MESI:3; // 12-14:
425 ULONGLONG MESIValid:1; // 15 : MESI field is valid
426 ULONGLONG Way:5; // 16-20: Failure in Way of Cache
427 ULONGLONG WayIndexValid:1; // 21 : Way and Index fields valid
428 ULONGLONG Reserved2:10; // 22-31
429 ULONGLONG Index:20; // 32-51: Index of cache line
430 ULONGLONG Reserved3:2; // 52-53
431 ULONGLONG InstructionSet:1; // 54 : 0 - IA64 instruction, 1- IA32 instruction
432 ULONGLONG InstructionSetValid:1; // 55 : InstructionSet field is valid
433 ULONGLONG PrivilegeLevel:2; // 56-57: Privlege level of instrustion
434 ULONGLONG PrivilegeLevelValid:1; // 58 : PrivilegeLevel field is Valid
435 ULONGLONG MachineCheckCorrected:1; // 59 : 1 - Machine Check Corrected
436 ULONGLONG TargetAddressValid:1; // 60 : Target Address is valid
437 ULONGLONG RequestIdValid:1; // 61 : RequestId is valid
438 ULONGLONG ResponderIdValid:1; // 62 : ResponderId is valid
439 ULONGLONG PreciseIPValid:1; // 63 : Precise Inststruction Pointer is Valid
440 };
441} ERROR_CACHE_CHECK, *PERROR_CACHE_CHECK;
442
443typedef enum _ERROR_TLB_CHECK_OPERATION {
444 TlbUnknownOp = 0,
445 TlbAccessWithLoad = 1,
446 TlbAccessWithStore = 2,
447 TlbAccessWithInstructionFetch = 3,
448 TlbAccessWithDataPrefetch = 4,
449 TlbShootDown = 5,
450 TlbProbe = 6,
451 TlbVhptFill = 7,
452} ERROR_TLB_CHECK_OPERATION;
453
454typedef union _ERROR_TLB_CHECK {
455 ULONGLONG TlbCheck;
456 struct
457 {
458 ULONGLONG TRSlot:8; // bits 0- 7: Slot number of Translation Register
459 ULONGLONG TRSlotValid:1; // 8 : TRSlot field is valid
460 ULONGLONG Reserved1:1; // 9
461 ULONGLONG Level:2; // 10-11: TLB Level
462 ULONGLONG Reserved2:4; // 12-15
463 ULONGLONG DataTransReg:1; // 16 : Error in data translation register
464 ULONGLONG InstructionTransReg:1; // 17 : Error in instruction translation register
465 ULONGLONG DataTransCache:1; // 18 : Error in data translation cache
466 ULONGLONG InstructionTransCache:1; // 19 : Error in instruction translation cache
467 ULONGLONG Operation:4; // 20-23: Operation
468 ULONGLONG Reserved3:30; // 24-53
469 ULONGLONG InstructionSet:1; // 54 : 0 - IA64 instruction, 1- IA32 instruction
470 ULONGLONG InstructionSetValid:1; // 55 : InstructionSet field is valid
471 ULONGLONG PrivilegeLevel:2; // 56-57: Privlege level of instrustion
472 ULONGLONG PrivilegeLevelValid:1; // 58 : PrivilegeLevel field is Valid
473 ULONGLONG MachineCheckCorrected:1; // 59 : 1 - Machine Check Corrected
474 ULONGLONG TargetAddressValid:1; // 60 : Target Address is valid
475 ULONGLONG RequestIdValid:1; // 61 : RequestId is valid
476 ULONGLONG ResponderIdValid:1; // 62 : ResponderId is valid
477 ULONGLONG PreciseIPValid:1; // 63 : Precise Inststruction Pointer is Valid
478 };
479} ERROR_TLB_CHECK, *PERROR_TLB_CHECK;
480
481typedef enum _ERROR_BUS_CHECK_OPERATION {
482 BusUnknownOp = 0,
483 BusPartialRead = 1,
484 BusPartialWrite = 2,
485 BusFullLineRead = 3,
486 BusFullLineWrite = 4,
487 BusWriteBack = 5,
488 BusSnoopProbe = 6,
489 BusIncomingPtcG = 7,
490 BusWriteCoalescing = 8,
491} ERROR_BUS_CHECK_OPERATION;
492
493typedef union _ERROR_BUS_CHECK {
494 ULONGLONG BusCheck;
495 struct
496 {
497 ULONGLONG Size:5; // bits 0- 4: Transaction size
498 ULONGLONG Internal:1; // 5 : Internal bus error
499 ULONGLONG External:1; // 6 : External bus error
500 ULONGLONG CacheTransfer:1; // 7 : Error occured in Cache to Cache Transfer
501 ULONGLONG Type:8; // 8-15: Transaction type
502 ULONGLONG Severity:5; // 16-20: Error severity - platform specific
503 ULONGLONG Hierarchy:2; // 21-22: Level or Bus hierarchy
504 ULONGLONG Reserved1:1; // 23
505 ULONGLONG Status:8; // 24-31: Bus error status - processor bus specific
506 ULONGLONG Reserved2:22; // 32-53
507 ULONGLONG InstructionSet:1; // 54 : 0 - IA64 instruction, 1- IA32 instruction
508 ULONGLONG InstructionSetValid:1; // 55 : InstructionSet field is valid
509 ULONGLONG PrivilegeLevel:2; // 56-57: Privlege level of instrustion
510 ULONGLONG PrivilegeLevelValid:1; // 58 : PrivilegeLevel field is Valid
511 ULONGLONG MachineCheckCorrected:1; // 59 : 1 - Machine Check Corrected
512 ULONGLONG TargetAddressValid:1; // 60 : Target Address is valid
513 ULONGLONG RequestIdValid:1; // 61 : RequestId is valid
514 ULONGLONG ResponderIdValid:1; // 62 : ResponderId is valid
515 ULONGLONG PreciseIPValid:1; // 63 : Precise Inststruction Pointer is Valid
516 };
517} ERROR_BUS_CHECK, *PERROR_BUS_CHECK;
518
519typedef enum _ERROR_REGFILE_CHECK_IDENTIFIER {
520 RegFileUnknownId = 0,
521 GeneralRegisterBank1 = 1,
522 GeneralRegisterBank0 = 2,
523 FloatingPointRegister = 3,
524 BranchRegister = 4,
525 PredicateRegister = 5,
526 ApplicationRegister = 6,
527 ControlRegister = 7,
528 RegionRegister = 8,
529 ProtectionKeyRegister = 9,
530 DataBreakPointRegister = 10,
531 InstructionBreakPointRegister = 11,
532 PerformanceMonitorControlRegister = 12,
533 PerformanceMonitorDataRegister = 13,
534} ERROR_REGFILE_CHECK_IDENTIFIER;
535
536typedef enum _ERROR_REGFILE_CHECK_OPERATION {
537 RegFileUnknownOp = 0,
538 RegFileRead = 1,
539 RegFileWrite = 2,
540} ERROR_REGFILE_CHECK_OPERATION;
541
542typedef union _ERROR_REGFILE_CHECK {
543 ULONGLONG RegFileCheck;
544 struct
545 {
546 ULONGLONG Identifier:4; // bits 0- 3: Register file identifier
547 ULONGLONG Operation:4; // 4- 7: Operation that causes the MC event
548 ULONGLONG RegisterNumber:7; // 8-14: Register number responsible for MC event
549 ULONGLONG RegisterNumberValid:1; // 15 : Register number field is valid
550 ULONGLONG Reserved1:38; // 16-53
551 ULONGLONG InstructionSet:1; // 54 : 0 - IA64 instruction, 1- IA32 instruction
552 ULONGLONG InstructionSetValid:1; // 55 : InstructionSet field is valid
553 ULONGLONG PrivilegeLevel:2; // 56-57: Privlege level of instrustion
554 ULONGLONG PrivilegeLevelValid:1; // 58 : PrivilegeLevel field is Valid
555 ULONGLONG MachineCheckCorrected:1; // 59 : 1 - Machine Check Corrected
556 ULONGLONG Reserved2:3; // 60-62
557 ULONGLONG PreciseIPValid:1; // 63 : Precise Inststruction Pointer is Valid
558 };
559} ERROR_REGFILE_CHECK, *PERROR_REGFILE_CHECK;
560
561typedef enum _ERROR_MS_CHECK_OPERATION {
562 MsUnknownOp = 0,
563 MsReadOrLoad = 1,
564 MsWriteOrStore = 2,
565 MsOverTemperature = 3,
566 MsNormalTemperature = 4
567} ERROR_MS_CHECK_OPERATION;
568
569typedef union _ERROR_MS_CHECK {
570 ULONGLONG MsCheck;
571 struct
572 {
573 ULONGLONG StructureIdentifier:5; // bits 0- 4: Structure Identifier - impl. specific
574 ULONGLONG Level:3; // 5- 7: Structure Level where error was generated
575 ULONGLONG ArrayId:4; // 8-11: Identification of the array
576 ULONGLONG Operation:4; // 12-15: Operation
577 ULONGLONG Way:6; // 16-21: Way where the error was located
578 ULONGLONG WayValid:1; // 22 : Way field is valid
579 ULONGLONG IndexValid:1; // 23 : Index field is valid
580 ULONGLONG Reserved1:8; // 24-31
581 ULONGLONG Index:8; // 32-39: Index where the error was located
582 ULONGLONG Reserved2:14; // 40-53
583 ULONGLONG InstructionSet:1; // 54 : 0 - IA64 instruction, 1- IA32 instruction
584 ULONGLONG InstructionSetValid:1; // 55 : InstructionSet field is valid
585 ULONGLONG PrivilegeLevel:2; // 56-57: Privlege level of instrustion
586 ULONGLONG PrivilegeLevelValid:1; // 58 : PrivilegeLevel field is Valid
587 ULONGLONG MachineCheckCorrected:1; // 59 : 1 - Machine Check Corrected
588 ULONGLONG TargetAddressValid:1; // 60 : Target Address is valid
589 ULONGLONG RequestIdValid:1; // 61 : RequestId is valid
590 ULONGLONG ResponderIdValid:1; // 62 : ResponderId is valid
591 ULONGLONG PreciseIPValid:1; // 63 : Precise Inststruction Pointer is Valid
592 };
593} ERROR_MS_CHECK, *PERROR_MS_CHECK;
594
595typedef union _ERROR_CHECK_INFO {
596 ULONGLONG CheckInfo;
597 ERROR_CACHE_CHECK CacheCheck;
598 ERROR_TLB_CHECK TlbCheck;
599 ERROR_BUS_CHECK BusCheck;
600 ERROR_REGFILE_CHECK RegFileCheck;
601 ERROR_MS_CHECK MsCheck;
602} ERROR_CHECK_INFO, *PERROR_CHECK_INFO;
603
604// SAL Specs July 2000: The size of _ERROR_MODINFO will always be 48 Bytes.
605
606typedef struct _ERROR_MODINFO {
607 ERROR_MODINFO_VALID Valid;
608 ERROR_CHECK_INFO CheckInfo;
609 ULONGLONG RequestorId;
610 ULONGLONG ResponderId;
611 ULONGLONG TargetId;
612 ULONGLONG PreciseIP;
613} ERROR_MODINFO, *PERROR_MODINFO;
614
615typedef union _ERROR_PROCESSOR_VALID {
616 ULONGLONG Valid;
617 struct { // Bits
618 ULONGLONG ErrorMap: 1; // 0:
619 ULONGLONG StateParameter: 1; // 1:
620 ULONGLONG CRLid: 1; // 2:
621 ULONGLONG StaticStruct:1; // 3: Processor Static Info error.
622 ULONGLONG CacheCheckNum:4; // 4-7: Cache errors.
623 ULONGLONG TlbCheckNum:4; // 8-11: Tlb errors.
624 ULONGLONG BusCheckNum:4; // 12-15: Bus errors.
625 ULONGLONG RegFileCheckNum:4; // 16-19: Registers file errors.
626 ULONGLONG MsCheckNum:4; // 20-23: Micro-Architecture errors.
627 ULONGLONG CpuIdInfo:1; // 24: CPUID Info.
628 ULONGLONG Reserved:39; // 25-63: Reserved.
629 };
630} ERROR_PROCESSOR_VALID, *PERROR_PROCESSOR_VALID;
631
632typedef union _ERROR_PROCESSOR_ERROR_MAP {
633 ULONGLONG ErrorMap;
634 struct {
635 ULONGLONG Cid:4; // bits 0- 3: Processor Core Identifier
636 ULONGLONG Tid:4; // 4- 7: Logical Thread Identifier
637 ULONGLONG Eic:4; // 8-11: Instruction Caches Level Information
638 ULONGLONG Edc:4; // 12-15: Data Caches Level Information
639 ULONGLONG Eit:4; // 16-19: Instruction TLB Level Information
640 ULONGLONG Edt:4; // 20-23: Data TLB Level Information
641 ULONGLONG Ebh:4; // 24-27: Processor Bus Level Information
642 ULONGLONG Erf:4; // 28-31: Register File Level Information
643 ULONGLONG Ems:16; // 32-47: MicroArchitecture Level Information
644 ULONGLONG Reserved:16;
645 };
646} ERROR_PROCESSOR_ERROR_MAP, *PERROR_PROCESSOR_ERROR_MAP;
647
648typedef ERROR_PROCESSOR_ERROR_MAP _ERROR_PROCESSOR_LEVEL_INDEX;
649typedef _ERROR_PROCESSOR_LEVEL_INDEX ERROR_PROCESSOR_LEVEL_INDEX, *PERROR_PROCESSOR_LEVEL_INDEX;
650
651typedef union _ERROR_PROCESSOR_STATE_PARAMETER {
652 ULONGLONG StateParameter;
653 struct {
654 ULONGLONG reserved0:2; // 0-1 : reserved
655 ULONGLONG rz:1; // 2 : Rendez-vous successful
656 ULONGLONG ra:1; // 3 : Rendez-vous attempted
657 ULONGLONG me:1; // 4 : Distinct Multiple errors
658 ULONGLONG mn:1; // 5 : Min-state Save Area registered
659 ULONGLONG sy:1; // 6 : Storage integrity synchronized
660 ULONGLONG co:1; // 7 : Continuable
661 ULONGLONG ci:1; // 8 : Machine Check isolated
662 ULONGLONG us:1; // 9 : Uncontained Storage damage
663 ULONGLONG hd:1; // 10 : Hardware damage
664 ULONGLONG tl:1; // 11 : Trap lost
665 ULONGLONG mi:1; // 12 : More Information
666 ULONGLONG pi:1; // 13 : Precise Instruction pointer
667 ULONGLONG pm:1; // 14 : Precise Min-state Save Area
668 ULONGLONG dy:1; // 15 : Processor Dynamic State valid
669 ULONGLONG in:1; // 16 : INIT interruption
670 ULONGLONG rs:1; // 17 : RSE valid
671 ULONGLONG cm:1; // 18 : Machine Check corrected
672 ULONGLONG ex:1; // 19 : Machine Check expected
673 ULONGLONG cr:1; // 20 : Control Registers valid
674 ULONGLONG pc:1; // 21 : Performance Counters valid
675 ULONGLONG dr:1; // 22 : Debug Registers valid
676 ULONGLONG tr:1; // 23 : Translation Registers valid
677 ULONGLONG rr:1; // 24 : Region Registers valid
678 ULONGLONG ar:1; // 25 : Application Registers valid
679 ULONGLONG br:1; // 26 : Branch Registers valid
680 ULONGLONG pr:1; // 27 : Predicate Registers valid
681 ULONGLONG fp:1; // 28 : Floating-Point Registers valid
682 ULONGLONG b1:1; // 29 : Preserved Bank 1 General Registers valid
683 ULONGLONG b0:1; // 30 : Preserved Bank 0 General Registers valid
684 ULONGLONG gr:1; // 31 : General Registers valid
685 ULONGLONG dsize:16; // 47-32 : Processor Dynamic State size
686 ULONGLONG reserved1:11; // 48-58 : reserved
687 ULONGLONG cc:1; // 59 : Cache Check
688 ULONGLONG tc:1; // 60 : TLB Check
689 ULONGLONG bc:1; // 61 : Bus Check
690 ULONGLONG rc:1; // 62 : Register File Check
691 ULONGLONG uc:1; // 63 : Micro-Architectural Check
692 };
693} ERROR_PROCESSOR_STATE_PARAMETER, *PERROR_PROCESSOR_STATE_PARAMETER;
694
695typedef union _PROCESSOR_LOCAL_ID {
696 ULONGLONG LocalId;
697 struct {
698 ULONGLONG reserved:16; // 0-16 : reserved
699 ULONGLONG eid:8; // 16-23 : Extended Id
700 ULONGLONG id:8; // 24-31 : Id
701 ULONGLONG ignored:32; // 32-63 : ignored
702 };
703} PROCESSOR_LOCAL_ID, *PPROCESSOR_LOCAL_ID;
704
705typedef struct _ERROR_PROCESSOR_MS {
706 ULONGLONG MsError [ /* Valid.MsCheckNum */ 1]; // 0 -> 15 registers file errors.
707} ERROR_PROCESSOR_MS, *PERROR_PROCESSOR_MS;
708
709typedef struct _ERROR_PROCESSOR_CPUID_INFO { // Must be 48 bytes.
710 ULONGLONG CpuId0;
711 ULONGLONG CpuId1;
712 ULONGLONG CpuId2;
713 ULONGLONG CpuId3;
714 ULONGLONG CpuId4;
715 ULONGLONG Reserved;
716} ERROR_PROCESSOR_CPUID_INFO, *PERROR_PROCESSOR_CPUID_INFO;
717
718typedef union _ERROR_PROCESSOR_STATIC_INFO_VALID {
719 ULONGLONG Valid;
720 struct { // Bits
721 // Warning: Match the VALID fields with the _ERROR_PROCESSOR_STATIC_INFO members.
722 // KD extensions use the field names to access the PSI structure.
723 ULONGLONG MinState: 1; // 0: MinState valid.
724 ULONGLONG BR: 1; // 1: Branch Registers valid.
725 ULONGLONG CR: 1; // 2: Control Registers valid.
726 ULONGLONG AR: 1; // 3: Application Registers valid.
727 ULONGLONG RR: 1; // 4: Registers valid.
728 ULONGLONG FR: 1; // 5: Registers valid.
729 ULONGLONG Reserved: 58; // 6-63: Reserved.
730 };
731} ERROR_PROCESSOR_STATIC_INFO_VALID, *PERROR_PROCESSOR_STATIC_INFO_VALID;
732
733typedef struct _ERROR_PROCESSOR_STATIC_INFO {
734 ERROR_PROCESSOR_STATIC_INFO_VALID Valid;
735 UCHAR MinState[ /* SAL Specs, July 2000 and Jan 2001 state approximatively: */ 1024];
736 ULONGLONG BR [ 8 ];
737 ULONGLONG CR [ /* SAL Specs, July 2000 states that it is processor dependent */ 128 ];
738 ULONGLONG AR [ /* SAL Specs, July 2000 states that it is processor dependent */ 128 ];
739 ULONGLONG RR [ 8 ];
740 ULONGLONG FR [ 2 * 128 ];
741} ERROR_PROCESSOR_STATIC_INFO, *PERROR_PROCESSOR_STATIC_INFO;
742
743typedef struct _ERROR_PROCESSOR {
744 ERROR_SECTION_HEADER Header;
745 ERROR_PROCESSOR_VALID Valid;
746 ERROR_PROCESSOR_ERROR_MAP ErrorMap;
747 ERROR_PROCESSOR_STATE_PARAMETER StateParameter;
748 PROCESSOR_LOCAL_ID CRLid;
749#if 0
750// The presence of the following data depends on the valid bits
751// from ERROR_PROCESSOR.Valid.
752//
753 ERROR_MODINFO CacheErrorInfo [ /* Valid.CacheCheckNum */ ]; // 0->15 cache error modinfo structs.
754 ERROR_MODINFO TlbErrorInfo [ /* Valid.TlbCheckNum */ ]; // 0->15 tlb error modinfo structs.
755 ERROR_MODINFO BusErrorInfo [ /* Valid.BusCheckNum */ ]; // 0->15 bus error modinfo structs.
756 ERROR_MODINFO RegFileCheckInfo [ /* Valid.RegFileCheckNum */ ]; // 0->15 registers file errors.
757 ERROR_MODINFO MsCheckInfo [ /* Valid.MsCheckNum */ ]; // 0->15 registers file errors.
758 ERROR_PROCESSOR_CPUID_INFO CpuIdInfo; // field will always be there but could be zero-padded.
759 ERROR_PROCESSOR_STATIC_INFO StaticInfo; // field will always be there but could be zero-padded.
760#endif // 0
761} ERROR_PROCESSOR, *PERROR_PROCESSOR;
762
763//
764// IA64 ERROR PROCESSOR State Parameter - GR18 - definitions.
765//
766
767#define ERROR_PROCESSOR_STATE_PARAMETER_CACHE_CHECK_SHIFT 59
768#define ERROR_PROCESSOR_STATE_PARAMETER_CACHE_CHECK_MASK 0x1
769#define ERROR_PROCESSOR_STATE_PARAMETER_TLB_CHECK_SHIFT 60
770#define ERROR_PROCESSOR_STATE_PARAMETER_TLB_CHECK_MASK 0x1
771#define ERROR_PROCESSOR_STATE_PARAMETER_BUS_CHECK_SHIFT 61
772#define ERROR_PROCESSOR_STATE_PARAMETER_BUS_CHECK_MASK 0x1
773#define ERROR_PROCESSOR_STATE_PARAMETER_REG_CHECK_SHIFT 62
774#define ERROR_PROCESSOR_STATE_PARAMETER_REG_CHECK_MASK 0x1
775#define ERROR_PROCESSOR_STATE_PARAMETER_MICROARCH_CHECK_SHIFT 63
776#define ERROR_PROCESSOR_STATE_PARAMETER_MICROARCH_CHECK_MASK 0x1
777
778//
779// For legacy consumers
780//
781#define ERROR_PROCESSOR_STATE_PARAMETER_UNKNOWN_CHECK_SHIFT ERROR_PROCESSOR_STATE_PARAMETER_MICROARCH_CHECK_SHIFT
782#define ERROR_PROCESSOR_STATE_PARAMETER_UNKNOWN_CHECK_MASK ERROR_PROCESSOR_STATE_PARAMETER_MICROARCH_CHECK_MASK
783
784////////////////////////////////////////////////////////////////////
785//
786// IA64 PLATFORM ERRORS Definitions
787//
788// We tried to respect the order in which these error devices are
789// presented in the SAL specs.
790
791//
792// IA64 ERRORS: _ERR_TYPE definitions
793//
794// Warning 04/01/01: "ERR_TYPE" or "ERROR_TYPE" are already used in the NT namespace.
795//
796
797typedef enum _ERR_TYPES {
798// Generic error types:
799 ERR_INTERNAL = 1, // Error detected internal to the component
800 ERR_BUS = 16, // Error detected in the bus
801// Detailed Internal Error Types:
802 ERR_MEM = 4, // Storage error in memory (DRAM)
803 ERR_TLB = 5, // Storage error in TLB
804 ERR_CACHE = 6, // Storage error in cache
805 ERR_FUNCTION = 7, // Error in one or more functional units
806 ERR_SELFTEST = 8, // Component failed self test
807 ERR_FLOW = 9, // Overflow or Undervalue of internal queue
808// Detailed Bus Error Types:
809 ERR_MAP = 17, // Virtual address not found on IO-TLB or IO-PDIR
810 ERR_IMPROPER = 18, // Improper access error
811 ERR_UNIMPL = 19, // Access to a memory address which is not mapped to any component
812 ERR_LOL = 20, // Loss Of Lockstep
813 ERR_RESPONSE = 21, // Response to which there is no associated request
814 ERR_PARITY = 22, // Bus parity error
815 ERR_PROTOCOL = 23, // Detection of a protocol error
816 ERR_ERROR = 24, // Detection of PATH_ERROR
817 ERR_TIMEOUT = 25, // Bus operation time-out
818 ERR_POISONED = 26, // A read was issued to data which has been poisoned
819} _ERR_TYPE;
820
821//
822// IA64 ERRORS: ERROR_STATUS definitions
823//
824
825typedef union _ERROR_STATUS {
826 ULONGLONG Status;
827 struct { // Bits:
828 ULONGLONG Reserved0:8; // 7-0: Reserved
829 ULONGLONG Type:8; // 15-8: Error Type - See _ERR_TYPE definitions.
830 ULONGLONG Address:1; // 16: Error was detected on address signals or on address portion of transaction
831 ULONGLONG Control:1; // 17: Error was detected on control signals or in control portion of transaction
832 ULONGLONG Data:1; // 18: Error was detected on data signals or in data portion of transaction
833 ULONGLONG Responder:1; // 19: Error was detected by responder of transaction
834 ULONGLONG Requestor:1; // 20: Error was detected by requestor of transaction
835 ULONGLONG FirstError:1; // 21: If multiple errors, this is the first error of the highest severity that occurred
836 ULONGLONG Overflow:1; // 22: Additional errors occurred which were not logged because registers overflow
837 ULONGLONG Reserved1:41; // 63-23: Reserved
838 };
839} ERROR_STATUS, *PERROR_STATUS;
840
841//
842// IA64 ERRORS: Platform OEM_DATA definitions
843//
844
845typedef struct _ERROR_OEM_DATA {
846 USHORT Length;
847#if 0
848 UCHAR Data[/* ERROR_OEM_DATA.Length */];
849#endif // 0
850} ERROR_OEM_DATA, *PERROR_OEM_DATA;
851
852//
853// IA64 ERRORS: Platform BUS_SPECIFIC_DATA definitions
854//
855
856typedef union _ERROR_BUS_SPECIFIC_DATA {
857 ULONGLONG BusSpecificData;
858 struct { // Bits :
859 ULONGLONG LockAsserted:1; // 0: LOCK# Asserted during request phase
860 ULONGLONG DeferLogged:1; // 1: Defer phase is logged
861 ULONGLONG IOQEmpty:1; // 2: IOQ is empty
862 ULONGLONG DeferredTransaction:1; // 3: Component interface deferred transaction
863 ULONGLONG RetriedTransaction:1; // 4: Component interface retried transaction
864 ULONGLONG MemoryClaimedTransaction:1; // 5: memory claimed the transaction
865 ULONGLONG IOClaimedTransaction:1; // 6: IO controller claimed the transaction
866 ULONGLONG ResponseParitySignal:1; // 7: Response parity signal
867 ULONGLONG DeferSignal:1; // 8: DEFER# signal
868 ULONGLONG HitMSignal:1; // 9: HITM# signal
869 ULONGLONG HitSignal:1; // 10: HIT# signal
870 ULONGLONG RequestBusFirstCycle:6; // 16-11: First cycle of request bus
871 ULONGLONG RequestBusSecondCycle:6; // 22-17: Second cycle of request bus
872 ULONGLONG AddressParityBusFirstCycle:2; // 24-23: First cycle of address parity bus
873 ULONGLONG AddressParityBusSecondCycle:2; // 26-25: Second cycle of address parity
874 ULONGLONG ResponseBus:3; // 29-27: Response bus
875 ULONGLONG RequestParitySignalFirstCycle:1; // 30: First cycle of request parity signal
876 ULONGLONG RequestParitySignalSecondCycle:1; // 31: Second cycle of request parity signal
877 ULONGLONG Reserved:32; // 63-32: Reserved
878 };
879} ERROR_BUS_SPECIFIC_DATA, *PERROR_BUS_SPECIFIC_DATA;
880
881//
882// IA64 ERRORS: Platform ERROR_MEMORY device definitions
883//
884// With reference to the ACPI Memory Device.
885//
886
887#define ERROR_MEMORY_GUID \
888 { 0xe429faf2, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 }}
889
890typedef union _ERROR_MEMORY_VALID {
891 ULONGLONG Valid;
892 struct { // Bits
893 ULONGLONG ErrorStatus:1; // 0: Error Status valid bit
894 ULONGLONG PhysicalAddress:1; // 1: Physical Address valid bit
895 ULONGLONG AddressMask:1; // 2: Address Mask bit
896 ULONGLONG Node:1; // 3: Node valid bit
897 ULONGLONG Card:1; // 4: Card valid bit
898 ULONGLONG Module:1; // 5: Module valid bit
899 ULONGLONG Bank:1; // 6: Bank valid bit
900 ULONGLONG Device:1; // 7: Device valid bit
901 ULONGLONG Row:1; // 8: Row valid bit
902 ULONGLONG Column:1; // 9: Column valid bit
903 ULONGLONG BitPosition:1; // 10: Bit Position valid bit
904 ULONGLONG RequestorId:1; // 11: Platform Requestor Id valid bit
905 ULONGLONG ResponderId:1; // 12: Platform Respinder Id valid bit
906 ULONGLONG TargetId:1; // 13: Platform Target Id valid bit
907 ULONGLONG BusSpecificData:1; // 14: Platform Bus specific data valid bit
908 ULONGLONG OemId:1; // 15: Platform OEM id valid bit
909 ULONGLONG OemData:1; // 16: Platform OEM data valid bit
910 ULONGLONG Reserved:47; // 63-17: Reserved
911 };
912} ERROR_MEMORY_VALID, *PERROR_MEMORY_VALID;
913
914typedef struct _ERROR_MEMORY {
915 ERROR_SECTION_HEADER Header;
916 ERROR_MEMORY_VALID Valid;
917 ERROR_STATUS ErrorStatus; // Memory device error status fields - See ERROR_STATUS defs.
918 ULONGLONG PhysicalAddress; // Physical Address of the memory error
919 ULONGLONG PhysicalAddressMask; // Valid bits for Physical Address
920 USHORT Node; // Node identifier in a multi-node system
921 USHORT Card; // Card number of the memory error location
922 USHORT Module; // Module number of the memory error location
923 USHORT Bank; // Bank number of the memory error location
924 USHORT Device; // Device number of the memory error location
925 USHORT Row; // Row number of the memory error location
926 USHORT Column; // Column number of the memory error location
927 USHORT BitPosition; // Bit within the word that is in error
928 ULONGLONG RequestorId; // Hardware address of the device or component initiating transaction
929 ULONGLONG ResponderId; // Hardware address of the responder to transaction
930 ULONGLONG TargetId; // Hardware address of intended target of transaction
931 ULONGLONG BusSpecificData; // Bus dependent data of the on-board processor. It is a OEM specific field.
932 UCHAR OemId[16]; // OEM defined identification for memory controller
933 ERROR_OEM_DATA OemData; // OEM platform specific data.
934} ERROR_MEMORY, *PERROR_MEMORY;
935
936//
937// IA64 ERRORS: Platform ERROR_PCI_BUS device definitions
938//
939// With reference to the PCI Specifications.
940//
941
942#define ERROR_PCI_BUS_GUID \
943 { 0xe429faf4, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 }}
944
945typedef union _ERROR_PCI_BUS_VALID {
946 ULONGLONG Valid;
947 struct { // Bits
948 ULONGLONG ErrorStatus:1; // 0: Error Status valid bit
949 ULONGLONG ErrorType:1; // 1: Error Type valid bit
950 ULONGLONG Id:1; // 2: Identifier valid bit
951 ULONGLONG Address:1; // 3: Address valid bit
952 ULONGLONG Data:1; // 4: Data valid bit
953 ULONGLONG CmdType:1; // 5: Command Type valid bit
954 ULONGLONG RequestorId:1; // 6: Requestor Identifier valid bit
955 ULONGLONG ResponderId:1; // 7: Responder Identifier valid bit
956 ULONGLONG TargetId:1; // 8: Target Identifer valid bit
957 ULONGLONG OemId:1; // 9: OEM Identification valid bit
958 ULONGLONG OemData:1; // 10: OEM Data valid bit
959 ULONGLONG Reserved:53; // 11-63: Reserved
960 };
961} ERROR_PCI_BUS_VALID, *PERROR_PCI_BUS_VALID;
962
963typedef struct _ERROR_PCI_BUS_TYPE {
964 UCHAR Type;
965 UCHAR Reserved;
966} ERROR_PCI_BUS_TYPE, *PERROR_PCI_BUS_TYPE;
967
968#define PciBusUnknownError ((UCHAR)0)
969#define PciBusDataParityError ((UCHAR)1)
970#define PciBusSystemError ((UCHAR)2)
971#define PciBusMasterAbort ((UCHAR)3)
972#define PciBusTimeOut ((UCHAR)4)
973#define PciMasterDataParityError ((UCHAR)5)
974#define PciAddressParityError ((UCHAR)6)
975#define PciCommandParityError ((UCHAR)7)
976// PciOtherErrors Reserved
977
978typedef struct _ERROR_PCI_BUS_ID {
979 UCHAR BusNumber; // Bus Number
980 UCHAR SegmentNumber; // Segment Number
981} ERROR_PCI_BUS_ID, *PERROR_PCI_BUS_ID;
982
983typedef struct _ERROR_PCI_BUS {
984 ERROR_SECTION_HEADER Header;
985 ERROR_PCI_BUS_VALID Valid;
986 ERROR_STATUS ErrorStatus; // PCI Bus Error Status - See ERROR_STATUS definitions.
987 ERROR_PCI_BUS_TYPE Type; // PCI Bus Error Type
988 ERROR_PCI_BUS_ID Id; // PCI Bus Identifier
989 UCHAR Reserved[4]; // Reserved
990 ULONGLONG Address; // Memory or IO Address on the PCI bus at
991 // the time of the event
992 ULONGLONG Data; // Data on the PCI bus at time of the event
993 ULONGLONG CmdType; // Bus Command or Operation at time of the event
994 ULONGLONG RequestorId; // Bus Requestor Identifier at time of the event
995 ULONGLONG ResponderId; // Bus Responder Identifier at time of the event
996 ULONGLONG TargetId; // Intended Bus Target Identifier at time of the event
997 UCHAR OemId[16]; // OEM defined identification for pci bus
998 ERROR_OEM_DATA OemData; // OEM specific data.
999} ERROR_PCI_BUS, *PERROR_PCI_BUS;
1000
1001//
1002// IA64 ERRORS: Platform ERROR_PCI_COMPONENT device definitions
1003//
1004// With reference to the PCI Specifications.
1005//
1006
1007#define ERROR_PCI_COMPONENT_GUID \
1008 { 0xe429faf6, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 }}
1009
1010typedef union _ERROR_PCI_COMPONENT_VALID {
1011 ULONGLONG Valid;
1012 struct { // Bits:
1013 ULONGLONG ErrorStatus:1; // 0: Error Status valid bit
1014 ULONGLONG Info:1; // 1: Information valid bit
1015 ULONGLONG MemoryMappedRegistersPairs:1; // 2: Number of Memory Mapped Registers Pairs valid bit
1016 ULONGLONG ProgrammedIORegistersPairs:1; // 3: Number of Programmed IO Registers Pairs valid bit
1017 ULONGLONG RegistersDataPairs:1; // 4: Memory Mapped Registers Pairs valid bit
1018 ULONGLONG OemData:1; // 5: OEM Data valid bit.
1019 ULONGLONG Reserved:58; // 63-6: Reserved
1020 };
1021} ERROR_PCI_COMPONENT_VALID, *PERROR_PCI_COMPONENT_VALID;
1022
1023typedef struct _ERROR_PCI_COMPONENT_INFO { // Bytes:
1024 USHORT VendorId; // 0-1: Vendor Identifier
1025 USHORT DeviceId; // 2-3: Device Identifier
1026 UCHAR ClassCodeInterface; // 4: Class Code.Interface field
1027 UCHAR ClassCodeSubClass; // 5: Class Code.SubClass field
1028 UCHAR ClassCodeBaseClass; // 6: Class Code.BaseClass field
1029 UCHAR FunctionNumber; // 7: Function Number
1030 UCHAR DeviceNumber; // 8: Device Number
1031 UCHAR BusNumber; // 9: Bus Number
1032 UCHAR SegmentNumber; // 10: Segment Number
1033 UCHAR Reserved0;
1034 ULONG Reserved1;
1035} ERROR_PCI_COMPONENT_INFO, *PERROR_PCI_COMPONENT_INFO;
1036
1037typedef struct _ERROR_PCI_COMPONENT {
1038 ERROR_SECTION_HEADER Header;
1039 ERROR_PCI_COMPONENT_VALID Valid;
1040 ERROR_STATUS ErrorStatus; // Component Error Status
1041 ERROR_PCI_COMPONENT_INFO Info; // Component Information
1042 ULONG MemoryMappedRegistersPairs; // Number of Memory Mapped Registers Pairs
1043 ULONG ProgrammedIORegistersPairs; // Number of Programmed IO Registers Pairs
1044#if 0
1045 ULONGLONG RegistersPairs[/* 2 * (MemoryMappedRegistersPairs + ProgrammedIORegistersPairs) */];
1046 ERROR_OEM_DATA OemData;
1047#endif // 0
1048 } ERROR_PCI_COMPONENT, *PERROR_PCI_COMPONENT;
1049
1050//
1051// IA64 ERRORS: Platform ERROR_SYSTEM_EVENT_LOG device definitions
1052//
1053// With reference to the IPMI System Event Log.
1054//
1055
1056#define ERROR_SYSTEM_EVENT_LOG_GUID \
1057 { 0xe429faf3, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 }}
1058
1059typedef union _ERROR_SYSTEM_EVENT_LOG_VALID {
1060 ULONGLONG Valid;
1061 struct { // Bits
1062 ULONGLONG RecordId:1; // 0: Record Identifier valid bit
1063 ULONGLONG RecordType:1; // 1: Record Type valid bit
1064 ULONGLONG GeneratorId:1; // 2: Generator Identifier valid bit
1065 ULONGLONG EVMRev:1; // 3: Event Format Revision valid bit
1066 ULONGLONG SensorType:1; // 4: Sensor Type valid bit
1067 ULONGLONG SensorNum:1; // 5: Sensor Number valid bit
1068 ULONGLONG EventDirType:1; // 6: Event Dir valid bit
1069 ULONGLONG EventData1:1; // 7: Event Data1 valid bit
1070 ULONGLONG EventData2:1; // 8: Event Data2 valid bit
1071 ULONGLONG EventData3:1; // 9: Event Data3 valid bit
1072 ULONGLONG Reserved:54; // 10-63:
1073 };
1074} ERROR_SYSTEM_EVENT_LOG_VALID, *PSYSTEM_EVENT_LOG_VALID;
1075
1076typedef struct _ERROR_SYSTEM_EVENT_LOG {
1077 ERROR_SECTION_HEADER Header;
1078 ERROR_SYSTEM_EVENT_LOG_VALID Valid;
1079 USHORT RecordId; // Record Identifier used for SEL record access
1080 UCHAR RecordType; // Record Type:
1081 // 0x02 - System Event Record
1082 // 0xC0 - 0xDF OEM time stamped, bytes 8-16 OEM defined
1083 // 0xE0 - 0xFF OEM non-time stamped, bytes 4-16 OEM defined
1084 ULONG TimeStamp; // Time stamp of the event log
1085 USHORT GeneratorId; // Software ID if event was generated by software
1086 // Byte 1:
1087 // Bit 0 - set to 1 when using system software
1088 // Bit 7:1 - 7-bit system ID
1089 // Byte 2:
1090 // Bit 1:0 - IPMB device LUN if byte 1 holds slave
1091 // address, 0x0 otherwise
1092 // Bit 7:2 - Reserved.
1093 UCHAR EVMRevision; // Error message format version
1094 UCHAR SensorType; // Sensor Type code of the sensor that generated event
1095 UCHAR SensorNumber; // Number of the sensor that generated event
1096 UCHAR EventDir; // Event Dir
1097 // Bit 7 - 0: asserted, 1: desasserted
1098 // Event Type
1099 // Bit 6:0 - Event Type code
1100 UCHAR Data1; // Event data field
1101 UCHAR Data2; // Event data field
1102 UCHAR Data3; // Event data field
1103} ERROR_SYSTEM_EVENT_LOG, *PERROR_SYSTEM_EVENT_LOG;
1104
1105//
1106// IA64 ERRORS: Platform ERROR_SMBIOS device definitions
1107//
1108// With reference to the SMBIOS Specifications.
1109//
1110
1111#define ERROR_SMBIOS_GUID \
1112 { 0xe429faf5, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 }}
1113
1114typedef union _ERROR_SMBIOS_VALID {
1115 ULONGLONG Valid;
1116 struct { // Bits
1117 ULONGLONG EventType:1; // 0: Event Type valid bit
1118 ULONGLONG Length:1; // 1: Length valid bit
1119 ULONGLONG TimeStamp:1; // 2: Time Stamp valid bit
1120 ULONGLONG OemData:1; // 3: Data valid bit
1121 ULONGLONG Reserved:60; // 4-63:
1122 };
1123} ERROR_SMBIOS_VALID, *PERROR_SMBIOS_VALID;
1124
1125//
1126// ERROR_SMBIOS.Type definitions
1127//
1128
1129typedef UCHAR ERROR_SMBIOS_EVENT_TYPE, *PERROR_SMBIOS_EVENT_TYPE;
1130// enum values defined in SMBIOS 2.3 - 3.3.16.6.1
1131
1132typedef struct _ERROR_SMBIOS {
1133 ERROR_SECTION_HEADER Header;
1134 ERROR_SMBIOS_VALID Valid;
1135 ERROR_SMBIOS_EVENT_TYPE EventType; // Event Type
1136 UCHAR Length; // Length of the error information in bytes
1137 ERROR_TIMESTAMP TimeStamp; // Event Time Stamp
1138 ERROR_OEM_DATA OemData; // Optional data validated by SMBIOS.Valid.Data.
1139} ERROR_SMBIOS, *PERROR_SMBIOS;
1140
1141//
1142// IA64 ERRORS: Platform Specific error device definitions
1143//
1144
1145#define ERROR_PLATFORM_SPECIFIC_GUID \
1146 { 0xe429faf7, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 }}
1147
1148typedef union _ERROR_PLATFORM_SPECIFIC_VALID {
1149 ULONGLONG Valid;
1150 struct { // Bits:
1151 ULONGLONG ErrorStatus:1; // 0: Error Status valid bit
1152 ULONGLONG RequestorId:1; // 1: Requestor Identifier valid bit
1153 ULONGLONG ResponderId:1; // 2: Responder Identifier valid bit
1154 ULONGLONG TargetId:1; // 3: Target Identifier valid bit
1155 ULONGLONG BusSpecificData:1; // 4: Bus Specific Data valid bit
1156 ULONGLONG OemId:1; // 5: OEM Identification valid bit
1157 ULONGLONG OemData:1; // 6: OEM Data valid bit
1158 ULONGLONG OemDevicePath:1; // 7: OEM Device Path valid bit
1159 ULONGLONG Reserved:56; // 63-8: Reserved
1160 };
1161} ERROR_PLATFORM_SPECIFIC_VALID, *PERROR_PLATFORM_SPECIFIC_VALID;
1162
1163typedef struct _ERROR_PLATFORM_SPECIFIC {
1164 ERROR_SECTION_HEADER Header;
1165 ERROR_PLATFORM_SPECIFIC_VALID Valid;
1166 ERROR_STATUS ErrorStatus; // Platform Generic Error Status
1167 ULONGLONG RequestorId; // Bus Requestor ID at the time of the event
1168 ULONGLONG ResponderId; // Bus Responder ID at the time of the event
1169 ULONGLONG TargetId; // Bus intended Target ID at the time of the event
1170 ERROR_BUS_SPECIFIC_DATA BusSpecificData; // OEM specific Bus dependent data
1171 UCHAR OemId[16]; // OEM specific data for bus identification
1172 ERROR_OEM_DATA OemData; // OEM specific data
1173#if 0
1174 UCHAR OemDevicePath[/* 16 ? */]; // OEM specific vendor device path.
1175#endif // 0
1176 } ERROR_PLATFORM_SPECIFIC, *PERROR_PLATFORM_SPECIFIC;
1177
1178//
1179// IA64 ERRORS: Platform Bus error device definitions
1180//
1181
1182#define ERROR_PLATFORM_BUS_GUID \
1183 { 0xe429faf9, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 }}
1184
1185typedef union _ERROR_PLATFORM_BUS_VALID {
1186 ULONGLONG Valid;
1187 struct { // Bits:
1188 ULONGLONG ErrorStatus:1; // 0: Error Status valid bit
1189 ULONGLONG RequestorId:1; // 1: Requestor Identifier valid bit
1190 ULONGLONG ResponderId:1; // 2: Responder Identifier valid bit
1191 ULONGLONG TargetId:1; // 3: Target Identifier valid bit
1192 ULONGLONG BusSpecificData:1; // 4: Bus Specific Data valid bit
1193 ULONGLONG OemId:1; // 5: OEM Identification valid bit
1194 ULONGLONG OemData:1; // 6: OEM Data valid bit
1195 ULONGLONG OemDevicePath:1; // 7: OEM Device Path valid bit
1196 ULONGLONG Reserved:56; // 63-8: Reserved
1197 };
1198} ERROR_PLATFORM_BUS_VALID, *PERROR_PLATFORM_BUS_VALID;
1199
1200typedef struct _ERROR_PLATFORM_BUS {
1201 ERROR_SECTION_HEADER Header;
1202 ERROR_PLATFORM_BUS_VALID Valid;
1203 ERROR_STATUS ErrorStatus; // Bus Error Status
1204 ULONGLONG RequestorId; // Bus Requestor ID at the time of the event
1205 ULONGLONG ResponderId; // Bus Responder ID at the time of the event
1206 ULONGLONG TargetId; // Bus intended Target ID at the time of the event
1207 ERROR_BUS_SPECIFIC_DATA BusSpecificData; // OEM specific Bus dependent data
1208 UCHAR OemId[16]; // OEM specific data for bus identification
1209 ERROR_OEM_DATA OemData; // OEM specific data
1210#if 0
1211 UCHAR OemDevicePath[/* 16 ? */]; // OEM specific vendor device path.
1212#endif // 0
1213 } ERROR_PLATFORM_BUS, *PERROR_PLATFORM_BUS;
1214
1215//
1216// IA64 ERRORS: Platform Host Controller error device definitions
1217//
1218
1219#define ERROR_PLATFORM_HOST_CONTROLLER_GUID \
1220 { 0xe429faf8, 0x3cb7, 0x11d4, { 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 }}
1221
1222
1223typedef union _ERROR_PLATFORM_HOST_CONTROLLER_VALID {
1224 ULONGLONG Valid;
1225 struct { // Bits:
1226 ULONGLONG ErrorStatus:1; // 0: Error Status valid bit
1227 ULONGLONG RequestorId:1; // 1: Requestor Identifier valid bit
1228 ULONGLONG ResponderId:1; // 2: Responder Identifier valid bit
1229 ULONGLONG TargetId:1; // 3: Target Identifier valid bit
1230 ULONGLONG BusSpecificData:1; // 4: Bus Specific Data valid bit
1231 ULONGLONG OemId:1; // 5: OEM Identification valid bit
1232 ULONGLONG OemData:1; // 6: OEM Data valid bit
1233 ULONGLONG OemDevicePath:1; // 7: OEM Device Path valid bit
1234 ULONGLONG Reserved:56; // 63-8: Reserved
1235 };
1236} ERROR_PLATFORM_HOST_CONTROLLER_VALID, *PERROR_PLATFORM_HOST_CONTROLLER_VALID;
1237
1238typedef struct _ERROR_PLATFORM_HOST_CONTROLLER {
1239 ERROR_SECTION_HEADER Header;
1240 ERROR_PCI_COMPONENT_VALID Valid;
1241 ERROR_STATUS ErrorStatus; // Host Controller Error Status
1242 ULONGLONG RequestorId; // Host controller Requestor ID at the time of the event
1243 ULONGLONG ResponderId; // Host controller Responder ID at the time of the event
1244 ULONGLONG TargetId; // Host controller intended Target ID at the time of the event
1245 ERROR_BUS_SPECIFIC_DATA BusSpecificData; // OEM specific Bus dependent data
1246 UCHAR OemId[16]; // OEM specific data for bus identification
1247 ERROR_OEM_DATA OemData; // OEM specific data
1248#if 0
1249 UCHAR OemDevicePath[/* 16 ? */]; // OEM specific vendor device path.
1250#endif // 0
1251} ERROR_PLATFORM_HOST_CONTROLLER, *PERROR_PLATFORM_HOST_CONTROLLER;
1252
1253//
1254// IA64 ERROR_LOGRECORDS definitions
1255//
1256// MCA_EXCEPTION,
1257// CMC_EXCEPTION,
1258// CPE_EXCEPTION.
1259//
1260
1261// For compatibility with previous versions of the definitions:
1262typedef ERROR_RECORD_HEADER ERROR_LOGRECORD, *PERROR_LOGRECORD;
1263
1264typedef ERROR_RECORD_HEADER MCA_EXCEPTION, *PMCA_EXCEPTION; // Machine Check Abort
1265typedef ERROR_RECORD_HEADER CMC_EXCEPTION, *PCMC_EXCEPTION; // Corrected Machine Check
1266typedef ERROR_RECORD_HEADER CPE_EXCEPTION, *PCPE_EXCEPTION; // Corrected Platform Error
1267
1268#endif // _IA64_
1269
1270#endif // defined(_X86_) || defined(_IA64_) || defined(_AMD64_)
1271
1272#endif // _MCE_
1273
1274
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