VirtualBox

source: vbox/trunk/include/iprt/x86.mac@ 68862

Last change on this file since 68862 was 66604, checked in by vboxsync, 8 years ago

VMM: Nested Hw.virt: SVM bits.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 48.9 KB
Line 
1%ifndef ___iprt_x86_h
2%define ___iprt_x86_h
3%ifndef VBOX_FOR_DTRACE_LIB
4%else
5%endif
6%ifdef RT_OS_SOLARIS
7%endif
8%ifndef VBOX_FOR_DTRACE_LIB
9%endif
10%ifndef VBOX_FOR_DTRACE_LIB
11%endif
12%ifndef VBOX_FOR_DTRACE_LIB
13%endif
14%define X86_EFL_CF RT_BIT_32(0)
15%define X86_EFL_CF_BIT 0
16%define X86_EFL_1 RT_BIT_32(1)
17%define X86_EFL_PF RT_BIT_32(2)
18%define X86_EFL_AF RT_BIT_32(4)
19%define X86_EFL_AF_BIT 4
20%define X86_EFL_ZF RT_BIT_32(6)
21%define X86_EFL_ZF_BIT 6
22%define X86_EFL_SF RT_BIT_32(7)
23%define X86_EFL_SF_BIT 7
24%define X86_EFL_TF RT_BIT_32(8)
25%define X86_EFL_IF RT_BIT_32(9)
26%define X86_EFL_DF RT_BIT_32(10)
27%define X86_EFL_OF RT_BIT_32(11)
28%define X86_EFL_OF_BIT 11
29%define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
30%define X86_EFL_NT RT_BIT_32(14)
31%define X86_EFL_RF RT_BIT_32(16)
32%define X86_EFL_VM RT_BIT_32(17)
33%define X86_EFL_AC RT_BIT_32(18)
34%define X86_EFL_VIF RT_BIT_32(19)
35%define X86_EFL_VIP RT_BIT_32(20)
36%define X86_EFL_ID RT_BIT_32(21)
37%define X86_EFL_LIVE_MASK 0x003f7fd5
38%define X86_EFL_RA1_MASK RT_BIT_32(1)
39%define X86_EFL_IOPL_SHIFT 12
40%define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
41%define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
42 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
43%define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
44 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
45%define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
46%ifndef VBOX_FOR_DTRACE_LIB
47%else
48%endif
49%ifndef VBOX_FOR_DTRACE_LIB
50%else
51%endif
52%define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547
53%define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e
54%define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69
55%define X86_CPUID_VENDOR_AMD_EBX 0x68747541
56%define X86_CPUID_VENDOR_AMD_ECX 0x444d4163
57%define X86_CPUID_VENDOR_AMD_EDX 0x69746e65
58%define X86_CPUID_VENDOR_VIA_EBX 0x746e6543
59%define X86_CPUID_VENDOR_VIA_ECX 0x736c7561
60%define X86_CPUID_VENDOR_VIA_EDX 0x48727561
61%define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
62%define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
63%define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
64%define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
65%define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
66%define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
67%define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
68%define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
69%define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
70%define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
71%define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
72%define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
73%define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
74%define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
75%define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
76%define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
77%define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
78%define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
79%define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
80%define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
81%define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
82%define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
83%define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
84%define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
85%define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
86%define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
87%define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
88%define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
89%define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
90%define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
91%define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
92%define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
93%define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
94%define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
95%define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
96%define X86_CPUID_FEATURE_EDX_PSE_BIT 3
97%define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
98%define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
99%define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
100%define X86_CPUID_FEATURE_EDX_PAE_BIT 6
101%define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
102%define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
103%define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
104%define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
105%define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
106%define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
107%define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
108%define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
109%define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
110%define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
111%define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
112%define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
113%define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
114%define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
115%define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
116%define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
117%define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
118%define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
119%define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
120%define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
121%define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
122%define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
123%define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
124%define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
125%define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
126%define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
127%define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
128%define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
129%define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
130%define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
131%define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
132%define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
133%define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
134%define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
135%define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
136%define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
137%define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
138%define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
139%define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
140%define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
141%define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
142%define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
143%define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
144%define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
145%define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
146%define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
147%define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
148%define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
149%define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
150%define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
151%define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
152%define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
153%define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
154%define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
155%define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
156%define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
157%define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
158%define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
159%define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
160%define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
161%define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
162%define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
163%define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
164%define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
165%define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
166%define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
167%define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
168%define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
169%define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
170%define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
171%define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
172%define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
173%define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
174%define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
175%define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
176%define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
177%define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
178%define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
179%define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
180%define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
181%define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
182%define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
183%define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
184%define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
185%define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
186%define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
187%define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
188%define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
189%define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
190%define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
191%define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
192%define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
193%define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
194%define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
195%define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
196%define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
197%define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
198%define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
199%define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
200%define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
201%define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
202%define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
203%define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
204%define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
205%define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
206%define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
207%define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
208%define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
209%define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
210%define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
211%define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
212%define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
213%define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
214%define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
215%define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
216%define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
217%define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
218%define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST RT_BIT(7)
219%define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
220%define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
221%define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
222%define X86_CR0_PE RT_BIT_32(0)
223%define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
224%define X86_CR0_MP RT_BIT_32(1)
225%define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
226%define X86_CR0_EM RT_BIT_32(2)
227%define X86_CR0_EMULATE_FPU RT_BIT_32(2)
228%define X86_CR0_TS RT_BIT_32(3)
229%define X86_CR0_TASK_SWITCH RT_BIT_32(3)
230%define X86_CR0_ET RT_BIT_32(4)
231%define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
232%define X86_CR0_NE RT_BIT_32(5)
233%define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
234%define X86_CR0_WP RT_BIT_32(16)
235%define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
236%define X86_CR0_AM RT_BIT_32(18)
237%define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
238%define X86_CR0_NW RT_BIT_32(29)
239%define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
240%define X86_CR0_CD RT_BIT_32(30)
241%define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
242%define X86_CR0_PG RT_BIT_32(31)
243%define X86_CR0_PAGING RT_BIT_32(31)
244%define X86_CR3_PWT RT_BIT_32(3)
245%define X86_CR3_PCD RT_BIT_32(4)
246%define X86_CR3_PAGE_MASK (0xfffff000)
247%define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
248%define X86_CR3_AMD64_PAGE_MASK 0x000ffffffffff000
249%define X86_CR4_VME RT_BIT_32(0)
250%define X86_CR4_PVI RT_BIT_32(1)
251%define X86_CR4_TSD RT_BIT_32(2)
252%define X86_CR4_DE RT_BIT_32(3)
253%define X86_CR4_PSE RT_BIT_32(4)
254%define X86_CR4_PAE RT_BIT_32(5)
255%define X86_CR4_MCE RT_BIT_32(6)
256%define X86_CR4_PGE RT_BIT_32(7)
257%define X86_CR4_PCE RT_BIT_32(8)
258%define X86_CR4_OSFXSR RT_BIT_32(9)
259%define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
260%define X86_CR4_VMXE RT_BIT_32(13)
261%define X86_CR4_SMXE RT_BIT_32(14)
262%define X86_CR4_PCIDE RT_BIT_32(17)
263%define X86_CR4_OSXSAVE RT_BIT_32(18)
264%define X86_CR4_SMEP RT_BIT_32(20)
265%define X86_CR4_SMAP RT_BIT_32(21)
266%define X86_CR4_PKE RT_BIT_32(22)
267%define X86_DR6_B0 RT_BIT_32(0)
268%define X86_DR6_B1 RT_BIT_32(1)
269%define X86_DR6_B2 RT_BIT_32(2)
270%define X86_DR6_B3 RT_BIT_32(3)
271%define X86_DR6_B_MASK 0x0000000f
272%define X86_DR6_BD RT_BIT_32(13)
273%define X86_DR6_BS RT_BIT_32(14)
274%define X86_DR6_BT RT_BIT_32(15)
275%define X86_DR6_INIT_VAL 0xFFFF0FF0
276%define X86_DR6_RA1_MASK 0xffff0ff0
277%define X86_DR6_RAZ_MASK RT_BIT_64(12)
278%define X86_DR6_MBZ_MASK 0xffffffff00000000
279%define X86_DR6_B(iBp) RT_BIT_64(iBp)
280%define X86_DR7_L0 RT_BIT_32(0)
281%define X86_DR7_G0 RT_BIT_32(1)
282%define X86_DR7_L1 RT_BIT_32(2)
283%define X86_DR7_G1 RT_BIT_32(3)
284%define X86_DR7_L2 RT_BIT_32(4)
285%define X86_DR7_G2 RT_BIT_32(5)
286%define X86_DR7_L3 RT_BIT_32(6)
287%define X86_DR7_G3 RT_BIT_32(7)
288%define X86_DR7_LE RT_BIT_32(8)
289%define X86_DR7_GE RT_BIT_32(9)
290%define X86_DR7_LE_ALL 0x0000000000000055
291%define X86_DR7_GE_ALL 0x00000000000000aa
292%define X86_DR7_ICE_IR RT_BIT_32(12)
293%define X86_DR7_GD RT_BIT_32(13)
294%define X86_DR7_ICE_TR1 RT_BIT_32(14)
295%define X86_DR7_ICE_TR2 RT_BIT_32(15)
296%define X86_DR7_RW0_MASK (3 << 16)
297%define X86_DR7_LEN0_MASK (3 << 18)
298%define X86_DR7_RW1_MASK (3 << 20)
299%define X86_DR7_LEN1_MASK (3 << 22)
300%define X86_DR7_RW2_MASK (3 << 24)
301%define X86_DR7_LEN2_MASK (3 << 26)
302%define X86_DR7_RW3_MASK (3 << 28)
303%define X86_DR7_LEN3_MASK (3 << 30)
304%define X86_DR7_RA1_MASK RT_BIT_32(10)
305%define X86_DR7_RAZ_MASK 0x0000d800
306%define X86_DR7_MBZ_MASK 0xffffffff00000000
307%define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
308%define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
309%define X86_DR7_L_G(iBp) ( 3 << (iBp * 2) )
310%define X86_DR7_RW_EO 0
311%define X86_DR7_RW_WO 1
312%define X86_DR7_RW_IO 2
313%define X86_DR7_RW_RW 3
314%define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
315%define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & 3 )
316%define X86_DR7_RW_ALL_MASKS 0x33330000
317%ifndef VBOX_FOR_DTRACE_LIB
318 %define X86_DR7_ANY_RW_IO(uDR7) \
319 ( ( 0x22220000 & (uDR7) )
320%endif
321%define X86_DR7_LEN_BYTE 0
322%define X86_DR7_LEN_WORD 1
323%define X86_DR7_LEN_QWORD 2
324%define X86_DR7_LEN_DWORD 3
325%define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
326%define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3 )
327%define X86_DR7_ENABLED_MASK 0x000000ff
328%define X86_DR7_LEN_ALL_MASKS 0xcccc0000
329%define X86_DR7_RW_LEN_ALL_MASKS 0xffff0000
330%define X86_DR7_INIT_VAL 0x400
331%define MSR_P5_MC_ADDR 0x00000000
332%define MSR_P5_MC_TYPE 0x00000001
333%define MSR_IA32_TSC 0x10
334%define MSR_IA32_CESR 0x00000011
335%define MSR_IA32_CTR0 0x00000012
336%define MSR_IA32_CTR1 0x00000013
337%define MSR_IA32_PLATFORM_ID 0x17
338%ifndef MSR_IA32_APICBASE
339 %define MSR_IA32_APICBASE 0x1b
340 %define MSR_IA32_APICBASE_EN RT_BIT_64(11)
341 %define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
342 %define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
343 %define MSR_IA32_APICBASE_BASE_MIN 0x0000000ffffff000
344 %define MSR_IA32_APICBASE_ADDR 0x00000000fee00000
345 %define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
346%endif
347%define MSR_CORE_THREAD_COUNT 0x35
348%define MSR_IA32_FEATURE_CONTROL 0x3A
349%define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_32(0)
350%define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_32(1)
351%define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_32(2)
352%define MSR_IA32_TSC_ADJUST 0x3B
353%define MSR_IA32_BIOS_UPDT_TRIG 0x79
354%define MSR_IA32_BIOS_SIGN_ID 0x8B
355%define MSR_IA32_SMM_MONITOR_CTL 0x9B
356%define MSR_IA32_PMC0 0xC1
357%define MSR_IA32_PMC1 0xC2
358%define MSR_IA32_PMC2 0xC3
359%define MSR_IA32_PMC3 0xC4
360%define MSR_IA32_PLATFORM_INFO 0xCE
361%define MSR_IA32_FSB_CLOCK_STS 0xCD
362%define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
363%define MSR_IA32_MPERF 0xE7
364%define MSR_IA32_APERF 0xE8
365%define MSR_IA32_MTRR_CAP 0xFE
366%define MSR_BBL_CR_CTL3 0x11e
367%ifndef MSR_IA32_SYSENTER_CS
368%define MSR_IA32_SYSENTER_CS 0x174
369%define MSR_IA32_SYSENTER_ESP 0x175
370%define MSR_IA32_SYSENTER_EIP 0x176
371%endif
372%define MSR_IA32_MCG_CAP 0x179
373%define MSR_IA32_MCG_STATUS 0x17A
374%define MSR_IA32_MCG_CTRL 0x17B
375%define MSR_IA32_CR_PAT 0x277
376%define MSR_IA32_PERFEVTSEL0 0x186
377%define MSR_IA32_PERFEVTSEL1 0x187
378%define MSR_FLEX_RATIO 0x194
379%define MSR_IA32_PERF_STATUS 0x198
380%define MSR_IA32_PERF_CTL 0x199
381%define MSR_IA32_THERM_STATUS 0x19c
382%define MSR_IA32_MISC_ENABLE 0x1A0
383%define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
384%define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
385%define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
386%define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
387%define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
388%define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
389%define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
390%define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
391%define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
392%define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
393%define MSR_IA32_DEBUGCTL 0x000001d9
394%define MSR_P4_LASTBRANCH_TOS 0x000001da
395%define MSR_P4_LASTBRANCH_0 0x000001db
396%define MSR_P4_LASTBRANCH_1 0x000001dc
397%define MSR_P4_LASTBRANCH_2 0x000001dd
398%define MSR_P4_LASTBRANCH_3 0x000001de
399%define IA32_MTRR_PHYSBASE0 0x200
400%define IA32_MTRR_PHYSMASK0 0x201
401%define IA32_MTRR_PHYSBASE1 0x202
402%define IA32_MTRR_PHYSMASK1 0x203
403%define IA32_MTRR_PHYSBASE2 0x204
404%define IA32_MTRR_PHYSMASK2 0x205
405%define IA32_MTRR_PHYSBASE3 0x206
406%define IA32_MTRR_PHYSMASK3 0x207
407%define IA32_MTRR_PHYSBASE4 0x208
408%define IA32_MTRR_PHYSMASK4 0x209
409%define IA32_MTRR_PHYSBASE5 0x20a
410%define IA32_MTRR_PHYSMASK5 0x20b
411%define IA32_MTRR_PHYSBASE6 0x20c
412%define IA32_MTRR_PHYSMASK6 0x20d
413%define IA32_MTRR_PHYSBASE7 0x20e
414%define IA32_MTRR_PHYSMASK7 0x20f
415%define IA32_MTRR_PHYSBASE8 0x210
416%define IA32_MTRR_PHYSMASK8 0x211
417%define IA32_MTRR_PHYSBASE9 0x212
418%define IA32_MTRR_PHYSMASK9 0x213
419%define IA32_MTRR_FIX64K_00000 0x250
420%define IA32_MTRR_FIX16K_80000 0x258
421%define IA32_MTRR_FIX16K_A0000 0x259
422%define IA32_MTRR_FIX4K_C0000 0x268
423%define IA32_MTRR_FIX4K_C8000 0x269
424%define IA32_MTRR_FIX4K_D0000 0x26a
425%define IA32_MTRR_FIX4K_D8000 0x26b
426%define IA32_MTRR_FIX4K_E0000 0x26c
427%define IA32_MTRR_FIX4K_E8000 0x26d
428%define IA32_MTRR_FIX4K_F0000 0x26e
429%define IA32_MTRR_FIX4K_F8000 0x26f
430%define MSR_IA32_MTRR_DEF_TYPE 0x2FF
431%define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
432%define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
433%define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
434%define MSR_IA32_PEBS_ENABLE 0x3F1
435%define MSR_IA32_MC0_CTL 0x400
436%define MSR_IA32_MC0_STATUS 0x401
437%define MSR_IA32_VMX_BASIC_INFO 0x480
438%define MSR_IA32_VMX_PINBASED_CTLS 0x481
439%define MSR_IA32_VMX_PROCBASED_CTLS 0x482
440%define MSR_IA32_VMX_EXIT_CTLS 0x483
441%define MSR_IA32_VMX_ENTRY_CTLS 0x484
442%define MSR_IA32_VMX_MISC 0x485
443%define MSR_IA32_VMX_CR0_FIXED0 0x486
444%define MSR_IA32_VMX_CR0_FIXED1 0x487
445%define MSR_IA32_VMX_CR4_FIXED0 0x488
446%define MSR_IA32_VMX_CR4_FIXED1 0x489
447%define MSR_IA32_VMX_VMCS_ENUM 0x48A
448%define MSR_IA32_VMX_VMFUNC 0x491
449%define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
450%define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
451%define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
452%define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
453%define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
454%define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
455%define MSR_IA32_DS_AREA 0x600
456%define MSR_RAPL_POWER_UNIT 0x606
457%define MSR_IA32_X2APIC_START 0x800
458%define MSR_IA32_X2APIC_ID 0x802
459%define MSR_IA32_X2APIC_VERSION 0x803
460%define MSR_IA32_X2APIC_TPR 0x808
461%define MSR_IA32_X2APIC_PPR 0x80A
462%define MSR_IA32_X2APIC_EOI 0x80B
463%define MSR_IA32_X2APIC_LDR 0x80D
464%define MSR_IA32_X2APIC_SVR 0x80F
465%define MSR_IA32_X2APIC_ISR0 0x810
466%define MSR_IA32_X2APIC_ISR1 0x811
467%define MSR_IA32_X2APIC_ISR2 0x812
468%define MSR_IA32_X2APIC_ISR3 0x813
469%define MSR_IA32_X2APIC_ISR4 0x814
470%define MSR_IA32_X2APIC_ISR5 0x815
471%define MSR_IA32_X2APIC_ISR6 0x816
472%define MSR_IA32_X2APIC_ISR7 0x817
473%define MSR_IA32_X2APIC_TMR0 0x818
474%define MSR_IA32_X2APIC_TMR1 0x819
475%define MSR_IA32_X2APIC_TMR2 0x81A
476%define MSR_IA32_X2APIC_TMR3 0x81B
477%define MSR_IA32_X2APIC_TMR4 0x81C
478%define MSR_IA32_X2APIC_TMR5 0x81D
479%define MSR_IA32_X2APIC_TMR6 0x81E
480%define MSR_IA32_X2APIC_TMR7 0x81F
481%define MSR_IA32_X2APIC_IRR0 0x820
482%define MSR_IA32_X2APIC_IRR1 0x821
483%define MSR_IA32_X2APIC_IRR2 0x822
484%define MSR_IA32_X2APIC_IRR3 0x823
485%define MSR_IA32_X2APIC_IRR4 0x824
486%define MSR_IA32_X2APIC_IRR5 0x825
487%define MSR_IA32_X2APIC_IRR6 0x826
488%define MSR_IA32_X2APIC_IRR7 0x827
489%define MSR_IA32_X2APIC_ESR 0x828
490%define MSR_IA32_X2APIC_LVT_CMCI 0x82F
491%define MSR_IA32_X2APIC_ICR 0x830
492%define MSR_IA32_X2APIC_LVT_TIMER 0x832
493%define MSR_IA32_X2APIC_LVT_THERMAL 0x833
494%define MSR_IA32_X2APIC_LVT_PERF 0x834
495%define MSR_IA32_X2APIC_LVT_LINT0 0x835
496%define MSR_IA32_X2APIC_LVT_LINT1 0x836
497%define MSR_IA32_X2APIC_LVT_ERROR 0x837
498%define MSR_IA32_X2APIC_TIMER_ICR 0x838
499%define MSR_IA32_X2APIC_TIMER_CCR 0x839
500%define MSR_IA32_X2APIC_TIMER_DCR 0x83E
501%define MSR_IA32_X2APIC_SELF_IPI 0x83F
502%define MSR_IA32_X2APIC_END 0xBFF
503%define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
504%define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
505%define MSR_K6_EFER 0xc0000080
506%define MSR_K6_EFER_SCE RT_BIT_32(0)
507%define MSR_K6_EFER_LME RT_BIT_32(8)
508%define MSR_K6_EFER_LMA RT_BIT_32(10)
509%define MSR_K6_EFER_NXE RT_BIT_32(11)
510%define MSR_K6_EFER_BIT_NXE 11
511%define MSR_K6_EFER_SVME RT_BIT_32(12)
512%define MSR_K6_EFER_LMSLE RT_BIT_32(13)
513%define MSR_K6_EFER_FFXSR RT_BIT_32(14)
514%define MSR_K6_EFER_TCE RT_BIT_32(15)
515%define MSR_K6_STAR 0xc0000081
516%define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
517%define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
518%define MSR_K6_STAR_SEL_MASK 0xffff
519%define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
520%define MSR_K6_WHCR 0xc0000082
521%define MSR_K6_UWCCR 0xc0000085
522%define MSR_K6_PSOR 0xc0000087
523%define MSR_K6_PFIR 0xc0000088
524%define MSR_K7_EVNTSEL0 0xc0010000
525%define MSR_K7_EVNTSEL1 0xc0010001
526%define MSR_K7_EVNTSEL2 0xc0010002
527%define MSR_K7_EVNTSEL3 0xc0010003
528%define MSR_K7_PERFCTR0 0xc0010004
529%define MSR_K7_PERFCTR1 0xc0010005
530%define MSR_K7_PERFCTR2 0xc0010006
531%define MSR_K7_PERFCTR3 0xc0010007
532%define MSR_K8_LSTAR 0xc0000082
533%define MSR_K8_CSTAR 0xc0000083
534%define MSR_K8_SF_MASK 0xc0000084
535%define MSR_K8_FS_BASE 0xc0000100
536%define MSR_K8_GS_BASE 0xc0000101
537%define MSR_K8_KERNEL_GS_BASE 0xc0000102
538%define MSR_K8_TSC_AUX 0xc0000103
539%define MSR_K8_SYSCFG 0xc0010010
540%define MSR_K8_HWCR 0xc0010015
541%define MSR_K8_IORRBASE0 0xc0010016
542%define MSR_K8_IORRMASK0 0xc0010017
543%define MSR_K8_IORRBASE1 0xc0010018
544%define MSR_K8_IORRMASK1 0xc0010019
545%define MSR_K8_TOP_MEM1 0xc001001a
546%define MSR_K8_TOP_MEM2 0xc001001d
547%define MSR_K8_NB_CFG 0xc001001f
548%define MSR_K8_INT_PENDING 0xc0010055
549%define MSR_K8_VM_CR 0xc0010114
550%define MSR_K8_VM_CR_DPD RT_BIT_32(0)
551%define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
552%define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
553%define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
554%define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
555%define MSR_K8_IGNNE 0xc0010115
556%define MSR_K8_SMM_CTL 0xc0010116
557%define MSR_K8_VM_HSAVE_PA 0xc0010117
558%define X86_PG_ENTRIES 1024
559%define X86_PG_PAE_ENTRIES 512
560%define X86_PG_PAE_PDPE_ENTRIES 4
561%define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
562%define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
563%define X86_PAGE_SIZE X86_PAGE_4K_SIZE
564%define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
565%define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
566%define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
567%define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
568%define X86_PAGE_4K_SIZE _4K
569%define X86_PAGE_4K_SHIFT 12
570%define X86_PAGE_4K_OFFSET_MASK 0xfff
571%define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000
572%define X86_PAGE_4K_BASE_MASK_32 0xfffff000
573%define X86_PAGE_2M_SIZE _2M
574%define X86_PAGE_2M_SHIFT 21
575%define X86_PAGE_2M_OFFSET_MASK 0x001fffff
576%define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000
577%define X86_PAGE_2M_BASE_MASK_32 0xffe00000
578%define X86_PAGE_4M_SIZE _4M
579%define X86_PAGE_4M_SHIFT 22
580%define X86_PAGE_4M_OFFSET_MASK 0x003fffff
581%define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000
582%define X86_PAGE_4M_BASE_MASK_32 0xffc00000
583%define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + 0x800000000000 < UINT64_C(0x1000000000000))
584%define X86_PTE_BIT_P 0
585%define X86_PTE_BIT_RW 1
586%define X86_PTE_BIT_US 2
587%define X86_PTE_BIT_PWT 3
588%define X86_PTE_BIT_PCD 4
589%define X86_PTE_BIT_A 5
590%define X86_PTE_BIT_D 6
591%define X86_PTE_BIT_PAT 7
592%define X86_PTE_BIT_G 8
593%define X86_PTE_PAE_BIT_NX 63
594%define X86_PTE_P RT_BIT_32(0)
595%define X86_PTE_RW RT_BIT_32(1)
596%define X86_PTE_US RT_BIT_32(2)
597%define X86_PTE_PWT RT_BIT_32(3)
598%define X86_PTE_PCD RT_BIT_32(4)
599%define X86_PTE_A RT_BIT_32(5)
600%define X86_PTE_D RT_BIT_32(6)
601%define X86_PTE_PAT RT_BIT_32(7)
602%define X86_PTE_G RT_BIT_32(8)
603%define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
604%define X86_PTE_PG_MASK ( 0xfffff000 )
605%define X86_PTE_PAE_PG_MASK 0x000ffffffffff000
606%define X86_PTE_PAE_NX RT_BIT_64(63)
607%define X86_PTE_PAE_MBZ_MASK_NX 0x7ff0000000000000
608%define X86_PTE_PAE_MBZ_MASK_NO_NX 0xfff0000000000000
609%define X86_PTE_LM_MBZ_MASK_NX 0x0000000000000000
610%define X86_PTE_LM_MBZ_MASK_NO_NX 0x8000000000000000
611%ifndef VBOX_FOR_DTRACE_LIB
612%endif
613%ifndef VBOX_FOR_DTRACE_LIB
614%endif
615%ifndef VBOX_FOR_DTRACE_LIB
616%endif
617%ifndef VBOX_FOR_DTRACE_LIB
618%endif
619%ifndef VBOX_FOR_DTRACE_LIB
620%endif
621%define X86_PT_SHIFT 12
622%define X86_PT_MASK 0x3ff
623%ifndef VBOX_FOR_DTRACE_LIB
624%endif
625%define X86_PT_PAE_SHIFT 12
626%define X86_PT_PAE_MASK 0x1ff
627%define X86_PDE_P RT_BIT_32(0)
628%define X86_PDE_RW RT_BIT_32(1)
629%define X86_PDE_US RT_BIT_32(2)
630%define X86_PDE_PWT RT_BIT_32(3)
631%define X86_PDE_PCD RT_BIT_32(4)
632%define X86_PDE_A RT_BIT_32(5)
633%define X86_PDE_PS RT_BIT_32(7)
634%define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
635%define X86_PDE_PG_MASK ( 0xfffff000 )
636%define X86_PDE_PAE_PG_MASK 0x000ffffffffff000
637%define X86_PDE_PAE_NX RT_BIT_64(63)
638%define X86_PDE_PAE_MBZ_MASK_NX 0x7ff0000000000080
639%define X86_PDE_PAE_MBZ_MASK_NO_NX 0xfff0000000000080
640%define X86_PDE_LM_MBZ_MASK_NX 0x0000000000000080
641%define X86_PDE_LM_MBZ_MASK_NO_NX 0x8000000000000080
642%ifndef VBOX_FOR_DTRACE_LIB
643%endif
644%ifndef VBOX_FOR_DTRACE_LIB
645%endif
646%define X86_PDE4M_P RT_BIT_32(0)
647%define X86_PDE4M_RW RT_BIT_32(1)
648%define X86_PDE4M_US RT_BIT_32(2)
649%define X86_PDE4M_PWT RT_BIT_32(3)
650%define X86_PDE4M_PCD RT_BIT_32(4)
651%define X86_PDE4M_A RT_BIT_32(5)
652%define X86_PDE4M_D RT_BIT_32(6)
653%define X86_PDE4M_PS RT_BIT_32(7)
654%define X86_PDE4M_G RT_BIT_32(8)
655%define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
656%define X86_PDE4M_PAT RT_BIT_32(12)
657%define X86_PDE4M_PAT_SHIFT (12 - 7)
658%define X86_PDE4M_PG_MASK ( 0xffc00000 )
659%define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
660%define X86_PDE4M_PG_HIGH_SHIFT 19
661%define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
662%define X86_PDE2M_PAE_PG_MASK 0x000fffffffe00000
663%define X86_PDE2M_PAE_NX RT_BIT_64(63)
664%define X86_PDE2M_PAE_MBZ_MASK_NX 0x7ff00000001fe000
665%define X86_PDE2M_PAE_MBZ_MASK_NO_NX 0xfff00000001fe000
666%define X86_PDE2M_LM_MBZ_MASK_NX 0x00000000001fe000
667%define X86_PDE2M_LM_MBZ_MASK_NO_NX 0x80000000001fe000
668%ifndef VBOX_FOR_DTRACE_LIB
669%endif
670%ifndef VBOX_FOR_DTRACE_LIB
671%endif
672%ifndef VBOX_FOR_DTRACE_LIB
673%endif
674%ifndef VBOX_FOR_DTRACE_LIB
675%endif
676%ifndef VBOX_FOR_DTRACE_LIB
677%endif
678%define X86_PD_SHIFT 22
679%define X86_PD_MASK 0x3ff
680%ifndef VBOX_FOR_DTRACE_LIB
681%endif
682%define X86_PD_PAE_SHIFT 21
683%define X86_PD_PAE_MASK 0x1ff
684%define X86_PDPE_P RT_BIT_32(0)
685%define X86_PDPE_RW RT_BIT_32(1)
686%define X86_PDPE_US RT_BIT_32(2)
687%define X86_PDPE_PWT RT_BIT_32(3)
688%define X86_PDPE_PCD RT_BIT_32(4)
689%define X86_PDPE_A RT_BIT_32(5)
690%define X86_PDPE_LM_PS RT_BIT_32(7)
691%define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
692%define X86_PDPE_PG_MASK 0x000ffffffffff000
693%define X86_PDPE_PAE_MBZ_MASK 0xfff00000000001e6
694%define X86_PDPE_LM_NX RT_BIT_64(63)
695%define X86_PDPE_LM_MBZ_MASK_NX 0x0000000000000180
696%define X86_PDPE_LM_MBZ_MASK_NO_NX 0x8000000000000180
697%define X86_PDPE1G_LM_MBZ_MASK_NX 0x000000003fffe000
698%define X86_PDPE1G_LM_MBZ_MASK_NO_NX 0x800000003fffe000
699%ifndef VBOX_FOR_DTRACE_LIB
700%endif
701%ifndef VBOX_FOR_DTRACE_LIB
702%endif
703%ifndef VBOX_FOR_DTRACE_LIB
704%endif
705%ifndef VBOX_FOR_DTRACE_LIB
706%endif
707%ifndef VBOX_FOR_DTRACE_LIB
708%endif
709%define X86_PDPT_SHIFT 30
710%define X86_PDPT_MASK_PAE 0x3
711%define X86_PDPT_MASK_AMD64 0x1ff
712%define X86_PML4E_P RT_BIT_32(0)
713%define X86_PML4E_RW RT_BIT_32(1)
714%define X86_PML4E_US RT_BIT_32(2)
715%define X86_PML4E_PWT RT_BIT_32(3)
716%define X86_PML4E_PCD RT_BIT_32(4)
717%define X86_PML4E_A RT_BIT_32(5)
718%define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
719%define X86_PML4E_PG_MASK 0x000ffffffffff000
720%define X86_PML4E_MBZ_MASK_NX 0x0000000000000080
721%define X86_PML4E_MBZ_MASK_NO_NX 0x8000000000000080
722%define X86_PML4E_NX RT_BIT_64(63)
723%ifndef VBOX_FOR_DTRACE_LIB
724%endif
725%ifndef VBOX_FOR_DTRACE_LIB
726%endif
727%ifndef VBOX_FOR_DTRACE_LIB
728%endif
729%define X86_PML4_SHIFT 39
730%define X86_PML4_MASK 0x1ff
731%ifndef VBOX_FOR_DTRACE_LIB
732%endif
733%ifndef VBOX_FOR_DTRACE_LIB
734%endif
735%ifndef VBOX_FOR_DTRACE_LIB
736%endif
737%ifndef VBOX_FOR_DTRACE_LIB
738%endif
739%ifndef VBOX_FOR_DTRACE_LIB
740%endif
741%define X86_OFF_FXSTATE_RSVD 0x1d0
742%define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
743%ifndef VBOX_FOR_DTRACE_LIB
744%endif
745%define X86_FSW_IE RT_BIT_32(0)
746%define X86_FSW_DE RT_BIT_32(1)
747%define X86_FSW_ZE RT_BIT_32(2)
748%define X86_FSW_OE RT_BIT_32(3)
749%define X86_FSW_UE RT_BIT_32(4)
750%define X86_FSW_PE RT_BIT_32(5)
751%define X86_FSW_SF RT_BIT_32(6)
752%define X86_FSW_ES RT_BIT_32(7)
753%define X86_FSW_XCPT_MASK 0x007f
754%define X86_FSW_XCPT_ES_MASK 0x00ff
755%define X86_FSW_C0 RT_BIT_32(8)
756%define X86_FSW_C1 RT_BIT_32(9)
757%define X86_FSW_C2 RT_BIT_32(10)
758%define X86_FSW_TOP_MASK 0x3800
759%define X86_FSW_TOP_SHIFT 11
760%define X86_FSW_TOP_SMASK 0x0007
761%define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
762%define X86_FSW_C3 RT_BIT_32(14)
763%define X86_FSW_C_MASK 0x4700
764%define X86_FSW_B RT_BIT_32(15)
765%define X86_FCW_IM RT_BIT_32(0)
766%define X86_FCW_DM RT_BIT_32(1)
767%define X86_FCW_ZM RT_BIT_32(2)
768%define X86_FCW_OM RT_BIT_32(3)
769%define X86_FCW_UM RT_BIT_32(4)
770%define X86_FCW_PM RT_BIT_32(5)
771%define X86_FCW_MASK_ALL 0x007f
772%define X86_FCW_XCPT_MASK 0x003f
773%define X86_FCW_PC_MASK 0x0300
774%define X86_FCW_PC_24 0x0000
775%define X86_FCW_PC_RSVD 0x0100
776%define X86_FCW_PC_53 0x0200
777%define X86_FCW_PC_64 0x0300
778%define X86_FCW_RC_MASK 0x0c00
779%define X86_FCW_RC_NEAREST 0x0000
780%define X86_FCW_RC_DOWN 0x0400
781%define X86_FCW_RC_UP 0x0800
782%define X86_FCW_RC_ZERO 0x0c00
783%define X86_FCW_ZERO_MASK 0xf080
784%define X86_MXSCR_IE RT_BIT_32(0)
785%define X86_MXSCR_DE RT_BIT_32(1)
786%define X86_MXSCR_ZE RT_BIT_32(2)
787%define X86_MXSCR_OE RT_BIT_32(3)
788%define X86_MXSCR_UE RT_BIT_32(4)
789%define X86_MXSCR_PE RT_BIT_32(5)
790%define X86_MXSCR_DAZ RT_BIT_32(6)
791%define X86_MXSCR_IM RT_BIT_32(7)
792%define X86_MXSCR_DM RT_BIT_32(8)
793%define X86_MXSCR_ZM RT_BIT_32(9)
794%define X86_MXSCR_OM RT_BIT_32(10)
795%define X86_MXSCR_UM RT_BIT_32(11)
796%define X86_MXSCR_PM RT_BIT_32(12)
797%define X86_MXSCR_RC_MASK 0x6000
798%define X86_MXSCR_RC_NEAREST 0x0000
799%define X86_MXSCR_RC_DOWN 0x2000
800%define X86_MXSCR_RC_UP 0x4000
801%define X86_MXSCR_RC_ZERO 0x6000
802%define X86_MXSCR_FZ RT_BIT_32(15)
803%define X86_MXSCR_MM RT_BIT_32(17)
804%ifndef VBOX_FOR_DTRACE_LIB
805%endif
806%ifndef VBOX_FOR_DTRACE_LIB
807%endif
808%ifndef VBOX_FOR_DTRACE_LIB
809%endif
810%ifndef VBOX_FOR_DTRACE_LIB
811%endif
812%ifndef VBOX_FOR_DTRACE_LIB
813%endif
814%ifndef VBOX_FOR_DTRACE_LIB
815%endif
816%ifndef VBOX_FOR_DTRACE_LIB
817%endif
818%ifndef VBOX_FOR_DTRACE_LIB
819%endif
820%ifndef VBOX_FOR_DTRACE_LIB
821%endif
822%define XSAVE_C_X87_BIT 0
823%define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
824%define XSAVE_C_SSE_BIT 1
825%define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
826%define XSAVE_C_YMM_BIT 2
827%define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
828%define XSAVE_C_BNDREGS_BIT 3
829%define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
830%define XSAVE_C_BNDCSR_BIT 4
831%define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
832%define XSAVE_C_OPMASK_BIT 5
833%define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
834%define XSAVE_C_ZMM_HI256_BIT 6
835%define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
836%define XSAVE_C_ZMM_16HI_BIT 7
837%define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
838%define XSAVE_C_PKRU_BIT 9
839%define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
840%define XSAVE_C_LWP_BIT 62
841%define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
842%ifndef VBOX_FOR_DTRACE_LIB
843%endif
844%define X86DESCATTR_TYPE 0x0000000f
845%define X86DESCATTR_DT 0x00000010
846%define X86DESCATTR_DPL 0x00000060
847%define X86DESCATTR_DPL_SHIFT 5
848%define X86DESCATTR_P 0x00000080
849%define X86DESCATTR_LIMIT_HIGH 0x00000f00
850%define X86DESCATTR_AVL 0x00001000
851%define X86DESCATTR_L 0x00002000
852%define X86DESCATTR_D 0x00004000
853%define X86DESCATTR_G 0x00008000
854%define X86DESCATTR_UNUSABLE 0x00010000
855%ifndef VBOX_FOR_DTRACE_LIB
856%endif
857%ifndef VBOX_FOR_DTRACE_LIB
858%define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0)
859%define X86DESCGENERIC_BIT_OFF_BASE_LOW (16)
860%define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32)
861%define X86DESCGENERIC_BIT_OFF_TYPE (40)
862%define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44)
863%define X86DESCGENERIC_BIT_OFF_DPL (45)
864%define X86DESCGENERIC_BIT_OFF_PRESENT (47)
865%define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48)
866%define X86DESCGENERIC_BIT_OFF_AVAILABLE (52)
867%define X86DESCGENERIC_BIT_OFF_LONG (53)
868%define X86DESCGENERIC_BIT_OFF_DEF_BIG (54)
869%define X86DESCGENERIC_BIT_OFF_GRANULARITY (55)
870%define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56)
871%define X86LAR_F_TYPE 0x0f00
872%define X86LAR_F_DT 0x1000
873%define X86LAR_F_DPL 0x6000
874%define X86LAR_F_DPL_SHIFT 13
875%define X86LAR_F_P 0x8000
876%define X86LAR_F_AVL 0x00100000
877%define X86LAR_F_L 0x00200000
878%define X86LAR_F_D 0x00400000
879%define X86LAR_F_G 0x00800000
880%endif
881%ifndef VBOX_FOR_DTRACE_LIB
882%endif
883%ifndef VBOX_FOR_DTRACE_LIB
884%endif
885%ifndef VBOX_FOR_DTRACE_LIB
886%endif
887%ifndef VBOX_FOR_DTRACE_LIB
888%endif
889%ifndef VBOX_FOR_DTRACE_LIB
890%endif
891%if HC_ARCH_BITS == 64
892%else
893%endif
894%if HC_ARCH_BITS == 64
895%else
896%endif
897%if HC_ARCH_BITS == 64
898%else
899%endif
900%define X86_SEL_TYPE_CODE 8
901%define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
902%define X86_SEL_TYPE_ACCESSED 1
903%define X86_SEL_TYPE_DOWN 4
904%define X86_SEL_TYPE_CONF 4
905%define X86_SEL_TYPE_WRITE 2
906%define X86_SEL_TYPE_READ 2
907%define X86_SEL_TYPE_READ_BIT 1
908%define X86_SEL_TYPE_RO 0
909%define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
910%define X86_SEL_TYPE_RW 2
911%define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
912%define X86_SEL_TYPE_RO_DOWN 4
913%define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
914%define X86_SEL_TYPE_RW_DOWN 6
915%define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
916%define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
917%define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
918%define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
919%define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
920%define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
921%define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
922%define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
923%define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
924%define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
925%define X86_SEL_TYPE_SYS_UNDEFINED 0
926%define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
927%define X86_SEL_TYPE_SYS_LDT 2
928%define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
929%define X86_SEL_TYPE_SYS_286_CALL_GATE 4
930%define X86_SEL_TYPE_SYS_TASK_GATE 5
931%define X86_SEL_TYPE_SYS_286_INT_GATE 6
932%define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
933%define X86_SEL_TYPE_SYS_UNDEFINED2 8
934%define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
935%define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
936%define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
937%define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
938%define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
939%define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
940%define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
941%define AMD64_SEL_TYPE_SYS_LDT 2
942%define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
943%define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
944%define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
945%define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
946%define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
947%define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
948%define X86_DESC_S RT_BIT_32(12)
949%define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
950%define X86_DESC_P RT_BIT_32(15)
951%define X86_DESC_AVL RT_BIT_32(20)
952%define X86_DESC_DB RT_BIT_32(22)
953%define X86_DESC_G RT_BIT_32(23)
954%define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
955%define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
956%ifndef VBOX_FOR_DTRACE_LIB
957%endif
958%ifndef VBOX_FOR_DTRACE_LIB
959%endif
960%ifndef VBOX_FOR_DTRACE_LIB
961%endif
962%define X86_SEL_SHIFT 3
963%define X86_SEL_MASK 0xfff8
964%define X86_SEL_MASK_OFF_RPL 0xfffc
965%define X86_SEL_LDT 0x0004
966%define X86_SEL_RPL 0x0003
967%define X86_SEL_RPL_LDT 0x0007
968%define X86_XCPT_LAST 0x1f
969%define X86_TRAP_ERR_EXTERNAL 1
970%define X86_TRAP_ERR_IDT 2
971%define X86_TRAP_ERR_TI 4
972%define X86_TRAP_ERR_SEL_MASK 0xfff8
973%define X86_TRAP_ERR_SEL_SHIFT 3
974%define X86_TRAP_PF_P RT_BIT_32(0)
975%define X86_TRAP_PF_RW RT_BIT_32(1)
976%define X86_TRAP_PF_US RT_BIT_32(2)
977%define X86_TRAP_PF_RSVD RT_BIT_32(3)
978%define X86_TRAP_PF_ID RT_BIT_32(4)
979%define X86_TRAP_PF_PK RT_BIT_32(5)
980%ifndef VBOX_FOR_DTRACE_LIB
981%else
982%endif
983%ifndef VBOX_FOR_DTRACE_LIB
984%else
985%endif
986%define X86_MODRM_RM_MASK 0x07
987%define X86_MODRM_REG_MASK 0x38
988%define X86_MODRM_REG_SMASK 0x07
989%define X86_MODRM_REG_SHIFT 3
990%define X86_MODRM_MOD_MASK 0xc0
991%define X86_MODRM_MOD_SMASK 0x03
992%define X86_MODRM_MOD_SHIFT 6
993%ifndef VBOX_FOR_DTRACE_LIB
994 %define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
995%endif
996%define X86_SIB_BASE_MASK 0x07
997%define X86_SIB_INDEX_MASK 0x38
998%define X86_SIB_INDEX_SMASK 0x07
999%define X86_SIB_INDEX_SHIFT 3
1000%define X86_SIB_SCALE_MASK 0xc0
1001%define X86_SIB_SCALE_SMASK 0x03
1002%define X86_SIB_SCALE_SHIFT 6
1003%ifndef VBOX_FOR_DTRACE_LIB
1004%endif
1005%define X86_GREG_xAX 0
1006%define X86_GREG_xCX 1
1007%define X86_GREG_xDX 2
1008%define X86_GREG_xBX 3
1009%define X86_GREG_xSP 4
1010%define X86_GREG_xBP 5
1011%define X86_GREG_xSI 6
1012%define X86_GREG_xDI 7
1013%define X86_GREG_x8 8
1014%define X86_GREG_x9 9
1015%define X86_GREG_x10 10
1016%define X86_GREG_x11 11
1017%define X86_GREG_x12 12
1018%define X86_GREG_x13 13
1019%define X86_GREG_x14 14
1020%define X86_GREG_x15 15
1021%define X86_SREG_ES 0
1022%define X86_SREG_CS 1
1023%define X86_SREG_SS 2
1024%define X86_SREG_DS 3
1025%define X86_SREG_FS 4
1026%define X86_SREG_GS 5
1027%define X86_SREG_COUNT 6
1028%define X86_OP_PRF_CS 0x2e
1029%define X86_OP_PRF_SS 0x36
1030%define X86_OP_PRF_DS 0x3e
1031%define X86_OP_PRF_ES 0x26
1032%define X86_OP_PRF_FS 0x64
1033%define X86_OP_PRF_GS 0x65
1034%define X86_OP_PRF_SIZE_OP 0x66
1035%define X86_OP_PRF_SIZE_ADDR 0x67
1036%define X86_OP_PRF_LOCK 0xf0
1037%define X86_OP_PRF_REPZ 0xf3
1038%define X86_OP_PRF_REPNZ 0xf2
1039%define X86_OP_REX_B 0x41
1040%define X86_OP_REX_X 0x42
1041%define X86_OP_REX_R 0x44
1042%define X86_OP_REX_W 0x48
1043%endif
1044%include "iprt/x86extra.mac"
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette