VirtualBox

source: vbox/trunk/include/iprt/x86.mac@ 56454

Last change on this file since 56454 was 55254, checked in by vboxsync, 10 years ago

kmk incs
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 41.3 KB
Line 
1%ifndef ___iprt_x86_h
2%define ___iprt_x86_h
3%ifndef VBOX_FOR_DTRACE_LIB
4%else
5%endif
6%ifdef RT_OS_SOLARIS
7%endif
8%ifndef VBOX_FOR_DTRACE_LIB
9%endif
10%ifndef VBOX_FOR_DTRACE_LIB
11%endif
12%ifndef VBOX_FOR_DTRACE_LIB
13%endif
14%define X86_EFL_CF RT_BIT(0)
15%define X86_EFL_CF_BIT 0
16%define X86_EFL_1 RT_BIT(1)
17%define X86_EFL_PF RT_BIT(2)
18%define X86_EFL_AF RT_BIT(4)
19%define X86_EFL_AF_BIT 4
20%define X86_EFL_ZF RT_BIT(6)
21%define X86_EFL_ZF_BIT 6
22%define X86_EFL_SF RT_BIT(7)
23%define X86_EFL_SF_BIT 7
24%define X86_EFL_TF RT_BIT(8)
25%define X86_EFL_IF RT_BIT(9)
26%define X86_EFL_DF RT_BIT(10)
27%define X86_EFL_OF RT_BIT(11)
28%define X86_EFL_OF_BIT 11
29%define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
30%define X86_EFL_NT RT_BIT(14)
31%define X86_EFL_RF RT_BIT(16)
32%define X86_EFL_VM RT_BIT(17)
33%define X86_EFL_AC RT_BIT(18)
34%define X86_EFL_VIF RT_BIT(19)
35%define X86_EFL_VIP RT_BIT(20)
36%define X86_EFL_ID RT_BIT(21)
37%define X86_EFL_LIVE_MASK 0x003f7fd5
38%define X86_EFL_RA1_MASK RT_BIT_32(1)
39%define X86_EFL_IOPL_SHIFT 12
40%define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
41%define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
42 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
43%define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
44%ifndef VBOX_FOR_DTRACE_LIB
45%else
46%endif
47%ifndef VBOX_FOR_DTRACE_LIB
48%else
49%endif
50%define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547
51%define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e
52%define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69
53%define X86_CPUID_VENDOR_AMD_EBX 0x68747541
54%define X86_CPUID_VENDOR_AMD_ECX 0x444d4163
55%define X86_CPUID_VENDOR_AMD_EDX 0x69746e65
56%define X86_CPUID_VENDOR_VIA_EBX 0x746e6543
57%define X86_CPUID_VENDOR_VIA_ECX 0x736c7561
58%define X86_CPUID_VENDOR_VIA_EDX 0x48727561
59%define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
60%define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
61%define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
62%define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
63%define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
64%define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
65%define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
66%define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
67%define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
68%define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
69%define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
70%define X86_CPUID_FEATURE_ECX_SDBG RT_BIT(11)
71%define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
72%define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
73%define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
74%define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
75%define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
76%define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
77%define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
78%define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
79%define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
80%define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
81%define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
82%define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
83%define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
84%define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
85%define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
86%define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
87%define X86_CPUID_FEATURE_ECX_F16C RT_BIT(29)
88%define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT(30)
89%define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
90%define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
91%define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
92%define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
93%define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
94%define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
95%define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
96%define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
97%define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
98%define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
99%define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
100%define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
101%define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
102%define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
103%define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
104%define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
105%define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
106%define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
107%define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
108%define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
109%define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
110%define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
111%define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
112%define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
113%define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
114%define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
115%define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
116%define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
117%define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
118%define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
119%define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
120%define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
121%define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
122%define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
123%define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
124%define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
125%define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT(5)
126%define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
127%define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
128%define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
129%define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
130%define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
131%define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
132%define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT(13)
133%define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
134%define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
135%define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
136%define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT(18)
137%define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
138%define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
139%define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT(23)
140%define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
141%define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
142%define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
143%define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
144%define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
145%define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT(0)
146%define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
147%define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
148%define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
149%define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
150%define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
151%define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
152%define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
153%define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
154%define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
155%define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
156%define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
157%define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
158%define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
159%define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
160%define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
161%define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
162%define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
163%define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
164%define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
165%define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
166%define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
167%define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
168%define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
169%define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
170%define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
171%define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
172%define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
173%define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
174%define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
175%define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
176%define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
177%define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
178%define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
179%define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
180%define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
181%define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
182%define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
183%define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
184%define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT(11)
185%define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
186%define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
187%define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT(15)
188%define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT(16)
189%define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT(19)
190%define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT(21)
191%define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT(22)
192%define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
193%define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
194%define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
195%define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
196%define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
197%define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
198%define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
199%define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
200%define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
201%define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
202%define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
203%define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
204%define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
205%define X86_CR0_PE RT_BIT(0)
206%define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
207%define X86_CR0_MP RT_BIT(1)
208%define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
209%define X86_CR0_EM RT_BIT(2)
210%define X86_CR0_EMULATE_FPU RT_BIT(2)
211%define X86_CR0_TS RT_BIT(3)
212%define X86_CR0_TASK_SWITCH RT_BIT(3)
213%define X86_CR0_ET RT_BIT(4)
214%define X86_CR0_EXTENSION_TYPE RT_BIT(4)
215%define X86_CR0_NE RT_BIT(5)
216%define X86_CR0_NUMERIC_ERROR RT_BIT(5)
217%define X86_CR0_WP RT_BIT(16)
218%define X86_CR0_WRITE_PROTECT RT_BIT(16)
219%define X86_CR0_AM RT_BIT(18)
220%define X86_CR0_ALIGMENT_MASK RT_BIT(18)
221%define X86_CR0_NW RT_BIT(29)
222%define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
223%define X86_CR0_CD RT_BIT(30)
224%define X86_CR0_CACHE_DISABLE RT_BIT(30)
225%define X86_CR0_PG RT_BIT(31)
226%define X86_CR0_PAGING RT_BIT(31)
227%define X86_CR3_PWT RT_BIT(3)
228%define X86_CR3_PCD RT_BIT(4)
229%define X86_CR3_PAGE_MASK (0xfffff000)
230%define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
231%define X86_CR3_AMD64_PAGE_MASK 0x000ffffffffff000
232%define X86_CR4_VME RT_BIT(0)
233%define X86_CR4_PVI RT_BIT(1)
234%define X86_CR4_TSD RT_BIT(2)
235%define X86_CR4_DE RT_BIT(3)
236%define X86_CR4_PSE RT_BIT(4)
237%define X86_CR4_PAE RT_BIT(5)
238%define X86_CR4_MCE RT_BIT(6)
239%define X86_CR4_PGE RT_BIT(7)
240%define X86_CR4_PCE RT_BIT(8)
241%define X86_CR4_OSFXSR RT_BIT(9)
242%define X86_CR4_OSXMMEEXCPT RT_BIT(10)
243%define X86_CR4_VMXE RT_BIT(13)
244%define X86_CR4_SMXE RT_BIT(14)
245%define X86_CR4_PCIDE RT_BIT(17)
246%define X86_CR4_OSXSAVE RT_BIT(18)
247%define X86_CR4_SMEP RT_BIT(20)
248%define X86_CR4_SMAP RT_BIT(21)
249%define X86_DR6_B0 RT_BIT(0)
250%define X86_DR6_B1 RT_BIT(1)
251%define X86_DR6_B2 RT_BIT(2)
252%define X86_DR6_B3 RT_BIT(3)
253%define X86_DR6_B_MASK 0x0000000f
254%define X86_DR6_BD RT_BIT(13)
255%define X86_DR6_BS RT_BIT(14)
256%define X86_DR6_BT RT_BIT(15)
257%define X86_DR6_INIT_VAL 0xFFFF0FF0
258%define X86_DR6_RA1_MASK 0xffff0ff0
259%define X86_DR6_RAZ_MASK RT_BIT_64(12)
260%define X86_DR6_MBZ_MASK 0xffffffff00000000
261%define X86_DR6_B(iBp) RT_BIT_64(iBp)
262%define X86_DR7_L0 RT_BIT(0)
263%define X86_DR7_G0 RT_BIT(1)
264%define X86_DR7_L1 RT_BIT(2)
265%define X86_DR7_G1 RT_BIT(3)
266%define X86_DR7_L2 RT_BIT(4)
267%define X86_DR7_G2 RT_BIT(5)
268%define X86_DR7_L3 RT_BIT(6)
269%define X86_DR7_G3 RT_BIT(7)
270%define X86_DR7_LE RT_BIT(8)
271%define X86_DR7_GE RT_BIT(9)
272%define X86_DR7_LE_ALL 0x0000000000000055
273%define X86_DR7_GE_ALL 0x00000000000000aa
274%define X86_DR7_ICE_IR RT_BIT(12)
275%define X86_DR7_GD RT_BIT(13)
276%define X86_DR7_ICE_TR1 RT_BIT(14)
277%define X86_DR7_ICE_TR2 RT_BIT(15)
278%define X86_DR7_RW0_MASK (3 << 16)
279%define X86_DR7_LEN0_MASK (3 << 18)
280%define X86_DR7_RW1_MASK (3 << 20)
281%define X86_DR7_LEN1_MASK (3 << 22)
282%define X86_DR7_RW2_MASK (3 << 24)
283%define X86_DR7_LEN2_MASK (3 << 26)
284%define X86_DR7_RW3_MASK (3 << 28)
285%define X86_DR7_LEN3_MASK (3 << 30)
286%define X86_DR7_RA1_MASK (RT_BIT(10))
287%define X86_DR7_RAZ_MASK 0x0000d800
288%define X86_DR7_MBZ_MASK 0xffffffff00000000
289%define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
290%define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
291%define X86_DR7_L_G(iBp) ( 3 << (iBp * 2) )
292%define X86_DR7_RW_EO 0
293%define X86_DR7_RW_WO 1
294%define X86_DR7_RW_IO 2
295%define X86_DR7_RW_RW 3
296%define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
297%define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & 3 )
298%define X86_DR7_RW_ALL_MASKS 0x33330000
299%ifndef VBOX_FOR_DTRACE_LIB
300 %define X86_DR7_ANY_RW_IO(uDR7) \
301 ( ( 0x22220000 & (uDR7) )
302%endif
303%define X86_DR7_LEN_BYTE 0
304%define X86_DR7_LEN_WORD 1
305%define X86_DR7_LEN_QWORD 2
306%define X86_DR7_LEN_DWORD 3
307%define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
308%define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3 )
309%define X86_DR7_ENABLED_MASK 0x000000ff
310%define X86_DR7_LEN_ALL_MASKS 0xcccc0000
311%define X86_DR7_RW_LEN_ALL_MASKS 0xffff0000
312%define X86_DR7_INIT_VAL 0x400
313%define MSR_P5_MC_ADDR 0x00000000
314%define MSR_P5_MC_TYPE 0x00000001
315%define MSR_IA32_TSC 0x10
316%define MSR_IA32_CESR 0x00000011
317%define MSR_IA32_CTR0 0x00000012
318%define MSR_IA32_CTR1 0x00000013
319%define MSR_IA32_PLATFORM_ID 0x17
320%ifndef MSR_IA32_APICBASE
321 %define MSR_IA32_APICBASE 0x1b
322 %define MSR_IA32_APICBASE_EN RT_BIT_64(11)
323 %define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
324 %define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
325 %define MSR_IA32_APICBASE_BASE_MIN 0x0000000ffffff000
326%endif
327%define MSR_CORE_THREAD_COUNT 0x35
328%define MSR_IA32_FEATURE_CONTROL 0x3A
329%define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
330%define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT(1)
331%define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
332%define MSR_IA32_TSC_ADJUST 0x3B
333%define MSR_IA32_BIOS_UPDT_TRIG 0x79
334%define MSR_IA32_BIOS_SIGN_ID 0x8B
335%define MSR_IA32_PMC0 0xC1
336%define MSR_IA32_PMC1 0xC2
337%define MSR_IA32_PMC2 0xC3
338%define MSR_IA32_PMC3 0xC4
339%define MSR_IA32_PLATFORM_INFO 0xCE
340%define MSR_IA32_FSB_CLOCK_STS 0xCD
341%define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
342%define MSR_IA32_MPERF 0xE7
343%define MSR_IA32_APERF 0xE8
344%define MSR_IA32_MTRR_CAP 0xFE
345%define MSR_BBL_CR_CTL3 0x11e
346%ifndef MSR_IA32_SYSENTER_CS
347%define MSR_IA32_SYSENTER_CS 0x174
348%define MSR_IA32_SYSENTER_ESP 0x175
349%define MSR_IA32_SYSENTER_EIP 0x176
350%endif
351%define MSR_IA32_MCG_CAP 0x179
352%define MSR_IA32_MCG_STATUS 0x17A
353%define MSR_IA32_MCG_CTRL 0x17B
354%define MSR_IA32_CR_PAT 0x277
355%define MSR_IA32_PERFEVTSEL0 0x186
356%define MSR_IA32_PERFEVTSEL1 0x187
357%define MSR_FLEX_RATIO 0x194
358%define MSR_IA32_PERF_STATUS 0x198
359%define MSR_IA32_PERF_CTL 0x199
360%define MSR_IA32_THERM_STATUS 0x19c
361%define MSR_IA32_MISC_ENABLE 0x1A0
362%define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
363%define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
364%define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
365%define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
366%define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
367%define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
368%define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
369%define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
370%define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
371%define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
372%define MSR_IA32_DEBUGCTL 0x000001d9
373%define MSR_P4_LASTBRANCH_TOS 0x000001da
374%define MSR_P4_LASTBRANCH_0 0x000001db
375%define MSR_P4_LASTBRANCH_1 0x000001dc
376%define MSR_P4_LASTBRANCH_2 0x000001dd
377%define MSR_P4_LASTBRANCH_3 0x000001de
378%define IA32_MTRR_PHYSBASE0 0x200
379%define IA32_MTRR_PHYSMASK0 0x201
380%define IA32_MTRR_PHYSBASE1 0x202
381%define IA32_MTRR_PHYSMASK1 0x203
382%define IA32_MTRR_PHYSBASE2 0x204
383%define IA32_MTRR_PHYSMASK2 0x205
384%define IA32_MTRR_PHYSBASE3 0x206
385%define IA32_MTRR_PHYSMASK3 0x207
386%define IA32_MTRR_PHYSBASE4 0x208
387%define IA32_MTRR_PHYSMASK4 0x209
388%define IA32_MTRR_PHYSBASE5 0x20a
389%define IA32_MTRR_PHYSMASK5 0x20b
390%define IA32_MTRR_PHYSBASE6 0x20c
391%define IA32_MTRR_PHYSMASK6 0x20d
392%define IA32_MTRR_PHYSBASE7 0x20e
393%define IA32_MTRR_PHYSMASK7 0x20f
394%define IA32_MTRR_PHYSBASE8 0x210
395%define IA32_MTRR_PHYSMASK8 0x211
396%define IA32_MTRR_PHYSBASE9 0x212
397%define IA32_MTRR_PHYSMASK9 0x213
398%define IA32_MTRR_FIX64K_00000 0x250
399%define IA32_MTRR_FIX16K_80000 0x258
400%define IA32_MTRR_FIX16K_A0000 0x259
401%define IA32_MTRR_FIX4K_C0000 0x268
402%define IA32_MTRR_FIX4K_C8000 0x269
403%define IA32_MTRR_FIX4K_D0000 0x26a
404%define IA32_MTRR_FIX4K_D8000 0x26b
405%define IA32_MTRR_FIX4K_E0000 0x26c
406%define IA32_MTRR_FIX4K_E8000 0x26d
407%define IA32_MTRR_FIX4K_F0000 0x26e
408%define IA32_MTRR_FIX4K_F8000 0x26f
409%define MSR_IA32_MTRR_DEF_TYPE 0x2FF
410%define MSR_IA32_MC0_CTL 0x400
411%define MSR_IA32_MC0_STATUS 0x401
412%define MSR_IA32_VMX_BASIC_INFO 0x480
413%define MSR_IA32_VMX_PINBASED_CTLS 0x481
414%define MSR_IA32_VMX_PROCBASED_CTLS 0x482
415%define MSR_IA32_VMX_EXIT_CTLS 0x483
416%define MSR_IA32_VMX_ENTRY_CTLS 0x484
417%define MSR_IA32_VMX_MISC 0x485
418%define MSR_IA32_VMX_CR0_FIXED0 0x486
419%define MSR_IA32_VMX_CR0_FIXED1 0x487
420%define MSR_IA32_VMX_CR4_FIXED0 0x488
421%define MSR_IA32_VMX_CR4_FIXED1 0x489
422%define MSR_IA32_VMX_VMCS_ENUM 0x48A
423%define MSR_IA32_VMX_VMFUNC 0x491
424%define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
425%define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
426%define MSR_IA32_DS_AREA 0x600
427%define MSR_RAPL_POWER_UNIT 0x606
428%define MSR_IA32_X2APIC_START 0x800
429%define MSR_IA32_X2APIC_TPR 0x808
430%define MSR_IA32_X2APIC_END 0xBFF
431%define MSR_K6_EFER 0xc0000080
432%define MSR_K6_EFER_SCE RT_BIT(0)
433%define MSR_K6_EFER_LME RT_BIT(8)
434%define MSR_K6_EFER_LMA RT_BIT(10)
435%define MSR_K6_EFER_NXE RT_BIT(11)
436%define MSR_K6_EFER_SVME RT_BIT(12)
437%define MSR_K6_EFER_LMSLE RT_BIT(13)
438%define MSR_K6_EFER_FFXSR RT_BIT(14)
439%define MSR_K6_EFER_TCE RT_BIT(15)
440%define MSR_K6_STAR 0xc0000081
441%define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
442%define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
443%define MSR_K6_STAR_SEL_MASK 0xffff
444%define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
445%define MSR_K6_WHCR 0xc0000082
446%define MSR_K6_UWCCR 0xc0000085
447%define MSR_K6_PSOR 0xc0000087
448%define MSR_K6_PFIR 0xc0000088
449%define MSR_K7_EVNTSEL0 0xc0010000
450%define MSR_K7_EVNTSEL1 0xc0010001
451%define MSR_K7_EVNTSEL2 0xc0010002
452%define MSR_K7_EVNTSEL3 0xc0010003
453%define MSR_K7_PERFCTR0 0xc0010004
454%define MSR_K7_PERFCTR1 0xc0010005
455%define MSR_K7_PERFCTR2 0xc0010006
456%define MSR_K7_PERFCTR3 0xc0010007
457%define MSR_K8_LSTAR 0xc0000082
458%define MSR_K8_CSTAR 0xc0000083
459%define MSR_K8_SF_MASK 0xc0000084
460%define MSR_K8_FS_BASE 0xc0000100
461%define MSR_K8_GS_BASE 0xc0000101
462%define MSR_K8_KERNEL_GS_BASE 0xc0000102
463%define MSR_K8_TSC_AUX 0xc0000103
464%define MSR_K8_SYSCFG 0xc0010010
465%define MSR_K8_HWCR 0xc0010015
466%define MSR_K8_IORRBASE0 0xc0010016
467%define MSR_K8_IORRMASK0 0xc0010017
468%define MSR_K8_IORRBASE1 0xc0010018
469%define MSR_K8_IORRMASK1 0xc0010019
470%define MSR_K8_TOP_MEM1 0xc001001a
471%define MSR_K8_TOP_MEM2 0xc001001d
472%define MSR_K8_NB_CFG 0xc001001f
473%define MSR_K8_INT_PENDING 0xc0010055
474%define MSR_K8_VM_CR 0xc0010114
475%define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
476%define MSR_K8_IGNNE 0xc0010115
477%define MSR_K8_SMM_CTL 0xc0010116
478%define MSR_K8_VM_HSAVE_PA 0xc0010117
479%define X86_PG_ENTRIES 1024
480%define X86_PG_PAE_ENTRIES 512
481%define X86_PG_PAE_PDPE_ENTRIES 4
482%define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
483%define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
484%define X86_PAGE_4K_SIZE _4K
485%define X86_PAGE_4K_SHIFT 12
486%define X86_PAGE_4K_OFFSET_MASK 0xfff
487%define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000
488%define X86_PAGE_4K_BASE_MASK_32 0xfffff000
489%define X86_PAGE_2M_SIZE _2M
490%define X86_PAGE_2M_SHIFT 21
491%define X86_PAGE_2M_OFFSET_MASK 0x001fffff
492%define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000
493%define X86_PAGE_2M_BASE_MASK_32 0xffe00000
494%define X86_PAGE_4M_SIZE _4M
495%define X86_PAGE_4M_SHIFT 22
496%define X86_PAGE_4M_OFFSET_MASK 0x003fffff
497%define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000
498%define X86_PAGE_4M_BASE_MASK_32 0xffc00000
499%define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + 0x800000000000 < UINT64_C(0x1000000000000))
500%define X86_PTE_BIT_P 0
501%define X86_PTE_BIT_RW 1
502%define X86_PTE_BIT_US 2
503%define X86_PTE_BIT_PWT 3
504%define X86_PTE_BIT_PCD 4
505%define X86_PTE_BIT_A 5
506%define X86_PTE_BIT_D 6
507%define X86_PTE_BIT_PAT 7
508%define X86_PTE_BIT_G 8
509%define X86_PTE_P RT_BIT(0)
510%define X86_PTE_RW RT_BIT(1)
511%define X86_PTE_US RT_BIT(2)
512%define X86_PTE_PWT RT_BIT(3)
513%define X86_PTE_PCD RT_BIT(4)
514%define X86_PTE_A RT_BIT(5)
515%define X86_PTE_D RT_BIT(6)
516%define X86_PTE_PAT RT_BIT(7)
517%define X86_PTE_G RT_BIT(8)
518%define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
519%define X86_PTE_PG_MASK ( 0xfffff000 )
520%define X86_PTE_PAE_PG_MASK 0x000ffffffffff000
521%define X86_PTE_PAE_NX RT_BIT_64(63)
522%define X86_PTE_PAE_MBZ_MASK_NX 0x7ff0000000000000
523%define X86_PTE_PAE_MBZ_MASK_NO_NX 0xfff0000000000000
524%define X86_PTE_LM_MBZ_MASK_NX 0x0000000000000000
525%define X86_PTE_LM_MBZ_MASK_NO_NX 0x8000000000000000
526%define X86_PT_SHIFT 12
527%define X86_PT_MASK 0x3ff
528%define X86_PT_PAE_SHIFT 12
529%define X86_PT_PAE_MASK 0x1ff
530%define X86_PDE_P RT_BIT(0)
531%define X86_PDE_RW RT_BIT(1)
532%define X86_PDE_US RT_BIT(2)
533%define X86_PDE_PWT RT_BIT(3)
534%define X86_PDE_PCD RT_BIT(4)
535%define X86_PDE_A RT_BIT(5)
536%define X86_PDE_PS RT_BIT(7)
537%define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
538%define X86_PDE_PG_MASK ( 0xfffff000 )
539%define X86_PDE_PAE_PG_MASK 0x000ffffffffff000
540%define X86_PDE_PAE_NX RT_BIT_64(63)
541%define X86_PDE_PAE_MBZ_MASK_NX 0x7ff0000000000080
542%define X86_PDE_PAE_MBZ_MASK_NO_NX 0xfff0000000000080
543%define X86_PDE_LM_MBZ_MASK_NX 0x0000000000000080
544%define X86_PDE_LM_MBZ_MASK_NO_NX 0x8000000000000080
545%define X86_PDE4M_P RT_BIT(0)
546%define X86_PDE4M_RW RT_BIT(1)
547%define X86_PDE4M_US RT_BIT(2)
548%define X86_PDE4M_PWT RT_BIT(3)
549%define X86_PDE4M_PCD RT_BIT(4)
550%define X86_PDE4M_A RT_BIT(5)
551%define X86_PDE4M_D RT_BIT(6)
552%define X86_PDE4M_PS RT_BIT(7)
553%define X86_PDE4M_G RT_BIT(8)
554%define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
555%define X86_PDE4M_PAT RT_BIT(12)
556%define X86_PDE4M_PAT_SHIFT (12 - 7)
557%define X86_PDE4M_PG_MASK ( 0xffc00000 )
558%define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
559%define X86_PDE4M_PG_HIGH_SHIFT 19
560%define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
561%define X86_PDE2M_PAE_PG_MASK 0x000fffffffe00000
562%define X86_PDE2M_PAE_NX RT_BIT_64(63)
563%define X86_PDE2M_PAE_MBZ_MASK_NX 0x7ff00000001fe000
564%define X86_PDE2M_PAE_MBZ_MASK_NO_NX 0xfff00000001fe000
565%define X86_PDE2M_LM_MBZ_MASK_NX 0x00000000001fe000
566%define X86_PDE2M_LM_MBZ_MASK_NO_NX 0x80000000001fe000
567%define X86_PD_SHIFT 22
568%define X86_PD_MASK 0x3ff
569%define X86_PD_PAE_SHIFT 21
570%define X86_PD_PAE_MASK 0x1ff
571%define X86_PDPE_P RT_BIT(0)
572%define X86_PDPE_RW RT_BIT(1)
573%define X86_PDPE_US RT_BIT(2)
574%define X86_PDPE_PWT RT_BIT(3)
575%define X86_PDPE_PCD RT_BIT(4)
576%define X86_PDPE_A RT_BIT(5)
577%define X86_PDPE_LM_PS RT_BIT(7)
578%define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
579%define X86_PDPE_PG_MASK 0x000ffffffffff000
580%define X86_PDPE_PAE_MBZ_MASK 0xfff00000000001e6
581%define X86_PDPE_LM_NX RT_BIT_64(63)
582%define X86_PDPE_LM_MBZ_MASK_NX 0x0000000000000180
583%define X86_PDPE_LM_MBZ_MASK_NO_NX 0x8000000000000180
584%define X86_PDPE1G_LM_MBZ_MASK_NX 0x000000003fffe000
585%define X86_PDPE1G_LM_MBZ_MASK_NO_NX 0x800000003fffe000
586%define X86_PDPT_SHIFT 30
587%define X86_PDPT_MASK_PAE 0x3
588%define X86_PDPT_MASK_AMD64 0x1ff
589%define X86_PML4E_P RT_BIT(0)
590%define X86_PML4E_RW RT_BIT(1)
591%define X86_PML4E_US RT_BIT(2)
592%define X86_PML4E_PWT RT_BIT(3)
593%define X86_PML4E_PCD RT_BIT(4)
594%define X86_PML4E_A RT_BIT(5)
595%define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
596%define X86_PML4E_PG_MASK 0x000ffffffffff000
597%define X86_PML4E_MBZ_MASK_NX 0x0000000000000080
598%define X86_PML4E_MBZ_MASK_NO_NX 0x8000000000000080
599%define X86_PML4E_NX RT_BIT_64(63)
600%define X86_PML4_SHIFT 39
601%define X86_PML4_MASK 0x1ff
602%ifndef VBOX_FOR_DTRACE_LIB
603%endif
604%ifndef VBOX_FOR_DTRACE_LIB
605%endif
606%ifndef VBOX_FOR_DTRACE_LIB
607%endif
608%ifndef VBOX_FOR_DTRACE_LIB
609%endif
610%ifndef VBOX_FOR_DTRACE_LIB
611%endif
612%define X86_OFF_FXSTATE_RSVD 0x1d0
613%define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
614%ifndef VBOX_FOR_DTRACE_LIB
615%endif
616%define X86_FSW_IE RT_BIT(0)
617%define X86_FSW_DE RT_BIT(1)
618%define X86_FSW_ZE RT_BIT(2)
619%define X86_FSW_OE RT_BIT(3)
620%define X86_FSW_UE RT_BIT(4)
621%define X86_FSW_PE RT_BIT(5)
622%define X86_FSW_SF RT_BIT(6)
623%define X86_FSW_ES RT_BIT(7)
624%define X86_FSW_XCPT_MASK 0x007f
625%define X86_FSW_XCPT_ES_MASK 0x00ff
626%define X86_FSW_C0 RT_BIT(8)
627%define X86_FSW_C1 RT_BIT(9)
628%define X86_FSW_C2 RT_BIT(10)
629%define X86_FSW_TOP_MASK 0x3800
630%define X86_FSW_TOP_SHIFT 11
631%define X86_FSW_TOP_SMASK 0x0007
632%define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
633%define X86_FSW_C3 RT_BIT(14)
634%define X86_FSW_C_MASK 0x4700
635%define X86_FSW_B RT_BIT(15)
636%define X86_FCW_IM RT_BIT(0)
637%define X86_FCW_DM RT_BIT(1)
638%define X86_FCW_ZM RT_BIT(2)
639%define X86_FCW_OM RT_BIT(3)
640%define X86_FCW_UM RT_BIT(4)
641%define X86_FCW_PM RT_BIT(5)
642%define X86_FCW_MASK_ALL 0x007f
643%define X86_FCW_XCPT_MASK 0x003f
644%define X86_FCW_PC_MASK 0x0300
645%define X86_FCW_PC_24 0x0000
646%define X86_FCW_PC_RSVD 0x0100
647%define X86_FCW_PC_53 0x0200
648%define X86_FCW_PC_64 0x0300
649%define X86_FCW_RC_MASK 0x0c00
650%define X86_FCW_RC_NEAREST 0x0000
651%define X86_FCW_RC_DOWN 0x0400
652%define X86_FCW_RC_UP 0x0800
653%define X86_FCW_RC_ZERO 0x0c00
654%define X86_FCW_ZERO_MASK 0xf080
655%define X86_MXSCR_IE RT_BIT(0)
656%define X86_MXSCR_DE RT_BIT(1)
657%define X86_MXSCR_ZE RT_BIT(2)
658%define X86_MXSCR_OE RT_BIT(3)
659%define X86_MXSCR_UE RT_BIT(4)
660%define X86_MXSCR_PE RT_BIT(5)
661%define X86_MXSCR_DAZ RT_BIT(6)
662%define X86_MXSCR_IM RT_BIT(7)
663%define X86_MXSCR_DM RT_BIT(8)
664%define X86_MXSCR_ZM RT_BIT(9)
665%define X86_MXSCR_OM RT_BIT(10)
666%define X86_MXSCR_UM RT_BIT(11)
667%define X86_MXSCR_PM RT_BIT(12)
668%define X86_MXSCR_RC_MASK 0x6000
669%define X86_MXSCR_RC_NEAREST 0x0000
670%define X86_MXSCR_RC_DOWN 0x2000
671%define X86_MXSCR_RC_UP 0x4000
672%define X86_MXSCR_RC_ZERO 0x6000
673%define X86_MXSCR_FZ RT_BIT(15)
674%define X86_MXSCR_MM RT_BIT(17)
675%ifndef VBOX_FOR_DTRACE_LIB
676%endif
677%ifndef VBOX_FOR_DTRACE_LIB
678%endif
679%ifndef VBOX_FOR_DTRACE_LIB
680%endif
681%ifndef VBOX_FOR_DTRACE_LIB
682%endif
683%ifndef VBOX_FOR_DTRACE_LIB
684%endif
685%ifndef VBOX_FOR_DTRACE_LIB
686%endif
687%ifndef VBOX_FOR_DTRACE_LIB
688%endif
689%ifndef VBOX_FOR_DTRACE_LIB
690%endif
691%ifndef VBOX_FOR_DTRACE_LIB
692%endif
693%define XSAVE_C_X87 RT_BIT_64(0)
694%define XSAVE_C_SSE RT_BIT_64(1)
695%define XSAVE_C_YMM RT_BIT_64(2)
696%define XSAVE_C_BNDREGS RT_BIT_64(3)
697%define XSAVE_C_BNDCSR RT_BIT_64(4)
698%define XSAVE_C_OPMASK RT_BIT_64(5)
699%define XSAVE_C_ZMM_HI256 RT_BIT_64(6)
700%define XSAVE_C_ZMM_16HI RT_BIT_64(7)
701%define XSAVE_C_LWP RT_BIT_64(62)
702%ifndef VBOX_FOR_DTRACE_LIB
703%endif
704%define X86DESCATTR_TYPE 0x0000000f
705%define X86DESCATTR_DT 0x00000010
706%define X86DESCATTR_DPL 0x00000060
707%define X86DESCATTR_DPL_SHIFT 5
708%define X86DESCATTR_P 0x00000080
709%define X86DESCATTR_LIMIT_HIGH 0x00000f00
710%define X86DESCATTR_AVL 0x00001000
711%define X86DESCATTR_L 0x00002000
712%define X86DESCATTR_D 0x00004000
713%define X86DESCATTR_G 0x00008000
714%define X86DESCATTR_UNUSABLE 0x00010000
715%ifndef VBOX_FOR_DTRACE_LIB
716%endif
717%ifndef VBOX_FOR_DTRACE_LIB
718%define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0)
719%define X86DESCGENERIC_BIT_OFF_BASE_LOW (16)
720%define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32)
721%define X86DESCGENERIC_BIT_OFF_TYPE (40)
722%define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44)
723%define X86DESCGENERIC_BIT_OFF_DPL (45)
724%define X86DESCGENERIC_BIT_OFF_PRESENT (47)
725%define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48)
726%define X86DESCGENERIC_BIT_OFF_AVAILABLE (52)
727%define X86DESCGENERIC_BIT_OFF_LONG (53)
728%define X86DESCGENERIC_BIT_OFF_DEF_BIG (54)
729%define X86DESCGENERIC_BIT_OFF_GRANULARITY (55)
730%define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56)
731%endif
732%ifndef VBOX_FOR_DTRACE_LIB
733%endif
734%ifndef VBOX_FOR_DTRACE_LIB
735%endif
736%ifndef VBOX_FOR_DTRACE_LIB
737%endif
738%ifndef VBOX_FOR_DTRACE_LIB
739%endif
740%ifndef VBOX_FOR_DTRACE_LIB
741%endif
742%if HC_ARCH_BITS == 64
743%else
744%endif
745%if HC_ARCH_BITS == 64
746%else
747%endif
748%if HC_ARCH_BITS == 64
749%else
750%endif
751%define X86_SEL_TYPE_CODE 8
752%define X86_SEL_TYPE_MEMORY RT_BIT(4)
753%define X86_SEL_TYPE_ACCESSED 1
754%define X86_SEL_TYPE_DOWN 4
755%define X86_SEL_TYPE_CONF 4
756%define X86_SEL_TYPE_WRITE 2
757%define X86_SEL_TYPE_READ 2
758%define X86_SEL_TYPE_READ_BIT 1
759%define X86_SEL_TYPE_RO 0
760%define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
761%define X86_SEL_TYPE_RW 2
762%define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
763%define X86_SEL_TYPE_RO_DOWN 4
764%define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
765%define X86_SEL_TYPE_RW_DOWN 6
766%define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
767%define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
768%define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
769%define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
770%define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
771%define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
772%define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
773%define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
774%define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
775%define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
776%define X86_SEL_TYPE_SYS_UNDEFINED 0
777%define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
778%define X86_SEL_TYPE_SYS_LDT 2
779%define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
780%define X86_SEL_TYPE_SYS_286_CALL_GATE 4
781%define X86_SEL_TYPE_SYS_TASK_GATE 5
782%define X86_SEL_TYPE_SYS_286_INT_GATE 6
783%define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
784%define X86_SEL_TYPE_SYS_UNDEFINED2 8
785%define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
786%define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
787%define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
788%define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
789%define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
790%define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
791%define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
792%define AMD64_SEL_TYPE_SYS_LDT 2
793%define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
794%define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
795%define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
796%define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
797%define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
798%define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
799%define X86_DESC_S RT_BIT(12)
800%define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
801%define X86_DESC_P RT_BIT(15)
802%define X86_DESC_AVL RT_BIT(20)
803%define X86_DESC_DB RT_BIT(22)
804%define X86_DESC_G RT_BIT(23)
805%define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
806%define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
807%ifndef VBOX_FOR_DTRACE_LIB
808%endif
809%ifndef VBOX_FOR_DTRACE_LIB
810%endif
811%define X86_SEL_SHIFT 3
812%define X86_SEL_MASK 0xfff8
813%define X86_SEL_MASK_OFF_RPL 0xfffc
814%define X86_SEL_LDT 0x0004
815%define X86_SEL_RPL 0x0003
816%define X86_SEL_RPL_LDT 0x0007
817%define X86_XCPT_MAX (X86_XCPT_SX)
818%define X86_TRAP_ERR_EXTERNAL 1
819%define X86_TRAP_ERR_IDT 2
820%define X86_TRAP_ERR_TI 4
821%define X86_TRAP_ERR_SEL_MASK 0xfff8
822%define X86_TRAP_ERR_SEL_SHIFT 3
823%define X86_TRAP_PF_P RT_BIT(0)
824%define X86_TRAP_PF_RW RT_BIT(1)
825%define X86_TRAP_PF_US RT_BIT(2)
826%define X86_TRAP_PF_RSVD RT_BIT(3)
827%define X86_TRAP_PF_ID RT_BIT(4)
828%ifndef VBOX_FOR_DTRACE_LIB
829%else
830%endif
831%ifndef VBOX_FOR_DTRACE_LIB
832%else
833%endif
834%define X86_MODRM_RM_MASK 0x07
835%define X86_MODRM_REG_MASK 0x38
836%define X86_MODRM_REG_SMASK 0x07
837%define X86_MODRM_REG_SHIFT 3
838%define X86_MODRM_MOD_MASK 0xc0
839%define X86_MODRM_MOD_SMASK 0x03
840%define X86_MODRM_MOD_SHIFT 6
841%ifndef VBOX_FOR_DTRACE_LIB
842%endif
843%define X86_SIB_BASE_MASK 0x07
844%define X86_SIB_INDEX_MASK 0x38
845%define X86_SIB_INDEX_SMASK 0x07
846%define X86_SIB_INDEX_SHIFT 3
847%define X86_SIB_SCALE_MASK 0xc0
848%define X86_SIB_SCALE_SMASK 0x03
849%define X86_SIB_SCALE_SHIFT 6
850%ifndef VBOX_FOR_DTRACE_LIB
851%endif
852%define X86_GREG_xAX 0
853%define X86_GREG_xCX 1
854%define X86_GREG_xDX 2
855%define X86_GREG_xBX 3
856%define X86_GREG_xSP 4
857%define X86_GREG_xBP 5
858%define X86_GREG_xSI 6
859%define X86_GREG_xDI 7
860%define X86_GREG_x8 8
861%define X86_GREG_x9 9
862%define X86_GREG_x10 10
863%define X86_GREG_x11 11
864%define X86_GREG_x12 12
865%define X86_GREG_x13 13
866%define X86_GREG_x14 14
867%define X86_GREG_x15 15
868%define X86_SREG_ES 0
869%define X86_SREG_CS 1
870%define X86_SREG_SS 2
871%define X86_SREG_DS 3
872%define X86_SREG_FS 4
873%define X86_SREG_GS 5
874%define X86_SREG_COUNT 6
875%define X86_OP_PRF_CS 0x2e
876%define X86_OP_PRF_SS 0x36
877%define X86_OP_PRF_DS 0x3e
878%define X86_OP_PRF_ES 0x26
879%define X86_OP_PRF_FS 0x64
880%define X86_OP_PRF_GS 0x65
881%define X86_OP_PRF_SIZE_OP 0x66
882%define X86_OP_PRF_SIZE_ADDR 0x67
883%define X86_OP_PRF_LOCK 0xf0
884%define X86_OP_PRF_REPZ 0xf2
885%define X86_OP_PRF_REPNZ 0xf3
886%define X86_OP_REX_B 0x41
887%define X86_OP_REX_X 0x42
888%define X86_OP_REX_R 0x44
889%define X86_OP_REX_W 0x48
890%endif
891%include "iprt/x86extra.mac"
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