VirtualBox

source: vbox/trunk/include/iprt/x86.mac@ 54894

Last change on this file since 54894 was 54894, checked in by vboxsync, 10 years ago

VMM: Expose some of the recent AMD instruction set extensions to the guest too.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 39.8 KB
Line 
1%ifndef ___iprt_x86_h
2%define ___iprt_x86_h
3%ifndef VBOX_FOR_DTRACE_LIB
4%else
5%endif
6%ifdef RT_OS_SOLARIS
7%endif
8%ifndef VBOX_FOR_DTRACE_LIB
9%endif
10%ifndef VBOX_FOR_DTRACE_LIB
11%endif
12%ifndef VBOX_FOR_DTRACE_LIB
13%endif
14%define X86_EFL_CF RT_BIT(0)
15%define X86_EFL_CF_BIT 0
16%define X86_EFL_1 RT_BIT(1)
17%define X86_EFL_PF RT_BIT(2)
18%define X86_EFL_AF RT_BIT(4)
19%define X86_EFL_AF_BIT 4
20%define X86_EFL_ZF RT_BIT(6)
21%define X86_EFL_ZF_BIT 6
22%define X86_EFL_SF RT_BIT(7)
23%define X86_EFL_SF_BIT 7
24%define X86_EFL_TF RT_BIT(8)
25%define X86_EFL_IF RT_BIT(9)
26%define X86_EFL_DF RT_BIT(10)
27%define X86_EFL_OF RT_BIT(11)
28%define X86_EFL_OF_BIT 11
29%define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
30%define X86_EFL_NT RT_BIT(14)
31%define X86_EFL_RF RT_BIT(16)
32%define X86_EFL_VM RT_BIT(17)
33%define X86_EFL_AC RT_BIT(18)
34%define X86_EFL_VIF RT_BIT(19)
35%define X86_EFL_VIP RT_BIT(20)
36%define X86_EFL_ID RT_BIT(21)
37%define X86_EFL_LIVE_MASK 0x003f7fd5
38%define X86_EFL_RA1_MASK RT_BIT_32(1)
39%define X86_EFL_IOPL_SHIFT 12
40%define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
41%define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
42 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
43%define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
44%ifndef VBOX_FOR_DTRACE_LIB
45%else
46%endif
47%ifndef VBOX_FOR_DTRACE_LIB
48%else
49%endif
50%define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547
51%define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e
52%define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69
53%define X86_CPUID_VENDOR_AMD_EBX 0x68747541
54%define X86_CPUID_VENDOR_AMD_ECX 0x444d4163
55%define X86_CPUID_VENDOR_AMD_EDX 0x69746e65
56%define X86_CPUID_VENDOR_VIA_EBX 0x746e6543
57%define X86_CPUID_VENDOR_VIA_ECX 0x736c7561
58%define X86_CPUID_VENDOR_VIA_EDX 0x48727561
59%define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
60%define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
61%define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
62%define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
63%define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
64%define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
65%define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
66%define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
67%define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
68%define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
69%define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
70%define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
71%define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
72%define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
73%define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
74%define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
75%define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
76%define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
77%define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
78%define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
79%define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
80%define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
81%define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
82%define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
83%define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
84%define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
85%define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
86%define X86_CPUID_FEATURE_ECX_F16C RT_BIT(29)
87%define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT(30)
88%define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
89%define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
90%define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
91%define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
92%define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
93%define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
94%define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
95%define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
96%define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
97%define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
98%define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
99%define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
100%define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
101%define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
102%define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
103%define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
104%define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
105%define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
106%define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
107%define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
108%define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
109%define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
110%define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
111%define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
112%define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
113%define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
114%define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
115%define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
116%define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
117%define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
118%define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
119%define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
120%define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
121%define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
122%define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
123%define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
124%define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT(5)
125%define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
126%define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
127%define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
128%define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
129%define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
130%define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
131%define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT(13)
132%define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
133%define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
134%define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
135%define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT(18)
136%define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
137%define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
138%define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT(23)
139%define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
140%define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
141%define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
142%define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
143%define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
144%define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
145%define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
146%define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
147%define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
148%define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
149%define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
150%define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
151%define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
152%define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
153%define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
154%define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
155%define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
156%define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
157%define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
158%define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
159%define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
160%define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
161%define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
162%define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
163%define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
164%define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
165%define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
166%define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
167%define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
168%define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
169%define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
170%define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
171%define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
172%define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
173%define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
174%define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
175%define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
176%define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
177%define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
178%define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
179%define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
180%define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
181%define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
182%define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT(11)
183%define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
184%define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
185%define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
186%define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
187%define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
188%define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
189%define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
190%define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
191%define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
192%define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
193%define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
194%define X86_CR0_PE RT_BIT(0)
195%define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
196%define X86_CR0_MP RT_BIT(1)
197%define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
198%define X86_CR0_EM RT_BIT(2)
199%define X86_CR0_EMULATE_FPU RT_BIT(2)
200%define X86_CR0_TS RT_BIT(3)
201%define X86_CR0_TASK_SWITCH RT_BIT(3)
202%define X86_CR0_ET RT_BIT(4)
203%define X86_CR0_EXTENSION_TYPE RT_BIT(4)
204%define X86_CR0_NE RT_BIT(5)
205%define X86_CR0_NUMERIC_ERROR RT_BIT(5)
206%define X86_CR0_WP RT_BIT(16)
207%define X86_CR0_WRITE_PROTECT RT_BIT(16)
208%define X86_CR0_AM RT_BIT(18)
209%define X86_CR0_ALIGMENT_MASK RT_BIT(18)
210%define X86_CR0_NW RT_BIT(29)
211%define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
212%define X86_CR0_CD RT_BIT(30)
213%define X86_CR0_CACHE_DISABLE RT_BIT(30)
214%define X86_CR0_PG RT_BIT(31)
215%define X86_CR0_PAGING RT_BIT(31)
216%define X86_CR3_PWT RT_BIT(3)
217%define X86_CR3_PCD RT_BIT(4)
218%define X86_CR3_PAGE_MASK (0xfffff000)
219%define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
220%define X86_CR3_AMD64_PAGE_MASK 0x000ffffffffff000
221%define X86_CR4_VME RT_BIT(0)
222%define X86_CR4_PVI RT_BIT(1)
223%define X86_CR4_TSD RT_BIT(2)
224%define X86_CR4_DE RT_BIT(3)
225%define X86_CR4_PSE RT_BIT(4)
226%define X86_CR4_PAE RT_BIT(5)
227%define X86_CR4_MCE RT_BIT(6)
228%define X86_CR4_PGE RT_BIT(7)
229%define X86_CR4_PCE RT_BIT(8)
230%define X86_CR4_OSFXSR RT_BIT(9)
231%define X86_CR4_OSXMMEEXCPT RT_BIT(10)
232%define X86_CR4_VMXE RT_BIT(13)
233%define X86_CR4_SMXE RT_BIT(14)
234%define X86_CR4_PCIDE RT_BIT(17)
235%define X86_CR4_OSXSAVE RT_BIT(18)
236%define X86_CR4_SMEP RT_BIT(20)
237%define X86_CR4_SMAP RT_BIT(21)
238%define X86_DR6_B0 RT_BIT(0)
239%define X86_DR6_B1 RT_BIT(1)
240%define X86_DR6_B2 RT_BIT(2)
241%define X86_DR6_B3 RT_BIT(3)
242%define X86_DR6_B_MASK 0x0000000f
243%define X86_DR6_BD RT_BIT(13)
244%define X86_DR6_BS RT_BIT(14)
245%define X86_DR6_BT RT_BIT(15)
246%define X86_DR6_INIT_VAL 0xFFFF0FF0
247%define X86_DR6_RA1_MASK 0xffff0ff0
248%define X86_DR6_RAZ_MASK RT_BIT_64(12)
249%define X86_DR6_MBZ_MASK 0xffffffff00000000
250%define X86_DR6_B(iBp) RT_BIT_64(iBp)
251%define X86_DR7_L0 RT_BIT(0)
252%define X86_DR7_G0 RT_BIT(1)
253%define X86_DR7_L1 RT_BIT(2)
254%define X86_DR7_G1 RT_BIT(3)
255%define X86_DR7_L2 RT_BIT(4)
256%define X86_DR7_G2 RT_BIT(5)
257%define X86_DR7_L3 RT_BIT(6)
258%define X86_DR7_G3 RT_BIT(7)
259%define X86_DR7_LE RT_BIT(8)
260%define X86_DR7_GE RT_BIT(9)
261%define X86_DR7_LE_ALL 0x0000000000000055
262%define X86_DR7_GE_ALL 0x00000000000000aa
263%define X86_DR7_ICE_IR RT_BIT(12)
264%define X86_DR7_GD RT_BIT(13)
265%define X86_DR7_ICE_TR1 RT_BIT(14)
266%define X86_DR7_ICE_TR2 RT_BIT(15)
267%define X86_DR7_RW0_MASK (3 << 16)
268%define X86_DR7_LEN0_MASK (3 << 18)
269%define X86_DR7_RW1_MASK (3 << 20)
270%define X86_DR7_LEN1_MASK (3 << 22)
271%define X86_DR7_RW2_MASK (3 << 24)
272%define X86_DR7_LEN2_MASK (3 << 26)
273%define X86_DR7_RW3_MASK (3 << 28)
274%define X86_DR7_LEN3_MASK (3 << 30)
275%define X86_DR7_RA1_MASK (RT_BIT(10))
276%define X86_DR7_RAZ_MASK 0x0000d800
277%define X86_DR7_MBZ_MASK 0xffffffff00000000
278%define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
279%define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
280%define X86_DR7_L_G(iBp) ( 3 << (iBp * 2) )
281%define X86_DR7_RW_EO 0
282%define X86_DR7_RW_WO 1
283%define X86_DR7_RW_IO 2
284%define X86_DR7_RW_RW 3
285%define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
286%define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & 3 )
287%define X86_DR7_RW_ALL_MASKS 0x33330000
288%define X86_DR7_ANY_RW_IO(uDR7) \
289 ( ( 0x22220000 & (uDR7) )
290%define X86_DR7_LEN_BYTE 0
291%define X86_DR7_LEN_WORD 1
292%define X86_DR7_LEN_QWORD 2
293%define X86_DR7_LEN_DWORD 3
294%define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
295%define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3 )
296%define X86_DR7_ENABLED_MASK 0x000000ff
297%define X86_DR7_LEN_ALL_MASKS 0xcccc0000
298%define X86_DR7_RW_LEN_ALL_MASKS 0xffff0000
299%define X86_DR7_INIT_VAL 0x400
300%define MSR_P5_MC_ADDR 0x00000000
301%define MSR_P5_MC_TYPE 0x00000001
302%define MSR_IA32_TSC 0x10
303%define MSR_IA32_CESR 0x00000011
304%define MSR_IA32_CTR0 0x00000012
305%define MSR_IA32_CTR1 0x00000013
306%define MSR_IA32_PLATFORM_ID 0x17
307%ifndef MSR_IA32_APICBASE
308 %define MSR_IA32_APICBASE 0x1b
309 %define MSR_IA32_APICBASE_EN RT_BIT_64(11)
310 %define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
311 %define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
312 %define MSR_IA32_APICBASE_BASE_MIN 0x0000000ffffff000
313%endif
314%define MSR_CORE_THREAD_COUNT 0x35
315%define MSR_IA32_FEATURE_CONTROL 0x3A
316%define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
317%define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT(1)
318%define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
319%define MSR_IA32_TSC_ADJUST 0x3B
320%define MSR_IA32_BIOS_UPDT_TRIG 0x79
321%define MSR_IA32_BIOS_SIGN_ID 0x8B
322%define MSR_IA32_PMC0 0xC1
323%define MSR_IA32_PMC1 0xC2
324%define MSR_IA32_PMC2 0xC3
325%define MSR_IA32_PMC3 0xC4
326%define MSR_IA32_PLATFORM_INFO 0xCE
327%define MSR_IA32_FSB_CLOCK_STS 0xCD
328%define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
329%define MSR_IA32_MPERF 0xE7
330%define MSR_IA32_APERF 0xE8
331%define MSR_IA32_MTRR_CAP 0xFE
332%define MSR_BBL_CR_CTL3 0x11e
333%ifndef MSR_IA32_SYSENTER_CS
334%define MSR_IA32_SYSENTER_CS 0x174
335%define MSR_IA32_SYSENTER_ESP 0x175
336%define MSR_IA32_SYSENTER_EIP 0x176
337%endif
338%define MSR_IA32_MCG_CAP 0x179
339%define MSR_IA32_MCG_STATUS 0x17A
340%define MSR_IA32_MCG_CTRL 0x17B
341%define MSR_IA32_CR_PAT 0x277
342%define MSR_IA32_PERFEVTSEL0 0x186
343%define MSR_IA32_PERFEVTSEL1 0x187
344%define MSR_FLEX_RATIO 0x194
345%define MSR_IA32_PERF_STATUS 0x198
346%define MSR_IA32_PERF_CTL 0x199
347%define MSR_IA32_THERM_STATUS 0x19c
348%define MSR_IA32_MISC_ENABLE 0x1A0
349%define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
350%define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
351%define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
352%define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
353%define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
354%define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
355%define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
356%define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
357%define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
358%define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
359%define MSR_IA32_DEBUGCTL 0x000001d9
360%define MSR_P4_LASTBRANCH_TOS 0x000001da
361%define MSR_P4_LASTBRANCH_0 0x000001db
362%define MSR_P4_LASTBRANCH_1 0x000001dc
363%define MSR_P4_LASTBRANCH_2 0x000001dd
364%define MSR_P4_LASTBRANCH_3 0x000001de
365%define IA32_MTRR_PHYSBASE0 0x200
366%define IA32_MTRR_PHYSMASK0 0x201
367%define IA32_MTRR_PHYSBASE1 0x202
368%define IA32_MTRR_PHYSMASK1 0x203
369%define IA32_MTRR_PHYSBASE2 0x204
370%define IA32_MTRR_PHYSMASK2 0x205
371%define IA32_MTRR_PHYSBASE3 0x206
372%define IA32_MTRR_PHYSMASK3 0x207
373%define IA32_MTRR_PHYSBASE4 0x208
374%define IA32_MTRR_PHYSMASK4 0x209
375%define IA32_MTRR_PHYSBASE5 0x20a
376%define IA32_MTRR_PHYSMASK5 0x20b
377%define IA32_MTRR_PHYSBASE6 0x20c
378%define IA32_MTRR_PHYSMASK6 0x20d
379%define IA32_MTRR_PHYSBASE7 0x20e
380%define IA32_MTRR_PHYSMASK7 0x20f
381%define IA32_MTRR_PHYSBASE8 0x210
382%define IA32_MTRR_PHYSMASK8 0x211
383%define IA32_MTRR_PHYSBASE9 0x212
384%define IA32_MTRR_PHYSMASK9 0x213
385%define IA32_MTRR_FIX64K_00000 0x250
386%define IA32_MTRR_FIX16K_80000 0x258
387%define IA32_MTRR_FIX16K_A0000 0x259
388%define IA32_MTRR_FIX4K_C0000 0x268
389%define IA32_MTRR_FIX4K_C8000 0x269
390%define IA32_MTRR_FIX4K_D0000 0x26a
391%define IA32_MTRR_FIX4K_D8000 0x26b
392%define IA32_MTRR_FIX4K_E0000 0x26c
393%define IA32_MTRR_FIX4K_E8000 0x26d
394%define IA32_MTRR_FIX4K_F0000 0x26e
395%define IA32_MTRR_FIX4K_F8000 0x26f
396%define MSR_IA32_MTRR_DEF_TYPE 0x2FF
397%define MSR_IA32_MC0_CTL 0x400
398%define MSR_IA32_MC0_STATUS 0x401
399%define MSR_IA32_VMX_BASIC_INFO 0x480
400%define MSR_IA32_VMX_PINBASED_CTLS 0x481
401%define MSR_IA32_VMX_PROCBASED_CTLS 0x482
402%define MSR_IA32_VMX_EXIT_CTLS 0x483
403%define MSR_IA32_VMX_ENTRY_CTLS 0x484
404%define MSR_IA32_VMX_MISC 0x485
405%define MSR_IA32_VMX_CR0_FIXED0 0x486
406%define MSR_IA32_VMX_CR0_FIXED1 0x487
407%define MSR_IA32_VMX_CR4_FIXED0 0x488
408%define MSR_IA32_VMX_CR4_FIXED1 0x489
409%define MSR_IA32_VMX_VMCS_ENUM 0x48A
410%define MSR_IA32_VMX_VMFUNC 0x491
411%define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
412%define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
413%define MSR_IA32_DS_AREA 0x600
414%define MSR_RAPL_POWER_UNIT 0x606
415%define MSR_IA32_X2APIC_START 0x800
416%define MSR_IA32_X2APIC_TPR 0x808
417%define MSR_IA32_X2APIC_END 0xBFF
418%define MSR_K6_EFER 0xc0000080
419%define MSR_K6_EFER_SCE RT_BIT(0)
420%define MSR_K6_EFER_LME RT_BIT(8)
421%define MSR_K6_EFER_LMA RT_BIT(10)
422%define MSR_K6_EFER_NXE RT_BIT(11)
423%define MSR_K6_EFER_SVME RT_BIT(12)
424%define MSR_K6_EFER_LMSLE RT_BIT(13)
425%define MSR_K6_EFER_FFXSR RT_BIT(14)
426%define MSR_K6_EFER_TCE RT_BIT(15)
427%define MSR_K6_STAR 0xc0000081
428%define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
429%define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
430%define MSR_K6_STAR_SEL_MASK 0xffff
431%define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
432%define MSR_K6_WHCR 0xc0000082
433%define MSR_K6_UWCCR 0xc0000085
434%define MSR_K6_PSOR 0xc0000087
435%define MSR_K6_PFIR 0xc0000088
436%define MSR_K7_EVNTSEL0 0xc0010000
437%define MSR_K7_EVNTSEL1 0xc0010001
438%define MSR_K7_EVNTSEL2 0xc0010002
439%define MSR_K7_EVNTSEL3 0xc0010003
440%define MSR_K7_PERFCTR0 0xc0010004
441%define MSR_K7_PERFCTR1 0xc0010005
442%define MSR_K7_PERFCTR2 0xc0010006
443%define MSR_K7_PERFCTR3 0xc0010007
444%define MSR_K8_LSTAR 0xc0000082
445%define MSR_K8_CSTAR 0xc0000083
446%define MSR_K8_SF_MASK 0xc0000084
447%define MSR_K8_FS_BASE 0xc0000100
448%define MSR_K8_GS_BASE 0xc0000101
449%define MSR_K8_KERNEL_GS_BASE 0xc0000102
450%define MSR_K8_TSC_AUX 0xc0000103
451%define MSR_K8_SYSCFG 0xc0010010
452%define MSR_K8_HWCR 0xc0010015
453%define MSR_K8_IORRBASE0 0xc0010016
454%define MSR_K8_IORRMASK0 0xc0010017
455%define MSR_K8_IORRBASE1 0xc0010018
456%define MSR_K8_IORRMASK1 0xc0010019
457%define MSR_K8_TOP_MEM1 0xc001001a
458%define MSR_K8_TOP_MEM2 0xc001001d
459%define MSR_K8_NB_CFG 0xc001001f
460%define MSR_K8_INT_PENDING 0xc0010055
461%define MSR_K8_VM_CR 0xc0010114
462%define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
463%define MSR_K8_IGNNE 0xc0010115
464%define MSR_K8_SMM_CTL 0xc0010116
465%define MSR_K8_VM_HSAVE_PA 0xc0010117
466%define X86_PG_ENTRIES 1024
467%define X86_PG_PAE_ENTRIES 512
468%define X86_PG_PAE_PDPE_ENTRIES 4
469%define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
470%define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
471%define X86_PAGE_4K_SIZE _4K
472%define X86_PAGE_4K_SHIFT 12
473%define X86_PAGE_4K_OFFSET_MASK 0xfff
474%define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000
475%define X86_PAGE_4K_BASE_MASK_32 0xfffff000
476%define X86_PAGE_2M_SIZE _2M
477%define X86_PAGE_2M_SHIFT 21
478%define X86_PAGE_2M_OFFSET_MASK 0x001fffff
479%define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000
480%define X86_PAGE_2M_BASE_MASK_32 0xffe00000
481%define X86_PAGE_4M_SIZE _4M
482%define X86_PAGE_4M_SHIFT 22
483%define X86_PAGE_4M_OFFSET_MASK 0x003fffff
484%define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000
485%define X86_PAGE_4M_BASE_MASK_32 0xffc00000
486%define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + 0x800000000000 < UINT64_C(0x1000000000000))
487%define X86_PTE_BIT_P 0
488%define X86_PTE_BIT_RW 1
489%define X86_PTE_BIT_US 2
490%define X86_PTE_BIT_PWT 3
491%define X86_PTE_BIT_PCD 4
492%define X86_PTE_BIT_A 5
493%define X86_PTE_BIT_D 6
494%define X86_PTE_BIT_PAT 7
495%define X86_PTE_BIT_G 8
496%define X86_PTE_P RT_BIT(0)
497%define X86_PTE_RW RT_BIT(1)
498%define X86_PTE_US RT_BIT(2)
499%define X86_PTE_PWT RT_BIT(3)
500%define X86_PTE_PCD RT_BIT(4)
501%define X86_PTE_A RT_BIT(5)
502%define X86_PTE_D RT_BIT(6)
503%define X86_PTE_PAT RT_BIT(7)
504%define X86_PTE_G RT_BIT(8)
505%define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
506%define X86_PTE_PG_MASK ( 0xfffff000 )
507%define X86_PTE_PAE_PG_MASK 0x000ffffffffff000
508%define X86_PTE_PAE_NX RT_BIT_64(63)
509%define X86_PTE_PAE_MBZ_MASK_NX 0x7ff0000000000000
510%define X86_PTE_PAE_MBZ_MASK_NO_NX 0xfff0000000000000
511%define X86_PTE_LM_MBZ_MASK_NX 0x0000000000000000
512%define X86_PTE_LM_MBZ_MASK_NO_NX 0x8000000000000000
513%define X86_PT_SHIFT 12
514%define X86_PT_MASK 0x3ff
515%define X86_PT_PAE_SHIFT 12
516%define X86_PT_PAE_MASK 0x1ff
517%define X86_PDE_P RT_BIT(0)
518%define X86_PDE_RW RT_BIT(1)
519%define X86_PDE_US RT_BIT(2)
520%define X86_PDE_PWT RT_BIT(3)
521%define X86_PDE_PCD RT_BIT(4)
522%define X86_PDE_A RT_BIT(5)
523%define X86_PDE_PS RT_BIT(7)
524%define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
525%define X86_PDE_PG_MASK ( 0xfffff000 )
526%define X86_PDE_PAE_PG_MASK 0x000ffffffffff000
527%define X86_PDE_PAE_NX RT_BIT_64(63)
528%define X86_PDE_PAE_MBZ_MASK_NX 0x7ff0000000000080
529%define X86_PDE_PAE_MBZ_MASK_NO_NX 0xfff0000000000080
530%define X86_PDE_LM_MBZ_MASK_NX 0x0000000000000080
531%define X86_PDE_LM_MBZ_MASK_NO_NX 0x8000000000000080
532%define X86_PDE4M_P RT_BIT(0)
533%define X86_PDE4M_RW RT_BIT(1)
534%define X86_PDE4M_US RT_BIT(2)
535%define X86_PDE4M_PWT RT_BIT(3)
536%define X86_PDE4M_PCD RT_BIT(4)
537%define X86_PDE4M_A RT_BIT(5)
538%define X86_PDE4M_D RT_BIT(6)
539%define X86_PDE4M_PS RT_BIT(7)
540%define X86_PDE4M_G RT_BIT(8)
541%define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
542%define X86_PDE4M_PAT RT_BIT(12)
543%define X86_PDE4M_PAT_SHIFT (12 - 7)
544%define X86_PDE4M_PG_MASK ( 0xffc00000 )
545%define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
546%define X86_PDE4M_PG_HIGH_SHIFT 19
547%define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
548%define X86_PDE2M_PAE_PG_MASK 0x000fffffffe00000
549%define X86_PDE2M_PAE_NX RT_BIT_64(63)
550%define X86_PDE2M_PAE_MBZ_MASK_NX 0x7ff00000001fe000
551%define X86_PDE2M_PAE_MBZ_MASK_NO_NX 0xfff00000001fe000
552%define X86_PDE2M_LM_MBZ_MASK_NX 0x00000000001fe000
553%define X86_PDE2M_LM_MBZ_MASK_NO_NX 0x80000000001fe000
554%define X86_PD_SHIFT 22
555%define X86_PD_MASK 0x3ff
556%define X86_PD_PAE_SHIFT 21
557%define X86_PD_PAE_MASK 0x1ff
558%define X86_PDPE_P RT_BIT(0)
559%define X86_PDPE_RW RT_BIT(1)
560%define X86_PDPE_US RT_BIT(2)
561%define X86_PDPE_PWT RT_BIT(3)
562%define X86_PDPE_PCD RT_BIT(4)
563%define X86_PDPE_A RT_BIT(5)
564%define X86_PDPE_LM_PS RT_BIT(7)
565%define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
566%define X86_PDPE_PG_MASK 0x000ffffffffff000
567%define X86_PDPE_PAE_MBZ_MASK 0xfff00000000001e6
568%define X86_PDPE_LM_NX RT_BIT_64(63)
569%define X86_PDPE_LM_MBZ_MASK_NX 0x0000000000000180
570%define X86_PDPE_LM_MBZ_MASK_NO_NX 0x8000000000000180
571%define X86_PDPE1G_LM_MBZ_MASK_NX 0x000000003fffe000
572%define X86_PDPE1G_LM_MBZ_MASK_NO_NX 0x800000003fffe000
573%define X86_PDPT_SHIFT 30
574%define X86_PDPT_MASK_PAE 0x3
575%define X86_PDPT_MASK_AMD64 0x1ff
576%define X86_PML4E_P RT_BIT(0)
577%define X86_PML4E_RW RT_BIT(1)
578%define X86_PML4E_US RT_BIT(2)
579%define X86_PML4E_PWT RT_BIT(3)
580%define X86_PML4E_PCD RT_BIT(4)
581%define X86_PML4E_A RT_BIT(5)
582%define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
583%define X86_PML4E_PG_MASK 0x000ffffffffff000
584%define X86_PML4E_MBZ_MASK_NX 0x0000000000000080
585%define X86_PML4E_MBZ_MASK_NO_NX 0x8000000000000080
586%define X86_PML4E_NX RT_BIT_64(63)
587%define X86_PML4_SHIFT 39
588%define X86_PML4_MASK 0x1ff
589%define X86_OFF_FXSTATE_RSVD 0x1d0
590%define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
591%define X86_FSW_IE RT_BIT(0)
592%define X86_FSW_DE RT_BIT(1)
593%define X86_FSW_ZE RT_BIT(2)
594%define X86_FSW_OE RT_BIT(3)
595%define X86_FSW_UE RT_BIT(4)
596%define X86_FSW_PE RT_BIT(5)
597%define X86_FSW_SF RT_BIT(6)
598%define X86_FSW_ES RT_BIT(7)
599%define X86_FSW_XCPT_MASK 0x007f
600%define X86_FSW_XCPT_ES_MASK 0x00ff
601%define X86_FSW_C0 RT_BIT(8)
602%define X86_FSW_C1 RT_BIT(9)
603%define X86_FSW_C2 RT_BIT(10)
604%define X86_FSW_TOP_MASK 0x3800
605%define X86_FSW_TOP_SHIFT 11
606%define X86_FSW_TOP_SMASK 0x0007
607%define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
608%define X86_FSW_C3 RT_BIT(14)
609%define X86_FSW_C_MASK 0x4700
610%define X86_FSW_B RT_BIT(15)
611%define X86_FCW_IM RT_BIT(0)
612%define X86_FCW_DM RT_BIT(1)
613%define X86_FCW_ZM RT_BIT(2)
614%define X86_FCW_OM RT_BIT(3)
615%define X86_FCW_UM RT_BIT(4)
616%define X86_FCW_PM RT_BIT(5)
617%define X86_FCW_MASK_ALL 0x007f
618%define X86_FCW_XCPT_MASK 0x003f
619%define X86_FCW_PC_MASK 0x0300
620%define X86_FCW_PC_24 0x0000
621%define X86_FCW_PC_RSVD 0x0100
622%define X86_FCW_PC_53 0x0200
623%define X86_FCW_PC_64 0x0300
624%define X86_FCW_RC_MASK 0x0c00
625%define X86_FCW_RC_NEAREST 0x0000
626%define X86_FCW_RC_DOWN 0x0400
627%define X86_FCW_RC_UP 0x0800
628%define X86_FCW_RC_ZERO 0x0c00
629%define X86_FCW_ZERO_MASK 0xf080
630%define X86_MXSCR_IE RT_BIT(0)
631%define X86_MXSCR_DE RT_BIT(1)
632%define X86_MXSCR_ZE RT_BIT(2)
633%define X86_MXSCR_OE RT_BIT(3)
634%define X86_MXSCR_UE RT_BIT(4)
635%define X86_MXSCR_PE RT_BIT(5)
636%define X86_MXSCR_DAZ RT_BIT(6)
637%define X86_MXSCR_IM RT_BIT(7)
638%define X86_MXSCR_DM RT_BIT(8)
639%define X86_MXSCR_ZM RT_BIT(9)
640%define X86_MXSCR_OM RT_BIT(10)
641%define X86_MXSCR_UM RT_BIT(11)
642%define X86_MXSCR_PM RT_BIT(12)
643%define X86_MXSCR_RC_MASK 0x6000
644%define X86_MXSCR_RC_NEAREST 0x0000
645%define X86_MXSCR_RC_DOWN 0x2000
646%define X86_MXSCR_RC_UP 0x4000
647%define X86_MXSCR_RC_ZERO 0x6000
648%define X86_MXSCR_FZ RT_BIT(15)
649%define X86_MXSCR_MM RT_BIT(17)
650%ifndef VBOX_FOR_DTRACE_LIB
651%endif
652%define X86DESCATTR_TYPE 0x0000000f
653%define X86DESCATTR_DT 0x00000010
654%define X86DESCATTR_DPL 0x00000060
655%define X86DESCATTR_DPL_SHIFT 5
656%define X86DESCATTR_P 0x00000080
657%define X86DESCATTR_LIMIT_HIGH 0x00000f00
658%define X86DESCATTR_AVL 0x00001000
659%define X86DESCATTR_L 0x00002000
660%define X86DESCATTR_D 0x00004000
661%define X86DESCATTR_G 0x00008000
662%define X86DESCATTR_UNUSABLE 0x00010000
663%ifndef VBOX_FOR_DTRACE_LIB
664%endif
665%ifndef VBOX_FOR_DTRACE_LIB
666%define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0)
667%define X86DESCGENERIC_BIT_OFF_BASE_LOW (16)
668%define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32)
669%define X86DESCGENERIC_BIT_OFF_TYPE (40)
670%define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44)
671%define X86DESCGENERIC_BIT_OFF_DPL (45)
672%define X86DESCGENERIC_BIT_OFF_PRESENT (47)
673%define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48)
674%define X86DESCGENERIC_BIT_OFF_AVAILABLE (52)
675%define X86DESCGENERIC_BIT_OFF_LONG (53)
676%define X86DESCGENERIC_BIT_OFF_DEF_BIG (54)
677%define X86DESCGENERIC_BIT_OFF_GRANULARITY (55)
678%define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56)
679%endif
680%ifndef VBOX_FOR_DTRACE_LIB
681%endif
682%ifndef VBOX_FOR_DTRACE_LIB
683%endif
684%ifndef VBOX_FOR_DTRACE_LIB
685%endif
686%ifndef VBOX_FOR_DTRACE_LIB
687%endif
688%ifndef VBOX_FOR_DTRACE_LIB
689%endif
690%if HC_ARCH_BITS == 64
691%else
692%endif
693%if HC_ARCH_BITS == 64
694%else
695%endif
696%if HC_ARCH_BITS == 64
697%else
698%endif
699%define X86_SEL_TYPE_CODE 8
700%define X86_SEL_TYPE_MEMORY RT_BIT(4)
701%define X86_SEL_TYPE_ACCESSED 1
702%define X86_SEL_TYPE_DOWN 4
703%define X86_SEL_TYPE_CONF 4
704%define X86_SEL_TYPE_WRITE 2
705%define X86_SEL_TYPE_READ 2
706%define X86_SEL_TYPE_READ_BIT 1
707%define X86_SEL_TYPE_RO 0
708%define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
709%define X86_SEL_TYPE_RW 2
710%define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
711%define X86_SEL_TYPE_RO_DOWN 4
712%define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
713%define X86_SEL_TYPE_RW_DOWN 6
714%define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
715%define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
716%define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
717%define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
718%define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
719%define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
720%define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
721%define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
722%define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
723%define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
724%define X86_SEL_TYPE_SYS_UNDEFINED 0
725%define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
726%define X86_SEL_TYPE_SYS_LDT 2
727%define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
728%define X86_SEL_TYPE_SYS_286_CALL_GATE 4
729%define X86_SEL_TYPE_SYS_TASK_GATE 5
730%define X86_SEL_TYPE_SYS_286_INT_GATE 6
731%define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
732%define X86_SEL_TYPE_SYS_UNDEFINED2 8
733%define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
734%define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
735%define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
736%define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
737%define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
738%define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
739%define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
740%define AMD64_SEL_TYPE_SYS_LDT 2
741%define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
742%define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
743%define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
744%define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
745%define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
746%define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
747%define X86_DESC_S RT_BIT(12)
748%define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
749%define X86_DESC_P RT_BIT(15)
750%define X86_DESC_AVL RT_BIT(20)
751%define X86_DESC_DB RT_BIT(22)
752%define X86_DESC_G RT_BIT(23)
753%define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
754%define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
755%ifndef VBOX_FOR_DTRACE_LIB
756%endif
757%ifndef VBOX_FOR_DTRACE_LIB
758%endif
759%define X86_SEL_SHIFT 3
760%define X86_SEL_MASK 0xfff8
761%define X86_SEL_MASK_OFF_RPL 0xfffc
762%define X86_SEL_LDT 0x0004
763%define X86_SEL_RPL 0x0003
764%define X86_SEL_RPL_LDT 0x0007
765%define X86_XCPT_MAX (X86_XCPT_SX)
766%define X86_TRAP_ERR_EXTERNAL 1
767%define X86_TRAP_ERR_IDT 2
768%define X86_TRAP_ERR_TI 4
769%define X86_TRAP_ERR_SEL_MASK 0xfff8
770%define X86_TRAP_ERR_SEL_SHIFT 3
771%define X86_TRAP_PF_P RT_BIT(0)
772%define X86_TRAP_PF_RW RT_BIT(1)
773%define X86_TRAP_PF_US RT_BIT(2)
774%define X86_TRAP_PF_RSVD RT_BIT(3)
775%define X86_TRAP_PF_ID RT_BIT(4)
776%ifndef VBOX_FOR_DTRACE_LIB
777%else
778%endif
779%ifndef VBOX_FOR_DTRACE_LIB
780%else
781%endif
782%define X86_MODRM_RM_MASK 0x07
783%define X86_MODRM_REG_MASK 0x38
784%define X86_MODRM_REG_SMASK 0x07
785%define X86_MODRM_REG_SHIFT 3
786%define X86_MODRM_MOD_MASK 0xc0
787%define X86_MODRM_MOD_SMASK 0x03
788%define X86_MODRM_MOD_SHIFT 6
789%ifndef VBOX_FOR_DTRACE_LIB
790%endif
791%define X86_SIB_BASE_MASK 0x07
792%define X86_SIB_INDEX_MASK 0x38
793%define X86_SIB_INDEX_SMASK 0x07
794%define X86_SIB_INDEX_SHIFT 3
795%define X86_SIB_SCALE_MASK 0xc0
796%define X86_SIB_SCALE_SMASK 0x03
797%define X86_SIB_SCALE_SHIFT 6
798%ifndef VBOX_FOR_DTRACE_LIB
799%endif
800%define X86_GREG_xAX 0
801%define X86_GREG_xCX 1
802%define X86_GREG_xDX 2
803%define X86_GREG_xBX 3
804%define X86_GREG_xSP 4
805%define X86_GREG_xBP 5
806%define X86_GREG_xSI 6
807%define X86_GREG_xDI 7
808%define X86_GREG_x8 8
809%define X86_GREG_x9 9
810%define X86_GREG_x10 10
811%define X86_GREG_x11 11
812%define X86_GREG_x12 12
813%define X86_GREG_x13 13
814%define X86_GREG_x14 14
815%define X86_GREG_x15 15
816%define X86_SREG_ES 0
817%define X86_SREG_CS 1
818%define X86_SREG_SS 2
819%define X86_SREG_DS 3
820%define X86_SREG_FS 4
821%define X86_SREG_GS 5
822%define X86_SREG_COUNT 6
823%define X86_OP_PRF_CS 0x2e
824%define X86_OP_PRF_SS 0x36
825%define X86_OP_PRF_DS 0x3e
826%define X86_OP_PRF_ES 0x26
827%define X86_OP_PRF_FS 0x64
828%define X86_OP_PRF_GS 0x65
829%define X86_OP_PRF_SIZE_OP 0x66
830%define X86_OP_PRF_SIZE_ADDR 0x67
831%define X86_OP_PRF_LOCK 0xf0
832%define X86_OP_PRF_REPZ 0xf2
833%define X86_OP_PRF_REPNZ 0xf3
834%define X86_OP_REX_B 0x41
835%define X86_OP_REX_X 0x42
836%define X86_OP_REX_R 0x44
837%define X86_OP_REX_W 0x48
838%endif
839%include "iprt/x86extra.mac"
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