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source: vbox/trunk/include/iprt/x86.mac@ 47356

Last change on this file since 47356 was 47305, checked in by vboxsync, 11 years ago

x86.h/mac: opcode prefixes.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 34.5 KB
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1%ifndef ___iprt_x86_h
2%define ___iprt_x86_h
3%ifndef VBOX_FOR_DTRACE_LIB
4%else
5%endif
6%ifdef RT_OS_SOLARIS
7%endif
8%ifndef VBOX_FOR_DTRACE_LIB
9%endif
10%ifndef VBOX_FOR_DTRACE_LIB
11%endif
12%ifndef VBOX_FOR_DTRACE_LIB
13%endif
14%define X86_EFL_CF RT_BIT(0)
15%define X86_EFL_1 RT_BIT(1)
16%define X86_EFL_PF RT_BIT(2)
17%define X86_EFL_AF RT_BIT(4)
18%define X86_EFL_ZF RT_BIT(6)
19%define X86_EFL_SF RT_BIT(7)
20%define X86_EFL_TF RT_BIT(8)
21%define X86_EFL_IF RT_BIT(9)
22%define X86_EFL_DF RT_BIT(10)
23%define X86_EFL_OF RT_BIT(11)
24%define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
25%define X86_EFL_NT RT_BIT(14)
26%define X86_EFL_RF RT_BIT(16)
27%define X86_EFL_VM RT_BIT(17)
28%define X86_EFL_AC RT_BIT(18)
29%define X86_EFL_VIF RT_BIT(19)
30%define X86_EFL_VIP RT_BIT(20)
31%define X86_EFL_ID RT_BIT(21)
32%define X86_EFL_IOPL_SHIFT 12
33%define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
34%define X86_EFL_POPF_BITS (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID)
35%ifndef VBOX_FOR_DTRACE_LIB
36%else
37%endif
38%ifndef VBOX_FOR_DTRACE_LIB
39%else
40%endif
41%define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547
42%define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e
43%define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69
44%define X86_CPUID_VENDOR_AMD_EBX 0x68747541
45%define X86_CPUID_VENDOR_AMD_ECX 0x444d4163
46%define X86_CPUID_VENDOR_AMD_EDX 0x69746e65
47%define X86_CPUID_VENDOR_VIA_EBX 0x746e6543
48%define X86_CPUID_VENDOR_VIA_ECX 0x736c7561
49%define X86_CPUID_VENDOR_VIA_EDX 0x48727561
50%define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
51%define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
52%define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
53%define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
54%define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
55%define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
56%define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
57%define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
58%define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
59%define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
60%define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
61%define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
62%define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
63%define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
64%define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
65%define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
66%define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
67%define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
68%define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
69%define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
70%define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
71%define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
72%define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
73%define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
74%define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
75%define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
76%define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
77%define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
78%define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
79%define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
80%define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
81%define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
82%define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
83%define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
84%define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
85%define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
86%define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
87%define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
88%define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
89%define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
90%define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
91%define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
92%define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
93%define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
94%define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
95%define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
96%define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
97%define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
98%define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
99%define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
100%define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
101%define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
102%define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
103%define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
104%define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
105%define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
106%define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
107%define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
108%define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
109%define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
110%define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
111%define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
112%define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
113%define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
114%define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
115%define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
116%define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
117%define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
118%define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
119%define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
120%define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
121%define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
122%define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
123%define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
124%define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
125%define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
126%define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
127%define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
128%define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
129%define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
130%define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
131%define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
132%define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
133%define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
134%define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
135%define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
136%define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
137%define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
138%define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
139%define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
140%define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
141%define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
142%define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
143%define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
144%define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
145%define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
146%define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
147%define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
148%define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
149%define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
150%define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
151%define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
152%define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
153%define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
154%define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
155%define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
156%define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
157%define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
158%define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
159%define X86_CR0_PE RT_BIT(0)
160%define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
161%define X86_CR0_MP RT_BIT(1)
162%define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
163%define X86_CR0_EM RT_BIT(2)
164%define X86_CR0_EMULATE_FPU RT_BIT(2)
165%define X86_CR0_TS RT_BIT(3)
166%define X86_CR0_TASK_SWITCH RT_BIT(3)
167%define X86_CR0_ET RT_BIT(4)
168%define X86_CR0_EXTENSION_TYPE RT_BIT(4)
169%define X86_CR0_NE RT_BIT(5)
170%define X86_CR0_NUMERIC_ERROR RT_BIT(5)
171%define X86_CR0_WP RT_BIT(16)
172%define X86_CR0_WRITE_PROTECT RT_BIT(16)
173%define X86_CR0_AM RT_BIT(18)
174%define X86_CR0_ALIGMENT_MASK RT_BIT(18)
175%define X86_CR0_NW RT_BIT(29)
176%define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
177%define X86_CR0_CD RT_BIT(30)
178%define X86_CR0_CACHE_DISABLE RT_BIT(30)
179%define X86_CR0_PG RT_BIT(31)
180%define X86_CR0_PAGING RT_BIT(31)
181%define X86_CR3_PWT RT_BIT(3)
182%define X86_CR3_PCD RT_BIT(4)
183%define X86_CR3_PAGE_MASK (0xfffff000)
184%define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
185%define X86_CR3_AMD64_PAGE_MASK 0x000ffffffffff000
186%define X86_CR4_VME RT_BIT(0)
187%define X86_CR4_PVI RT_BIT(1)
188%define X86_CR4_TSD RT_BIT(2)
189%define X86_CR4_DE RT_BIT(3)
190%define X86_CR4_PSE RT_BIT(4)
191%define X86_CR4_PAE RT_BIT(5)
192%define X86_CR4_MCE RT_BIT(6)
193%define X86_CR4_PGE RT_BIT(7)
194%define X86_CR4_PCE RT_BIT(8)
195%define X86_CR4_OSFSXR RT_BIT(9)
196%define X86_CR4_OSXMMEEXCPT RT_BIT(10)
197%define X86_CR4_VMXE RT_BIT(13)
198%define X86_CR4_SMXE RT_BIT(14)
199%define X86_CR4_PCIDE RT_BIT(17)
200%define X86_CR4_OSXSAVE RT_BIT(18)
201%define X86_CR4_SMEP RT_BIT(20)
202%define X86_DR6_B0 RT_BIT(0)
203%define X86_DR6_B1 RT_BIT(1)
204%define X86_DR6_B2 RT_BIT(2)
205%define X86_DR6_B3 RT_BIT(3)
206%define X86_DR6_BD RT_BIT(13)
207%define X86_DR6_BS RT_BIT(14)
208%define X86_DR6_BT RT_BIT(15)
209%define X86_DR6_INIT_VAL 0xFFFF0FF0
210%define X86_DR7_L0 RT_BIT(0)
211%define X86_DR7_G0 RT_BIT(1)
212%define X86_DR7_L1 RT_BIT(2)
213%define X86_DR7_G1 RT_BIT(3)
214%define X86_DR7_L2 RT_BIT(4)
215%define X86_DR7_G2 RT_BIT(5)
216%define X86_DR7_L3 RT_BIT(6)
217%define X86_DR7_G3 RT_BIT(7)
218%define X86_DR7_LE RT_BIT(8)
219%define X86_DR7_GE RT_BIT(9)
220%define X86_DR7_GD RT_BIT(13)
221%define X86_DR7_RW0_MASK (3 << 16)
222%define X86_DR7_LEN0_MASK (3 << 18)
223%define X86_DR7_RW1_MASK (3 << 20)
224%define X86_DR7_LEN1_MASK (3 << 22)
225%define X86_DR7_RW2_MASK (3 << 24)
226%define X86_DR7_LEN2_MASK (3 << 26)
227%define X86_DR7_RW3_MASK (3 << 28)
228%define X86_DR7_LEN3_MASK (3 << 30)
229%define X86_DR7_MB1_MASK (RT_BIT(10))
230%define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
231%define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
232%define X86_DR7_RW_EO 0
233%define X86_DR7_RW_WO 1
234%define X86_DR7_RW_IO 2
235%define X86_DR7_RW_RW 3
236%define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
237%define X86_DR7_LEN_BYTE 0
238%define X86_DR7_LEN_WORD 1
239%define X86_DR7_LEN_QWORD 2
240%define X86_DR7_LEN_DWORD 3
241%define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
242%define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3)
243%define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7))
244%define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) | X86_DR7_RW(1, X86_DR7_RW_IO) | X86_DR7_RW(2, X86_DR7_RW_IO) | X86_DR7_RW(3, X86_DR7_RW_IO))
245%define X86_DR7_INIT_VAL 0x400
246%define MSR_IA32_TSC 0x10
247%define MSR_IA32_PLATFORM_ID 0x17
248%ifndef MSR_IA32_APICBASE
249%define MSR_IA32_APICBASE 0x1b
250%endif
251%define MSR_IA32_FEATURE_CONTROL 0x3A
252%define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
253%define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
254%define MSR_IA32_BIOS_UPDT_TRIG 0x79
255%define MSR_IA32_BIOS_SIGN_ID 0x8B
256%define MSR_IA32_PMC0 0xC1
257%define MSR_IA32_PMC1 0xC2
258%define MSR_IA32_PMC2 0xC3
259%define MSR_IA32_PMC3 0xC4
260%define MSR_IA32_PLATFORM_INFO 0xCE
261%define MSR_IA32_FSB_CLOCK_STS 0xCD
262%define MSR_IA32_MTRR_CAP 0xFE
263%ifndef MSR_IA32_SYSENTER_CS
264%define MSR_IA32_SYSENTER_CS 0x174
265%define MSR_IA32_SYSENTER_ESP 0x175
266%define MSR_IA32_SYSENTER_EIP 0x176
267%endif
268%define MSR_IA32_MCP_CAP 0x179
269%define MSR_IA32_MCP_STATUS 0x17A
270%define MSR_IA32_MCP_CTRL 0x17B
271%define MSR_IA32_DEBUGCTL 0x1D9
272%define MSR_IA32_CR_PAT 0x277
273%define MSR_IA32_PERFEVTSEL0 0x186
274%define MSR_IA32_PERFEVTSEL1 0x187
275%define MSR_IA32_FLEX_RATIO 0x194
276%define MSR_IA32_PERF_STATUS 0x198
277%define MSR_IA32_PERF_CTL 0x199
278%define MSR_IA32_THERM_STATUS 0x19c
279%define MSR_IA32_MISC_ENABLE 0x1A0
280%define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
281%define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
282%define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
283%define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
284%define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
285%define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
286%define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
287%define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
288%define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
289%define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
290%define IA32_MTRR_PHYSBASE0 0x200
291%define IA32_MTRR_PHYSMASK0 0x201
292%define IA32_MTRR_PHYSBASE1 0x202
293%define IA32_MTRR_PHYSMASK1 0x203
294%define IA32_MTRR_PHYSBASE2 0x204
295%define IA32_MTRR_PHYSMASK2 0x205
296%define IA32_MTRR_PHYSBASE3 0x206
297%define IA32_MTRR_PHYSMASK3 0x207
298%define IA32_MTRR_PHYSBASE4 0x208
299%define IA32_MTRR_PHYSMASK4 0x209
300%define IA32_MTRR_PHYSBASE5 0x20a
301%define IA32_MTRR_PHYSMASK5 0x20b
302%define IA32_MTRR_PHYSBASE6 0x20c
303%define IA32_MTRR_PHYSMASK6 0x20d
304%define IA32_MTRR_PHYSBASE7 0x20e
305%define IA32_MTRR_PHYSMASK7 0x20f
306%define IA32_MTRR_PHYSBASE8 0x210
307%define IA32_MTRR_PHYSMASK8 0x211
308%define IA32_MTRR_PHYSBASE9 0x212
309%define IA32_MTRR_PHYSMASK9 0x213
310%define IA32_MTRR_FIX64K_00000 0x250
311%define IA32_MTRR_FIX16K_80000 0x258
312%define IA32_MTRR_FIX16K_A0000 0x259
313%define IA32_MTRR_FIX4K_C0000 0x268
314%define IA32_MTRR_FIX4K_C8000 0x269
315%define IA32_MTRR_FIX4K_D0000 0x26a
316%define IA32_MTRR_FIX4K_D8000 0x26b
317%define IA32_MTRR_FIX4K_E0000 0x26c
318%define IA32_MTRR_FIX4K_E8000 0x26d
319%define IA32_MTRR_FIX4K_F0000 0x26e
320%define IA32_MTRR_FIX4K_F8000 0x26f
321%define MSR_IA32_MTRR_DEF_TYPE 0x2FF
322%define MSR_IA32_MC0_CTL 0x400
323%define MSR_IA32_MC0_STATUS 0x401
324%define MSR_IA32_VMX_BASIC_INFO 0x480
325%define MSR_IA32_VMX_PINBASED_CTLS 0x481
326%define MSR_IA32_VMX_PROCBASED_CTLS 0x482
327%define MSR_IA32_VMX_EXIT_CTLS 0x483
328%define MSR_IA32_VMX_ENTRY_CTLS 0x484
329%define MSR_IA32_VMX_MISC 0x485
330%define MSR_IA32_VMX_CR0_FIXED0 0x486
331%define MSR_IA32_VMX_CR0_FIXED1 0x487
332%define MSR_IA32_VMX_CR4_FIXED0 0x488
333%define MSR_IA32_VMX_CR4_FIXED1 0x489
334%define MSR_IA32_VMX_VMCS_ENUM 0x48A
335%define MSR_IA32_VMX_VMFUNC 0x491
336%define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
337%define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
338%define MSR_IA32_DS_AREA 0x600
339%define MSR_IA32_X2APIC_START 0x800
340%define MSR_IA32_X2APIC_TPR 0x808
341%define MSR_IA32_X2APIC_END 0xBFF
342%define MSR_K6_EFER 0xc0000080
343%define MSR_K6_EFER_SCE RT_BIT(0)
344%define MSR_K6_EFER_LME RT_BIT(8)
345%define MSR_K6_EFER_LMA RT_BIT(10)
346%define MSR_K6_EFER_NXE RT_BIT(11)
347%define MSR_K6_EFER_SVME RT_BIT(12)
348%define MSR_K6_EFER_LMSLE RT_BIT(13)
349%define MSR_K6_EFER_FFXSR RT_BIT(14)
350%define MSR_K6_STAR 0xc0000081
351%define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
352%define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
353%define MSR_K6_STAR_SEL_MASK 0xffff
354%define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
355%define MSR_K6_WHCR 0xc0000082
356%define MSR_K6_UWCCR 0xc0000085
357%define MSR_K6_PSOR 0xc0000087
358%define MSR_K6_PFIR 0xc0000088
359%define MSR_K7_EVNTSEL0 0xc0010000
360%define MSR_K7_EVNTSEL1 0xc0010001
361%define MSR_K7_EVNTSEL2 0xc0010002
362%define MSR_K7_EVNTSEL3 0xc0010003
363%define MSR_K7_PERFCTR0 0xc0010004
364%define MSR_K7_PERFCTR1 0xc0010005
365%define MSR_K7_PERFCTR2 0xc0010006
366%define MSR_K7_PERFCTR3 0xc0010007
367%define MSR_K8_LSTAR 0xc0000082
368%define MSR_K8_CSTAR 0xc0000083
369%define MSR_K8_SF_MASK 0xc0000084
370%define MSR_K8_FS_BASE 0xc0000100
371%define MSR_K8_GS_BASE 0xc0000101
372%define MSR_K8_KERNEL_GS_BASE 0xc0000102
373%define MSR_K8_TSC_AUX 0xc0000103
374%define MSR_K8_SYSCFG 0xc0010010
375%define MSR_K8_HWCR 0xc0010015
376%define MSR_K8_IORRBASE0 0xc0010016
377%define MSR_K8_IORRMASK0 0xc0010017
378%define MSR_K8_IORRBASE1 0xc0010018
379%define MSR_K8_IORRMASK1 0xc0010019
380%define MSR_K8_TOP_MEM1 0xc001001a
381%define MSR_K8_TOP_MEM2 0xc001001d
382%define MSR_K8_VM_CR 0xc0010114
383%define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
384%define MSR_K8_IGNNE 0xc0010115
385%define MSR_K8_SMM_CTL 0xc0010116
386%define MSR_K8_VM_HSAVE_PA 0xc0010117
387%define X86_PG_ENTRIES 1024
388%define X86_PG_PAE_ENTRIES 512
389%define X86_PG_PAE_PDPE_ENTRIES 4
390%define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
391%define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
392%define X86_PAGE_4K_SIZE _4K
393%define X86_PAGE_4K_SHIFT 12
394%define X86_PAGE_4K_OFFSET_MASK 0xfff
395%define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000
396%define X86_PAGE_4K_BASE_MASK_32 0xfffff000
397%define X86_PAGE_2M_SIZE _2M
398%define X86_PAGE_2M_SHIFT 21
399%define X86_PAGE_2M_OFFSET_MASK 0x001fffff
400%define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000
401%define X86_PAGE_2M_BASE_MASK_32 0xffe00000
402%define X86_PAGE_4M_SIZE _4M
403%define X86_PAGE_4M_SHIFT 22
404%define X86_PAGE_4M_OFFSET_MASK 0x003fffff
405%define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000
406%define X86_PAGE_4M_BASE_MASK_32 0xffc00000
407%define X86_PTE_BIT_P 0
408%define X86_PTE_BIT_RW 1
409%define X86_PTE_BIT_US 2
410%define X86_PTE_BIT_PWT 3
411%define X86_PTE_BIT_PCD 4
412%define X86_PTE_BIT_A 5
413%define X86_PTE_BIT_D 6
414%define X86_PTE_BIT_PAT 7
415%define X86_PTE_BIT_G 8
416%define X86_PTE_P RT_BIT(0)
417%define X86_PTE_RW RT_BIT(1)
418%define X86_PTE_US RT_BIT(2)
419%define X86_PTE_PWT RT_BIT(3)
420%define X86_PTE_PCD RT_BIT(4)
421%define X86_PTE_A RT_BIT(5)
422%define X86_PTE_D RT_BIT(6)
423%define X86_PTE_PAT RT_BIT(7)
424%define X86_PTE_G RT_BIT(8)
425%define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
426%define X86_PTE_PG_MASK ( 0xfffff000 )
427%define X86_PTE_PAE_PG_MASK 0x000ffffffffff000
428%define X86_PTE_PAE_NX RT_BIT_64(63)
429%define X86_PTE_PAE_MBZ_MASK_NX 0x7ff0000000000000
430%define X86_PTE_PAE_MBZ_MASK_NO_NX 0xfff0000000000000
431%define X86_PTE_LM_MBZ_MASK_NX 0x0000000000000000
432%define X86_PTE_LM_MBZ_MASK_NO_NX 0x8000000000000000
433%define X86_PT_SHIFT 12
434%define X86_PT_MASK 0x3ff
435%define X86_PT_PAE_SHIFT 12
436%define X86_PT_PAE_MASK 0x1ff
437%define X86_PDE_P RT_BIT(0)
438%define X86_PDE_RW RT_BIT(1)
439%define X86_PDE_US RT_BIT(2)
440%define X86_PDE_PWT RT_BIT(3)
441%define X86_PDE_PCD RT_BIT(4)
442%define X86_PDE_A RT_BIT(5)
443%define X86_PDE_PS RT_BIT(7)
444%define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
445%define X86_PDE_PG_MASK ( 0xfffff000 )
446%define X86_PDE_PAE_PG_MASK 0x000ffffffffff000
447%define X86_PDE_PAE_NX RT_BIT_64(63)
448%define X86_PDE_PAE_MBZ_MASK_NX 0x7ff0000000000080
449%define X86_PDE_PAE_MBZ_MASK_NO_NX 0xfff0000000000080
450%define X86_PDE_LM_MBZ_MASK_NX 0x0000000000000080
451%define X86_PDE_LM_MBZ_MASK_NO_NX 0x8000000000000080
452%define X86_PDE4M_P RT_BIT(0)
453%define X86_PDE4M_RW RT_BIT(1)
454%define X86_PDE4M_US RT_BIT(2)
455%define X86_PDE4M_PWT RT_BIT(3)
456%define X86_PDE4M_PCD RT_BIT(4)
457%define X86_PDE4M_A RT_BIT(5)
458%define X86_PDE4M_D RT_BIT(6)
459%define X86_PDE4M_PS RT_BIT(7)
460%define X86_PDE4M_G RT_BIT(8)
461%define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
462%define X86_PDE4M_PAT RT_BIT(12)
463%define X86_PDE4M_PAT_SHIFT (12 - 7)
464%define X86_PDE4M_PG_MASK ( 0xffc00000 )
465%define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
466%define X86_PDE4M_PG_HIGH_SHIFT 19
467%define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
468%define X86_PDE2M_PAE_PG_MASK 0x000fffffffe00000
469%define X86_PDE2M_PAE_NX RT_BIT_64(63)
470%define X86_PDE2M_PAE_MBZ_MASK_NX 0x7ff00000001fe000
471%define X86_PDE2M_PAE_MBZ_MASK_NO_NX 0xfff00000001fe000
472%define X86_PDE2M_LM_MBZ_MASK_NX 0x00000000001fe000
473%define X86_PDE2M_LM_MBZ_MASK_NO_NX 0x80000000001fe000
474%define X86_PD_SHIFT 22
475%define X86_PD_MASK 0x3ff
476%define X86_PD_PAE_SHIFT 21
477%define X86_PD_PAE_MASK 0x1ff
478%define X86_PDPE_P RT_BIT(0)
479%define X86_PDPE_RW RT_BIT(1)
480%define X86_PDPE_US RT_BIT(2)
481%define X86_PDPE_PWT RT_BIT(3)
482%define X86_PDPE_PCD RT_BIT(4)
483%define X86_PDPE_A RT_BIT(5)
484%define X86_PDPE_LM_PS RT_BIT(7)
485%define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
486%define X86_PDPE_PG_MASK 0x000ffffffffff000
487%define X86_PDPE_PAE_MBZ_MASK 0xfff00000000001e6
488%define X86_PDPE_LM_NX RT_BIT_64(63)
489%define X86_PDPE_LM_MBZ_MASK_NX 0x0000000000000180
490%define X86_PDPE_LM_MBZ_MASK_NO_NX 0x8000000000000180
491%define X86_PDPE1G_LM_MBZ_MASK_NX 0x000000003fffe000
492%define X86_PDPE1G_LM_MBZ_MASK_NO_NX 0x800000003fffe000
493%define X86_PDPT_SHIFT 30
494%define X86_PDPT_MASK_PAE 0x3
495%define X86_PDPT_MASK_AMD64 0x1ff
496%define X86_PML4E_P RT_BIT(0)
497%define X86_PML4E_RW RT_BIT(1)
498%define X86_PML4E_US RT_BIT(2)
499%define X86_PML4E_PWT RT_BIT(3)
500%define X86_PML4E_PCD RT_BIT(4)
501%define X86_PML4E_A RT_BIT(5)
502%define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
503%define X86_PML4E_PG_MASK 0x000ffffffffff000
504%define X86_PML4E_MBZ_MASK_NX 0x0000000000000080
505%define X86_PML4E_MBZ_MASK_NO_NX 0x8000000000000080
506%define X86_PML4E_NX RT_BIT_64(63)
507%define X86_PML4_SHIFT 39
508%define X86_PML4_MASK 0x1ff
509%define X86_FSW_IE RT_BIT(0)
510%define X86_FSW_DE RT_BIT(1)
511%define X86_FSW_ZE RT_BIT(2)
512%define X86_FSW_OE RT_BIT(3)
513%define X86_FSW_UE RT_BIT(4)
514%define X86_FSW_PE RT_BIT(5)
515%define X86_FSW_SF RT_BIT(6)
516%define X86_FSW_ES RT_BIT(7)
517%define X86_FSW_XCPT_MASK 0x007f
518%define X86_FSW_XCPT_ES_MASK 0x00ff
519%define X86_FSW_C0 RT_BIT(8)
520%define X86_FSW_C1 RT_BIT(9)
521%define X86_FSW_C2 RT_BIT(10)
522%define X86_FSW_TOP_MASK 0x3800
523%define X86_FSW_TOP_SHIFT 11
524%define X86_FSW_TOP_SMASK 0x0007
525%define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
526%define X86_FSW_C3 RT_BIT(14)
527%define X86_FSW_C_MASK 0x4700
528%define X86_FSW_B RT_BIT(15)
529%define X86_FCW_IM RT_BIT(0)
530%define X86_FCW_DM RT_BIT(1)
531%define X86_FCW_ZM RT_BIT(2)
532%define X86_FCW_OM RT_BIT(3)
533%define X86_FCW_UM RT_BIT(4)
534%define X86_FCW_PM RT_BIT(5)
535%define X86_FCW_MASK_ALL 0x007f
536%define X86_FCW_XCPT_MASK 0x003f
537%define X86_FCW_PC_MASK 0x0300
538%define X86_FCW_PC_24 0x0000
539%define X86_FCW_PC_RSVD 0x0100
540%define X86_FCW_PC_53 0x0200
541%define X86_FCW_PC_64 0x0300
542%define X86_FCW_RC_MASK 0x0c00
543%define X86_FCW_RC_NEAREST 0x0000
544%define X86_FCW_RC_DOWN 0x0400
545%define X86_FCW_RC_UP 0x0800
546%define X86_FCW_RC_ZERO 0x0c00
547%define X86_FCW_ZERO_MASK 0xf080
548%ifndef VBOX_FOR_DTRACE_LIB
549%endif
550%define X86DESCATTR_TYPE 0x0000000f
551%define X86DESCATTR_DT 0x00000010
552%define X86DESCATTR_DPL 0x00000060
553%define X86DESCATTR_DPL_SHIFT 5
554%define X86DESCATTR_P 0x00000800
555%define X86DESCATTR_LIMIT_HIGH 0x00000f00
556%define X86DESCATTR_AVL 0x00001000
557%define X86DESCATTR_L 0x00002000
558%define X86DESCATTR_D 0x00004000
559%define X86DESCATTR_G 0x00008000
560%define X86DESCATTR_UNUSABLE 0x00010000
561%ifndef VBOX_FOR_DTRACE_LIB
562%endif
563%ifndef VBOX_FOR_DTRACE_LIB
564%define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0)
565%define X86DESCGENERIC_BIT_OFF_BASE_LOW (16)
566%define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32)
567%define X86DESCGENERIC_BIT_OFF_TYPE (40)
568%define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44)
569%define X86DESCGENERIC_BIT_OFF_DPL (45)
570%define X86DESCGENERIC_BIT_OFF_PRESENT (47)
571%define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48)
572%define X86DESCGENERIC_BIT_OFF_AVAILABLE (52)
573%define X86DESCGENERIC_BIT_OFF_LONG (53)
574%define X86DESCGENERIC_BIT_OFF_DEF_BIG (54)
575%define X86DESCGENERIC_BIT_OFF_GRANULARITY (55)
576%define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56)
577%endif
578%ifndef VBOX_FOR_DTRACE_LIB
579%endif
580%ifndef VBOX_FOR_DTRACE_LIB
581%endif
582%ifndef VBOX_FOR_DTRACE_LIB
583%endif
584%ifndef VBOX_FOR_DTRACE_LIB
585%endif
586%ifndef VBOX_FOR_DTRACE_LIB
587%endif
588%if HC_ARCH_BITS == 64
589%else
590%endif
591%if HC_ARCH_BITS == 64
592%else
593%endif
594%if HC_ARCH_BITS == 64
595%else
596%endif
597%define X86_SEL_TYPE_CODE 8
598%define X86_SEL_TYPE_MEMORY RT_BIT(4)
599%define X86_SEL_TYPE_ACCESSED 1
600%define X86_SEL_TYPE_DOWN 4
601%define X86_SEL_TYPE_CONF 4
602%define X86_SEL_TYPE_WRITE 2
603%define X86_SEL_TYPE_READ 2
604%define X86_SEL_TYPE_READ_BIT 1
605%define X86_SEL_TYPE_RO 0
606%define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
607%define X86_SEL_TYPE_RW 2
608%define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
609%define X86_SEL_TYPE_RO_DOWN 4
610%define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
611%define X86_SEL_TYPE_RW_DOWN 6
612%define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
613%define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
614%define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
615%define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
616%define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
617%define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
618%define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
619%define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
620%define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
621%define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
622%define X86_SEL_TYPE_SYS_UNDEFINED 0
623%define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
624%define X86_SEL_TYPE_SYS_LDT 2
625%define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
626%define X86_SEL_TYPE_SYS_286_CALL_GATE 4
627%define X86_SEL_TYPE_SYS_TASK_GATE 5
628%define X86_SEL_TYPE_SYS_286_INT_GATE 6
629%define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
630%define X86_SEL_TYPE_SYS_UNDEFINED2 8
631%define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
632%define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
633%define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
634%define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
635%define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
636%define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
637%define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
638%define AMD64_SEL_TYPE_SYS_LDT 2
639%define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
640%define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
641%define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
642%define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
643%define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
644%define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
645%define X86_DESC_S RT_BIT(12)
646%define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
647%define X86_DESC_P RT_BIT(15)
648%define X86_DESC_AVL RT_BIT(20)
649%define X86_DESC_DB RT_BIT(22)
650%define X86_DESC_G RT_BIT(23)
651%ifndef VBOX_FOR_DTRACE_LIB
652%endif
653%ifndef VBOX_FOR_DTRACE_LIB
654%endif
655%define X86_SEL_SHIFT 3
656%define X86_SEL_MASK 0xfff8
657%define X86_SEL_MASK_OFF_RPL 0xfffc
658%define X86_SEL_LDT 0x0004
659%define X86_SEL_RPL 0x0003
660%define X86_SEL_RPL_LDT 0x0007
661%define X86_XCPT_MAX (X86_XCPT_SX)
662%define X86_TRAP_ERR_EXTERNAL 1
663%define X86_TRAP_ERR_IDT 2
664%define X86_TRAP_ERR_TI 4
665%define X86_TRAP_ERR_SEL_MASK 0xfff8
666%define X86_TRAP_ERR_SEL_SHIFT 3
667%define X86_TRAP_PF_P RT_BIT(0)
668%define X86_TRAP_PF_RW RT_BIT(1)
669%define X86_TRAP_PF_US RT_BIT(2)
670%define X86_TRAP_PF_RSVD RT_BIT(3)
671%define X86_TRAP_PF_ID RT_BIT(4)
672%ifndef VBOX_FOR_DTRACE_LIB
673%else
674%endif
675%ifndef VBOX_FOR_DTRACE_LIB
676%else
677%endif
678%define X86_MODRM_RM_MASK 0x07
679%define X86_MODRM_REG_MASK 0x38
680%define X86_MODRM_REG_SMASK 0x07
681%define X86_MODRM_REG_SHIFT 3
682%define X86_MODRM_MOD_MASK 0xc0
683%define X86_MODRM_MOD_SMASK 0x03
684%define X86_MODRM_MOD_SHIFT 6
685%ifndef VBOX_FOR_DTRACE_LIB
686%endif
687%define X86_SIB_BASE_MASK 0x07
688%define X86_SIB_INDEX_MASK 0x38
689%define X86_SIB_INDEX_SMASK 0x07
690%define X86_SIB_INDEX_SHIFT 3
691%define X86_SIB_SCALE_MASK 0xc0
692%define X86_SIB_SCALE_SMASK 0x03
693%define X86_SIB_SCALE_SHIFT 6
694%ifndef VBOX_FOR_DTRACE_LIB
695%endif
696%define X86_GREG_xAX 0
697%define X86_GREG_xCX 1
698%define X86_GREG_xDX 2
699%define X86_GREG_xBX 3
700%define X86_GREG_xSP 4
701%define X86_GREG_xBP 5
702%define X86_GREG_xSI 6
703%define X86_GREG_xDI 7
704%define X86_GREG_x8 8
705%define X86_GREG_x9 9
706%define X86_GREG_x10 10
707%define X86_GREG_x11 11
708%define X86_GREG_x12 12
709%define X86_GREG_x13 13
710%define X86_GREG_x14 14
711%define X86_GREG_x15 15
712%define X86_SREG_ES 0
713%define X86_SREG_CS 1
714%define X86_SREG_SS 2
715%define X86_SREG_DS 3
716%define X86_SREG_FS 4
717%define X86_SREG_GS 5
718%define X86_SREG_COUNT 6
719%define X86_OP_PRF_CS 0x2e
720%define X86_OP_PRF_SS 0x36
721%define X86_OP_PRF_DS 0x3e
722%define X86_OP_PRF_ES 0x26
723%define X86_OP_PRF_FS 0x64
724%define X86_OP_PRF_GS 0x65
725%define X86_OP_PRF_SIZE_OP 0x66
726%define X86_OP_PRF_SIZE_ADDR 0x67
727%define X86_OP_PRF_LOCK 0xf0
728%define X86_OP_PRF_REPZ 0xf2
729%define X86_OP_PRF_REPNZ 0xf3
730%define X86_OP_REX_B 0x41
731%define X86_OP_REX_X 0x42
732%define X86_OP_REX_R 0x44
733%define X86_OP_REX_W 0x48
734%endif
735%include "iprt/x86extra.mac"
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