VirtualBox

source: vbox/trunk/include/iprt/x86.mac@ 103732

Last change on this file since 103732 was 102126, checked in by vboxsync, 12 months ago

include: kmk incs (sans VBox/err.mac) bugref:10371
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File size: 70.4 KB
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1;; @file
2; IPRT - X86 and AMD64 Structures and Definitions.
3;
4; Automatically generated by various.sed. DO NOT EDIT!
5;
6
7;
8; Copyright (C) 2006-2023 Oracle and/or its affiliates.
9;
10; This file is part of VirtualBox base platform packages, as
11; available from https://www.virtualbox.org.
12;
13; This program is free software; you can redistribute it and/or
14; modify it under the terms of the GNU General Public License
15; as published by the Free Software Foundation, in version 3 of the
16; License.
17;
18; This program is distributed in the hope that it will be useful, but
19; WITHOUT ANY WARRANTY; without even the implied warranty of
20; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21; General Public License for more details.
22;
23; You should have received a copy of the GNU General Public License
24; along with this program; if not, see <https://www.gnu.org/licenses>.
25;
26; The contents of this file may alternatively be used under the terms
27; of the Common Development and Distribution License Version 1.0
28; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
29; in the VirtualBox distribution, in which case the provisions of the
30; CDDL are applicable instead of those of the GPL.
31;
32; You may elect to license modified versions of this file under the
33; terms and conditions of either the GPL or the CDDL or both.
34;
35; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
36;
37
38%ifndef IPRT_INCLUDED_x86_h
39%define IPRT_INCLUDED_x86_h
40%ifndef RT_WITHOUT_PRAGMA_ONCE
41%endif
42%ifndef VBOX_FOR_DTRACE_LIB
43%else
44%endif
45%ifdef RT_OS_SOLARIS
46%endif
47%ifndef VBOX_FOR_DTRACE_LIB
48%endif
49%ifndef VBOX_FOR_DTRACE_LIB
50%endif
51%ifndef VBOX_FOR_DTRACE_LIB
52%endif
53%define X86_EFL_CF RT_BIT_32(0)
54%define X86_EFL_CF_BIT 0
55%define X86_EFL_1 RT_BIT_32(1)
56%define X86_EFL_PF RT_BIT_32(2)
57%define X86_EFL_PF_BIT 2
58%define X86_EFL_AF RT_BIT_32(4)
59%define X86_EFL_AF_BIT 4
60%define X86_EFL_ZF RT_BIT_32(6)
61%define X86_EFL_ZF_BIT 6
62%define X86_EFL_SF RT_BIT_32(7)
63%define X86_EFL_SF_BIT 7
64%define X86_EFL_TF RT_BIT_32(8)
65%define X86_EFL_TF_BIT 8
66%define X86_EFL_IF RT_BIT_32(9)
67%define X86_EFL_IF_BIT 9
68%define X86_EFL_DF RT_BIT_32(10)
69%define X86_EFL_DF_BIT 10
70%define X86_EFL_OF RT_BIT_32(11)
71%define X86_EFL_OF_BIT 11
72%define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
73%define X86_EFL_NT RT_BIT_32(14)
74%define X86_EFL_NT_BIT 14
75%define X86_EFL_RF RT_BIT_32(16)
76%define X86_EFL_RF_BIT 16
77%define X86_EFL_VM RT_BIT_32(17)
78%define X86_EFL_VM_BIT 17
79%define X86_EFL_AC RT_BIT_32(18)
80%define X86_EFL_AC_BIT 18
81%define X86_EFL_VIF RT_BIT_32(19)
82%define X86_EFL_VIF_BIT 19
83%define X86_EFL_VIP RT_BIT_32(20)
84%define X86_EFL_VIP_BIT 20
85%define X86_EFL_ID RT_BIT_32(21)
86%define X86_EFL_ID_BIT 21
87%define X86_EFL_LIVE_MASK 0x003f7fd5
88%define X86_EFL_RA1_MASK RT_BIT_32(1)
89%define X86_EFL_RAZ_MASK 0xffc08028
90%define X86_EFL_RAZ_LO_MASK 0x00008028
91%define X86_EFL_IOPL_SHIFT 12
92%define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
93%define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
94 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
95%define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
96 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
97%define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
98%ifndef VBOX_FOR_DTRACE_LIB
99%else
100%endif
101%ifndef VBOX_FOR_DTRACE_LIB
102%else
103%endif
104%define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547
105%define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e
106%define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69
107%define X86_CPUID_VENDOR_AMD_EBX 0x68747541
108%define X86_CPUID_VENDOR_AMD_ECX 0x444d4163
109%define X86_CPUID_VENDOR_AMD_EDX 0x69746e65
110%define X86_CPUID_VENDOR_VIA_EBX 0x746e6543
111%define X86_CPUID_VENDOR_VIA_ECX 0x736c7561
112%define X86_CPUID_VENDOR_VIA_EDX 0x48727561
113%define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020
114%define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961
115%define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61
116%define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948
117%define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975
118%define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e
119%define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
120%define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
121%define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
122%define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
123%define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
124%define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
125%define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
126%define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
127%define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
128%define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
129%define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
130%define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
131%define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
132%define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
133%define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
134%define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
135%define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
136%define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
137%define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
138%define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
139%define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
140%define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
141%define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
142%define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
143%define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
144%define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
145%define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
146%define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
147%define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
148%define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
149%define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
150%define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
151%define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
152%define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
153%define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
154%define X86_CPUID_FEATURE_EDX_PSE_BIT 3
155%define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
156%define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
157%define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
158%define X86_CPUID_FEATURE_EDX_PAE_BIT 6
159%define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
160%define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
161%define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
162%define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
163%define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
164%define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
165%define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
166%define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
167%define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
168%define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
169%define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
170%define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
171%define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
172%define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
173%define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
174%define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
175%define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
176%define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
177%define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
178%define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
179%define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
180%define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
181%define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
182%define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
183%define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
184%define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
185%define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
186%define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
187%define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
188%define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
189%define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
190%define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
191%define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
192%define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
193%define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
194%define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
195%define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
196%define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
197%define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
198%define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
199%define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
200%define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
201%define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
202%define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
203%define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
204%define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
205%define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
206%define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
207%define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
208%define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
209%define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
210%define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
211%define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
212%define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
213%define X86_CPUID_STEXT_FEATURE_ECX_CET_SS RT_BIT_32(7)
214%define X86_CPUID_STEXT_FEATURE_ECX_MAWAU 0x003e0000
215%define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
216%define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
217%define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
218%define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT_32(20)
219%define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
220%define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
221%define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
222%define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
223%define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
224%define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
225%define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
226%define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
227%define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
228%define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
229%define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
230%define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
231%define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
232%define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
233%define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
234%define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
235%define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
236%define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
237%define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
238%define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
239%define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
240%define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
241%define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
242%define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
243%define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
244%define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
245%define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
246%define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
247%define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
248%define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
249%define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
250%define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
251%define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
252%define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
253%define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
254%define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
255%define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
256%define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
257%define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
258%define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
259%define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
260%define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
261%define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
262%define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
263%define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
264%define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
265%define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
266%define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
267%define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
268%define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
269%define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
270%define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
271%define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
272%define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
273%define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
274%define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
275%define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
276%define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
277%define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
278%define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
279%define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
280%define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
281%define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
282%define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
283%define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
284%define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
285%define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
286%define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
287%define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
288%define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
289%define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
290%define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
291%define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
292%define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
293%define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
294%define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
295%define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
296%define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
297%define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
298%define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
299%define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
300%define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
301%define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
302%define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
303%define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
304%define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
305%define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
306%define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
307%define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
308%define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
309%define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
310%define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
311%define X86_CPUID_SVM_FEATURE_EDX_X2AVIC RT_BIT(18)
312%define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
313%define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
314%define X86_CPUID_SVM_FEATURE_EDX_ROGPT RT_BIT(21)
315%define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
316%define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
317%define X86_CPUID_SVM_FEATURE_EDX_VNMI RT_BIT(25)
318%define X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT RT_BIT(26)
319%define X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG RT_BIT(27)
320%define X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK RT_BIT(28)
321%define X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD RT_BIT(29)
322%define X86_CR0_PE RT_BIT_32(0)
323%define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
324%define X86_CR0_MP RT_BIT_32(1)
325%define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
326%define X86_CR0_EM RT_BIT_32(2)
327%define X86_CR0_EMULATE_FPU RT_BIT_32(2)
328%define X86_CR0_TS RT_BIT_32(3)
329%define X86_CR0_TASK_SWITCH RT_BIT_32(3)
330%define X86_CR0_ET RT_BIT_32(4)
331%define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
332%define X86_CR0_NE RT_BIT_32(5)
333%define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
334%define X86_CR0_WP RT_BIT_32(16)
335%define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
336%define X86_CR0_AM RT_BIT_32(18)
337%define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
338%define X86_CR0_NW RT_BIT_32(29)
339%define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
340%define X86_CR0_CD RT_BIT_32(30)
341%define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
342%define X86_CR0_PG RT_BIT_32(31)
343%define X86_CR0_PAGING RT_BIT_32(31)
344%define X86_CR0_BIT_PG 31
345%define X86_CR3_PWT RT_BIT_32(3)
346%define X86_CR3_PCD RT_BIT_32(4)
347%define X86_CR3_PAGE_MASK (0xfffff000)
348%define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
349%define X86_CR3_AMD64_PAGE_MASK 0x000ffffffffff000
350%define X86_CR3_EPT_PAGE_MASK 0x000ffffffffff000
351%define X86_CR4_VME RT_BIT_32(0)
352%define X86_CR4_PVI RT_BIT_32(1)
353%define X86_CR4_TSD RT_BIT_32(2)
354%define X86_CR4_DE RT_BIT_32(3)
355%define X86_CR4_PSE RT_BIT_32(4)
356%define X86_CR4_PAE RT_BIT_32(5)
357%define X86_CR4_MCE RT_BIT_32(6)
358%define X86_CR4_PGE RT_BIT_32(7)
359%define X86_CR4_PCE RT_BIT_32(8)
360%define X86_CR4_OSFXSR RT_BIT_32(9)
361%define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
362%define X86_CR4_UMIP RT_BIT_32(11)
363%define X86_CR4_VMXE RT_BIT_32(13)
364%define X86_CR4_SMXE RT_BIT_32(14)
365%define X86_CR4_FSGSBASE RT_BIT_32(16)
366%define X86_CR4_PCIDE RT_BIT_32(17)
367%define X86_CR4_OSXSAVE RT_BIT_32(18)
368%define X86_CR4_SMEP RT_BIT_32(20)
369%define X86_CR4_SMAP RT_BIT_32(21)
370%define X86_CR4_PKE RT_BIT_32(22)
371%define X86_CR4_CET RT_BIT_32(23)
372%define X86_DR6_B0 RT_BIT_32(0)
373%define X86_DR6_B1 RT_BIT_32(1)
374%define X86_DR6_B2 RT_BIT_32(2)
375%define X86_DR6_B3 RT_BIT_32(3)
376%define X86_DR6_B_MASK 0x0000000f
377%define X86_DR6_BD RT_BIT_32(13)
378%define X86_DR6_BS RT_BIT_32(14)
379%define X86_DR6_BT RT_BIT_32(15)
380%define X86_DR6_RTM RT_BIT_32(16)
381%define X86_DR6_INIT_VAL 0xffff0ff0
382%define X86_DR6_RA1_MASK 0xffff0ff0
383%define X86_DR6_RA1_MASK_RTM 0xfffe0ff0
384%define X86_DR6_RAZ_MASK RT_BIT_64(12)
385%define X86_DR6_MBZ_MASK 0xffffffff00000000
386%define X86_DR6_B(iBp) RT_BIT_64(iBp)
387%define X86_DR7_L0 RT_BIT_32(0)
388%define X86_DR7_G0 RT_BIT_32(1)
389%define X86_DR7_L1 RT_BIT_32(2)
390%define X86_DR7_G1 RT_BIT_32(3)
391%define X86_DR7_L2 RT_BIT_32(4)
392%define X86_DR7_G2 RT_BIT_32(5)
393%define X86_DR7_L3 RT_BIT_32(6)
394%define X86_DR7_G3 RT_BIT_32(7)
395%define X86_DR7_LE RT_BIT_32(8)
396%define X86_DR7_GE RT_BIT_32(9)
397%define X86_DR7_LE_ALL 0x0000000000000055
398%define X86_DR7_GE_ALL 0x00000000000000aa
399%define X86_DR7_RTM RT_BIT_32(11)
400%define X86_DR7_ICE_IR RT_BIT_32(12)
401%define X86_DR7_GD RT_BIT_32(13)
402%define X86_DR7_ICE_TR1 RT_BIT_32(14)
403%define X86_DR7_ICE_TR2 RT_BIT_32(15)
404%define X86_DR7_RW0_MASK (3 << 16)
405%define X86_DR7_LEN0_MASK (3 << 18)
406%define X86_DR7_RW1_MASK (3 << 20)
407%define X86_DR7_LEN1_MASK (3 << 22)
408%define X86_DR7_RW2_MASK (3 << 24)
409%define X86_DR7_LEN2_MASK (3 << 26)
410%define X86_DR7_RW3_MASK (3 << 28)
411%define X86_DR7_LEN3_MASK (3 << 30)
412%define X86_DR7_RA1_MASK RT_BIT_32(10)
413%define X86_DR7_RAZ_MASK 0x0000d800
414%define X86_DR7_MBZ_MASK 0xffffffff00000000
415%define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
416%define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
417%define X86_DR7_L_G(iBp) ( 3 << (iBp * 2) )
418%define X86_DR7_RW_EO 0
419%define X86_DR7_RW_WO 1
420%define X86_DR7_RW_IO 2
421%define X86_DR7_RW_RW 3
422%define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
423%define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & 3 )
424%define X86_DR7_RW_ALL_MASKS 0x33330000
425%ifndef VBOX_FOR_DTRACE_LIB
426 %define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (0x000f0000 << ((a_iBp) * 4))) == 0 )
427 %define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
428 ( ((a_uDR7) & (0x03 << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
429 %define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
430 ( (((a_uDR7) & 0x03) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \
431 || (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \
432 || (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
433 || (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
434 %define X86_DR7_ANY_RW_IO(uDR7) \
435 ( ( 0x22220000 & (uDR7) )
436%endif
437%define X86_DR7_LEN_BYTE 0
438%define X86_DR7_LEN_WORD 1
439%define X86_DR7_LEN_QWORD 2
440%define X86_DR7_LEN_DWORD 3
441%define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
442%define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3 )
443%define X86_DR7_ENABLED_MASK 0x000000ff
444%define X86_DR7_LEN_ALL_MASKS 0xcccc0000
445%define X86_DR7_RW_LEN_ALL_MASKS 0xffff0000
446%define X86_DR7_INIT_VAL 0x400
447%define MSR_P5_MC_ADDR 0x00000000
448%define MSR_P5_MC_TYPE 0x00000001
449%define MSR_IA32_TSC 0x10
450%define MSR_IA32_CESR 0x00000011
451%define MSR_IA32_CTR0 0x00000012
452%define MSR_IA32_CTR1 0x00000013
453%define MSR_IA32_PLATFORM_ID 0x17
454%ifndef MSR_IA32_APICBASE
455 %define MSR_IA32_APICBASE 0x1b
456 %define MSR_IA32_APICBASE_EN RT_BIT_64(11)
457 %define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
458 %define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
459 %define MSR_IA32_APICBASE_BASE_MIN 0x0000000ffffff000
460 %define MSR_IA32_APICBASE_ADDR 0x00000000fee00000
461 %define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
462%endif
463%define MSR_CORE_THREAD_COUNT 0x35
464%define MSR_IA32_FEATURE_CONTROL 0x3A
465%define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
466%define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
467%define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
468%define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
469%define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
470%define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
471%define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
472%define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
473%define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
474%define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
475%define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
476%define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
477%define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
478%define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
479%define MSR_IA32_TSC_ADJUST 0x3B
480%define MSR_IA32_SPEC_CTRL 0x48
481%define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
482%define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
483%define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
484%define MSR_IA32_PRED_CMD 0x49
485%define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
486%define MSR_IA32_BIOS_UPDT_TRIG 0x79
487%define MSR_IA32_BIOS_SIGN_ID 0x8B
488%define MSR_IA32_SMM_MONITOR_CTL 0x9B
489%define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
490%define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
491%define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & 0xfffff)
492%define MSR_IA32_SMBASE 0x9E
493%define MSR_IA32_PMC0 0xC1
494%define MSR_IA32_PMC1 0xC2
495%define MSR_IA32_PMC2 0xC3
496%define MSR_IA32_PMC3 0xC4
497%define MSR_IA32_PMC4 0xC5
498%define MSR_IA32_PMC5 0xC6
499%define MSR_IA32_PMC6 0xC7
500%define MSR_IA32_PMC7 0xC8
501%define MSR_IA32_PLATFORM_INFO 0xCE
502%define MSR_IA32_FSB_CLOCK_STS 0xCD
503%define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
504%define MSR_IA32_MPERF 0xE7
505%define MSR_IA32_APERF 0xE8
506%define MSR_IA32_MTRR_CAP 0xFE
507%define MSR_IA32_MTRR_CAP_VCNT_MASK 0x00000000000000ff
508%define MSR_IA32_MTRR_CAP_FIX RT_BIT_64(8)
509%define MSR_IA32_MTRR_CAP_WC RT_BIT_64(10)
510%define MSR_IA32_MTRR_CAP_SMRR RT_BIT_64(11)
511%define MSR_IA32_MTRR_CAP_PRMRR RT_BIT_64(12)
512%ifndef VBOX_FOR_DTRACE_LIB
513%endif
514%define X86_MTRR_MT_UC 0
515%define X86_MTRR_MT_WC 1
516%define X86_MTRR_MT_WT 4
517%define X86_MTRR_MT_WP 5
518%define X86_MTRR_MT_WB 6
519%define MSR_IA32_ARCH_CAPABILITIES 0x10a
520%define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
521%define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
522%define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
523%define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
524%define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
525%define MSR_IA32_FLUSH_CMD 0x10b
526%define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
527%define MSR_BBL_CR_CTL3 0x11e
528%ifndef MSR_IA32_SYSENTER_CS
529%define MSR_IA32_SYSENTER_CS 0x174
530%define MSR_IA32_SYSENTER_ESP 0x175
531%define MSR_IA32_SYSENTER_EIP 0x176
532%endif
533%define MSR_IA32_MCG_CAP 0x179
534%define MSR_IA32_MCG_STATUS 0x17A
535%define MSR_IA32_MCG_CTRL 0x17B
536%define MSR_IA32_CR_PAT 0x277
537%define MSR_IA32_CR_PAT_INIT_VAL 0x0007040600070406
538%define MSR_IA32_PAT_MT_UC 0
539%define MSR_IA32_PAT_MT_WC 1
540%define MSR_IA32_PAT_MT_RSVD_2 2
541%define MSR_IA32_PAT_MT_RSVD_3 3
542%define MSR_IA32_PAT_MT_WT 4
543%define MSR_IA32_PAT_MT_WP 5
544%define MSR_IA32_PAT_MT_WB 6
545%define MSR_IA32_PAT_MT_UCD 7
546%define MSR_IA32_PERFEVTSEL0 0x186
547%define MSR_IA32_PERFEVTSEL1 0x187
548%define MSR_IA32_PERFEVTSEL2 0x188
549%define MSR_IA32_PERFEVTSEL3 0x189
550%define MSR_FLEX_RATIO 0x194
551%define MSR_IA32_PERF_STATUS 0x198
552%define MSR_IA32_PERF_CTL 0x199
553%define MSR_IA32_THERM_STATUS 0x19c
554%define MSR_OFFCORE_RSP_0 0x1a6
555%define MSR_OFFCORE_RSP_1 0x1a7
556%define MSR_IA32_MISC_ENABLE 0x1A0
557%define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
558%define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
559%define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
560%define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
561%define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
562%define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
563%define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
564%define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
565%define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
566%define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
567%define MSR_IA32_DEBUGCTL 0x000001d9
568%define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
569%define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
570%define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
571%define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
572%define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
573%define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
574%define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
575%define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
576%define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
577%define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
578%define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
579%define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
580%define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
581%define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
582%define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
583%define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \
584 | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \
585 | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
586 | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
587 | MSR_IA32_DEBUGCTL_RTM)
588%define MSR_P4_LASTBRANCH_0 0x1db
589%define MSR_P4_LASTBRANCH_1 0x1dc
590%define MSR_P4_LASTBRANCH_2 0x1dd
591%define MSR_P4_LASTBRANCH_3 0x1de
592%define MSR_P4_LASTBRANCH_TOS 0x1da
593%define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
594%define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
595%define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
596%define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
597%define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
598%define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
599%define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
600%define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
601%define MSR_CORE2_LASTBRANCH_TOS 0x1c9
602%define MSR_LASTBRANCH_0_FROM_IP 0x680
603%define MSR_LASTBRANCH_1_FROM_IP 0x681
604%define MSR_LASTBRANCH_2_FROM_IP 0x682
605%define MSR_LASTBRANCH_3_FROM_IP 0x683
606%define MSR_LASTBRANCH_4_FROM_IP 0x684
607%define MSR_LASTBRANCH_5_FROM_IP 0x685
608%define MSR_LASTBRANCH_6_FROM_IP 0x686
609%define MSR_LASTBRANCH_7_FROM_IP 0x687
610%define MSR_LASTBRANCH_8_FROM_IP 0x688
611%define MSR_LASTBRANCH_9_FROM_IP 0x689
612%define MSR_LASTBRANCH_10_FROM_IP 0x68a
613%define MSR_LASTBRANCH_11_FROM_IP 0x68b
614%define MSR_LASTBRANCH_12_FROM_IP 0x68c
615%define MSR_LASTBRANCH_13_FROM_IP 0x68d
616%define MSR_LASTBRANCH_14_FROM_IP 0x68e
617%define MSR_LASTBRANCH_15_FROM_IP 0x68f
618%define MSR_LASTBRANCH_16_FROM_IP 0x690
619%define MSR_LASTBRANCH_17_FROM_IP 0x691
620%define MSR_LASTBRANCH_18_FROM_IP 0x692
621%define MSR_LASTBRANCH_19_FROM_IP 0x693
622%define MSR_LASTBRANCH_20_FROM_IP 0x694
623%define MSR_LASTBRANCH_21_FROM_IP 0x695
624%define MSR_LASTBRANCH_22_FROM_IP 0x696
625%define MSR_LASTBRANCH_23_FROM_IP 0x697
626%define MSR_LASTBRANCH_24_FROM_IP 0x698
627%define MSR_LASTBRANCH_25_FROM_IP 0x699
628%define MSR_LASTBRANCH_26_FROM_IP 0x69a
629%define MSR_LASTBRANCH_27_FROM_IP 0x69b
630%define MSR_LASTBRANCH_28_FROM_IP 0x69c
631%define MSR_LASTBRANCH_29_FROM_IP 0x69d
632%define MSR_LASTBRANCH_30_FROM_IP 0x69e
633%define MSR_LASTBRANCH_31_FROM_IP 0x69f
634%define MSR_LASTBRANCH_0_TO_IP 0x6c0
635%define MSR_LASTBRANCH_1_TO_IP 0x6c1
636%define MSR_LASTBRANCH_2_TO_IP 0x6c2
637%define MSR_LASTBRANCH_3_TO_IP 0x6c3
638%define MSR_LASTBRANCH_4_TO_IP 0x6c4
639%define MSR_LASTBRANCH_5_TO_IP 0x6c5
640%define MSR_LASTBRANCH_6_TO_IP 0x6c6
641%define MSR_LASTBRANCH_7_TO_IP 0x6c7
642%define MSR_LASTBRANCH_8_TO_IP 0x6c8
643%define MSR_LASTBRANCH_9_TO_IP 0x6c9
644%define MSR_LASTBRANCH_10_TO_IP 0x6ca
645%define MSR_LASTBRANCH_11_TO_IP 0x6cb
646%define MSR_LASTBRANCH_12_TO_IP 0x6cc
647%define MSR_LASTBRANCH_13_TO_IP 0x6cd
648%define MSR_LASTBRANCH_14_TO_IP 0x6ce
649%define MSR_LASTBRANCH_15_TO_IP 0x6cf
650%define MSR_LASTBRANCH_16_TO_IP 0x6d0
651%define MSR_LASTBRANCH_17_TO_IP 0x6d1
652%define MSR_LASTBRANCH_18_TO_IP 0x6d2
653%define MSR_LASTBRANCH_19_TO_IP 0x6d3
654%define MSR_LASTBRANCH_20_TO_IP 0x6d4
655%define MSR_LASTBRANCH_21_TO_IP 0x6d5
656%define MSR_LASTBRANCH_22_TO_IP 0x6d6
657%define MSR_LASTBRANCH_23_TO_IP 0x6d7
658%define MSR_LASTBRANCH_24_TO_IP 0x6d8
659%define MSR_LASTBRANCH_25_TO_IP 0x6d9
660%define MSR_LASTBRANCH_26_TO_IP 0x6da
661%define MSR_LASTBRANCH_27_TO_IP 0x6db
662%define MSR_LASTBRANCH_28_TO_IP 0x6dc
663%define MSR_LASTBRANCH_29_TO_IP 0x6dd
664%define MSR_LASTBRANCH_30_TO_IP 0x6de
665%define MSR_LASTBRANCH_31_TO_IP 0x6df
666%define MSR_LASTBRANCH_0_INFO 0xdc0
667%define MSR_LASTBRANCH_1_INFO 0xdc1
668%define MSR_LASTBRANCH_2_INFO 0xdc2
669%define MSR_LASTBRANCH_3_INFO 0xdc3
670%define MSR_LASTBRANCH_4_INFO 0xdc4
671%define MSR_LASTBRANCH_5_INFO 0xdc5
672%define MSR_LASTBRANCH_6_INFO 0xdc6
673%define MSR_LASTBRANCH_7_INFO 0xdc7
674%define MSR_LASTBRANCH_8_INFO 0xdc8
675%define MSR_LASTBRANCH_9_INFO 0xdc9
676%define MSR_LASTBRANCH_10_INFO 0xdca
677%define MSR_LASTBRANCH_11_INFO 0xdcb
678%define MSR_LASTBRANCH_12_INFO 0xdcc
679%define MSR_LASTBRANCH_13_INFO 0xdcd
680%define MSR_LASTBRANCH_14_INFO 0xdce
681%define MSR_LASTBRANCH_15_INFO 0xdcf
682%define MSR_LASTBRANCH_16_INFO 0xdd0
683%define MSR_LASTBRANCH_17_INFO 0xdd1
684%define MSR_LASTBRANCH_18_INFO 0xdd2
685%define MSR_LASTBRANCH_19_INFO 0xdd3
686%define MSR_LASTBRANCH_20_INFO 0xdd4
687%define MSR_LASTBRANCH_21_INFO 0xdd5
688%define MSR_LASTBRANCH_22_INFO 0xdd6
689%define MSR_LASTBRANCH_23_INFO 0xdd7
690%define MSR_LASTBRANCH_24_INFO 0xdd8
691%define MSR_LASTBRANCH_25_INFO 0xdd9
692%define MSR_LASTBRANCH_26_INFO 0xdda
693%define MSR_LASTBRANCH_27_INFO 0xddb
694%define MSR_LASTBRANCH_28_INFO 0xddc
695%define MSR_LASTBRANCH_29_INFO 0xddd
696%define MSR_LASTBRANCH_30_INFO 0xdde
697%define MSR_LASTBRANCH_31_INFO 0xddf
698%define MSR_LASTBRANCH_SELECT 0x1c8
699%define MSR_LASTBRANCH_TOS 0x1c9
700%define MSR_LER_FROM_IP 0x1dd
701%define MSR_LER_TO_IP 0x1de
702%define MSR_IA32_TSX_CTRL 0x122
703%define MSR_IA32_MTRR_PHYSBASE0 0x200
704%define MSR_IA32_MTRR_PHYSMASK0 0x201
705%define MSR_IA32_MTRR_PHYSBASE1 0x202
706%define MSR_IA32_MTRR_PHYSMASK1 0x203
707%define MSR_IA32_MTRR_PHYSBASE2 0x204
708%define MSR_IA32_MTRR_PHYSMASK2 0x205
709%define MSR_IA32_MTRR_PHYSBASE3 0x206
710%define MSR_IA32_MTRR_PHYSMASK3 0x207
711%define MSR_IA32_MTRR_PHYSBASE4 0x208
712%define MSR_IA32_MTRR_PHYSMASK4 0x209
713%define MSR_IA32_MTRR_PHYSBASE5 0x20a
714%define MSR_IA32_MTRR_PHYSMASK5 0x20b
715%define MSR_IA32_MTRR_PHYSBASE6 0x20c
716%define MSR_IA32_MTRR_PHYSMASK6 0x20d
717%define MSR_IA32_MTRR_PHYSBASE7 0x20e
718%define MSR_IA32_MTRR_PHYSMASK7 0x20f
719%define MSR_IA32_MTRR_PHYSBASE8 0x210
720%define MSR_IA32_MTRR_PHYSMASK8 0x211
721%define MSR_IA32_MTRR_PHYSBASE9 0x212
722%define MSR_IA32_MTRR_PHYSMASK9 0x213
723%define MSR_IA32_MTRR_FIX64K_00000 0x250
724%define MSR_IA32_MTRR_FIX16K_80000 0x258
725%define MSR_IA32_MTRR_FIX16K_A0000 0x259
726%define MSR_IA32_MTRR_FIX4K_C0000 0x268
727%define MSR_IA32_MTRR_FIX4K_C8000 0x269
728%define MSR_IA32_MTRR_FIX4K_D0000 0x26a
729%define MSR_IA32_MTRR_FIX4K_D8000 0x26b
730%define MSR_IA32_MTRR_FIX4K_E0000 0x26c
731%define MSR_IA32_MTRR_FIX4K_E8000 0x26d
732%define MSR_IA32_MTRR_FIX4K_F0000 0x26e
733%define MSR_IA32_MTRR_FIX4K_F8000 0x26f
734%define MSR_IA32_MTRR_DEF_TYPE 0x2FF
735%define MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK 0xFF
736%define MSR_IA32_MTRR_DEF_TYPE_FIXED_EN RT_BIT_64(10)
737%define MSR_IA32_MTRR_DEF_TYPE_MTRR_EN RT_BIT_64(11)
738%define MSR_IA32_MTRR_DEF_TYPE_VALID_MASK ( MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK \
739 | MSR_IA32_MTRR_DEF_TYPE_FIXED_EN \
740 | MSR_IA32_MTRR_DEF_TYPE_MTRR_EN)
741%define MSR_IA32_MTRR_PHYSMASK_VALID RT_BIT_64(11)
742%define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
743%define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
744%define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
745%define MSR_IA32_PEBS_ENABLE 0x3F1
746%define MSR_IA32_MC0_CTL 0x400
747%define MSR_IA32_MC0_STATUS 0x401
748%define MSR_IA32_VMX_BASIC 0x480
749%define MSR_IA32_VMX_PINBASED_CTLS 0x481
750%define MSR_IA32_VMX_PROCBASED_CTLS 0x482
751%define MSR_IA32_VMX_EXIT_CTLS 0x483
752%define MSR_IA32_VMX_ENTRY_CTLS 0x484
753%define MSR_IA32_VMX_MISC 0x485
754%define MSR_IA32_VMX_CR0_FIXED0 0x486
755%define MSR_IA32_VMX_CR0_FIXED1 0x487
756%define MSR_IA32_VMX_CR4_FIXED0 0x488
757%define MSR_IA32_VMX_CR4_FIXED1 0x489
758%define MSR_IA32_VMX_VMCS_ENUM 0x48A
759%define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
760%define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
761%define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
762%define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
763%define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
764%define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
765%define MSR_IA32_VMX_VMFUNC 0x491
766%define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
767%define MSR_IA32_VMX_EXIT_CTLS2 0x493
768%define MSR_IA32_RTIT_CTL 0x570
769%define MSR_IA32_DS_AREA 0x600
770%define MSR_RAPL_POWER_UNIT 0x606
771%define MSR_PKGC3_IRTL 0x60a
772%define MSR_PKGC_IRTL1 0x60b
773%define MSR_PKGC_IRTL2 0x60c
774%define MSR_PKG_C2_RESIDENCY 0x60d
775%define MSR_PKG_POWER_LIMIT 0x610
776%define MSR_PKG_ENERGY_STATUS 0x611
777%define MSR_PKG_PERF_STATUS 0x613
778%define MSR_PKG_POWER_INFO 0x614
779%define MSR_DRAM_POWER_LIMIT 0x618
780%define MSR_DRAM_ENERGY_STATUS 0x619
781%define MSR_DRAM_PERF_STATUS 0x61b
782%define MSR_DRAM_POWER_INFO 0x61c
783%define MSR_PKG_C10_RESIDENCY 0x632
784%define MSR_PP0_ENERGY_STATUS 0x639
785%define MSR_PP1_ENERGY_STATUS 0x641
786%define MSR_TURBO_ACTIVATION_RATIO 0x64c
787%define MSR_CORE_PERF_LIMIT_REASONS 0x64f
788%define MSR_IA32_U_CET 0x6a0
789%define MSR_IA32_S_CET 0x6a2
790 %define MSR_IA32_CET_SH_STK_EN RT_BIT_64(0)
791 %define MSR_IA32_CET_WR_SHSTK_EN RT_BIT_64(1)
792 %define MSR_IA32_CET_ENDBR_EN RT_BIT_64(2)
793 %define MSR_IA32_CET_LEG_IW_EN RT_BIT_64(3)
794 %define MSR_IA32_CET_NO_TRACK_EN RT_BIT_64(4)
795 %define MSR_IA32_CET_SUPPRESS_DIS RT_BIT_64(5)
796 %define MSR_IA32_CET_SUPPRESS RT_BIT_64(10)
797 %define MSR_IA32_CET_TRACKER RT_BIT_64(11)
798 %define MSR_IA32_CET_EB_LEG_BITMAP_BASE 0xfffffffffffff000
799%define MSR_IA32_X2APIC_START 0x800
800%define MSR_IA32_X2APIC_ID 0x802
801%define MSR_IA32_X2APIC_VERSION 0x803
802%define MSR_IA32_X2APIC_TPR 0x808
803%define MSR_IA32_X2APIC_PPR 0x80A
804%define MSR_IA32_X2APIC_EOI 0x80B
805%define MSR_IA32_X2APIC_LDR 0x80D
806%define MSR_IA32_X2APIC_SVR 0x80F
807%define MSR_IA32_X2APIC_ISR0 0x810
808%define MSR_IA32_X2APIC_ISR1 0x811
809%define MSR_IA32_X2APIC_ISR2 0x812
810%define MSR_IA32_X2APIC_ISR3 0x813
811%define MSR_IA32_X2APIC_ISR4 0x814
812%define MSR_IA32_X2APIC_ISR5 0x815
813%define MSR_IA32_X2APIC_ISR6 0x816
814%define MSR_IA32_X2APIC_ISR7 0x817
815%define MSR_IA32_X2APIC_TMR0 0x818
816%define MSR_IA32_X2APIC_TMR1 0x819
817%define MSR_IA32_X2APIC_TMR2 0x81A
818%define MSR_IA32_X2APIC_TMR3 0x81B
819%define MSR_IA32_X2APIC_TMR4 0x81C
820%define MSR_IA32_X2APIC_TMR5 0x81D
821%define MSR_IA32_X2APIC_TMR6 0x81E
822%define MSR_IA32_X2APIC_TMR7 0x81F
823%define MSR_IA32_X2APIC_IRR0 0x820
824%define MSR_IA32_X2APIC_IRR1 0x821
825%define MSR_IA32_X2APIC_IRR2 0x822
826%define MSR_IA32_X2APIC_IRR3 0x823
827%define MSR_IA32_X2APIC_IRR4 0x824
828%define MSR_IA32_X2APIC_IRR5 0x825
829%define MSR_IA32_X2APIC_IRR6 0x826
830%define MSR_IA32_X2APIC_IRR7 0x827
831%define MSR_IA32_X2APIC_ESR 0x828
832%define MSR_IA32_X2APIC_LVT_CMCI 0x82F
833%define MSR_IA32_X2APIC_ICR 0x830
834%define MSR_IA32_X2APIC_LVT_TIMER 0x832
835%define MSR_IA32_X2APIC_LVT_THERMAL 0x833
836%define MSR_IA32_X2APIC_LVT_PERF 0x834
837%define MSR_IA32_X2APIC_LVT_LINT0 0x835
838%define MSR_IA32_X2APIC_LVT_LINT1 0x836
839%define MSR_IA32_X2APIC_LVT_ERROR 0x837
840%define MSR_IA32_X2APIC_TIMER_ICR 0x838
841%define MSR_IA32_X2APIC_TIMER_CCR 0x839
842%define MSR_IA32_X2APIC_TIMER_DCR 0x83E
843%define MSR_IA32_X2APIC_SELF_IPI 0x83F
844%define MSR_IA32_X2APIC_END 0x8FF
845%define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
846%define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
847%define MSR_K6_EFER 0xc0000080
848%define MSR_K6_EFER_SCE RT_BIT_32(0)
849%define MSR_K6_EFER_LME RT_BIT_32(8)
850%define MSR_K6_EFER_BIT_LME 8
851%define MSR_K6_EFER_LMA RT_BIT_32(10)
852%define MSR_K6_EFER_BIT_LMA 10
853%define MSR_K6_EFER_NXE RT_BIT_32(11)
854%define MSR_K6_EFER_BIT_NXE 11
855%define MSR_K6_EFER_SVME RT_BIT_32(12)
856%define MSR_K6_EFER_LMSLE RT_BIT_32(13)
857%define MSR_K6_EFER_FFXSR RT_BIT_32(14)
858%define MSR_K6_EFER_TCE RT_BIT_32(15)
859%define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
860%define MSR_K6_STAR 0xc0000081
861%define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
862%define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
863%define MSR_K6_STAR_SEL_MASK 0xffff
864%define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
865%define MSR_K6_WHCR 0xc0000082
866%define MSR_K6_UWCCR 0xc0000085
867%define MSR_K6_PSOR 0xc0000087
868%define MSR_K6_PFIR 0xc0000088
869%define MSR_K7_EVNTSEL0 0xc0010000
870%define MSR_K7_EVNTSEL1 0xc0010001
871%define MSR_K7_EVNTSEL2 0xc0010002
872%define MSR_K7_EVNTSEL3 0xc0010003
873%define MSR_K7_PERFCTR0 0xc0010004
874%define MSR_K7_PERFCTR1 0xc0010005
875%define MSR_K7_PERFCTR2 0xc0010006
876%define MSR_K7_PERFCTR3 0xc0010007
877%define MSR_K8_LSTAR 0xc0000082
878%define MSR_K8_CSTAR 0xc0000083
879%define MSR_K8_SF_MASK 0xc0000084
880%define MSR_K8_FS_BASE 0xc0000100
881%define MSR_K8_GS_BASE 0xc0000101
882%define MSR_K8_KERNEL_GS_BASE 0xc0000102
883%define MSR_K8_TSC_AUX 0xc0000103
884%define MSR_K8_SYSCFG 0xc0010010
885%define MSR_K8_HWCR 0xc0010015
886%define MSR_K8_IORRBASE0 0xc0010016
887%define MSR_K8_IORRMASK0 0xc0010017
888%define MSR_K8_IORRBASE1 0xc0010018
889%define MSR_K8_IORRMASK1 0xc0010019
890%define MSR_K8_TOP_MEM1 0xc001001a
891%define MSR_K8_TOP_MEM2 0xc001001d
892%define MSR_K7_SMBASE 0xc0010111
893%define MSR_K7_SMM_ADDR 0xc0010112
894%define MSR_K7_SMM_MASK 0xc0010113
895%define MSR_K8_NB_CFG 0xc001001f
896%define MSR_K8_INT_PENDING 0xc0010055
897%define MSR_K8_VM_CR 0xc0010114
898%define MSR_K8_VM_CR_DPD RT_BIT_32(0)
899%define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
900%define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
901%define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
902%define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
903%define MSR_K8_IGNNE 0xc0010115
904%define MSR_K8_SMM_CTL 0xc0010116
905%define MSR_K8_VM_HSAVE_PA 0xc0010117
906%define MSR_AMD_VIRT_SPEC_CTL 0xc001011f
907 %define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
908%define X86_PG_ENTRIES 1024
909%define X86_PG_PAE_ENTRIES 512
910%define X86_PG_PAE_PDPE_ENTRIES 4
911%define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
912%define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
913%define X86_PAGE_SIZE X86_PAGE_4K_SIZE
914%define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
915%define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
916%define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
917%define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
918%define X86_PAGE_4K_SIZE _4K
919%define X86_PAGE_4K_SHIFT 12
920%define X86_PAGE_4K_OFFSET_MASK 0xfff
921%define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000
922%define X86_PAGE_4K_BASE_MASK_32 0xfffff000
923%define X86_PAGE_2M_SIZE _2M
924%define X86_PAGE_2M_SHIFT 21
925%define X86_PAGE_2M_OFFSET_MASK 0x001fffff
926%define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000
927%define X86_PAGE_2M_BASE_MASK_32 0xffe00000
928%define X86_PAGE_4M_SIZE _4M
929%define X86_PAGE_4M_SHIFT 22
930%define X86_PAGE_4M_OFFSET_MASK 0x003fffff
931%define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000
932%define X86_PAGE_4M_BASE_MASK_32 0xffc00000
933%define X86_PAGE_1G_SIZE _1G
934%define X86_PAGE_1G_SHIFT 30
935%define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
936%define X86_PAGE_1G_BASE_MASK 0xffffffffc0000000
937%define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + 0x800000000000 < UINT64_C(0x1000000000000))
938%define X86_GET_PAGE_BASE_MASK(a_cShift) (0xffffffffffffffff << (a_cShift))
939%define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
940%define X86_PTE_BIT_P 0
941%define X86_PTE_BIT_RW 1
942%define X86_PTE_BIT_US 2
943%define X86_PTE_BIT_PWT 3
944%define X86_PTE_BIT_PCD 4
945%define X86_PTE_BIT_A 5
946%define X86_PTE_BIT_D 6
947%define X86_PTE_BIT_PAT 7
948%define X86_PTE_BIT_G 8
949%define X86_PTE_PAE_BIT_NX 63
950%define X86_PTE_P RT_BIT_32(0)
951%define X86_PTE_RW RT_BIT_32(1)
952%define X86_PTE_US RT_BIT_32(2)
953%define X86_PTE_PWT RT_BIT_32(3)
954%define X86_PTE_PCD RT_BIT_32(4)
955%define X86_PTE_A RT_BIT_32(5)
956%define X86_PTE_D RT_BIT_32(6)
957%define X86_PTE_PAT RT_BIT_32(7)
958%define X86_PTE_G RT_BIT_32(8)
959%define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
960%define X86_PTE_PG_MASK ( 0xfffff000 )
961%define X86_PTE_PAE_PG_MASK 0x000ffffffffff000
962%define X86_PTE_PAE_NX RT_BIT_64(63)
963%define X86_PTE_PAE_MBZ_MASK_NX 0x7ff0000000000000
964%define X86_PTE_PAE_MBZ_MASK_NO_NX 0xfff0000000000000
965%define X86_PTE_LM_MBZ_MASK_NX 0x0000000000000000
966%define X86_PTE_LM_MBZ_MASK_NO_NX 0x8000000000000000
967%ifndef VBOX_FOR_DTRACE_LIB
968%endif
969%ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
970%endif
971%ifndef VBOX_FOR_DTRACE_LIB
972%endif
973%ifndef VBOX_FOR_DTRACE_LIB
974%endif
975%ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
976%endif
977%ifndef VBOX_FOR_DTRACE_LIB
978%endif
979%ifndef VBOX_FOR_DTRACE_LIB
980%endif
981%define X86_PT_SHIFT 12
982%define X86_PT_MASK 0x3ff
983%ifndef VBOX_FOR_DTRACE_LIB
984%endif
985%define X86_PT_PAE_SHIFT 12
986%define X86_PT_PAE_MASK 0x1ff
987%define X86_PDE_P RT_BIT_32(0)
988%define X86_PDE_RW RT_BIT_32(1)
989%define X86_PDE_US RT_BIT_32(2)
990%define X86_PDE_PWT RT_BIT_32(3)
991%define X86_PDE_PCD RT_BIT_32(4)
992%define X86_PDE_A RT_BIT_32(5)
993%define X86_PDE_PS RT_BIT_32(7)
994%define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
995%define X86_PDE_PG_MASK ( 0xfffff000 )
996%define X86_PDE_PAE_PG_MASK 0x000ffffffffff000
997%define X86_PDE_PAE_NX RT_BIT_64(63)
998%define X86_PDE_PAE_MBZ_MASK_NX 0x7ff0000000000080
999%define X86_PDE_PAE_MBZ_MASK_NO_NX 0xfff0000000000080
1000%define X86_PDE_LM_MBZ_MASK_NX 0x0000000000000080
1001%define X86_PDE_LM_MBZ_MASK_NO_NX 0x8000000000000080
1002%ifndef VBOX_FOR_DTRACE_LIB
1003%endif
1004%ifndef VBOX_FOR_DTRACE_LIB
1005%endif
1006%define X86_PDE4M_P RT_BIT_32(0)
1007%define X86_PDE4M_RW RT_BIT_32(1)
1008%define X86_PDE4M_US RT_BIT_32(2)
1009%define X86_PDE4M_PWT RT_BIT_32(3)
1010%define X86_PDE4M_PCD RT_BIT_32(4)
1011%define X86_PDE4M_A RT_BIT_32(5)
1012%define X86_PDE4M_D RT_BIT_32(6)
1013%define X86_PDE4M_PS RT_BIT_32(7)
1014%define X86_PDE4M_G RT_BIT_32(8)
1015%define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1016%define X86_PDE4M_PAT RT_BIT_32(12)
1017%define X86_PDE4M_PAT_SHIFT (12 - 7)
1018%define X86_PDE4M_PG_MASK ( 0xffc00000 )
1019%define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1020%define X86_PDE4M_PG_HIGH_SHIFT 19
1021%define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1022%define X86_PDE2M_PAE_PG_MASK 0x000fffffffe00000
1023%define X86_PDE2M_PAE_NX RT_BIT_64(63)
1024%define X86_PDE2M_PAE_MBZ_MASK_NX 0x7ff00000001fe000
1025%define X86_PDE2M_PAE_MBZ_MASK_NO_NX 0xfff00000001fe000
1026%define X86_PDE2M_LM_MBZ_MASK_NX 0x00000000001fe000
1027%define X86_PDE2M_LM_MBZ_MASK_NO_NX 0x80000000001fe000
1028%ifndef VBOX_FOR_DTRACE_LIB
1029%endif
1030%ifndef VBOX_FOR_DTRACE_LIB
1031%endif
1032%ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
1033%endif
1034%ifndef VBOX_FOR_DTRACE_LIB
1035%endif
1036%ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
1037%endif
1038%ifndef VBOX_FOR_DTRACE_LIB
1039%endif
1040%ifndef VBOX_FOR_DTRACE_LIB
1041%endif
1042%define X86_PD_SHIFT 22
1043%define X86_PD_MASK 0x3ff
1044%ifndef VBOX_FOR_DTRACE_LIB
1045%endif
1046%define X86_PD_PAE_SHIFT 21
1047%define X86_PD_PAE_MASK 0x1ff
1048%define X86_PDPE_P RT_BIT_32(0)
1049%define X86_PDPE_RW RT_BIT_32(1)
1050%define X86_PDPE_US RT_BIT_32(2)
1051%define X86_PDPE_PWT RT_BIT_32(3)
1052%define X86_PDPE_PCD RT_BIT_32(4)
1053%define X86_PDPE_A RT_BIT_32(5)
1054%define X86_PDPE_LM_PS RT_BIT_32(7)
1055%define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1056%define X86_PDPE_PG_MASK 0x000ffffffffff000
1057%define X86_PDPE1G_PG_MASK 0x000fffffc0000000
1058%define X86_PDPE_PAE_MBZ_MASK 0xfff00000000001e6
1059%define X86_PDPE_LM_NX RT_BIT_64(63)
1060%define X86_PDPE_LM_MBZ_MASK_NX 0x0000000000000180
1061%define X86_PDPE_LM_MBZ_MASK_NO_NX 0x8000000000000180
1062%define X86_PDPE1G_LM_MBZ_MASK_NX 0x000000003fffe000
1063%define X86_PDPE1G_LM_MBZ_MASK_NO_NX 0x800000003fffe000
1064%ifndef VBOX_FOR_DTRACE_LIB
1065%endif
1066%ifndef VBOX_FOR_DTRACE_LIB
1067%endif
1068%ifndef VBOX_FOR_DTRACE_LIB
1069%endif
1070%ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
1071%endif
1072%ifndef VBOX_FOR_DTRACE_LIB
1073%endif
1074%ifndef VBOX_FOR_DTRACE_LIB
1075%endif
1076%define X86_PDPT_SHIFT 30
1077%define X86_PDPT_MASK_PAE 0x3
1078%define X86_PDPT_MASK_AMD64 0x1ff
1079%define X86_PML4E_P RT_BIT_32(0)
1080%define X86_PML4E_RW RT_BIT_32(1)
1081%define X86_PML4E_US RT_BIT_32(2)
1082%define X86_PML4E_PWT RT_BIT_32(3)
1083%define X86_PML4E_PCD RT_BIT_32(4)
1084%define X86_PML4E_A RT_BIT_32(5)
1085%define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1086%define X86_PML4E_PG_MASK 0x000ffffffffff000
1087%define X86_PML4E_MBZ_MASK_NX 0x0000000000000080
1088%define X86_PML4E_MBZ_MASK_NO_NX 0x8000000000000080
1089%define X86_PML4E_NX RT_BIT_64(63)
1090%ifndef VBOX_FOR_DTRACE_LIB
1091%endif
1092%ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
1093%endif
1094%ifndef VBOX_FOR_DTRACE_LIB
1095%endif
1096%ifndef VBOX_FOR_DTRACE_LIB
1097%endif
1098%define X86_PML4_SHIFT 39
1099%define X86_PML4_MASK 0x1ff
1100%define X86_INVPCID_TYPE_INDV_ADDR 0
1101%define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
1102%define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
1103%define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
1104%define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
1105%define X86_FPU_INT64_INDEFINITE INT64_MIN
1106%define X86_FPU_INT32_INDEFINITE INT32_MIN
1107%define X86_FPU_INT16_INDEFINITE INT16_MIN
1108%ifndef VBOX_FOR_DTRACE_LIB
1109%endif
1110%ifndef VBOX_FOR_DTRACE_LIB
1111%endif
1112%ifndef VBOX_FOR_DTRACE_LIB
1113%endif
1114%ifndef VBOX_FOR_DTRACE_LIB
1115%endif
1116%ifndef VBOX_FOR_DTRACE_LIB
1117%endif
1118%ifndef VBOX_FOR_DTRACE_LIB
1119%endif
1120%ifndef VBOX_FOR_DTRACE_LIB
1121%endif
1122%ifndef VBOX_FOR_DTRACE_LIB
1123%endif
1124%define X86_OFF_FXSTATE_RSVD 0x1d0
1125%define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
1126%ifndef VBOX_FOR_DTRACE_LIB
1127%endif
1128%define X86_FSW_IE RT_BIT_32(0)
1129%define X86_FSW_IE_BIT 0
1130%define X86_FSW_DE RT_BIT_32(1)
1131%define X86_FSW_DE_BIT 1
1132%define X86_FSW_ZE RT_BIT_32(2)
1133%define X86_FSW_ZE_BIT 2
1134%define X86_FSW_OE RT_BIT_32(3)
1135%define X86_FSW_OE_BIT 3
1136%define X86_FSW_UE RT_BIT_32(4)
1137%define X86_FSW_UE_BIT 4
1138%define X86_FSW_PE RT_BIT_32(5)
1139%define X86_FSW_PE_BIT 5
1140%define X86_FSW_SF RT_BIT_32(6)
1141%define X86_FSW_SF_BIT 6
1142%define X86_FSW_ES RT_BIT_32(7)
1143%define X86_FSW_ES_BIT 7
1144%define X86_FSW_XCPT_MASK 0x007f
1145%define X86_FSW_XCPT_ES_MASK 0x00ff
1146%define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
1147%define X86_FSW_C0_BIT 8
1148%define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
1149%define X86_FSW_C1_BIT 9
1150%define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
1151%define X86_FSW_C2_BIT 10
1152%define X86_FSW_TOP_MASK 0x3800
1153%define X86_FSW_TOP_SHIFT 11
1154%define X86_FSW_TOP_SMASK 0x0007
1155%define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
1156%define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
1157%define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
1158%define X86_FSW_C3_BIT 14
1159%define X86_FSW_C_MASK 0x4700
1160%define X86_FSW_B RT_BIT_32(15)
1161%define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
1162 ( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
1163 | (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
1164 | (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
1165%define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
1166 ( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
1167 | ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
1168 | ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
1169%define X86_FCW_IM RT_BIT_32(0)
1170%define X86_FCW_IM_BIT 0
1171%define X86_FCW_DM RT_BIT_32(1)
1172%define X86_FCW_DM_BIT 1
1173%define X86_FCW_ZM RT_BIT_32(2)
1174%define X86_FCW_ZM_BIT 2
1175%define X86_FCW_OM RT_BIT_32(3)
1176%define X86_FCW_OM_BIT 3
1177%define X86_FCW_UM RT_BIT_32(4)
1178%define X86_FCW_UM_BIT 4
1179%define X86_FCW_PM RT_BIT_32(5)
1180%define X86_FCW_PM_BIT 5
1181%define X86_FCW_MASK_ALL 0x007f
1182%define X86_FCW_XCPT_MASK 0x003f
1183%define X86_FCW_PC_MASK 0x0300
1184%define X86_FCW_PC_SHIFT 8
1185%define X86_FCW_PC_24 0x0000
1186%define X86_FCW_PC_RSVD 0x0100
1187%define X86_FCW_PC_53 0x0200
1188%define X86_FCW_PC_64 0x0300
1189%define X86_FCW_RC_MASK 0x0c00
1190%define X86_FCW_RC_SHIFT 10
1191%define X86_FCW_RC_NEAREST 0x0000
1192%define X86_FCW_RC_DOWN 0x0400
1193%define X86_FCW_RC_UP 0x0800
1194%define X86_FCW_RC_ZERO 0x0c00
1195%define X86_FCW_IC_MASK 0x1000
1196%define X86_FCW_IC_AFFINE 0x1000
1197%define X86_FCW_IC_PROJECTIVE 0x0000
1198%define X86_FCW_ZERO_MASK 0xf080
1199%define X86_MXCSR_IE RT_BIT_32(0)
1200%define X86_MXCSR_DE RT_BIT_32(1)
1201%define X86_MXCSR_ZE RT_BIT_32(2)
1202%define X86_MXCSR_OE RT_BIT_32(3)
1203%define X86_MXCSR_UE RT_BIT_32(4)
1204%define X86_MXCSR_PE RT_BIT_32(5)
1205%define X86_MXCSR_XCPT_FLAGS 0x003f
1206%define X86_MXCSR_DAZ RT_BIT_32(6)
1207%define X86_MXCSR_IM RT_BIT_32(7)
1208%define X86_MXCSR_DM RT_BIT_32(8)
1209%define X86_MXCSR_ZM RT_BIT_32(9)
1210%define X86_MXCSR_OM RT_BIT_32(10)
1211%define X86_MXCSR_UM RT_BIT_32(11)
1212%define X86_MXCSR_PM RT_BIT_32(12)
1213%define X86_MXCSR_XCPT_MASK 0x1f80
1214%define X86_MXCSR_XCPT_MASK_SHIFT 7
1215%define X86_MXCSR_RC_MASK 0x6000
1216%define X86_MXCSR_RC_SHIFT 13
1217%define X86_MXCSR_RC_NEAREST 0x0000
1218%define X86_MXCSR_RC_DOWN 0x2000
1219%define X86_MXCSR_RC_UP 0x4000
1220%define X86_MXCSR_RC_ZERO 0x6000
1221%define X86_MXCSR_FZ RT_BIT_32(15)
1222%define X86_MXCSR_MM RT_BIT_32(17)
1223%define X86_MXCSR_ZERO_MASK 0xfffd0000
1224%ifndef VBOX_FOR_DTRACE_LIB
1225%endif
1226%ifndef VBOX_FOR_DTRACE_LIB
1227%endif
1228%ifndef VBOX_FOR_DTRACE_LIB
1229%endif
1230%ifndef VBOX_FOR_DTRACE_LIB
1231%endif
1232%ifndef VBOX_FOR_DTRACE_LIB
1233%endif
1234%ifndef VBOX_FOR_DTRACE_LIB
1235%endif
1236%ifndef VBOX_FOR_DTRACE_LIB
1237%endif
1238%ifndef VBOX_FOR_DTRACE_LIB
1239%endif
1240%ifndef VBOX_FOR_DTRACE_LIB
1241%endif
1242%define XSAVE_C_X87_BIT 0
1243%define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
1244%define XSAVE_C_SSE_BIT 1
1245%define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
1246%define XSAVE_C_YMM_BIT 2
1247%define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
1248%define XSAVE_C_BNDREGS_BIT 3
1249%define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
1250%define XSAVE_C_BNDCSR_BIT 4
1251%define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
1252%define XSAVE_C_OPMASK_BIT 5
1253%define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
1254%define XSAVE_C_ZMM_HI256_BIT 6
1255%define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
1256%define XSAVE_C_ZMM_16HI_BIT 7
1257%define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
1258%define XSAVE_C_PKRU_BIT 9
1259%define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
1260%define XSAVE_C_LWP_BIT 62
1261%define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
1262%define XSAVE_C_X_BIT 63
1263%define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
1264%ifndef VBOX_FOR_DTRACE_LIB
1265%endif
1266%define X86DESCATTR_TYPE 0x0000000f
1267%define X86DESCATTR_DT 0x00000010
1268%define X86DESCATTR_DPL 0x00000060
1269%define X86DESCATTR_DPL_SHIFT 5
1270%define X86DESCATTR_P 0x00000080
1271%define X86DESCATTR_LIMIT_HIGH 0x00000f00
1272%define X86DESCATTR_AVL 0x00001000
1273%define X86DESCATTR_L 0x00002000
1274%define X86DESCATTR_D 0x00004000
1275%define X86DESCATTR_G 0x00008000
1276%define X86DESCATTR_UNUSABLE 0x00010000
1277%ifndef VBOX_FOR_DTRACE_LIB
1278%endif
1279%ifndef VBOX_FOR_DTRACE_LIB
1280%define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0)
1281%define X86DESCGENERIC_BIT_OFF_BASE_LOW (16)
1282%define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32)
1283%define X86DESCGENERIC_BIT_OFF_TYPE (40)
1284%define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44)
1285%define X86DESCGENERIC_BIT_OFF_DPL (45)
1286%define X86DESCGENERIC_BIT_OFF_PRESENT (47)
1287%define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48)
1288%define X86DESCGENERIC_BIT_OFF_AVAILABLE (52)
1289%define X86DESCGENERIC_BIT_OFF_LONG (53)
1290%define X86DESCGENERIC_BIT_OFF_DEF_BIG (54)
1291%define X86DESCGENERIC_BIT_OFF_GRANULARITY (55)
1292%define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56)
1293%define X86LAR_F_TYPE 0x0f00
1294%define X86LAR_F_DT 0x1000
1295%define X86LAR_F_DPL 0x6000
1296%define X86LAR_F_DPL_SHIFT 13
1297%define X86LAR_F_P 0x8000
1298%define X86LAR_F_AVL 0x00100000
1299%define X86LAR_F_L 0x00200000
1300%define X86LAR_F_D 0x00400000
1301%define X86LAR_F_G 0x00800000
1302%endif
1303%ifndef VBOX_FOR_DTRACE_LIB
1304%endif
1305%ifndef VBOX_FOR_DTRACE_LIB
1306%endif
1307%ifndef VBOX_FOR_DTRACE_LIB
1308%endif
1309%ifndef VBOX_FOR_DTRACE_LIB
1310%endif
1311%ifndef VBOX_FOR_DTRACE_LIB
1312%endif
1313%if HC_ARCH_BITS == 64
1314%else
1315%endif
1316%if HC_ARCH_BITS == 64
1317%else
1318%endif
1319%if HC_ARCH_BITS == 64
1320%else
1321%endif
1322%define X86_SEL_TYPE_CODE 8
1323%define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
1324%define X86_SEL_TYPE_ACCESSED 1
1325%define X86_SEL_TYPE_DOWN 4
1326%define X86_SEL_TYPE_CONF 4
1327%define X86_SEL_TYPE_WRITE 2
1328%define X86_SEL_TYPE_READ 2
1329%define X86_SEL_TYPE_READ_BIT 1
1330%define X86_SEL_TYPE_RO 0
1331%define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
1332%define X86_SEL_TYPE_RW 2
1333%define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
1334%define X86_SEL_TYPE_RO_DOWN 4
1335%define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
1336%define X86_SEL_TYPE_RW_DOWN 6
1337%define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
1338%define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
1339%define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
1340%define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
1341%define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
1342%define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
1343%define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
1344%define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
1345%define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
1346%define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
1347%define X86_SEL_TYPE_SYS_UNDEFINED 0
1348%define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
1349%define X86_SEL_TYPE_SYS_LDT 2
1350%define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
1351%define X86_SEL_TYPE_SYS_286_CALL_GATE 4
1352%define X86_SEL_TYPE_SYS_TASK_GATE 5
1353%define X86_SEL_TYPE_SYS_286_INT_GATE 6
1354%define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
1355%define X86_SEL_TYPE_SYS_UNDEFINED2 8
1356%define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
1357%define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
1358%define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
1359%define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
1360%define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
1361%define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
1362%define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
1363%define AMD64_SEL_TYPE_SYS_LDT 2
1364%define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
1365%define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
1366%define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
1367%define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
1368%define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
1369%define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1370%define X86_DESC_S RT_BIT_32(12)
1371%define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
1372%define X86_DESC_P RT_BIT_32(15)
1373%define X86_DESC_AVL RT_BIT_32(20)
1374%define X86_DESC_DB RT_BIT_32(22)
1375%define X86_DESC_G RT_BIT_32(23)
1376%define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
1377%define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
1378%ifndef VBOX_FOR_DTRACE_LIB
1379%endif
1380%ifndef VBOX_FOR_DTRACE_LIB
1381%endif
1382%ifndef VBOX_FOR_DTRACE_LIB
1383%endif
1384%define X86_SEL_SHIFT 3
1385%define X86_SEL_MASK 0xfff8
1386%define X86_SEL_MASK_OFF_RPL 0xfffc
1387%define X86_SEL_LDT 0x0004
1388%define X86_SEL_RPL 0x0003
1389%define X86_SEL_RPL_LDT 0x0007
1390%define X86_XCPT_LAST 0x1f
1391%define X86_TRAP_ERR_EXTERNAL 1
1392%define X86_TRAP_ERR_IDT 2
1393%define X86_TRAP_ERR_TI 4
1394%define X86_TRAP_ERR_SEL_MASK 0xfff8
1395%define X86_TRAP_ERR_SEL_SHIFT 3
1396%define X86_TRAP_PF_P RT_BIT_32(0)
1397%define X86_TRAP_PF_RW RT_BIT_32(1)
1398%define X86_TRAP_PF_US RT_BIT_32(2)
1399%define X86_TRAP_PF_RSVD RT_BIT_32(3)
1400%define X86_TRAP_PF_ID RT_BIT_32(4)
1401%define X86_TRAP_PF_PK RT_BIT_32(5)
1402%ifndef VBOX_FOR_DTRACE_LIB
1403%else
1404%endif
1405%ifndef VBOX_FOR_DTRACE_LIB
1406%else
1407%endif
1408%define X86_MODRM_RM_MASK 0x07
1409%define X86_MODRM_REG_MASK 0x38
1410%define X86_MODRM_REG_SMASK 0x07
1411%define X86_MODRM_REG_SHIFT 3
1412%define X86_MODRM_MOD_MASK 0xc0
1413%define X86_MODRM_MOD_SMASK 0x03
1414%define X86_MODRM_MOD_SHIFT 6
1415%define X86_MOD_MEM0 0
1416%define X86_MOD_MEM1 1
1417%define X86_MOD_MEM4 2
1418%define X86_MOD_REG 3
1419%ifndef VBOX_FOR_DTRACE_LIB
1420 %define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
1421%endif
1422%define X86_SIB_BASE_MASK 0x07
1423%define X86_SIB_INDEX_MASK 0x38
1424%define X86_SIB_INDEX_SMASK 0x07
1425%define X86_SIB_INDEX_SHIFT 3
1426%define X86_SIB_SCALE_MASK 0xc0
1427%define X86_SIB_SCALE_SMASK 0x03
1428%define X86_SIB_SCALE_SHIFT 6
1429%ifndef VBOX_FOR_DTRACE_LIB
1430 %define X86_SIB_MAKE(a_BaseReg, a_IndexReg, a_Scale) \
1431 (((a_Scale) << X86_SIB_SCALE_SHIFT) | ((a_IndexReg) << X86_SIB_INDEX_SHIFT) | (a_BaseReg))
1432%endif
1433%define X86_GREG_xAX 0
1434%define X86_GREG_xCX 1
1435%define X86_GREG_xDX 2
1436%define X86_GREG_xBX 3
1437%define X86_GREG_xSP 4
1438%define X86_GREG_xBP 5
1439%define X86_GREG_xSI 6
1440%define X86_GREG_xDI 7
1441%define X86_GREG_x8 8
1442%define X86_GREG_x9 9
1443%define X86_GREG_x10 10
1444%define X86_GREG_x11 11
1445%define X86_GREG_x12 12
1446%define X86_GREG_x13 13
1447%define X86_GREG_x14 14
1448%define X86_GREG_x15 15
1449%define X86_GREG_COUNT 16
1450%define X86_SREG_ES 0
1451%define X86_SREG_CS 1
1452%define X86_SREG_SS 2
1453%define X86_SREG_DS 3
1454%define X86_SREG_FS 4
1455%define X86_SREG_GS 5
1456%define X86_SREG_COUNT 6
1457%define X86_OP_PRF_CS 0x2e
1458%define X86_OP_PRF_SS 0x36
1459%define X86_OP_PRF_DS 0x3e
1460%define X86_OP_PRF_ES 0x26
1461%define X86_OP_PRF_FS 0x64
1462%define X86_OP_PRF_GS 0x65
1463%define X86_OP_PRF_SIZE_OP 0x66
1464%define X86_OP_PRF_SIZE_ADDR 0x67
1465%define X86_OP_PRF_LOCK 0xf0
1466%define X86_OP_PRF_REPZ 0xf3
1467%define X86_OP_PRF_REPNZ 0xf2
1468%define X86_OP_REX 0x40
1469%define X86_OP_REX_B 0x41
1470%define X86_OP_REX_X 0x42
1471%define X86_OP_REX_R 0x44
1472%define X86_OP_REX_W 0x48
1473%endif
1474%include "iprt/x86extra.mac"
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