VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 96798

Last change on this file since 96798 was 96798, checked in by vboxsync, 2 years ago

VMM/IEM: Implement cvtdq2ps/cvtps2dq/cvttps2dq/cvttpd2dq/cvtdq2pd/cvtpd2dq instructions, bugref:9898 [missing file]

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1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2022 Oracle and/or its affiliates.
9 *
10 * This file is part of VirtualBox base platform packages, as
11 * available from https://www.virtualbox.org.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation, in version 3 of the
16 * License.
17 *
18 * This program is distributed in the hope that it will be useful, but
19 * WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, see <https://www.gnu.org/licenses>.
25 *
26 * The contents of this file may alternatively be used under the terms
27 * of the Common Development and Distribution License Version 1.0
28 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
29 * in the VirtualBox distribution, in which case the provisions of the
30 * CDDL are applicable instead of those of the GPL.
31 *
32 * You may elect to license modified versions of this file under the
33 * terms and conditions of either the GPL or the CDDL or both.
34 *
35 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
36 */
37
38#ifndef IPRT_INCLUDED_x86_h
39#define IPRT_INCLUDED_x86_h
40#ifndef RT_WITHOUT_PRAGMA_ONCE
41# pragma once
42#endif
43
44#ifndef VBOX_FOR_DTRACE_LIB
45# include <iprt/types.h>
46# include <iprt/assert.h>
47#else
48# pragma D depends_on library vbox-types.d
49#endif
50
51/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
52 * defining MSR_IA32_FLUSH_CMD */
53#ifdef RT_OS_SOLARIS
54# undef CS
55# undef DS
56# undef MSR_IA32_FLUSH_CMD
57#endif
58
59/** @defgroup grp_rt_x86 x86 Types and Definitions
60 * @ingroup grp_rt
61 * @{
62 */
63
64#ifndef VBOX_FOR_DTRACE_LIB
65/**
66 * EFLAGS Bits.
67 */
68typedef struct X86EFLAGSBITS
69{
70 /** Bit 0 - CF - Carry flag - Status flag. */
71 unsigned u1CF : 1;
72 /** Bit 1 - 1 - Reserved flag. */
73 unsigned u1Reserved0 : 1;
74 /** Bit 2 - PF - Parity flag - Status flag. */
75 unsigned u1PF : 1;
76 /** Bit 3 - 0 - Reserved flag. */
77 unsigned u1Reserved1 : 1;
78 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
79 unsigned u1AF : 1;
80 /** Bit 5 - 0 - Reserved flag. */
81 unsigned u1Reserved2 : 1;
82 /** Bit 6 - ZF - Zero flag - Status flag. */
83 unsigned u1ZF : 1;
84 /** Bit 7 - SF - Signed flag - Status flag. */
85 unsigned u1SF : 1;
86 /** Bit 8 - TF - Trap flag - System flag. */
87 unsigned u1TF : 1;
88 /** Bit 9 - IF - Interrupt flag - System flag. */
89 unsigned u1IF : 1;
90 /** Bit 10 - DF - Direction flag - Control flag. */
91 unsigned u1DF : 1;
92 /** Bit 11 - OF - Overflow flag - Status flag. */
93 unsigned u1OF : 1;
94 /** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
95 unsigned u2IOPL : 2;
96 /** Bit 14 - NT - Nested task flag - System flag. */
97 unsigned u1NT : 1;
98 /** Bit 15 - 0 - Reserved flag. */
99 unsigned u1Reserved3 : 1;
100 /** Bit 16 - RF - Resume flag - System flag. */
101 unsigned u1RF : 1;
102 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
103 unsigned u1VM : 1;
104 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
105 unsigned u1AC : 1;
106 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
107 unsigned u1VIF : 1;
108 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
109 unsigned u1VIP : 1;
110 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
111 unsigned u1ID : 1;
112 /** Bit 22-31 - 0 - Reserved flag. */
113 unsigned u10Reserved4 : 10;
114} X86EFLAGSBITS;
115/** Pointer to EFLAGS bits. */
116typedef X86EFLAGSBITS *PX86EFLAGSBITS;
117/** Pointer to const EFLAGS bits. */
118typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
119#endif /* !VBOX_FOR_DTRACE_LIB */
120
121/**
122 * EFLAGS.
123 */
124typedef union X86EFLAGS
125{
126 /** The plain unsigned view. */
127 uint32_t u;
128#ifndef VBOX_FOR_DTRACE_LIB
129 /** The bitfield view. */
130 X86EFLAGSBITS Bits;
131#endif
132 /** The 8-bit view. */
133 uint8_t au8[4];
134 /** The 16-bit view. */
135 uint16_t au16[2];
136 /** The 32-bit view. */
137 uint32_t au32[1];
138 /** The 32-bit view. */
139 uint32_t u32;
140} X86EFLAGS;
141/** Pointer to EFLAGS. */
142typedef X86EFLAGS *PX86EFLAGS;
143/** Pointer to const EFLAGS. */
144typedef const X86EFLAGS *PCX86EFLAGS;
145
146/**
147 * RFLAGS (32 upper bits are reserved).
148 */
149typedef union X86RFLAGS
150{
151 /** The plain unsigned view. */
152 uint64_t u;
153#ifndef VBOX_FOR_DTRACE_LIB
154 /** The bitfield view. */
155 X86EFLAGSBITS Bits;
156#endif
157 /** The 8-bit view. */
158 uint8_t au8[8];
159 /** The 16-bit view. */
160 uint16_t au16[4];
161 /** The 32-bit view. */
162 uint32_t au32[2];
163 /** The 64-bit view. */
164 uint64_t au64[1];
165 /** The 64-bit view. */
166 uint64_t u64;
167} X86RFLAGS;
168/** Pointer to RFLAGS. */
169typedef X86RFLAGS *PX86RFLAGS;
170/** Pointer to const RFLAGS. */
171typedef const X86RFLAGS *PCX86RFLAGS;
172
173
174/** @name EFLAGS
175 * @{
176 */
177/** Bit 0 - CF - Carry flag - Status flag. */
178#define X86_EFL_CF RT_BIT_32(0)
179#define X86_EFL_CF_BIT 0
180/** Bit 1 - Reserved, reads as 1. */
181#define X86_EFL_1 RT_BIT_32(1)
182/** Bit 2 - PF - Parity flag - Status flag. */
183#define X86_EFL_PF RT_BIT_32(2)
184#define X86_EFL_PF_BIT 2
185/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
186#define X86_EFL_AF RT_BIT_32(4)
187#define X86_EFL_AF_BIT 4
188/** Bit 6 - ZF - Zero flag - Status flag. */
189#define X86_EFL_ZF RT_BIT_32(6)
190#define X86_EFL_ZF_BIT 6
191/** Bit 7 - SF - Signed flag - Status flag. */
192#define X86_EFL_SF RT_BIT_32(7)
193#define X86_EFL_SF_BIT 7
194/** Bit 8 - TF - Trap flag - System flag. */
195#define X86_EFL_TF RT_BIT_32(8)
196#define X86_EFL_TF_BIT 8
197/** Bit 9 - IF - Interrupt flag - System flag. */
198#define X86_EFL_IF RT_BIT_32(9)
199#define X86_EFL_IF_BIT 9
200/** Bit 10 - DF - Direction flag - Control flag. */
201#define X86_EFL_DF RT_BIT_32(10)
202#define X86_EFL_DF_BIT 10
203/** Bit 11 - OF - Overflow flag - Status flag. */
204#define X86_EFL_OF RT_BIT_32(11)
205#define X86_EFL_OF_BIT 11
206/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
207#define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
208/** Bit 14 - NT - Nested task flag - System flag. */
209#define X86_EFL_NT RT_BIT_32(14)
210#define X86_EFL_NT_BIT 14
211/** Bit 16 - RF - Resume flag - System flag. */
212#define X86_EFL_RF RT_BIT_32(16)
213#define X86_EFL_RF_BIT 16
214/** Bit 17 - VM - Virtual 8086 mode - System flag. */
215#define X86_EFL_VM RT_BIT_32(17)
216#define X86_EFL_VM_BIT 17
217/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
218#define X86_EFL_AC RT_BIT_32(18)
219#define X86_EFL_AC_BIT 18
220/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
221#define X86_EFL_VIF RT_BIT_32(19)
222#define X86_EFL_VIF_BIT 19
223/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
224#define X86_EFL_VIP RT_BIT_32(20)
225#define X86_EFL_VIP_BIT 20
226/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
227#define X86_EFL_ID RT_BIT_32(21)
228#define X86_EFL_ID_BIT 21
229/** All live bits. */
230#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
231/** Read as 1 bits. */
232#define X86_EFL_RA1_MASK RT_BIT_32(1)
233/** IOPL shift. */
234#define X86_EFL_IOPL_SHIFT 12
235/** The IOPL level from the flags. */
236#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
237/** Bits restored by popf */
238#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
239 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
240/** Bits restored by popf */
241#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
242 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
243/** The status bits commonly updated by arithmetic instructions. */
244#define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
245/** @} */
246
247
248/** CPUID Feature information - ECX.
249 * CPUID query with EAX=1.
250 */
251#ifndef VBOX_FOR_DTRACE_LIB
252typedef struct X86CPUIDFEATECX
253{
254 /** Bit 0 - SSE3 - Supports SSE3 or not. */
255 unsigned u1SSE3 : 1;
256 /** Bit 1 - PCLMULQDQ. */
257 unsigned u1PCLMULQDQ : 1;
258 /** Bit 2 - DS Area 64-bit layout. */
259 unsigned u1DTE64 : 1;
260 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
261 unsigned u1Monitor : 1;
262 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
263 unsigned u1CPLDS : 1;
264 /** Bit 5 - VMX - Virtual Machine Technology. */
265 unsigned u1VMX : 1;
266 /** Bit 6 - SMX: Safer Mode Extensions. */
267 unsigned u1SMX : 1;
268 /** Bit 7 - EST - Enh. SpeedStep Tech. */
269 unsigned u1EST : 1;
270 /** Bit 8 - TM2 - Terminal Monitor 2. */
271 unsigned u1TM2 : 1;
272 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
273 unsigned u1SSSE3 : 1;
274 /** Bit 10 - CNTX-ID - L1 Context ID. */
275 unsigned u1CNTXID : 1;
276 /** Bit 11 - Reserved. */
277 unsigned u1Reserved1 : 1;
278 /** Bit 12 - FMA. */
279 unsigned u1FMA : 1;
280 /** Bit 13 - CX16 - CMPXCHG16B. */
281 unsigned u1CX16 : 1;
282 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
283 unsigned u1TPRUpdate : 1;
284 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
285 unsigned u1PDCM : 1;
286 /** Bit 16 - Reserved. */
287 unsigned u1Reserved2 : 1;
288 /** Bit 17 - PCID - Process-context identifiers. */
289 unsigned u1PCID : 1;
290 /** Bit 18 - Direct Cache Access. */
291 unsigned u1DCA : 1;
292 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
293 unsigned u1SSE4_1 : 1;
294 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
295 unsigned u1SSE4_2 : 1;
296 /** Bit 21 - x2APIC. */
297 unsigned u1x2APIC : 1;
298 /** Bit 22 - MOVBE - Supports MOVBE. */
299 unsigned u1MOVBE : 1;
300 /** Bit 23 - POPCNT - Supports POPCNT. */
301 unsigned u1POPCNT : 1;
302 /** Bit 24 - TSC-Deadline. */
303 unsigned u1TSCDEADLINE : 1;
304 /** Bit 25 - AES. */
305 unsigned u1AES : 1;
306 /** Bit 26 - XSAVE - Supports XSAVE. */
307 unsigned u1XSAVE : 1;
308 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
309 unsigned u1OSXSAVE : 1;
310 /** Bit 28 - AVX - Supports AVX instruction extensions. */
311 unsigned u1AVX : 1;
312 /** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
313 unsigned u1F16C : 1;
314 /** Bit 30 - RDRAND - Supports RDRAND. */
315 unsigned u1RDRAND : 1;
316 /** Bit 31 - Hypervisor present (we're a guest). */
317 unsigned u1HVP : 1;
318} X86CPUIDFEATECX;
319#else /* VBOX_FOR_DTRACE_LIB */
320typedef uint32_t X86CPUIDFEATECX;
321#endif /* VBOX_FOR_DTRACE_LIB */
322/** Pointer to CPUID Feature Information - ECX. */
323typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
324/** Pointer to const CPUID Feature Information - ECX. */
325typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
326
327
328/** CPUID Feature Information - EDX.
329 * CPUID query with EAX=1.
330 */
331#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
332typedef struct X86CPUIDFEATEDX
333{
334 /** Bit 0 - FPU - x87 FPU on Chip. */
335 unsigned u1FPU : 1;
336 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
337 unsigned u1VME : 1;
338 /** Bit 2 - DE - Debugging extensions. */
339 unsigned u1DE : 1;
340 /** Bit 3 - PSE - Page Size Extension. */
341 unsigned u1PSE : 1;
342 /** Bit 4 - TSC - Time Stamp Counter. */
343 unsigned u1TSC : 1;
344 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
345 unsigned u1MSR : 1;
346 /** Bit 6 - PAE - Physical Address Extension. */
347 unsigned u1PAE : 1;
348 /** Bit 7 - MCE - Machine Check Exception. */
349 unsigned u1MCE : 1;
350 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
351 unsigned u1CX8 : 1;
352 /** Bit 9 - APIC - APIC On-Chip. */
353 unsigned u1APIC : 1;
354 /** Bit 10 - Reserved. */
355 unsigned u1Reserved1 : 1;
356 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
357 unsigned u1SEP : 1;
358 /** Bit 12 - MTRR - Memory Type Range Registers. */
359 unsigned u1MTRR : 1;
360 /** Bit 13 - PGE - PTE Global Bit. */
361 unsigned u1PGE : 1;
362 /** Bit 14 - MCA - Machine Check Architecture. */
363 unsigned u1MCA : 1;
364 /** Bit 15 - CMOV - Conditional Move Instructions. */
365 unsigned u1CMOV : 1;
366 /** Bit 16 - PAT - Page Attribute Table. */
367 unsigned u1PAT : 1;
368 /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
369 unsigned u1PSE36 : 1;
370 /** Bit 18 - PSN - Processor Serial Number. */
371 unsigned u1PSN : 1;
372 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
373 unsigned u1CLFSH : 1;
374 /** Bit 20 - Reserved. */
375 unsigned u1Reserved2 : 1;
376 /** Bit 21 - DS - Debug Store. */
377 unsigned u1DS : 1;
378 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
379 unsigned u1ACPI : 1;
380 /** Bit 23 - MMX - Intel MMX 'Technology'. */
381 unsigned u1MMX : 1;
382 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
383 unsigned u1FXSR : 1;
384 /** Bit 25 - SSE - SSE Support. */
385 unsigned u1SSE : 1;
386 /** Bit 26 - SSE2 - SSE2 Support. */
387 unsigned u1SSE2 : 1;
388 /** Bit 27 - SS - Self Snoop. */
389 unsigned u1SS : 1;
390 /** Bit 28 - HTT - Hyper-Threading Technology. */
391 unsigned u1HTT : 1;
392 /** Bit 29 - TM - Thermal Monitor. */
393 unsigned u1TM : 1;
394 /** Bit 30 - Reserved - . */
395 unsigned u1Reserved3 : 1;
396 /** Bit 31 - PBE - Pending Break Enabled. */
397 unsigned u1PBE : 1;
398} X86CPUIDFEATEDX;
399#else /* VBOX_FOR_DTRACE_LIB */
400typedef uint32_t X86CPUIDFEATEDX;
401#endif /* VBOX_FOR_DTRACE_LIB */
402/** Pointer to CPUID Feature Information - EDX. */
403typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
404/** Pointer to const CPUID Feature Information - EDX. */
405typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
406
407/** @name CPUID Vendor information.
408 * CPUID query with EAX=0.
409 * @{
410 */
411#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
412#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
413#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
414
415#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
416#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
417#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
418
419#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
420#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
421#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
422
423#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
424#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
425#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
426
427#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
428#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
429#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
430/** @} */
431
432
433/** @name CPUID Feature information.
434 * CPUID query with EAX=1.
435 * @{
436 */
437/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
438#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
439/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
440#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
441/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
442#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
443/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
444#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
445/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
446#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
447/** ECX Bit 5 - VMX - Virtual Machine Technology. */
448#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
449/** ECX Bit 6 - SMX - Safer Mode Extensions. */
450#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
451/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
452#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
453/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
454#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
455/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
456#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
457/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
458#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
459/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
460 * See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
461#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
462/** ECX Bit 12 - FMA. */
463#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
464/** ECX Bit 13 - CX16 - CMPXCHG16B. */
465#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
466/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
467#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
468/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
469#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
470/** ECX Bit 17 - PCID - Process-context identifiers. */
471#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
472/** ECX Bit 18 - DCA - Direct Cache Access. */
473#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
474/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
475#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
476/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
477#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
478/** ECX Bit 21 - x2APIC support. */
479#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
480/** ECX Bit 22 - MOVBE instruction. */
481#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
482/** ECX Bit 23 - POPCNT instruction. */
483#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
484/** ECX Bir 24 - TSC-Deadline. */
485#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
486/** ECX Bit 25 - AES instructions. */
487#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
488/** ECX Bit 26 - XSAVE instruction. */
489#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
490/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
491#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
492/** ECX Bit 28 - AVX. */
493#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
494/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
495#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
496/** ECX Bit 30 - RDRAND instruction. */
497#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
498/** ECX Bit 31 - Hypervisor Present (software only). */
499#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
500
501
502/** Bit 0 - FPU - x87 FPU on Chip. */
503#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
504/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
505#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
506/** Bit 2 - DE - Debugging extensions. */
507#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
508/** Bit 3 - PSE - Page Size Extension. */
509#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
510#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /**< Bit number for X86_CPUID_FEATURE_EDX_PSE. */
511/** Bit 4 - TSC - Time Stamp Counter. */
512#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
513/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
514#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
515/** Bit 6 - PAE - Physical Address Extension. */
516#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
517#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /**< Bit number for X86_CPUID_FEATURE_EDX_PAE. */
518/** Bit 7 - MCE - Machine Check Exception. */
519#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
520/** Bit 8 - CX8 - CMPXCHG8B instruction. */
521#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
522/** Bit 9 - APIC - APIC On-Chip. */
523#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
524/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
525#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
526/** Bit 12 - MTRR - Memory Type Range Registers. */
527#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
528/** Bit 13 - PGE - PTE Global Bit. */
529#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
530/** Bit 14 - MCA - Machine Check Architecture. */
531#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
532/** Bit 15 - CMOV - Conditional Move Instructions. */
533#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
534/** Bit 16 - PAT - Page Attribute Table. */
535#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
536/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
537#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
538/** Bit 18 - PSN - Processor Serial Number. */
539#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
540/** Bit 19 - CLFSH - CLFLUSH Instruction. */
541#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
542/** Bit 21 - DS - Debug Store. */
543#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
544/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
545#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
546/** Bit 23 - MMX - Intel MMX Technology. */
547#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
548/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
549#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
550/** Bit 25 - SSE - SSE Support. */
551#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
552/** Bit 26 - SSE2 - SSE2 Support. */
553#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
554/** Bit 27 - SS - Self Snoop. */
555#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
556/** Bit 28 - HTT - Hyper-Threading Technology. */
557#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
558/** Bit 29 - TM - Therm. Monitor. */
559#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
560/** Bit 31 - PBE - Pending Break Enabled. */
561#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
562/** @} */
563
564/** @name CPUID mwait/monitor information.
565 * CPUID query with EAX=5.
566 * @{
567 */
568/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
569#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
570/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
571#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
572/** @} */
573
574
575/** @name CPUID Structured Extended Feature information.
576 * CPUID query with EAX=7.
577 * @{
578 */
579/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
580#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
581/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
582#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
583/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
584#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
585/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
586#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
587/** EBX Bit 4 - HLE - Hardware Lock Elision. */
588#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
589/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
590#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
591/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
592#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
593/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
594#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
595/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
596#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
597/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
598#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
599/** EBX Bit 10 - INVPCID - Supports INVPCID. */
600#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
601/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
602#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
603/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
604#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
605/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
606#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
607/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
608#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
609/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
610#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
611/** EBX Bit 16 - AVX512F - Supports AVX512F. */
612#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
613/** EBX Bit 18 - RDSEED - Supports RDSEED. */
614#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
615/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
616#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
617/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
618#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
619/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
620#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
621/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
622#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
623/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
624#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
625/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
626#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
627/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
628#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
629/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
630#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
631
632/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
633#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
634/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
635#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
636/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
637#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
638/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
639#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
640/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
641#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
642/** ECX Bit 22 - RDPID - Support pread process ID. */
643#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
644/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
645#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
646
647/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
648#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
649/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
650 * IBPB command in IA32_PRED_CMD. */
651#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
652/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
653#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
654/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
655#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
656/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
657#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
658/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
659#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
660
661/** @} */
662
663
664/** @name CPUID Extended Feature information.
665 * CPUID query with EAX=0x80000001.
666 * @{
667 */
668/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
669#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
670
671/** EDX Bit 11 - SYSCALL/SYSRET. */
672#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
673/** EDX Bit 20 - No-Execute/Execute-Disable. */
674#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
675/** EDX Bit 26 - 1 GB large page. */
676#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
677/** EDX Bit 27 - RDTSCP. */
678#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
679/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
680#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
681/** @}*/
682
683/** @name CPUID AMD Feature information.
684 * CPUID query with EAX=0x80000001.
685 * @{
686 */
687/** Bit 0 - FPU - x87 FPU on Chip. */
688#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
689/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
690#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
691/** Bit 2 - DE - Debugging extensions. */
692#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
693/** Bit 3 - PSE - Page Size Extension. */
694#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
695/** Bit 4 - TSC - Time Stamp Counter. */
696#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
697/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
698#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
699/** Bit 6 - PAE - Physical Address Extension. */
700#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
701/** Bit 7 - MCE - Machine Check Exception. */
702#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
703/** Bit 8 - CX8 - CMPXCHG8B instruction. */
704#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
705/** Bit 9 - APIC - APIC On-Chip. */
706#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
707/** Bit 12 - MTRR - Memory Type Range Registers. */
708#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
709/** Bit 13 - PGE - PTE Global Bit. */
710#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
711/** Bit 14 - MCA - Machine Check Architecture. */
712#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
713/** Bit 15 - CMOV - Conditional Move Instructions. */
714#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
715/** Bit 16 - PAT - Page Attribute Table. */
716#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
717/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
718#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
719/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
720#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
721/** Bit 23 - MMX - Intel MMX Technology. */
722#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
723/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
724#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
725/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
726#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
727/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
728#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
729/** Bit 31 - 3DNOW - AMD 3DNow. */
730#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
731
732/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
733#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
734/** Bit 2 - SVM - AMD VM extensions. */
735#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
736/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
737#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
738/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
739#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
740/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
741#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
742/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
743#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
744/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
745#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
746/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
747#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
748/** Bit 9 - OSVW - AMD OS visible workaround. */
749#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
750/** Bit 10 - IBS - Instruct based sampling. */
751#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
752/** Bit 11 - XOP - Extended operation support (see APM6). */
753#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
754/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
755#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
756/** Bit 13 - WDT - AMD Watchdog timer support. */
757#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
758/** Bit 15 - LWP - Lightweight profiling support. */
759#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
760/** Bit 16 - FMA4 - Four operand FMA instruction support. */
761#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
762/** Bit 19 - NodeId - Indicates support for
763 * MSR_C001_100C[NodeId,NodesPerProcessr]. */
764#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
765/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
766#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
767/** Bit 22 - TopologyExtensions - . */
768#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
769/** @} */
770
771
772/** @name CPUID AMD Feature information.
773 * CPUID query with EAX=0x80000007.
774 * @{
775 */
776/** Bit 0 - TS - Temperature Sensor. */
777#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
778/** Bit 1 - FID - Frequency ID Control. */
779#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
780/** Bit 2 - VID - Voltage ID Control. */
781#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
782/** Bit 3 - TTP - THERMTRIP. */
783#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
784/** Bit 4 - TM - Hardware Thermal Control. */
785#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
786/** Bit 5 - STC - Software Thermal Control. */
787#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
788/** Bit 6 - MC - 100 Mhz Multiplier Control. */
789#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
790/** Bit 7 - HWPSTATE - Hardware P-State Control. */
791#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
792/** Bit 8 - TSCINVAR - TSC Invariant. */
793#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
794/** Bit 9 - CPB - TSC Invariant. */
795#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
796/** Bit 10 - EffFreqRO - MPERF/APERF. */
797#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
798/** Bit 11 - PFI - Processor feedback interface (see EAX). */
799#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
800/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
801#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
802/** @} */
803
804
805/** @name CPUID AMD extended feature extensions ID (EBX).
806 * CPUID query with EAX=0x80000008.
807 * @{
808 */
809/** Bit 0 - CLZERO - Clear zero instruction. */
810#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
811/** Bit 1 - IRPerf - Instructions retired count support. */
812#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
813/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
814#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
815/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
816#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
817/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
818#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
819/* AMD pipeline length: 9 feature bits ;-) */
820/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
821#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
822/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
823#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
824/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
825#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
826/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
827#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
828/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
829#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
830/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
831#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
832/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
833#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
834/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
835#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
836/** Bit 26 - Speculative Store Bypass Disable not required. */
837#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
838/** @} */
839
840
841/** @name CPUID AMD SVM Feature information.
842 * CPUID query with EAX=0x8000000a.
843 * @{
844 */
845/** Bit 0 - NP - Nested Paging supported. */
846#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
847/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
848#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
849/** Bit 2 - SVML - SVM locking bit supported. */
850#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
851/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
852#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
853/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
854#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
855/** Bit 5 - VmcbClean - Support VMCB clean bits. */
856#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
857/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
858 * VMCB.TLB_Control is supported. */
859#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
860/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
861#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
862/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
863#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
864/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
865 * intercept filter cycle count threshold. */
866#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
867/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
868#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
869/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
870#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
871/** Bit 16 - VGIF - Supports virtualized GIF. */
872#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
873/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
874#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
875/** Bit 19 - SSSCheck - SVM supervisor shadow stack restrictions. */
876#define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
877/** Bit 20 - SpecCtrl - Supports SPEC_CTRL Virtualization. */
878#define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
879/** Bit 23 - HOST_MCE_OVERRIDE - Supports host \#MC exception override. */
880#define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
881/** Bit 24 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
882#define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
883/** @} */
884
885
886/** @name CR0
887 * @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
888 * reserved flags.
889 * @{ */
890/** Bit 0 - PE - Protection Enabled */
891#define X86_CR0_PE RT_BIT_32(0)
892#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
893/** Bit 1 - MP - Monitor Coprocessor */
894#define X86_CR0_MP RT_BIT_32(1)
895#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
896/** Bit 2 - EM - Emulation. */
897#define X86_CR0_EM RT_BIT_32(2)
898#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
899/** Bit 3 - TS - Task Switch. */
900#define X86_CR0_TS RT_BIT_32(3)
901#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
902/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
903#define X86_CR0_ET RT_BIT_32(4)
904#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
905/** Bit 5 - NE - Numeric error (486+). */
906#define X86_CR0_NE RT_BIT_32(5)
907#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
908/** Bit 16 - WP - Write Protect (486+). */
909#define X86_CR0_WP RT_BIT_32(16)
910#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
911/** Bit 18 - AM - Alignment Mask (486+). */
912#define X86_CR0_AM RT_BIT_32(18)
913#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
914/** Bit 29 - NW - Not Write-though (486+). */
915#define X86_CR0_NW RT_BIT_32(29)
916#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
917/** Bit 30 - WP - Cache Disable (486+). */
918#define X86_CR0_CD RT_BIT_32(30)
919#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
920/** Bit 31 - PG - Paging. */
921#define X86_CR0_PG RT_BIT_32(31)
922#define X86_CR0_PAGING RT_BIT_32(31)
923#define X86_CR0_BIT_PG 31 /**< Bit number of X86_CR0_PG */
924/** @} */
925
926
927/** @name CR3
928 * @{ */
929/** Bit 3 - PWT - Page-level Writes Transparent. */
930#define X86_CR3_PWT RT_BIT_32(3)
931/** Bit 4 - PCD - Page-level Cache Disable. */
932#define X86_CR3_PCD RT_BIT_32(4)
933/** Bits 12-31 - - Page directory page number. */
934#define X86_CR3_PAGE_MASK (0xfffff000)
935/** Bits 5-31 - - PAE Page directory page number. */
936#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
937/** Bits 12-51 - - AMD64 Page directory page number. */
938#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
939/** Bits 12-47 - - Intel EPT Page directory page number. */
940#define X86_CR3_EPT_PAGE_MASK UINT64_C(0x0000fffffffff000)
941/** @} */
942
943
944/** @name CR4
945 * @{ */
946/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
947#define X86_CR4_VME RT_BIT_32(0)
948/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
949#define X86_CR4_PVI RT_BIT_32(1)
950/** Bit 2 - TSD - Time Stamp Disable. */
951#define X86_CR4_TSD RT_BIT_32(2)
952/** Bit 3 - DE - Debugging Extensions. */
953#define X86_CR4_DE RT_BIT_32(3)
954/** Bit 4 - PSE - Page Size Extension. */
955#define X86_CR4_PSE RT_BIT_32(4)
956/** Bit 5 - PAE - Physical Address Extension. */
957#define X86_CR4_PAE RT_BIT_32(5)
958/** Bit 6 - MCE - Machine-Check Enable. */
959#define X86_CR4_MCE RT_BIT_32(6)
960/** Bit 7 - PGE - Page Global Enable. */
961#define X86_CR4_PGE RT_BIT_32(7)
962/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
963#define X86_CR4_PCE RT_BIT_32(8)
964/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
965#define X86_CR4_OSFXSR RT_BIT_32(9)
966/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
967#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
968/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
969#define X86_CR4_UMIP RT_BIT_32(11)
970/** Bit 13 - VMXE - VMX mode is enabled. */
971#define X86_CR4_VMXE RT_BIT_32(13)
972/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
973#define X86_CR4_SMXE RT_BIT_32(14)
974/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
975#define X86_CR4_FSGSBASE RT_BIT_32(16)
976/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
977#define X86_CR4_PCIDE RT_BIT_32(17)
978/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
979 * extended states. */
980#define X86_CR4_OSXSAVE RT_BIT_32(18)
981/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
982#define X86_CR4_SMEP RT_BIT_32(20)
983/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
984#define X86_CR4_SMAP RT_BIT_32(21)
985/** Bit 22 - PKE - Protection Key Enable. */
986#define X86_CR4_PKE RT_BIT_32(22)
987/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
988#define X86_CR4_CET RT_BIT_32(23)
989/** @} */
990
991
992/** @name DR6
993 * @{ */
994/** Bit 0 - B0 - Breakpoint 0 condition detected. */
995#define X86_DR6_B0 RT_BIT_32(0)
996/** Bit 1 - B1 - Breakpoint 1 condition detected. */
997#define X86_DR6_B1 RT_BIT_32(1)
998/** Bit 2 - B2 - Breakpoint 2 condition detected. */
999#define X86_DR6_B2 RT_BIT_32(2)
1000/** Bit 3 - B3 - Breakpoint 3 condition detected. */
1001#define X86_DR6_B3 RT_BIT_32(3)
1002/** Mask of all the Bx bits. */
1003#define X86_DR6_B_MASK UINT64_C(0x0000000f)
1004/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
1005#define X86_DR6_BD RT_BIT_32(13)
1006/** Bit 14 - BS - Single step */
1007#define X86_DR6_BS RT_BIT_32(14)
1008/** Bit 15 - BT - Task switch. (TSS T bit.) */
1009#define X86_DR6_BT RT_BIT_32(15)
1010/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
1011#define X86_DR6_RTM RT_BIT_32(16)
1012/** Value of DR6 after powerup/reset. */
1013#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
1014/** Bits which must be 1s in DR6. */
1015#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
1016/** Bits which must be 1s in DR6, when RTM is supported. */
1017#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
1018/** Bits which must be 0s in DR6. */
1019#define X86_DR6_RAZ_MASK RT_BIT_64(12)
1020/** Bits which must be 0s on writes to DR6. */
1021#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
1022/** @} */
1023
1024/** Get the DR6.Bx bit for a the given breakpoint. */
1025#define X86_DR6_B(iBp) RT_BIT_64(iBp)
1026
1027
1028/** @name DR7
1029 * @{ */
1030/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1031#define X86_DR7_L0 RT_BIT_32(0)
1032/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1033#define X86_DR7_G0 RT_BIT_32(1)
1034/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1035#define X86_DR7_L1 RT_BIT_32(2)
1036/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1037#define X86_DR7_G1 RT_BIT_32(3)
1038/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1039#define X86_DR7_L2 RT_BIT_32(4)
1040/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1041#define X86_DR7_G2 RT_BIT_32(5)
1042/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1043#define X86_DR7_L3 RT_BIT_32(6)
1044/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1045#define X86_DR7_G3 RT_BIT_32(7)
1046/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1047#define X86_DR7_LE RT_BIT_32(8)
1048/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1049#define X86_DR7_GE RT_BIT_32(9)
1050
1051/** L0, L1, L2, and L3. */
1052#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1053/** L0, L1, L2, and L3. */
1054#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1055
1056/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1057 * Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1058#define X86_DR7_RTM RT_BIT_32(11)
1059/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1060 * Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1061 * May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1062 * instruction is executed.
1063 * @see http://www.rcollins.org/secrets/DR7.html */
1064#define X86_DR7_ICE_IR RT_BIT_32(12)
1065/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1066 * any DR register is accessed. */
1067#define X86_DR7_GD RT_BIT_32(13)
1068/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1069 * Pentium. */
1070#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1071/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1072#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1073/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
1074#define X86_DR7_RW0_MASK (3 << 16)
1075/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
1076#define X86_DR7_LEN0_MASK (3 << 18)
1077/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
1078#define X86_DR7_RW1_MASK (3 << 20)
1079/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
1080#define X86_DR7_LEN1_MASK (3 << 22)
1081/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
1082#define X86_DR7_RW2_MASK (3 << 24)
1083/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
1084#define X86_DR7_LEN2_MASK (3 << 26)
1085/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
1086#define X86_DR7_RW3_MASK (3 << 28)
1087/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
1088#define X86_DR7_LEN3_MASK (3 << 30)
1089
1090/** Bits which reads as 1s. */
1091#define X86_DR7_RA1_MASK RT_BIT_32(10)
1092/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1093#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1094/** Bits which must be 0s when writing to DR7. */
1095#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1096
1097/** Calcs the L bit of Nth breakpoint.
1098 * @param iBp The breakpoint number [0..3].
1099 */
1100#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1101
1102/** Calcs the G bit of Nth breakpoint.
1103 * @param iBp The breakpoint number [0..3].
1104 */
1105#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1106
1107/** Calcs the L and G bits of Nth breakpoint.
1108 * @param iBp The breakpoint number [0..3].
1109 */
1110#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1111
1112/** @name Read/Write values.
1113 * @{ */
1114/** Break on instruction fetch only. */
1115#define X86_DR7_RW_EO UINT32_C(0)
1116/** Break on write only. */
1117#define X86_DR7_RW_WO UINT32_C(1)
1118/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1119#define X86_DR7_RW_IO UINT32_C(2)
1120/** Break on read or write (but not instruction fetches). */
1121#define X86_DR7_RW_RW UINT32_C(3)
1122/** @} */
1123
1124/** Shifts a X86_DR7_RW_* value to its right place.
1125 * @param iBp The breakpoint number [0..3].
1126 * @param fRw One of the X86_DR7_RW_* value.
1127 */
1128#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1129
1130/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1131 * one of the X86_DR7_RW_XXX constants).
1132 *
1133 * @returns X86_DR7_RW_XXX
1134 * @param uDR7 DR7 value
1135 * @param iBp The breakpoint number [0..3].
1136 */
1137#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1138
1139/** R/W0, R/W1, R/W2, and R/W3. */
1140#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1141
1142#ifndef VBOX_FOR_DTRACE_LIB
1143/** Checks if there are any I/O breakpoint types configured in the RW
1144 * registers. Does NOT check if these are enabled, sorry. */
1145# define X86_DR7_ANY_RW_IO(uDR7) \
1146 ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1147 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1148AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1149AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1150AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1151AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1152AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1153AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1154AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1155AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1156AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1157#endif /* !VBOX_FOR_DTRACE_LIB */
1158
1159/** @name Length values.
1160 * @{ */
1161#define X86_DR7_LEN_BYTE UINT32_C(0)
1162#define X86_DR7_LEN_WORD UINT32_C(1)
1163#define X86_DR7_LEN_QWORD UINT32_C(2) /**< AMD64 long mode only. */
1164#define X86_DR7_LEN_DWORD UINT32_C(3)
1165/** @} */
1166
1167/** Shifts a X86_DR7_LEN_* value to its right place.
1168 * @param iBp The breakpoint number [0..3].
1169 * @param cb One of the X86_DR7_LEN_* values.
1170 */
1171#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1172
1173/** Fetch the breakpoint length bits from the DR7 value.
1174 * @param uDR7 DR7 value
1175 * @param iBp The breakpoint number [0..3].
1176 */
1177#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1178
1179/** Mask used to check if any breakpoints are enabled. */
1180#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1181
1182/** LEN0, LEN1, LEN2, and LEN3. */
1183#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1184/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1185#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1186
1187/** Value of DR7 after powerup/reset. */
1188#define X86_DR7_INIT_VAL 0x400
1189/** @} */
1190
1191
1192/** @name Machine Specific Registers
1193 * @{
1194 */
1195/** Machine check address register (P5). */
1196#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1197/** Machine check type register (P5). */
1198#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1199/** Time Stamp Counter. */
1200#define MSR_IA32_TSC 0x10
1201#define MSR_IA32_CESR UINT32_C(0x00000011)
1202#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1203#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1204
1205#define MSR_IA32_PLATFORM_ID 0x17
1206
1207#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1208# define MSR_IA32_APICBASE 0x1b
1209/** Local APIC enabled. */
1210# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1211/** X2APIC enabled (requires the EN bit to be set). */
1212# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1213/** The processor is the boot strap processor (BSP). */
1214# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1215/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1216 * width. */
1217# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1218/** The default physical base address of the APIC. */
1219# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1220/** Gets the physical base address from the MSR. */
1221# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1222#endif
1223
1224/** Undocumented intel MSR for reporting thread and core counts.
1225 * Judging from the XNU sources, it seems to be introduced in Nehalem. The
1226 * first 16 bits is the thread count. The next 16 bits the core count, except
1227 * on Westmere where it seems it's only the next 4 bits for some reason. */
1228#define MSR_CORE_THREAD_COUNT 0x35
1229
1230/** CPU Feature control. */
1231#define MSR_IA32_FEATURE_CONTROL 0x3A
1232/** Feature control - Lock MSR from writes (R/W0). */
1233#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1234/** Feature control - Enable VMX inside SMX operation (R/WL). */
1235#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1236/** Feature control - Enable VMX outside SMX operation (R/WL). */
1237#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1238/** Feature control - SENTER local functions enable (R/WL). */
1239#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1240#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1241#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1242#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1243#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1244#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1245#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1246/** Feature control - SENTER global enable (R/WL). */
1247#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1248/** Feature control - SGX launch control enable (R/WL). */
1249#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1250/** Feature control - SGX global enable (R/WL). */
1251#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1252/** Feature control - LMCE on (R/WL). */
1253#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1254
1255/** Per-processor TSC adjust MSR. */
1256#define MSR_IA32_TSC_ADJUST 0x3B
1257
1258/** Spectre control register.
1259 * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1260#define MSR_IA32_SPEC_CTRL 0x48
1261/** IBRS - Indirect branch restricted speculation. */
1262#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1263/** STIBP - Single thread indirect branch predictors. */
1264#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1265/** SSBD - Speculative Store Bypass Disable. */
1266#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
1267
1268/** Prediction command register.
1269 * Write only, logical processor scope, no state since write only. */
1270#define MSR_IA32_PRED_CMD 0x49
1271/** IBPB - Indirect branch prediction barrie when written as 1. */
1272#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1273
1274/** BIOS update trigger (microcode update). */
1275#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1276
1277/** BIOS update signature (microcode). */
1278#define MSR_IA32_BIOS_SIGN_ID 0x8B
1279
1280/** SMM monitor control. */
1281#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1282/** SMM control - Valid. */
1283#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1284/** SMM control - VMXOFF unblocks SMI. */
1285#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1286/** SMM control - MSEG base physical address. */
1287#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1288
1289/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1290#define MSR_IA32_SMBASE 0x9E
1291
1292/** General performance counter no. 0. */
1293#define MSR_IA32_PMC0 0xC1
1294/** General performance counter no. 1. */
1295#define MSR_IA32_PMC1 0xC2
1296/** General performance counter no. 2. */
1297#define MSR_IA32_PMC2 0xC3
1298/** General performance counter no. 3. */
1299#define MSR_IA32_PMC3 0xC4
1300/** General performance counter no. 4. */
1301#define MSR_IA32_PMC4 0xC5
1302/** General performance counter no. 5. */
1303#define MSR_IA32_PMC5 0xC6
1304/** General performance counter no. 6. */
1305#define MSR_IA32_PMC6 0xC7
1306/** General performance counter no. 7. */
1307#define MSR_IA32_PMC7 0xC8
1308
1309/** Nehalem power control. */
1310#define MSR_IA32_PLATFORM_INFO 0xCE
1311
1312/** Get FSB clock status (Intel-specific). */
1313#define MSR_IA32_FSB_CLOCK_STS 0xCD
1314
1315/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1316#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1317
1318/** C0 Maximum Frequency Clock Count */
1319#define MSR_IA32_MPERF 0xE7
1320/** C0 Actual Frequency Clock Count */
1321#define MSR_IA32_APERF 0xE8
1322
1323/** MTRR Capabilities. */
1324#define MSR_IA32_MTRR_CAP 0xFE
1325
1326/** Architecture capabilities (bugfixes). */
1327#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1328/** CPU is no subject to meltdown problems. */
1329#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1330/** CPU has better IBRS and you can leave it on all the time. */
1331#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1332/** CPU has return stack buffer (RSB) override. */
1333#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1334/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1335 * This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1336#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1337/** CPU does not suffer from MDS issues. */
1338#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1339
1340/** Flush command register. */
1341#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1342/** Flush the level 1 data cache when this bit is written. */
1343#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1344
1345/** Cache control/info. */
1346#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1347
1348#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1349/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1350 * R0 SS == CS + 8
1351 * R3 CS == CS + 16
1352 * R3 SS == CS + 24
1353 */
1354#define MSR_IA32_SYSENTER_CS 0x174
1355/** SYSENTER_ESP - the R0 ESP. */
1356#define MSR_IA32_SYSENTER_ESP 0x175
1357/** SYSENTER_EIP - the R0 EIP. */
1358#define MSR_IA32_SYSENTER_EIP 0x176
1359#endif
1360
1361/** Machine Check Global Capabilities Register. */
1362#define MSR_IA32_MCG_CAP 0x179
1363/** Machine Check Global Status Register. */
1364#define MSR_IA32_MCG_STATUS 0x17A
1365/** Machine Check Global Control Register. */
1366#define MSR_IA32_MCG_CTRL 0x17B
1367
1368/** Page Attribute Table. */
1369#define MSR_IA32_CR_PAT 0x277
1370/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1371 * "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1372#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1373
1374/** Performance event select MSRs. (Intel only) */
1375#define MSR_IA32_PERFEVTSEL0 0x186
1376#define MSR_IA32_PERFEVTSEL1 0x187
1377#define MSR_IA32_PERFEVTSEL2 0x188
1378#define MSR_IA32_PERFEVTSEL3 0x189
1379
1380/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1381 * The 16th bit whether flex ratio is being used, in which case bits 15:8
1382 * holds a ratio that Apple takes for TSC granularity.
1383 *
1384 * @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1385#define MSR_FLEX_RATIO 0x194
1386/** Performance state value and starting with Intel core more.
1387 * Apple uses the >=core features to determine TSC granularity on older CPUs. */
1388#define MSR_IA32_PERF_STATUS 0x198
1389#define MSR_IA32_PERF_CTL 0x199
1390#define MSR_IA32_THERM_STATUS 0x19c
1391
1392/** Offcore response event select registers. */
1393#define MSR_OFFCORE_RSP_0 0x1a6
1394#define MSR_OFFCORE_RSP_1 0x1a7
1395
1396/** Enable misc. processor features (R/W). */
1397#define MSR_IA32_MISC_ENABLE 0x1A0
1398/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1399#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1400/** Automatic Thermal Control Circuit Enable (R/W). */
1401#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1402/** Performance Monitoring Available (R). */
1403#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1404/** Branch Trace Storage Unavailable (R/O). */
1405#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1406/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1407#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1408/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1409#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1410/** If MONITOR/MWAIT is supported (R/W). */
1411#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1412/** Limit CPUID Maxval to 3 leafs (R/W). */
1413#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1414/** When set to 1, xTPR messages are disabled (R/W). */
1415#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1416/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1417#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1418
1419/** Trace/Profile Resource Control (R/W) */
1420#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1421/** Last branch record. */
1422#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1423/** Branch trace flag (single step on branches). */
1424#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1425/** Performance monitoring pin control (AMD only). */
1426#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1427#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1428#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1429#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1430/** Trace message enable (Intel only). */
1431#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1432/** Branch trace store (Intel only). */
1433#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1434/** Branch trace interrupt (Intel only). */
1435#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1436/** Branch trace off in privileged code (Intel only). */
1437#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1438/** Branch trace off in user code (Intel only). */
1439#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1440/** Freeze LBR on PMI flag (Intel only). */
1441#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1442/** Freeze PERFMON on PMI flag (Intel only). */
1443#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1444/** Freeze while SMM enabled (Intel only). */
1445#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1446/** Advanced debugging of RTM regions (Intel only). */
1447#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1448/** Debug control MSR valid bits (Intel only). */
1449#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \
1450 | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1451 | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1452 | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1453 | MSR_IA32_DEBUGCTL_RTM)
1454
1455/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1456 * @{ */
1457#define MSR_P4_LASTBRANCH_0 0x1db
1458#define MSR_P4_LASTBRANCH_1 0x1dc
1459#define MSR_P4_LASTBRANCH_2 0x1dd
1460#define MSR_P4_LASTBRANCH_3 0x1de
1461
1462/** LBR Top-of-stack MSR (index to most recent record). */
1463#define MSR_P4_LASTBRANCH_TOS 0x1da
1464/** @} */
1465
1466/** @name Last branch registers for Core 2 and related Xeons.
1467 * @{ */
1468#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1469#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1470#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1471#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1472
1473#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1474#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1475#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1476#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1477
1478/** LBR Top-of-stack MSR (index to most recent record). */
1479#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1480/** @} */
1481
1482/** @name Last branch registers.
1483 * @{ */
1484#define MSR_LASTBRANCH_0_FROM_IP 0x680
1485#define MSR_LASTBRANCH_1_FROM_IP 0x681
1486#define MSR_LASTBRANCH_2_FROM_IP 0x682
1487#define MSR_LASTBRANCH_3_FROM_IP 0x683
1488#define MSR_LASTBRANCH_4_FROM_IP 0x684
1489#define MSR_LASTBRANCH_5_FROM_IP 0x685
1490#define MSR_LASTBRANCH_6_FROM_IP 0x686
1491#define MSR_LASTBRANCH_7_FROM_IP 0x687
1492#define MSR_LASTBRANCH_8_FROM_IP 0x688
1493#define MSR_LASTBRANCH_9_FROM_IP 0x689
1494#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1495#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1496#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1497#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1498#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1499#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1500#define MSR_LASTBRANCH_16_FROM_IP 0x690
1501#define MSR_LASTBRANCH_17_FROM_IP 0x691
1502#define MSR_LASTBRANCH_18_FROM_IP 0x692
1503#define MSR_LASTBRANCH_19_FROM_IP 0x693
1504#define MSR_LASTBRANCH_20_FROM_IP 0x694
1505#define MSR_LASTBRANCH_21_FROM_IP 0x695
1506#define MSR_LASTBRANCH_22_FROM_IP 0x696
1507#define MSR_LASTBRANCH_23_FROM_IP 0x697
1508#define MSR_LASTBRANCH_24_FROM_IP 0x698
1509#define MSR_LASTBRANCH_25_FROM_IP 0x699
1510#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1511#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1512#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1513#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1514#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1515#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1516
1517#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1518#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1519#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1520#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1521#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1522#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1523#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1524#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1525#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1526#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1527#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1528#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1529#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1530#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1531#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1532#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1533#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1534#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1535#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1536#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1537#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1538#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1539#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1540#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1541#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1542#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1543#define MSR_LASTBRANCH_26_TO_IP 0x6da
1544#define MSR_LASTBRANCH_27_TO_IP 0x6db
1545#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1546#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1547#define MSR_LASTBRANCH_30_TO_IP 0x6de
1548#define MSR_LASTBRANCH_31_TO_IP 0x6df
1549
1550#define MSR_LASTBRANCH_0_INFO 0xdc0
1551#define MSR_LASTBRANCH_1_INFO 0xdc1
1552#define MSR_LASTBRANCH_2_INFO 0xdc2
1553#define MSR_LASTBRANCH_3_INFO 0xdc3
1554#define MSR_LASTBRANCH_4_INFO 0xdc4
1555#define MSR_LASTBRANCH_5_INFO 0xdc5
1556#define MSR_LASTBRANCH_6_INFO 0xdc6
1557#define MSR_LASTBRANCH_7_INFO 0xdc7
1558#define MSR_LASTBRANCH_8_INFO 0xdc8
1559#define MSR_LASTBRANCH_9_INFO 0xdc9
1560#define MSR_LASTBRANCH_10_INFO 0xdca
1561#define MSR_LASTBRANCH_11_INFO 0xdcb
1562#define MSR_LASTBRANCH_12_INFO 0xdcc
1563#define MSR_LASTBRANCH_13_INFO 0xdcd
1564#define MSR_LASTBRANCH_14_INFO 0xdce
1565#define MSR_LASTBRANCH_15_INFO 0xdcf
1566#define MSR_LASTBRANCH_16_INFO 0xdd0
1567#define MSR_LASTBRANCH_17_INFO 0xdd1
1568#define MSR_LASTBRANCH_18_INFO 0xdd2
1569#define MSR_LASTBRANCH_19_INFO 0xdd3
1570#define MSR_LASTBRANCH_20_INFO 0xdd4
1571#define MSR_LASTBRANCH_21_INFO 0xdd5
1572#define MSR_LASTBRANCH_22_INFO 0xdd6
1573#define MSR_LASTBRANCH_23_INFO 0xdd7
1574#define MSR_LASTBRANCH_24_INFO 0xdd8
1575#define MSR_LASTBRANCH_25_INFO 0xdd9
1576#define MSR_LASTBRANCH_26_INFO 0xdda
1577#define MSR_LASTBRANCH_27_INFO 0xddb
1578#define MSR_LASTBRANCH_28_INFO 0xddc
1579#define MSR_LASTBRANCH_29_INFO 0xddd
1580#define MSR_LASTBRANCH_30_INFO 0xdde
1581#define MSR_LASTBRANCH_31_INFO 0xddf
1582
1583/** LBR branch tracking selection MSR. */
1584#define MSR_LASTBRANCH_SELECT 0x1c8
1585/** LBR Top-of-stack MSR (index to most recent record). */
1586#define MSR_LASTBRANCH_TOS 0x1c9
1587/** @} */
1588
1589/** @name Last event record registers.
1590 * @{ */
1591/** Last event record source IP register. */
1592#define MSR_LER_FROM_IP 0x1dd
1593/** Last event record destination IP register. */
1594#define MSR_LER_TO_IP 0x1de
1595/** @} */
1596
1597/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1598#define MSR_IA32_TSX_CTRL 0x122
1599
1600/** Variable range MTRRs.
1601 * @{ */
1602#define MSR_IA32_MTRR_PHYSBASE0 0x200
1603#define MSR_IA32_MTRR_PHYSMASK0 0x201
1604#define MSR_IA32_MTRR_PHYSBASE1 0x202
1605#define MSR_IA32_MTRR_PHYSMASK1 0x203
1606#define MSR_IA32_MTRR_PHYSBASE2 0x204
1607#define MSR_IA32_MTRR_PHYSMASK2 0x205
1608#define MSR_IA32_MTRR_PHYSBASE3 0x206
1609#define MSR_IA32_MTRR_PHYSMASK3 0x207
1610#define MSR_IA32_MTRR_PHYSBASE4 0x208
1611#define MSR_IA32_MTRR_PHYSMASK4 0x209
1612#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1613#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1614#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1615#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1616#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1617#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1618#define MSR_IA32_MTRR_PHYSBASE8 0x210
1619#define MSR_IA32_MTRR_PHYSMASK8 0x211
1620#define MSR_IA32_MTRR_PHYSBASE9 0x212
1621#define MSR_IA32_MTRR_PHYSMASK9 0x213
1622/** @} */
1623
1624/** Fixed range MTRRs.
1625 * @{ */
1626#define MSR_IA32_MTRR_FIX64K_00000 0x250
1627#define MSR_IA32_MTRR_FIX16K_80000 0x258
1628#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1629#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1630#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1631#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1632#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1633#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1634#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1635#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1636#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1637/** @} */
1638
1639/** MTRR Default Range. */
1640#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1641
1642/** Global performance counter control facilities (Intel only). */
1643#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1644#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1645#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1646
1647/** Precise Event Based sampling (Intel only). */
1648#define MSR_IA32_PEBS_ENABLE 0x3F1
1649
1650#define MSR_IA32_MC0_CTL 0x400
1651#define MSR_IA32_MC0_STATUS 0x401
1652
1653/** Basic VMX information. */
1654#define MSR_IA32_VMX_BASIC 0x480
1655/** Allowed settings for pin-based VM execution controls. */
1656#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1657/** Allowed settings for proc-based VM execution controls. */
1658#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1659/** Allowed settings for the VM-exit controls. */
1660#define MSR_IA32_VMX_EXIT_CTLS 0x483
1661/** Allowed settings for the VM-entry controls. */
1662#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1663/** Misc VMX info. */
1664#define MSR_IA32_VMX_MISC 0x485
1665/** Fixed cleared bits in CR0. */
1666#define MSR_IA32_VMX_CR0_FIXED0 0x486
1667/** Fixed set bits in CR0. */
1668#define MSR_IA32_VMX_CR0_FIXED1 0x487
1669/** Fixed cleared bits in CR4. */
1670#define MSR_IA32_VMX_CR4_FIXED0 0x488
1671/** Fixed set bits in CR4. */
1672#define MSR_IA32_VMX_CR4_FIXED1 0x489
1673/** Information for enumerating fields in the VMCS. */
1674#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1675/** Allowed settings for secondary processor-based VM-execution controls. */
1676#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1677/** EPT capabilities. */
1678#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1679/** Allowed settings of all pin-based VM execution controls. */
1680#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1681/** Allowed settings of all proc-based VM execution controls. */
1682#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1683/** Allowed settings of all VMX exit controls. */
1684#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1685/** Allowed settings of all VMX entry controls. */
1686#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1687/** Allowed settings for the VM-function controls. */
1688#define MSR_IA32_VMX_VMFUNC 0x491
1689/** Tertiary processor-based VM execution controls. */
1690#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
1691
1692/** Intel PT - Enable and control for trace packet generation. */
1693#define MSR_IA32_RTIT_CTL 0x570
1694
1695/** DS Save Area (R/W). */
1696#define MSR_IA32_DS_AREA 0x600
1697/** Running Average Power Limit (RAPL) power units. */
1698#define MSR_RAPL_POWER_UNIT 0x606
1699/** Package C3 Interrupt Response Limit. */
1700#define MSR_PKGC3_IRTL 0x60a
1701/** Package C6/C7S Interrupt Response Limit 1. */
1702#define MSR_PKGC_IRTL1 0x60b
1703/** Package C6/C7S Interrupt Response Limit 2. */
1704#define MSR_PKGC_IRTL2 0x60c
1705/** Package C2 Residency Counter. */
1706#define MSR_PKG_C2_RESIDENCY 0x60d
1707/** PKG RAPL Power Limit Control. */
1708#define MSR_PKG_POWER_LIMIT 0x610
1709/** PKG Energy Status. */
1710#define MSR_PKG_ENERGY_STATUS 0x611
1711/** PKG Perf Status. */
1712#define MSR_PKG_PERF_STATUS 0x613
1713/** PKG RAPL Parameters. */
1714#define MSR_PKG_POWER_INFO 0x614
1715/** DRAM RAPL Power Limit Control. */
1716#define MSR_DRAM_POWER_LIMIT 0x618
1717/** DRAM Energy Status. */
1718#define MSR_DRAM_ENERGY_STATUS 0x619
1719/** DRAM Performance Throttling Status. */
1720#define MSR_DRAM_PERF_STATUS 0x61b
1721/** DRAM RAPL Parameters. */
1722#define MSR_DRAM_POWER_INFO 0x61c
1723/** Package C10 Residency Counter. */
1724#define MSR_PKG_C10_RESIDENCY 0x632
1725/** PP0 Energy Status. */
1726#define MSR_PP0_ENERGY_STATUS 0x639
1727/** PP1 Energy Status. */
1728#define MSR_PP1_ENERGY_STATUS 0x641
1729/** Turbo Activation Ratio. */
1730#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1731/** Core Performance Limit Reasons. */
1732#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1733
1734/** X2APIC MSR range start. */
1735#define MSR_IA32_X2APIC_START 0x800
1736/** X2APIC MSR - APIC ID Register. */
1737#define MSR_IA32_X2APIC_ID 0x802
1738/** X2APIC MSR - APIC Version Register. */
1739#define MSR_IA32_X2APIC_VERSION 0x803
1740/** X2APIC MSR - Task Priority Register. */
1741#define MSR_IA32_X2APIC_TPR 0x808
1742/** X2APIC MSR - Processor Priority register. */
1743#define MSR_IA32_X2APIC_PPR 0x80A
1744/** X2APIC MSR - End Of Interrupt register. */
1745#define MSR_IA32_X2APIC_EOI 0x80B
1746/** X2APIC MSR - Logical Destination Register. */
1747#define MSR_IA32_X2APIC_LDR 0x80D
1748/** X2APIC MSR - Spurious Interrupt Vector Register. */
1749#define MSR_IA32_X2APIC_SVR 0x80F
1750/** X2APIC MSR - In-service Register (bits 31:0). */
1751#define MSR_IA32_X2APIC_ISR0 0x810
1752/** X2APIC MSR - In-service Register (bits 63:32). */
1753#define MSR_IA32_X2APIC_ISR1 0x811
1754/** X2APIC MSR - In-service Register (bits 95:64). */
1755#define MSR_IA32_X2APIC_ISR2 0x812
1756/** X2APIC MSR - In-service Register (bits 127:96). */
1757#define MSR_IA32_X2APIC_ISR3 0x813
1758/** X2APIC MSR - In-service Register (bits 159:128). */
1759#define MSR_IA32_X2APIC_ISR4 0x814
1760/** X2APIC MSR - In-service Register (bits 191:160). */
1761#define MSR_IA32_X2APIC_ISR5 0x815
1762/** X2APIC MSR - In-service Register (bits 223:192). */
1763#define MSR_IA32_X2APIC_ISR6 0x816
1764/** X2APIC MSR - In-service Register (bits 255:224). */
1765#define MSR_IA32_X2APIC_ISR7 0x817
1766/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1767#define MSR_IA32_X2APIC_TMR0 0x818
1768/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1769#define MSR_IA32_X2APIC_TMR1 0x819
1770/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1771#define MSR_IA32_X2APIC_TMR2 0x81A
1772/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1773#define MSR_IA32_X2APIC_TMR3 0x81B
1774/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1775#define MSR_IA32_X2APIC_TMR4 0x81C
1776/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1777#define MSR_IA32_X2APIC_TMR5 0x81D
1778/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1779#define MSR_IA32_X2APIC_TMR6 0x81E
1780/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1781#define MSR_IA32_X2APIC_TMR7 0x81F
1782/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1783#define MSR_IA32_X2APIC_IRR0 0x820
1784/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1785#define MSR_IA32_X2APIC_IRR1 0x821
1786/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1787#define MSR_IA32_X2APIC_IRR2 0x822
1788/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1789#define MSR_IA32_X2APIC_IRR3 0x823
1790/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1791#define MSR_IA32_X2APIC_IRR4 0x824
1792/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1793#define MSR_IA32_X2APIC_IRR5 0x825
1794/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1795#define MSR_IA32_X2APIC_IRR6 0x826
1796/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1797#define MSR_IA32_X2APIC_IRR7 0x827
1798/** X2APIC MSR - Error Status Register. */
1799#define MSR_IA32_X2APIC_ESR 0x828
1800/** X2APIC MSR - LVT CMCI Register. */
1801#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1802/** X2APIC MSR - Interrupt Command Register. */
1803#define MSR_IA32_X2APIC_ICR 0x830
1804/** X2APIC MSR - LVT Timer Register. */
1805#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1806/** X2APIC MSR - LVT Thermal Sensor Register. */
1807#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1808/** X2APIC MSR - LVT Performance Counter Register. */
1809#define MSR_IA32_X2APIC_LVT_PERF 0x834
1810/** X2APIC MSR - LVT LINT0 Register. */
1811#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1812/** X2APIC MSR - LVT LINT1 Register. */
1813#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1814/** X2APIC MSR - LVT Error Register . */
1815#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1816/** X2APIC MSR - Timer Initial Count Register. */
1817#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1818/** X2APIC MSR - Timer Current Count Register. */
1819#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1820/** X2APIC MSR - Timer Divide Configuration Register. */
1821#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1822/** X2APIC MSR - Self IPI. */
1823#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1824/** X2APIC MSR range end. */
1825#define MSR_IA32_X2APIC_END 0x8FF
1826/** X2APIC MSR - LVT start range. */
1827#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1828/** X2APIC MSR - LVT end range (inclusive). */
1829#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1830
1831/** K6 EFER - Extended Feature Enable Register. */
1832#define MSR_K6_EFER UINT32_C(0xc0000080)
1833/** @todo document EFER */
1834/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1835#define MSR_K6_EFER_SCE RT_BIT_32(0)
1836/** Bit 8 - LME - Long mode enabled. (R/W) */
1837#define MSR_K6_EFER_LME RT_BIT_32(8)
1838#define MSR_K6_EFER_BIT_LME 8 /**< Bit number of MSR_K6_EFER_LME */
1839/** Bit 10 - LMA - Long mode active. (R) */
1840#define MSR_K6_EFER_LMA RT_BIT_32(10)
1841#define MSR_K6_EFER_BIT_LMA 10 /**< Bit number of MSR_K6_EFER_LMA */
1842/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1843#define MSR_K6_EFER_NXE RT_BIT_32(11)
1844#define MSR_K6_EFER_BIT_NXE 11 /**< Bit number of MSR_K6_EFER_NXE */
1845/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1846#define MSR_K6_EFER_SVME RT_BIT_32(12)
1847/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1848#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1849/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1850#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1851/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1852#define MSR_K6_EFER_TCE RT_BIT_32(15)
1853/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
1854#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
1855
1856/** K6 STAR - SYSCALL/RET targets. */
1857#define MSR_K6_STAR UINT32_C(0xc0000081)
1858/** Shift value for getting the SYSRET CS and SS value. */
1859#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1860/** Shift value for getting the SYSCALL CS and SS value. */
1861#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1862/** Selector mask for use after shifting. */
1863#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1864/** The mask which give the SYSCALL EIP. */
1865#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1866/** K6 WHCR - Write Handling Control Register. */
1867#define MSR_K6_WHCR UINT32_C(0xc0000082)
1868/** K6 UWCCR - UC/WC Cacheability Control Register. */
1869#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1870/** K6 PSOR - Processor State Observability Register. */
1871#define MSR_K6_PSOR UINT32_C(0xc0000087)
1872/** K6 PFIR - Page Flush/Invalidate Register. */
1873#define MSR_K6_PFIR UINT32_C(0xc0000088)
1874
1875/** Performance counter MSRs. (AMD only) */
1876#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1877#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1878#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1879#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1880#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1881#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1882#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1883#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1884
1885/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1886#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1887/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1888#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1889/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1890#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1891/** K8 FS.base - The 64-bit base FS register. */
1892#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1893/** K8 GS.base - The 64-bit base GS register. */
1894#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1895/** K8 KernelGSbase - Used with SWAPGS. */
1896#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1897/** K8 TSC_AUX - Used with RDTSCP. */
1898#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1899#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1900#define MSR_K8_HWCR UINT32_C(0xc0010015)
1901#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1902#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1903#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1904#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1905#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1906#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1907
1908/** SMM MSRs. */
1909#define MSR_K7_SMBASE UINT32_C(0xc0010111)
1910#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
1911#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
1912
1913/** North bridge config? See BIOS & Kernel dev guides for
1914 * details. */
1915#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1916
1917/** Hypertransport interrupt pending register.
1918 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1919#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1920
1921/** SVM Control. */
1922#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1923/** Disables HDT (Hardware Debug Tool) and certain internal debug
1924 * features. */
1925#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1926/** If set, non-intercepted INIT signals are converted to \#SX
1927 * exceptions. */
1928#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1929/** Disables A20 masking. */
1930#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1931/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1932#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1933/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1934 * clear, EFER.SVME can be written normally. */
1935#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1936
1937#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1938#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1939/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1940 * host state during world switch. */
1941#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1942
1943/** Virtualized speculation control for AMD processors.
1944 *
1945 * Unified interface among different CPU generations.
1946 * The VMM will set any architectural MSRs based on the CPU.
1947 * See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
1948 * (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
1949#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
1950/** Speculative Store Bypass Disable. */
1951# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
1952
1953/** @} */
1954
1955
1956/** @name Page Table / Directory / Directory Pointers / L4.
1957 * @{
1958 */
1959
1960/** Page table/directory entry as an unsigned integer. */
1961typedef uint32_t X86PGUINT;
1962/** Pointer to a page table/directory table entry as an unsigned integer. */
1963typedef X86PGUINT *PX86PGUINT;
1964/** Pointer to an const page table/directory table entry as an unsigned integer. */
1965typedef X86PGUINT const *PCX86PGUINT;
1966
1967/** Number of entries in a 32-bit PT/PD. */
1968#define X86_PG_ENTRIES 1024
1969
1970
1971/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1972typedef uint64_t X86PGPAEUINT;
1973/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1974typedef X86PGPAEUINT *PX86PGPAEUINT;
1975/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1976typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1977
1978/** Number of entries in a PAE PT/PD. */
1979#define X86_PG_PAE_ENTRIES 512
1980/** Number of entries in a PAE PDPT. */
1981#define X86_PG_PAE_PDPE_ENTRIES 4
1982
1983/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1984#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1985/** Number of entries in an AMD64 PDPT.
1986 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1987#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1988
1989/** The size of a default page. */
1990#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1991/** The page shift of a default page. */
1992#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1993/** The default page offset mask. */
1994#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1995/** The default page base mask for virtual addresses. */
1996#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1997/** The default page base mask for virtual addresses - 32bit version. */
1998#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1999
2000/** The size of a 4KB page. */
2001#define X86_PAGE_4K_SIZE _4K
2002/** The page shift of a 4KB page. */
2003#define X86_PAGE_4K_SHIFT 12
2004/** The 4KB page offset mask. */
2005#define X86_PAGE_4K_OFFSET_MASK 0xfff
2006/** The 4KB page base mask for virtual addresses. */
2007#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
2008/** The 4KB page base mask for virtual addresses - 32bit version. */
2009#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
2010
2011/** The size of a 2MB page. */
2012#define X86_PAGE_2M_SIZE _2M
2013/** The page shift of a 2MB page. */
2014#define X86_PAGE_2M_SHIFT 21
2015/** The 2MB page offset mask. */
2016#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
2017/** The 2MB page base mask for virtual addresses. */
2018#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
2019/** The 2MB page base mask for virtual addresses - 32bit version. */
2020#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
2021
2022/** The size of a 4MB page. */
2023#define X86_PAGE_4M_SIZE _4M
2024/** The page shift of a 4MB page. */
2025#define X86_PAGE_4M_SHIFT 22
2026/** The 4MB page offset mask. */
2027#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
2028/** The 4MB page base mask for virtual addresses. */
2029#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
2030/** The 4MB page base mask for virtual addresses - 32bit version. */
2031#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
2032
2033/** The size of a 1GB page. */
2034#define X86_PAGE_1G_SIZE _1G
2035/** The page shift of a 1GB page. */
2036#define X86_PAGE_1G_SHIFT 30
2037/** The 1GB page offset mask. */
2038#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
2039/** The 1GB page base mask for virtual addresses. */
2040#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
2041
2042/**
2043 * Check if the given address is canonical.
2044 */
2045#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
2046
2047/**
2048 * Gets the page base mask given the page shift.
2049 */
2050#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
2051
2052/**
2053 * Gets the page offset mask given the page shift.
2054 */
2055#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
2056
2057
2058/** @name Page Table Entry
2059 * @{
2060 */
2061/** Bit 0 - P - Present bit. */
2062#define X86_PTE_BIT_P 0
2063/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2064#define X86_PTE_BIT_RW 1
2065/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2066#define X86_PTE_BIT_US 2
2067/** Bit 3 - PWT - Page level write thru bit. */
2068#define X86_PTE_BIT_PWT 3
2069/** Bit 4 - PCD - Page level cache disable bit. */
2070#define X86_PTE_BIT_PCD 4
2071/** Bit 5 - A - Access bit. */
2072#define X86_PTE_BIT_A 5
2073/** Bit 6 - D - Dirty bit. */
2074#define X86_PTE_BIT_D 6
2075/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2076#define X86_PTE_BIT_PAT 7
2077/** Bit 8 - G - Global flag. */
2078#define X86_PTE_BIT_G 8
2079/** Bits 63 - NX - PAE/LM - No execution flag. */
2080#define X86_PTE_PAE_BIT_NX 63
2081
2082/** Bit 0 - P - Present bit mask. */
2083#define X86_PTE_P RT_BIT_32(0)
2084/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2085#define X86_PTE_RW RT_BIT_32(1)
2086/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2087#define X86_PTE_US RT_BIT_32(2)
2088/** Bit 3 - PWT - Page level write thru bit mask. */
2089#define X86_PTE_PWT RT_BIT_32(3)
2090/** Bit 4 - PCD - Page level cache disable bit mask. */
2091#define X86_PTE_PCD RT_BIT_32(4)
2092/** Bit 5 - A - Access bit mask. */
2093#define X86_PTE_A RT_BIT_32(5)
2094/** Bit 6 - D - Dirty bit mask. */
2095#define X86_PTE_D RT_BIT_32(6)
2096/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2097#define X86_PTE_PAT RT_BIT_32(7)
2098/** Bit 8 - G - Global bit mask. */
2099#define X86_PTE_G RT_BIT_32(8)
2100
2101/** Bits 9-11 - - Available for use to system software. */
2102#define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2103/** Bits 12-31 - - Physical Page number of the next level. */
2104#define X86_PTE_PG_MASK ( 0xfffff000 )
2105
2106/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2107#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2108/** Bits 63 - NX - PAE/LM - No execution flag. */
2109#define X86_PTE_PAE_NX RT_BIT_64(63)
2110/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2111#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2112/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2113#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2114/** No bits - - LM - MBZ bits when NX is active. */
2115#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2116/** Bits 63 - - LM - MBZ bits when no NX. */
2117#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2118
2119/**
2120 * Page table entry.
2121 */
2122typedef struct X86PTEBITS
2123{
2124 /** Flags whether(=1) or not the page is present. */
2125 uint32_t u1Present : 1;
2126 /** Read(=0) / Write(=1) flag. */
2127 uint32_t u1Write : 1;
2128 /** User(=1) / Supervisor (=0) flag. */
2129 uint32_t u1User : 1;
2130 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2131 uint32_t u1WriteThru : 1;
2132 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2133 uint32_t u1CacheDisable : 1;
2134 /** Accessed flag.
2135 * Indicates that the page have been read or written to. */
2136 uint32_t u1Accessed : 1;
2137 /** Dirty flag.
2138 * Indicates that the page has been written to. */
2139 uint32_t u1Dirty : 1;
2140 /** Reserved / If PAT enabled, bit 2 of the index. */
2141 uint32_t u1PAT : 1;
2142 /** Global flag. (Ignored in all but final level.) */
2143 uint32_t u1Global : 1;
2144 /** Available for use to system software. */
2145 uint32_t u3Available : 3;
2146 /** Physical Page number of the next level. */
2147 uint32_t u20PageNo : 20;
2148} X86PTEBITS;
2149#ifndef VBOX_FOR_DTRACE_LIB
2150AssertCompileSize(X86PTEBITS, 4);
2151#endif
2152/** Pointer to a page table entry. */
2153typedef X86PTEBITS *PX86PTEBITS;
2154/** Pointer to a const page table entry. */
2155typedef const X86PTEBITS *PCX86PTEBITS;
2156
2157/**
2158 * Page table entry.
2159 */
2160typedef union X86PTE
2161{
2162 /** Unsigned integer view */
2163 X86PGUINT u;
2164#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2165 /** Bit field view. */
2166 X86PTEBITS n;
2167#endif
2168 /** 32-bit view. */
2169 uint32_t au32[1];
2170 /** 16-bit view. */
2171 uint16_t au16[2];
2172 /** 8-bit view. */
2173 uint8_t au8[4];
2174} X86PTE;
2175#ifndef VBOX_FOR_DTRACE_LIB
2176AssertCompileSize(X86PTE, 4);
2177#endif
2178/** Pointer to a page table entry. */
2179typedef X86PTE *PX86PTE;
2180/** Pointer to a const page table entry. */
2181typedef const X86PTE *PCX86PTE;
2182
2183
2184/**
2185 * PAE page table entry.
2186 */
2187typedef struct X86PTEPAEBITS
2188{
2189 /** Flags whether(=1) or not the page is present. */
2190 uint32_t u1Present : 1;
2191 /** Read(=0) / Write(=1) flag. */
2192 uint32_t u1Write : 1;
2193 /** User(=1) / Supervisor(=0) flag. */
2194 uint32_t u1User : 1;
2195 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2196 uint32_t u1WriteThru : 1;
2197 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2198 uint32_t u1CacheDisable : 1;
2199 /** Accessed flag.
2200 * Indicates that the page have been read or written to. */
2201 uint32_t u1Accessed : 1;
2202 /** Dirty flag.
2203 * Indicates that the page has been written to. */
2204 uint32_t u1Dirty : 1;
2205 /** Reserved / If PAT enabled, bit 2 of the index. */
2206 uint32_t u1PAT : 1;
2207 /** Global flag. (Ignored in all but final level.) */
2208 uint32_t u1Global : 1;
2209 /** Available for use to system software. */
2210 uint32_t u3Available : 3;
2211 /** Physical Page number of the next level - Low Part. Don't use this. */
2212 uint32_t u20PageNoLow : 20;
2213 /** Physical Page number of the next level - High Part. Don't use this. */
2214 uint32_t u20PageNoHigh : 20;
2215 /** MBZ bits */
2216 uint32_t u11Reserved : 11;
2217 /** No Execute flag. */
2218 uint32_t u1NoExecute : 1;
2219} X86PTEPAEBITS;
2220#ifndef VBOX_FOR_DTRACE_LIB
2221AssertCompileSize(X86PTEPAEBITS, 8);
2222#endif
2223/** Pointer to a page table entry. */
2224typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2225/** Pointer to a page table entry. */
2226typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2227
2228/**
2229 * PAE Page table entry.
2230 */
2231typedef union X86PTEPAE
2232{
2233 /** Unsigned integer view */
2234 X86PGPAEUINT u;
2235#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2236 /** Bit field view. */
2237 X86PTEPAEBITS n;
2238#endif
2239 /** 32-bit view. */
2240 uint32_t au32[2];
2241 /** 16-bit view. */
2242 uint16_t au16[4];
2243 /** 8-bit view. */
2244 uint8_t au8[8];
2245} X86PTEPAE;
2246#ifndef VBOX_FOR_DTRACE_LIB
2247AssertCompileSize(X86PTEPAE, 8);
2248#endif
2249/** Pointer to a PAE page table entry. */
2250typedef X86PTEPAE *PX86PTEPAE;
2251/** Pointer to a const PAE page table entry. */
2252typedef const X86PTEPAE *PCX86PTEPAE;
2253/** @} */
2254
2255/**
2256 * Page table.
2257 */
2258typedef struct X86PT
2259{
2260 /** PTE Array. */
2261 X86PTE a[X86_PG_ENTRIES];
2262} X86PT;
2263#ifndef VBOX_FOR_DTRACE_LIB
2264AssertCompileSize(X86PT, 4096);
2265#endif
2266/** Pointer to a page table. */
2267typedef X86PT *PX86PT;
2268/** Pointer to a const page table. */
2269typedef const X86PT *PCX86PT;
2270
2271/** The page shift to get the PT index. */
2272#define X86_PT_SHIFT 12
2273/** The PT index mask (apply to a shifted page address). */
2274#define X86_PT_MASK 0x3ff
2275
2276
2277/**
2278 * Page directory.
2279 */
2280typedef struct X86PTPAE
2281{
2282 /** PTE Array. */
2283 X86PTEPAE a[X86_PG_PAE_ENTRIES];
2284} X86PTPAE;
2285#ifndef VBOX_FOR_DTRACE_LIB
2286AssertCompileSize(X86PTPAE, 4096);
2287#endif
2288/** Pointer to a page table. */
2289typedef X86PTPAE *PX86PTPAE;
2290/** Pointer to a const page table. */
2291typedef const X86PTPAE *PCX86PTPAE;
2292
2293/** The page shift to get the PA PTE index. */
2294#define X86_PT_PAE_SHIFT 12
2295/** The PAE PT index mask (apply to a shifted page address). */
2296#define X86_PT_PAE_MASK 0x1ff
2297
2298
2299/** @name 4KB Page Directory Entry
2300 * @{
2301 */
2302/** Bit 0 - P - Present bit. */
2303#define X86_PDE_P RT_BIT_32(0)
2304/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2305#define X86_PDE_RW RT_BIT_32(1)
2306/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2307#define X86_PDE_US RT_BIT_32(2)
2308/** Bit 3 - PWT - Page level write thru bit. */
2309#define X86_PDE_PWT RT_BIT_32(3)
2310/** Bit 4 - PCD - Page level cache disable bit. */
2311#define X86_PDE_PCD RT_BIT_32(4)
2312/** Bit 5 - A - Access bit. */
2313#define X86_PDE_A RT_BIT_32(5)
2314/** Bit 7 - PS - Page size attribute.
2315 * Clear mean 4KB pages, set means large pages (2/4MB). */
2316#define X86_PDE_PS RT_BIT_32(7)
2317/** Bits 9-11 - - Available for use to system software. */
2318#define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2319/** Bits 12-31 - - Physical Page number of the next level. */
2320#define X86_PDE_PG_MASK ( 0xfffff000 )
2321
2322/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2323#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2324/** Bits 63 - NX - PAE/LM - No execution flag. */
2325#define X86_PDE_PAE_NX RT_BIT_64(63)
2326/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2327#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2328/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2329#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2330/** Bit 7 - - LM - MBZ bits when NX is active. */
2331#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2332/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2333#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2334
2335/**
2336 * Page directory entry.
2337 */
2338typedef struct X86PDEBITS
2339{
2340 /** Flags whether(=1) or not the page is present. */
2341 uint32_t u1Present : 1;
2342 /** Read(=0) / Write(=1) flag. */
2343 uint32_t u1Write : 1;
2344 /** User(=1) / Supervisor (=0) flag. */
2345 uint32_t u1User : 1;
2346 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2347 uint32_t u1WriteThru : 1;
2348 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2349 uint32_t u1CacheDisable : 1;
2350 /** Accessed flag.
2351 * Indicates that the page has been read or written to. */
2352 uint32_t u1Accessed : 1;
2353 /** Reserved / Ignored (dirty bit). */
2354 uint32_t u1Reserved0 : 1;
2355 /** Size bit if PSE is enabled - in any event it's 0. */
2356 uint32_t u1Size : 1;
2357 /** Reserved / Ignored (global bit). */
2358 uint32_t u1Reserved1 : 1;
2359 /** Available for use to system software. */
2360 uint32_t u3Available : 3;
2361 /** Physical Page number of the next level. */
2362 uint32_t u20PageNo : 20;
2363} X86PDEBITS;
2364#ifndef VBOX_FOR_DTRACE_LIB
2365AssertCompileSize(X86PDEBITS, 4);
2366#endif
2367/** Pointer to a page directory entry. */
2368typedef X86PDEBITS *PX86PDEBITS;
2369/** Pointer to a const page directory entry. */
2370typedef const X86PDEBITS *PCX86PDEBITS;
2371
2372
2373/**
2374 * PAE page directory entry.
2375 */
2376typedef struct X86PDEPAEBITS
2377{
2378 /** Flags whether(=1) or not the page is present. */
2379 uint32_t u1Present : 1;
2380 /** Read(=0) / Write(=1) flag. */
2381 uint32_t u1Write : 1;
2382 /** User(=1) / Supervisor (=0) flag. */
2383 uint32_t u1User : 1;
2384 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2385 uint32_t u1WriteThru : 1;
2386 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2387 uint32_t u1CacheDisable : 1;
2388 /** Accessed flag.
2389 * Indicates that the page has been read or written to. */
2390 uint32_t u1Accessed : 1;
2391 /** Reserved / Ignored (dirty bit). */
2392 uint32_t u1Reserved0 : 1;
2393 /** Size bit if PSE is enabled - in any event it's 0. */
2394 uint32_t u1Size : 1;
2395 /** Reserved / Ignored (global bit). / */
2396 uint32_t u1Reserved1 : 1;
2397 /** Available for use to system software. */
2398 uint32_t u3Available : 3;
2399 /** Physical Page number of the next level - Low Part. Don't use! */
2400 uint32_t u20PageNoLow : 20;
2401 /** Physical Page number of the next level - High Part. Don't use! */
2402 uint32_t u20PageNoHigh : 20;
2403 /** MBZ bits */
2404 uint32_t u11Reserved : 11;
2405 /** No Execute flag. */
2406 uint32_t u1NoExecute : 1;
2407} X86PDEPAEBITS;
2408#ifndef VBOX_FOR_DTRACE_LIB
2409AssertCompileSize(X86PDEPAEBITS, 8);
2410#endif
2411/** Pointer to a page directory entry. */
2412typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2413/** Pointer to a const page directory entry. */
2414typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2415
2416/** @} */
2417
2418
2419/** @name 2/4MB Page Directory Entry
2420 * @{
2421 */
2422/** Bit 0 - P - Present bit. */
2423#define X86_PDE4M_P RT_BIT_32(0)
2424/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2425#define X86_PDE4M_RW RT_BIT_32(1)
2426/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2427#define X86_PDE4M_US RT_BIT_32(2)
2428/** Bit 3 - PWT - Page level write thru bit. */
2429#define X86_PDE4M_PWT RT_BIT_32(3)
2430/** Bit 4 - PCD - Page level cache disable bit. */
2431#define X86_PDE4M_PCD RT_BIT_32(4)
2432/** Bit 5 - A - Access bit. */
2433#define X86_PDE4M_A RT_BIT_32(5)
2434/** Bit 6 - D - Dirty bit. */
2435#define X86_PDE4M_D RT_BIT_32(6)
2436/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2437#define X86_PDE4M_PS RT_BIT_32(7)
2438/** Bit 8 - G - Global flag. */
2439#define X86_PDE4M_G RT_BIT_32(8)
2440/** Bits 9-11 - AVL - Available for use to system software. */
2441#define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2442/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2443#define X86_PDE4M_PAT RT_BIT_32(12)
2444/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2445#define X86_PDE4M_PAT_SHIFT (12 - 7)
2446/** Bits 22-31 - - Physical Page number. */
2447#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2448/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2449#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2450/** The number of bits to the high part of the page number. */
2451#define X86_PDE4M_PG_HIGH_SHIFT 19
2452/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2453#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2454
2455/** Bits 21-51 - - PAE/LM - Physical Page number.
2456 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2457#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2458/** Bits 63 - NX - PAE/LM - No execution flag. */
2459#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2460/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2461#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2462/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2463#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2464/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2465#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2466/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2467#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2468
2469/**
2470 * 4MB page directory entry.
2471 */
2472typedef struct X86PDE4MBITS
2473{
2474 /** Flags whether(=1) or not the page is present. */
2475 uint32_t u1Present : 1;
2476 /** Read(=0) / Write(=1) flag. */
2477 uint32_t u1Write : 1;
2478 /** User(=1) / Supervisor (=0) flag. */
2479 uint32_t u1User : 1;
2480 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2481 uint32_t u1WriteThru : 1;
2482 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2483 uint32_t u1CacheDisable : 1;
2484 /** Accessed flag.
2485 * Indicates that the page have been read or written to. */
2486 uint32_t u1Accessed : 1;
2487 /** Dirty flag.
2488 * Indicates that the page has been written to. */
2489 uint32_t u1Dirty : 1;
2490 /** Page size flag - always 1 for 4MB entries. */
2491 uint32_t u1Size : 1;
2492 /** Global flag. */
2493 uint32_t u1Global : 1;
2494 /** Available for use to system software. */
2495 uint32_t u3Available : 3;
2496 /** Reserved / If PAT enabled, bit 2 of the index. */
2497 uint32_t u1PAT : 1;
2498 /** Bits 32-39 of the page number on AMD64.
2499 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2500 uint32_t u8PageNoHigh : 8;
2501 /** Reserved. */
2502 uint32_t u1Reserved : 1;
2503 /** Physical Page number of the page. */
2504 uint32_t u10PageNo : 10;
2505} X86PDE4MBITS;
2506#ifndef VBOX_FOR_DTRACE_LIB
2507AssertCompileSize(X86PDE4MBITS, 4);
2508#endif
2509/** Pointer to a page table entry. */
2510typedef X86PDE4MBITS *PX86PDE4MBITS;
2511/** Pointer to a const page table entry. */
2512typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2513
2514
2515/**
2516 * 2MB PAE page directory entry.
2517 */
2518typedef struct X86PDE2MPAEBITS
2519{
2520 /** Flags whether(=1) or not the page is present. */
2521 uint32_t u1Present : 1;
2522 /** Read(=0) / Write(=1) flag. */
2523 uint32_t u1Write : 1;
2524 /** User(=1) / Supervisor(=0) flag. */
2525 uint32_t u1User : 1;
2526 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2527 uint32_t u1WriteThru : 1;
2528 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2529 uint32_t u1CacheDisable : 1;
2530 /** Accessed flag.
2531 * Indicates that the page have been read or written to. */
2532 uint32_t u1Accessed : 1;
2533 /** Dirty flag.
2534 * Indicates that the page has been written to. */
2535 uint32_t u1Dirty : 1;
2536 /** Page size flag - always 1 for 2MB entries. */
2537 uint32_t u1Size : 1;
2538 /** Global flag. */
2539 uint32_t u1Global : 1;
2540 /** Available for use to system software. */
2541 uint32_t u3Available : 3;
2542 /** Reserved / If PAT enabled, bit 2 of the index. */
2543 uint32_t u1PAT : 1;
2544 /** Reserved. */
2545 uint32_t u9Reserved : 9;
2546 /** Physical Page number of the next level - Low part. Don't use! */
2547 uint32_t u10PageNoLow : 10;
2548 /** Physical Page number of the next level - High part. Don't use! */
2549 uint32_t u20PageNoHigh : 20;
2550 /** MBZ bits */
2551 uint32_t u11Reserved : 11;
2552 /** No Execute flag. */
2553 uint32_t u1NoExecute : 1;
2554} X86PDE2MPAEBITS;
2555#ifndef VBOX_FOR_DTRACE_LIB
2556AssertCompileSize(X86PDE2MPAEBITS, 8);
2557#endif
2558/** Pointer to a 2MB PAE page table entry. */
2559typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2560/** Pointer to a 2MB PAE page table entry. */
2561typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2562
2563/** @} */
2564
2565/**
2566 * Page directory entry.
2567 */
2568typedef union X86PDE
2569{
2570 /** Unsigned integer view. */
2571 X86PGUINT u;
2572#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2573 /** Normal view. */
2574 X86PDEBITS n;
2575 /** 4MB view (big). */
2576 X86PDE4MBITS b;
2577#endif
2578 /** 8 bit unsigned integer view. */
2579 uint8_t au8[4];
2580 /** 16 bit unsigned integer view. */
2581 uint16_t au16[2];
2582 /** 32 bit unsigned integer view. */
2583 uint32_t au32[1];
2584} X86PDE;
2585#ifndef VBOX_FOR_DTRACE_LIB
2586AssertCompileSize(X86PDE, 4);
2587#endif
2588/** Pointer to a page directory entry. */
2589typedef X86PDE *PX86PDE;
2590/** Pointer to a const page directory entry. */
2591typedef const X86PDE *PCX86PDE;
2592
2593/**
2594 * PAE page directory entry.
2595 */
2596typedef union X86PDEPAE
2597{
2598 /** Unsigned integer view. */
2599 X86PGPAEUINT u;
2600#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2601 /** Normal view. */
2602 X86PDEPAEBITS n;
2603 /** 2MB page view (big). */
2604 X86PDE2MPAEBITS b;
2605#endif
2606 /** 8 bit unsigned integer view. */
2607 uint8_t au8[8];
2608 /** 16 bit unsigned integer view. */
2609 uint16_t au16[4];
2610 /** 32 bit unsigned integer view. */
2611 uint32_t au32[2];
2612} X86PDEPAE;
2613#ifndef VBOX_FOR_DTRACE_LIB
2614AssertCompileSize(X86PDEPAE, 8);
2615#endif
2616/** Pointer to a page directory entry. */
2617typedef X86PDEPAE *PX86PDEPAE;
2618/** Pointer to a const page directory entry. */
2619typedef const X86PDEPAE *PCX86PDEPAE;
2620
2621/**
2622 * Page directory.
2623 */
2624typedef struct X86PD
2625{
2626 /** PDE Array. */
2627 X86PDE a[X86_PG_ENTRIES];
2628} X86PD;
2629#ifndef VBOX_FOR_DTRACE_LIB
2630AssertCompileSize(X86PD, 4096);
2631#endif
2632/** Pointer to a page directory. */
2633typedef X86PD *PX86PD;
2634/** Pointer to a const page directory. */
2635typedef const X86PD *PCX86PD;
2636
2637/** The page shift to get the PD index. */
2638#define X86_PD_SHIFT 22
2639/** The PD index mask (apply to a shifted page address). */
2640#define X86_PD_MASK 0x3ff
2641
2642
2643/**
2644 * PAE page directory.
2645 */
2646typedef struct X86PDPAE
2647{
2648 /** PDE Array. */
2649 X86PDEPAE a[X86_PG_PAE_ENTRIES];
2650} X86PDPAE;
2651#ifndef VBOX_FOR_DTRACE_LIB
2652AssertCompileSize(X86PDPAE, 4096);
2653#endif
2654/** Pointer to a PAE page directory. */
2655typedef X86PDPAE *PX86PDPAE;
2656/** Pointer to a const PAE page directory. */
2657typedef const X86PDPAE *PCX86PDPAE;
2658
2659/** The page shift to get the PAE PD index. */
2660#define X86_PD_PAE_SHIFT 21
2661/** The PAE PD index mask (apply to a shifted page address). */
2662#define X86_PD_PAE_MASK 0x1ff
2663
2664
2665/** @name Page Directory Pointer Table Entry (PAE)
2666 * @{
2667 */
2668/** Bit 0 - P - Present bit. */
2669#define X86_PDPE_P RT_BIT_32(0)
2670/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2671#define X86_PDPE_RW RT_BIT_32(1)
2672/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2673#define X86_PDPE_US RT_BIT_32(2)
2674/** Bit 3 - PWT - Page level write thru bit. */
2675#define X86_PDPE_PWT RT_BIT_32(3)
2676/** Bit 4 - PCD - Page level cache disable bit. */
2677#define X86_PDPE_PCD RT_BIT_32(4)
2678/** Bit 5 - A - Access bit. Long Mode only. */
2679#define X86_PDPE_A RT_BIT_32(5)
2680/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2681#define X86_PDPE_LM_PS RT_BIT_32(7)
2682/** Bits 9-11 - - Available for use to system software. */
2683#define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2684/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2685#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2686/** Bits 30-51 - - PG - Physical address of the 1GB page referenced by this entry. */
2687#define X86_PDPE1G_PG_MASK UINT64_C(0x000fffffc0000000)
2688/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2689#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2690/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2691#define X86_PDPE_LM_NX RT_BIT_64(63)
2692/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2693#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2694/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2695#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2696/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2697#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2698/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2699#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2700
2701
2702/**
2703 * Page directory pointer table entry.
2704 */
2705typedef struct X86PDPEBITS
2706{
2707 /** Flags whether(=1) or not the page is present. */
2708 uint32_t u1Present : 1;
2709 /** Chunk of reserved bits. */
2710 uint32_t u2Reserved : 2;
2711 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2712 uint32_t u1WriteThru : 1;
2713 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2714 uint32_t u1CacheDisable : 1;
2715 /** Chunk of reserved bits. */
2716 uint32_t u4Reserved : 4;
2717 /** Available for use to system software. */
2718 uint32_t u3Available : 3;
2719 /** Physical Page number of the next level - Low Part. Don't use! */
2720 uint32_t u20PageNoLow : 20;
2721 /** Physical Page number of the next level - High Part. Don't use! */
2722 uint32_t u20PageNoHigh : 20;
2723 /** MBZ bits */
2724 uint32_t u12Reserved : 12;
2725} X86PDPEBITS;
2726#ifndef VBOX_FOR_DTRACE_LIB
2727AssertCompileSize(X86PDPEBITS, 8);
2728#endif
2729/** Pointer to a page directory pointer table entry. */
2730typedef X86PDPEBITS *PX86PTPEBITS;
2731/** Pointer to a const page directory pointer table entry. */
2732typedef const X86PDPEBITS *PCX86PTPEBITS;
2733
2734/**
2735 * Page directory pointer table entry. AMD64 version
2736 */
2737typedef struct X86PDPEAMD64BITS
2738{
2739 /** Flags whether(=1) or not the page is present. */
2740 uint32_t u1Present : 1;
2741 /** Read(=0) / Write(=1) flag. */
2742 uint32_t u1Write : 1;
2743 /** User(=1) / Supervisor (=0) flag. */
2744 uint32_t u1User : 1;
2745 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2746 uint32_t u1WriteThru : 1;
2747 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2748 uint32_t u1CacheDisable : 1;
2749 /** Accessed flag.
2750 * Indicates that the page have been read or written to. */
2751 uint32_t u1Accessed : 1;
2752 /** Chunk of reserved bits. */
2753 uint32_t u3Reserved : 3;
2754 /** Available for use to system software. */
2755 uint32_t u3Available : 3;
2756 /** Physical Page number of the next level - Low Part. Don't use! */
2757 uint32_t u20PageNoLow : 20;
2758 /** Physical Page number of the next level - High Part. Don't use! */
2759 uint32_t u20PageNoHigh : 20;
2760 /** MBZ bits */
2761 uint32_t u11Reserved : 11;
2762 /** No Execute flag. */
2763 uint32_t u1NoExecute : 1;
2764} X86PDPEAMD64BITS;
2765#ifndef VBOX_FOR_DTRACE_LIB
2766AssertCompileSize(X86PDPEAMD64BITS, 8);
2767#endif
2768/** Pointer to a page directory pointer table entry. */
2769typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2770/** Pointer to a const page directory pointer table entry. */
2771typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2772
2773/**
2774 * Page directory pointer table entry for 1GB page. (AMD64 only)
2775 */
2776typedef struct X86PDPE1GB
2777{
2778 /** 0: Flags whether(=1) or not the page is present. */
2779 uint32_t u1Present : 1;
2780 /** 1: Read(=0) / Write(=1) flag. */
2781 uint32_t u1Write : 1;
2782 /** 2: User(=1) / Supervisor (=0) flag. */
2783 uint32_t u1User : 1;
2784 /** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2785 uint32_t u1WriteThru : 1;
2786 /** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2787 uint32_t u1CacheDisable : 1;
2788 /** 5: Accessed flag.
2789 * Indicates that the page have been read or written to. */
2790 uint32_t u1Accessed : 1;
2791 /** 6: Dirty flag for 1GB pages. */
2792 uint32_t u1Dirty : 1;
2793 /** 7: Indicates 1GB page if set. */
2794 uint32_t u1Size : 1;
2795 /** 8: Global 1GB page. */
2796 uint32_t u1Global: 1;
2797 /** 9-11: Available for use to system software. */
2798 uint32_t u3Available : 3;
2799 /** 12: PAT bit for 1GB page. */
2800 uint32_t u1PAT : 1;
2801 /** 13-29: MBZ bits. */
2802 uint32_t u17Reserved : 17;
2803 /** 30-31: Physical page number - Low Part. Don't use! */
2804 uint32_t u2PageNoLow : 2;
2805 /** 32-51: Physical Page number of the next level - High Part. Don't use! */
2806 uint32_t u20PageNoHigh : 20;
2807 /** 52-62: MBZ bits */
2808 uint32_t u11Reserved : 11;
2809 /** 63: No Execute flag. */
2810 uint32_t u1NoExecute : 1;
2811} X86PDPE1GB;
2812#ifndef VBOX_FOR_DTRACE_LIB
2813AssertCompileSize(X86PDPE1GB, 8);
2814#endif
2815/** Pointer to a page directory pointer table entry for a 1GB page. */
2816typedef X86PDPE1GB *PX86PDPE1GB;
2817/** Pointer to a const page directory pointer table entry for a 1GB page. */
2818typedef const X86PDPE1GB *PCX86PDPE1GB;
2819
2820/**
2821 * Page directory pointer table entry.
2822 */
2823typedef union X86PDPE
2824{
2825 /** Unsigned integer view. */
2826 X86PGPAEUINT u;
2827#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2828 /** Normal view. */
2829 X86PDPEBITS n;
2830 /** AMD64 view. */
2831 X86PDPEAMD64BITS lm;
2832 /** AMD64 big view. */
2833 X86PDPE1GB b;
2834#endif
2835 /** 8 bit unsigned integer view. */
2836 uint8_t au8[8];
2837 /** 16 bit unsigned integer view. */
2838 uint16_t au16[4];
2839 /** 32 bit unsigned integer view. */
2840 uint32_t au32[2];
2841} X86PDPE;
2842#ifndef VBOX_FOR_DTRACE_LIB
2843AssertCompileSize(X86PDPE, 8);
2844#endif
2845/** Pointer to a page directory pointer table entry. */
2846typedef X86PDPE *PX86PDPE;
2847/** Pointer to a const page directory pointer table entry. */
2848typedef const X86PDPE *PCX86PDPE;
2849
2850
2851/**
2852 * Page directory pointer table.
2853 */
2854typedef struct X86PDPT
2855{
2856 /** PDE Array. */
2857 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2858} X86PDPT;
2859#ifndef VBOX_FOR_DTRACE_LIB
2860AssertCompileSize(X86PDPT, 4096);
2861#endif
2862/** Pointer to a page directory pointer table. */
2863typedef X86PDPT *PX86PDPT;
2864/** Pointer to a const page directory pointer table. */
2865typedef const X86PDPT *PCX86PDPT;
2866
2867/** The page shift to get the PDPT index. */
2868#define X86_PDPT_SHIFT 30
2869/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2870#define X86_PDPT_MASK_PAE 0x3
2871/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2872#define X86_PDPT_MASK_AMD64 0x1ff
2873
2874/** @} */
2875
2876
2877/** @name Page Map Level-4 Entry (Long Mode PAE)
2878 * @{
2879 */
2880/** Bit 0 - P - Present bit. */
2881#define X86_PML4E_P RT_BIT_32(0)
2882/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2883#define X86_PML4E_RW RT_BIT_32(1)
2884/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2885#define X86_PML4E_US RT_BIT_32(2)
2886/** Bit 3 - PWT - Page level write thru bit. */
2887#define X86_PML4E_PWT RT_BIT_32(3)
2888/** Bit 4 - PCD - Page level cache disable bit. */
2889#define X86_PML4E_PCD RT_BIT_32(4)
2890/** Bit 5 - A - Access bit. */
2891#define X86_PML4E_A RT_BIT_32(5)
2892/** Bits 9-11 - - Available for use to system software. */
2893#define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2894/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2895#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2896/** Bits 8, 7 - - MBZ bits when NX is active. */
2897#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2898/** Bits 63, 7 - - MBZ bits when no NX. */
2899#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2900/** Bits 63 - NX - PAE - No execution flag. */
2901#define X86_PML4E_NX RT_BIT_64(63)
2902
2903/**
2904 * Page Map Level-4 Entry
2905 */
2906typedef struct X86PML4EBITS
2907{
2908 /** Flags whether(=1) or not the page is present. */
2909 uint32_t u1Present : 1;
2910 /** Read(=0) / Write(=1) flag. */
2911 uint32_t u1Write : 1;
2912 /** User(=1) / Supervisor (=0) flag. */
2913 uint32_t u1User : 1;
2914 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2915 uint32_t u1WriteThru : 1;
2916 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2917 uint32_t u1CacheDisable : 1;
2918 /** Accessed flag.
2919 * Indicates that the page have been read or written to. */
2920 uint32_t u1Accessed : 1;
2921 /** Chunk of reserved bits. */
2922 uint32_t u3Reserved : 3;
2923 /** Available for use to system software. */
2924 uint32_t u3Available : 3;
2925 /** Physical Page number of the next level - Low Part. Don't use! */
2926 uint32_t u20PageNoLow : 20;
2927 /** Physical Page number of the next level - High Part. Don't use! */
2928 uint32_t u20PageNoHigh : 20;
2929 /** MBZ bits */
2930 uint32_t u11Reserved : 11;
2931 /** No Execute flag. */
2932 uint32_t u1NoExecute : 1;
2933} X86PML4EBITS;
2934#ifndef VBOX_FOR_DTRACE_LIB
2935AssertCompileSize(X86PML4EBITS, 8);
2936#endif
2937/** Pointer to a page map level-4 entry. */
2938typedef X86PML4EBITS *PX86PML4EBITS;
2939/** Pointer to a const page map level-4 entry. */
2940typedef const X86PML4EBITS *PCX86PML4EBITS;
2941
2942/**
2943 * Page Map Level-4 Entry.
2944 */
2945typedef union X86PML4E
2946{
2947 /** Unsigned integer view. */
2948 X86PGPAEUINT u;
2949#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2950 /** Normal view. */
2951 X86PML4EBITS n;
2952#endif
2953 /** 8 bit unsigned integer view. */
2954 uint8_t au8[8];
2955 /** 16 bit unsigned integer view. */
2956 uint16_t au16[4];
2957 /** 32 bit unsigned integer view. */
2958 uint32_t au32[2];
2959} X86PML4E;
2960#ifndef VBOX_FOR_DTRACE_LIB
2961AssertCompileSize(X86PML4E, 8);
2962#endif
2963/** Pointer to a page map level-4 entry. */
2964typedef X86PML4E *PX86PML4E;
2965/** Pointer to a const page map level-4 entry. */
2966typedef const X86PML4E *PCX86PML4E;
2967
2968
2969/**
2970 * Page Map Level-4.
2971 */
2972typedef struct X86PML4
2973{
2974 /** PDE Array. */
2975 X86PML4E a[X86_PG_PAE_ENTRIES];
2976} X86PML4;
2977#ifndef VBOX_FOR_DTRACE_LIB
2978AssertCompileSize(X86PML4, 4096);
2979#endif
2980/** Pointer to a page map level-4. */
2981typedef X86PML4 *PX86PML4;
2982/** Pointer to a const page map level-4. */
2983typedef const X86PML4 *PCX86PML4;
2984
2985/** The page shift to get the PML4 index. */
2986#define X86_PML4_SHIFT 39
2987/** The PML4 index mask (apply to a shifted page address). */
2988#define X86_PML4_MASK 0x1ff
2989
2990/** @} */
2991
2992/** @} */
2993
2994/**
2995 * Intel PCID invalidation types.
2996 */
2997/** Individual address invalidation. */
2998#define X86_INVPCID_TYPE_INDV_ADDR 0
2999/** Single-context invalidation. */
3000#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
3001/** All-context including globals invalidation. */
3002#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
3003/** All-context excluding globals invalidation. */
3004#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
3005/** The maximum valid invalidation type value. */
3006#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
3007
3008
3009/** @name Special FPU integer values.
3010 * @{ */
3011#define X86_FPU_INT64_INDEFINITE INT64_MIN
3012#define X86_FPU_INT32_INDEFINITE INT32_MIN
3013#define X86_FPU_INT16_INDEFINITE INT16_MIN
3014/** @} */
3015
3016/**
3017 * 32-bit protected mode FSTENV image.
3018 */
3019typedef struct X86FSTENV32P
3020{
3021 uint16_t FCW; /**< 0x00 */
3022 uint16_t padding1; /**< 0x02 */
3023 uint16_t FSW; /**< 0x04 */
3024 uint16_t padding2; /**< 0x06 */
3025 uint16_t FTW; /**< 0x08 */
3026 uint16_t padding3; /**< 0x0a */
3027 uint32_t FPUIP; /**< 0x0c */
3028 uint16_t FPUCS; /**< 0x10 */
3029 uint16_t FOP; /**< 0x12 */
3030 uint32_t FPUDP; /**< 0x14 */
3031 uint16_t FPUDS; /**< 0x18 */
3032 uint16_t padding4; /**< 0x1a */
3033} X86FSTENV32P;
3034#ifndef VBOX_FOR_DTRACE_LIB
3035AssertCompileSize(X86FSTENV32P, 0x1c);
3036#endif
3037/** Pointer to a 32-bit protected mode FSTENV image. */
3038typedef X86FSTENV32P *PX86FSTENV32P;
3039/** Pointer to a const 32-bit protected mode FSTENV image. */
3040typedef X86FSTENV32P const *PCX86FSTENV32P;
3041
3042
3043/**
3044 * 80-bit MMX/FPU register type.
3045 */
3046typedef struct X86FPUMMX
3047{
3048 uint8_t reg[10];
3049} X86FPUMMX;
3050#ifndef VBOX_FOR_DTRACE_LIB
3051AssertCompileSize(X86FPUMMX, 10);
3052#endif
3053/** Pointer to a 80-bit MMX/FPU register type. */
3054typedef X86FPUMMX *PX86FPUMMX;
3055/** Pointer to a const 80-bit MMX/FPU register type. */
3056typedef const X86FPUMMX *PCX86FPUMMX;
3057
3058/** FPU (x87) register. */
3059typedef union X86FPUREG
3060{
3061 /** MMX view. */
3062 uint64_t mmx;
3063 /** FPU view - todo. */
3064 X86FPUMMX fpu;
3065 /** Extended precision floating point view. */
3066 RTFLOAT80U r80;
3067 /** Extended precision floating point view v2 */
3068 RTFLOAT80U2 r80Ex;
3069 /** 8-bit view. */
3070 uint8_t au8[16];
3071 /** 16-bit view. */
3072 uint16_t au16[8];
3073 /** 32-bit view. */
3074 uint32_t au32[4];
3075 /** 64-bit view. */
3076 uint64_t au64[2];
3077 /** 128-bit view. (yeah, very helpful) */
3078 uint128_t au128[1];
3079} X86FPUREG;
3080#ifndef VBOX_FOR_DTRACE_LIB
3081AssertCompileSize(X86FPUREG, 16);
3082#endif
3083/** Pointer to a FPU register. */
3084typedef X86FPUREG *PX86FPUREG;
3085/** Pointer to a const FPU register. */
3086typedef X86FPUREG const *PCX86FPUREG;
3087
3088/** FPU (x87) register - v2 with correct size. */
3089#pragma pack(1)
3090typedef union X86FPUREG2
3091{
3092 /** MMX view. */
3093 uint64_t mmx;
3094 /** FPU view - todo. */
3095 X86FPUMMX fpu;
3096 /** Extended precision floating point view. */
3097 RTFLOAT80U r80;
3098 /** 8-bit view. */
3099 uint8_t au8[10];
3100 /** 16-bit view. */
3101 uint16_t au16[5];
3102 /** 32-bit view. */
3103 uint32_t au32[2];
3104 /** 64-bit view. */
3105 uint64_t au64[1];
3106} X86FPUREG2;
3107#pragma pack()
3108#ifndef VBOX_FOR_DTRACE_LIB
3109AssertCompileSize(X86FPUREG2, 10);
3110#endif
3111/** Pointer to a FPU register - v2. */
3112typedef X86FPUREG2 *PX86FPUREG2;
3113/** Pointer to a const FPU register - v2. */
3114typedef X86FPUREG2 const *PCX86FPUREG2;
3115
3116/**
3117 * XMM register union.
3118 */
3119typedef union X86XMMREG
3120{
3121 /** XMM Register view. */
3122 uint128_t xmm;
3123 /** 8-bit view. */
3124 uint8_t au8[16];
3125 /** 16-bit view. */
3126 uint16_t au16[8];
3127 /** 32-bit view. */
3128 uint32_t au32[4];
3129 /** 64-bit view. */
3130 uint64_t au64[2];
3131 /** Signed 8-bit view. */
3132 int8_t ai8[16];
3133 /** Signed 16-bit view. */
3134 int16_t ai16[8];
3135 /** Signed 32-bit view. */
3136 int32_t ai32[4];
3137 /** Signed 64-bit view. */
3138 int64_t ai64[2];
3139 /** 128-bit view. (yeah, very helpful) */
3140 uint128_t au128[1];
3141 /** Single precision floating point view. */
3142 RTFLOAT32U ar32[4];
3143 /** Double precision floating point view. */
3144 RTFLOAT64U ar64[2];
3145#ifndef VBOX_FOR_DTRACE_LIB
3146 /** Confusing nested 128-bit union view (this is what xmm should've been). */
3147 RTUINT128U uXmm;
3148#endif
3149} X86XMMREG;
3150#ifndef VBOX_FOR_DTRACE_LIB
3151AssertCompileSize(X86XMMREG, 16);
3152#endif
3153/** Pointer to an XMM register state. */
3154typedef X86XMMREG *PX86XMMREG;
3155/** Pointer to a const XMM register state. */
3156typedef X86XMMREG const *PCX86XMMREG;
3157
3158/**
3159 * YMM register union.
3160 */
3161typedef union X86YMMREG
3162{
3163 /** YMM register view. */
3164 RTUINT256U ymm;
3165 /** 8-bit view. */
3166 uint8_t au8[32];
3167 /** 16-bit view. */
3168 uint16_t au16[16];
3169 /** 32-bit view. */
3170 uint32_t au32[8];
3171 /** 64-bit view. */
3172 uint64_t au64[4];
3173 /** 128-bit view. (yeah, very helpful) */
3174 uint128_t au128[2];
3175 /** Single precision floating point view. */
3176 RTFLOAT32U ar32[8];
3177 /** Double precision floating point view. */
3178 RTFLOAT64U ar64[4];
3179 /** XMM sub register view. */
3180 X86XMMREG aXmm[2];
3181} X86YMMREG;
3182#ifndef VBOX_FOR_DTRACE_LIB
3183AssertCompileSize(X86YMMREG, 32);
3184#endif
3185/** Pointer to an YMM register state. */
3186typedef X86YMMREG *PX86YMMREG;
3187/** Pointer to a const YMM register state. */
3188typedef X86YMMREG const *PCX86YMMREG;
3189
3190/**
3191 * ZMM register union.
3192 */
3193typedef union X86ZMMREG
3194{
3195 /** 8-bit view. */
3196 uint8_t au8[64];
3197 /** 16-bit view. */
3198 uint16_t au16[32];
3199 /** 32-bit view. */
3200 uint32_t au32[16];
3201 /** 64-bit view. */
3202 uint64_t au64[8];
3203 /** 128-bit view. (yeah, very helpful) */
3204 uint128_t au128[4];
3205 /** Single precision floating point view. */
3206 RTFLOAT32U ar32[16];
3207 /** Double precision floating point view. */
3208 RTFLOAT64U ar64[8];
3209 /** XMM sub register view. */
3210 X86XMMREG aXmm[4];
3211 /** YMM sub register view. */
3212 X86YMMREG aYmm[2];
3213} X86ZMMREG;
3214#ifndef VBOX_FOR_DTRACE_LIB
3215AssertCompileSize(X86ZMMREG, 64);
3216#endif
3217/** Pointer to an ZMM register state. */
3218typedef X86ZMMREG *PX86ZMMREG;
3219/** Pointer to a const ZMM register state. */
3220typedef X86ZMMREG const *PCX86ZMMREG;
3221
3222
3223/**
3224 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3225 */
3226#pragma pack(1)
3227typedef struct X86FPUSTATE
3228{
3229 /** 0x00 - Control word. */
3230 uint16_t FCW;
3231 /** 0x02 - Alignment word */
3232 uint16_t Dummy1;
3233 /** 0x04 - Status word. */
3234 uint16_t FSW;
3235 /** 0x06 - Alignment word */
3236 uint16_t Dummy2;
3237 /** 0x08 - Tag word */
3238 uint16_t FTW;
3239 /** 0x0a - Alignment word */
3240 uint16_t Dummy3;
3241
3242 /** 0x0c - Instruction pointer. */
3243 uint32_t FPUIP;
3244 /** 0x10 - Code selector. */
3245 uint16_t CS;
3246 /** 0x12 - Opcode. */
3247 uint16_t FOP;
3248 /** 0x14 - Data pointer. */
3249 uint32_t FPUOO;
3250 /** 0x18 - FOS. */
3251 uint16_t FPUOS;
3252 /** 0x0a - Alignment word */
3253 uint16_t Dummy4;
3254 /** 0x1c - FPU register. */
3255 X86FPUREG2 regs[8];
3256} X86FPUSTATE;
3257#pragma pack()
3258AssertCompileSize(X86FPUSTATE, 108);
3259/** Pointer to a FPU state. */
3260typedef X86FPUSTATE *PX86FPUSTATE;
3261/** Pointer to a const FPU state. */
3262typedef const X86FPUSTATE *PCX86FPUSTATE;
3263
3264/**
3265 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3266 */
3267#pragma pack(1)
3268typedef struct X86FXSTATE
3269{
3270 /** 0x00 - Control word. */
3271 uint16_t FCW;
3272 /** 0x02 - Status word. */
3273 uint16_t FSW;
3274 /** 0x04 - Tag word. (The upper byte is always zero.) */
3275 uint16_t FTW;
3276 /** 0x06 - Opcode. */
3277 uint16_t FOP;
3278 /** 0x08 - Instruction pointer. */
3279 uint32_t FPUIP;
3280 /** 0x0c - Code selector. */
3281 uint16_t CS;
3282 uint16_t Rsrvd1;
3283 /** 0x10 - Data pointer. */
3284 uint32_t FPUDP;
3285 /** 0x14 - Data segment */
3286 uint16_t DS;
3287 /** 0x16 */
3288 uint16_t Rsrvd2;
3289 /** 0x18 */
3290 uint32_t MXCSR;
3291 /** 0x1c */
3292 uint32_t MXCSR_MASK;
3293 /** 0x20 - FPU registers. */
3294 X86FPUREG aRegs[8];
3295 /** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3296 X86XMMREG aXMM[16];
3297 /* - offset 416 - */
3298 uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3299 /* - offset 464 - Software usable reserved bits. */
3300 uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3301} X86FXSTATE;
3302#pragma pack()
3303/** Pointer to a FPU Extended state. */
3304typedef X86FXSTATE *PX86FXSTATE;
3305/** Pointer to a const FPU Extended state. */
3306typedef const X86FXSTATE *PCX86FXSTATE;
3307
3308/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3309 * magic. Don't forget to update x86.mac if you change this! */
3310#define X86_OFF_FXSTATE_RSVD 0x1d0
3311/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3312 * forget to update x86.mac if you change this!
3313 * @todo r=bird: This has nothing what-so-ever to do here.... */
3314#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3315#ifndef VBOX_FOR_DTRACE_LIB
3316AssertCompileSize(X86FXSTATE, 512);
3317AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3318#endif
3319
3320/** @name FPU status word flags.
3321 * @{ */
3322/** Exception Flag: Invalid operation. */
3323#define X86_FSW_IE RT_BIT_32(0)
3324#define X86_FSW_IE_BIT 0
3325/** Exception Flag: Denormalized operand. */
3326#define X86_FSW_DE RT_BIT_32(1)
3327#define X86_FSW_DE_BIT 1
3328/** Exception Flag: Zero divide. */
3329#define X86_FSW_ZE RT_BIT_32(2)
3330#define X86_FSW_ZE_BIT 2
3331/** Exception Flag: Overflow. */
3332#define X86_FSW_OE RT_BIT_32(3)
3333#define X86_FSW_OE_BIT 3
3334/** Exception Flag: Underflow. */
3335#define X86_FSW_UE RT_BIT_32(4)
3336#define X86_FSW_UE_BIT 4
3337/** Exception Flag: Precision. */
3338#define X86_FSW_PE RT_BIT_32(5)
3339#define X86_FSW_PE_BIT 5
3340/** Stack fault. */
3341#define X86_FSW_SF RT_BIT_32(6)
3342#define X86_FSW_SF_BIT 6
3343/** Error summary status. */
3344#define X86_FSW_ES RT_BIT_32(7)
3345#define X86_FSW_ES_BIT 7
3346/** Mask of exceptions flags, excluding the summary bit. */
3347#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3348/** Mask of exceptions flags, including the summary bit. */
3349#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3350/** Condition code 0. */
3351#define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
3352#define X86_FSW_C0_BIT 8
3353/** Condition code 1. */
3354#define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
3355#define X86_FSW_C1_BIT 9
3356/** Condition code 2. */
3357#define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
3358#define X86_FSW_C2_BIT 10
3359/** Top of the stack mask. */
3360#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3361/** TOP shift value. */
3362#define X86_FSW_TOP_SHIFT 11
3363/** Mask for getting TOP value after shifting it right. */
3364#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3365/** Get the TOP value. */
3366#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3367/** Get the TOP value offsetted by a_iSt (0-7). */
3368#define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
3369/** Condition code 3. */
3370#define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
3371#define X86_FSW_C3_BIT 14
3372/** Mask of exceptions flags, including the summary bit. */
3373#define X86_FSW_C_MASK UINT16_C(0x4700)
3374/** FPU busy. */
3375#define X86_FSW_B RT_BIT_32(15)
3376/** For use with FPREM and FPREM1. */
3377#define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
3378 ( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
3379 | (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
3380 | (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
3381/** For use with FPREM and FPREM1. */
3382#define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
3383 ( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
3384 | ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
3385 | ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
3386/** @} */
3387
3388
3389/** @name FPU control word flags.
3390 * @{ */
3391/** Exception Mask: Invalid operation. */
3392#define X86_FCW_IM RT_BIT_32(0)
3393#define X86_FCW_IM_BIT 0
3394/** Exception Mask: Denormalized operand. */
3395#define X86_FCW_DM RT_BIT_32(1)
3396#define X86_FCW_DM_BIT 1
3397/** Exception Mask: Zero divide. */
3398#define X86_FCW_ZM RT_BIT_32(2)
3399#define X86_FCW_ZM_BIT 2
3400/** Exception Mask: Overflow. */
3401#define X86_FCW_OM RT_BIT_32(3)
3402#define X86_FCW_OM_BIT 3
3403/** Exception Mask: Underflow. */
3404#define X86_FCW_UM RT_BIT_32(4)
3405#define X86_FCW_UM_BIT 4
3406/** Exception Mask: Precision. */
3407#define X86_FCW_PM RT_BIT_32(5)
3408#define X86_FCW_PM_BIT 5
3409/** Mask all exceptions, the value typically loaded (by for instance fninit).
3410 * @remarks This includes reserved bit 6. */
3411#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3412/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3413#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3414/** Precision control mask. */
3415#define X86_FCW_PC_MASK UINT16_C(0x0300)
3416/** Precision control shift. */
3417#define X86_FCW_PC_SHIFT 8
3418/** Precision control: 24-bit. */
3419#define X86_FCW_PC_24 UINT16_C(0x0000)
3420/** Precision control: Reserved. */
3421#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3422/** Precision control: 53-bit. */
3423#define X86_FCW_PC_53 UINT16_C(0x0200)
3424/** Precision control: 64-bit. */
3425#define X86_FCW_PC_64 UINT16_C(0x0300)
3426/** Rounding control mask. */
3427#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3428/** Rounding control shift. */
3429#define X86_FCW_RC_SHIFT 10
3430/** Rounding control: To nearest. */
3431#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3432/** Rounding control: Down. */
3433#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3434/** Rounding control: Up. */
3435#define X86_FCW_RC_UP UINT16_C(0x0800)
3436/** Rounding control: Towards zero. */
3437#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3438/** Infinity control mask - obsolete, 8087 & 287 only. */
3439#define X86_FCW_IC_MASK UINT16_C(0x1000)
3440/** Infinity control: Affine - positive infinity is distictly different from
3441 * negative infinity.
3442 * @note 8087, 287 only */
3443#define X86_FCW_IC_AFFINE UINT16_C(0x1000)
3444/** Infinity control: Projective - positive and negative infinity are the
3445 * same (sign ignored).
3446 * @note 8087, 287 only */
3447#define X86_FCW_IC_PROJECTIVE UINT16_C(0x0000)
3448/** Bits which should be zero, apparently. */
3449#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3450/** @} */
3451
3452/** @name SSE MXCSR
3453 * @{ */
3454/** Exception Flag: Invalid operation. */
3455#define X86_MXCSR_IE RT_BIT_32(0)
3456/** Exception Flag: Denormalized operand. */
3457#define X86_MXCSR_DE RT_BIT_32(1)
3458/** Exception Flag: Zero divide. */
3459#define X86_MXCSR_ZE RT_BIT_32(2)
3460/** Exception Flag: Overflow. */
3461#define X86_MXCSR_OE RT_BIT_32(3)
3462/** Exception Flag: Underflow. */
3463#define X86_MXCSR_UE RT_BIT_32(4)
3464/** Exception Flag: Precision. */
3465#define X86_MXCSR_PE RT_BIT_32(5)
3466/** Exception Flags: mask */
3467#define X86_MXCSR_XCPT_FLAGS UINT32_C(0x003f)
3468
3469/** Denormals are zero. */
3470#define X86_MXCSR_DAZ RT_BIT_32(6)
3471
3472/** Exception Mask: Invalid operation. */
3473#define X86_MXCSR_IM RT_BIT_32(7)
3474/** Exception Mask: Denormalized operand. */
3475#define X86_MXCSR_DM RT_BIT_32(8)
3476/** Exception Mask: Zero divide. */
3477#define X86_MXCSR_ZM RT_BIT_32(9)
3478/** Exception Mask: Overflow. */
3479#define X86_MXCSR_OM RT_BIT_32(10)
3480/** Exception Mask: Underflow. */
3481#define X86_MXCSR_UM RT_BIT_32(11)
3482/** Exception Mask: Precision. */
3483#define X86_MXCSR_PM RT_BIT_32(12)
3484/** Exception Mask: mask. */
3485#define X86_MXCSR_XCPT_MASK UINT32_C(0x1f80)
3486/** Exception Mask: shift. */
3487#define X86_MXCSR_XCPT_MASK_SHIFT 7
3488
3489/** Rounding control mask. */
3490#define X86_MXCSR_RC_MASK UINT32_C(0x6000)
3491/** Rounding control shift. */
3492#define X86_MXCSR_RC_SHIFT 13
3493/** Rounding control: To nearest. */
3494#define X86_MXCSR_RC_NEAREST UINT32_C(0x0000)
3495/** Rounding control: Down. */
3496#define X86_MXCSR_RC_DOWN UINT32_C(0x2000)
3497/** Rounding control: Up. */
3498#define X86_MXCSR_RC_UP UINT32_C(0x4000)
3499/** Rounding control: Towards zero. */
3500#define X86_MXCSR_RC_ZERO UINT32_C(0x6000)
3501
3502/** Flush-to-zero for masked underflow. */
3503#define X86_MXCSR_FZ RT_BIT_32(15)
3504
3505/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3506#define X86_MXCSR_MM RT_BIT_32(17)
3507/** Bits which should be zero, apparently. */
3508#define X86_MXCSR_ZERO_MASK UINT32_C(0xfffd0000)
3509/** @} */
3510
3511/**
3512 * XSAVE header.
3513 */
3514typedef struct X86XSAVEHDR
3515{
3516 /** XTATE_BV - Bitmap indicating whether a component is in the state. */
3517 uint64_t bmXState;
3518 /** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3519 uint64_t bmXComp;
3520 /** Reserved for furture extensions, probably MBZ. */
3521 uint64_t au64Reserved[6];
3522} X86XSAVEHDR;
3523#ifndef VBOX_FOR_DTRACE_LIB
3524AssertCompileSize(X86XSAVEHDR, 64);
3525#endif
3526/** Pointer to an XSAVE header. */
3527typedef X86XSAVEHDR *PX86XSAVEHDR;
3528/** Pointer to a const XSAVE header. */
3529typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3530
3531
3532/**
3533 * The high 128-bit YMM register state (XSAVE_C_YMM).
3534 * (The lower 128-bits being in X86FXSTATE.)
3535 */
3536typedef struct X86XSAVEYMMHI
3537{
3538 /** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3539 X86XMMREG aYmmHi[16];
3540} X86XSAVEYMMHI;
3541#ifndef VBOX_FOR_DTRACE_LIB
3542AssertCompileSize(X86XSAVEYMMHI, 256);
3543#endif
3544/** Pointer to a high 128-bit YMM register state. */
3545typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3546/** Pointer to a const high 128-bit YMM register state. */
3547typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3548
3549/**
3550 * Intel MPX bound registers state (XSAVE_C_BNDREGS).
3551 */
3552typedef struct X86XSAVEBNDREGS
3553{
3554 /** Array of registers (BND0...BND3). */
3555 struct
3556 {
3557 /** Lower bound. */
3558 uint64_t uLowerBound;
3559 /** Upper bound. */
3560 uint64_t uUpperBound;
3561 } aRegs[4];
3562} X86XSAVEBNDREGS;
3563#ifndef VBOX_FOR_DTRACE_LIB
3564AssertCompileSize(X86XSAVEBNDREGS, 64);
3565#endif
3566/** Pointer to a MPX bound register state. */
3567typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3568/** Pointer to a const MPX bound register state. */
3569typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3570
3571/**
3572 * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3573 */
3574typedef struct X86XSAVEBNDCFG
3575{
3576 uint64_t fConfig;
3577 uint64_t fStatus;
3578} X86XSAVEBNDCFG;
3579#ifndef VBOX_FOR_DTRACE_LIB
3580AssertCompileSize(X86XSAVEBNDCFG, 16);
3581#endif
3582/** Pointer to a MPX bound config and status register state. */
3583typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3584/** Pointer to a const MPX bound config and status register state. */
3585typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3586
3587/**
3588 * AVX-512 opmask state (XSAVE_C_OPMASK).
3589 */
3590typedef struct X86XSAVEOPMASK
3591{
3592 /** The K0..K7 values. */
3593 uint64_t aKRegs[8];
3594} X86XSAVEOPMASK;
3595#ifndef VBOX_FOR_DTRACE_LIB
3596AssertCompileSize(X86XSAVEOPMASK, 64);
3597#endif
3598/** Pointer to a AVX-512 opmask state. */
3599typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3600/** Pointer to a const AVX-512 opmask state. */
3601typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3602
3603/**
3604 * ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3605 */
3606typedef struct X86XSAVEZMMHI256
3607{
3608 /** Upper 256-bits of ZMM0-15. */
3609 X86YMMREG aHi256Regs[16];
3610} X86XSAVEZMMHI256;
3611#ifndef VBOX_FOR_DTRACE_LIB
3612AssertCompileSize(X86XSAVEZMMHI256, 512);
3613#endif
3614/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3615typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3616/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3617typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3618
3619/**
3620 * ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3621 */
3622typedef struct X86XSAVEZMM16HI
3623{
3624 /** ZMM16 thru ZMM31. */
3625 X86ZMMREG aRegs[16];
3626} X86XSAVEZMM16HI;
3627#ifndef VBOX_FOR_DTRACE_LIB
3628AssertCompileSize(X86XSAVEZMM16HI, 1024);
3629#endif
3630/** Pointer to a state comprising ZMM16-32. */
3631typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3632/** Pointer to a const state comprising ZMM16-32. */
3633typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3634
3635/**
3636 * AMD Light weight profiling state (XSAVE_C_LWP).
3637 *
3638 * We probably won't play with this as AMD seems to be dropping from their "zen"
3639 * processor micro architecture.
3640 */
3641typedef struct X86XSAVELWP
3642{
3643 /** Details when needed. */
3644 uint64_t auLater[128/8];
3645} X86XSAVELWP;
3646#ifndef VBOX_FOR_DTRACE_LIB
3647AssertCompileSize(X86XSAVELWP, 128);
3648#endif
3649
3650
3651/**
3652 * x86 FPU/SSE/AVX/XXXX state.
3653 *
3654 * Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3655 * changes to this structure.
3656 */
3657typedef struct X86XSAVEAREA
3658{
3659 /** The x87 and SSE region (or legacy region if you like). */
3660 X86FXSTATE x87;
3661 /** The XSAVE header. */
3662 X86XSAVEHDR Hdr;
3663 /** Beyond the header, there isn't really a fixed layout, but we can
3664 generally assume the YMM (AVX) register extensions are present and
3665 follows immediately. */
3666 union
3667 {
3668 /** The high 128-bit AVX registers for easy access by IEM.
3669 * @note This ASSUMES they will always be here... */
3670 X86XSAVEYMMHI YmmHi;
3671
3672 /** This is a typical layout on intel CPUs (good for debuggers). */
3673 struct
3674 {
3675 X86XSAVEYMMHI YmmHi;
3676 X86XSAVEBNDREGS BndRegs;
3677 X86XSAVEBNDCFG BndCfg;
3678 uint8_t abFudgeToMatchDocs[0xB0];
3679 X86XSAVEOPMASK Opmask;
3680 X86XSAVEZMMHI256 ZmmHi256;
3681 X86XSAVEZMM16HI Zmm16Hi;
3682 } Intel;
3683
3684 /** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3685 struct
3686 {
3687 X86XSAVEYMMHI YmmHi;
3688 X86XSAVELWP Lwp;
3689 } AmdBd;
3690
3691 /** To enbling static deployments that have a reasonable chance of working for
3692 * the next 3-6 CPU generations without running short on space, we allocate a
3693 * lot of extra space here, making the structure a round 8KB in size. This
3694 * leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3695 * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3696 uint8_t ab[8192 - 512 - 64];
3697 } u;
3698} X86XSAVEAREA;
3699#ifndef VBOX_FOR_DTRACE_LIB
3700AssertCompileSize(X86XSAVEAREA, 8192);
3701AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
3702AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3703AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3704AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3705AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3706AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3707AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3708AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3709#endif
3710/** Pointer to a XSAVE area. */
3711typedef X86XSAVEAREA *PX86XSAVEAREA;
3712/** Pointer to a const XSAVE area. */
3713typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3714
3715
3716/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3717 * @{ */
3718/** Bit 0 - x87 - Legacy FPU state (bit number) */
3719#define XSAVE_C_X87_BIT 0
3720/** Bit 0 - x87 - Legacy FPU state. */
3721#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3722/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3723#define XSAVE_C_SSE_BIT 1
3724/** Bit 1 - SSE - 128-bit SSE state. */
3725#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3726/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3727#define XSAVE_C_YMM_BIT 2
3728/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3729#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3730/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3731#define XSAVE_C_BNDREGS_BIT 3
3732/** Bit 3 - BNDREGS - MPX bound register state. */
3733#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3734/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3735#define XSAVE_C_BNDCSR_BIT 4
3736/** Bit 4 - BNDCSR - MPX bound config and status state. */
3737#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3738/** Bit 5 - Opmask - opmask state (bit number). */
3739#define XSAVE_C_OPMASK_BIT 5
3740/** Bit 5 - Opmask - opmask state. */
3741#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3742/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3743#define XSAVE_C_ZMM_HI256_BIT 6
3744/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3745#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3746/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3747#define XSAVE_C_ZMM_16HI_BIT 7
3748/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3749#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3750/** Bit 9 - PKRU - Protection-key state (bit number). */
3751#define XSAVE_C_PKRU_BIT 9
3752/** Bit 9 - PKRU - Protection-key state. */
3753#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3754/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3755#define XSAVE_C_LWP_BIT 62
3756/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3757#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3758/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3759#define XSAVE_C_X_BIT 63
3760/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3761#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3762/** @} */
3763
3764
3765
3766/** @name Selector Descriptor
3767 * @{
3768 */
3769
3770#ifndef VBOX_FOR_DTRACE_LIB
3771/**
3772 * Descriptor attributes (as seen by VT-x).
3773 */
3774typedef struct X86DESCATTRBITS
3775{
3776 /** 00 - Segment Type. */
3777 unsigned u4Type : 4;
3778 /** 04 - Descriptor Type. System(=0) or code/data selector */
3779 unsigned u1DescType : 1;
3780 /** 05 - Descriptor Privilege level. */
3781 unsigned u2Dpl : 2;
3782 /** 07 - Flags selector present(=1) or not. */
3783 unsigned u1Present : 1;
3784 /** 08 - Segment limit 16-19. */
3785 unsigned u4LimitHigh : 4;
3786 /** 0c - Available for system software. */
3787 unsigned u1Available : 1;
3788 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3789 unsigned u1Long : 1;
3790 /** 0e - This flags meaning depends on the segment type. Try make sense out
3791 * of the intel manual yourself. */
3792 unsigned u1DefBig : 1;
3793 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
3794 * clear byte. */
3795 unsigned u1Granularity : 1;
3796 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3797 unsigned u1Unusable : 1;
3798} X86DESCATTRBITS;
3799#endif /* !VBOX_FOR_DTRACE_LIB */
3800
3801/** @name X86DESCATTR masks
3802 * @{ */
3803#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3804#define X86DESCATTR_DT UINT32_C(0x00000010)
3805#define X86DESCATTR_DPL UINT32_C(0x00000060)
3806#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
3807#define X86DESCATTR_P UINT32_C(0x00000080)
3808#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3809#define X86DESCATTR_AVL UINT32_C(0x00001000)
3810#define X86DESCATTR_L UINT32_C(0x00002000)
3811#define X86DESCATTR_D UINT32_C(0x00004000)
3812#define X86DESCATTR_G UINT32_C(0x00008000)
3813#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3814/** @} */
3815
3816#pragma pack(1)
3817typedef union X86DESCATTR
3818{
3819 /** Unsigned integer view. */
3820 uint32_t u;
3821#ifndef VBOX_FOR_DTRACE_LIB
3822 /** Normal view. */
3823 X86DESCATTRBITS n;
3824#endif
3825} X86DESCATTR;
3826#pragma pack()
3827/** Pointer to descriptor attributes. */
3828typedef X86DESCATTR *PX86DESCATTR;
3829/** Pointer to const descriptor attributes. */
3830typedef const X86DESCATTR *PCX86DESCATTR;
3831
3832#ifndef VBOX_FOR_DTRACE_LIB
3833
3834/**
3835 * Generic descriptor table entry
3836 */
3837#pragma pack(1)
3838typedef struct X86DESCGENERIC
3839{
3840 /** 00 - Limit - Low word. */
3841 unsigned u16LimitLow : 16;
3842 /** 10 - Base address - low word.
3843 * Don't try set this to 24 because MSC is doing stupid things then. */
3844 unsigned u16BaseLow : 16;
3845 /** 20 - Base address - first 8 bits of high word. */
3846 unsigned u8BaseHigh1 : 8;
3847 /** 28 - Segment Type. */
3848 unsigned u4Type : 4;
3849 /** 2c - Descriptor Type. System(=0) or code/data selector */
3850 unsigned u1DescType : 1;
3851 /** 2d - Descriptor Privilege level. */
3852 unsigned u2Dpl : 2;
3853 /** 2f - Flags selector present(=1) or not. */
3854 unsigned u1Present : 1;
3855 /** 30 - Segment limit 16-19. */
3856 unsigned u4LimitHigh : 4;
3857 /** 34 - Available for system software. */
3858 unsigned u1Available : 1;
3859 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3860 unsigned u1Long : 1;
3861 /** 36 - This flags meaning depends on the segment type. Try make sense out
3862 * of the intel manual yourself. */
3863 unsigned u1DefBig : 1;
3864 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
3865 * clear byte. */
3866 unsigned u1Granularity : 1;
3867 /** 38 - Base address - highest 8 bits. */
3868 unsigned u8BaseHigh2 : 8;
3869} X86DESCGENERIC;
3870#pragma pack()
3871/** Pointer to a generic descriptor entry. */
3872typedef X86DESCGENERIC *PX86DESCGENERIC;
3873/** Pointer to a const generic descriptor entry. */
3874typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3875
3876/** @name Bit offsets of X86DESCGENERIC members.
3877 * @{*/
3878#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
3879#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
3880#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
3881#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
3882#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
3883#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
3884#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
3885#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
3886#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
3887#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
3888#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
3889#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
3890#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
3891/** @} */
3892
3893
3894/** @name LAR mask
3895 * @{ */
3896#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3897#define X86LAR_F_DT UINT16_C( 0x1000)
3898#define X86LAR_F_DPL UINT16_C( 0x6000)
3899#define X86LAR_F_DPL_SHIFT 13 /**< Shift count for the DPL value. */
3900#define X86LAR_F_P UINT16_C( 0x8000)
3901#define X86LAR_F_AVL UINT32_C(0x00100000)
3902#define X86LAR_F_L UINT32_C(0x00200000)
3903#define X86LAR_F_D UINT32_C(0x00400000)
3904#define X86LAR_F_G UINT32_C(0x00800000)
3905/** @} */
3906
3907
3908/**
3909 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3910 */
3911typedef struct X86DESCGATE
3912{
3913 /** 00 - Target code segment offset - Low word.
3914 * Ignored if task-gate. */
3915 unsigned u16OffsetLow : 16;
3916 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3917 * TSS selector if task-gate. */
3918 unsigned u16Sel : 16;
3919 /** 20 - Number of parameters for a call-gate.
3920 * Ignored if interrupt-, trap- or task-gate. */
3921 unsigned u5ParmCount : 5;
3922 /** 25 - Reserved / ignored. */
3923 unsigned u3Reserved : 3;
3924 /** 28 - Segment Type. */
3925 unsigned u4Type : 4;
3926 /** 2c - Descriptor Type (0 = system). */
3927 unsigned u1DescType : 1;
3928 /** 2d - Descriptor Privilege level. */
3929 unsigned u2Dpl : 2;
3930 /** 2f - Flags selector present(=1) or not. */
3931 unsigned u1Present : 1;
3932 /** 30 - Target code segment offset - High word.
3933 * Ignored if task-gate. */
3934 unsigned u16OffsetHigh : 16;
3935} X86DESCGATE;
3936/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3937typedef X86DESCGATE *PX86DESCGATE;
3938/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3939typedef const X86DESCGATE *PCX86DESCGATE;
3940
3941#endif /* VBOX_FOR_DTRACE_LIB */
3942
3943/**
3944 * Descriptor table entry.
3945 */
3946#pragma pack(1)
3947typedef union X86DESC
3948{
3949#ifndef VBOX_FOR_DTRACE_LIB
3950 /** Generic descriptor view. */
3951 X86DESCGENERIC Gen;
3952 /** Gate descriptor view. */
3953 X86DESCGATE Gate;
3954#endif
3955
3956 /** 8 bit unsigned integer view. */
3957 uint8_t au8[8];
3958 /** 16 bit unsigned integer view. */
3959 uint16_t au16[4];
3960 /** 32 bit unsigned integer view. */
3961 uint32_t au32[2];
3962 /** 64 bit unsigned integer view. */
3963 uint64_t au64[1];
3964 /** Unsigned integer view. */
3965 uint64_t u;
3966} X86DESC;
3967#ifndef VBOX_FOR_DTRACE_LIB
3968AssertCompileSize(X86DESC, 8);
3969#endif
3970#pragma pack()
3971/** Pointer to descriptor table entry. */
3972typedef X86DESC *PX86DESC;
3973/** Pointer to const descriptor table entry. */
3974typedef const X86DESC *PCX86DESC;
3975
3976/** @def X86DESC_BASE
3977 * Return the base address of a descriptor.
3978 */
3979#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
3980 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3981 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3982 | ( (a_pDesc)->Gen.u16BaseLow ) )
3983
3984/** @def X86DESC_LIMIT
3985 * Return the limit of a descriptor.
3986 */
3987#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
3988 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3989 | ( (a_pDesc)->Gen.u16LimitLow ) )
3990
3991/** @def X86DESC_LIMIT_G
3992 * Return the limit of a descriptor with the granularity bit taken into account.
3993 * @returns Selector limit (uint32_t).
3994 * @param a_pDesc Pointer to the descriptor.
3995 */
3996#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
3997 ( (a_pDesc)->Gen.u1Granularity \
3998 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
3999 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
4000 )
4001
4002/** @def X86DESC_GET_HID_ATTR
4003 * Get the descriptor attributes for the hidden register.
4004 */
4005#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
4006 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
4007
4008#ifndef VBOX_FOR_DTRACE_LIB
4009
4010/**
4011 * 64 bits generic descriptor table entry
4012 * Note: most of these bits have no meaning in long mode.
4013 */
4014#pragma pack(1)
4015typedef struct X86DESC64GENERIC
4016{
4017 /** Limit - Low word - *IGNORED*. */
4018 uint32_t u16LimitLow : 16;
4019 /** Base address - low word. - *IGNORED*
4020 * Don't try set this to 24 because MSC is doing stupid things then. */
4021 uint32_t u16BaseLow : 16;
4022 /** Base address - first 8 bits of high word. - *IGNORED* */
4023 uint32_t u8BaseHigh1 : 8;
4024 /** Segment Type. */
4025 uint32_t u4Type : 4;
4026 /** Descriptor Type. System(=0) or code/data selector */
4027 uint32_t u1DescType : 1;
4028 /** Descriptor Privilege level. */
4029 uint32_t u2Dpl : 2;
4030 /** Flags selector present(=1) or not. */
4031 uint32_t u1Present : 1;
4032 /** Segment limit 16-19. - *IGNORED* */
4033 uint32_t u4LimitHigh : 4;
4034 /** Available for system software. - *IGNORED* */
4035 uint32_t u1Available : 1;
4036 /** Long mode flag. */
4037 uint32_t u1Long : 1;
4038 /** This flags meaning depends on the segment type. Try make sense out
4039 * of the intel manual yourself. */
4040 uint32_t u1DefBig : 1;
4041 /** Granularity of the limit. If set 4KB granularity is used, if
4042 * clear byte. - *IGNORED* */
4043 uint32_t u1Granularity : 1;
4044 /** Base address - highest 8 bits. - *IGNORED* */
4045 uint32_t u8BaseHigh2 : 8;
4046 /** Base address - bits 63-32. */
4047 uint32_t u32BaseHigh3 : 32;
4048 uint32_t u8Reserved : 8;
4049 uint32_t u5Zeros : 5;
4050 uint32_t u19Reserved : 19;
4051} X86DESC64GENERIC;
4052#pragma pack()
4053/** Pointer to a generic descriptor entry. */
4054typedef X86DESC64GENERIC *PX86DESC64GENERIC;
4055/** Pointer to a const generic descriptor entry. */
4056typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
4057
4058/**
4059 * System descriptor table entry (64 bits)
4060 *
4061 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
4062 */
4063#pragma pack(1)
4064typedef struct X86DESC64SYSTEM
4065{
4066 /** Limit - Low word. */
4067 uint32_t u16LimitLow : 16;
4068 /** Base address - low word.
4069 * Don't try set this to 24 because MSC is doing stupid things then. */
4070 uint32_t u16BaseLow : 16;
4071 /** Base address - first 8 bits of high word. */
4072 uint32_t u8BaseHigh1 : 8;
4073 /** Segment Type. */
4074 uint32_t u4Type : 4;
4075 /** Descriptor Type. System(=0) or code/data selector */
4076 uint32_t u1DescType : 1;
4077 /** Descriptor Privilege level. */
4078 uint32_t u2Dpl : 2;
4079 /** Flags selector present(=1) or not. */
4080 uint32_t u1Present : 1;
4081 /** Segment limit 16-19. */
4082 uint32_t u4LimitHigh : 4;
4083 /** Available for system software. */
4084 uint32_t u1Available : 1;
4085 /** Reserved - 0. */
4086 uint32_t u1Reserved : 1;
4087 /** This flags meaning depends on the segment type. Try make sense out
4088 * of the intel manual yourself. */
4089 uint32_t u1DefBig : 1;
4090 /** Granularity of the limit. If set 4KB granularity is used, if
4091 * clear byte. */
4092 uint32_t u1Granularity : 1;
4093 /** Base address - bits 31-24. */
4094 uint32_t u8BaseHigh2 : 8;
4095 /** Base address - bits 63-32. */
4096 uint32_t u32BaseHigh3 : 32;
4097 uint32_t u8Reserved : 8;
4098 uint32_t u5Zeros : 5;
4099 uint32_t u19Reserved : 19;
4100} X86DESC64SYSTEM;
4101#pragma pack()
4102/** Pointer to a system descriptor entry. */
4103typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
4104/** Pointer to a const system descriptor entry. */
4105typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
4106
4107/**
4108 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
4109 */
4110typedef struct X86DESC64GATE
4111{
4112 /** Target code segment offset - Low word. */
4113 uint32_t u16OffsetLow : 16;
4114 /** Target code segment selector. */
4115 uint32_t u16Sel : 16;
4116 /** Interrupt stack table for interrupt- and trap-gates.
4117 * Ignored by call-gates. */
4118 uint32_t u3IST : 3;
4119 /** Reserved / ignored. */
4120 uint32_t u5Reserved : 5;
4121 /** Segment Type. */
4122 uint32_t u4Type : 4;
4123 /** Descriptor Type (0 = system). */
4124 uint32_t u1DescType : 1;
4125 /** Descriptor Privilege level. */
4126 uint32_t u2Dpl : 2;
4127 /** Flags selector present(=1) or not. */
4128 uint32_t u1Present : 1;
4129 /** Target code segment offset - High word.
4130 * Ignored if task-gate. */
4131 uint32_t u16OffsetHigh : 16;
4132 /** Target code segment offset - Top dword.
4133 * Ignored if task-gate. */
4134 uint32_t u32OffsetTop : 32;
4135 /** Reserved / ignored / must be zero.
4136 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
4137 uint32_t u32Reserved : 32;
4138} X86DESC64GATE;
4139AssertCompileSize(X86DESC64GATE, 16);
4140/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4141typedef X86DESC64GATE *PX86DESC64GATE;
4142/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4143typedef const X86DESC64GATE *PCX86DESC64GATE;
4144
4145#endif /* VBOX_FOR_DTRACE_LIB */
4146
4147/**
4148 * Descriptor table entry.
4149 */
4150#pragma pack(1)
4151typedef union X86DESC64
4152{
4153#ifndef VBOX_FOR_DTRACE_LIB
4154 /** Generic descriptor view. */
4155 X86DESC64GENERIC Gen;
4156 /** System descriptor view. */
4157 X86DESC64SYSTEM System;
4158 /** Gate descriptor view. */
4159 X86DESC64GATE Gate;
4160#endif
4161
4162 /** 8 bit unsigned integer view. */
4163 uint8_t au8[16];
4164 /** 16 bit unsigned integer view. */
4165 uint16_t au16[8];
4166 /** 32 bit unsigned integer view. */
4167 uint32_t au32[4];
4168 /** 64 bit unsigned integer view. */
4169 uint64_t au64[2];
4170} X86DESC64;
4171#ifndef VBOX_FOR_DTRACE_LIB
4172AssertCompileSize(X86DESC64, 16);
4173#endif
4174#pragma pack()
4175/** Pointer to descriptor table entry. */
4176typedef X86DESC64 *PX86DESC64;
4177/** Pointer to const descriptor table entry. */
4178typedef const X86DESC64 *PCX86DESC64;
4179
4180/** @def X86DESC64_BASE
4181 * Return the base of a 64-bit descriptor.
4182 */
4183#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
4184 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
4185 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4186 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4187 | ( (a_pDesc)->Gen.u16BaseLow ) )
4188
4189
4190
4191/** @name Host system descriptor table entry - Use with care!
4192 * @{ */
4193/** Host system descriptor table entry. */
4194#if HC_ARCH_BITS == 64
4195typedef X86DESC64 X86DESCHC;
4196#else
4197typedef X86DESC X86DESCHC;
4198#endif
4199/** Pointer to a host system descriptor table entry. */
4200#if HC_ARCH_BITS == 64
4201typedef PX86DESC64 PX86DESCHC;
4202#else
4203typedef PX86DESC PX86DESCHC;
4204#endif
4205/** Pointer to a const host system descriptor table entry. */
4206#if HC_ARCH_BITS == 64
4207typedef PCX86DESC64 PCX86DESCHC;
4208#else
4209typedef PCX86DESC PCX86DESCHC;
4210#endif
4211/** @} */
4212
4213
4214/** @name Selector Descriptor Types.
4215 * @{
4216 */
4217
4218/** @name Non-System Selector Types.
4219 * @{ */
4220/** Code(=set)/Data(=clear) bit. */
4221#define X86_SEL_TYPE_CODE 8
4222/** Memory(=set)/System(=clear) bit. */
4223#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4224/** Accessed bit. */
4225#define X86_SEL_TYPE_ACCESSED 1
4226/** Expand down bit (for data selectors only). */
4227#define X86_SEL_TYPE_DOWN 4
4228/** Conforming bit (for code selectors only). */
4229#define X86_SEL_TYPE_CONF 4
4230/** Write bit (for data selectors only). */
4231#define X86_SEL_TYPE_WRITE 2
4232/** Read bit (for code selectors only). */
4233#define X86_SEL_TYPE_READ 2
4234/** The bit number of the code segment read bit (relative to u4Type). */
4235#define X86_SEL_TYPE_READ_BIT 1
4236
4237/** Read only selector type. */
4238#define X86_SEL_TYPE_RO 0
4239/** Accessed read only selector type. */
4240#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
4241/** Read write selector type. */
4242#define X86_SEL_TYPE_RW 2
4243/** Accessed read write selector type. */
4244#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
4245/** Expand down read only selector type. */
4246#define X86_SEL_TYPE_RO_DOWN 4
4247/** Accessed expand down read only selector type. */
4248#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
4249/** Expand down read write selector type. */
4250#define X86_SEL_TYPE_RW_DOWN 6
4251/** Accessed expand down read write selector type. */
4252#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
4253/** Execute only selector type. */
4254#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
4255/** Accessed execute only selector type. */
4256#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4257/** Execute and read selector type. */
4258#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
4259/** Accessed execute and read selector type. */
4260#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4261/** Conforming execute only selector type. */
4262#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
4263/** Accessed Conforming execute only selector type. */
4264#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4265/** Conforming execute and write selector type. */
4266#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
4267/** Accessed Conforming execute and write selector type. */
4268#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4269/** @} */
4270
4271
4272/** @name System Selector Types.
4273 * @{ */
4274/** The TSS busy bit mask. */
4275#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4276
4277/** Undefined system selector type. */
4278#define X86_SEL_TYPE_SYS_UNDEFINED 0
4279/** 286 TSS selector. */
4280#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4281/** LDT selector. */
4282#define X86_SEL_TYPE_SYS_LDT 2
4283/** 286 TSS selector - Busy. */
4284#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4285/** 286 Callgate selector. */
4286#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4287/** Taskgate selector. */
4288#define X86_SEL_TYPE_SYS_TASK_GATE 5
4289/** 286 Interrupt gate selector. */
4290#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4291/** 286 Trapgate selector. */
4292#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4293/** Undefined system selector. */
4294#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4295/** 386 TSS selector. */
4296#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4297/** Undefined system selector. */
4298#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4299/** 386 TSS selector - Busy. */
4300#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4301/** 386 Callgate selector. */
4302#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4303/** Undefined system selector. */
4304#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4305/** 386 Interruptgate selector. */
4306#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4307/** 386 Trapgate selector. */
4308#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4309/** @} */
4310
4311/** @name AMD64 System Selector Types.
4312 * @{ */
4313/** LDT selector. */
4314#define AMD64_SEL_TYPE_SYS_LDT 2
4315/** TSS selector - Busy. */
4316#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4317/** TSS selector - Busy. */
4318#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4319/** Callgate selector. */
4320#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4321/** Interruptgate selector. */
4322#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4323/** Trapgate selector. */
4324#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4325/** @} */
4326
4327/** @} */
4328
4329
4330/** @name Descriptor Table Entry Flag Masks.
4331 * These are for the 2nd 32-bit word of a descriptor.
4332 * @{ */
4333/** Bits 8-11 - TYPE - Descriptor type mask. */
4334#define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
4335/** Bit 12 - S - System (=0) or Code/Data (=1). */
4336#define X86_DESC_S RT_BIT_32(12)
4337/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4338#define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
4339/** Bit 15 - P - Present. */
4340#define X86_DESC_P RT_BIT_32(15)
4341/** Bit 20 - AVL - Available for system software. */
4342#define X86_DESC_AVL RT_BIT_32(20)
4343/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4344#define X86_DESC_DB RT_BIT_32(22)
4345/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4346 * used, if clear byte. */
4347#define X86_DESC_G RT_BIT_32(23)
4348/** @} */
4349
4350/** @} */
4351
4352
4353/** @name Task Segments.
4354 * @{
4355 */
4356
4357/**
4358 * The minimum TSS descriptor limit for 286 tasks.
4359 */
4360#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4361
4362/**
4363 * The minimum TSS descriptor segment limit for 386 tasks.
4364 */
4365#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4366
4367/**
4368 * 16-bit Task Segment (TSS).
4369 */
4370#pragma pack(1)
4371typedef struct X86TSS16
4372{
4373 /** Back link to previous task. (static) */
4374 RTSEL selPrev;
4375 /** Ring-0 stack pointer. (static) */
4376 uint16_t sp0;
4377 /** Ring-0 stack segment. (static) */
4378 RTSEL ss0;
4379 /** Ring-1 stack pointer. (static) */
4380 uint16_t sp1;
4381 /** Ring-1 stack segment. (static) */
4382 RTSEL ss1;
4383 /** Ring-2 stack pointer. (static) */
4384 uint16_t sp2;
4385 /** Ring-2 stack segment. (static) */
4386 RTSEL ss2;
4387 /** IP before task switch. */
4388 uint16_t ip;
4389 /** FLAGS before task switch. */
4390 uint16_t flags;
4391 /** AX before task switch. */
4392 uint16_t ax;
4393 /** CX before task switch. */
4394 uint16_t cx;
4395 /** DX before task switch. */
4396 uint16_t dx;
4397 /** BX before task switch. */
4398 uint16_t bx;
4399 /** SP before task switch. */
4400 uint16_t sp;
4401 /** BP before task switch. */
4402 uint16_t bp;
4403 /** SI before task switch. */
4404 uint16_t si;
4405 /** DI before task switch. */
4406 uint16_t di;
4407 /** ES before task switch. */
4408 RTSEL es;
4409 /** CS before task switch. */
4410 RTSEL cs;
4411 /** SS before task switch. */
4412 RTSEL ss;
4413 /** DS before task switch. */
4414 RTSEL ds;
4415 /** LDTR before task switch. */
4416 RTSEL selLdt;
4417} X86TSS16;
4418#ifndef VBOX_FOR_DTRACE_LIB
4419AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4420#endif
4421#pragma pack()
4422/** Pointer to a 16-bit task segment. */
4423typedef X86TSS16 *PX86TSS16;
4424/** Pointer to a const 16-bit task segment. */
4425typedef const X86TSS16 *PCX86TSS16;
4426
4427
4428/**
4429 * 32-bit Task Segment (TSS).
4430 */
4431#pragma pack(1)
4432typedef struct X86TSS32
4433{
4434 /** Back link to previous task. (static) */
4435 RTSEL selPrev;
4436 uint16_t padding1;
4437 /** Ring-0 stack pointer. (static) */
4438 uint32_t esp0;
4439 /** Ring-0 stack segment. (static) */
4440 RTSEL ss0;
4441 uint16_t padding_ss0;
4442 /** Ring-1 stack pointer. (static) */
4443 uint32_t esp1;
4444 /** Ring-1 stack segment. (static) */
4445 RTSEL ss1;
4446 uint16_t padding_ss1;
4447 /** Ring-2 stack pointer. (static) */
4448 uint32_t esp2;
4449 /** Ring-2 stack segment. (static) */
4450 RTSEL ss2;
4451 uint16_t padding_ss2;
4452 /** Page directory for the task. (static) */
4453 uint32_t cr3;
4454 /** EIP before task switch. */
4455 uint32_t eip;
4456 /** EFLAGS before task switch. */
4457 uint32_t eflags;
4458 /** EAX before task switch. */
4459 uint32_t eax;
4460 /** ECX before task switch. */
4461 uint32_t ecx;
4462 /** EDX before task switch. */
4463 uint32_t edx;
4464 /** EBX before task switch. */
4465 uint32_t ebx;
4466 /** ESP before task switch. */
4467 uint32_t esp;
4468 /** EBP before task switch. */
4469 uint32_t ebp;
4470 /** ESI before task switch. */
4471 uint32_t esi;
4472 /** EDI before task switch. */
4473 uint32_t edi;
4474 /** ES before task switch. */
4475 RTSEL es;
4476 uint16_t padding_es;
4477 /** CS before task switch. */
4478 RTSEL cs;
4479 uint16_t padding_cs;
4480 /** SS before task switch. */
4481 RTSEL ss;
4482 uint16_t padding_ss;
4483 /** DS before task switch. */
4484 RTSEL ds;
4485 uint16_t padding_ds;
4486 /** FS before task switch. */
4487 RTSEL fs;
4488 uint16_t padding_fs;
4489 /** GS before task switch. */
4490 RTSEL gs;
4491 uint16_t padding_gs;
4492 /** LDTR before task switch. */
4493 RTSEL selLdt;
4494 uint16_t padding_ldt;
4495 /** Debug trap flag */
4496 uint16_t fDebugTrap;
4497 /** Offset relative to the TSS of the start of the I/O Bitmap
4498 * and the end of the interrupt redirection bitmap. */
4499 uint16_t offIoBitmap;
4500} X86TSS32;
4501#pragma pack()
4502/** Pointer to task segment. */
4503typedef X86TSS32 *PX86TSS32;
4504/** Pointer to const task segment. */
4505typedef const X86TSS32 *PCX86TSS32;
4506#ifndef VBOX_FOR_DTRACE_LIB
4507AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4508AssertCompileMemberOffset(X86TSS32, cr3, 28);
4509AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4510#endif
4511
4512/**
4513 * 64-bit Task segment.
4514 */
4515#pragma pack(1)
4516typedef struct X86TSS64
4517{
4518 /** Reserved. */
4519 uint32_t u32Reserved;
4520 /** Ring-0 stack pointer. (static) */
4521 uint64_t rsp0;
4522 /** Ring-1 stack pointer. (static) */
4523 uint64_t rsp1;
4524 /** Ring-2 stack pointer. (static) */
4525 uint64_t rsp2;
4526 /** Reserved. */
4527 uint32_t u32Reserved2[2];
4528 /* IST */
4529 uint64_t ist1;
4530 uint64_t ist2;
4531 uint64_t ist3;
4532 uint64_t ist4;
4533 uint64_t ist5;
4534 uint64_t ist6;
4535 uint64_t ist7;
4536 /* Reserved. */
4537 uint16_t u16Reserved[5];
4538 /** Offset relative to the TSS of the start of the I/O Bitmap
4539 * and the end of the interrupt redirection bitmap. */
4540 uint16_t offIoBitmap;
4541} X86TSS64;
4542#pragma pack()
4543/** Pointer to a 64-bit task segment. */
4544typedef X86TSS64 *PX86TSS64;
4545/** Pointer to a const 64-bit task segment. */
4546typedef const X86TSS64 *PCX86TSS64;
4547#ifndef VBOX_FOR_DTRACE_LIB
4548AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4549#endif
4550
4551/** @} */
4552
4553
4554/** @name Selectors.
4555 * @{
4556 */
4557
4558/**
4559 * The shift used to convert a selector from and to index an index (C).
4560 */
4561#define X86_SEL_SHIFT 3
4562
4563/**
4564 * The mask used to mask off the table indicator and RPL of an selector.
4565 */
4566#define X86_SEL_MASK 0xfff8U
4567
4568/**
4569 * The mask used to mask off the RPL of an selector.
4570 * This is suitable for checking for NULL selectors.
4571 */
4572#define X86_SEL_MASK_OFF_RPL 0xfffcU
4573
4574/**
4575 * The bit indicating that a selector is in the LDT and not in the GDT.
4576 */
4577#define X86_SEL_LDT 0x0004U
4578
4579/**
4580 * The bit mask for getting the RPL of a selector.
4581 */
4582#define X86_SEL_RPL 0x0003U
4583
4584/**
4585 * The mask covering both RPL and LDT.
4586 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4587 * checks.
4588 */
4589#define X86_SEL_RPL_LDT 0x0007U
4590
4591/** @} */
4592
4593
4594/**
4595 * x86 Exceptions/Faults/Traps.
4596 */
4597typedef enum X86XCPT
4598{
4599 /** \#DE - Divide error. */
4600 X86_XCPT_DE = 0x00,
4601 /** \#DB - Debug event (single step, DRx, ..) */
4602 X86_XCPT_DB = 0x01,
4603 /** NMI - Non-Maskable Interrupt */
4604 X86_XCPT_NMI = 0x02,
4605 /** \#BP - Breakpoint (INT3). */
4606 X86_XCPT_BP = 0x03,
4607 /** \#OF - Overflow (INTO). */
4608 X86_XCPT_OF = 0x04,
4609 /** \#BR - Bound range exceeded (BOUND). */
4610 X86_XCPT_BR = 0x05,
4611 /** \#UD - Undefined opcode. */
4612 X86_XCPT_UD = 0x06,
4613 /** \#NM - Device not available (math coprocessor device). */
4614 X86_XCPT_NM = 0x07,
4615 /** \#DF - Double fault. */
4616 X86_XCPT_DF = 0x08,
4617 /** ??? - Coprocessor segment overrun (obsolete). */
4618 X86_XCPT_CO_SEG_OVERRUN = 0x09,
4619 /** \#TS - Taskswitch (TSS). */
4620 X86_XCPT_TS = 0x0a,
4621 /** \#NP - Segment no present. */
4622 X86_XCPT_NP = 0x0b,
4623 /** \#SS - Stack segment fault. */
4624 X86_XCPT_SS = 0x0c,
4625 /** \#GP - General protection fault. */
4626 X86_XCPT_GP = 0x0d,
4627 /** \#PF - Page fault. */
4628 X86_XCPT_PF = 0x0e,
4629 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4630 /** \#MF - Math fault (FPU). */
4631 X86_XCPT_MF = 0x10,
4632 /** \#AC - Alignment check. */
4633 X86_XCPT_AC = 0x11,
4634 /** \#MC - Machine check. */
4635 X86_XCPT_MC = 0x12,
4636 /** \#XF - SIMD Floating-Point Exception. */
4637 X86_XCPT_XF = 0x13,
4638 /** \#VE - Virtualization Exception (Intel only). */
4639 X86_XCPT_VE = 0x14,
4640 /** \#CP - Control Protection Exception (Intel only). */
4641 X86_XCPT_CP = 0x15,
4642 /** \#VC - VMM Communication Exception (AMD only). */
4643 X86_XCPT_VC = 0x1d,
4644 /** \#SX - Security Exception (AMD only). */
4645 X86_XCPT_SX = 0x1e
4646} X86XCPT;
4647/** Pointer to a x86 exception code. */
4648typedef X86XCPT *PX86XCPT;
4649/** Pointer to a const x86 exception code. */
4650typedef const X86XCPT *PCX86XCPT;
4651/** The last valid (currently reserved) exception value. */
4652#define X86_XCPT_LAST 0x1f
4653
4654
4655/** @name Trap Error Codes
4656 * @{
4657 */
4658/** External indicator. */
4659#define X86_TRAP_ERR_EXTERNAL 1
4660/** IDT indicator. */
4661#define X86_TRAP_ERR_IDT 2
4662/** Descriptor table indicator - If set LDT, if clear GDT. */
4663#define X86_TRAP_ERR_TI 4
4664/** Mask for getting the selector. */
4665#define X86_TRAP_ERR_SEL_MASK 0xfff8
4666/** Shift for getting the selector table index (C type index). */
4667#define X86_TRAP_ERR_SEL_SHIFT 3
4668/** @} */
4669
4670
4671/** @name \#PF Trap Error Codes
4672 * @{
4673 */
4674/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4675#define X86_TRAP_PF_P RT_BIT_32(0)
4676/** Bit 1 - R/W - Read (clear) or write (set) access. */
4677#define X86_TRAP_PF_RW RT_BIT_32(1)
4678/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4679#define X86_TRAP_PF_US RT_BIT_32(2)
4680/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4681#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4682/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4683#define X86_TRAP_PF_ID RT_BIT_32(4)
4684/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4685#define X86_TRAP_PF_PK RT_BIT_32(5)
4686/** @} */
4687
4688#pragma pack(1)
4689/**
4690 * 16-bit IDTR.
4691 */
4692typedef struct X86IDTR16
4693{
4694 /** Offset. */
4695 uint16_t offSel;
4696 /** Selector. */
4697 uint16_t uSel;
4698} X86IDTR16, *PX86IDTR16;
4699#pragma pack()
4700
4701#pragma pack(1)
4702/**
4703 * 32-bit IDTR/GDTR.
4704 */
4705typedef struct X86XDTR32
4706{
4707 /** Size of the descriptor table. */
4708 uint16_t cb;
4709 /** Address of the descriptor table. */
4710#ifndef VBOX_FOR_DTRACE_LIB
4711 uint32_t uAddr;
4712#else
4713 uint16_t au16Addr[2];
4714#endif
4715} X86XDTR32, *PX86XDTR32;
4716#pragma pack()
4717
4718#pragma pack(1)
4719/**
4720 * 64-bit IDTR/GDTR.
4721 */
4722typedef struct X86XDTR64
4723{
4724 /** Size of the descriptor table. */
4725 uint16_t cb;
4726 /** Address of the descriptor table. */
4727#ifndef VBOX_FOR_DTRACE_LIB
4728 uint64_t uAddr;
4729#else
4730 uint16_t au16Addr[4];
4731#endif
4732} X86XDTR64, *PX86XDTR64;
4733#pragma pack()
4734
4735
4736/** @name ModR/M
4737 * @{ */
4738#define X86_MODRM_RM_MASK UINT8_C(0x07)
4739#define X86_MODRM_REG_MASK UINT8_C(0x38)
4740#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4741#define X86_MODRM_REG_SHIFT 3
4742#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4743#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4744#define X86_MODRM_MOD_SHIFT 6
4745#ifndef VBOX_FOR_DTRACE_LIB
4746AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
4747AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4748AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4749/** @def X86_MODRM_MAKE
4750 * @param a_Mod The mod value (0..3).
4751 * @param a_Reg The register value (0..7).
4752 * @param a_RegMem The register or memory value (0..7). */
4753# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
4754#endif
4755/** @} */
4756
4757/** @name SIB
4758 * @{ */
4759#define X86_SIB_BASE_MASK UINT8_C(0x07)
4760#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4761#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4762#define X86_SIB_INDEX_SHIFT 3
4763#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4764#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4765#define X86_SIB_SCALE_SHIFT 6
4766#ifndef VBOX_FOR_DTRACE_LIB
4767AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
4768AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4769AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4770#endif
4771/** @} */
4772
4773/** @name General register indexes.
4774 * @{ */
4775#define X86_GREG_xAX 0
4776#define X86_GREG_xCX 1
4777#define X86_GREG_xDX 2
4778#define X86_GREG_xBX 3
4779#define X86_GREG_xSP 4
4780#define X86_GREG_xBP 5
4781#define X86_GREG_xSI 6
4782#define X86_GREG_xDI 7
4783#define X86_GREG_x8 8
4784#define X86_GREG_x9 9
4785#define X86_GREG_x10 10
4786#define X86_GREG_x11 11
4787#define X86_GREG_x12 12
4788#define X86_GREG_x13 13
4789#define X86_GREG_x14 14
4790#define X86_GREG_x15 15
4791/** @} */
4792/** General register count. */
4793#define X86_GREG_COUNT 16
4794
4795/** @name X86_SREG_XXX - Segment register indexes.
4796 * @{ */
4797#define X86_SREG_ES 0
4798#define X86_SREG_CS 1
4799#define X86_SREG_SS 2
4800#define X86_SREG_DS 3
4801#define X86_SREG_FS 4
4802#define X86_SREG_GS 5
4803/** @} */
4804/** Segment register count. */
4805#define X86_SREG_COUNT 6
4806
4807
4808/** @name X86_OP_XXX - Prefixes
4809 * @{ */
4810#define X86_OP_PRF_CS UINT8_C(0x2e)
4811#define X86_OP_PRF_SS UINT8_C(0x36)
4812#define X86_OP_PRF_DS UINT8_C(0x3e)
4813#define X86_OP_PRF_ES UINT8_C(0x26)
4814#define X86_OP_PRF_FS UINT8_C(0x64)
4815#define X86_OP_PRF_GS UINT8_C(0x65)
4816#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4817#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4818#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4819#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4820#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4821#define X86_OP_REX_B UINT8_C(0x41)
4822#define X86_OP_REX_X UINT8_C(0x42)
4823#define X86_OP_REX_R UINT8_C(0x44)
4824#define X86_OP_REX_W UINT8_C(0x48)
4825/** @} */
4826
4827
4828/** @} */
4829
4830#endif /* !IPRT_INCLUDED_x86_h */
4831
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