x86.h@ 94480

Last change on this file since 94480 was 94440, checked in by vboxsync, 3 years ago
VMM/IEM: fxam does not raise any exceptions and has special classification result for an empty ST(0) register. bugref:9898
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 178.9 KB

Line
1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2022 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef IPRT_INCLUDED_x86_h
29	#define IPRT_INCLUDED_x86_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef VBOX_FOR_DTRACE_LIB
35	# include <iprt/types.h>
36	# include <iprt/assert.h>
37	#else
38	# pragma D depends_on library vbox-types.d
39	#endif
40
41	/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
42	* defining MSR_IA32_FLUSH_CMD */
43	#ifdef RT_OS_SOLARIS
44	# undef CS
45	# undef DS
46	# undef MSR_IA32_FLUSH_CMD
47	#endif
48
49	/** @defgroup grp_rt_x86 x86 Types and Definitions
50	* @ingroup grp_rt
51	* @{
52	*/
53
54	#ifndef VBOX_FOR_DTRACE_LIB
55	/**
56	* EFLAGS Bits.
57	*/
58	typedef struct X86EFLAGSBITS
59	{
60	/** Bit 0 - CF - Carry flag - Status flag. */
61	unsigned u1CF : 1;
62	/** Bit 1 - 1 - Reserved flag. */
63	unsigned u1Reserved0 : 1;
64	/** Bit 2 - PF - Parity flag - Status flag. */
65	unsigned u1PF : 1;
66	/** Bit 3 - 0 - Reserved flag. */
67	unsigned u1Reserved1 : 1;
68	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
69	unsigned u1AF : 1;
70	/** Bit 5 - 0 - Reserved flag. */
71	unsigned u1Reserved2 : 1;
72	/** Bit 6 - ZF - Zero flag - Status flag. */
73	unsigned u1ZF : 1;
74	/** Bit 7 - SF - Signed flag - Status flag. */
75	unsigned u1SF : 1;
76	/** Bit 8 - TF - Trap flag - System flag. */
77	unsigned u1TF : 1;
78	/** Bit 9 - IF - Interrupt flag - System flag. */
79	unsigned u1IF : 1;
80	/** Bit 10 - DF - Direction flag - Control flag. */
81	unsigned u1DF : 1;
82	/** Bit 11 - OF - Overflow flag - Status flag. */
83	unsigned u1OF : 1;
84	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
85	unsigned u2IOPL : 2;
86	/** Bit 14 - NT - Nested task flag - System flag. */
87	unsigned u1NT : 1;
88	/** Bit 15 - 0 - Reserved flag. */
89	unsigned u1Reserved3 : 1;
90	/** Bit 16 - RF - Resume flag - System flag. */
91	unsigned u1RF : 1;
92	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
93	unsigned u1VM : 1;
94	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
95	unsigned u1AC : 1;
96	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
97	unsigned u1VIF : 1;
98	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
99	unsigned u1VIP : 1;
100	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
101	unsigned u1ID : 1;
102	/** Bit 22-31 - 0 - Reserved flag. */
103	unsigned u10Reserved4 : 10;
104	} X86EFLAGSBITS;
105	/** Pointer to EFLAGS bits. */
106	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
107	/** Pointer to const EFLAGS bits. */
108	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
109	#endif /* !VBOX_FOR_DTRACE_LIB */
110
111	/**
112	* EFLAGS.
113	*/
114	typedef union X86EFLAGS
115	{
116	/** The plain unsigned view. */
117	uint32_t u;
118	#ifndef VBOX_FOR_DTRACE_LIB
119	/** The bitfield view. */
120	X86EFLAGSBITS Bits;
121	#endif
122	/** The 8-bit view. */
123	uint8_t au8[4];
124	/** The 16-bit view. */
125	uint16_t au16[2];
126	/** The 32-bit view. */
127	uint32_t au32[1];
128	/** The 32-bit view. */
129	uint32_t u32;
130	} X86EFLAGS;
131	/** Pointer to EFLAGS. */
132	typedef X86EFLAGS *PX86EFLAGS;
133	/** Pointer to const EFLAGS. */
134	typedef const X86EFLAGS *PCX86EFLAGS;
135
136	/**
137	* RFLAGS (32 upper bits are reserved).
138	*/
139	typedef union X86RFLAGS
140	{
141	/** The plain unsigned view. */
142	uint64_t u;
143	#ifndef VBOX_FOR_DTRACE_LIB
144	/** The bitfield view. */
145	X86EFLAGSBITS Bits;
146	#endif
147	/** The 8-bit view. */
148	uint8_t au8[8];
149	/** The 16-bit view. */
150	uint16_t au16[4];
151	/** The 32-bit view. */
152	uint32_t au32[2];
153	/** The 64-bit view. */
154	uint64_t au64[1];
155	/** The 64-bit view. */
156	uint64_t u64;
157	} X86RFLAGS;
158	/** Pointer to RFLAGS. */
159	typedef X86RFLAGS *PX86RFLAGS;
160	/** Pointer to const RFLAGS. */
161	typedef const X86RFLAGS *PCX86RFLAGS;
162
163
164	/** @name EFLAGS
165	* @{
166	*/
167	/** Bit 0 - CF - Carry flag - Status flag. */
168	#define X86_EFL_CF RT_BIT_32(0)
169	#define X86_EFL_CF_BIT 0
170	/** Bit 1 - Reserved, reads as 1. */
171	#define X86_EFL_1 RT_BIT_32(1)
172	/** Bit 2 - PF - Parity flag - Status flag. */
173	#define X86_EFL_PF RT_BIT_32(2)
174	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
175	#define X86_EFL_AF RT_BIT_32(4)
176	#define X86_EFL_AF_BIT 4
177	/** Bit 6 - ZF - Zero flag - Status flag. */
178	#define X86_EFL_ZF RT_BIT_32(6)
179	#define X86_EFL_ZF_BIT 6
180	/** Bit 7 - SF - Signed flag - Status flag. */
181	#define X86_EFL_SF RT_BIT_32(7)
182	#define X86_EFL_SF_BIT 7
183	/** Bit 8 - TF - Trap flag - System flag. */
184	#define X86_EFL_TF RT_BIT_32(8)
185	/** Bit 9 - IF - Interrupt flag - System flag. */
186	#define X86_EFL_IF RT_BIT_32(9)
187	/** Bit 10 - DF - Direction flag - Control flag. */
188	#define X86_EFL_DF RT_BIT_32(10)
189	/** Bit 11 - OF - Overflow flag - Status flag. */
190	#define X86_EFL_OF RT_BIT_32(11)
191	#define X86_EFL_OF_BIT 11
192	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
193	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
194	/** Bit 14 - NT - Nested task flag - System flag. */
195	#define X86_EFL_NT RT_BIT_32(14)
196	/** Bit 16 - RF - Resume flag - System flag. */
197	#define X86_EFL_RF RT_BIT_32(16)
198	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
199	#define X86_EFL_VM RT_BIT_32(17)
200	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
201	#define X86_EFL_AC RT_BIT_32(18)
202	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
203	#define X86_EFL_VIF RT_BIT_32(19)
204	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
205	#define X86_EFL_VIP RT_BIT_32(20)
206	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
207	#define X86_EFL_ID RT_BIT_32(21)
208	/** All live bits. */
209	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
210	/** Read as 1 bits. */
211	#define X86_EFL_RA1_MASK RT_BIT_32(1)
212	/** IOPL shift. */
213	#define X86_EFL_IOPL_SHIFT 12
214	/** The IOPL level from the flags. */
215	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
216	/** Bits restored by popf */
217	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
218	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
219	/** Bits restored by popf */
220	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
221	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
222	/** The status bits commonly updated by arithmetic instructions. */
223	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
224	/** @} */
225
226
227	/** CPUID Feature information - ECX.
228	* CPUID query with EAX=1.
229	*/
230	#ifndef VBOX_FOR_DTRACE_LIB
231	typedef struct X86CPUIDFEATECX
232	{
233	/** Bit 0 - SSE3 - Supports SSE3 or not. */
234	unsigned u1SSE3 : 1;
235	/** Bit 1 - PCLMULQDQ. */
236	unsigned u1PCLMULQDQ : 1;
237	/** Bit 2 - DS Area 64-bit layout. */
238	unsigned u1DTE64 : 1;
239	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
240	unsigned u1Monitor : 1;
241	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
242	unsigned u1CPLDS : 1;
243	/** Bit 5 - VMX - Virtual Machine Technology. */
244	unsigned u1VMX : 1;
245	/** Bit 6 - SMX: Safer Mode Extensions. */
246	unsigned u1SMX : 1;
247	/** Bit 7 - EST - Enh. SpeedStep Tech. */
248	unsigned u1EST : 1;
249	/** Bit 8 - TM2 - Terminal Monitor 2. */
250	unsigned u1TM2 : 1;
251	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
252	unsigned u1SSSE3 : 1;
253	/** Bit 10 - CNTX-ID - L1 Context ID. */
254	unsigned u1CNTXID : 1;
255	/** Bit 11 - Reserved. */
256	unsigned u1Reserved1 : 1;
257	/** Bit 12 - FMA. */
258	unsigned u1FMA : 1;
259	/** Bit 13 - CX16 - CMPXCHG16B. */
260	unsigned u1CX16 : 1;
261	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
262	unsigned u1TPRUpdate : 1;
263	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
264	unsigned u1PDCM : 1;
265	/** Bit 16 - Reserved. */
266	unsigned u1Reserved2 : 1;
267	/** Bit 17 - PCID - Process-context identifiers. */
268	unsigned u1PCID : 1;
269	/** Bit 18 - Direct Cache Access. */
270	unsigned u1DCA : 1;
271	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
272	unsigned u1SSE4_1 : 1;
273	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
274	unsigned u1SSE4_2 : 1;
275	/** Bit 21 - x2APIC. */
276	unsigned u1x2APIC : 1;
277	/** Bit 22 - MOVBE - Supports MOVBE. */
278	unsigned u1MOVBE : 1;
279	/** Bit 23 - POPCNT - Supports POPCNT. */
280	unsigned u1POPCNT : 1;
281	/** Bit 24 - TSC-Deadline. */
282	unsigned u1TSCDEADLINE : 1;
283	/** Bit 25 - AES. */
284	unsigned u1AES : 1;
285	/** Bit 26 - XSAVE - Supports XSAVE. */
286	unsigned u1XSAVE : 1;
287	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
288	unsigned u1OSXSAVE : 1;
289	/** Bit 28 - AVX - Supports AVX instruction extensions. */
290	unsigned u1AVX : 1;
291	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
292	unsigned u1F16C : 1;
293	/** Bit 30 - RDRAND - Supports RDRAND. */
294	unsigned u1RDRAND : 1;
295	/** Bit 31 - Hypervisor present (we're a guest). */
296	unsigned u1HVP : 1;
297	} X86CPUIDFEATECX;
298	#else /* VBOX_FOR_DTRACE_LIB */
299	typedef uint32_t X86CPUIDFEATECX;
300	#endif /* VBOX_FOR_DTRACE_LIB */
301	/** Pointer to CPUID Feature Information - ECX. */
302	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
303	/** Pointer to const CPUID Feature Information - ECX. */
304	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
305
306
307	/** CPUID Feature Information - EDX.
308	* CPUID query with EAX=1.
309	*/
310	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
311	typedef struct X86CPUIDFEATEDX
312	{
313	/** Bit 0 - FPU - x87 FPU on Chip. */
314	unsigned u1FPU : 1;
315	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
316	unsigned u1VME : 1;
317	/** Bit 2 - DE - Debugging extensions. */
318	unsigned u1DE : 1;
319	/** Bit 3 - PSE - Page Size Extension. */
320	unsigned u1PSE : 1;
321	/** Bit 4 - TSC - Time Stamp Counter. */
322	unsigned u1TSC : 1;
323	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
324	unsigned u1MSR : 1;
325	/** Bit 6 - PAE - Physical Address Extension. */
326	unsigned u1PAE : 1;
327	/** Bit 7 - MCE - Machine Check Exception. */
328	unsigned u1MCE : 1;
329	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
330	unsigned u1CX8 : 1;
331	/** Bit 9 - APIC - APIC On-Chip. */
332	unsigned u1APIC : 1;
333	/** Bit 10 - Reserved. */
334	unsigned u1Reserved1 : 1;
335	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
336	unsigned u1SEP : 1;
337	/** Bit 12 - MTRR - Memory Type Range Registers. */
338	unsigned u1MTRR : 1;
339	/** Bit 13 - PGE - PTE Global Bit. */
340	unsigned u1PGE : 1;
341	/** Bit 14 - MCA - Machine Check Architecture. */
342	unsigned u1MCA : 1;
343	/** Bit 15 - CMOV - Conditional Move Instructions. */
344	unsigned u1CMOV : 1;
345	/** Bit 16 - PAT - Page Attribute Table. */
346	unsigned u1PAT : 1;
347	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
348	unsigned u1PSE36 : 1;
349	/** Bit 18 - PSN - Processor Serial Number. */
350	unsigned u1PSN : 1;
351	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
352	unsigned u1CLFSH : 1;
353	/** Bit 20 - Reserved. */
354	unsigned u1Reserved2 : 1;
355	/** Bit 21 - DS - Debug Store. */
356	unsigned u1DS : 1;
357	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
358	unsigned u1ACPI : 1;
359	/** Bit 23 - MMX - Intel MMX 'Technology'. */
360	unsigned u1MMX : 1;
361	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
362	unsigned u1FXSR : 1;
363	/** Bit 25 - SSE - SSE Support. */
364	unsigned u1SSE : 1;
365	/** Bit 26 - SSE2 - SSE2 Support. */
366	unsigned u1SSE2 : 1;
367	/** Bit 27 - SS - Self Snoop. */
368	unsigned u1SS : 1;
369	/** Bit 28 - HTT - Hyper-Threading Technology. */
370	unsigned u1HTT : 1;
371	/** Bit 29 - TM - Thermal Monitor. */
372	unsigned u1TM : 1;
373	/** Bit 30 - Reserved - . */
374	unsigned u1Reserved3 : 1;
375	/** Bit 31 - PBE - Pending Break Enabled. */
376	unsigned u1PBE : 1;
377	} X86CPUIDFEATEDX;
378	#else /* VBOX_FOR_DTRACE_LIB */
379	typedef uint32_t X86CPUIDFEATEDX;
380	#endif /* VBOX_FOR_DTRACE_LIB */
381	/** Pointer to CPUID Feature Information - EDX. */
382	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
383	/** Pointer to const CPUID Feature Information - EDX. */
384	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
385
386	/** @name CPUID Vendor information.
387	* CPUID query with EAX=0.
388	* @{
389	*/
390	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
391	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
392	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
393
394	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
395	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
396	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
397
398	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
399	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
400	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
401
402	#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
403	#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
404	#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
405
406	#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
407	#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
408	#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
409	/** @} */
410
411
412	/** @name CPUID Feature information.
413	* CPUID query with EAX=1.
414	* @{
415	*/
416	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
417	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
418	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
419	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
420	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
421	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
422	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
423	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
424	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
425	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
426	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
427	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
428	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
429	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
430	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
431	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
432	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
433	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
434	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
435	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
436	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
437	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
438	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
439	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
440	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
441	/** ECX Bit 12 - FMA. */
442	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
443	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
444	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
445	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
446	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
447	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
448	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
449	/** ECX Bit 17 - PCID - Process-context identifiers. */
450	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
451	/** ECX Bit 18 - DCA - Direct Cache Access. */
452	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
453	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
454	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
455	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
456	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
457	/** ECX Bit 21 - x2APIC support. */
458	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
459	/** ECX Bit 22 - MOVBE instruction. */
460	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
461	/** ECX Bit 23 - POPCNT instruction. */
462	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
463	/** ECX Bir 24 - TSC-Deadline. */
464	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
465	/** ECX Bit 25 - AES instructions. */
466	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
467	/** ECX Bit 26 - XSAVE instruction. */
468	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
469	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
470	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
471	/** ECX Bit 28 - AVX. */
472	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
473	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
474	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
475	/** ECX Bit 30 - RDRAND instruction. */
476	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
477	/** ECX Bit 31 - Hypervisor Present (software only). */
478	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
479
480
481	/** Bit 0 - FPU - x87 FPU on Chip. */
482	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
483	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
484	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
485	/** Bit 2 - DE - Debugging extensions. */
486	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
487	/** Bit 3 - PSE - Page Size Extension. */
488	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
489	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
490	/** Bit 4 - TSC - Time Stamp Counter. */
491	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
492	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
493	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
494	/** Bit 6 - PAE - Physical Address Extension. */
495	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
496	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
497	/** Bit 7 - MCE - Machine Check Exception. */
498	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
499	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
500	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
501	/** Bit 9 - APIC - APIC On-Chip. */
502	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
503	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
504	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
505	/** Bit 12 - MTRR - Memory Type Range Registers. */
506	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
507	/** Bit 13 - PGE - PTE Global Bit. */
508	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
509	/** Bit 14 - MCA - Machine Check Architecture. */
510	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
511	/** Bit 15 - CMOV - Conditional Move Instructions. */
512	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
513	/** Bit 16 - PAT - Page Attribute Table. */
514	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
515	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
516	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
517	/** Bit 18 - PSN - Processor Serial Number. */
518	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
519	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
520	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
521	/** Bit 21 - DS - Debug Store. */
522	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
523	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
524	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
525	/** Bit 23 - MMX - Intel MMX Technology. */
526	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
527	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
528	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
529	/** Bit 25 - SSE - SSE Support. */
530	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
531	/** Bit 26 - SSE2 - SSE2 Support. */
532	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
533	/** Bit 27 - SS - Self Snoop. */
534	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
535	/** Bit 28 - HTT - Hyper-Threading Technology. */
536	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
537	/** Bit 29 - TM - Therm. Monitor. */
538	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
539	/** Bit 31 - PBE - Pending Break Enabled. */
540	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
541	/** @} */
542
543	/** @name CPUID mwait/monitor information.
544	* CPUID query with EAX=5.
545	* @{
546	*/
547	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
548	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
549	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
550	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
551	/** @} */
552
553
554	/** @name CPUID Structured Extended Feature information.
555	* CPUID query with EAX=7.
556	* @{
557	*/
558	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
559	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
560	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
561	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
562	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
563	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
564	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
565	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
566	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
567	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
568	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
569	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
570	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
571	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
572	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
573	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
574	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
575	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
576	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
577	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
578	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
579	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
580	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
581	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
582	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
583	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
584	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
585	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
586	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
587	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
588	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
589	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
590	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
591	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
592	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
593	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
594	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
595	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
596	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
597	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
598	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
599	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
600	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
601	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
602	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
603	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
604	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
605	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
606	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
607	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
608	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
609	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
610
611	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
612	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
613	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
614	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
615	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
616	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
617	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
618	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
619	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
620	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
621	/** ECX Bit 22 - RDPID - Support pread process ID. */
622	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
623	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
624	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
625
626	/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
627	#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
628	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
629	* IBPB command in IA32_PRED_CMD. */
630	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
631	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
632	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
633	/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
634	#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
635	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
636	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
637	/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
638	#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
639
640	/** @} */
641
642
643	/** @name CPUID Extended Feature information.
644	* CPUID query with EAX=0x80000001.
645	* @{
646	*/
647	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
648	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
649
650	/** EDX Bit 11 - SYSCALL/SYSRET. */
651	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
652	/** EDX Bit 20 - No-Execute/Execute-Disable. */
653	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
654	/** EDX Bit 26 - 1 GB large page. */
655	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
656	/** EDX Bit 27 - RDTSCP. */
657	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
658	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
659	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
660	/** @}*/
661
662	/** @name CPUID AMD Feature information.
663	* CPUID query with EAX=0x80000001.
664	* @{
665	*/
666	/** Bit 0 - FPU - x87 FPU on Chip. */
667	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
668	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
669	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
670	/** Bit 2 - DE - Debugging extensions. */
671	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
672	/** Bit 3 - PSE - Page Size Extension. */
673	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
674	/** Bit 4 - TSC - Time Stamp Counter. */
675	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
676	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
677	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
678	/** Bit 6 - PAE - Physical Address Extension. */
679	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
680	/** Bit 7 - MCE - Machine Check Exception. */
681	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
682	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
683	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
684	/** Bit 9 - APIC - APIC On-Chip. */
685	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
686	/** Bit 12 - MTRR - Memory Type Range Registers. */
687	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
688	/** Bit 13 - PGE - PTE Global Bit. */
689	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
690	/** Bit 14 - MCA - Machine Check Architecture. */
691	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
692	/** Bit 15 - CMOV - Conditional Move Instructions. */
693	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
694	/** Bit 16 - PAT - Page Attribute Table. */
695	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
696	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
697	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
698	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
699	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
700	/** Bit 23 - MMX - Intel MMX Technology. */
701	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
702	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
703	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
704	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
705	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
706	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
707	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
708	/** Bit 31 - 3DNOW - AMD 3DNow. */
709	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
710
711	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
712	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
713	/** Bit 2 - SVM - AMD VM extensions. */
714	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
715	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
716	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
717	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
718	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
719	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
720	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
721	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
722	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
723	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
724	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
725	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
726	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
727	/** Bit 9 - OSVW - AMD OS visible workaround. */
728	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
729	/** Bit 10 - IBS - Instruct based sampling. */
730	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
731	/** Bit 11 - XOP - Extended operation support (see APM6). */
732	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
733	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
734	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
735	/** Bit 13 - WDT - AMD Watchdog timer support. */
736	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
737	/** Bit 15 - LWP - Lightweight profiling support. */
738	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
739	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
740	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
741	/** Bit 19 - NodeId - Indicates support for
742	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
743	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
744	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
745	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
746	/** Bit 22 - TopologyExtensions - . */
747	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
748	/** @} */
749
750
751	/** @name CPUID AMD Feature information.
752	* CPUID query with EAX=0x80000007.
753	* @{
754	*/
755	/** Bit 0 - TS - Temperature Sensor. */
756	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
757	/** Bit 1 - FID - Frequency ID Control. */
758	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
759	/** Bit 2 - VID - Voltage ID Control. */
760	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
761	/** Bit 3 - TTP - THERMTRIP. */
762	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
763	/** Bit 4 - TM - Hardware Thermal Control. */
764	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
765	/** Bit 5 - STC - Software Thermal Control. */
766	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
767	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
768	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
769	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
770	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
771	/** Bit 8 - TSCINVAR - TSC Invariant. */
772	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
773	/** Bit 9 - CPB - TSC Invariant. */
774	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
775	/** Bit 10 - EffFreqRO - MPERF/APERF. */
776	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
777	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
778	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
779	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
780	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
781	/** @} */
782
783
784	/** @name CPUID AMD extended feature extensions ID (EBX).
785	* CPUID query with EAX=0x80000008.
786	* @{
787	*/
788	/** Bit 0 - CLZERO - Clear zero instruction. */
789	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
790	/** Bit 1 - IRPerf - Instructions retired count support. */
791	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
792	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
793	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
794	/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
795	#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
796	/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
797	#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
798	/* AMD pipeline length: 9 feature bits ;-) */
799	/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
800	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
801	/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
802	#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
803	/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
804	#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
805	/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
806	#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
807	/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
808	#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
809	/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
810	#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
811	/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
812	#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
813	/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
814	#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
815	/** Bit 26 - Speculative Store Bypass Disable not required. */
816	#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
817	/** @} */
818
819
820	/** @name CPUID AMD SVM Feature information.
821	* CPUID query with EAX=0x8000000a.
822	* @{
823	*/
824	/** Bit 0 - NP - Nested Paging supported. */
825	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
826	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
827	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
828	/** Bit 2 - SVML - SVM locking bit supported. */
829	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
830	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
831	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
832	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
833	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
834	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
835	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
836	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
837	* VMCB.TLB_Control is supported. */
838	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
839	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
840	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
841	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
842	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
843	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
844	* intercept filter cycle count threshold. */
845	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
846	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
847	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
848	/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
849	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
850	/** Bit 16 - VGIF - Supports virtualized GIF. */
851	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
852	/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
853	#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
854
855	/** @} */
856
857
858	/** @name CR0
859	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
860	* reserved flags.
861	* @{ */
862	/** Bit 0 - PE - Protection Enabled */
863	#define X86_CR0_PE RT_BIT_32(0)
864	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
865	/** Bit 1 - MP - Monitor Coprocessor */
866	#define X86_CR0_MP RT_BIT_32(1)
867	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
868	/** Bit 2 - EM - Emulation. */
869	#define X86_CR0_EM RT_BIT_32(2)
870	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
871	/** Bit 3 - TS - Task Switch. */
872	#define X86_CR0_TS RT_BIT_32(3)
873	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
874	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
875	#define X86_CR0_ET RT_BIT_32(4)
876	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
877	/** Bit 5 - NE - Numeric error (486+). */
878	#define X86_CR0_NE RT_BIT_32(5)
879	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
880	/** Bit 16 - WP - Write Protect (486+). */
881	#define X86_CR0_WP RT_BIT_32(16)
882	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
883	/** Bit 18 - AM - Alignment Mask (486+). */
884	#define X86_CR0_AM RT_BIT_32(18)
885	#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
886	/** Bit 29 - NW - Not Write-though (486+). */
887	#define X86_CR0_NW RT_BIT_32(29)
888	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
889	/** Bit 30 - WP - Cache Disable (486+). */
890	#define X86_CR0_CD RT_BIT_32(30)
891	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
892	/** Bit 31 - PG - Paging. */
893	#define X86_CR0_PG RT_BIT_32(31)
894	#define X86_CR0_PAGING RT_BIT_32(31)
895	#define X86_CR0_BIT_PG 31 /*< Bit number of X86_CR0_PG /
896	/** @} */
897
898
899	/** @name CR3
900	* @{ */
901	/** Bit 3 - PWT - Page-level Writes Transparent. */
902	#define X86_CR3_PWT RT_BIT_32(3)
903	/** Bit 4 - PCD - Page-level Cache Disable. */
904	#define X86_CR3_PCD RT_BIT_32(4)
905	/** Bits 12-31 - - Page directory page number. */
906	#define X86_CR3_PAGE_MASK (0xfffff000)
907	/** Bits 5-31 - - PAE Page directory page number. */
908	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
909	/** Bits 12-51 - - AMD64 Page directory page number. */
910	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
911	/** Bits 12-47 - - Intel EPT Page directory page number. */
912	#define X86_CR3_EPT_PAGE_MASK UINT64_C(0x0000fffffffff000)
913	/** @} */
914
915
916	/** @name CR4
917	* @{ */
918	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
919	#define X86_CR4_VME RT_BIT_32(0)
920	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
921	#define X86_CR4_PVI RT_BIT_32(1)
922	/** Bit 2 - TSD - Time Stamp Disable. */
923	#define X86_CR4_TSD RT_BIT_32(2)
924	/** Bit 3 - DE - Debugging Extensions. */
925	#define X86_CR4_DE RT_BIT_32(3)
926	/** Bit 4 - PSE - Page Size Extension. */
927	#define X86_CR4_PSE RT_BIT_32(4)
928	/** Bit 5 - PAE - Physical Address Extension. */
929	#define X86_CR4_PAE RT_BIT_32(5)
930	/** Bit 6 - MCE - Machine-Check Enable. */
931	#define X86_CR4_MCE RT_BIT_32(6)
932	/** Bit 7 - PGE - Page Global Enable. */
933	#define X86_CR4_PGE RT_BIT_32(7)
934	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
935	#define X86_CR4_PCE RT_BIT_32(8)
936	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
937	#define X86_CR4_OSFXSR RT_BIT_32(9)
938	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
939	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
940	/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
941	#define X86_CR4_UMIP RT_BIT_32(11)
942	/** Bit 13 - VMXE - VMX mode is enabled. */
943	#define X86_CR4_VMXE RT_BIT_32(13)
944	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
945	#define X86_CR4_SMXE RT_BIT_32(14)
946	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
947	#define X86_CR4_FSGSBASE RT_BIT_32(16)
948	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
949	#define X86_CR4_PCIDE RT_BIT_32(17)
950	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
951	* extended states. */
952	#define X86_CR4_OSXSAVE RT_BIT_32(18)
953	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
954	#define X86_CR4_SMEP RT_BIT_32(20)
955	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
956	#define X86_CR4_SMAP RT_BIT_32(21)
957	/** Bit 22 - PKE - Protection Key Enable. */
958	#define X86_CR4_PKE RT_BIT_32(22)
959	/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
960	#define X86_CR4_CET RT_BIT_32(23)
961	/** @} */
962
963
964	/** @name DR6
965	* @{ */
966	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
967	#define X86_DR6_B0 RT_BIT_32(0)
968	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
969	#define X86_DR6_B1 RT_BIT_32(1)
970	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
971	#define X86_DR6_B2 RT_BIT_32(2)
972	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
973	#define X86_DR6_B3 RT_BIT_32(3)
974	/** Mask of all the Bx bits. */
975	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
976	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
977	#define X86_DR6_BD RT_BIT_32(13)
978	/** Bit 14 - BS - Single step */
979	#define X86_DR6_BS RT_BIT_32(14)
980	/** Bit 15 - BT - Task switch. (TSS T bit.) */
981	#define X86_DR6_BT RT_BIT_32(15)
982	/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
983	#define X86_DR6_RTM RT_BIT_32(16)
984	/** Value of DR6 after powerup/reset. */
985	#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
986	/** Bits which must be 1s in DR6. */
987	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
988	/** Bits which must be 1s in DR6, when RTM is supported. */
989	#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
990	/** Bits which must be 0s in DR6. */
991	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
992	/** Bits which must be 0s on writes to DR6. */
993	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
994	/** @} */
995
996	/** Get the DR6.Bx bit for a the given breakpoint. */
997	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
998
999
1000	/** @name DR7
1001	* @{ */
1002	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1003	#define X86_DR7_L0 RT_BIT_32(0)
1004	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1005	#define X86_DR7_G0 RT_BIT_32(1)
1006	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1007	#define X86_DR7_L1 RT_BIT_32(2)
1008	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1009	#define X86_DR7_G1 RT_BIT_32(3)
1010	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1011	#define X86_DR7_L2 RT_BIT_32(4)
1012	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1013	#define X86_DR7_G2 RT_BIT_32(5)
1014	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1015	#define X86_DR7_L3 RT_BIT_32(6)
1016	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1017	#define X86_DR7_G3 RT_BIT_32(7)
1018	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1019	#define X86_DR7_LE RT_BIT_32(8)
1020	/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1021	#define X86_DR7_GE RT_BIT_32(9)
1022
1023	/** L0, L1, L2, and L3. */
1024	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1025	/** L0, L1, L2, and L3. */
1026	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1027
1028	/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1029	* Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1030	#define X86_DR7_RTM RT_BIT_32(11)
1031	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1032	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1033	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1034	* instruction is executed.
1035	* @see http://www.rcollins.org/secrets/DR7.html */
1036	#define X86_DR7_ICE_IR RT_BIT_32(12)
1037	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1038	* any DR register is accessed. */
1039	#define X86_DR7_GD RT_BIT_32(13)
1040	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1041	* Pentium. */
1042	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1043	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1044	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1045	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
1046	#define X86_DR7_RW0_MASK (3 << 16)
1047	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
1048	#define X86_DR7_LEN0_MASK (3 << 18)
1049	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
1050	#define X86_DR7_RW1_MASK (3 << 20)
1051	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
1052	#define X86_DR7_LEN1_MASK (3 << 22)
1053	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
1054	#define X86_DR7_RW2_MASK (3 << 24)
1055	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1056	#define X86_DR7_LEN2_MASK (3 << 26)
1057	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1058	#define X86_DR7_RW3_MASK (3 << 28)
1059	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1060	#define X86_DR7_LEN3_MASK (3 << 30)
1061
1062	/** Bits which reads as 1s. */
1063	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1064	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1065	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1066	/** Bits which must be 0s when writing to DR7. */
1067	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1068
1069	/** Calcs the L bit of Nth breakpoint.
1070	* @param iBp The breakpoint number [0..3].
1071	*/
1072	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1073
1074	/** Calcs the G bit of Nth breakpoint.
1075	* @param iBp The breakpoint number [0..3].
1076	*/
1077	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1078
1079	/** Calcs the L and G bits of Nth breakpoint.
1080	* @param iBp The breakpoint number [0..3].
1081	*/
1082	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1083
1084	/** @name Read/Write values.
1085	* @{ */
1086	/** Break on instruction fetch only. */
1087	#define X86_DR7_RW_EO UINT32_C(0)
1088	/** Break on write only. */
1089	#define X86_DR7_RW_WO UINT32_C(1)
1090	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1091	#define X86_DR7_RW_IO UINT32_C(2)
1092	/** Break on read or write (but not instruction fetches). */
1093	#define X86_DR7_RW_RW UINT32_C(3)
1094	/** @} */
1095
1096	/** Shifts a X86_DR7_RW_* value to its right place.
1097	* @param iBp The breakpoint number [0..3].
1098	* @param fRw One of the X86_DR7_RW_* value.
1099	*/
1100	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1101
1102	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1103	* one of the X86_DR7_RW_XXX constants).
1104	*
1105	* @returns X86_DR7_RW_XXX
1106	* @param uDR7 DR7 value
1107	* @param iBp The breakpoint number [0..3].
1108	*/
1109	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1110
1111	/** R/W0, R/W1, R/W2, and R/W3. */
1112	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1113
1114	#ifndef VBOX_FOR_DTRACE_LIB
1115	/** Checks if there are any I/O breakpoint types configured in the RW
1116	* registers. Does NOT check if these are enabled, sorry. */
1117	# define X86_DR7_ANY_RW_IO(uDR7) \
1118	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1119	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1120	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1121	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1122	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1123	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1124	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1125	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1126	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1127	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1128	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1129	#endif /* !VBOX_FOR_DTRACE_LIB */
1130
1131	/** @name Length values.
1132	* @{ */
1133	#define X86_DR7_LEN_BYTE UINT32_C(0)
1134	#define X86_DR7_LEN_WORD UINT32_C(1)
1135	#define X86_DR7_LEN_QWORD UINT32_C(2) /*< AMD64 long mode only. /
1136	#define X86_DR7_LEN_DWORD UINT32_C(3)
1137	/** @} */
1138
1139	/** Shifts a X86_DR7_LEN_* value to its right place.
1140	* @param iBp The breakpoint number [0..3].
1141	* @param cb One of the X86_DR7_LEN_* values.
1142	*/
1143	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1144
1145	/** Fetch the breakpoint length bits from the DR7 value.
1146	* @param uDR7 DR7 value
1147	* @param iBp The breakpoint number [0..3].
1148	*/
1149	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1150
1151	/** Mask used to check if any breakpoints are enabled. */
1152	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1153
1154	/** LEN0, LEN1, LEN2, and LEN3. */
1155	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1156	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1157	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1158
1159	/** Value of DR7 after powerup/reset. */
1160	#define X86_DR7_INIT_VAL 0x400
1161	/** @} */
1162
1163
1164	/** @name Machine Specific Registers
1165	* @{
1166	*/
1167	/** Machine check address register (P5). */
1168	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1169	/** Machine check type register (P5). */
1170	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1171	/** Time Stamp Counter. */
1172	#define MSR_IA32_TSC 0x10
1173	#define MSR_IA32_CESR UINT32_C(0x00000011)
1174	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1175	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1176
1177	#define MSR_IA32_PLATFORM_ID 0x17
1178
1179	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1180	# define MSR_IA32_APICBASE 0x1b
1181	/** Local APIC enabled. */
1182	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1183	/** X2APIC enabled (requires the EN bit to be set). */
1184	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1185	/** The processor is the boot strap processor (BSP). */
1186	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1187	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1188	* width. */
1189	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1190	/** The default physical base address of the APIC. */
1191	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1192	/** Gets the physical base address from the MSR. */
1193	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1194	#endif
1195
1196	/** Undocumented intel MSR for reporting thread and core counts.
1197	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1198	* first 16 bits is the thread count. The next 16 bits the core count, except
1199	* on Westmere where it seems it's only the next 4 bits for some reason. */
1200	#define MSR_CORE_THREAD_COUNT 0x35
1201
1202	/** CPU Feature control. */
1203	#define MSR_IA32_FEATURE_CONTROL 0x3A
1204	/** Feature control - Lock MSR from writes (R/W0). */
1205	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1206	/** Feature control - Enable VMX inside SMX operation (R/WL). */
1207	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1208	/** Feature control - Enable VMX outside SMX operation (R/WL). */
1209	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1210	/** Feature control - SENTER local functions enable (R/WL). */
1211	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1212	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1213	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1214	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1215	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1216	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1217	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1218	/** Feature control - SENTER global enable (R/WL). */
1219	#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1220	/** Feature control - SGX launch control enable (R/WL). */
1221	#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1222	/** Feature control - SGX global enable (R/WL). */
1223	#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1224	/** Feature control - LMCE on (R/WL). */
1225	#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1226
1227	/** Per-processor TSC adjust MSR. */
1228	#define MSR_IA32_TSC_ADJUST 0x3B
1229
1230	/** Spectre control register.
1231	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1232	#define MSR_IA32_SPEC_CTRL 0x48
1233	/** IBRS - Indirect branch restricted speculation. */
1234	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1235	/** STIBP - Single thread indirect branch predictors. */
1236	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1237	/** SSBD - Speculative Store Bypass Disable. */
1238	#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
1239
1240	/** Prediction command register.
1241	* Write only, logical processor scope, no state since write only. */
1242	#define MSR_IA32_PRED_CMD 0x49
1243	/** IBPB - Indirect branch prediction barrie when written as 1. */
1244	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1245
1246	/** BIOS update trigger (microcode update). */
1247	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1248
1249	/** BIOS update signature (microcode). */
1250	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1251
1252	/** SMM monitor control. */
1253	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1254	/** SMM control - Valid. */
1255	#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1256	/** SMM control - VMXOFF unblocks SMI. */
1257	#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1258	/** SMM control - MSEG base physical address. */
1259	#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1260
1261	/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1262	#define MSR_IA32_SMBASE 0x9E
1263
1264	/** General performance counter no. 0. */
1265	#define MSR_IA32_PMC0 0xC1
1266	/** General performance counter no. 1. */
1267	#define MSR_IA32_PMC1 0xC2
1268	/** General performance counter no. 2. */
1269	#define MSR_IA32_PMC2 0xC3
1270	/** General performance counter no. 3. */
1271	#define MSR_IA32_PMC3 0xC4
1272	/** General performance counter no. 4. */
1273	#define MSR_IA32_PMC4 0xC5
1274	/** General performance counter no. 5. */
1275	#define MSR_IA32_PMC5 0xC6
1276	/** General performance counter no. 6. */
1277	#define MSR_IA32_PMC6 0xC7
1278	/** General performance counter no. 7. */
1279	#define MSR_IA32_PMC7 0xC8
1280
1281	/** Nehalem power control. */
1282	#define MSR_IA32_PLATFORM_INFO 0xCE
1283
1284	/** Get FSB clock status (Intel-specific). */
1285	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1286
1287	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1288	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1289
1290	/** C0 Maximum Frequency Clock Count */
1291	#define MSR_IA32_MPERF 0xE7
1292	/** C0 Actual Frequency Clock Count */
1293	#define MSR_IA32_APERF 0xE8
1294
1295	/** MTRR Capabilities. */
1296	#define MSR_IA32_MTRR_CAP 0xFE
1297
1298	/** Architecture capabilities (bugfixes). */
1299	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1300	/** CPU is no subject to meltdown problems. */
1301	#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1302	/** CPU has better IBRS and you can leave it on all the time. */
1303	#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1304	/** CPU has return stack buffer (RSB) override. */
1305	#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1306	/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1307	* This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1308	#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1309	/** CPU does not suffer from MDS issues. */
1310	#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1311
1312	/** Flush command register. */
1313	#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1314	/** Flush the level 1 data cache when this bit is written. */
1315	#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1316
1317	/** Cache control/info. */
1318	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1319
1320	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1321	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1322	* R0 SS == CS + 8
1323	* R3 CS == CS + 16
1324	* R3 SS == CS + 24
1325	*/
1326	#define MSR_IA32_SYSENTER_CS 0x174
1327	/** SYSENTER_ESP - the R0 ESP. */
1328	#define MSR_IA32_SYSENTER_ESP 0x175
1329	/** SYSENTER_EIP - the R0 EIP. */
1330	#define MSR_IA32_SYSENTER_EIP 0x176
1331	#endif
1332
1333	/** Machine Check Global Capabilities Register. */
1334	#define MSR_IA32_MCG_CAP 0x179
1335	/** Machine Check Global Status Register. */
1336	#define MSR_IA32_MCG_STATUS 0x17A
1337	/** Machine Check Global Control Register. */
1338	#define MSR_IA32_MCG_CTRL 0x17B
1339
1340	/** Page Attribute Table. */
1341	#define MSR_IA32_CR_PAT 0x277
1342	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1343	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1344	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1345
1346	/** Performance event select MSRs. (Intel only) */
1347	#define MSR_IA32_PERFEVTSEL0 0x186
1348	#define MSR_IA32_PERFEVTSEL1 0x187
1349	#define MSR_IA32_PERFEVTSEL2 0x188
1350	#define MSR_IA32_PERFEVTSEL3 0x189
1351
1352	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1353	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1354	* holds a ratio that Apple takes for TSC granularity.
1355	*
1356	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1357	#define MSR_FLEX_RATIO 0x194
1358	/** Performance state value and starting with Intel core more.
1359	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1360	#define MSR_IA32_PERF_STATUS 0x198
1361	#define MSR_IA32_PERF_CTL 0x199
1362	#define MSR_IA32_THERM_STATUS 0x19c
1363
1364	/** Offcore response event select registers. */
1365	#define MSR_OFFCORE_RSP_0 0x1a6
1366	#define MSR_OFFCORE_RSP_1 0x1a7
1367
1368	/** Enable misc. processor features (R/W). */
1369	#define MSR_IA32_MISC_ENABLE 0x1A0
1370	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1371	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1372	/** Automatic Thermal Control Circuit Enable (R/W). */
1373	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1374	/** Performance Monitoring Available (R). */
1375	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1376	/** Branch Trace Storage Unavailable (R/O). */
1377	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1378	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1379	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1380	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1381	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1382	/** If MONITOR/MWAIT is supported (R/W). */
1383	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1384	/** Limit CPUID Maxval to 3 leafs (R/W). */
1385	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1386	/** When set to 1, xTPR messages are disabled (R/W). */
1387	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1388	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1389	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1390
1391	/** Trace/Profile Resource Control (R/W) */
1392	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1393	/** Last branch record. */
1394	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1395	/** Branch trace flag (single step on branches). */
1396	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1397	/** Performance monitoring pin control (AMD only). */
1398	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1399	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1400	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1401	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1402	/** Trace message enable (Intel only). */
1403	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1404	/** Branch trace store (Intel only). */
1405	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1406	/** Branch trace interrupt (Intel only). */
1407	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1408	/** Branch trace off in privileged code (Intel only). */
1409	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1410	/** Branch trace off in user code (Intel only). */
1411	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1412	/** Freeze LBR on PMI flag (Intel only). */
1413	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1414	/** Freeze PERFMON on PMI flag (Intel only). */
1415	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1416	/** Freeze while SMM enabled (Intel only). */
1417	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1418	/** Advanced debugging of RTM regions (Intel only). */
1419	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1420	/** Debug control MSR valid bits (Intel only). */
1421	#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR \| MSR_IA32_DEBUGCTL_BTF \| MSR_IA32_DEBUGCTL_TR \
1422	\| MSR_IA32_DEBUGCTL_BTS \| MSR_IA32_DEBUGCTL_BTINT \| MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1423	\| MSR_IA32_DEBUGCTL_BTS_OFF_USER \| MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1424	\| MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI \| MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1425	\| MSR_IA32_DEBUGCTL_RTM)
1426
1427	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1428	* @{ */
1429	#define MSR_P4_LASTBRANCH_0 0x1db
1430	#define MSR_P4_LASTBRANCH_1 0x1dc
1431	#define MSR_P4_LASTBRANCH_2 0x1dd
1432	#define MSR_P4_LASTBRANCH_3 0x1de
1433
1434	/** LBR Top-of-stack MSR (index to most recent record). */
1435	#define MSR_P4_LASTBRANCH_TOS 0x1da
1436	/** @} */
1437
1438	/** @name Last branch registers for Core 2 and related Xeons.
1439	* @{ */
1440	#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1441	#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1442	#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1443	#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1444
1445	#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1446	#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1447	#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1448	#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1449
1450	/** LBR Top-of-stack MSR (index to most recent record). */
1451	#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1452	/** @} */
1453
1454	/** @name Last branch registers.
1455	* @{ */
1456	#define MSR_LASTBRANCH_0_FROM_IP 0x680
1457	#define MSR_LASTBRANCH_1_FROM_IP 0x681
1458	#define MSR_LASTBRANCH_2_FROM_IP 0x682
1459	#define MSR_LASTBRANCH_3_FROM_IP 0x683
1460	#define MSR_LASTBRANCH_4_FROM_IP 0x684
1461	#define MSR_LASTBRANCH_5_FROM_IP 0x685
1462	#define MSR_LASTBRANCH_6_FROM_IP 0x686
1463	#define MSR_LASTBRANCH_7_FROM_IP 0x687
1464	#define MSR_LASTBRANCH_8_FROM_IP 0x688
1465	#define MSR_LASTBRANCH_9_FROM_IP 0x689
1466	#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1467	#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1468	#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1469	#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1470	#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1471	#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1472	#define MSR_LASTBRANCH_16_FROM_IP 0x690
1473	#define MSR_LASTBRANCH_17_FROM_IP 0x691
1474	#define MSR_LASTBRANCH_18_FROM_IP 0x692
1475	#define MSR_LASTBRANCH_19_FROM_IP 0x693
1476	#define MSR_LASTBRANCH_20_FROM_IP 0x694
1477	#define MSR_LASTBRANCH_21_FROM_IP 0x695
1478	#define MSR_LASTBRANCH_22_FROM_IP 0x696
1479	#define MSR_LASTBRANCH_23_FROM_IP 0x697
1480	#define MSR_LASTBRANCH_24_FROM_IP 0x698
1481	#define MSR_LASTBRANCH_25_FROM_IP 0x699
1482	#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1483	#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1484	#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1485	#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1486	#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1487	#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1488
1489	#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1490	#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1491	#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1492	#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1493	#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1494	#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1495	#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1496	#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1497	#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1498	#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1499	#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1500	#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1501	#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1502	#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1503	#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1504	#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1505	#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1506	#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1507	#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1508	#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1509	#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1510	#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1511	#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1512	#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1513	#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1514	#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1515	#define MSR_LASTBRANCH_26_TO_IP 0x6da
1516	#define MSR_LASTBRANCH_27_TO_IP 0x6db
1517	#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1518	#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1519	#define MSR_LASTBRANCH_30_TO_IP 0x6de
1520	#define MSR_LASTBRANCH_31_TO_IP 0x6df
1521
1522	#define MSR_LASTBRANCH_0_INFO 0xdc0
1523	#define MSR_LASTBRANCH_1_INFO 0xdc1
1524	#define MSR_LASTBRANCH_2_INFO 0xdc2
1525	#define MSR_LASTBRANCH_3_INFO 0xdc3
1526	#define MSR_LASTBRANCH_4_INFO 0xdc4
1527	#define MSR_LASTBRANCH_5_INFO 0xdc5
1528	#define MSR_LASTBRANCH_6_INFO 0xdc6
1529	#define MSR_LASTBRANCH_7_INFO 0xdc7
1530	#define MSR_LASTBRANCH_8_INFO 0xdc8
1531	#define MSR_LASTBRANCH_9_INFO 0xdc9
1532	#define MSR_LASTBRANCH_10_INFO 0xdca
1533	#define MSR_LASTBRANCH_11_INFO 0xdcb
1534	#define MSR_LASTBRANCH_12_INFO 0xdcc
1535	#define MSR_LASTBRANCH_13_INFO 0xdcd
1536	#define MSR_LASTBRANCH_14_INFO 0xdce
1537	#define MSR_LASTBRANCH_15_INFO 0xdcf
1538	#define MSR_LASTBRANCH_16_INFO 0xdd0
1539	#define MSR_LASTBRANCH_17_INFO 0xdd1
1540	#define MSR_LASTBRANCH_18_INFO 0xdd2
1541	#define MSR_LASTBRANCH_19_INFO 0xdd3
1542	#define MSR_LASTBRANCH_20_INFO 0xdd4
1543	#define MSR_LASTBRANCH_21_INFO 0xdd5
1544	#define MSR_LASTBRANCH_22_INFO 0xdd6
1545	#define MSR_LASTBRANCH_23_INFO 0xdd7
1546	#define MSR_LASTBRANCH_24_INFO 0xdd8
1547	#define MSR_LASTBRANCH_25_INFO 0xdd9
1548	#define MSR_LASTBRANCH_26_INFO 0xdda
1549	#define MSR_LASTBRANCH_27_INFO 0xddb
1550	#define MSR_LASTBRANCH_28_INFO 0xddc
1551	#define MSR_LASTBRANCH_29_INFO 0xddd
1552	#define MSR_LASTBRANCH_30_INFO 0xdde
1553	#define MSR_LASTBRANCH_31_INFO 0xddf
1554
1555	/** LBR branch tracking selection MSR. */
1556	#define MSR_LASTBRANCH_SELECT 0x1c8
1557	/** LBR Top-of-stack MSR (index to most recent record). */
1558	#define MSR_LASTBRANCH_TOS 0x1c9
1559	/** @} */
1560
1561	/** @name Last event record registers.
1562	* @{ */
1563	/** Last event record source IP register. */
1564	#define MSR_LER_FROM_IP 0x1dd
1565	/** Last event record destination IP register. */
1566	#define MSR_LER_TO_IP 0x1de
1567	/** @} */
1568
1569	/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1570	#define MSR_IA32_TSX_CTRL 0x122
1571
1572	/** Variable range MTRRs.
1573	* @{ */
1574	#define MSR_IA32_MTRR_PHYSBASE0 0x200
1575	#define MSR_IA32_MTRR_PHYSMASK0 0x201
1576	#define MSR_IA32_MTRR_PHYSBASE1 0x202
1577	#define MSR_IA32_MTRR_PHYSMASK1 0x203
1578	#define MSR_IA32_MTRR_PHYSBASE2 0x204
1579	#define MSR_IA32_MTRR_PHYSMASK2 0x205
1580	#define MSR_IA32_MTRR_PHYSBASE3 0x206
1581	#define MSR_IA32_MTRR_PHYSMASK3 0x207
1582	#define MSR_IA32_MTRR_PHYSBASE4 0x208
1583	#define MSR_IA32_MTRR_PHYSMASK4 0x209
1584	#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1585	#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1586	#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1587	#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1588	#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1589	#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1590	#define MSR_IA32_MTRR_PHYSBASE8 0x210
1591	#define MSR_IA32_MTRR_PHYSMASK8 0x211
1592	#define MSR_IA32_MTRR_PHYSBASE9 0x212
1593	#define MSR_IA32_MTRR_PHYSMASK9 0x213
1594	/** @} */
1595
1596	/** Fixed range MTRRs.
1597	* @{ */
1598	#define MSR_IA32_MTRR_FIX64K_00000 0x250
1599	#define MSR_IA32_MTRR_FIX16K_80000 0x258
1600	#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1601	#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1602	#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1603	#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1604	#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1605	#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1606	#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1607	#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1608	#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1609	/** @} */
1610
1611	/** MTRR Default Range. */
1612	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1613
1614	/** Global performance counter control facilities (Intel only). */
1615	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1616	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1617	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1618
1619	/** Precise Event Based sampling (Intel only). */
1620	#define MSR_IA32_PEBS_ENABLE 0x3F1
1621
1622	#define MSR_IA32_MC0_CTL 0x400
1623	#define MSR_IA32_MC0_STATUS 0x401
1624
1625	/** Basic VMX information. */
1626	#define MSR_IA32_VMX_BASIC 0x480
1627	/** Allowed settings for pin-based VM execution controls. */
1628	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1629	/** Allowed settings for proc-based VM execution controls. */
1630	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1631	/** Allowed settings for the VM-exit controls. */
1632	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1633	/** Allowed settings for the VM-entry controls. */
1634	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1635	/** Misc VMX info. */
1636	#define MSR_IA32_VMX_MISC 0x485
1637	/** Fixed cleared bits in CR0. */
1638	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1639	/** Fixed set bits in CR0. */
1640	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1641	/** Fixed cleared bits in CR4. */
1642	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1643	/** Fixed set bits in CR4. */
1644	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1645	/** Information for enumerating fields in the VMCS. */
1646	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1647	/** Allowed settings for secondary processor-based VM-execution controls. */
1648	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1649	/** EPT capabilities. */
1650	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1651	/** Allowed settings of all pin-based VM execution controls. */
1652	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1653	/** Allowed settings of all proc-based VM execution controls. */
1654	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1655	/** Allowed settings of all VMX exit controls. */
1656	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1657	/** Allowed settings of all VMX entry controls. */
1658	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1659	/** Allowed settings for the VM-function controls. */
1660	#define MSR_IA32_VMX_VMFUNC 0x491
1661	/** Tertiary processor-based VM execution controls. */
1662	#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
1663
1664	/** Intel PT - Enable and control for trace packet generation. */
1665	#define MSR_IA32_RTIT_CTL 0x570
1666
1667	/** DS Save Area (R/W). */
1668	#define MSR_IA32_DS_AREA 0x600
1669	/** Running Average Power Limit (RAPL) power units. */
1670	#define MSR_RAPL_POWER_UNIT 0x606
1671	/** Package C3 Interrupt Response Limit. */
1672	#define MSR_PKGC3_IRTL 0x60a
1673	/** Package C6/C7S Interrupt Response Limit 1. */
1674	#define MSR_PKGC_IRTL1 0x60b
1675	/** Package C6/C7S Interrupt Response Limit 2. */
1676	#define MSR_PKGC_IRTL2 0x60c
1677	/** Package C2 Residency Counter. */
1678	#define MSR_PKG_C2_RESIDENCY 0x60d
1679	/** PKG RAPL Power Limit Control. */
1680	#define MSR_PKG_POWER_LIMIT 0x610
1681	/** PKG Energy Status. */
1682	#define MSR_PKG_ENERGY_STATUS 0x611
1683	/** PKG Perf Status. */
1684	#define MSR_PKG_PERF_STATUS 0x613
1685	/** PKG RAPL Parameters. */
1686	#define MSR_PKG_POWER_INFO 0x614
1687	/** DRAM RAPL Power Limit Control. */
1688	#define MSR_DRAM_POWER_LIMIT 0x618
1689	/** DRAM Energy Status. */
1690	#define MSR_DRAM_ENERGY_STATUS 0x619
1691	/** DRAM Performance Throttling Status. */
1692	#define MSR_DRAM_PERF_STATUS 0x61b
1693	/** DRAM RAPL Parameters. */
1694	#define MSR_DRAM_POWER_INFO 0x61c
1695	/** Package C10 Residency Counter. */
1696	#define MSR_PKG_C10_RESIDENCY 0x632
1697	/** PP0 Energy Status. */
1698	#define MSR_PP0_ENERGY_STATUS 0x639
1699	/** PP1 Energy Status. */
1700	#define MSR_PP1_ENERGY_STATUS 0x641
1701	/** Turbo Activation Ratio. */
1702	#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1703	/** Core Performance Limit Reasons. */
1704	#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1705
1706	/** X2APIC MSR range start. */
1707	#define MSR_IA32_X2APIC_START 0x800
1708	/** X2APIC MSR - APIC ID Register. */
1709	#define MSR_IA32_X2APIC_ID 0x802
1710	/** X2APIC MSR - APIC Version Register. */
1711	#define MSR_IA32_X2APIC_VERSION 0x803
1712	/** X2APIC MSR - Task Priority Register. */
1713	#define MSR_IA32_X2APIC_TPR 0x808
1714	/** X2APIC MSR - Processor Priority register. */
1715	#define MSR_IA32_X2APIC_PPR 0x80A
1716	/** X2APIC MSR - End Of Interrupt register. */
1717	#define MSR_IA32_X2APIC_EOI 0x80B
1718	/** X2APIC MSR - Logical Destination Register. */
1719	#define MSR_IA32_X2APIC_LDR 0x80D
1720	/** X2APIC MSR - Spurious Interrupt Vector Register. */
1721	#define MSR_IA32_X2APIC_SVR 0x80F
1722	/** X2APIC MSR - In-service Register (bits 31:0). */
1723	#define MSR_IA32_X2APIC_ISR0 0x810
1724	/** X2APIC MSR - In-service Register (bits 63:32). */
1725	#define MSR_IA32_X2APIC_ISR1 0x811
1726	/** X2APIC MSR - In-service Register (bits 95:64). */
1727	#define MSR_IA32_X2APIC_ISR2 0x812
1728	/** X2APIC MSR - In-service Register (bits 127:96). */
1729	#define MSR_IA32_X2APIC_ISR3 0x813
1730	/** X2APIC MSR - In-service Register (bits 159:128). */
1731	#define MSR_IA32_X2APIC_ISR4 0x814
1732	/** X2APIC MSR - In-service Register (bits 191:160). */
1733	#define MSR_IA32_X2APIC_ISR5 0x815
1734	/** X2APIC MSR - In-service Register (bits 223:192). */
1735	#define MSR_IA32_X2APIC_ISR6 0x816
1736	/** X2APIC MSR - In-service Register (bits 255:224). */
1737	#define MSR_IA32_X2APIC_ISR7 0x817
1738	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1739	#define MSR_IA32_X2APIC_TMR0 0x818
1740	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1741	#define MSR_IA32_X2APIC_TMR1 0x819
1742	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1743	#define MSR_IA32_X2APIC_TMR2 0x81A
1744	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1745	#define MSR_IA32_X2APIC_TMR3 0x81B
1746	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1747	#define MSR_IA32_X2APIC_TMR4 0x81C
1748	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1749	#define MSR_IA32_X2APIC_TMR5 0x81D
1750	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1751	#define MSR_IA32_X2APIC_TMR6 0x81E
1752	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1753	#define MSR_IA32_X2APIC_TMR7 0x81F
1754	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1755	#define MSR_IA32_X2APIC_IRR0 0x820
1756	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1757	#define MSR_IA32_X2APIC_IRR1 0x821
1758	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1759	#define MSR_IA32_X2APIC_IRR2 0x822
1760	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1761	#define MSR_IA32_X2APIC_IRR3 0x823
1762	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1763	#define MSR_IA32_X2APIC_IRR4 0x824
1764	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1765	#define MSR_IA32_X2APIC_IRR5 0x825
1766	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1767	#define MSR_IA32_X2APIC_IRR6 0x826
1768	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1769	#define MSR_IA32_X2APIC_IRR7 0x827
1770	/** X2APIC MSR - Error Status Register. */
1771	#define MSR_IA32_X2APIC_ESR 0x828
1772	/** X2APIC MSR - LVT CMCI Register. */
1773	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1774	/** X2APIC MSR - Interrupt Command Register. */
1775	#define MSR_IA32_X2APIC_ICR 0x830
1776	/** X2APIC MSR - LVT Timer Register. */
1777	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1778	/** X2APIC MSR - LVT Thermal Sensor Register. */
1779	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1780	/** X2APIC MSR - LVT Performance Counter Register. */
1781	#define MSR_IA32_X2APIC_LVT_PERF 0x834
1782	/** X2APIC MSR - LVT LINT0 Register. */
1783	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1784	/** X2APIC MSR - LVT LINT1 Register. */
1785	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1786	/** X2APIC MSR - LVT Error Register . */
1787	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1788	/** X2APIC MSR - Timer Initial Count Register. */
1789	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1790	/** X2APIC MSR - Timer Current Count Register. */
1791	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1792	/** X2APIC MSR - Timer Divide Configuration Register. */
1793	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1794	/** X2APIC MSR - Self IPI. */
1795	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1796	/** X2APIC MSR range end. */
1797	#define MSR_IA32_X2APIC_END 0x8FF
1798	/** X2APIC MSR - LVT start range. */
1799	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1800	/** X2APIC MSR - LVT end range (inclusive). */
1801	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1802
1803	/** K6 EFER - Extended Feature Enable Register. */
1804	#define MSR_K6_EFER UINT32_C(0xc0000080)
1805	/** @todo document EFER */
1806	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1807	#define MSR_K6_EFER_SCE RT_BIT_32(0)
1808	/** Bit 8 - LME - Long mode enabled. (R/W) */
1809	#define MSR_K6_EFER_LME RT_BIT_32(8)
1810	#define MSR_K6_EFER_BIT_LME 8 /*< Bit number of MSR_K6_EFER_LME /
1811	/** Bit 10 - LMA - Long mode active. (R) */
1812	#define MSR_K6_EFER_LMA RT_BIT_32(10)
1813	#define MSR_K6_EFER_BIT_LMA 10 /*< Bit number of MSR_K6_EFER_LMA /
1814	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1815	#define MSR_K6_EFER_NXE RT_BIT_32(11)
1816	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
1817	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1818	#define MSR_K6_EFER_SVME RT_BIT_32(12)
1819	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1820	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1821	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1822	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1823	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1824	#define MSR_K6_EFER_TCE RT_BIT_32(15)
1825	/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
1826	#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
1827
1828	/** K6 STAR - SYSCALL/RET targets. */
1829	#define MSR_K6_STAR UINT32_C(0xc0000081)
1830	/** Shift value for getting the SYSRET CS and SS value. */
1831	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1832	/** Shift value for getting the SYSCALL CS and SS value. */
1833	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1834	/** Selector mask for use after shifting. */
1835	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1836	/** The mask which give the SYSCALL EIP. */
1837	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1838	/** K6 WHCR - Write Handling Control Register. */
1839	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1840	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1841	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1842	/** K6 PSOR - Processor State Observability Register. */
1843	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1844	/** K6 PFIR - Page Flush/Invalidate Register. */
1845	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1846
1847	/** Performance counter MSRs. (AMD only) */
1848	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1849	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1850	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1851	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1852	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1853	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1854	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1855	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1856
1857	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1858	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1859	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1860	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1861	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1862	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1863	/** K8 FS.base - The 64-bit base FS register. */
1864	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1865	/** K8 GS.base - The 64-bit base GS register. */
1866	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1867	/** K8 KernelGSbase - Used with SWAPGS. */
1868	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1869	/** K8 TSC_AUX - Used with RDTSCP. */
1870	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1871	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1872	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1873	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1874	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1875	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1876	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1877	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1878	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1879
1880	/** SMM MSRs. */
1881	#define MSR_K7_SMBASE UINT32_C(0xc0010111)
1882	#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
1883	#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
1884
1885	/** North bridge config? See BIOS & Kernel dev guides for
1886	* details. */
1887	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1888
1889	/** Hypertransport interrupt pending register.
1890	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1891	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1892
1893	/** SVM Control. */
1894	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1895	/** Disables HDT (Hardware Debug Tool) and certain internal debug
1896	* features. */
1897	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1898	/** If set, non-intercepted INIT signals are converted to \#SX
1899	* exceptions. */
1900	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1901	/** Disables A20 masking. */
1902	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1903	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1904	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1905	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1906	* clear, EFER.SVME can be written normally. */
1907	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1908
1909	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1910	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1911	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1912	* host state during world switch. */
1913	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1914
1915	/** Virtualized speculation control for AMD processors.
1916	*
1917	* Unified interface among different CPU generations.
1918	* The VMM will set any architectural MSRs based on the CPU.
1919	* See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
1920	* (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
1921	#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
1922	/** Speculative Store Bypass Disable. */
1923	# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
1924
1925	/** @} */
1926
1927
1928	/** @name Page Table / Directory / Directory Pointers / L4.
1929	* @{
1930	*/
1931
1932	/** Page table/directory entry as an unsigned integer. */
1933	typedef uint32_t X86PGUINT;
1934	/** Pointer to a page table/directory table entry as an unsigned integer. */
1935	typedef X86PGUINT *PX86PGUINT;
1936	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1937	typedef X86PGUINT const *PCX86PGUINT;
1938
1939	/** Number of entries in a 32-bit PT/PD. */
1940	#define X86_PG_ENTRIES 1024
1941
1942
1943	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1944	typedef uint64_t X86PGPAEUINT;
1945	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1946	typedef X86PGPAEUINT *PX86PGPAEUINT;
1947	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1948	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1949
1950	/** Number of entries in a PAE PT/PD. */
1951	#define X86_PG_PAE_ENTRIES 512
1952	/** Number of entries in a PAE PDPT. */
1953	#define X86_PG_PAE_PDPE_ENTRIES 4
1954
1955	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1956	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1957	/** Number of entries in an AMD64 PDPT.
1958	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1959	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1960
1961	/** The size of a default page. */
1962	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1963	/** The page shift of a default page. */
1964	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1965	/** The default page offset mask. */
1966	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1967	/** The default page base mask for virtual addresses. */
1968	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1969	/** The default page base mask for virtual addresses - 32bit version. */
1970	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1971
1972	/** The size of a 4KB page. */
1973	#define X86_PAGE_4K_SIZE _4K
1974	/** The page shift of a 4KB page. */
1975	#define X86_PAGE_4K_SHIFT 12
1976	/** The 4KB page offset mask. */
1977	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1978	/** The 4KB page base mask for virtual addresses. */
1979	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1980	/** The 4KB page base mask for virtual addresses - 32bit version. */
1981	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1982
1983	/** The size of a 2MB page. */
1984	#define X86_PAGE_2M_SIZE _2M
1985	/** The page shift of a 2MB page. */
1986	#define X86_PAGE_2M_SHIFT 21
1987	/** The 2MB page offset mask. */
1988	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1989	/** The 2MB page base mask for virtual addresses. */
1990	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1991	/** The 2MB page base mask for virtual addresses - 32bit version. */
1992	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1993
1994	/** The size of a 4MB page. */
1995	#define X86_PAGE_4M_SIZE _4M
1996	/** The page shift of a 4MB page. */
1997	#define X86_PAGE_4M_SHIFT 22
1998	/** The 4MB page offset mask. */
1999	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
2000	/** The 4MB page base mask for virtual addresses. */
2001	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
2002	/** The 4MB page base mask for virtual addresses - 32bit version. */
2003	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
2004
2005	/** The size of a 1GB page. */
2006	#define X86_PAGE_1G_SIZE _1G
2007	/** The page shift of a 1GB page. */
2008	#define X86_PAGE_1G_SHIFT 30
2009	/** The 1GB page offset mask. */
2010	#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
2011	/** The 1GB page base mask for virtual addresses. */
2012	#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
2013
2014	/**
2015	* Check if the given address is canonical.
2016	*/
2017	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
2018
2019	/**
2020	* Gets the page base mask given the page shift.
2021	*/
2022	#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
2023
2024	/**
2025	* Gets the page offset mask given the page shift.
2026	*/
2027	#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
2028
2029
2030	/** @name Page Table Entry
2031	* @{
2032	*/
2033	/** Bit 0 - P - Present bit. */
2034	#define X86_PTE_BIT_P 0
2035	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2036	#define X86_PTE_BIT_RW 1
2037	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2038	#define X86_PTE_BIT_US 2
2039	/** Bit 3 - PWT - Page level write thru bit. */
2040	#define X86_PTE_BIT_PWT 3
2041	/** Bit 4 - PCD - Page level cache disable bit. */
2042	#define X86_PTE_BIT_PCD 4
2043	/** Bit 5 - A - Access bit. */
2044	#define X86_PTE_BIT_A 5
2045	/** Bit 6 - D - Dirty bit. */
2046	#define X86_PTE_BIT_D 6
2047	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2048	#define X86_PTE_BIT_PAT 7
2049	/** Bit 8 - G - Global flag. */
2050	#define X86_PTE_BIT_G 8
2051	/** Bits 63 - NX - PAE/LM - No execution flag. */
2052	#define X86_PTE_PAE_BIT_NX 63
2053
2054	/** Bit 0 - P - Present bit mask. */
2055	#define X86_PTE_P RT_BIT_32(0)
2056	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2057	#define X86_PTE_RW RT_BIT_32(1)
2058	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2059	#define X86_PTE_US RT_BIT_32(2)
2060	/** Bit 3 - PWT - Page level write thru bit mask. */
2061	#define X86_PTE_PWT RT_BIT_32(3)
2062	/** Bit 4 - PCD - Page level cache disable bit mask. */
2063	#define X86_PTE_PCD RT_BIT_32(4)
2064	/** Bit 5 - A - Access bit mask. */
2065	#define X86_PTE_A RT_BIT_32(5)
2066	/** Bit 6 - D - Dirty bit mask. */
2067	#define X86_PTE_D RT_BIT_32(6)
2068	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2069	#define X86_PTE_PAT RT_BIT_32(7)
2070	/** Bit 8 - G - Global bit mask. */
2071	#define X86_PTE_G RT_BIT_32(8)
2072
2073	/** Bits 9-11 - - Available for use to system software. */
2074	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2075	/** Bits 12-31 - - Physical Page number of the next level. */
2076	#define X86_PTE_PG_MASK ( 0xfffff000 )
2077
2078	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2079	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2080	/** Bits 63 - NX - PAE/LM - No execution flag. */
2081	#define X86_PTE_PAE_NX RT_BIT_64(63)
2082	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2083	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2084	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2085	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2086	/** No bits - - LM - MBZ bits when NX is active. */
2087	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2088	/** Bits 63 - - LM - MBZ bits when no NX. */
2089	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2090
2091	/**
2092	* Page table entry.
2093	*/
2094	typedef struct X86PTEBITS
2095	{
2096	/** Flags whether(=1) or not the page is present. */
2097	uint32_t u1Present : 1;
2098	/** Read(=0) / Write(=1) flag. */
2099	uint32_t u1Write : 1;
2100	/** User(=1) / Supervisor (=0) flag. */
2101	uint32_t u1User : 1;
2102	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2103	uint32_t u1WriteThru : 1;
2104	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2105	uint32_t u1CacheDisable : 1;
2106	/** Accessed flag.
2107	* Indicates that the page have been read or written to. */
2108	uint32_t u1Accessed : 1;
2109	/** Dirty flag.
2110	* Indicates that the page has been written to. */
2111	uint32_t u1Dirty : 1;
2112	/** Reserved / If PAT enabled, bit 2 of the index. */
2113	uint32_t u1PAT : 1;
2114	/** Global flag. (Ignored in all but final level.) */
2115	uint32_t u1Global : 1;
2116	/** Available for use to system software. */
2117	uint32_t u3Available : 3;
2118	/** Physical Page number of the next level. */
2119	uint32_t u20PageNo : 20;
2120	} X86PTEBITS;
2121	#ifndef VBOX_FOR_DTRACE_LIB
2122	AssertCompileSize(X86PTEBITS, 4);
2123	#endif
2124	/** Pointer to a page table entry. */
2125	typedef X86PTEBITS *PX86PTEBITS;
2126	/** Pointer to a const page table entry. */
2127	typedef const X86PTEBITS *PCX86PTEBITS;
2128
2129	/**
2130	* Page table entry.
2131	*/
2132	typedef union X86PTE
2133	{
2134	/** Unsigned integer view */
2135	X86PGUINT u;
2136	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2137	/** Bit field view. */
2138	X86PTEBITS n;
2139	#endif
2140	/** 32-bit view. */
2141	uint32_t au32[1];
2142	/** 16-bit view. */
2143	uint16_t au16[2];
2144	/** 8-bit view. */
2145	uint8_t au8[4];
2146	} X86PTE;
2147	#ifndef VBOX_FOR_DTRACE_LIB
2148	AssertCompileSize(X86PTE, 4);
2149	#endif
2150	/** Pointer to a page table entry. */
2151	typedef X86PTE *PX86PTE;
2152	/** Pointer to a const page table entry. */
2153	typedef const X86PTE *PCX86PTE;
2154
2155
2156	/**
2157	* PAE page table entry.
2158	*/
2159	typedef struct X86PTEPAEBITS
2160	{
2161	/** Flags whether(=1) or not the page is present. */
2162	uint32_t u1Present : 1;
2163	/** Read(=0) / Write(=1) flag. */
2164	uint32_t u1Write : 1;
2165	/** User(=1) / Supervisor(=0) flag. */
2166	uint32_t u1User : 1;
2167	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2168	uint32_t u1WriteThru : 1;
2169	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2170	uint32_t u1CacheDisable : 1;
2171	/** Accessed flag.
2172	* Indicates that the page have been read or written to. */
2173	uint32_t u1Accessed : 1;
2174	/** Dirty flag.
2175	* Indicates that the page has been written to. */
2176	uint32_t u1Dirty : 1;
2177	/** Reserved / If PAT enabled, bit 2 of the index. */
2178	uint32_t u1PAT : 1;
2179	/** Global flag. (Ignored in all but final level.) */
2180	uint32_t u1Global : 1;
2181	/** Available for use to system software. */
2182	uint32_t u3Available : 3;
2183	/** Physical Page number of the next level - Low Part. Don't use this. */
2184	uint32_t u20PageNoLow : 20;
2185	/** Physical Page number of the next level - High Part. Don't use this. */
2186	uint32_t u20PageNoHigh : 20;
2187	/** MBZ bits */
2188	uint32_t u11Reserved : 11;
2189	/** No Execute flag. */
2190	uint32_t u1NoExecute : 1;
2191	} X86PTEPAEBITS;
2192	#ifndef VBOX_FOR_DTRACE_LIB
2193	AssertCompileSize(X86PTEPAEBITS, 8);
2194	#endif
2195	/** Pointer to a page table entry. */
2196	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2197	/** Pointer to a page table entry. */
2198	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2199
2200	/**
2201	* PAE Page table entry.
2202	*/
2203	typedef union X86PTEPAE
2204	{
2205	/** Unsigned integer view */
2206	X86PGPAEUINT u;
2207	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2208	/** Bit field view. */
2209	X86PTEPAEBITS n;
2210	#endif
2211	/** 32-bit view. */
2212	uint32_t au32[2];
2213	/** 16-bit view. */
2214	uint16_t au16[4];
2215	/** 8-bit view. */
2216	uint8_t au8[8];
2217	} X86PTEPAE;
2218	#ifndef VBOX_FOR_DTRACE_LIB
2219	AssertCompileSize(X86PTEPAE, 8);
2220	#endif
2221	/** Pointer to a PAE page table entry. */
2222	typedef X86PTEPAE *PX86PTEPAE;
2223	/** Pointer to a const PAE page table entry. */
2224	typedef const X86PTEPAE *PCX86PTEPAE;
2225	/** @} */
2226
2227	/**
2228	* Page table.
2229	*/
2230	typedef struct X86PT
2231	{
2232	/** PTE Array. */
2233	X86PTE a[X86_PG_ENTRIES];
2234	} X86PT;
2235	#ifndef VBOX_FOR_DTRACE_LIB
2236	AssertCompileSize(X86PT, 4096);
2237	#endif
2238	/** Pointer to a page table. */
2239	typedef X86PT *PX86PT;
2240	/** Pointer to a const page table. */
2241	typedef const X86PT *PCX86PT;
2242
2243	/** The page shift to get the PT index. */
2244	#define X86_PT_SHIFT 12
2245	/** The PT index mask (apply to a shifted page address). */
2246	#define X86_PT_MASK 0x3ff
2247
2248
2249	/**
2250	* Page directory.
2251	*/
2252	typedef struct X86PTPAE
2253	{
2254	/** PTE Array. */
2255	X86PTEPAE a[X86_PG_PAE_ENTRIES];
2256	} X86PTPAE;
2257	#ifndef VBOX_FOR_DTRACE_LIB
2258	AssertCompileSize(X86PTPAE, 4096);
2259	#endif
2260	/** Pointer to a page table. */
2261	typedef X86PTPAE *PX86PTPAE;
2262	/** Pointer to a const page table. */
2263	typedef const X86PTPAE *PCX86PTPAE;
2264
2265	/** The page shift to get the PA PTE index. */
2266	#define X86_PT_PAE_SHIFT 12
2267	/** The PAE PT index mask (apply to a shifted page address). */
2268	#define X86_PT_PAE_MASK 0x1ff
2269
2270
2271	/** @name 4KB Page Directory Entry
2272	* @{
2273	*/
2274	/** Bit 0 - P - Present bit. */
2275	#define X86_PDE_P RT_BIT_32(0)
2276	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2277	#define X86_PDE_RW RT_BIT_32(1)
2278	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2279	#define X86_PDE_US RT_BIT_32(2)
2280	/** Bit 3 - PWT - Page level write thru bit. */
2281	#define X86_PDE_PWT RT_BIT_32(3)
2282	/** Bit 4 - PCD - Page level cache disable bit. */
2283	#define X86_PDE_PCD RT_BIT_32(4)
2284	/** Bit 5 - A - Access bit. */
2285	#define X86_PDE_A RT_BIT_32(5)
2286	/** Bit 7 - PS - Page size attribute.
2287	* Clear mean 4KB pages, set means large pages (2/4MB). */
2288	#define X86_PDE_PS RT_BIT_32(7)
2289	/** Bits 9-11 - - Available for use to system software. */
2290	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2291	/** Bits 12-31 - - Physical Page number of the next level. */
2292	#define X86_PDE_PG_MASK ( 0xfffff000 )
2293
2294	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2295	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2296	/** Bits 63 - NX - PAE/LM - No execution flag. */
2297	#define X86_PDE_PAE_NX RT_BIT_64(63)
2298	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2299	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2300	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2301	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2302	/** Bit 7 - - LM - MBZ bits when NX is active. */
2303	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2304	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2305	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2306
2307	/**
2308	* Page directory entry.
2309	*/
2310	typedef struct X86PDEBITS
2311	{
2312	/** Flags whether(=1) or not the page is present. */
2313	uint32_t u1Present : 1;
2314	/** Read(=0) / Write(=1) flag. */
2315	uint32_t u1Write : 1;
2316	/** User(=1) / Supervisor (=0) flag. */
2317	uint32_t u1User : 1;
2318	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2319	uint32_t u1WriteThru : 1;
2320	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2321	uint32_t u1CacheDisable : 1;
2322	/** Accessed flag.
2323	* Indicates that the page has been read or written to. */
2324	uint32_t u1Accessed : 1;
2325	/** Reserved / Ignored (dirty bit). */
2326	uint32_t u1Reserved0 : 1;
2327	/** Size bit if PSE is enabled - in any event it's 0. */
2328	uint32_t u1Size : 1;
2329	/** Reserved / Ignored (global bit). */
2330	uint32_t u1Reserved1 : 1;
2331	/** Available for use to system software. */
2332	uint32_t u3Available : 3;
2333	/** Physical Page number of the next level. */
2334	uint32_t u20PageNo : 20;
2335	} X86PDEBITS;
2336	#ifndef VBOX_FOR_DTRACE_LIB
2337	AssertCompileSize(X86PDEBITS, 4);
2338	#endif
2339	/** Pointer to a page directory entry. */
2340	typedef X86PDEBITS *PX86PDEBITS;
2341	/** Pointer to a const page directory entry. */
2342	typedef const X86PDEBITS *PCX86PDEBITS;
2343
2344
2345	/**
2346	* PAE page directory entry.
2347	*/
2348	typedef struct X86PDEPAEBITS
2349	{
2350	/** Flags whether(=1) or not the page is present. */
2351	uint32_t u1Present : 1;
2352	/** Read(=0) / Write(=1) flag. */
2353	uint32_t u1Write : 1;
2354	/** User(=1) / Supervisor (=0) flag. */
2355	uint32_t u1User : 1;
2356	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2357	uint32_t u1WriteThru : 1;
2358	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2359	uint32_t u1CacheDisable : 1;
2360	/** Accessed flag.
2361	* Indicates that the page has been read or written to. */
2362	uint32_t u1Accessed : 1;
2363	/** Reserved / Ignored (dirty bit). */
2364	uint32_t u1Reserved0 : 1;
2365	/** Size bit if PSE is enabled - in any event it's 0. */
2366	uint32_t u1Size : 1;
2367	/** Reserved / Ignored (global bit). / */
2368	uint32_t u1Reserved1 : 1;
2369	/** Available for use to system software. */
2370	uint32_t u3Available : 3;
2371	/** Physical Page number of the next level - Low Part. Don't use! */
2372	uint32_t u20PageNoLow : 20;
2373	/** Physical Page number of the next level - High Part. Don't use! */
2374	uint32_t u20PageNoHigh : 20;
2375	/** MBZ bits */
2376	uint32_t u11Reserved : 11;
2377	/** No Execute flag. */
2378	uint32_t u1NoExecute : 1;
2379	} X86PDEPAEBITS;
2380	#ifndef VBOX_FOR_DTRACE_LIB
2381	AssertCompileSize(X86PDEPAEBITS, 8);
2382	#endif
2383	/** Pointer to a page directory entry. */
2384	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2385	/** Pointer to a const page directory entry. */
2386	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2387
2388	/** @} */
2389
2390
2391	/** @name 2/4MB Page Directory Entry
2392	* @{
2393	*/
2394	/** Bit 0 - P - Present bit. */
2395	#define X86_PDE4M_P RT_BIT_32(0)
2396	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2397	#define X86_PDE4M_RW RT_BIT_32(1)
2398	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2399	#define X86_PDE4M_US RT_BIT_32(2)
2400	/** Bit 3 - PWT - Page level write thru bit. */
2401	#define X86_PDE4M_PWT RT_BIT_32(3)
2402	/** Bit 4 - PCD - Page level cache disable bit. */
2403	#define X86_PDE4M_PCD RT_BIT_32(4)
2404	/** Bit 5 - A - Access bit. */
2405	#define X86_PDE4M_A RT_BIT_32(5)
2406	/** Bit 6 - D - Dirty bit. */
2407	#define X86_PDE4M_D RT_BIT_32(6)
2408	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2409	#define X86_PDE4M_PS RT_BIT_32(7)
2410	/** Bit 8 - G - Global flag. */
2411	#define X86_PDE4M_G RT_BIT_32(8)
2412	/** Bits 9-11 - AVL - Available for use to system software. */
2413	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2414	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2415	#define X86_PDE4M_PAT RT_BIT_32(12)
2416	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2417	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2418	/** Bits 22-31 - - Physical Page number. */
2419	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2420	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2421	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2422	/** The number of bits to the high part of the page number. */
2423	#define X86_PDE4M_PG_HIGH_SHIFT 19
2424	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2425	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2426
2427	/** Bits 21-51 - - PAE/LM - Physical Page number.
2428	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2429	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2430	/** Bits 63 - NX - PAE/LM - No execution flag. */
2431	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2432	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2433	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2434	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2435	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2436	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2437	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2438	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2439	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2440
2441	/**
2442	* 4MB page directory entry.
2443	*/
2444	typedef struct X86PDE4MBITS
2445	{
2446	/** Flags whether(=1) or not the page is present. */
2447	uint32_t u1Present : 1;
2448	/** Read(=0) / Write(=1) flag. */
2449	uint32_t u1Write : 1;
2450	/** User(=1) / Supervisor (=0) flag. */
2451	uint32_t u1User : 1;
2452	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2453	uint32_t u1WriteThru : 1;
2454	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2455	uint32_t u1CacheDisable : 1;
2456	/** Accessed flag.
2457	* Indicates that the page have been read or written to. */
2458	uint32_t u1Accessed : 1;
2459	/** Dirty flag.
2460	* Indicates that the page has been written to. */
2461	uint32_t u1Dirty : 1;
2462	/** Page size flag - always 1 for 4MB entries. */
2463	uint32_t u1Size : 1;
2464	/** Global flag. */
2465	uint32_t u1Global : 1;
2466	/** Available for use to system software. */
2467	uint32_t u3Available : 3;
2468	/** Reserved / If PAT enabled, bit 2 of the index. */
2469	uint32_t u1PAT : 1;
2470	/** Bits 32-39 of the page number on AMD64.
2471	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2472	uint32_t u8PageNoHigh : 8;
2473	/** Reserved. */
2474	uint32_t u1Reserved : 1;
2475	/** Physical Page number of the page. */
2476	uint32_t u10PageNo : 10;
2477	} X86PDE4MBITS;
2478	#ifndef VBOX_FOR_DTRACE_LIB
2479	AssertCompileSize(X86PDE4MBITS, 4);
2480	#endif
2481	/** Pointer to a page table entry. */
2482	typedef X86PDE4MBITS *PX86PDE4MBITS;
2483	/** Pointer to a const page table entry. */
2484	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2485
2486
2487	/**
2488	* 2MB PAE page directory entry.
2489	*/
2490	typedef struct X86PDE2MPAEBITS
2491	{
2492	/** Flags whether(=1) or not the page is present. */
2493	uint32_t u1Present : 1;
2494	/** Read(=0) / Write(=1) flag. */
2495	uint32_t u1Write : 1;
2496	/** User(=1) / Supervisor(=0) flag. */
2497	uint32_t u1User : 1;
2498	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2499	uint32_t u1WriteThru : 1;
2500	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2501	uint32_t u1CacheDisable : 1;
2502	/** Accessed flag.
2503	* Indicates that the page have been read or written to. */
2504	uint32_t u1Accessed : 1;
2505	/** Dirty flag.
2506	* Indicates that the page has been written to. */
2507	uint32_t u1Dirty : 1;
2508	/** Page size flag - always 1 for 2MB entries. */
2509	uint32_t u1Size : 1;
2510	/** Global flag. */
2511	uint32_t u1Global : 1;
2512	/** Available for use to system software. */
2513	uint32_t u3Available : 3;
2514	/** Reserved / If PAT enabled, bit 2 of the index. */
2515	uint32_t u1PAT : 1;
2516	/** Reserved. */
2517	uint32_t u9Reserved : 9;
2518	/** Physical Page number of the next level - Low part. Don't use! */
2519	uint32_t u10PageNoLow : 10;
2520	/** Physical Page number of the next level - High part. Don't use! */
2521	uint32_t u20PageNoHigh : 20;
2522	/** MBZ bits */
2523	uint32_t u11Reserved : 11;
2524	/** No Execute flag. */
2525	uint32_t u1NoExecute : 1;
2526	} X86PDE2MPAEBITS;
2527	#ifndef VBOX_FOR_DTRACE_LIB
2528	AssertCompileSize(X86PDE2MPAEBITS, 8);
2529	#endif
2530	/** Pointer to a 2MB PAE page table entry. */
2531	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2532	/** Pointer to a 2MB PAE page table entry. */
2533	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2534
2535	/** @} */
2536
2537	/**
2538	* Page directory entry.
2539	*/
2540	typedef union X86PDE
2541	{
2542	/** Unsigned integer view. */
2543	X86PGUINT u;
2544	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2545	/** Normal view. */
2546	X86PDEBITS n;
2547	/** 4MB view (big). */
2548	X86PDE4MBITS b;
2549	#endif
2550	/** 8 bit unsigned integer view. */
2551	uint8_t au8[4];
2552	/** 16 bit unsigned integer view. */
2553	uint16_t au16[2];
2554	/** 32 bit unsigned integer view. */
2555	uint32_t au32[1];
2556	} X86PDE;
2557	#ifndef VBOX_FOR_DTRACE_LIB
2558	AssertCompileSize(X86PDE, 4);
2559	#endif
2560	/** Pointer to a page directory entry. */
2561	typedef X86PDE *PX86PDE;
2562	/** Pointer to a const page directory entry. */
2563	typedef const X86PDE *PCX86PDE;
2564
2565	/**
2566	* PAE page directory entry.
2567	*/
2568	typedef union X86PDEPAE
2569	{
2570	/** Unsigned integer view. */
2571	X86PGPAEUINT u;
2572	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2573	/** Normal view. */
2574	X86PDEPAEBITS n;
2575	/** 2MB page view (big). */
2576	X86PDE2MPAEBITS b;
2577	#endif
2578	/** 8 bit unsigned integer view. */
2579	uint8_t au8[8];
2580	/** 16 bit unsigned integer view. */
2581	uint16_t au16[4];
2582	/** 32 bit unsigned integer view. */
2583	uint32_t au32[2];
2584	} X86PDEPAE;
2585	#ifndef VBOX_FOR_DTRACE_LIB
2586	AssertCompileSize(X86PDEPAE, 8);
2587	#endif
2588	/** Pointer to a page directory entry. */
2589	typedef X86PDEPAE *PX86PDEPAE;
2590	/** Pointer to a const page directory entry. */
2591	typedef const X86PDEPAE *PCX86PDEPAE;
2592
2593	/**
2594	* Page directory.
2595	*/
2596	typedef struct X86PD
2597	{
2598	/** PDE Array. */
2599	X86PDE a[X86_PG_ENTRIES];
2600	} X86PD;
2601	#ifndef VBOX_FOR_DTRACE_LIB
2602	AssertCompileSize(X86PD, 4096);
2603	#endif
2604	/** Pointer to a page directory. */
2605	typedef X86PD *PX86PD;
2606	/** Pointer to a const page directory. */
2607	typedef const X86PD *PCX86PD;
2608
2609	/** The page shift to get the PD index. */
2610	#define X86_PD_SHIFT 22
2611	/** The PD index mask (apply to a shifted page address). */
2612	#define X86_PD_MASK 0x3ff
2613
2614
2615	/**
2616	* PAE page directory.
2617	*/
2618	typedef struct X86PDPAE
2619	{
2620	/** PDE Array. */
2621	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2622	} X86PDPAE;
2623	#ifndef VBOX_FOR_DTRACE_LIB
2624	AssertCompileSize(X86PDPAE, 4096);
2625	#endif
2626	/** Pointer to a PAE page directory. */
2627	typedef X86PDPAE *PX86PDPAE;
2628	/** Pointer to a const PAE page directory. */
2629	typedef const X86PDPAE *PCX86PDPAE;
2630
2631	/** The page shift to get the PAE PD index. */
2632	#define X86_PD_PAE_SHIFT 21
2633	/** The PAE PD index mask (apply to a shifted page address). */
2634	#define X86_PD_PAE_MASK 0x1ff
2635
2636
2637	/** @name Page Directory Pointer Table Entry (PAE)
2638	* @{
2639	*/
2640	/** Bit 0 - P - Present bit. */
2641	#define X86_PDPE_P RT_BIT_32(0)
2642	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2643	#define X86_PDPE_RW RT_BIT_32(1)
2644	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2645	#define X86_PDPE_US RT_BIT_32(2)
2646	/** Bit 3 - PWT - Page level write thru bit. */
2647	#define X86_PDPE_PWT RT_BIT_32(3)
2648	/** Bit 4 - PCD - Page level cache disable bit. */
2649	#define X86_PDPE_PCD RT_BIT_32(4)
2650	/** Bit 5 - A - Access bit. Long Mode only. */
2651	#define X86_PDPE_A RT_BIT_32(5)
2652	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2653	#define X86_PDPE_LM_PS RT_BIT_32(7)
2654	/** Bits 9-11 - - Available for use to system software. */
2655	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2656	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2657	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2658	/** Bits 30-51 - - PG - Physical address of the 1GB page referenced by this entry. */
2659	#define X86_PDPE1G_PG_MASK UINT64_C(0x000fffffc0000000)
2660	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2661	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2662	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2663	#define X86_PDPE_LM_NX RT_BIT_64(63)
2664	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2665	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2666	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2667	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2668	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2669	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2670	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2671	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2672
2673
2674	/**
2675	* Page directory pointer table entry.
2676	*/
2677	typedef struct X86PDPEBITS
2678	{
2679	/** Flags whether(=1) or not the page is present. */
2680	uint32_t u1Present : 1;
2681	/** Chunk of reserved bits. */
2682	uint32_t u2Reserved : 2;
2683	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2684	uint32_t u1WriteThru : 1;
2685	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2686	uint32_t u1CacheDisable : 1;
2687	/** Chunk of reserved bits. */
2688	uint32_t u4Reserved : 4;
2689	/** Available for use to system software. */
2690	uint32_t u3Available : 3;
2691	/** Physical Page number of the next level - Low Part. Don't use! */
2692	uint32_t u20PageNoLow : 20;
2693	/** Physical Page number of the next level - High Part. Don't use! */
2694	uint32_t u20PageNoHigh : 20;
2695	/** MBZ bits */
2696	uint32_t u12Reserved : 12;
2697	} X86PDPEBITS;
2698	#ifndef VBOX_FOR_DTRACE_LIB
2699	AssertCompileSize(X86PDPEBITS, 8);
2700	#endif
2701	/** Pointer to a page directory pointer table entry. */
2702	typedef X86PDPEBITS *PX86PTPEBITS;
2703	/** Pointer to a const page directory pointer table entry. */
2704	typedef const X86PDPEBITS *PCX86PTPEBITS;
2705
2706	/**
2707	* Page directory pointer table entry. AMD64 version
2708	*/
2709	typedef struct X86PDPEAMD64BITS
2710	{
2711	/** Flags whether(=1) or not the page is present. */
2712	uint32_t u1Present : 1;
2713	/** Read(=0) / Write(=1) flag. */
2714	uint32_t u1Write : 1;
2715	/** User(=1) / Supervisor (=0) flag. */
2716	uint32_t u1User : 1;
2717	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2718	uint32_t u1WriteThru : 1;
2719	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2720	uint32_t u1CacheDisable : 1;
2721	/** Accessed flag.
2722	* Indicates that the page have been read or written to. */
2723	uint32_t u1Accessed : 1;
2724	/** Chunk of reserved bits. */
2725	uint32_t u3Reserved : 3;
2726	/** Available for use to system software. */
2727	uint32_t u3Available : 3;
2728	/** Physical Page number of the next level - Low Part. Don't use! */
2729	uint32_t u20PageNoLow : 20;
2730	/** Physical Page number of the next level - High Part. Don't use! */
2731	uint32_t u20PageNoHigh : 20;
2732	/** MBZ bits */
2733	uint32_t u11Reserved : 11;
2734	/** No Execute flag. */
2735	uint32_t u1NoExecute : 1;
2736	} X86PDPEAMD64BITS;
2737	#ifndef VBOX_FOR_DTRACE_LIB
2738	AssertCompileSize(X86PDPEAMD64BITS, 8);
2739	#endif
2740	/** Pointer to a page directory pointer table entry. */
2741	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2742	/** Pointer to a const page directory pointer table entry. */
2743	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2744
2745	/**
2746	* Page directory pointer table entry for 1GB page. (AMD64 only)
2747	*/
2748	typedef struct X86PDPE1GB
2749	{
2750	/** 0: Flags whether(=1) or not the page is present. */
2751	uint32_t u1Present : 1;
2752	/** 1: Read(=0) / Write(=1) flag. */
2753	uint32_t u1Write : 1;
2754	/** 2: User(=1) / Supervisor (=0) flag. */
2755	uint32_t u1User : 1;
2756	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2757	uint32_t u1WriteThru : 1;
2758	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2759	uint32_t u1CacheDisable : 1;
2760	/** 5: Accessed flag.
2761	* Indicates that the page have been read or written to. */
2762	uint32_t u1Accessed : 1;
2763	/** 6: Dirty flag for 1GB pages. */
2764	uint32_t u1Dirty : 1;
2765	/** 7: Indicates 1GB page if set. */
2766	uint32_t u1Size : 1;
2767	/** 8: Global 1GB page. */
2768	uint32_t u1Global: 1;
2769	/** 9-11: Available for use to system software. */
2770	uint32_t u3Available : 3;
2771	/** 12: PAT bit for 1GB page. */
2772	uint32_t u1PAT : 1;
2773	/** 13-29: MBZ bits. */
2774	uint32_t u17Reserved : 17;
2775	/** 30-31: Physical page number - Low Part. Don't use! */
2776	uint32_t u2PageNoLow : 2;
2777	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
2778	uint32_t u20PageNoHigh : 20;
2779	/** 52-62: MBZ bits */
2780	uint32_t u11Reserved : 11;
2781	/** 63: No Execute flag. */
2782	uint32_t u1NoExecute : 1;
2783	} X86PDPE1GB;
2784	#ifndef VBOX_FOR_DTRACE_LIB
2785	AssertCompileSize(X86PDPE1GB, 8);
2786	#endif
2787	/** Pointer to a page directory pointer table entry for a 1GB page. */
2788	typedef X86PDPE1GB *PX86PDPE1GB;
2789	/** Pointer to a const page directory pointer table entry for a 1GB page. */
2790	typedef const X86PDPE1GB *PCX86PDPE1GB;
2791
2792	/**
2793	* Page directory pointer table entry.
2794	*/
2795	typedef union X86PDPE
2796	{
2797	/** Unsigned integer view. */
2798	X86PGPAEUINT u;
2799	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2800	/** Normal view. */
2801	X86PDPEBITS n;
2802	/** AMD64 view. */
2803	X86PDPEAMD64BITS lm;
2804	/** AMD64 big view. */
2805	X86PDPE1GB b;
2806	#endif
2807	/** 8 bit unsigned integer view. */
2808	uint8_t au8[8];
2809	/** 16 bit unsigned integer view. */
2810	uint16_t au16[4];
2811	/** 32 bit unsigned integer view. */
2812	uint32_t au32[2];
2813	} X86PDPE;
2814	#ifndef VBOX_FOR_DTRACE_LIB
2815	AssertCompileSize(X86PDPE, 8);
2816	#endif
2817	/** Pointer to a page directory pointer table entry. */
2818	typedef X86PDPE *PX86PDPE;
2819	/** Pointer to a const page directory pointer table entry. */
2820	typedef const X86PDPE *PCX86PDPE;
2821
2822
2823	/**
2824	* Page directory pointer table.
2825	*/
2826	typedef struct X86PDPT
2827	{
2828	/** PDE Array. */
2829	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2830	} X86PDPT;
2831	#ifndef VBOX_FOR_DTRACE_LIB
2832	AssertCompileSize(X86PDPT, 4096);
2833	#endif
2834	/** Pointer to a page directory pointer table. */
2835	typedef X86PDPT *PX86PDPT;
2836	/** Pointer to a const page directory pointer table. */
2837	typedef const X86PDPT *PCX86PDPT;
2838
2839	/** The page shift to get the PDPT index. */
2840	#define X86_PDPT_SHIFT 30
2841	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2842	#define X86_PDPT_MASK_PAE 0x3
2843	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2844	#define X86_PDPT_MASK_AMD64 0x1ff
2845
2846	/** @} */
2847
2848
2849	/** @name Page Map Level-4 Entry (Long Mode PAE)
2850	* @{
2851	*/
2852	/** Bit 0 - P - Present bit. */
2853	#define X86_PML4E_P RT_BIT_32(0)
2854	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2855	#define X86_PML4E_RW RT_BIT_32(1)
2856	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2857	#define X86_PML4E_US RT_BIT_32(2)
2858	/** Bit 3 - PWT - Page level write thru bit. */
2859	#define X86_PML4E_PWT RT_BIT_32(3)
2860	/** Bit 4 - PCD - Page level cache disable bit. */
2861	#define X86_PML4E_PCD RT_BIT_32(4)
2862	/** Bit 5 - A - Access bit. */
2863	#define X86_PML4E_A RT_BIT_32(5)
2864	/** Bits 9-11 - - Available for use to system software. */
2865	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2866	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2867	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2868	/** Bits 8, 7 - - MBZ bits when NX is active. */
2869	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2870	/** Bits 63, 7 - - MBZ bits when no NX. */
2871	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2872	/** Bits 63 - NX - PAE - No execution flag. */
2873	#define X86_PML4E_NX RT_BIT_64(63)
2874
2875	/**
2876	* Page Map Level-4 Entry
2877	*/
2878	typedef struct X86PML4EBITS
2879	{
2880	/** Flags whether(=1) or not the page is present. */
2881	uint32_t u1Present : 1;
2882	/** Read(=0) / Write(=1) flag. */
2883	uint32_t u1Write : 1;
2884	/** User(=1) / Supervisor (=0) flag. */
2885	uint32_t u1User : 1;
2886	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2887	uint32_t u1WriteThru : 1;
2888	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2889	uint32_t u1CacheDisable : 1;
2890	/** Accessed flag.
2891	* Indicates that the page have been read or written to. */
2892	uint32_t u1Accessed : 1;
2893	/** Chunk of reserved bits. */
2894	uint32_t u3Reserved : 3;
2895	/** Available for use to system software. */
2896	uint32_t u3Available : 3;
2897	/** Physical Page number of the next level - Low Part. Don't use! */
2898	uint32_t u20PageNoLow : 20;
2899	/** Physical Page number of the next level - High Part. Don't use! */
2900	uint32_t u20PageNoHigh : 20;
2901	/** MBZ bits */
2902	uint32_t u11Reserved : 11;
2903	/** No Execute flag. */
2904	uint32_t u1NoExecute : 1;
2905	} X86PML4EBITS;
2906	#ifndef VBOX_FOR_DTRACE_LIB
2907	AssertCompileSize(X86PML4EBITS, 8);
2908	#endif
2909	/** Pointer to a page map level-4 entry. */
2910	typedef X86PML4EBITS *PX86PML4EBITS;
2911	/** Pointer to a const page map level-4 entry. */
2912	typedef const X86PML4EBITS *PCX86PML4EBITS;
2913
2914	/**
2915	* Page Map Level-4 Entry.
2916	*/
2917	typedef union X86PML4E
2918	{
2919	/** Unsigned integer view. */
2920	X86PGPAEUINT u;
2921	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2922	/** Normal view. */
2923	X86PML4EBITS n;
2924	#endif
2925	/** 8 bit unsigned integer view. */
2926	uint8_t au8[8];
2927	/** 16 bit unsigned integer view. */
2928	uint16_t au16[4];
2929	/** 32 bit unsigned integer view. */
2930	uint32_t au32[2];
2931	} X86PML4E;
2932	#ifndef VBOX_FOR_DTRACE_LIB
2933	AssertCompileSize(X86PML4E, 8);
2934	#endif
2935	/** Pointer to a page map level-4 entry. */
2936	typedef X86PML4E *PX86PML4E;
2937	/** Pointer to a const page map level-4 entry. */
2938	typedef const X86PML4E *PCX86PML4E;
2939
2940
2941	/**
2942	* Page Map Level-4.
2943	*/
2944	typedef struct X86PML4
2945	{
2946	/** PDE Array. */
2947	X86PML4E a[X86_PG_PAE_ENTRIES];
2948	} X86PML4;
2949	#ifndef VBOX_FOR_DTRACE_LIB
2950	AssertCompileSize(X86PML4, 4096);
2951	#endif
2952	/** Pointer to a page map level-4. */
2953	typedef X86PML4 *PX86PML4;
2954	/** Pointer to a const page map level-4. */
2955	typedef const X86PML4 *PCX86PML4;
2956
2957	/** The page shift to get the PML4 index. */
2958	#define X86_PML4_SHIFT 39
2959	/** The PML4 index mask (apply to a shifted page address). */
2960	#define X86_PML4_MASK 0x1ff
2961
2962	/** @} */
2963
2964	/** @} */
2965
2966	/**
2967	* Intel PCID invalidation types.
2968	*/
2969	/** Individual address invalidation. */
2970	#define X86_INVPCID_TYPE_INDV_ADDR 0
2971	/** Single-context invalidation. */
2972	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2973	/** All-context including globals invalidation. */
2974	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2975	/** All-context excluding globals invalidation. */
2976	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2977	/** The maximum valid invalidation type value. */
2978	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2979
2980
2981	/** @name Special FPU integer values.
2982	* @{ */
2983	#define X86_FPU_INT64_INDEFINITE INT64_MIN
2984	#define X86_FPU_INT32_INDEFINITE INT32_MIN
2985	#define X86_FPU_INT16_INDEFINITE INT16_MIN
2986	/** @} */
2987
2988	/**
2989	* 32-bit protected mode FSTENV image.
2990	*/
2991	typedef struct X86FSTENV32P
2992	{
2993	uint16_t FCW; /*< 0x00 /
2994	uint16_t padding1; /*< 0x02 /
2995	uint16_t FSW; /*< 0x04 /
2996	uint16_t padding2; /*< 0x06 /
2997	uint16_t FTW; /*< 0x08 /
2998	uint16_t padding3; /*< 0x0a /
2999	uint32_t FPUIP; /*< 0x0c /
3000	uint16_t FPUCS; /*< 0x10 /
3001	uint16_t FOP; /*< 0x12 /
3002	uint32_t FPUDP; /*< 0x14 /
3003	uint16_t FPUDS; /*< 0x18 /
3004	uint16_t padding4; /*< 0x1a /
3005	} X86FSTENV32P;
3006	#ifndef VBOX_FOR_DTRACE_LIB
3007	AssertCompileSize(X86FSTENV32P, 0x1c);
3008	#endif
3009	/** Pointer to a 32-bit protected mode FSTENV image. */
3010	typedef X86FSTENV32P *PX86FSTENV32P;
3011	/** Pointer to a const 32-bit protected mode FSTENV image. */
3012	typedef X86FSTENV32P const *PCX86FSTENV32P;
3013
3014
3015	/**
3016	* 80-bit MMX/FPU register type.
3017	*/
3018	typedef struct X86FPUMMX
3019	{
3020	uint8_t reg[10];
3021	} X86FPUMMX;
3022	#ifndef VBOX_FOR_DTRACE_LIB
3023	AssertCompileSize(X86FPUMMX, 10);
3024	#endif
3025	/** Pointer to a 80-bit MMX/FPU register type. */
3026	typedef X86FPUMMX *PX86FPUMMX;
3027	/** Pointer to a const 80-bit MMX/FPU register type. */
3028	typedef const X86FPUMMX *PCX86FPUMMX;
3029
3030	/** FPU (x87) register. */
3031	typedef union X86FPUREG
3032	{
3033	/** MMX view. */
3034	uint64_t mmx;
3035	/** FPU view - todo. */
3036	X86FPUMMX fpu;
3037	/** Extended precision floating point view. */
3038	RTFLOAT80U r80;
3039	/** Extended precision floating point view v2 */
3040	RTFLOAT80U2 r80Ex;
3041	/** 8-bit view. */
3042	uint8_t au8[16];
3043	/** 16-bit view. */
3044	uint16_t au16[8];
3045	/** 32-bit view. */
3046	uint32_t au32[4];
3047	/** 64-bit view. */
3048	uint64_t au64[2];
3049	/** 128-bit view. (yeah, very helpful) */
3050	uint128_t au128[1];
3051	} X86FPUREG;
3052	#ifndef VBOX_FOR_DTRACE_LIB
3053	AssertCompileSize(X86FPUREG, 16);
3054	#endif
3055	/** Pointer to a FPU register. */
3056	typedef X86FPUREG *PX86FPUREG;
3057	/** Pointer to a const FPU register. */
3058	typedef X86FPUREG const *PCX86FPUREG;
3059
3060	/**
3061	* XMM register union.
3062	*/
3063	typedef union X86XMMREG
3064	{
3065	/** XMM Register view. */
3066	uint128_t xmm;
3067	/** 8-bit view. */
3068	uint8_t au8[16];
3069	/** 16-bit view. */
3070	uint16_t au16[8];
3071	/** 32-bit view. */
3072	uint32_t au32[4];
3073	/** 64-bit view. */
3074	uint64_t au64[2];
3075	/** 128-bit view. (yeah, very helpful) */
3076	uint128_t au128[1];
3077	#ifndef VBOX_FOR_DTRACE_LIB
3078	/** Confusing nested 128-bit union view (this is what xmm should've been). */
3079	RTUINT128U uXmm;
3080	#endif
3081	} X86XMMREG;
3082	#ifndef VBOX_FOR_DTRACE_LIB
3083	AssertCompileSize(X86XMMREG, 16);
3084	#endif
3085	/** Pointer to an XMM register state. */
3086	typedef X86XMMREG *PX86XMMREG;
3087	/** Pointer to a const XMM register state. */
3088	typedef X86XMMREG const *PCX86XMMREG;
3089
3090	/**
3091	* YMM register union.
3092	*/
3093	typedef union X86YMMREG
3094	{
3095	/** 8-bit view. */
3096	uint8_t au8[32];
3097	/** 16-bit view. */
3098	uint16_t au16[16];
3099	/** 32-bit view. */
3100	uint32_t au32[8];
3101	/** 64-bit view. */
3102	uint64_t au64[4];
3103	/** 128-bit view. (yeah, very helpful) */
3104	uint128_t au128[2];
3105	/** XMM sub register view. */
3106	X86XMMREG aXmm[2];
3107	} X86YMMREG;
3108	#ifndef VBOX_FOR_DTRACE_LIB
3109	AssertCompileSize(X86YMMREG, 32);
3110	#endif
3111	/** Pointer to an YMM register state. */
3112	typedef X86YMMREG *PX86YMMREG;
3113	/** Pointer to a const YMM register state. */
3114	typedef X86YMMREG const *PCX86YMMREG;
3115
3116	/**
3117	* ZMM register union.
3118	*/
3119	typedef union X86ZMMREG
3120	{
3121	/** 8-bit view. */
3122	uint8_t au8[64];
3123	/** 16-bit view. */
3124	uint16_t au16[32];
3125	/** 32-bit view. */
3126	uint32_t au32[16];
3127	/** 64-bit view. */
3128	uint64_t au64[8];
3129	/** 128-bit view. (yeah, very helpful) */
3130	uint128_t au128[4];
3131	/** XMM sub register view. */
3132	X86XMMREG aXmm[4];
3133	/** YMM sub register view. */
3134	X86YMMREG aYmm[2];
3135	} X86ZMMREG;
3136	#ifndef VBOX_FOR_DTRACE_LIB
3137	AssertCompileSize(X86ZMMREG, 64);
3138	#endif
3139	/** Pointer to an ZMM register state. */
3140	typedef X86ZMMREG *PX86ZMMREG;
3141	/** Pointer to a const ZMM register state. */
3142	typedef X86ZMMREG const *PCX86ZMMREG;
3143
3144
3145	/**
3146	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3147	* @todo verify this...
3148	*/
3149	#pragma pack(1)
3150	typedef struct X86FPUSTATE
3151	{
3152	/** 0x00 - Control word. */
3153	uint16_t FCW;
3154	/** 0x02 - Alignment word */
3155	uint16_t Dummy1;
3156	/** 0x04 - Status word. */
3157	uint16_t FSW;
3158	/** 0x06 - Alignment word */
3159	uint16_t Dummy2;
3160	/** 0x08 - Tag word */
3161	uint16_t FTW;
3162	/** 0x0a - Alignment word */
3163	uint16_t Dummy3;
3164
3165	/** 0x0c - Instruction pointer. */
3166	uint32_t FPUIP;
3167	/** 0x10 - Code selector. */
3168	uint16_t CS;
3169	/** 0x12 - Opcode. */
3170	uint16_t FOP;
3171	/** 0x14 - FOO. */
3172	uint32_t FPUOO;
3173	/** 0x18 - FOS. */
3174	uint32_t FPUOS;
3175	/** 0x1c - FPU register. */
3176	X86FPUREG regs[8];
3177	} X86FPUSTATE;
3178	#pragma pack()
3179	/** Pointer to a FPU state. */
3180	typedef X86FPUSTATE *PX86FPUSTATE;
3181	/** Pointer to a const FPU state. */
3182	typedef const X86FPUSTATE *PCX86FPUSTATE;
3183
3184	/**
3185	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3186	*/
3187	#pragma pack(1)
3188	typedef struct X86FXSTATE
3189	{
3190	/** 0x00 - Control word. */
3191	uint16_t FCW;
3192	/** 0x02 - Status word. */
3193	uint16_t FSW;
3194	/** 0x04 - Tag word. (The upper byte is always zero.) */
3195	uint16_t FTW;
3196	/** 0x06 - Opcode. */
3197	uint16_t FOP;
3198	/** 0x08 - Instruction pointer. */
3199	uint32_t FPUIP;
3200	/** 0x0c - Code selector. */
3201	uint16_t CS;
3202	uint16_t Rsrvd1;
3203	/** 0x10 - Data pointer. */
3204	uint32_t FPUDP;
3205	/** 0x14 - Data segment */
3206	uint16_t DS;
3207	/** 0x16 */
3208	uint16_t Rsrvd2;
3209	/** 0x18 */
3210	uint32_t MXCSR;
3211	/** 0x1c */
3212	uint32_t MXCSR_MASK;
3213	/** 0x20 - FPU registers. */
3214	X86FPUREG aRegs[8];
3215	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3216	X86XMMREG aXMM[16];
3217	/* - offset 416 - */
3218	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3219	/* - offset 464 - Software usable reserved bits. */
3220	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3221	} X86FXSTATE;
3222	#pragma pack()
3223	/** Pointer to a FPU Extended state. */
3224	typedef X86FXSTATE *PX86FXSTATE;
3225	/** Pointer to a const FPU Extended state. */
3226	typedef const X86FXSTATE *PCX86FXSTATE;
3227
3228	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3229	* magic. Don't forget to update x86.mac if you change this! */
3230	#define X86_OFF_FXSTATE_RSVD 0x1d0
3231	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3232	* forget to update x86.mac if you change this!
3233	* @todo r=bird: This has nothing what-so-ever to do here.... */
3234	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3235	#ifndef VBOX_FOR_DTRACE_LIB
3236	AssertCompileSize(X86FXSTATE, 512);
3237	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3238	#endif
3239
3240	/** @name FPU status word flags.
3241	* @{ */
3242	/** Exception Flag: Invalid operation. */
3243	#define X86_FSW_IE RT_BIT_32(0)
3244	/** Exception Flag: Denormalized operand. */
3245	#define X86_FSW_DE RT_BIT_32(1)
3246	/** Exception Flag: Zero divide. */
3247	#define X86_FSW_ZE RT_BIT_32(2)
3248	/** Exception Flag: Overflow. */
3249	#define X86_FSW_OE RT_BIT_32(3)
3250	/** Exception Flag: Underflow. */
3251	#define X86_FSW_UE RT_BIT_32(4)
3252	/** Exception Flag: Precision. */
3253	#define X86_FSW_PE RT_BIT_32(5)
3254	/** Stack fault. */
3255	#define X86_FSW_SF RT_BIT_32(6)
3256	/** Error summary status. */
3257	#define X86_FSW_ES RT_BIT_32(7)
3258	/** Mask of exceptions flags, excluding the summary bit. */
3259	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3260	/** Mask of exceptions flags, including the summary bit. */
3261	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3262	/** Condition code 0. */
3263	#define X86_FSW_C0 RT_BIT_32(8)
3264	/** Condition code 1. */
3265	#define X86_FSW_C1 RT_BIT_32(9)
3266	/** Condition code 2. */
3267	#define X86_FSW_C2 RT_BIT_32(10)
3268	/** Top of the stack mask. */
3269	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3270	/** TOP shift value. */
3271	#define X86_FSW_TOP_SHIFT 11
3272	/** Mask for getting TOP value after shifting it right. */
3273	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3274	/** Get the TOP value. */
3275	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3276	/** Get the TOP value offsetted by a_iSt (0-7). */
3277	#define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
3278	/** Condition code 3. */
3279	#define X86_FSW_C3 RT_BIT_32(14)
3280	/** Mask of exceptions flags, including the summary bit. */
3281	#define X86_FSW_C_MASK UINT16_C(0x4700)
3282	/** FPU busy. */
3283	#define X86_FSW_B RT_BIT_32(15)
3284	/** @} */
3285
3286
3287	/** @name FPU control word flags.
3288	* @{ */
3289	/** Exception Mask: Invalid operation. */
3290	#define X86_FCW_IM RT_BIT_32(0)
3291	#define X86_FCW_IM_BIT 0
3292	/** Exception Mask: Denormalized operand. */
3293	#define X86_FCW_DM RT_BIT_32(1)
3294	#define X86_FCW_DM_BIT 1
3295	/** Exception Mask: Zero divide. */
3296	#define X86_FCW_ZM RT_BIT_32(2)
3297	#define X86_FCW_ZM_BIT 2
3298	/** Exception Mask: Overflow. */
3299	#define X86_FCW_OM RT_BIT_32(3)
3300	#define X86_FCW_OM_BIT 3
3301	/** Exception Mask: Underflow. */
3302	#define X86_FCW_UM RT_BIT_32(4)
3303	#define X86_FCW_UM_BIT 4
3304	/** Exception Mask: Precision. */
3305	#define X86_FCW_PM RT_BIT_32(5)
3306	#define X86_FCW_PM_BIT 5
3307	/** Mask all exceptions, the value typically loaded (by for instance fninit).
3308	* @remarks This includes reserved bit 6. */
3309	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3310	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3311	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3312	/** Precision control mask. */
3313	#define X86_FCW_PC_MASK UINT16_C(0x0300)
3314	/** Precision control shift. */
3315	#define X86_FCW_PC_SHIFT 8
3316	/** Precision control: 24-bit. */
3317	#define X86_FCW_PC_24 UINT16_C(0x0000)
3318	/** Precision control: Reserved. */
3319	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3320	/** Precision control: 53-bit. */
3321	#define X86_FCW_PC_53 UINT16_C(0x0200)
3322	/** Precision control: 64-bit. */
3323	#define X86_FCW_PC_64 UINT16_C(0x0300)
3324	/** Rounding control mask. */
3325	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3326	/** Rounding control shift. */
3327	#define X86_FCW_RC_SHIFT 10
3328	/** Rounding control: To nearest. */
3329	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3330	/** Rounding control: Down. */
3331	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3332	/** Rounding control: Up. */
3333	#define X86_FCW_RC_UP UINT16_C(0x0800)
3334	/** Rounding control: Towards zero. */
3335	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3336	/** Bits which should be zero, apparently. */
3337	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3338	/** @} */
3339
3340	/** @name SSE MXCSR
3341	* @{ */
3342	/** Exception Flag: Invalid operation. */
3343	#define X86_MXCSR_IE RT_BIT_32(0)
3344	/** Exception Flag: Denormalized operand. */
3345	#define X86_MXCSR_DE RT_BIT_32(1)
3346	/** Exception Flag: Zero divide. */
3347	#define X86_MXCSR_ZE RT_BIT_32(2)
3348	/** Exception Flag: Overflow. */
3349	#define X86_MXCSR_OE RT_BIT_32(3)
3350	/** Exception Flag: Underflow. */
3351	#define X86_MXCSR_UE RT_BIT_32(4)
3352	/** Exception Flag: Precision. */
3353	#define X86_MXCSR_PE RT_BIT_32(5)
3354
3355	/** Denormals are zero. */
3356	#define X86_MXCSR_DAZ RT_BIT_32(6)
3357
3358	/** Exception Mask: Invalid operation. */
3359	#define X86_MXCSR_IM RT_BIT_32(7)
3360	/** Exception Mask: Denormalized operand. */
3361	#define X86_MXCSR_DM RT_BIT_32(8)
3362	/** Exception Mask: Zero divide. */
3363	#define X86_MXCSR_ZM RT_BIT_32(9)
3364	/** Exception Mask: Overflow. */
3365	#define X86_MXCSR_OM RT_BIT_32(10)
3366	/** Exception Mask: Underflow. */
3367	#define X86_MXCSR_UM RT_BIT_32(11)
3368	/** Exception Mask: Precision. */
3369	#define X86_MXCSR_PM RT_BIT_32(12)
3370
3371	/** Rounding control mask. */
3372	#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
3373	/** Rounding control: To nearest. */
3374	#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3375	/** Rounding control: Down. */
3376	#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3377	/** Rounding control: Up. */
3378	#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3379	/** Rounding control: Towards zero. */
3380	#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3381
3382	/** Flush-to-zero for masked underflow. */
3383	#define X86_MXCSR_FZ RT_BIT_32(15)
3384
3385	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3386	#define X86_MXCSR_MM RT_BIT_32(17)
3387	/** @} */
3388
3389	/**
3390	* XSAVE header.
3391	*/
3392	typedef struct X86XSAVEHDR
3393	{
3394	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
3395	uint64_t bmXState;
3396	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3397	uint64_t bmXComp;
3398	/** Reserved for furture extensions, probably MBZ. */
3399	uint64_t au64Reserved[6];
3400	} X86XSAVEHDR;
3401	#ifndef VBOX_FOR_DTRACE_LIB
3402	AssertCompileSize(X86XSAVEHDR, 64);
3403	#endif
3404	/** Pointer to an XSAVE header. */
3405	typedef X86XSAVEHDR *PX86XSAVEHDR;
3406	/** Pointer to a const XSAVE header. */
3407	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3408
3409
3410	/**
3411	* The high 128-bit YMM register state (XSAVE_C_YMM).
3412	* (The lower 128-bits being in X86FXSTATE.)
3413	*/
3414	typedef struct X86XSAVEYMMHI
3415	{
3416	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3417	X86XMMREG aYmmHi[16];
3418	} X86XSAVEYMMHI;
3419	#ifndef VBOX_FOR_DTRACE_LIB
3420	AssertCompileSize(X86XSAVEYMMHI, 256);
3421	#endif
3422	/** Pointer to a high 128-bit YMM register state. */
3423	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3424	/** Pointer to a const high 128-bit YMM register state. */
3425	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3426
3427	/**
3428	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
3429	*/
3430	typedef struct X86XSAVEBNDREGS
3431	{
3432	/** Array of registers (BND0...BND3). */
3433	struct
3434	{
3435	/** Lower bound. */
3436	uint64_t uLowerBound;
3437	/** Upper bound. */
3438	uint64_t uUpperBound;
3439	} aRegs[4];
3440	} X86XSAVEBNDREGS;
3441	#ifndef VBOX_FOR_DTRACE_LIB
3442	AssertCompileSize(X86XSAVEBNDREGS, 64);
3443	#endif
3444	/** Pointer to a MPX bound register state. */
3445	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3446	/** Pointer to a const MPX bound register state. */
3447	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3448
3449	/**
3450	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3451	*/
3452	typedef struct X86XSAVEBNDCFG
3453	{
3454	uint64_t fConfig;
3455	uint64_t fStatus;
3456	} X86XSAVEBNDCFG;
3457	#ifndef VBOX_FOR_DTRACE_LIB
3458	AssertCompileSize(X86XSAVEBNDCFG, 16);
3459	#endif
3460	/** Pointer to a MPX bound config and status register state. */
3461	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3462	/** Pointer to a const MPX bound config and status register state. */
3463	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3464
3465	/**
3466	* AVX-512 opmask state (XSAVE_C_OPMASK).
3467	*/
3468	typedef struct X86XSAVEOPMASK
3469	{
3470	/** The K0..K7 values. */
3471	uint64_t aKRegs[8];
3472	} X86XSAVEOPMASK;
3473	#ifndef VBOX_FOR_DTRACE_LIB
3474	AssertCompileSize(X86XSAVEOPMASK, 64);
3475	#endif
3476	/** Pointer to a AVX-512 opmask state. */
3477	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3478	/** Pointer to a const AVX-512 opmask state. */
3479	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3480
3481	/**
3482	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3483	*/
3484	typedef struct X86XSAVEZMMHI256
3485	{
3486	/** Upper 256-bits of ZMM0-15. */
3487	X86YMMREG aHi256Regs[16];
3488	} X86XSAVEZMMHI256;
3489	#ifndef VBOX_FOR_DTRACE_LIB
3490	AssertCompileSize(X86XSAVEZMMHI256, 512);
3491	#endif
3492	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3493	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3494	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3495	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3496
3497	/**
3498	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3499	*/
3500	typedef struct X86XSAVEZMM16HI
3501	{
3502	/** ZMM16 thru ZMM31. */
3503	X86ZMMREG aRegs[16];
3504	} X86XSAVEZMM16HI;
3505	#ifndef VBOX_FOR_DTRACE_LIB
3506	AssertCompileSize(X86XSAVEZMM16HI, 1024);
3507	#endif
3508	/** Pointer to a state comprising ZMM16-32. */
3509	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3510	/** Pointer to a const state comprising ZMM16-32. */
3511	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3512
3513	/**
3514	* AMD Light weight profiling state (XSAVE_C_LWP).
3515	*
3516	* We probably won't play with this as AMD seems to be dropping from their "zen"
3517	* processor micro architecture.
3518	*/
3519	typedef struct X86XSAVELWP
3520	{
3521	/** Details when needed. */
3522	uint64_t auLater[128/8];
3523	} X86XSAVELWP;
3524	#ifndef VBOX_FOR_DTRACE_LIB
3525	AssertCompileSize(X86XSAVELWP, 128);
3526	#endif
3527
3528
3529	/**
3530	* x86 FPU/SSE/AVX/XXXX state.
3531	*
3532	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3533	* changes to this structure.
3534	*/
3535	typedef struct X86XSAVEAREA
3536	{
3537	/** The x87 and SSE region (or legacy region if you like). */
3538	X86FXSTATE x87;
3539	/** The XSAVE header. */
3540	X86XSAVEHDR Hdr;
3541	/** Beyond the header, there isn't really a fixed layout, but we can
3542	generally assume the YMM (AVX) register extensions are present and
3543	follows immediately. */
3544	union
3545	{
3546	/** The high 128-bit AVX registers for easy access by IEM.
3547	* @note This ASSUMES they will always be here... */
3548	X86XSAVEYMMHI YmmHi;
3549
3550	/** This is a typical layout on intel CPUs (good for debuggers). */
3551	struct
3552	{
3553	X86XSAVEYMMHI YmmHi;
3554	X86XSAVEBNDREGS BndRegs;
3555	X86XSAVEBNDCFG BndCfg;
3556	uint8_t abFudgeToMatchDocs[0xB0];
3557	X86XSAVEOPMASK Opmask;
3558	X86XSAVEZMMHI256 ZmmHi256;
3559	X86XSAVEZMM16HI Zmm16Hi;
3560	} Intel;
3561
3562	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3563	struct
3564	{
3565	X86XSAVEYMMHI YmmHi;
3566	X86XSAVELWP Lwp;
3567	} AmdBd;
3568
3569	/** To enbling static deployments that have a reasonable chance of working for
3570	* the next 3-6 CPU generations without running short on space, we allocate a
3571	* lot of extra space here, making the structure a round 8KB in size. This
3572	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3573	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3574	uint8_t ab[8192 - 512 - 64];
3575	} u;
3576	} X86XSAVEAREA;
3577	#ifndef VBOX_FOR_DTRACE_LIB
3578	AssertCompileSize(X86XSAVEAREA, 8192);
3579	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
3580	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3581	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3582	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3583	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3584	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3585	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3586	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3587	#endif
3588	/** Pointer to a XSAVE area. */
3589	typedef X86XSAVEAREA *PX86XSAVEAREA;
3590	/** Pointer to a const XSAVE area. */
3591	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3592
3593
3594	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3595	* @{ */
3596	/** Bit 0 - x87 - Legacy FPU state (bit number) */
3597	#define XSAVE_C_X87_BIT 0
3598	/** Bit 0 - x87 - Legacy FPU state. */
3599	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3600	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3601	#define XSAVE_C_SSE_BIT 1
3602	/** Bit 1 - SSE - 128-bit SSE state. */
3603	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3604	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3605	#define XSAVE_C_YMM_BIT 2
3606	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3607	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3608	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3609	#define XSAVE_C_BNDREGS_BIT 3
3610	/** Bit 3 - BNDREGS - MPX bound register state. */
3611	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3612	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3613	#define XSAVE_C_BNDCSR_BIT 4
3614	/** Bit 4 - BNDCSR - MPX bound config and status state. */
3615	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3616	/** Bit 5 - Opmask - opmask state (bit number). */
3617	#define XSAVE_C_OPMASK_BIT 5
3618	/** Bit 5 - Opmask - opmask state. */
3619	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3620	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3621	#define XSAVE_C_ZMM_HI256_BIT 6
3622	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3623	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3624	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3625	#define XSAVE_C_ZMM_16HI_BIT 7
3626	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3627	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3628	/** Bit 9 - PKRU - Protection-key state (bit number). */
3629	#define XSAVE_C_PKRU_BIT 9
3630	/** Bit 9 - PKRU - Protection-key state. */
3631	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3632	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3633	#define XSAVE_C_LWP_BIT 62
3634	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3635	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3636	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3637	#define XSAVE_C_X_BIT 63
3638	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3639	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3640	/** @} */
3641
3642
3643
3644	/** @name Selector Descriptor
3645	* @{
3646	*/
3647
3648	#ifndef VBOX_FOR_DTRACE_LIB
3649	/**
3650	* Descriptor attributes (as seen by VT-x).
3651	*/
3652	typedef struct X86DESCATTRBITS
3653	{
3654	/** 00 - Segment Type. */
3655	unsigned u4Type : 4;
3656	/** 04 - Descriptor Type. System(=0) or code/data selector */
3657	unsigned u1DescType : 1;
3658	/** 05 - Descriptor Privilege level. */
3659	unsigned u2Dpl : 2;
3660	/** 07 - Flags selector present(=1) or not. */
3661	unsigned u1Present : 1;
3662	/** 08 - Segment limit 16-19. */
3663	unsigned u4LimitHigh : 4;
3664	/** 0c - Available for system software. */
3665	unsigned u1Available : 1;
3666	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3667	unsigned u1Long : 1;
3668	/** 0e - This flags meaning depends on the segment type. Try make sense out
3669	* of the intel manual yourself. */
3670	unsigned u1DefBig : 1;
3671	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
3672	* clear byte. */
3673	unsigned u1Granularity : 1;
3674	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3675	unsigned u1Unusable : 1;
3676	} X86DESCATTRBITS;
3677	#endif /* !VBOX_FOR_DTRACE_LIB */
3678
3679	/** @name X86DESCATTR masks
3680	* @{ */
3681	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3682	#define X86DESCATTR_DT UINT32_C(0x00000010)
3683	#define X86DESCATTR_DPL UINT32_C(0x00000060)
3684	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
3685	#define X86DESCATTR_P UINT32_C(0x00000080)
3686	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3687	#define X86DESCATTR_AVL UINT32_C(0x00001000)
3688	#define X86DESCATTR_L UINT32_C(0x00002000)
3689	#define X86DESCATTR_D UINT32_C(0x00004000)
3690	#define X86DESCATTR_G UINT32_C(0x00008000)
3691	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3692	/** @} */
3693
3694	#pragma pack(1)
3695	typedef union X86DESCATTR
3696	{
3697	/** Unsigned integer view. */
3698	uint32_t u;
3699	#ifndef VBOX_FOR_DTRACE_LIB
3700	/** Normal view. */
3701	X86DESCATTRBITS n;
3702	#endif
3703	} X86DESCATTR;
3704	#pragma pack()
3705	/** Pointer to descriptor attributes. */
3706	typedef X86DESCATTR *PX86DESCATTR;
3707	/** Pointer to const descriptor attributes. */
3708	typedef const X86DESCATTR *PCX86DESCATTR;
3709
3710	#ifndef VBOX_FOR_DTRACE_LIB
3711
3712	/**
3713	* Generic descriptor table entry
3714	*/
3715	#pragma pack(1)
3716	typedef struct X86DESCGENERIC
3717	{
3718	/** 00 - Limit - Low word. */
3719	unsigned u16LimitLow : 16;
3720	/** 10 - Base address - low word.
3721	* Don't try set this to 24 because MSC is doing stupid things then. */
3722	unsigned u16BaseLow : 16;
3723	/** 20 - Base address - first 8 bits of high word. */
3724	unsigned u8BaseHigh1 : 8;
3725	/** 28 - Segment Type. */
3726	unsigned u4Type : 4;
3727	/** 2c - Descriptor Type. System(=0) or code/data selector */
3728	unsigned u1DescType : 1;
3729	/** 2d - Descriptor Privilege level. */
3730	unsigned u2Dpl : 2;
3731	/** 2f - Flags selector present(=1) or not. */
3732	unsigned u1Present : 1;
3733	/** 30 - Segment limit 16-19. */
3734	unsigned u4LimitHigh : 4;
3735	/** 34 - Available for system software. */
3736	unsigned u1Available : 1;
3737	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3738	unsigned u1Long : 1;
3739	/** 36 - This flags meaning depends on the segment type. Try make sense out
3740	* of the intel manual yourself. */
3741	unsigned u1DefBig : 1;
3742	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
3743	* clear byte. */
3744	unsigned u1Granularity : 1;
3745	/** 38 - Base address - highest 8 bits. */
3746	unsigned u8BaseHigh2 : 8;
3747	} X86DESCGENERIC;
3748	#pragma pack()
3749	/** Pointer to a generic descriptor entry. */
3750	typedef X86DESCGENERIC *PX86DESCGENERIC;
3751	/** Pointer to a const generic descriptor entry. */
3752	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3753
3754	/** @name Bit offsets of X86DESCGENERIC members.
3755	* @{*/
3756	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
3757	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
3758	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
3759	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
3760	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
3761	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
3762	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
3763	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
3764	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
3765	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
3766	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
3767	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
3768	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
3769	/** @} */
3770
3771
3772	/** @name LAR mask
3773	* @{ */
3774	#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3775	#define X86LAR_F_DT UINT16_C( 0x1000)
3776	#define X86LAR_F_DPL UINT16_C( 0x6000)
3777	#define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
3778	#define X86LAR_F_P UINT16_C( 0x8000)
3779	#define X86LAR_F_AVL UINT32_C(0x00100000)
3780	#define X86LAR_F_L UINT32_C(0x00200000)
3781	#define X86LAR_F_D UINT32_C(0x00400000)
3782	#define X86LAR_F_G UINT32_C(0x00800000)
3783	/** @} */
3784
3785
3786	/**
3787	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3788	*/
3789	typedef struct X86DESCGATE
3790	{
3791	/** 00 - Target code segment offset - Low word.
3792	* Ignored if task-gate. */
3793	unsigned u16OffsetLow : 16;
3794	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3795	* TSS selector if task-gate. */
3796	unsigned u16Sel : 16;
3797	/** 20 - Number of parameters for a call-gate.
3798	* Ignored if interrupt-, trap- or task-gate. */
3799	unsigned u5ParmCount : 5;
3800	/** 25 - Reserved / ignored. */
3801	unsigned u3Reserved : 3;
3802	/** 28 - Segment Type. */
3803	unsigned u4Type : 4;
3804	/** 2c - Descriptor Type (0 = system). */
3805	unsigned u1DescType : 1;
3806	/** 2d - Descriptor Privilege level. */
3807	unsigned u2Dpl : 2;
3808	/** 2f - Flags selector present(=1) or not. */
3809	unsigned u1Present : 1;
3810	/** 30 - Target code segment offset - High word.
3811	* Ignored if task-gate. */
3812	unsigned u16OffsetHigh : 16;
3813	} X86DESCGATE;
3814	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3815	typedef X86DESCGATE *PX86DESCGATE;
3816	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3817	typedef const X86DESCGATE *PCX86DESCGATE;
3818
3819	#endif /* VBOX_FOR_DTRACE_LIB */
3820
3821	/**
3822	* Descriptor table entry.
3823	*/
3824	#pragma pack(1)
3825	typedef union X86DESC
3826	{
3827	#ifndef VBOX_FOR_DTRACE_LIB
3828	/** Generic descriptor view. */
3829	X86DESCGENERIC Gen;
3830	/** Gate descriptor view. */
3831	X86DESCGATE Gate;
3832	#endif
3833
3834	/** 8 bit unsigned integer view. */
3835	uint8_t au8[8];
3836	/** 16 bit unsigned integer view. */
3837	uint16_t au16[4];
3838	/** 32 bit unsigned integer view. */
3839	uint32_t au32[2];
3840	/** 64 bit unsigned integer view. */
3841	uint64_t au64[1];
3842	/** Unsigned integer view. */
3843	uint64_t u;
3844	} X86DESC;
3845	#ifndef VBOX_FOR_DTRACE_LIB
3846	AssertCompileSize(X86DESC, 8);
3847	#endif
3848	#pragma pack()
3849	/** Pointer to descriptor table entry. */
3850	typedef X86DESC *PX86DESC;
3851	/** Pointer to const descriptor table entry. */
3852	typedef const X86DESC *PCX86DESC;
3853
3854	/** @def X86DESC_BASE
3855	* Return the base address of a descriptor.
3856	*/
3857	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
3858	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3859	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3860	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3861
3862	/** @def X86DESC_LIMIT
3863	* Return the limit of a descriptor.
3864	*/
3865	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
3866	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3867	\| ( (a_pDesc)->Gen.u16LimitLow ) )
3868
3869	/** @def X86DESC_LIMIT_G
3870	* Return the limit of a descriptor with the granularity bit taken into account.
3871	* @returns Selector limit (uint32_t).
3872	* @param a_pDesc Pointer to the descriptor.
3873	*/
3874	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
3875	( (a_pDesc)->Gen.u1Granularity \
3876	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
3877	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
3878	)
3879
3880	/** @def X86DESC_GET_HID_ATTR
3881	* Get the descriptor attributes for the hidden register.
3882	*/
3883	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
3884	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3885
3886	#ifndef VBOX_FOR_DTRACE_LIB
3887
3888	/**
3889	* 64 bits generic descriptor table entry
3890	* Note: most of these bits have no meaning in long mode.
3891	*/
3892	#pragma pack(1)
3893	typedef struct X86DESC64GENERIC
3894	{
3895	/** Limit - Low word - IGNORED. */
3896	uint32_t u16LimitLow : 16;
3897	/** Base address - low word. - IGNORED
3898	* Don't try set this to 24 because MSC is doing stupid things then. */
3899	uint32_t u16BaseLow : 16;
3900	/** Base address - first 8 bits of high word. - IGNORED */
3901	uint32_t u8BaseHigh1 : 8;
3902	/** Segment Type. */
3903	uint32_t u4Type : 4;
3904	/** Descriptor Type. System(=0) or code/data selector */
3905	uint32_t u1DescType : 1;
3906	/** Descriptor Privilege level. */
3907	uint32_t u2Dpl : 2;
3908	/** Flags selector present(=1) or not. */
3909	uint32_t u1Present : 1;
3910	/** Segment limit 16-19. - IGNORED */
3911	uint32_t u4LimitHigh : 4;
3912	/** Available for system software. - IGNORED */
3913	uint32_t u1Available : 1;
3914	/** Long mode flag. */
3915	uint32_t u1Long : 1;
3916	/** This flags meaning depends on the segment type. Try make sense out
3917	* of the intel manual yourself. */
3918	uint32_t u1DefBig : 1;
3919	/** Granularity of the limit. If set 4KB granularity is used, if
3920	* clear byte. - IGNORED */
3921	uint32_t u1Granularity : 1;
3922	/** Base address - highest 8 bits. - IGNORED */
3923	uint32_t u8BaseHigh2 : 8;
3924	/** Base address - bits 63-32. */
3925	uint32_t u32BaseHigh3 : 32;
3926	uint32_t u8Reserved : 8;
3927	uint32_t u5Zeros : 5;
3928	uint32_t u19Reserved : 19;
3929	} X86DESC64GENERIC;
3930	#pragma pack()
3931	/** Pointer to a generic descriptor entry. */
3932	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3933	/** Pointer to a const generic descriptor entry. */
3934	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3935
3936	/**
3937	* System descriptor table entry (64 bits)
3938	*
3939	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3940	*/
3941	#pragma pack(1)
3942	typedef struct X86DESC64SYSTEM
3943	{
3944	/** Limit - Low word. */
3945	uint32_t u16LimitLow : 16;
3946	/** Base address - low word.
3947	* Don't try set this to 24 because MSC is doing stupid things then. */
3948	uint32_t u16BaseLow : 16;
3949	/** Base address - first 8 bits of high word. */
3950	uint32_t u8BaseHigh1 : 8;
3951	/** Segment Type. */
3952	uint32_t u4Type : 4;
3953	/** Descriptor Type. System(=0) or code/data selector */
3954	uint32_t u1DescType : 1;
3955	/** Descriptor Privilege level. */
3956	uint32_t u2Dpl : 2;
3957	/** Flags selector present(=1) or not. */
3958	uint32_t u1Present : 1;
3959	/** Segment limit 16-19. */
3960	uint32_t u4LimitHigh : 4;
3961	/** Available for system software. */
3962	uint32_t u1Available : 1;
3963	/** Reserved - 0. */
3964	uint32_t u1Reserved : 1;
3965	/** This flags meaning depends on the segment type. Try make sense out
3966	* of the intel manual yourself. */
3967	uint32_t u1DefBig : 1;
3968	/** Granularity of the limit. If set 4KB granularity is used, if
3969	* clear byte. */
3970	uint32_t u1Granularity : 1;
3971	/** Base address - bits 31-24. */
3972	uint32_t u8BaseHigh2 : 8;
3973	/** Base address - bits 63-32. */
3974	uint32_t u32BaseHigh3 : 32;
3975	uint32_t u8Reserved : 8;
3976	uint32_t u5Zeros : 5;
3977	uint32_t u19Reserved : 19;
3978	} X86DESC64SYSTEM;
3979	#pragma pack()
3980	/** Pointer to a system descriptor entry. */
3981	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3982	/** Pointer to a const system descriptor entry. */
3983	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3984
3985	/**
3986	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3987	*/
3988	typedef struct X86DESC64GATE
3989	{
3990	/** Target code segment offset - Low word. */
3991	uint32_t u16OffsetLow : 16;
3992	/** Target code segment selector. */
3993	uint32_t u16Sel : 16;
3994	/** Interrupt stack table for interrupt- and trap-gates.
3995	* Ignored by call-gates. */
3996	uint32_t u3IST : 3;
3997	/** Reserved / ignored. */
3998	uint32_t u5Reserved : 5;
3999	/** Segment Type. */
4000	uint32_t u4Type : 4;
4001	/** Descriptor Type (0 = system). */
4002	uint32_t u1DescType : 1;
4003	/** Descriptor Privilege level. */
4004	uint32_t u2Dpl : 2;
4005	/** Flags selector present(=1) or not. */
4006	uint32_t u1Present : 1;
4007	/** Target code segment offset - High word.
4008	* Ignored if task-gate. */
4009	uint32_t u16OffsetHigh : 16;
4010	/** Target code segment offset - Top dword.
4011	* Ignored if task-gate. */
4012	uint32_t u32OffsetTop : 32;
4013	/** Reserved / ignored / must be zero.
4014	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
4015	uint32_t u32Reserved : 32;
4016	} X86DESC64GATE;
4017	AssertCompileSize(X86DESC64GATE, 16);
4018	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4019	typedef X86DESC64GATE *PX86DESC64GATE;
4020	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4021	typedef const X86DESC64GATE *PCX86DESC64GATE;
4022
4023	#endif /* VBOX_FOR_DTRACE_LIB */
4024
4025	/**
4026	* Descriptor table entry.
4027	*/
4028	#pragma pack(1)
4029	typedef union X86DESC64
4030	{
4031	#ifndef VBOX_FOR_DTRACE_LIB
4032	/** Generic descriptor view. */
4033	X86DESC64GENERIC Gen;
4034	/** System descriptor view. */
4035	X86DESC64SYSTEM System;
4036	/** Gate descriptor view. */
4037	X86DESC64GATE Gate;
4038	#endif
4039
4040	/** 8 bit unsigned integer view. */
4041	uint8_t au8[16];
4042	/** 16 bit unsigned integer view. */
4043	uint16_t au16[8];
4044	/** 32 bit unsigned integer view. */
4045	uint32_t au32[4];
4046	/** 64 bit unsigned integer view. */
4047	uint64_t au64[2];
4048	} X86DESC64;
4049	#ifndef VBOX_FOR_DTRACE_LIB
4050	AssertCompileSize(X86DESC64, 16);
4051	#endif
4052	#pragma pack()
4053	/** Pointer to descriptor table entry. */
4054	typedef X86DESC64 *PX86DESC64;
4055	/** Pointer to const descriptor table entry. */
4056	typedef const X86DESC64 *PCX86DESC64;
4057
4058	/** @def X86DESC64_BASE
4059	* Return the base of a 64-bit descriptor.
4060	*/
4061	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
4062	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
4063	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4064	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4065	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4066
4067
4068
4069	/** @name Host system descriptor table entry - Use with care!
4070	* @{ */
4071	/** Host system descriptor table entry. */
4072	#if HC_ARCH_BITS == 64
4073	typedef X86DESC64 X86DESCHC;
4074	#else
4075	typedef X86DESC X86DESCHC;
4076	#endif
4077	/** Pointer to a host system descriptor table entry. */
4078	#if HC_ARCH_BITS == 64
4079	typedef PX86DESC64 PX86DESCHC;
4080	#else
4081	typedef PX86DESC PX86DESCHC;
4082	#endif
4083	/** Pointer to a const host system descriptor table entry. */
4084	#if HC_ARCH_BITS == 64
4085	typedef PCX86DESC64 PCX86DESCHC;
4086	#else
4087	typedef PCX86DESC PCX86DESCHC;
4088	#endif
4089	/** @} */
4090
4091
4092	/** @name Selector Descriptor Types.
4093	* @{
4094	*/
4095
4096	/** @name Non-System Selector Types.
4097	* @{ */
4098	/** Code(=set)/Data(=clear) bit. */
4099	#define X86_SEL_TYPE_CODE 8
4100	/** Memory(=set)/System(=clear) bit. */
4101	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4102	/** Accessed bit. */
4103	#define X86_SEL_TYPE_ACCESSED 1
4104	/** Expand down bit (for data selectors only). */
4105	#define X86_SEL_TYPE_DOWN 4
4106	/** Conforming bit (for code selectors only). */
4107	#define X86_SEL_TYPE_CONF 4
4108	/** Write bit (for data selectors only). */
4109	#define X86_SEL_TYPE_WRITE 2
4110	/** Read bit (for code selectors only). */
4111	#define X86_SEL_TYPE_READ 2
4112	/** The bit number of the code segment read bit (relative to u4Type). */
4113	#define X86_SEL_TYPE_READ_BIT 1
4114
4115	/** Read only selector type. */
4116	#define X86_SEL_TYPE_RO 0
4117	/** Accessed read only selector type. */
4118	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
4119	/** Read write selector type. */
4120	#define X86_SEL_TYPE_RW 2
4121	/** Accessed read write selector type. */
4122	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
4123	/** Expand down read only selector type. */
4124	#define X86_SEL_TYPE_RO_DOWN 4
4125	/** Accessed expand down read only selector type. */
4126	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
4127	/** Expand down read write selector type. */
4128	#define X86_SEL_TYPE_RW_DOWN 6
4129	/** Accessed expand down read write selector type. */
4130	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
4131	/** Execute only selector type. */
4132	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
4133	/** Accessed execute only selector type. */
4134	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4135	/** Execute and read selector type. */
4136	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
4137	/** Accessed execute and read selector type. */
4138	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4139	/** Conforming execute only selector type. */
4140	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
4141	/** Accessed Conforming execute only selector type. */
4142	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4143	/** Conforming execute and write selector type. */
4144	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
4145	/** Accessed Conforming execute and write selector type. */
4146	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4147	/** @} */
4148
4149
4150	/** @name System Selector Types.
4151	* @{ */
4152	/** The TSS busy bit mask. */
4153	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4154
4155	/** Undefined system selector type. */
4156	#define X86_SEL_TYPE_SYS_UNDEFINED 0
4157	/** 286 TSS selector. */
4158	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4159	/** LDT selector. */
4160	#define X86_SEL_TYPE_SYS_LDT 2
4161	/** 286 TSS selector - Busy. */
4162	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4163	/** 286 Callgate selector. */
4164	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4165	/** Taskgate selector. */
4166	#define X86_SEL_TYPE_SYS_TASK_GATE 5
4167	/** 286 Interrupt gate selector. */
4168	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4169	/** 286 Trapgate selector. */
4170	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4171	/** Undefined system selector. */
4172	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4173	/** 386 TSS selector. */
4174	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4175	/** Undefined system selector. */
4176	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4177	/** 386 TSS selector - Busy. */
4178	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4179	/** 386 Callgate selector. */
4180	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4181	/** Undefined system selector. */
4182	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4183	/** 386 Interruptgate selector. */
4184	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4185	/** 386 Trapgate selector. */
4186	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4187	/** @} */
4188
4189	/** @name AMD64 System Selector Types.
4190	* @{ */
4191	/** LDT selector. */
4192	#define AMD64_SEL_TYPE_SYS_LDT 2
4193	/** TSS selector - Busy. */
4194	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4195	/** TSS selector - Busy. */
4196	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4197	/** Callgate selector. */
4198	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4199	/** Interruptgate selector. */
4200	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4201	/** Trapgate selector. */
4202	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4203	/** @} */
4204
4205	/** @} */
4206
4207
4208	/** @name Descriptor Table Entry Flag Masks.
4209	* These are for the 2nd 32-bit word of a descriptor.
4210	* @{ */
4211	/** Bits 8-11 - TYPE - Descriptor type mask. */
4212	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
4213	/** Bit 12 - S - System (=0) or Code/Data (=1). */
4214	#define X86_DESC_S RT_BIT_32(12)
4215	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4216	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
4217	/** Bit 15 - P - Present. */
4218	#define X86_DESC_P RT_BIT_32(15)
4219	/** Bit 20 - AVL - Available for system software. */
4220	#define X86_DESC_AVL RT_BIT_32(20)
4221	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4222	#define X86_DESC_DB RT_BIT_32(22)
4223	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4224	* used, if clear byte. */
4225	#define X86_DESC_G RT_BIT_32(23)
4226	/** @} */
4227
4228	/** @} */
4229
4230
4231	/** @name Task Segments.
4232	* @{
4233	*/
4234
4235	/**
4236	* The minimum TSS descriptor limit for 286 tasks.
4237	*/
4238	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4239
4240	/**
4241	* The minimum TSS descriptor segment limit for 386 tasks.
4242	*/
4243	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4244
4245	/**
4246	* 16-bit Task Segment (TSS).
4247	*/
4248	#pragma pack(1)
4249	typedef struct X86TSS16
4250	{
4251	/** Back link to previous task. (static) */
4252	RTSEL selPrev;
4253	/** Ring-0 stack pointer. (static) */
4254	uint16_t sp0;
4255	/** Ring-0 stack segment. (static) */
4256	RTSEL ss0;
4257	/** Ring-1 stack pointer. (static) */
4258	uint16_t sp1;
4259	/** Ring-1 stack segment. (static) */
4260	RTSEL ss1;
4261	/** Ring-2 stack pointer. (static) */
4262	uint16_t sp2;
4263	/** Ring-2 stack segment. (static) */
4264	RTSEL ss2;
4265	/** IP before task switch. */
4266	uint16_t ip;
4267	/** FLAGS before task switch. */
4268	uint16_t flags;
4269	/** AX before task switch. */
4270	uint16_t ax;
4271	/** CX before task switch. */
4272	uint16_t cx;
4273	/** DX before task switch. */
4274	uint16_t dx;
4275	/** BX before task switch. */
4276	uint16_t bx;
4277	/** SP before task switch. */
4278	uint16_t sp;
4279	/** BP before task switch. */
4280	uint16_t bp;
4281	/** SI before task switch. */
4282	uint16_t si;
4283	/** DI before task switch. */
4284	uint16_t di;
4285	/** ES before task switch. */
4286	RTSEL es;
4287	/** CS before task switch. */
4288	RTSEL cs;
4289	/** SS before task switch. */
4290	RTSEL ss;
4291	/** DS before task switch. */
4292	RTSEL ds;
4293	/** LDTR before task switch. */
4294	RTSEL selLdt;
4295	} X86TSS16;
4296	#ifndef VBOX_FOR_DTRACE_LIB
4297	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4298	#endif
4299	#pragma pack()
4300	/** Pointer to a 16-bit task segment. */
4301	typedef X86TSS16 *PX86TSS16;
4302	/** Pointer to a const 16-bit task segment. */
4303	typedef const X86TSS16 *PCX86TSS16;
4304
4305
4306	/**
4307	* 32-bit Task Segment (TSS).
4308	*/
4309	#pragma pack(1)
4310	typedef struct X86TSS32
4311	{
4312	/** Back link to previous task. (static) */
4313	RTSEL selPrev;
4314	uint16_t padding1;
4315	/** Ring-0 stack pointer. (static) */
4316	uint32_t esp0;
4317	/** Ring-0 stack segment. (static) */
4318	RTSEL ss0;
4319	uint16_t padding_ss0;
4320	/** Ring-1 stack pointer. (static) */
4321	uint32_t esp1;
4322	/** Ring-1 stack segment. (static) */
4323	RTSEL ss1;
4324	uint16_t padding_ss1;
4325	/** Ring-2 stack pointer. (static) */
4326	uint32_t esp2;
4327	/** Ring-2 stack segment. (static) */
4328	RTSEL ss2;
4329	uint16_t padding_ss2;
4330	/** Page directory for the task. (static) */
4331	uint32_t cr3;
4332	/** EIP before task switch. */
4333	uint32_t eip;
4334	/** EFLAGS before task switch. */
4335	uint32_t eflags;
4336	/** EAX before task switch. */
4337	uint32_t eax;
4338	/** ECX before task switch. */
4339	uint32_t ecx;
4340	/** EDX before task switch. */
4341	uint32_t edx;
4342	/** EBX before task switch. */
4343	uint32_t ebx;
4344	/** ESP before task switch. */
4345	uint32_t esp;
4346	/** EBP before task switch. */
4347	uint32_t ebp;
4348	/** ESI before task switch. */
4349	uint32_t esi;
4350	/** EDI before task switch. */
4351	uint32_t edi;
4352	/** ES before task switch. */
4353	RTSEL es;
4354	uint16_t padding_es;
4355	/** CS before task switch. */
4356	RTSEL cs;
4357	uint16_t padding_cs;
4358	/** SS before task switch. */
4359	RTSEL ss;
4360	uint16_t padding_ss;
4361	/** DS before task switch. */
4362	RTSEL ds;
4363	uint16_t padding_ds;
4364	/** FS before task switch. */
4365	RTSEL fs;
4366	uint16_t padding_fs;
4367	/** GS before task switch. */
4368	RTSEL gs;
4369	uint16_t padding_gs;
4370	/** LDTR before task switch. */
4371	RTSEL selLdt;
4372	uint16_t padding_ldt;
4373	/** Debug trap flag */
4374	uint16_t fDebugTrap;
4375	/** Offset relative to the TSS of the start of the I/O Bitmap
4376	* and the end of the interrupt redirection bitmap. */
4377	uint16_t offIoBitmap;
4378	} X86TSS32;
4379	#pragma pack()
4380	/** Pointer to task segment. */
4381	typedef X86TSS32 *PX86TSS32;
4382	/** Pointer to const task segment. */
4383	typedef const X86TSS32 *PCX86TSS32;
4384	#ifndef VBOX_FOR_DTRACE_LIB
4385	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4386	AssertCompileMemberOffset(X86TSS32, cr3, 28);
4387	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4388	#endif
4389
4390	/**
4391	* 64-bit Task segment.
4392	*/
4393	#pragma pack(1)
4394	typedef struct X86TSS64
4395	{
4396	/** Reserved. */
4397	uint32_t u32Reserved;
4398	/** Ring-0 stack pointer. (static) */
4399	uint64_t rsp0;
4400	/** Ring-1 stack pointer. (static) */
4401	uint64_t rsp1;
4402	/** Ring-2 stack pointer. (static) */
4403	uint64_t rsp2;
4404	/** Reserved. */
4405	uint32_t u32Reserved2[2];
4406	/* IST */
4407	uint64_t ist1;
4408	uint64_t ist2;
4409	uint64_t ist3;
4410	uint64_t ist4;
4411	uint64_t ist5;
4412	uint64_t ist6;
4413	uint64_t ist7;
4414	/* Reserved. */
4415	uint16_t u16Reserved[5];
4416	/** Offset relative to the TSS of the start of the I/O Bitmap
4417	* and the end of the interrupt redirection bitmap. */
4418	uint16_t offIoBitmap;
4419	} X86TSS64;
4420	#pragma pack()
4421	/** Pointer to a 64-bit task segment. */
4422	typedef X86TSS64 *PX86TSS64;
4423	/** Pointer to a const 64-bit task segment. */
4424	typedef const X86TSS64 *PCX86TSS64;
4425	#ifndef VBOX_FOR_DTRACE_LIB
4426	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4427	#endif
4428
4429	/** @} */
4430
4431
4432	/** @name Selectors.
4433	* @{
4434	*/
4435
4436	/**
4437	* The shift used to convert a selector from and to index an index (C).
4438	*/
4439	#define X86_SEL_SHIFT 3
4440
4441	/**
4442	* The mask used to mask off the table indicator and RPL of an selector.
4443	*/
4444	#define X86_SEL_MASK 0xfff8U
4445
4446	/**
4447	* The mask used to mask off the RPL of an selector.
4448	* This is suitable for checking for NULL selectors.
4449	*/
4450	#define X86_SEL_MASK_OFF_RPL 0xfffcU
4451
4452	/**
4453	* The bit indicating that a selector is in the LDT and not in the GDT.
4454	*/
4455	#define X86_SEL_LDT 0x0004U
4456
4457	/**
4458	* The bit mask for getting the RPL of a selector.
4459	*/
4460	#define X86_SEL_RPL 0x0003U
4461
4462	/**
4463	* The mask covering both RPL and LDT.
4464	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4465	* checks.
4466	*/
4467	#define X86_SEL_RPL_LDT 0x0007U
4468
4469	/** @} */
4470
4471
4472	/**
4473	* x86 Exceptions/Faults/Traps.
4474	*/
4475	typedef enum X86XCPT
4476	{
4477	/** \#DE - Divide error. */
4478	X86_XCPT_DE = 0x00,
4479	/** \#DB - Debug event (single step, DRx, ..) */
4480	X86_XCPT_DB = 0x01,
4481	/** NMI - Non-Maskable Interrupt */
4482	X86_XCPT_NMI = 0x02,
4483	/** \#BP - Breakpoint (INT3). */
4484	X86_XCPT_BP = 0x03,
4485	/** \#OF - Overflow (INTO). */
4486	X86_XCPT_OF = 0x04,
4487	/** \#BR - Bound range exceeded (BOUND). */
4488	X86_XCPT_BR = 0x05,
4489	/** \#UD - Undefined opcode. */
4490	X86_XCPT_UD = 0x06,
4491	/** \#NM - Device not available (math coprocessor device). */
4492	X86_XCPT_NM = 0x07,
4493	/** \#DF - Double fault. */
4494	X86_XCPT_DF = 0x08,
4495	/** ??? - Coprocessor segment overrun (obsolete). */
4496	X86_XCPT_CO_SEG_OVERRUN = 0x09,
4497	/** \#TS - Taskswitch (TSS). */
4498	X86_XCPT_TS = 0x0a,
4499	/** \#NP - Segment no present. */
4500	X86_XCPT_NP = 0x0b,
4501	/** \#SS - Stack segment fault. */
4502	X86_XCPT_SS = 0x0c,
4503	/** \#GP - General protection fault. */
4504	X86_XCPT_GP = 0x0d,
4505	/** \#PF - Page fault. */
4506	X86_XCPT_PF = 0x0e,
4507	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4508	/** \#MF - Math fault (FPU). */
4509	X86_XCPT_MF = 0x10,
4510	/** \#AC - Alignment check. */
4511	X86_XCPT_AC = 0x11,
4512	/** \#MC - Machine check. */
4513	X86_XCPT_MC = 0x12,
4514	/** \#XF - SIMD Floating-Point Exception. */
4515	X86_XCPT_XF = 0x13,
4516	/** \#VE - Virtualization Exception (Intel only). */
4517	X86_XCPT_VE = 0x14,
4518	/** \#CP - Control Protection Exception (Intel only). */
4519	X86_XCPT_CP = 0x15,
4520	/** \#VC - VMM Communication Exception (AMD only). */
4521	X86_XCPT_VC = 0x1d,
4522	/** \#SX - Security Exception (AMD only). */
4523	X86_XCPT_SX = 0x1e
4524	} X86XCPT;
4525	/** Pointer to a x86 exception code. */
4526	typedef X86XCPT *PX86XCPT;
4527	/** Pointer to a const x86 exception code. */
4528	typedef const X86XCPT *PCX86XCPT;
4529	/** The last valid (currently reserved) exception value. */
4530	#define X86_XCPT_LAST 0x1f
4531
4532
4533	/** @name Trap Error Codes
4534	* @{
4535	*/
4536	/** External indicator. */
4537	#define X86_TRAP_ERR_EXTERNAL 1
4538	/** IDT indicator. */
4539	#define X86_TRAP_ERR_IDT 2
4540	/** Descriptor table indicator - If set LDT, if clear GDT. */
4541	#define X86_TRAP_ERR_TI 4
4542	/** Mask for getting the selector. */
4543	#define X86_TRAP_ERR_SEL_MASK 0xfff8
4544	/** Shift for getting the selector table index (C type index). */
4545	#define X86_TRAP_ERR_SEL_SHIFT 3
4546	/** @} */
4547
4548
4549	/** @name \#PF Trap Error Codes
4550	* @{
4551	*/
4552	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4553	#define X86_TRAP_PF_P RT_BIT_32(0)
4554	/** Bit 1 - R/W - Read (clear) or write (set) access. */
4555	#define X86_TRAP_PF_RW RT_BIT_32(1)
4556	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4557	#define X86_TRAP_PF_US RT_BIT_32(2)
4558	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4559	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4560	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4561	#define X86_TRAP_PF_ID RT_BIT_32(4)
4562	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4563	#define X86_TRAP_PF_PK RT_BIT_32(5)
4564	/** @} */
4565
4566	#pragma pack(1)
4567	/**
4568	* 16-bit IDTR.
4569	*/
4570	typedef struct X86IDTR16
4571	{
4572	/** Offset. */
4573	uint16_t offSel;
4574	/** Selector. */
4575	uint16_t uSel;
4576	} X86IDTR16, *PX86IDTR16;
4577	#pragma pack()
4578
4579	#pragma pack(1)
4580	/**
4581	* 32-bit IDTR/GDTR.
4582	*/
4583	typedef struct X86XDTR32
4584	{
4585	/** Size of the descriptor table. */
4586	uint16_t cb;
4587	/** Address of the descriptor table. */
4588	#ifndef VBOX_FOR_DTRACE_LIB
4589	uint32_t uAddr;
4590	#else
4591	uint16_t au16Addr[2];
4592	#endif
4593	} X86XDTR32, *PX86XDTR32;
4594	#pragma pack()
4595
4596	#pragma pack(1)
4597	/**
4598	* 64-bit IDTR/GDTR.
4599	*/
4600	typedef struct X86XDTR64
4601	{
4602	/** Size of the descriptor table. */
4603	uint16_t cb;
4604	/** Address of the descriptor table. */
4605	#ifndef VBOX_FOR_DTRACE_LIB
4606	uint64_t uAddr;
4607	#else
4608	uint16_t au16Addr[4];
4609	#endif
4610	} X86XDTR64, *PX86XDTR64;
4611	#pragma pack()
4612
4613
4614	/** @name ModR/M
4615	* @{ */
4616	#define X86_MODRM_RM_MASK UINT8_C(0x07)
4617	#define X86_MODRM_REG_MASK UINT8_C(0x38)
4618	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4619	#define X86_MODRM_REG_SHIFT 3
4620	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4621	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4622	#define X86_MODRM_MOD_SHIFT 6
4623	#ifndef VBOX_FOR_DTRACE_LIB
4624	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
4625	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4626	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4627	/** @def X86_MODRM_MAKE
4628	* @param a_Mod The mod value (0..3).
4629	* @param a_Reg The register value (0..7).
4630	* @param a_RegMem The register or memory value (0..7). */
4631	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
4632	#endif
4633	/** @} */
4634
4635	/** @name SIB
4636	* @{ */
4637	#define X86_SIB_BASE_MASK UINT8_C(0x07)
4638	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4639	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4640	#define X86_SIB_INDEX_SHIFT 3
4641	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4642	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4643	#define X86_SIB_SCALE_SHIFT 6
4644	#ifndef VBOX_FOR_DTRACE_LIB
4645	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
4646	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4647	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4648	#endif
4649	/** @} */
4650
4651	/** @name General register indexes.
4652	* @{ */
4653	#define X86_GREG_xAX 0
4654	#define X86_GREG_xCX 1
4655	#define X86_GREG_xDX 2
4656	#define X86_GREG_xBX 3
4657	#define X86_GREG_xSP 4
4658	#define X86_GREG_xBP 5
4659	#define X86_GREG_xSI 6
4660	#define X86_GREG_xDI 7
4661	#define X86_GREG_x8 8
4662	#define X86_GREG_x9 9
4663	#define X86_GREG_x10 10
4664	#define X86_GREG_x11 11
4665	#define X86_GREG_x12 12
4666	#define X86_GREG_x13 13
4667	#define X86_GREG_x14 14
4668	#define X86_GREG_x15 15
4669	/** @} */
4670	/** General register count. */
4671	#define X86_GREG_COUNT 16
4672
4673	/** @name X86_SREG_XXX - Segment register indexes.
4674	* @{ */
4675	#define X86_SREG_ES 0
4676	#define X86_SREG_CS 1
4677	#define X86_SREG_SS 2
4678	#define X86_SREG_DS 3
4679	#define X86_SREG_FS 4
4680	#define X86_SREG_GS 5
4681	/** @} */
4682	/** Segment register count. */
4683	#define X86_SREG_COUNT 6
4684
4685
4686	/** @name X86_OP_XXX - Prefixes
4687	* @{ */
4688	#define X86_OP_PRF_CS UINT8_C(0x2e)
4689	#define X86_OP_PRF_SS UINT8_C(0x36)
4690	#define X86_OP_PRF_DS UINT8_C(0x3e)
4691	#define X86_OP_PRF_ES UINT8_C(0x26)
4692	#define X86_OP_PRF_FS UINT8_C(0x64)
4693	#define X86_OP_PRF_GS UINT8_C(0x65)
4694	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4695	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4696	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4697	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4698	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4699	#define X86_OP_REX_B UINT8_C(0x41)
4700	#define X86_OP_REX_X UINT8_C(0x42)
4701	#define X86_OP_REX_R UINT8_C(0x44)
4702	#define X86_OP_REX_W UINT8_C(0x48)
4703	/** @} */
4704
4705
4706	/** @} */
4707
4708	#endif /* !IPRT_INCLUDED_x86_h */
4709

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source: vbox/trunk/include/iprt/x86.h@ 94480

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