VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 82574

Last change on this file since 82574 was 82574, checked in by vboxsync, 5 years ago

x86.h: Added CR4.UMIP and CR4.CET.
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File size: 172.2 KB
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1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2019 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef IPRT_INCLUDED_x86_h
29#define IPRT_INCLUDED_x86_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#ifndef VBOX_FOR_DTRACE_LIB
35# include <iprt/types.h>
36# include <iprt/assert.h>
37#else
38# pragma D depends_on library vbox-types.d
39#endif
40
41/* Workaround for Solaris sys/regset.h defining CS, DS */
42#ifdef RT_OS_SOLARIS
43# undef CS
44# undef DS
45#endif
46
47/** @defgroup grp_rt_x86 x86 Types and Definitions
48 * @ingroup grp_rt
49 * @{
50 */
51
52#ifndef VBOX_FOR_DTRACE_LIB
53/**
54 * EFLAGS Bits.
55 */
56typedef struct X86EFLAGSBITS
57{
58 /** Bit 0 - CF - Carry flag - Status flag. */
59 unsigned u1CF : 1;
60 /** Bit 1 - 1 - Reserved flag. */
61 unsigned u1Reserved0 : 1;
62 /** Bit 2 - PF - Parity flag - Status flag. */
63 unsigned u1PF : 1;
64 /** Bit 3 - 0 - Reserved flag. */
65 unsigned u1Reserved1 : 1;
66 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
67 unsigned u1AF : 1;
68 /** Bit 5 - 0 - Reserved flag. */
69 unsigned u1Reserved2 : 1;
70 /** Bit 6 - ZF - Zero flag - Status flag. */
71 unsigned u1ZF : 1;
72 /** Bit 7 - SF - Signed flag - Status flag. */
73 unsigned u1SF : 1;
74 /** Bit 8 - TF - Trap flag - System flag. */
75 unsigned u1TF : 1;
76 /** Bit 9 - IF - Interrupt flag - System flag. */
77 unsigned u1IF : 1;
78 /** Bit 10 - DF - Direction flag - Control flag. */
79 unsigned u1DF : 1;
80 /** Bit 11 - OF - Overflow flag - Status flag. */
81 unsigned u1OF : 1;
82 /** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
83 unsigned u2IOPL : 2;
84 /** Bit 14 - NT - Nested task flag - System flag. */
85 unsigned u1NT : 1;
86 /** Bit 15 - 0 - Reserved flag. */
87 unsigned u1Reserved3 : 1;
88 /** Bit 16 - RF - Resume flag - System flag. */
89 unsigned u1RF : 1;
90 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
91 unsigned u1VM : 1;
92 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
93 unsigned u1AC : 1;
94 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
95 unsigned u1VIF : 1;
96 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
97 unsigned u1VIP : 1;
98 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
99 unsigned u1ID : 1;
100 /** Bit 22-31 - 0 - Reserved flag. */
101 unsigned u10Reserved4 : 10;
102} X86EFLAGSBITS;
103/** Pointer to EFLAGS bits. */
104typedef X86EFLAGSBITS *PX86EFLAGSBITS;
105/** Pointer to const EFLAGS bits. */
106typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
107#endif /* !VBOX_FOR_DTRACE_LIB */
108
109/**
110 * EFLAGS.
111 */
112typedef union X86EFLAGS
113{
114 /** The plain unsigned view. */
115 uint32_t u;
116#ifndef VBOX_FOR_DTRACE_LIB
117 /** The bitfield view. */
118 X86EFLAGSBITS Bits;
119#endif
120 /** The 8-bit view. */
121 uint8_t au8[4];
122 /** The 16-bit view. */
123 uint16_t au16[2];
124 /** The 32-bit view. */
125 uint32_t au32[1];
126 /** The 32-bit view. */
127 uint32_t u32;
128} X86EFLAGS;
129/** Pointer to EFLAGS. */
130typedef X86EFLAGS *PX86EFLAGS;
131/** Pointer to const EFLAGS. */
132typedef const X86EFLAGS *PCX86EFLAGS;
133
134/**
135 * RFLAGS (32 upper bits are reserved).
136 */
137typedef union X86RFLAGS
138{
139 /** The plain unsigned view. */
140 uint64_t u;
141#ifndef VBOX_FOR_DTRACE_LIB
142 /** The bitfield view. */
143 X86EFLAGSBITS Bits;
144#endif
145 /** The 8-bit view. */
146 uint8_t au8[8];
147 /** The 16-bit view. */
148 uint16_t au16[4];
149 /** The 32-bit view. */
150 uint32_t au32[2];
151 /** The 64-bit view. */
152 uint64_t au64[1];
153 /** The 64-bit view. */
154 uint64_t u64;
155} X86RFLAGS;
156/** Pointer to RFLAGS. */
157typedef X86RFLAGS *PX86RFLAGS;
158/** Pointer to const RFLAGS. */
159typedef const X86RFLAGS *PCX86RFLAGS;
160
161
162/** @name EFLAGS
163 * @{
164 */
165/** Bit 0 - CF - Carry flag - Status flag. */
166#define X86_EFL_CF RT_BIT_32(0)
167#define X86_EFL_CF_BIT 0
168/** Bit 1 - Reserved, reads as 1. */
169#define X86_EFL_1 RT_BIT_32(1)
170/** Bit 2 - PF - Parity flag - Status flag. */
171#define X86_EFL_PF RT_BIT_32(2)
172/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
173#define X86_EFL_AF RT_BIT_32(4)
174#define X86_EFL_AF_BIT 4
175/** Bit 6 - ZF - Zero flag - Status flag. */
176#define X86_EFL_ZF RT_BIT_32(6)
177#define X86_EFL_ZF_BIT 6
178/** Bit 7 - SF - Signed flag - Status flag. */
179#define X86_EFL_SF RT_BIT_32(7)
180#define X86_EFL_SF_BIT 7
181/** Bit 8 - TF - Trap flag - System flag. */
182#define X86_EFL_TF RT_BIT_32(8)
183/** Bit 9 - IF - Interrupt flag - System flag. */
184#define X86_EFL_IF RT_BIT_32(9)
185/** Bit 10 - DF - Direction flag - Control flag. */
186#define X86_EFL_DF RT_BIT_32(10)
187/** Bit 11 - OF - Overflow flag - Status flag. */
188#define X86_EFL_OF RT_BIT_32(11)
189#define X86_EFL_OF_BIT 11
190/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
191#define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
192/** Bit 14 - NT - Nested task flag - System flag. */
193#define X86_EFL_NT RT_BIT_32(14)
194/** Bit 16 - RF - Resume flag - System flag. */
195#define X86_EFL_RF RT_BIT_32(16)
196/** Bit 17 - VM - Virtual 8086 mode - System flag. */
197#define X86_EFL_VM RT_BIT_32(17)
198/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
199#define X86_EFL_AC RT_BIT_32(18)
200/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
201#define X86_EFL_VIF RT_BIT_32(19)
202/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
203#define X86_EFL_VIP RT_BIT_32(20)
204/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
205#define X86_EFL_ID RT_BIT_32(21)
206/** All live bits. */
207#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
208/** Read as 1 bits. */
209#define X86_EFL_RA1_MASK RT_BIT_32(1)
210/** IOPL shift. */
211#define X86_EFL_IOPL_SHIFT 12
212/** The IOPL level from the flags. */
213#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
214/** Bits restored by popf */
215#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
216 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
217/** Bits restored by popf */
218#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
219 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
220/** The status bits commonly updated by arithmetic instructions. */
221#define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
222/** @} */
223
224
225/** CPUID Feature information - ECX.
226 * CPUID query with EAX=1.
227 */
228#ifndef VBOX_FOR_DTRACE_LIB
229typedef struct X86CPUIDFEATECX
230{
231 /** Bit 0 - SSE3 - Supports SSE3 or not. */
232 unsigned u1SSE3 : 1;
233 /** Bit 1 - PCLMULQDQ. */
234 unsigned u1PCLMULQDQ : 1;
235 /** Bit 2 - DS Area 64-bit layout. */
236 unsigned u1DTE64 : 1;
237 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
238 unsigned u1Monitor : 1;
239 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
240 unsigned u1CPLDS : 1;
241 /** Bit 5 - VMX - Virtual Machine Technology. */
242 unsigned u1VMX : 1;
243 /** Bit 6 - SMX: Safer Mode Extensions. */
244 unsigned u1SMX : 1;
245 /** Bit 7 - EST - Enh. SpeedStep Tech. */
246 unsigned u1EST : 1;
247 /** Bit 8 - TM2 - Terminal Monitor 2. */
248 unsigned u1TM2 : 1;
249 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
250 unsigned u1SSSE3 : 1;
251 /** Bit 10 - CNTX-ID - L1 Context ID. */
252 unsigned u1CNTXID : 1;
253 /** Bit 11 - Reserved. */
254 unsigned u1Reserved1 : 1;
255 /** Bit 12 - FMA. */
256 unsigned u1FMA : 1;
257 /** Bit 13 - CX16 - CMPXCHG16B. */
258 unsigned u1CX16 : 1;
259 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
260 unsigned u1TPRUpdate : 1;
261 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
262 unsigned u1PDCM : 1;
263 /** Bit 16 - Reserved. */
264 unsigned u1Reserved2 : 1;
265 /** Bit 17 - PCID - Process-context identifiers. */
266 unsigned u1PCID : 1;
267 /** Bit 18 - Direct Cache Access. */
268 unsigned u1DCA : 1;
269 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
270 unsigned u1SSE4_1 : 1;
271 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
272 unsigned u1SSE4_2 : 1;
273 /** Bit 21 - x2APIC. */
274 unsigned u1x2APIC : 1;
275 /** Bit 22 - MOVBE - Supports MOVBE. */
276 unsigned u1MOVBE : 1;
277 /** Bit 23 - POPCNT - Supports POPCNT. */
278 unsigned u1POPCNT : 1;
279 /** Bit 24 - TSC-Deadline. */
280 unsigned u1TSCDEADLINE : 1;
281 /** Bit 25 - AES. */
282 unsigned u1AES : 1;
283 /** Bit 26 - XSAVE - Supports XSAVE. */
284 unsigned u1XSAVE : 1;
285 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
286 unsigned u1OSXSAVE : 1;
287 /** Bit 28 - AVX - Supports AVX instruction extensions. */
288 unsigned u1AVX : 1;
289 /** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
290 unsigned u1F16C : 1;
291 /** Bit 30 - RDRAND - Supports RDRAND. */
292 unsigned u1RDRAND : 1;
293 /** Bit 31 - Hypervisor present (we're a guest). */
294 unsigned u1HVP : 1;
295} X86CPUIDFEATECX;
296#else /* VBOX_FOR_DTRACE_LIB */
297typedef uint32_t X86CPUIDFEATECX;
298#endif /* VBOX_FOR_DTRACE_LIB */
299/** Pointer to CPUID Feature Information - ECX. */
300typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
301/** Pointer to const CPUID Feature Information - ECX. */
302typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
303
304
305/** CPUID Feature Information - EDX.
306 * CPUID query with EAX=1.
307 */
308#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
309typedef struct X86CPUIDFEATEDX
310{
311 /** Bit 0 - FPU - x87 FPU on Chip. */
312 unsigned u1FPU : 1;
313 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
314 unsigned u1VME : 1;
315 /** Bit 2 - DE - Debugging extensions. */
316 unsigned u1DE : 1;
317 /** Bit 3 - PSE - Page Size Extension. */
318 unsigned u1PSE : 1;
319 /** Bit 4 - TSC - Time Stamp Counter. */
320 unsigned u1TSC : 1;
321 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
322 unsigned u1MSR : 1;
323 /** Bit 6 - PAE - Physical Address Extension. */
324 unsigned u1PAE : 1;
325 /** Bit 7 - MCE - Machine Check Exception. */
326 unsigned u1MCE : 1;
327 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
328 unsigned u1CX8 : 1;
329 /** Bit 9 - APIC - APIC On-Chip. */
330 unsigned u1APIC : 1;
331 /** Bit 10 - Reserved. */
332 unsigned u1Reserved1 : 1;
333 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
334 unsigned u1SEP : 1;
335 /** Bit 12 - MTRR - Memory Type Range Registers. */
336 unsigned u1MTRR : 1;
337 /** Bit 13 - PGE - PTE Global Bit. */
338 unsigned u1PGE : 1;
339 /** Bit 14 - MCA - Machine Check Architecture. */
340 unsigned u1MCA : 1;
341 /** Bit 15 - CMOV - Conditional Move Instructions. */
342 unsigned u1CMOV : 1;
343 /** Bit 16 - PAT - Page Attribute Table. */
344 unsigned u1PAT : 1;
345 /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
346 unsigned u1PSE36 : 1;
347 /** Bit 18 - PSN - Processor Serial Number. */
348 unsigned u1PSN : 1;
349 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
350 unsigned u1CLFSH : 1;
351 /** Bit 20 - Reserved. */
352 unsigned u1Reserved2 : 1;
353 /** Bit 21 - DS - Debug Store. */
354 unsigned u1DS : 1;
355 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
356 unsigned u1ACPI : 1;
357 /** Bit 23 - MMX - Intel MMX 'Technology'. */
358 unsigned u1MMX : 1;
359 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
360 unsigned u1FXSR : 1;
361 /** Bit 25 - SSE - SSE Support. */
362 unsigned u1SSE : 1;
363 /** Bit 26 - SSE2 - SSE2 Support. */
364 unsigned u1SSE2 : 1;
365 /** Bit 27 - SS - Self Snoop. */
366 unsigned u1SS : 1;
367 /** Bit 28 - HTT - Hyper-Threading Technology. */
368 unsigned u1HTT : 1;
369 /** Bit 29 - TM - Thermal Monitor. */
370 unsigned u1TM : 1;
371 /** Bit 30 - Reserved - . */
372 unsigned u1Reserved3 : 1;
373 /** Bit 31 - PBE - Pending Break Enabled. */
374 unsigned u1PBE : 1;
375} X86CPUIDFEATEDX;
376#else /* VBOX_FOR_DTRACE_LIB */
377typedef uint32_t X86CPUIDFEATEDX;
378#endif /* VBOX_FOR_DTRACE_LIB */
379/** Pointer to CPUID Feature Information - EDX. */
380typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
381/** Pointer to const CPUID Feature Information - EDX. */
382typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
383
384/** @name CPUID Vendor information.
385 * CPUID query with EAX=0.
386 * @{
387 */
388#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
389#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
390#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
391
392#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
393#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
394#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
395
396#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
397#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
398#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
399
400#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
401#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
402#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
403
404#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
405#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
406#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
407/** @} */
408
409
410/** @name CPUID Feature information.
411 * CPUID query with EAX=1.
412 * @{
413 */
414/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
415#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
416/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
417#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
418/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
419#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
420/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
421#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
422/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
423#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
424/** ECX Bit 5 - VMX - Virtual Machine Technology. */
425#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
426/** ECX Bit 6 - SMX - Safer Mode Extensions. */
427#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
428/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
429#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
430/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
431#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
432/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
433#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
434/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
435#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
436/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
437 * See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
438#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
439/** ECX Bit 12 - FMA. */
440#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
441/** ECX Bit 13 - CX16 - CMPXCHG16B. */
442#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
443/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
444#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
445/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
446#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
447/** ECX Bit 17 - PCID - Process-context identifiers. */
448#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
449/** ECX Bit 18 - DCA - Direct Cache Access. */
450#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
451/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
452#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
453/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
454#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
455/** ECX Bit 21 - x2APIC support. */
456#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
457/** ECX Bit 22 - MOVBE instruction. */
458#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
459/** ECX Bit 23 - POPCNT instruction. */
460#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
461/** ECX Bir 24 - TSC-Deadline. */
462#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
463/** ECX Bit 25 - AES instructions. */
464#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
465/** ECX Bit 26 - XSAVE instruction. */
466#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
467/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
468#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
469/** ECX Bit 28 - AVX. */
470#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
471/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
472#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
473/** ECX Bit 30 - RDRAND instruction. */
474#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
475/** ECX Bit 31 - Hypervisor Present (software only). */
476#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
477
478
479/** Bit 0 - FPU - x87 FPU on Chip. */
480#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
481/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
482#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
483/** Bit 2 - DE - Debugging extensions. */
484#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
485/** Bit 3 - PSE - Page Size Extension. */
486#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
487#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /**< Bit number for X86_CPUID_FEATURE_EDX_PSE. */
488/** Bit 4 - TSC - Time Stamp Counter. */
489#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
490/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
491#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
492/** Bit 6 - PAE - Physical Address Extension. */
493#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
494#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /**< Bit number for X86_CPUID_FEATURE_EDX_PAE. */
495/** Bit 7 - MCE - Machine Check Exception. */
496#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
497/** Bit 8 - CX8 - CMPXCHG8B instruction. */
498#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
499/** Bit 9 - APIC - APIC On-Chip. */
500#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
501/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
502#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
503/** Bit 12 - MTRR - Memory Type Range Registers. */
504#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
505/** Bit 13 - PGE - PTE Global Bit. */
506#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
507/** Bit 14 - MCA - Machine Check Architecture. */
508#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
509/** Bit 15 - CMOV - Conditional Move Instructions. */
510#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
511/** Bit 16 - PAT - Page Attribute Table. */
512#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
513/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
514#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
515/** Bit 18 - PSN - Processor Serial Number. */
516#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
517/** Bit 19 - CLFSH - CLFLUSH Instruction. */
518#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
519/** Bit 21 - DS - Debug Store. */
520#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
521/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
522#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
523/** Bit 23 - MMX - Intel MMX Technology. */
524#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
525/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
526#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
527/** Bit 25 - SSE - SSE Support. */
528#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
529/** Bit 26 - SSE2 - SSE2 Support. */
530#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
531/** Bit 27 - SS - Self Snoop. */
532#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
533/** Bit 28 - HTT - Hyper-Threading Technology. */
534#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
535/** Bit 29 - TM - Therm. Monitor. */
536#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
537/** Bit 31 - PBE - Pending Break Enabled. */
538#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
539/** @} */
540
541/** @name CPUID mwait/monitor information.
542 * CPUID query with EAX=5.
543 * @{
544 */
545/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
546#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
547/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
548#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
549/** @} */
550
551
552/** @name CPUID Structured Extended Feature information.
553 * CPUID query with EAX=7.
554 * @{
555 */
556/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
557#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
558/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
559#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
560/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
561#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
562/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
563#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
564/** EBX Bit 4 - HLE - Hardware Lock Elision. */
565#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
566/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
567#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
568/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
569#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
570/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
571#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
572/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
573#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
574/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
575#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
576/** EBX Bit 10 - INVPCID - Supports INVPCID. */
577#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
578/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
579#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
580/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
581#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
582/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
583#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
584/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
585#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
586/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
587#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
588/** EBX Bit 16 - AVX512F - Supports AVX512F. */
589#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
590/** EBX Bit 18 - RDSEED - Supports RDSEED. */
591#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
592/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
593#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
594/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
595#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
596/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
597#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
598/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
599#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
600/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
601#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
602/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
603#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
604/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
605#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
606/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
607#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
608
609/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
610#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
611/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
612#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
613/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
614#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
615/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
616#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
617/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
618#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
619/** ECX Bit 22 - RDPID - Support pread process ID. */
620#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
621/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
622#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
623
624/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
625#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
626/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
627 * IBPB command in IA32_PRED_CMD. */
628#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
629/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
630#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
631/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
632#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
633/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
634#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
635
636/** @} */
637
638
639/** @name CPUID Extended Feature information.
640 * CPUID query with EAX=0x80000001.
641 * @{
642 */
643/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
644#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
645
646/** EDX Bit 11 - SYSCALL/SYSRET. */
647#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
648/** EDX Bit 20 - No-Execute/Execute-Disable. */
649#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
650/** EDX Bit 26 - 1 GB large page. */
651#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
652/** EDX Bit 27 - RDTSCP. */
653#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
654/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
655#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
656/** @}*/
657
658/** @name CPUID AMD Feature information.
659 * CPUID query with EAX=0x80000001.
660 * @{
661 */
662/** Bit 0 - FPU - x87 FPU on Chip. */
663#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
664/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
665#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
666/** Bit 2 - DE - Debugging extensions. */
667#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
668/** Bit 3 - PSE - Page Size Extension. */
669#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
670/** Bit 4 - TSC - Time Stamp Counter. */
671#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
672/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
673#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
674/** Bit 6 - PAE - Physical Address Extension. */
675#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
676/** Bit 7 - MCE - Machine Check Exception. */
677#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
678/** Bit 8 - CX8 - CMPXCHG8B instruction. */
679#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
680/** Bit 9 - APIC - APIC On-Chip. */
681#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
682/** Bit 12 - MTRR - Memory Type Range Registers. */
683#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
684/** Bit 13 - PGE - PTE Global Bit. */
685#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
686/** Bit 14 - MCA - Machine Check Architecture. */
687#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
688/** Bit 15 - CMOV - Conditional Move Instructions. */
689#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
690/** Bit 16 - PAT - Page Attribute Table. */
691#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
692/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
693#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
694/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
695#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
696/** Bit 23 - MMX - Intel MMX Technology. */
697#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
698/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
699#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
700/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
701#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
702/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
703#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
704/** Bit 31 - 3DNOW - AMD 3DNow. */
705#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
706
707/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
708#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
709/** Bit 2 - SVM - AMD VM extensions. */
710#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
711/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
712#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
713/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
714#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
715/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
716#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
717/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
718#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
719/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
720#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
721/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
722#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
723/** Bit 9 - OSVW - AMD OS visible workaround. */
724#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
725/** Bit 10 - IBS - Instruct based sampling. */
726#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
727/** Bit 11 - XOP - Extended operation support (see APM6). */
728#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
729/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
730#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
731/** Bit 13 - WDT - AMD Watchdog timer support. */
732#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
733/** Bit 15 - LWP - Lightweight profiling support. */
734#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
735/** Bit 16 - FMA4 - Four operand FMA instruction support. */
736#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
737/** Bit 19 - NodeId - Indicates support for
738 * MSR_C001_100C[NodeId,NodesPerProcessr]. */
739#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
740/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
741#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
742/** Bit 22 - TopologyExtensions - . */
743#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
744/** @} */
745
746
747/** @name CPUID AMD Feature information.
748 * CPUID query with EAX=0x80000007.
749 * @{
750 */
751/** Bit 0 - TS - Temperature Sensor. */
752#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
753/** Bit 1 - FID - Frequency ID Control. */
754#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
755/** Bit 2 - VID - Voltage ID Control. */
756#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
757/** Bit 3 - TTP - THERMTRIP. */
758#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
759/** Bit 4 - TM - Hardware Thermal Control. */
760#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
761/** Bit 5 - STC - Software Thermal Control. */
762#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
763/** Bit 6 - MC - 100 Mhz Multiplier Control. */
764#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
765/** Bit 7 - HWPSTATE - Hardware P-State Control. */
766#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
767/** Bit 8 - TSCINVAR - TSC Invariant. */
768#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
769/** Bit 9 - CPB - TSC Invariant. */
770#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
771/** Bit 10 - EffFreqRO - MPERF/APERF. */
772#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
773/** Bit 11 - PFI - Processor feedback interface (see EAX). */
774#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
775/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
776#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
777/** @} */
778
779
780/** @name CPUID AMD extended feature extensions ID (EBX).
781 * CPUID query with EAX=0x80000008.
782 * @{
783 */
784/** Bit 0 - CLZERO - Clear zero instruction. */
785#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
786/** Bit 1 - IRPerf - Instructions retired count support. */
787#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
788/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
789#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
790/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
791#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
792/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
793#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
794/* AMD pipeline length: 9 feature bits ;-) */
795/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
796#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
797/** @} */
798
799
800/** @name CPUID AMD SVM Feature information.
801 * CPUID query with EAX=0x8000000a.
802 * @{
803 */
804/** Bit 0 - NP - Nested Paging supported. */
805#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
806/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
807#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
808/** Bit 2 - SVML - SVM locking bit supported. */
809#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
810/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
811#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
812/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
813#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
814/** Bit 5 - VmcbClean - Support VMCB clean bits. */
815#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
816/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
817 * VMCB.TLB_Control is supported. */
818#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
819/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
820#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
821/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
822#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
823/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
824 * intercept filter cycle count threshold. */
825#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
826/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
827#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
828/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
829#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
830/** Bit 16 - VGIF - Supports virtualized GIF. */
831#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
832/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
833#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
834
835/** @} */
836
837
838/** @name CR0
839 * @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
840 * reserved flags.
841 * @{ */
842/** Bit 0 - PE - Protection Enabled */
843#define X86_CR0_PE RT_BIT_32(0)
844#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
845/** Bit 1 - MP - Monitor Coprocessor */
846#define X86_CR0_MP RT_BIT_32(1)
847#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
848/** Bit 2 - EM - Emulation. */
849#define X86_CR0_EM RT_BIT_32(2)
850#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
851/** Bit 3 - TS - Task Switch. */
852#define X86_CR0_TS RT_BIT_32(3)
853#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
854/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
855#define X86_CR0_ET RT_BIT_32(4)
856#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
857/** Bit 5 - NE - Numeric error (486+). */
858#define X86_CR0_NE RT_BIT_32(5)
859#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
860/** Bit 16 - WP - Write Protect (486+). */
861#define X86_CR0_WP RT_BIT_32(16)
862#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
863/** Bit 18 - AM - Alignment Mask (486+). */
864#define X86_CR0_AM RT_BIT_32(18)
865#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
866/** Bit 29 - NW - Not Write-though (486+). */
867#define X86_CR0_NW RT_BIT_32(29)
868#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
869/** Bit 30 - WP - Cache Disable (486+). */
870#define X86_CR0_CD RT_BIT_32(30)
871#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
872/** Bit 31 - PG - Paging. */
873#define X86_CR0_PG RT_BIT_32(31)
874#define X86_CR0_PAGING RT_BIT_32(31)
875#define X86_CR0_BIT_PG 31 /**< Bit number of X86_CR0_PG */
876/** @} */
877
878
879/** @name CR3
880 * @{ */
881/** Bit 3 - PWT - Page-level Writes Transparent. */
882#define X86_CR3_PWT RT_BIT_32(3)
883/** Bit 4 - PCD - Page-level Cache Disable. */
884#define X86_CR3_PCD RT_BIT_32(4)
885/** Bits 12-31 - - Page directory page number. */
886#define X86_CR3_PAGE_MASK (0xfffff000)
887/** Bits 5-31 - - PAE Page directory page number. */
888#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
889/** Bits 12-51 - - AMD64 Page directory page number. */
890#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
891/** @} */
892
893
894/** @name CR4
895 * @{ */
896/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
897#define X86_CR4_VME RT_BIT_32(0)
898/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
899#define X86_CR4_PVI RT_BIT_32(1)
900/** Bit 2 - TSD - Time Stamp Disable. */
901#define X86_CR4_TSD RT_BIT_32(2)
902/** Bit 3 - DE - Debugging Extensions. */
903#define X86_CR4_DE RT_BIT_32(3)
904/** Bit 4 - PSE - Page Size Extension. */
905#define X86_CR4_PSE RT_BIT_32(4)
906/** Bit 5 - PAE - Physical Address Extension. */
907#define X86_CR4_PAE RT_BIT_32(5)
908/** Bit 6 - MCE - Machine-Check Enable. */
909#define X86_CR4_MCE RT_BIT_32(6)
910/** Bit 7 - PGE - Page Global Enable. */
911#define X86_CR4_PGE RT_BIT_32(7)
912/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
913#define X86_CR4_PCE RT_BIT_32(8)
914/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
915#define X86_CR4_OSFXSR RT_BIT_32(9)
916/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
917#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
918/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
919#define X86_CR4_UMIP RT_BIT_32(11)
920/** Bit 13 - VMXE - VMX mode is enabled. */
921#define X86_CR4_VMXE RT_BIT_32(13)
922/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
923#define X86_CR4_SMXE RT_BIT_32(14)
924/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
925#define X86_CR4_FSGSBASE RT_BIT_32(16)
926/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
927#define X86_CR4_PCIDE RT_BIT_32(17)
928/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
929 * extended states. */
930#define X86_CR4_OSXSAVE RT_BIT_32(18)
931/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
932#define X86_CR4_SMEP RT_BIT_32(20)
933/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
934#define X86_CR4_SMAP RT_BIT_32(21)
935/** Bit 22 - PKE - Protection Key Enable. */
936#define X86_CR4_PKE RT_BIT_32(22)
937/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
938#define X86_CR4_CET RT_BIT_32(23)
939/** @} */
940
941
942/** @name DR6
943 * @{ */
944/** Bit 0 - B0 - Breakpoint 0 condition detected. */
945#define X86_DR6_B0 RT_BIT_32(0)
946/** Bit 1 - B1 - Breakpoint 1 condition detected. */
947#define X86_DR6_B1 RT_BIT_32(1)
948/** Bit 2 - B2 - Breakpoint 2 condition detected. */
949#define X86_DR6_B2 RT_BIT_32(2)
950/** Bit 3 - B3 - Breakpoint 3 condition detected. */
951#define X86_DR6_B3 RT_BIT_32(3)
952/** Mask of all the Bx bits. */
953#define X86_DR6_B_MASK UINT64_C(0x0000000f)
954/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
955#define X86_DR6_BD RT_BIT_32(13)
956/** Bit 14 - BS - Single step */
957#define X86_DR6_BS RT_BIT_32(14)
958/** Bit 15 - BT - Task switch. (TSS T bit.) */
959#define X86_DR6_BT RT_BIT_32(15)
960/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
961#define X86_DR6_RTM RT_BIT_32(16)
962/** Value of DR6 after powerup/reset. */
963#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
964/** Bits which must be 1s in DR6. */
965#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
966/** Bits which must be 1s in DR6, when RTM is supported. */
967#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
968/** Bits which must be 0s in DR6. */
969#define X86_DR6_RAZ_MASK RT_BIT_64(12)
970/** Bits which must be 0s on writes to DR6. */
971#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
972/** @} */
973
974/** Get the DR6.Bx bit for a the given breakpoint. */
975#define X86_DR6_B(iBp) RT_BIT_64(iBp)
976
977
978/** @name DR7
979 * @{ */
980/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
981#define X86_DR7_L0 RT_BIT_32(0)
982/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
983#define X86_DR7_G0 RT_BIT_32(1)
984/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
985#define X86_DR7_L1 RT_BIT_32(2)
986/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
987#define X86_DR7_G1 RT_BIT_32(3)
988/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
989#define X86_DR7_L2 RT_BIT_32(4)
990/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
991#define X86_DR7_G2 RT_BIT_32(5)
992/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
993#define X86_DR7_L3 RT_BIT_32(6)
994/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
995#define X86_DR7_G3 RT_BIT_32(7)
996/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
997#define X86_DR7_LE RT_BIT_32(8)
998/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
999#define X86_DR7_GE RT_BIT_32(9)
1000
1001/** L0, L1, L2, and L3. */
1002#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1003/** L0, L1, L2, and L3. */
1004#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1005
1006/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1007 * Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1008#define X86_DR7_RTM RT_BIT_32(11)
1009/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1010 * Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1011 * May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1012 * instruction is executed.
1013 * @see http://www.rcollins.org/secrets/DR7.html */
1014#define X86_DR7_ICE_IR RT_BIT_32(12)
1015/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1016 * any DR register is accessed. */
1017#define X86_DR7_GD RT_BIT_32(13)
1018/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1019 * Pentium. */
1020#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1021/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1022#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1023/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
1024#define X86_DR7_RW0_MASK (3 << 16)
1025/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
1026#define X86_DR7_LEN0_MASK (3 << 18)
1027/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
1028#define X86_DR7_RW1_MASK (3 << 20)
1029/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
1030#define X86_DR7_LEN1_MASK (3 << 22)
1031/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
1032#define X86_DR7_RW2_MASK (3 << 24)
1033/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
1034#define X86_DR7_LEN2_MASK (3 << 26)
1035/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
1036#define X86_DR7_RW3_MASK (3 << 28)
1037/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
1038#define X86_DR7_LEN3_MASK (3 << 30)
1039
1040/** Bits which reads as 1s. */
1041#define X86_DR7_RA1_MASK RT_BIT_32(10)
1042/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1043#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1044/** Bits which must be 0s when writing to DR7. */
1045#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1046
1047/** Calcs the L bit of Nth breakpoint.
1048 * @param iBp The breakpoint number [0..3].
1049 */
1050#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1051
1052/** Calcs the G bit of Nth breakpoint.
1053 * @param iBp The breakpoint number [0..3].
1054 */
1055#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1056
1057/** Calcs the L and G bits of Nth breakpoint.
1058 * @param iBp The breakpoint number [0..3].
1059 */
1060#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1061
1062/** @name Read/Write values.
1063 * @{ */
1064/** Break on instruction fetch only. */
1065#define X86_DR7_RW_EO UINT32_C(0)
1066/** Break on write only. */
1067#define X86_DR7_RW_WO UINT32_C(1)
1068/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1069#define X86_DR7_RW_IO UINT32_C(2)
1070/** Break on read or write (but not instruction fetches). */
1071#define X86_DR7_RW_RW UINT32_C(3)
1072/** @} */
1073
1074/** Shifts a X86_DR7_RW_* value to its right place.
1075 * @param iBp The breakpoint number [0..3].
1076 * @param fRw One of the X86_DR7_RW_* value.
1077 */
1078#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1079
1080/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1081 * one of the X86_DR7_RW_XXX constants).
1082 *
1083 * @returns X86_DR7_RW_XXX
1084 * @param uDR7 DR7 value
1085 * @param iBp The breakpoint number [0..3].
1086 */
1087#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1088
1089/** R/W0, R/W1, R/W2, and R/W3. */
1090#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1091
1092#ifndef VBOX_FOR_DTRACE_LIB
1093/** Checks if there are any I/O breakpoint types configured in the RW
1094 * registers. Does NOT check if these are enabled, sorry. */
1095# define X86_DR7_ANY_RW_IO(uDR7) \
1096 ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1097 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1098AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1099AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1100AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1101AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1102AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1103AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1104AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1105AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1106AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1107#endif /* !VBOX_FOR_DTRACE_LIB */
1108
1109/** @name Length values.
1110 * @{ */
1111#define X86_DR7_LEN_BYTE UINT32_C(0)
1112#define X86_DR7_LEN_WORD UINT32_C(1)
1113#define X86_DR7_LEN_QWORD UINT32_C(2) /**< AMD64 long mode only. */
1114#define X86_DR7_LEN_DWORD UINT32_C(3)
1115/** @} */
1116
1117/** Shifts a X86_DR7_LEN_* value to its right place.
1118 * @param iBp The breakpoint number [0..3].
1119 * @param cb One of the X86_DR7_LEN_* values.
1120 */
1121#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1122
1123/** Fetch the breakpoint length bits from the DR7 value.
1124 * @param uDR7 DR7 value
1125 * @param iBp The breakpoint number [0..3].
1126 */
1127#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1128
1129/** Mask used to check if any breakpoints are enabled. */
1130#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1131
1132/** LEN0, LEN1, LEN2, and LEN3. */
1133#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1134/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1135#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1136
1137/** Value of DR7 after powerup/reset. */
1138#define X86_DR7_INIT_VAL 0x400
1139/** @} */
1140
1141
1142/** @name Machine Specific Registers
1143 * @{
1144 */
1145/** Machine check address register (P5). */
1146#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1147/** Machine check type register (P5). */
1148#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1149/** Time Stamp Counter. */
1150#define MSR_IA32_TSC 0x10
1151#define MSR_IA32_CESR UINT32_C(0x00000011)
1152#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1153#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1154
1155#define MSR_IA32_PLATFORM_ID 0x17
1156
1157#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1158# define MSR_IA32_APICBASE 0x1b
1159/** Local APIC enabled. */
1160# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1161/** X2APIC enabled (requires the EN bit to be set). */
1162# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1163/** The processor is the boot strap processor (BSP). */
1164# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1165/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1166 * width. */
1167# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1168/** The default physical base address of the APIC. */
1169# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1170/** Gets the physical base address from the MSR. */
1171# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1172#endif
1173
1174/** Undocumented intel MSR for reporting thread and core counts.
1175 * Judging from the XNU sources, it seems to be introduced in Nehalem. The
1176 * first 16 bits is the thread count. The next 16 bits the core count, except
1177 * on Westmere where it seems it's only the next 4 bits for some reason. */
1178#define MSR_CORE_THREAD_COUNT 0x35
1179
1180/** CPU Feature control. */
1181#define MSR_IA32_FEATURE_CONTROL 0x3A
1182/** Feature control - Lock MSR from writes (R/W0). */
1183#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1184/** Feature control - Enable VMX inside SMX operation (R/WL). */
1185#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1186/** Feature control - Enable VMX outside SMX operation (R/WL). */
1187#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1188/** Feature control - SENTER local functions enable (R/WL). */
1189#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1190#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1191#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1192#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1193#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1194#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1195#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1196/** Feature control - SENTER global enable (R/WL). */
1197#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1198/** Feature control - SGX launch control enable (R/WL). */
1199#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1200/** Feature control - SGX global enable (R/WL). */
1201#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1202/** Feature control - LMCE on (R/WL). */
1203#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1204
1205/** Per-processor TSC adjust MSR. */
1206#define MSR_IA32_TSC_ADJUST 0x3B
1207
1208/** Spectre control register.
1209 * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1210#define MSR_IA32_SPEC_CTRL 0x48
1211/** IBRS - Indirect branch restricted speculation. */
1212#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1213/** STIBP - Single thread indirect branch predictors. */
1214#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1215
1216/** Prediction command register.
1217 * Write only, logical processor scope, no state since write only. */
1218#define MSR_IA32_PRED_CMD 0x49
1219/** IBPB - Indirect branch prediction barrie when written as 1. */
1220#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1221
1222/** BIOS update trigger (microcode update). */
1223#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1224
1225/** BIOS update signature (microcode). */
1226#define MSR_IA32_BIOS_SIGN_ID 0x8B
1227
1228/** SMM monitor control. */
1229#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1230/** SMM control - Valid. */
1231#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1232/** SMM control - VMXOFF unblocks SMI. */
1233#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1234/** SMM control - MSEG base physical address. */
1235#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1236
1237/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1238#define MSR_IA32_SMBASE 0x9E
1239
1240/** General performance counter no. 0. */
1241#define MSR_IA32_PMC0 0xC1
1242/** General performance counter no. 1. */
1243#define MSR_IA32_PMC1 0xC2
1244/** General performance counter no. 2. */
1245#define MSR_IA32_PMC2 0xC3
1246/** General performance counter no. 3. */
1247#define MSR_IA32_PMC3 0xC4
1248/** General performance counter no. 4. */
1249#define MSR_IA32_PMC4 0xC5
1250/** General performance counter no. 5. */
1251#define MSR_IA32_PMC5 0xC6
1252/** General performance counter no. 6. */
1253#define MSR_IA32_PMC6 0xC7
1254/** General performance counter no. 7. */
1255#define MSR_IA32_PMC7 0xC8
1256
1257/** Nehalem power control. */
1258#define MSR_IA32_PLATFORM_INFO 0xCE
1259
1260/** Get FSB clock status (Intel-specific). */
1261#define MSR_IA32_FSB_CLOCK_STS 0xCD
1262
1263/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1264#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1265
1266/** C0 Maximum Frequency Clock Count */
1267#define MSR_IA32_MPERF 0xE7
1268/** C0 Actual Frequency Clock Count */
1269#define MSR_IA32_APERF 0xE8
1270
1271/** MTRR Capabilities. */
1272#define MSR_IA32_MTRR_CAP 0xFE
1273
1274/** Architecture capabilities (bugfixes). */
1275#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1276/** CPU is no subject to meltdown problems. */
1277#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1278/** CPU has better IBRS and you can leave it on all the time. */
1279#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1280/** CPU has return stack buffer (RSB) override. */
1281#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1282/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1283 * This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1284#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1285/** CPU does not suffer from MDS issues. */
1286#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1287
1288/** Flush command register. */
1289#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1290/** Flush the level 1 data cache when this bit is written. */
1291#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1292
1293/** Cache control/info. */
1294#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1295
1296#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1297/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1298 * R0 SS == CS + 8
1299 * R3 CS == CS + 16
1300 * R3 SS == CS + 24
1301 */
1302#define MSR_IA32_SYSENTER_CS 0x174
1303/** SYSENTER_ESP - the R0 ESP. */
1304#define MSR_IA32_SYSENTER_ESP 0x175
1305/** SYSENTER_EIP - the R0 EIP. */
1306#define MSR_IA32_SYSENTER_EIP 0x176
1307#endif
1308
1309/** Machine Check Global Capabilities Register. */
1310#define MSR_IA32_MCG_CAP 0x179
1311/** Machine Check Global Status Register. */
1312#define MSR_IA32_MCG_STATUS 0x17A
1313/** Machine Check Global Control Register. */
1314#define MSR_IA32_MCG_CTRL 0x17B
1315
1316/** Page Attribute Table. */
1317#define MSR_IA32_CR_PAT 0x277
1318/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1319 * "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1320#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1321
1322/** Performance event select MSRs. (Intel only) */
1323#define MSR_IA32_PERFEVTSEL0 0x186
1324#define MSR_IA32_PERFEVTSEL1 0x187
1325#define MSR_IA32_PERFEVTSEL2 0x188
1326#define MSR_IA32_PERFEVTSEL3 0x189
1327
1328/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1329 * The 16th bit whether flex ratio is being used, in which case bits 15:8
1330 * holds a ratio that Apple takes for TSC granularity.
1331 *
1332 * @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1333#define MSR_FLEX_RATIO 0x194
1334/** Performance state value and starting with Intel core more.
1335 * Apple uses the >=core features to determine TSC granularity on older CPUs. */
1336#define MSR_IA32_PERF_STATUS 0x198
1337#define MSR_IA32_PERF_CTL 0x199
1338#define MSR_IA32_THERM_STATUS 0x19c
1339
1340/** Offcore response event select registers. */
1341#define MSR_OFFCORE_RSP_0 0x1a6
1342#define MSR_OFFCORE_RSP_1 0x1a7
1343
1344/** Enable misc. processor features (R/W). */
1345#define MSR_IA32_MISC_ENABLE 0x1A0
1346/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1347#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1348/** Automatic Thermal Control Circuit Enable (R/W). */
1349#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1350/** Performance Monitoring Available (R). */
1351#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1352/** Branch Trace Storage Unavailable (R/O). */
1353#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1354/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1355#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1356/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1357#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1358/** If MONITOR/MWAIT is supported (R/W). */
1359#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1360/** Limit CPUID Maxval to 3 leafs (R/W). */
1361#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1362/** When set to 1, xTPR messages are disabled (R/W). */
1363#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1364/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1365#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1366
1367/** Trace/Profile Resource Control (R/W) */
1368#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1369/** Last branch record. */
1370#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1371/** Branch trace flag (single step on branches). */
1372#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1373/** Performance monitoring pin control (AMD only). */
1374#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1375#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1376#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1377#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1378/** Trace message enable (Intel only). */
1379#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1380/** Branch trace store (Intel only). */
1381#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1382/** Branch trace interrupt (Intel only). */
1383#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1384/** Branch trace off in privileged code (Intel only). */
1385#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1386/** Branch trace off in user code (Intel only). */
1387#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1388/** Freeze LBR on PMI flag (Intel only). */
1389#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1390/** Freeze PERFMON on PMI flag (Intel only). */
1391#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1392/** Freeze while SMM enabled (Intel only). */
1393#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1394/** Advanced debugging of RTM regions (Intel only). */
1395#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1396/** Debug control MSR valid bits (Intel only). */
1397#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \
1398 | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1399 | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1400 | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1401 | MSR_IA32_DEBUGCTL_RTM)
1402
1403/** The number (0..3 or 0..15) of the last branch record register on P4 and
1404 * related Xeons. */
1405#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1406/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1407 * @{ */
1408#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1409#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1410#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1411#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1412/** @} */
1413
1414
1415#define IA32_MTRR_PHYSBASE0 0x200
1416#define IA32_MTRR_PHYSMASK0 0x201
1417#define IA32_MTRR_PHYSBASE1 0x202
1418#define IA32_MTRR_PHYSMASK1 0x203
1419#define IA32_MTRR_PHYSBASE2 0x204
1420#define IA32_MTRR_PHYSMASK2 0x205
1421#define IA32_MTRR_PHYSBASE3 0x206
1422#define IA32_MTRR_PHYSMASK3 0x207
1423#define IA32_MTRR_PHYSBASE4 0x208
1424#define IA32_MTRR_PHYSMASK4 0x209
1425#define IA32_MTRR_PHYSBASE5 0x20a
1426#define IA32_MTRR_PHYSMASK5 0x20b
1427#define IA32_MTRR_PHYSBASE6 0x20c
1428#define IA32_MTRR_PHYSMASK6 0x20d
1429#define IA32_MTRR_PHYSBASE7 0x20e
1430#define IA32_MTRR_PHYSMASK7 0x20f
1431#define IA32_MTRR_PHYSBASE8 0x210
1432#define IA32_MTRR_PHYSMASK8 0x211
1433#define IA32_MTRR_PHYSBASE9 0x212
1434#define IA32_MTRR_PHYSMASK9 0x213
1435
1436/** Fixed range MTRRs.
1437 * @{ */
1438#define IA32_MTRR_FIX64K_00000 0x250
1439#define IA32_MTRR_FIX16K_80000 0x258
1440#define IA32_MTRR_FIX16K_A0000 0x259
1441#define IA32_MTRR_FIX4K_C0000 0x268
1442#define IA32_MTRR_FIX4K_C8000 0x269
1443#define IA32_MTRR_FIX4K_D0000 0x26a
1444#define IA32_MTRR_FIX4K_D8000 0x26b
1445#define IA32_MTRR_FIX4K_E0000 0x26c
1446#define IA32_MTRR_FIX4K_E8000 0x26d
1447#define IA32_MTRR_FIX4K_F0000 0x26e
1448#define IA32_MTRR_FIX4K_F8000 0x26f
1449/** @} */
1450
1451/** MTRR Default Range. */
1452#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1453
1454/** Global performance counter control facilities (Intel only). */
1455#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1456#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1457#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1458
1459/** Precise Event Based sampling (Intel only). */
1460#define MSR_IA32_PEBS_ENABLE 0x3F1
1461
1462#define MSR_IA32_MC0_CTL 0x400
1463#define MSR_IA32_MC0_STATUS 0x401
1464
1465/** Basic VMX information. */
1466#define MSR_IA32_VMX_BASIC 0x480
1467/** Allowed settings for pin-based VM execution controls. */
1468#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1469/** Allowed settings for proc-based VM execution controls. */
1470#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1471/** Allowed settings for the VM-exit controls. */
1472#define MSR_IA32_VMX_EXIT_CTLS 0x483
1473/** Allowed settings for the VM-entry controls. */
1474#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1475/** Misc VMX info. */
1476#define MSR_IA32_VMX_MISC 0x485
1477/** Fixed cleared bits in CR0. */
1478#define MSR_IA32_VMX_CR0_FIXED0 0x486
1479/** Fixed set bits in CR0. */
1480#define MSR_IA32_VMX_CR0_FIXED1 0x487
1481/** Fixed cleared bits in CR4. */
1482#define MSR_IA32_VMX_CR4_FIXED0 0x488
1483/** Fixed set bits in CR4. */
1484#define MSR_IA32_VMX_CR4_FIXED1 0x489
1485/** Information for enumerating fields in the VMCS. */
1486#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1487/** Allowed settings for secondary proc-based VM execution controls */
1488#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1489/** EPT capabilities. */
1490#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1491/** Allowed settings of all pin-based VM execution controls. */
1492#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1493/** Allowed settings of all proc-based VM execution controls. */
1494#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1495/** Allowed settings of all VMX exit controls. */
1496#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1497/** Allowed settings of all VMX entry controls. */
1498#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1499/** Allowed settings for the VM-function controls. */
1500#define MSR_IA32_VMX_VMFUNC 0x491
1501
1502/** Intel PT - Enable and control for trace packet generation. */
1503#define MSR_IA32_RTIT_CTL 0x570
1504
1505/** DS Save Area (R/W). */
1506#define MSR_IA32_DS_AREA 0x600
1507/** Running Average Power Limit (RAPL) power units. */
1508#define MSR_RAPL_POWER_UNIT 0x606
1509/** Package C3 Interrupt Response Limit. */
1510#define MSR_PKGC3_IRTL 0x60a
1511/** Package C6/C7S Interrupt Response Limit 1. */
1512#define MSR_PKGC_IRTL1 0x60b
1513/** Package C6/C7S Interrupt Response Limit 2. */
1514#define MSR_PKGC_IRTL2 0x60c
1515/** Package C2 Residency Counter. */
1516#define MSR_PKG_C2_RESIDENCY 0x60d
1517/** PKG RAPL Power Limit Control. */
1518#define MSR_PKG_POWER_LIMIT 0x610
1519/** PKG Energy Status. */
1520#define MSR_PKG_ENERGY_STATUS 0x611
1521/** PKG Perf Status. */
1522#define MSR_PKG_PERF_STATUS 0x613
1523/** PKG RAPL Parameters. */
1524#define MSR_PKG_POWER_INFO 0x614
1525/** DRAM RAPL Power Limit Control. */
1526#define MSR_DRAM_POWER_LIMIT 0x618
1527/** DRAM Energy Status. */
1528#define MSR_DRAM_ENERGY_STATUS 0x619
1529/** DRAM Performance Throttling Status. */
1530#define MSR_DRAM_PERF_STATUS 0x61b
1531/** DRAM RAPL Parameters. */
1532#define MSR_DRAM_POWER_INFO 0x61c
1533/** Package C10 Residency Counter. */
1534#define MSR_PKG_C10_RESIDENCY 0x632
1535/** PP0 Energy Status. */
1536#define MSR_PP0_ENERGY_STATUS 0x639
1537/** PP1 Energy Status. */
1538#define MSR_PP1_ENERGY_STATUS 0x641
1539/** Turbo Activation Ratio. */
1540#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1541/** Core Performance Limit Reasons. */
1542#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1543
1544/** Last branch record from IP MSRs.
1545 * @{ */
1546#define MSR_LASTBRANCH_0_FROM_IP 0x680
1547#define MSR_LASTBRANCH_1_FROM_IP 0x681
1548#define MSR_LASTBRANCH_2_FROM_IP 0x682
1549#define MSR_LASTBRANCH_3_FROM_IP 0x683
1550#define MSR_LASTBRANCH_4_FROM_IP 0x684
1551#define MSR_LASTBRANCH_5_FROM_IP 0x685
1552#define MSR_LASTBRANCH_6_FROM_IP 0x686
1553#define MSR_LASTBRANCH_7_FROM_IP 0x687
1554#define MSR_LASTBRANCH_8_FROM_IP 0x688
1555#define MSR_LASTBRANCH_9_FROM_IP 0x689
1556#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1557#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1558#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1559#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1560#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1561#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1562#define MSR_LASTBRANCH_16_FROM_IP 0x690
1563#define MSR_LASTBRANCH_17_FROM_IP 0x691
1564#define MSR_LASTBRANCH_18_FROM_IP 0x692
1565#define MSR_LASTBRANCH_19_FROM_IP 0x693
1566#define MSR_LASTBRANCH_20_FROM_IP 0x694
1567#define MSR_LASTBRANCH_21_FROM_IP 0x695
1568#define MSR_LASTBRANCH_22_FROM_IP 0x696
1569#define MSR_LASTBRANCH_23_FROM_IP 0x697
1570#define MSR_LASTBRANCH_24_FROM_IP 0x698
1571#define MSR_LASTBRANCH_25_FROM_IP 0x699
1572#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1573#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1574#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1575#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1576#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1577#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1578/** @} */
1579
1580/** Last branch record to IP MSRs.
1581 * @{ */
1582#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1583#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1584#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1585#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1586#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1587#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1588#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1589#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1590#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1591#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1592#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1593#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1594#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1595#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1596#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1597#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1598#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1599#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1600#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1601#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1602#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1603#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1604#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1605#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1606#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1607#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1608#define MSR_LASTBRANCH_26_TO_IP 0x6da
1609#define MSR_LASTBRANCH_27_TO_IP 0x6db
1610#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1611#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1612#define MSR_LASTBRANCH_30_TO_IP 0x6de
1613#define MSR_LASTBRANCH_31_TO_IP 0x6df
1614/** @} */
1615
1616/** X2APIC MSR range start. */
1617#define MSR_IA32_X2APIC_START 0x800
1618/** X2APIC MSR - APIC ID Register. */
1619#define MSR_IA32_X2APIC_ID 0x802
1620/** X2APIC MSR - APIC Version Register. */
1621#define MSR_IA32_X2APIC_VERSION 0x803
1622/** X2APIC MSR - Task Priority Register. */
1623#define MSR_IA32_X2APIC_TPR 0x808
1624/** X2APIC MSR - Processor Priority register. */
1625#define MSR_IA32_X2APIC_PPR 0x80A
1626/** X2APIC MSR - End Of Interrupt register. */
1627#define MSR_IA32_X2APIC_EOI 0x80B
1628/** X2APIC MSR - Logical Destination Register. */
1629#define MSR_IA32_X2APIC_LDR 0x80D
1630/** X2APIC MSR - Spurious Interrupt Vector Register. */
1631#define MSR_IA32_X2APIC_SVR 0x80F
1632/** X2APIC MSR - In-service Register (bits 31:0). */
1633#define MSR_IA32_X2APIC_ISR0 0x810
1634/** X2APIC MSR - In-service Register (bits 63:32). */
1635#define MSR_IA32_X2APIC_ISR1 0x811
1636/** X2APIC MSR - In-service Register (bits 95:64). */
1637#define MSR_IA32_X2APIC_ISR2 0x812
1638/** X2APIC MSR - In-service Register (bits 127:96). */
1639#define MSR_IA32_X2APIC_ISR3 0x813
1640/** X2APIC MSR - In-service Register (bits 159:128). */
1641#define MSR_IA32_X2APIC_ISR4 0x814
1642/** X2APIC MSR - In-service Register (bits 191:160). */
1643#define MSR_IA32_X2APIC_ISR5 0x815
1644/** X2APIC MSR - In-service Register (bits 223:192). */
1645#define MSR_IA32_X2APIC_ISR6 0x816
1646/** X2APIC MSR - In-service Register (bits 255:224). */
1647#define MSR_IA32_X2APIC_ISR7 0x817
1648/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1649#define MSR_IA32_X2APIC_TMR0 0x818
1650/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1651#define MSR_IA32_X2APIC_TMR1 0x819
1652/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1653#define MSR_IA32_X2APIC_TMR2 0x81A
1654/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1655#define MSR_IA32_X2APIC_TMR3 0x81B
1656/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1657#define MSR_IA32_X2APIC_TMR4 0x81C
1658/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1659#define MSR_IA32_X2APIC_TMR5 0x81D
1660/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1661#define MSR_IA32_X2APIC_TMR6 0x81E
1662/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1663#define MSR_IA32_X2APIC_TMR7 0x81F
1664/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1665#define MSR_IA32_X2APIC_IRR0 0x820
1666/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1667#define MSR_IA32_X2APIC_IRR1 0x821
1668/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1669#define MSR_IA32_X2APIC_IRR2 0x822
1670/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1671#define MSR_IA32_X2APIC_IRR3 0x823
1672/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1673#define MSR_IA32_X2APIC_IRR4 0x824
1674/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1675#define MSR_IA32_X2APIC_IRR5 0x825
1676/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1677#define MSR_IA32_X2APIC_IRR6 0x826
1678/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1679#define MSR_IA32_X2APIC_IRR7 0x827
1680/** X2APIC MSR - Error Status Register. */
1681#define MSR_IA32_X2APIC_ESR 0x828
1682/** X2APIC MSR - LVT CMCI Register. */
1683#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1684/** X2APIC MSR - Interrupt Command Register. */
1685#define MSR_IA32_X2APIC_ICR 0x830
1686/** X2APIC MSR - LVT Timer Register. */
1687#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1688/** X2APIC MSR - LVT Thermal Sensor Register. */
1689#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1690/** X2APIC MSR - LVT Performance Counter Register. */
1691#define MSR_IA32_X2APIC_LVT_PERF 0x834
1692/** X2APIC MSR - LVT LINT0 Register. */
1693#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1694/** X2APIC MSR - LVT LINT1 Register. */
1695#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1696/** X2APIC MSR - LVT Error Register . */
1697#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1698/** X2APIC MSR - Timer Initial Count Register. */
1699#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1700/** X2APIC MSR - Timer Current Count Register. */
1701#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1702/** X2APIC MSR - Timer Divide Configuration Register. */
1703#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1704/** X2APIC MSR - Self IPI. */
1705#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1706/** X2APIC MSR range end. */
1707#define MSR_IA32_X2APIC_END 0xBFF
1708/** X2APIC MSR - LVT start range. */
1709#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1710/** X2APIC MSR - LVT end range (inclusive). */
1711#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1712
1713/** K6 EFER - Extended Feature Enable Register. */
1714#define MSR_K6_EFER UINT32_C(0xc0000080)
1715/** @todo document EFER */
1716/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1717#define MSR_K6_EFER_SCE RT_BIT_32(0)
1718/** Bit 8 - LME - Long mode enabled. (R/W) */
1719#define MSR_K6_EFER_LME RT_BIT_32(8)
1720#define MSR_K6_EFER_BIT_LME 8 /**< Bit number of MSR_K6_EFER_LME */
1721/** Bit 10 - LMA - Long mode active. (R) */
1722#define MSR_K6_EFER_LMA RT_BIT_32(10)
1723#define MSR_K6_EFER_BIT_LMA 10 /**< Bit number of MSR_K6_EFER_LMA */
1724/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1725#define MSR_K6_EFER_NXE RT_BIT_32(11)
1726#define MSR_K6_EFER_BIT_NXE 11 /**< Bit number of MSR_K6_EFER_NXE */
1727/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1728#define MSR_K6_EFER_SVME RT_BIT_32(12)
1729/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1730#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1731/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1732#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1733/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1734#define MSR_K6_EFER_TCE RT_BIT_32(15)
1735/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
1736#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
1737
1738/** K6 STAR - SYSCALL/RET targets. */
1739#define MSR_K6_STAR UINT32_C(0xc0000081)
1740/** Shift value for getting the SYSRET CS and SS value. */
1741#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1742/** Shift value for getting the SYSCALL CS and SS value. */
1743#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1744/** Selector mask for use after shifting. */
1745#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1746/** The mask which give the SYSCALL EIP. */
1747#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1748/** K6 WHCR - Write Handling Control Register. */
1749#define MSR_K6_WHCR UINT32_C(0xc0000082)
1750/** K6 UWCCR - UC/WC Cacheability Control Register. */
1751#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1752/** K6 PSOR - Processor State Observability Register. */
1753#define MSR_K6_PSOR UINT32_C(0xc0000087)
1754/** K6 PFIR - Page Flush/Invalidate Register. */
1755#define MSR_K6_PFIR UINT32_C(0xc0000088)
1756
1757/** Performance counter MSRs. (AMD only) */
1758#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1759#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1760#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1761#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1762#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1763#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1764#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1765#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1766
1767/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1768#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1769/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1770#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1771/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1772#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1773/** K8 FS.base - The 64-bit base FS register. */
1774#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1775/** K8 GS.base - The 64-bit base GS register. */
1776#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1777/** K8 KernelGSbase - Used with SWAPGS. */
1778#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1779/** K8 TSC_AUX - Used with RDTSCP. */
1780#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1781#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1782#define MSR_K8_HWCR UINT32_C(0xc0010015)
1783#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1784#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1785#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1786#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1787#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1788#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1789/** North bridge config? See BIOS & Kernel dev guides for
1790 * details. */
1791#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1792
1793/** Hypertransport interrupt pending register.
1794 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1795#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1796
1797/** SVM Control. */
1798#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1799/** Disables HDT (Hardware Debug Tool) and certain internal debug
1800 * features. */
1801#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1802/** If set, non-intercepted INIT signals are converted to \#SX
1803 * exceptions. */
1804#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1805/** Disables A20 masking. */
1806#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1807/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1808#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1809/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1810 * clear, EFER.SVME can be written normally. */
1811#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1812
1813#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1814#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1815/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1816 * host state during world switch. */
1817#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1818
1819/** @} */
1820
1821
1822/** @name Page Table / Directory / Directory Pointers / L4.
1823 * @{
1824 */
1825
1826/** Page table/directory entry as an unsigned integer. */
1827typedef uint32_t X86PGUINT;
1828/** Pointer to a page table/directory table entry as an unsigned integer. */
1829typedef X86PGUINT *PX86PGUINT;
1830/** Pointer to an const page table/directory table entry as an unsigned integer. */
1831typedef X86PGUINT const *PCX86PGUINT;
1832
1833/** Number of entries in a 32-bit PT/PD. */
1834#define X86_PG_ENTRIES 1024
1835
1836
1837/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1838typedef uint64_t X86PGPAEUINT;
1839/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1840typedef X86PGPAEUINT *PX86PGPAEUINT;
1841/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1842typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1843
1844/** Number of entries in a PAE PT/PD. */
1845#define X86_PG_PAE_ENTRIES 512
1846/** Number of entries in a PAE PDPT. */
1847#define X86_PG_PAE_PDPE_ENTRIES 4
1848
1849/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1850#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1851/** Number of entries in an AMD64 PDPT.
1852 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1853#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1854
1855/** The size of a default page. */
1856#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1857/** The page shift of a default page. */
1858#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1859/** The default page offset mask. */
1860#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1861/** The default page base mask for virtual addresses. */
1862#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1863/** The default page base mask for virtual addresses - 32bit version. */
1864#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1865
1866/** The size of a 4KB page. */
1867#define X86_PAGE_4K_SIZE _4K
1868/** The page shift of a 4KB page. */
1869#define X86_PAGE_4K_SHIFT 12
1870/** The 4KB page offset mask. */
1871#define X86_PAGE_4K_OFFSET_MASK 0xfff
1872/** The 4KB page base mask for virtual addresses. */
1873#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1874/** The 4KB page base mask for virtual addresses - 32bit version. */
1875#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1876
1877/** The size of a 2MB page. */
1878#define X86_PAGE_2M_SIZE _2M
1879/** The page shift of a 2MB page. */
1880#define X86_PAGE_2M_SHIFT 21
1881/** The 2MB page offset mask. */
1882#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1883/** The 2MB page base mask for virtual addresses. */
1884#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1885/** The 2MB page base mask for virtual addresses - 32bit version. */
1886#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1887
1888/** The size of a 4MB page. */
1889#define X86_PAGE_4M_SIZE _4M
1890/** The page shift of a 4MB page. */
1891#define X86_PAGE_4M_SHIFT 22
1892/** The 4MB page offset mask. */
1893#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1894/** The 4MB page base mask for virtual addresses. */
1895#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1896/** The 4MB page base mask for virtual addresses - 32bit version. */
1897#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1898
1899/** The size of a 1GB page. */
1900#define X86_PAGE_1G_SIZE _1G
1901/** The page shift of a 1GB page. */
1902#define X86_PAGE_1G_SHIFT 30
1903/** The 1GB page offset mask. */
1904#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
1905/** The 1GB page base mask for virtual addresses. */
1906#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
1907
1908/**
1909 * Check if the given address is canonical.
1910 */
1911#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1912
1913
1914/** @name Page Table Entry
1915 * @{
1916 */
1917/** Bit 0 - P - Present bit. */
1918#define X86_PTE_BIT_P 0
1919/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1920#define X86_PTE_BIT_RW 1
1921/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1922#define X86_PTE_BIT_US 2
1923/** Bit 3 - PWT - Page level write thru bit. */
1924#define X86_PTE_BIT_PWT 3
1925/** Bit 4 - PCD - Page level cache disable bit. */
1926#define X86_PTE_BIT_PCD 4
1927/** Bit 5 - A - Access bit. */
1928#define X86_PTE_BIT_A 5
1929/** Bit 6 - D - Dirty bit. */
1930#define X86_PTE_BIT_D 6
1931/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1932#define X86_PTE_BIT_PAT 7
1933/** Bit 8 - G - Global flag. */
1934#define X86_PTE_BIT_G 8
1935/** Bits 63 - NX - PAE/LM - No execution flag. */
1936#define X86_PTE_PAE_BIT_NX 63
1937
1938/** Bit 0 - P - Present bit mask. */
1939#define X86_PTE_P RT_BIT_32(0)
1940/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1941#define X86_PTE_RW RT_BIT_32(1)
1942/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1943#define X86_PTE_US RT_BIT_32(2)
1944/** Bit 3 - PWT - Page level write thru bit mask. */
1945#define X86_PTE_PWT RT_BIT_32(3)
1946/** Bit 4 - PCD - Page level cache disable bit mask. */
1947#define X86_PTE_PCD RT_BIT_32(4)
1948/** Bit 5 - A - Access bit mask. */
1949#define X86_PTE_A RT_BIT_32(5)
1950/** Bit 6 - D - Dirty bit mask. */
1951#define X86_PTE_D RT_BIT_32(6)
1952/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1953#define X86_PTE_PAT RT_BIT_32(7)
1954/** Bit 8 - G - Global bit mask. */
1955#define X86_PTE_G RT_BIT_32(8)
1956
1957/** Bits 9-11 - - Available for use to system software. */
1958#define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1959/** Bits 12-31 - - Physical Page number of the next level. */
1960#define X86_PTE_PG_MASK ( 0xfffff000 )
1961
1962/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1963#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1964/** Bits 63 - NX - PAE/LM - No execution flag. */
1965#define X86_PTE_PAE_NX RT_BIT_64(63)
1966/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1967#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1968/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1969#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1970/** No bits - - LM - MBZ bits when NX is active. */
1971#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1972/** Bits 63 - - LM - MBZ bits when no NX. */
1973#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1974
1975/**
1976 * Page table entry.
1977 */
1978typedef struct X86PTEBITS
1979{
1980 /** Flags whether(=1) or not the page is present. */
1981 uint32_t u1Present : 1;
1982 /** Read(=0) / Write(=1) flag. */
1983 uint32_t u1Write : 1;
1984 /** User(=1) / Supervisor (=0) flag. */
1985 uint32_t u1User : 1;
1986 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1987 uint32_t u1WriteThru : 1;
1988 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1989 uint32_t u1CacheDisable : 1;
1990 /** Accessed flag.
1991 * Indicates that the page have been read or written to. */
1992 uint32_t u1Accessed : 1;
1993 /** Dirty flag.
1994 * Indicates that the page has been written to. */
1995 uint32_t u1Dirty : 1;
1996 /** Reserved / If PAT enabled, bit 2 of the index. */
1997 uint32_t u1PAT : 1;
1998 /** Global flag. (Ignored in all but final level.) */
1999 uint32_t u1Global : 1;
2000 /** Available for use to system software. */
2001 uint32_t u3Available : 3;
2002 /** Physical Page number of the next level. */
2003 uint32_t u20PageNo : 20;
2004} X86PTEBITS;
2005#ifndef VBOX_FOR_DTRACE_LIB
2006AssertCompileSize(X86PTEBITS, 4);
2007#endif
2008/** Pointer to a page table entry. */
2009typedef X86PTEBITS *PX86PTEBITS;
2010/** Pointer to a const page table entry. */
2011typedef const X86PTEBITS *PCX86PTEBITS;
2012
2013/**
2014 * Page table entry.
2015 */
2016typedef union X86PTE
2017{
2018 /** Unsigned integer view */
2019 X86PGUINT u;
2020 /** Bit field view. */
2021 X86PTEBITS n;
2022 /** 32-bit view. */
2023 uint32_t au32[1];
2024 /** 16-bit view. */
2025 uint16_t au16[2];
2026 /** 8-bit view. */
2027 uint8_t au8[4];
2028} X86PTE;
2029#ifndef VBOX_FOR_DTRACE_LIB
2030AssertCompileSize(X86PTE, 4);
2031#endif
2032/** Pointer to a page table entry. */
2033typedef X86PTE *PX86PTE;
2034/** Pointer to a const page table entry. */
2035typedef const X86PTE *PCX86PTE;
2036
2037
2038/**
2039 * PAE page table entry.
2040 */
2041typedef struct X86PTEPAEBITS
2042{
2043 /** Flags whether(=1) or not the page is present. */
2044 uint32_t u1Present : 1;
2045 /** Read(=0) / Write(=1) flag. */
2046 uint32_t u1Write : 1;
2047 /** User(=1) / Supervisor(=0) flag. */
2048 uint32_t u1User : 1;
2049 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2050 uint32_t u1WriteThru : 1;
2051 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2052 uint32_t u1CacheDisable : 1;
2053 /** Accessed flag.
2054 * Indicates that the page have been read or written to. */
2055 uint32_t u1Accessed : 1;
2056 /** Dirty flag.
2057 * Indicates that the page has been written to. */
2058 uint32_t u1Dirty : 1;
2059 /** Reserved / If PAT enabled, bit 2 of the index. */
2060 uint32_t u1PAT : 1;
2061 /** Global flag. (Ignored in all but final level.) */
2062 uint32_t u1Global : 1;
2063 /** Available for use to system software. */
2064 uint32_t u3Available : 3;
2065 /** Physical Page number of the next level - Low Part. Don't use this. */
2066 uint32_t u20PageNoLow : 20;
2067 /** Physical Page number of the next level - High Part. Don't use this. */
2068 uint32_t u20PageNoHigh : 20;
2069 /** MBZ bits */
2070 uint32_t u11Reserved : 11;
2071 /** No Execute flag. */
2072 uint32_t u1NoExecute : 1;
2073} X86PTEPAEBITS;
2074#ifndef VBOX_FOR_DTRACE_LIB
2075AssertCompileSize(X86PTEPAEBITS, 8);
2076#endif
2077/** Pointer to a page table entry. */
2078typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2079/** Pointer to a page table entry. */
2080typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2081
2082/**
2083 * PAE Page table entry.
2084 */
2085typedef union X86PTEPAE
2086{
2087 /** Unsigned integer view */
2088 X86PGPAEUINT u;
2089 /** Bit field view. */
2090 X86PTEPAEBITS n;
2091 /** 32-bit view. */
2092 uint32_t au32[2];
2093 /** 16-bit view. */
2094 uint16_t au16[4];
2095 /** 8-bit view. */
2096 uint8_t au8[8];
2097} X86PTEPAE;
2098#ifndef VBOX_FOR_DTRACE_LIB
2099AssertCompileSize(X86PTEPAE, 8);
2100#endif
2101/** Pointer to a PAE page table entry. */
2102typedef X86PTEPAE *PX86PTEPAE;
2103/** Pointer to a const PAE page table entry. */
2104typedef const X86PTEPAE *PCX86PTEPAE;
2105/** @} */
2106
2107/**
2108 * Page table.
2109 */
2110typedef struct X86PT
2111{
2112 /** PTE Array. */
2113 X86PTE a[X86_PG_ENTRIES];
2114} X86PT;
2115#ifndef VBOX_FOR_DTRACE_LIB
2116AssertCompileSize(X86PT, 4096);
2117#endif
2118/** Pointer to a page table. */
2119typedef X86PT *PX86PT;
2120/** Pointer to a const page table. */
2121typedef const X86PT *PCX86PT;
2122
2123/** The page shift to get the PT index. */
2124#define X86_PT_SHIFT 12
2125/** The PT index mask (apply to a shifted page address). */
2126#define X86_PT_MASK 0x3ff
2127
2128
2129/**
2130 * Page directory.
2131 */
2132typedef struct X86PTPAE
2133{
2134 /** PTE Array. */
2135 X86PTEPAE a[X86_PG_PAE_ENTRIES];
2136} X86PTPAE;
2137#ifndef VBOX_FOR_DTRACE_LIB
2138AssertCompileSize(X86PTPAE, 4096);
2139#endif
2140/** Pointer to a page table. */
2141typedef X86PTPAE *PX86PTPAE;
2142/** Pointer to a const page table. */
2143typedef const X86PTPAE *PCX86PTPAE;
2144
2145/** The page shift to get the PA PTE index. */
2146#define X86_PT_PAE_SHIFT 12
2147/** The PAE PT index mask (apply to a shifted page address). */
2148#define X86_PT_PAE_MASK 0x1ff
2149
2150
2151/** @name 4KB Page Directory Entry
2152 * @{
2153 */
2154/** Bit 0 - P - Present bit. */
2155#define X86_PDE_P RT_BIT_32(0)
2156/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2157#define X86_PDE_RW RT_BIT_32(1)
2158/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2159#define X86_PDE_US RT_BIT_32(2)
2160/** Bit 3 - PWT - Page level write thru bit. */
2161#define X86_PDE_PWT RT_BIT_32(3)
2162/** Bit 4 - PCD - Page level cache disable bit. */
2163#define X86_PDE_PCD RT_BIT_32(4)
2164/** Bit 5 - A - Access bit. */
2165#define X86_PDE_A RT_BIT_32(5)
2166/** Bit 7 - PS - Page size attribute.
2167 * Clear mean 4KB pages, set means large pages (2/4MB). */
2168#define X86_PDE_PS RT_BIT_32(7)
2169/** Bits 9-11 - - Available for use to system software. */
2170#define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2171/** Bits 12-31 - - Physical Page number of the next level. */
2172#define X86_PDE_PG_MASK ( 0xfffff000 )
2173
2174/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2175#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2176/** Bits 63 - NX - PAE/LM - No execution flag. */
2177#define X86_PDE_PAE_NX RT_BIT_64(63)
2178/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2179#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2180/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2181#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2182/** Bit 7 - - LM - MBZ bits when NX is active. */
2183#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2184/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2185#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2186
2187/**
2188 * Page directory entry.
2189 */
2190typedef struct X86PDEBITS
2191{
2192 /** Flags whether(=1) or not the page is present. */
2193 uint32_t u1Present : 1;
2194 /** Read(=0) / Write(=1) flag. */
2195 uint32_t u1Write : 1;
2196 /** User(=1) / Supervisor (=0) flag. */
2197 uint32_t u1User : 1;
2198 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2199 uint32_t u1WriteThru : 1;
2200 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2201 uint32_t u1CacheDisable : 1;
2202 /** Accessed flag.
2203 * Indicates that the page has been read or written to. */
2204 uint32_t u1Accessed : 1;
2205 /** Reserved / Ignored (dirty bit). */
2206 uint32_t u1Reserved0 : 1;
2207 /** Size bit if PSE is enabled - in any event it's 0. */
2208 uint32_t u1Size : 1;
2209 /** Reserved / Ignored (global bit). */
2210 uint32_t u1Reserved1 : 1;
2211 /** Available for use to system software. */
2212 uint32_t u3Available : 3;
2213 /** Physical Page number of the next level. */
2214 uint32_t u20PageNo : 20;
2215} X86PDEBITS;
2216#ifndef VBOX_FOR_DTRACE_LIB
2217AssertCompileSize(X86PDEBITS, 4);
2218#endif
2219/** Pointer to a page directory entry. */
2220typedef X86PDEBITS *PX86PDEBITS;
2221/** Pointer to a const page directory entry. */
2222typedef const X86PDEBITS *PCX86PDEBITS;
2223
2224
2225/**
2226 * PAE page directory entry.
2227 */
2228typedef struct X86PDEPAEBITS
2229{
2230 /** Flags whether(=1) or not the page is present. */
2231 uint32_t u1Present : 1;
2232 /** Read(=0) / Write(=1) flag. */
2233 uint32_t u1Write : 1;
2234 /** User(=1) / Supervisor (=0) flag. */
2235 uint32_t u1User : 1;
2236 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2237 uint32_t u1WriteThru : 1;
2238 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2239 uint32_t u1CacheDisable : 1;
2240 /** Accessed flag.
2241 * Indicates that the page has been read or written to. */
2242 uint32_t u1Accessed : 1;
2243 /** Reserved / Ignored (dirty bit). */
2244 uint32_t u1Reserved0 : 1;
2245 /** Size bit if PSE is enabled - in any event it's 0. */
2246 uint32_t u1Size : 1;
2247 /** Reserved / Ignored (global bit). / */
2248 uint32_t u1Reserved1 : 1;
2249 /** Available for use to system software. */
2250 uint32_t u3Available : 3;
2251 /** Physical Page number of the next level - Low Part. Don't use! */
2252 uint32_t u20PageNoLow : 20;
2253 /** Physical Page number of the next level - High Part. Don't use! */
2254 uint32_t u20PageNoHigh : 20;
2255 /** MBZ bits */
2256 uint32_t u11Reserved : 11;
2257 /** No Execute flag. */
2258 uint32_t u1NoExecute : 1;
2259} X86PDEPAEBITS;
2260#ifndef VBOX_FOR_DTRACE_LIB
2261AssertCompileSize(X86PDEPAEBITS, 8);
2262#endif
2263/** Pointer to a page directory entry. */
2264typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2265/** Pointer to a const page directory entry. */
2266typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2267
2268/** @} */
2269
2270
2271/** @name 2/4MB Page Directory Entry
2272 * @{
2273 */
2274/** Bit 0 - P - Present bit. */
2275#define X86_PDE4M_P RT_BIT_32(0)
2276/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2277#define X86_PDE4M_RW RT_BIT_32(1)
2278/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2279#define X86_PDE4M_US RT_BIT_32(2)
2280/** Bit 3 - PWT - Page level write thru bit. */
2281#define X86_PDE4M_PWT RT_BIT_32(3)
2282/** Bit 4 - PCD - Page level cache disable bit. */
2283#define X86_PDE4M_PCD RT_BIT_32(4)
2284/** Bit 5 - A - Access bit. */
2285#define X86_PDE4M_A RT_BIT_32(5)
2286/** Bit 6 - D - Dirty bit. */
2287#define X86_PDE4M_D RT_BIT_32(6)
2288/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2289#define X86_PDE4M_PS RT_BIT_32(7)
2290/** Bit 8 - G - Global flag. */
2291#define X86_PDE4M_G RT_BIT_32(8)
2292/** Bits 9-11 - AVL - Available for use to system software. */
2293#define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2294/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2295#define X86_PDE4M_PAT RT_BIT_32(12)
2296/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2297#define X86_PDE4M_PAT_SHIFT (12 - 7)
2298/** Bits 22-31 - - Physical Page number. */
2299#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2300/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2301#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2302/** The number of bits to the high part of the page number. */
2303#define X86_PDE4M_PG_HIGH_SHIFT 19
2304/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2305#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2306
2307/** Bits 21-51 - - PAE/LM - Physical Page number.
2308 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2309#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2310/** Bits 63 - NX - PAE/LM - No execution flag. */
2311#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2312/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2313#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2314/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2315#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2316/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2317#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2318/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2319#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2320
2321/**
2322 * 4MB page directory entry.
2323 */
2324typedef struct X86PDE4MBITS
2325{
2326 /** Flags whether(=1) or not the page is present. */
2327 uint32_t u1Present : 1;
2328 /** Read(=0) / Write(=1) flag. */
2329 uint32_t u1Write : 1;
2330 /** User(=1) / Supervisor (=0) flag. */
2331 uint32_t u1User : 1;
2332 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2333 uint32_t u1WriteThru : 1;
2334 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2335 uint32_t u1CacheDisable : 1;
2336 /** Accessed flag.
2337 * Indicates that the page have been read or written to. */
2338 uint32_t u1Accessed : 1;
2339 /** Dirty flag.
2340 * Indicates that the page has been written to. */
2341 uint32_t u1Dirty : 1;
2342 /** Page size flag - always 1 for 4MB entries. */
2343 uint32_t u1Size : 1;
2344 /** Global flag. */
2345 uint32_t u1Global : 1;
2346 /** Available for use to system software. */
2347 uint32_t u3Available : 3;
2348 /** Reserved / If PAT enabled, bit 2 of the index. */
2349 uint32_t u1PAT : 1;
2350 /** Bits 32-39 of the page number on AMD64.
2351 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2352 uint32_t u8PageNoHigh : 8;
2353 /** Reserved. */
2354 uint32_t u1Reserved : 1;
2355 /** Physical Page number of the page. */
2356 uint32_t u10PageNo : 10;
2357} X86PDE4MBITS;
2358#ifndef VBOX_FOR_DTRACE_LIB
2359AssertCompileSize(X86PDE4MBITS, 4);
2360#endif
2361/** Pointer to a page table entry. */
2362typedef X86PDE4MBITS *PX86PDE4MBITS;
2363/** Pointer to a const page table entry. */
2364typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2365
2366
2367/**
2368 * 2MB PAE page directory entry.
2369 */
2370typedef struct X86PDE2MPAEBITS
2371{
2372 /** Flags whether(=1) or not the page is present. */
2373 uint32_t u1Present : 1;
2374 /** Read(=0) / Write(=1) flag. */
2375 uint32_t u1Write : 1;
2376 /** User(=1) / Supervisor(=0) flag. */
2377 uint32_t u1User : 1;
2378 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2379 uint32_t u1WriteThru : 1;
2380 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2381 uint32_t u1CacheDisable : 1;
2382 /** Accessed flag.
2383 * Indicates that the page have been read or written to. */
2384 uint32_t u1Accessed : 1;
2385 /** Dirty flag.
2386 * Indicates that the page has been written to. */
2387 uint32_t u1Dirty : 1;
2388 /** Page size flag - always 1 for 2MB entries. */
2389 uint32_t u1Size : 1;
2390 /** Global flag. */
2391 uint32_t u1Global : 1;
2392 /** Available for use to system software. */
2393 uint32_t u3Available : 3;
2394 /** Reserved / If PAT enabled, bit 2 of the index. */
2395 uint32_t u1PAT : 1;
2396 /** Reserved. */
2397 uint32_t u9Reserved : 9;
2398 /** Physical Page number of the next level - Low part. Don't use! */
2399 uint32_t u10PageNoLow : 10;
2400 /** Physical Page number of the next level - High part. Don't use! */
2401 uint32_t u20PageNoHigh : 20;
2402 /** MBZ bits */
2403 uint32_t u11Reserved : 11;
2404 /** No Execute flag. */
2405 uint32_t u1NoExecute : 1;
2406} X86PDE2MPAEBITS;
2407#ifndef VBOX_FOR_DTRACE_LIB
2408AssertCompileSize(X86PDE2MPAEBITS, 8);
2409#endif
2410/** Pointer to a 2MB PAE page table entry. */
2411typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2412/** Pointer to a 2MB PAE page table entry. */
2413typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2414
2415/** @} */
2416
2417/**
2418 * Page directory entry.
2419 */
2420typedef union X86PDE
2421{
2422 /** Unsigned integer view. */
2423 X86PGUINT u;
2424 /** Normal view. */
2425 X86PDEBITS n;
2426 /** 4MB view (big). */
2427 X86PDE4MBITS b;
2428 /** 8 bit unsigned integer view. */
2429 uint8_t au8[4];
2430 /** 16 bit unsigned integer view. */
2431 uint16_t au16[2];
2432 /** 32 bit unsigned integer view. */
2433 uint32_t au32[1];
2434} X86PDE;
2435#ifndef VBOX_FOR_DTRACE_LIB
2436AssertCompileSize(X86PDE, 4);
2437#endif
2438/** Pointer to a page directory entry. */
2439typedef X86PDE *PX86PDE;
2440/** Pointer to a const page directory entry. */
2441typedef const X86PDE *PCX86PDE;
2442
2443/**
2444 * PAE page directory entry.
2445 */
2446typedef union X86PDEPAE
2447{
2448 /** Unsigned integer view. */
2449 X86PGPAEUINT u;
2450 /** Normal view. */
2451 X86PDEPAEBITS n;
2452 /** 2MB page view (big). */
2453 X86PDE2MPAEBITS b;
2454 /** 8 bit unsigned integer view. */
2455 uint8_t au8[8];
2456 /** 16 bit unsigned integer view. */
2457 uint16_t au16[4];
2458 /** 32 bit unsigned integer view. */
2459 uint32_t au32[2];
2460} X86PDEPAE;
2461#ifndef VBOX_FOR_DTRACE_LIB
2462AssertCompileSize(X86PDEPAE, 8);
2463#endif
2464/** Pointer to a page directory entry. */
2465typedef X86PDEPAE *PX86PDEPAE;
2466/** Pointer to a const page directory entry. */
2467typedef const X86PDEPAE *PCX86PDEPAE;
2468
2469/**
2470 * Page directory.
2471 */
2472typedef struct X86PD
2473{
2474 /** PDE Array. */
2475 X86PDE a[X86_PG_ENTRIES];
2476} X86PD;
2477#ifndef VBOX_FOR_DTRACE_LIB
2478AssertCompileSize(X86PD, 4096);
2479#endif
2480/** Pointer to a page directory. */
2481typedef X86PD *PX86PD;
2482/** Pointer to a const page directory. */
2483typedef const X86PD *PCX86PD;
2484
2485/** The page shift to get the PD index. */
2486#define X86_PD_SHIFT 22
2487/** The PD index mask (apply to a shifted page address). */
2488#define X86_PD_MASK 0x3ff
2489
2490
2491/**
2492 * PAE page directory.
2493 */
2494typedef struct X86PDPAE
2495{
2496 /** PDE Array. */
2497 X86PDEPAE a[X86_PG_PAE_ENTRIES];
2498} X86PDPAE;
2499#ifndef VBOX_FOR_DTRACE_LIB
2500AssertCompileSize(X86PDPAE, 4096);
2501#endif
2502/** Pointer to a PAE page directory. */
2503typedef X86PDPAE *PX86PDPAE;
2504/** Pointer to a const PAE page directory. */
2505typedef const X86PDPAE *PCX86PDPAE;
2506
2507/** The page shift to get the PAE PD index. */
2508#define X86_PD_PAE_SHIFT 21
2509/** The PAE PD index mask (apply to a shifted page address). */
2510#define X86_PD_PAE_MASK 0x1ff
2511
2512
2513/** @name Page Directory Pointer Table Entry (PAE)
2514 * @{
2515 */
2516/** Bit 0 - P - Present bit. */
2517#define X86_PDPE_P RT_BIT_32(0)
2518/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2519#define X86_PDPE_RW RT_BIT_32(1)
2520/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2521#define X86_PDPE_US RT_BIT_32(2)
2522/** Bit 3 - PWT - Page level write thru bit. */
2523#define X86_PDPE_PWT RT_BIT_32(3)
2524/** Bit 4 - PCD - Page level cache disable bit. */
2525#define X86_PDPE_PCD RT_BIT_32(4)
2526/** Bit 5 - A - Access bit. Long Mode only. */
2527#define X86_PDPE_A RT_BIT_32(5)
2528/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2529#define X86_PDPE_LM_PS RT_BIT_32(7)
2530/** Bits 9-11 - - Available for use to system software. */
2531#define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2532/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2533#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2534/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2535#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2536/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2537#define X86_PDPE_LM_NX RT_BIT_64(63)
2538/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2539#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2540/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2541#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2542/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2543#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2544/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2545#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2546
2547
2548/**
2549 * Page directory pointer table entry.
2550 */
2551typedef struct X86PDPEBITS
2552{
2553 /** Flags whether(=1) or not the page is present. */
2554 uint32_t u1Present : 1;
2555 /** Chunk of reserved bits. */
2556 uint32_t u2Reserved : 2;
2557 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2558 uint32_t u1WriteThru : 1;
2559 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2560 uint32_t u1CacheDisable : 1;
2561 /** Chunk of reserved bits. */
2562 uint32_t u4Reserved : 4;
2563 /** Available for use to system software. */
2564 uint32_t u3Available : 3;
2565 /** Physical Page number of the next level - Low Part. Don't use! */
2566 uint32_t u20PageNoLow : 20;
2567 /** Physical Page number of the next level - High Part. Don't use! */
2568 uint32_t u20PageNoHigh : 20;
2569 /** MBZ bits */
2570 uint32_t u12Reserved : 12;
2571} X86PDPEBITS;
2572#ifndef VBOX_FOR_DTRACE_LIB
2573AssertCompileSize(X86PDPEBITS, 8);
2574#endif
2575/** Pointer to a page directory pointer table entry. */
2576typedef X86PDPEBITS *PX86PTPEBITS;
2577/** Pointer to a const page directory pointer table entry. */
2578typedef const X86PDPEBITS *PCX86PTPEBITS;
2579
2580/**
2581 * Page directory pointer table entry. AMD64 version
2582 */
2583typedef struct X86PDPEAMD64BITS
2584{
2585 /** Flags whether(=1) or not the page is present. */
2586 uint32_t u1Present : 1;
2587 /** Read(=0) / Write(=1) flag. */
2588 uint32_t u1Write : 1;
2589 /** User(=1) / Supervisor (=0) flag. */
2590 uint32_t u1User : 1;
2591 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2592 uint32_t u1WriteThru : 1;
2593 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2594 uint32_t u1CacheDisable : 1;
2595 /** Accessed flag.
2596 * Indicates that the page have been read or written to. */
2597 uint32_t u1Accessed : 1;
2598 /** Chunk of reserved bits. */
2599 uint32_t u3Reserved : 3;
2600 /** Available for use to system software. */
2601 uint32_t u3Available : 3;
2602 /** Physical Page number of the next level - Low Part. Don't use! */
2603 uint32_t u20PageNoLow : 20;
2604 /** Physical Page number of the next level - High Part. Don't use! */
2605 uint32_t u20PageNoHigh : 20;
2606 /** MBZ bits */
2607 uint32_t u11Reserved : 11;
2608 /** No Execute flag. */
2609 uint32_t u1NoExecute : 1;
2610} X86PDPEAMD64BITS;
2611#ifndef VBOX_FOR_DTRACE_LIB
2612AssertCompileSize(X86PDPEAMD64BITS, 8);
2613#endif
2614/** Pointer to a page directory pointer table entry. */
2615typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2616/** Pointer to a const page directory pointer table entry. */
2617typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2618
2619/**
2620 * Page directory pointer table entry for 1GB page. (AMD64 only)
2621 */
2622typedef struct X86PDPE1GB
2623{
2624 /** 0: Flags whether(=1) or not the page is present. */
2625 uint32_t u1Present : 1;
2626 /** 1: Read(=0) / Write(=1) flag. */
2627 uint32_t u1Write : 1;
2628 /** 2: User(=1) / Supervisor (=0) flag. */
2629 uint32_t u1User : 1;
2630 /** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2631 uint32_t u1WriteThru : 1;
2632 /** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2633 uint32_t u1CacheDisable : 1;
2634 /** 5: Accessed flag.
2635 * Indicates that the page have been read or written to. */
2636 uint32_t u1Accessed : 1;
2637 /** 6: Dirty flag for 1GB pages. */
2638 uint32_t u1Dirty : 1;
2639 /** 7: Indicates 1GB page if set. */
2640 uint32_t u1Size : 1;
2641 /** 8: Global 1GB page. */
2642 uint32_t u1Global: 1;
2643 /** 9-11: Available for use to system software. */
2644 uint32_t u3Available : 3;
2645 /** 12: PAT bit for 1GB page. */
2646 uint32_t u1PAT : 1;
2647 /** 13-29: MBZ bits. */
2648 uint32_t u17Reserved : 17;
2649 /** 30-31: Physical page number - Low Part. Don't use! */
2650 uint32_t u2PageNoLow : 2;
2651 /** 32-51: Physical Page number of the next level - High Part. Don't use! */
2652 uint32_t u20PageNoHigh : 20;
2653 /** 52-62: MBZ bits */
2654 uint32_t u11Reserved : 11;
2655 /** 63: No Execute flag. */
2656 uint32_t u1NoExecute : 1;
2657} X86PDPE1GB;
2658#ifndef VBOX_FOR_DTRACE_LIB
2659AssertCompileSize(X86PDPE1GB, 8);
2660#endif
2661/** Pointer to a page directory pointer table entry for a 1GB page. */
2662typedef X86PDPE1GB *PX86PDPE1GB;
2663/** Pointer to a const page directory pointer table entry for a 1GB page. */
2664typedef const X86PDPE1GB *PCX86PDPE1GB;
2665
2666/**
2667 * Page directory pointer table entry.
2668 */
2669typedef union X86PDPE
2670{
2671 /** Unsigned integer view. */
2672 X86PGPAEUINT u;
2673 /** Normal view. */
2674 X86PDPEBITS n;
2675 /** AMD64 view. */
2676 X86PDPEAMD64BITS lm;
2677 /** AMD64 big view. */
2678 X86PDPE1GB b;
2679 /** 8 bit unsigned integer view. */
2680 uint8_t au8[8];
2681 /** 16 bit unsigned integer view. */
2682 uint16_t au16[4];
2683 /** 32 bit unsigned integer view. */
2684 uint32_t au32[2];
2685} X86PDPE;
2686#ifndef VBOX_FOR_DTRACE_LIB
2687AssertCompileSize(X86PDPE, 8);
2688#endif
2689/** Pointer to a page directory pointer table entry. */
2690typedef X86PDPE *PX86PDPE;
2691/** Pointer to a const page directory pointer table entry. */
2692typedef const X86PDPE *PCX86PDPE;
2693
2694
2695/**
2696 * Page directory pointer table.
2697 */
2698typedef struct X86PDPT
2699{
2700 /** PDE Array. */
2701 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2702} X86PDPT;
2703#ifndef VBOX_FOR_DTRACE_LIB
2704AssertCompileSize(X86PDPT, 4096);
2705#endif
2706/** Pointer to a page directory pointer table. */
2707typedef X86PDPT *PX86PDPT;
2708/** Pointer to a const page directory pointer table. */
2709typedef const X86PDPT *PCX86PDPT;
2710
2711/** The page shift to get the PDPT index. */
2712#define X86_PDPT_SHIFT 30
2713/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2714#define X86_PDPT_MASK_PAE 0x3
2715/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2716#define X86_PDPT_MASK_AMD64 0x1ff
2717
2718/** @} */
2719
2720
2721/** @name Page Map Level-4 Entry (Long Mode PAE)
2722 * @{
2723 */
2724/** Bit 0 - P - Present bit. */
2725#define X86_PML4E_P RT_BIT_32(0)
2726/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2727#define X86_PML4E_RW RT_BIT_32(1)
2728/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2729#define X86_PML4E_US RT_BIT_32(2)
2730/** Bit 3 - PWT - Page level write thru bit. */
2731#define X86_PML4E_PWT RT_BIT_32(3)
2732/** Bit 4 - PCD - Page level cache disable bit. */
2733#define X86_PML4E_PCD RT_BIT_32(4)
2734/** Bit 5 - A - Access bit. */
2735#define X86_PML4E_A RT_BIT_32(5)
2736/** Bits 9-11 - - Available for use to system software. */
2737#define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2738/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2739#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2740/** Bits 8, 7 - - MBZ bits when NX is active. */
2741#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2742/** Bits 63, 7 - - MBZ bits when no NX. */
2743#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2744/** Bits 63 - NX - PAE - No execution flag. */
2745#define X86_PML4E_NX RT_BIT_64(63)
2746
2747/**
2748 * Page Map Level-4 Entry
2749 */
2750typedef struct X86PML4EBITS
2751{
2752 /** Flags whether(=1) or not the page is present. */
2753 uint32_t u1Present : 1;
2754 /** Read(=0) / Write(=1) flag. */
2755 uint32_t u1Write : 1;
2756 /** User(=1) / Supervisor (=0) flag. */
2757 uint32_t u1User : 1;
2758 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2759 uint32_t u1WriteThru : 1;
2760 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2761 uint32_t u1CacheDisable : 1;
2762 /** Accessed flag.
2763 * Indicates that the page have been read or written to. */
2764 uint32_t u1Accessed : 1;
2765 /** Chunk of reserved bits. */
2766 uint32_t u3Reserved : 3;
2767 /** Available for use to system software. */
2768 uint32_t u3Available : 3;
2769 /** Physical Page number of the next level - Low Part. Don't use! */
2770 uint32_t u20PageNoLow : 20;
2771 /** Physical Page number of the next level - High Part. Don't use! */
2772 uint32_t u20PageNoHigh : 20;
2773 /** MBZ bits */
2774 uint32_t u11Reserved : 11;
2775 /** No Execute flag. */
2776 uint32_t u1NoExecute : 1;
2777} X86PML4EBITS;
2778#ifndef VBOX_FOR_DTRACE_LIB
2779AssertCompileSize(X86PML4EBITS, 8);
2780#endif
2781/** Pointer to a page map level-4 entry. */
2782typedef X86PML4EBITS *PX86PML4EBITS;
2783/** Pointer to a const page map level-4 entry. */
2784typedef const X86PML4EBITS *PCX86PML4EBITS;
2785
2786/**
2787 * Page Map Level-4 Entry.
2788 */
2789typedef union X86PML4E
2790{
2791 /** Unsigned integer view. */
2792 X86PGPAEUINT u;
2793 /** Normal view. */
2794 X86PML4EBITS n;
2795 /** 8 bit unsigned integer view. */
2796 uint8_t au8[8];
2797 /** 16 bit unsigned integer view. */
2798 uint16_t au16[4];
2799 /** 32 bit unsigned integer view. */
2800 uint32_t au32[2];
2801} X86PML4E;
2802#ifndef VBOX_FOR_DTRACE_LIB
2803AssertCompileSize(X86PML4E, 8);
2804#endif
2805/** Pointer to a page map level-4 entry. */
2806typedef X86PML4E *PX86PML4E;
2807/** Pointer to a const page map level-4 entry. */
2808typedef const X86PML4E *PCX86PML4E;
2809
2810
2811/**
2812 * Page Map Level-4.
2813 */
2814typedef struct X86PML4
2815{
2816 /** PDE Array. */
2817 X86PML4E a[X86_PG_PAE_ENTRIES];
2818} X86PML4;
2819#ifndef VBOX_FOR_DTRACE_LIB
2820AssertCompileSize(X86PML4, 4096);
2821#endif
2822/** Pointer to a page map level-4. */
2823typedef X86PML4 *PX86PML4;
2824/** Pointer to a const page map level-4. */
2825typedef const X86PML4 *PCX86PML4;
2826
2827/** The page shift to get the PML4 index. */
2828#define X86_PML4_SHIFT 39
2829/** The PML4 index mask (apply to a shifted page address). */
2830#define X86_PML4_MASK 0x1ff
2831
2832/** @} */
2833
2834/** @} */
2835
2836/**
2837 * Intel PCID invalidation types.
2838 */
2839/** Individual address invalidation. */
2840#define X86_INVPCID_TYPE_INDV_ADDR 0
2841/** Single-context invalidation. */
2842#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2843/** All-context including globals invalidation. */
2844#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2845/** All-context excluding globals invalidation. */
2846#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2847/** The maximum valid invalidation type value. */
2848#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2849
2850/**
2851 * 32-bit protected mode FSTENV image.
2852 */
2853typedef struct X86FSTENV32P
2854{
2855 uint16_t FCW;
2856 uint16_t padding1;
2857 uint16_t FSW;
2858 uint16_t padding2;
2859 uint16_t FTW;
2860 uint16_t padding3;
2861 uint32_t FPUIP;
2862 uint16_t FPUCS;
2863 uint16_t FOP;
2864 uint32_t FPUDP;
2865 uint16_t FPUDS;
2866 uint16_t padding4;
2867} X86FSTENV32P;
2868/** Pointer to a 32-bit protected mode FSTENV image. */
2869typedef X86FSTENV32P *PX86FSTENV32P;
2870/** Pointer to a const 32-bit protected mode FSTENV image. */
2871typedef X86FSTENV32P const *PCX86FSTENV32P;
2872
2873
2874/**
2875 * 80-bit MMX/FPU register type.
2876 */
2877typedef struct X86FPUMMX
2878{
2879 uint8_t reg[10];
2880} X86FPUMMX;
2881#ifndef VBOX_FOR_DTRACE_LIB
2882AssertCompileSize(X86FPUMMX, 10);
2883#endif
2884/** Pointer to a 80-bit MMX/FPU register type. */
2885typedef X86FPUMMX *PX86FPUMMX;
2886/** Pointer to a const 80-bit MMX/FPU register type. */
2887typedef const X86FPUMMX *PCX86FPUMMX;
2888
2889/** FPU (x87) register. */
2890typedef union X86FPUREG
2891{
2892 /** MMX view. */
2893 uint64_t mmx;
2894 /** FPU view - todo. */
2895 X86FPUMMX fpu;
2896 /** Extended precision floating point view. */
2897 RTFLOAT80U r80;
2898 /** Extended precision floating point view v2 */
2899 RTFLOAT80U2 r80Ex;
2900 /** 8-bit view. */
2901 uint8_t au8[16];
2902 /** 16-bit view. */
2903 uint16_t au16[8];
2904 /** 32-bit view. */
2905 uint32_t au32[4];
2906 /** 64-bit view. */
2907 uint64_t au64[2];
2908 /** 128-bit view. (yeah, very helpful) */
2909 uint128_t au128[1];
2910} X86FPUREG;
2911#ifndef VBOX_FOR_DTRACE_LIB
2912AssertCompileSize(X86FPUREG, 16);
2913#endif
2914/** Pointer to a FPU register. */
2915typedef X86FPUREG *PX86FPUREG;
2916/** Pointer to a const FPU register. */
2917typedef X86FPUREG const *PCX86FPUREG;
2918
2919/**
2920 * XMM register union.
2921 */
2922typedef union X86XMMREG
2923{
2924 /** XMM Register view. */
2925 uint128_t xmm;
2926 /** 8-bit view. */
2927 uint8_t au8[16];
2928 /** 16-bit view. */
2929 uint16_t au16[8];
2930 /** 32-bit view. */
2931 uint32_t au32[4];
2932 /** 64-bit view. */
2933 uint64_t au64[2];
2934 /** 128-bit view. (yeah, very helpful) */
2935 uint128_t au128[1];
2936#ifndef VBOX_FOR_DTRACE_LIB
2937 /** Confusing nested 128-bit union view (this is what xmm should've been). */
2938 RTUINT128U uXmm;
2939#endif
2940} X86XMMREG;
2941#ifndef VBOX_FOR_DTRACE_LIB
2942AssertCompileSize(X86XMMREG, 16);
2943#endif
2944/** Pointer to an XMM register state. */
2945typedef X86XMMREG *PX86XMMREG;
2946/** Pointer to a const XMM register state. */
2947typedef X86XMMREG const *PCX86XMMREG;
2948
2949/**
2950 * YMM register union.
2951 */
2952typedef union X86YMMREG
2953{
2954 /** 8-bit view. */
2955 uint8_t au8[32];
2956 /** 16-bit view. */
2957 uint16_t au16[16];
2958 /** 32-bit view. */
2959 uint32_t au32[8];
2960 /** 64-bit view. */
2961 uint64_t au64[4];
2962 /** 128-bit view. (yeah, very helpful) */
2963 uint128_t au128[2];
2964 /** XMM sub register view. */
2965 X86XMMREG aXmm[2];
2966} X86YMMREG;
2967#ifndef VBOX_FOR_DTRACE_LIB
2968AssertCompileSize(X86YMMREG, 32);
2969#endif
2970/** Pointer to an YMM register state. */
2971typedef X86YMMREG *PX86YMMREG;
2972/** Pointer to a const YMM register state. */
2973typedef X86YMMREG const *PCX86YMMREG;
2974
2975/**
2976 * ZMM register union.
2977 */
2978typedef union X86ZMMREG
2979{
2980 /** 8-bit view. */
2981 uint8_t au8[64];
2982 /** 16-bit view. */
2983 uint16_t au16[32];
2984 /** 32-bit view. */
2985 uint32_t au32[16];
2986 /** 64-bit view. */
2987 uint64_t au64[8];
2988 /** 128-bit view. (yeah, very helpful) */
2989 uint128_t au128[4];
2990 /** XMM sub register view. */
2991 X86XMMREG aXmm[4];
2992 /** YMM sub register view. */
2993 X86YMMREG aYmm[2];
2994} X86ZMMREG;
2995#ifndef VBOX_FOR_DTRACE_LIB
2996AssertCompileSize(X86ZMMREG, 64);
2997#endif
2998/** Pointer to an ZMM register state. */
2999typedef X86ZMMREG *PX86ZMMREG;
3000/** Pointer to a const ZMM register state. */
3001typedef X86ZMMREG const *PCX86ZMMREG;
3002
3003
3004/**
3005 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3006 * @todo verify this...
3007 */
3008#pragma pack(1)
3009typedef struct X86FPUSTATE
3010{
3011 /** 0x00 - Control word. */
3012 uint16_t FCW;
3013 /** 0x02 - Alignment word */
3014 uint16_t Dummy1;
3015 /** 0x04 - Status word. */
3016 uint16_t FSW;
3017 /** 0x06 - Alignment word */
3018 uint16_t Dummy2;
3019 /** 0x08 - Tag word */
3020 uint16_t FTW;
3021 /** 0x0a - Alignment word */
3022 uint16_t Dummy3;
3023
3024 /** 0x0c - Instruction pointer. */
3025 uint32_t FPUIP;
3026 /** 0x10 - Code selector. */
3027 uint16_t CS;
3028 /** 0x12 - Opcode. */
3029 uint16_t FOP;
3030 /** 0x14 - FOO. */
3031 uint32_t FPUOO;
3032 /** 0x18 - FOS. */
3033 uint32_t FPUOS;
3034 /** 0x1c - FPU register. */
3035 X86FPUREG regs[8];
3036} X86FPUSTATE;
3037#pragma pack()
3038/** Pointer to a FPU state. */
3039typedef X86FPUSTATE *PX86FPUSTATE;
3040/** Pointer to a const FPU state. */
3041typedef const X86FPUSTATE *PCX86FPUSTATE;
3042
3043/**
3044 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3045 */
3046#pragma pack(1)
3047typedef struct X86FXSTATE
3048{
3049 /** 0x00 - Control word. */
3050 uint16_t FCW;
3051 /** 0x02 - Status word. */
3052 uint16_t FSW;
3053 /** 0x04 - Tag word. (The upper byte is always zero.) */
3054 uint16_t FTW;
3055 /** 0x06 - Opcode. */
3056 uint16_t FOP;
3057 /** 0x08 - Instruction pointer. */
3058 uint32_t FPUIP;
3059 /** 0x0c - Code selector. */
3060 uint16_t CS;
3061 uint16_t Rsrvd1;
3062 /** 0x10 - Data pointer. */
3063 uint32_t FPUDP;
3064 /** 0x14 - Data segment */
3065 uint16_t DS;
3066 /** 0x16 */
3067 uint16_t Rsrvd2;
3068 /** 0x18 */
3069 uint32_t MXCSR;
3070 /** 0x1c */
3071 uint32_t MXCSR_MASK;
3072 /** 0x20 - FPU registers. */
3073 X86FPUREG aRegs[8];
3074 /** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3075 X86XMMREG aXMM[16];
3076 /* - offset 416 - */
3077 uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3078 /* - offset 464 - Software usable reserved bits. */
3079 uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3080} X86FXSTATE;
3081#pragma pack()
3082/** Pointer to a FPU Extended state. */
3083typedef X86FXSTATE *PX86FXSTATE;
3084/** Pointer to a const FPU Extended state. */
3085typedef const X86FXSTATE *PCX86FXSTATE;
3086
3087/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3088 * magic. Don't forget to update x86.mac if you change this! */
3089#define X86_OFF_FXSTATE_RSVD 0x1d0
3090/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3091 * forget to update x86.mac if you change this!
3092 * @todo r=bird: This has nothing what-so-ever to do here.... */
3093#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3094#ifndef VBOX_FOR_DTRACE_LIB
3095AssertCompileSize(X86FXSTATE, 512);
3096AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3097#endif
3098
3099/** @name FPU status word flags.
3100 * @{ */
3101/** Exception Flag: Invalid operation. */
3102#define X86_FSW_IE RT_BIT_32(0)
3103/** Exception Flag: Denormalized operand. */
3104#define X86_FSW_DE RT_BIT_32(1)
3105/** Exception Flag: Zero divide. */
3106#define X86_FSW_ZE RT_BIT_32(2)
3107/** Exception Flag: Overflow. */
3108#define X86_FSW_OE RT_BIT_32(3)
3109/** Exception Flag: Underflow. */
3110#define X86_FSW_UE RT_BIT_32(4)
3111/** Exception Flag: Precision. */
3112#define X86_FSW_PE RT_BIT_32(5)
3113/** Stack fault. */
3114#define X86_FSW_SF RT_BIT_32(6)
3115/** Error summary status. */
3116#define X86_FSW_ES RT_BIT_32(7)
3117/** Mask of exceptions flags, excluding the summary bit. */
3118#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3119/** Mask of exceptions flags, including the summary bit. */
3120#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3121/** Condition code 0. */
3122#define X86_FSW_C0 RT_BIT_32(8)
3123/** Condition code 1. */
3124#define X86_FSW_C1 RT_BIT_32(9)
3125/** Condition code 2. */
3126#define X86_FSW_C2 RT_BIT_32(10)
3127/** Top of the stack mask. */
3128#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3129/** TOP shift value. */
3130#define X86_FSW_TOP_SHIFT 11
3131/** Mask for getting TOP value after shifting it right. */
3132#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3133/** Get the TOP value. */
3134#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3135/** Condition code 3. */
3136#define X86_FSW_C3 RT_BIT_32(14)
3137/** Mask of exceptions flags, including the summary bit. */
3138#define X86_FSW_C_MASK UINT16_C(0x4700)
3139/** FPU busy. */
3140#define X86_FSW_B RT_BIT_32(15)
3141/** @} */
3142
3143
3144/** @name FPU control word flags.
3145 * @{ */
3146/** Exception Mask: Invalid operation. */
3147#define X86_FCW_IM RT_BIT_32(0)
3148/** Exception Mask: Denormalized operand. */
3149#define X86_FCW_DM RT_BIT_32(1)
3150/** Exception Mask: Zero divide. */
3151#define X86_FCW_ZM RT_BIT_32(2)
3152/** Exception Mask: Overflow. */
3153#define X86_FCW_OM RT_BIT_32(3)
3154/** Exception Mask: Underflow. */
3155#define X86_FCW_UM RT_BIT_32(4)
3156/** Exception Mask: Precision. */
3157#define X86_FCW_PM RT_BIT_32(5)
3158/** Mask all exceptions, the value typically loaded (by for instance fninit).
3159 * @remarks This includes reserved bit 6. */
3160#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3161/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3162#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3163/** Precision control mask. */
3164#define X86_FCW_PC_MASK UINT16_C(0x0300)
3165/** Precision control: 24-bit. */
3166#define X86_FCW_PC_24 UINT16_C(0x0000)
3167/** Precision control: Reserved. */
3168#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3169/** Precision control: 53-bit. */
3170#define X86_FCW_PC_53 UINT16_C(0x0200)
3171/** Precision control: 64-bit. */
3172#define X86_FCW_PC_64 UINT16_C(0x0300)
3173/** Rounding control mask. */
3174#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3175/** Rounding control: To nearest. */
3176#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3177/** Rounding control: Down. */
3178#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3179/** Rounding control: Up. */
3180#define X86_FCW_RC_UP UINT16_C(0x0800)
3181/** Rounding control: Towards zero. */
3182#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3183/** Bits which should be zero, apparently. */
3184#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3185/** @} */
3186
3187/** @name SSE MXCSR
3188 * @{ */
3189/** Exception Flag: Invalid operation. */
3190#define X86_MXCSR_IE RT_BIT_32(0)
3191/** Exception Flag: Denormalized operand. */
3192#define X86_MXCSR_DE RT_BIT_32(1)
3193/** Exception Flag: Zero divide. */
3194#define X86_MXCSR_ZE RT_BIT_32(2)
3195/** Exception Flag: Overflow. */
3196#define X86_MXCSR_OE RT_BIT_32(3)
3197/** Exception Flag: Underflow. */
3198#define X86_MXCSR_UE RT_BIT_32(4)
3199/** Exception Flag: Precision. */
3200#define X86_MXCSR_PE RT_BIT_32(5)
3201
3202/** Denormals are zero. */
3203#define X86_MXCSR_DAZ RT_BIT_32(6)
3204
3205/** Exception Mask: Invalid operation. */
3206#define X86_MXCSR_IM RT_BIT_32(7)
3207/** Exception Mask: Denormalized operand. */
3208#define X86_MXCSR_DM RT_BIT_32(8)
3209/** Exception Mask: Zero divide. */
3210#define X86_MXCSR_ZM RT_BIT_32(9)
3211/** Exception Mask: Overflow. */
3212#define X86_MXCSR_OM RT_BIT_32(10)
3213/** Exception Mask: Underflow. */
3214#define X86_MXCSR_UM RT_BIT_32(11)
3215/** Exception Mask: Precision. */
3216#define X86_MXCSR_PM RT_BIT_32(12)
3217
3218/** Rounding control mask. */
3219#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
3220/** Rounding control: To nearest. */
3221#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3222/** Rounding control: Down. */
3223#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3224/** Rounding control: Up. */
3225#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3226/** Rounding control: Towards zero. */
3227#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3228
3229/** Flush-to-zero for masked underflow. */
3230#define X86_MXCSR_FZ RT_BIT_32(15)
3231
3232/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3233#define X86_MXCSR_MM RT_BIT_32(17)
3234/** @} */
3235
3236/**
3237 * XSAVE header.
3238 */
3239typedef struct X86XSAVEHDR
3240{
3241 /** XTATE_BV - Bitmap indicating whether a component is in the state. */
3242 uint64_t bmXState;
3243 /** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3244 uint64_t bmXComp;
3245 /** Reserved for furture extensions, probably MBZ. */
3246 uint64_t au64Reserved[6];
3247} X86XSAVEHDR;
3248#ifndef VBOX_FOR_DTRACE_LIB
3249AssertCompileSize(X86XSAVEHDR, 64);
3250#endif
3251/** Pointer to an XSAVE header. */
3252typedef X86XSAVEHDR *PX86XSAVEHDR;
3253/** Pointer to a const XSAVE header. */
3254typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3255
3256
3257/**
3258 * The high 128-bit YMM register state (XSAVE_C_YMM).
3259 * (The lower 128-bits being in X86FXSTATE.)
3260 */
3261typedef struct X86XSAVEYMMHI
3262{
3263 /** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3264 X86XMMREG aYmmHi[16];
3265} X86XSAVEYMMHI;
3266#ifndef VBOX_FOR_DTRACE_LIB
3267AssertCompileSize(X86XSAVEYMMHI, 256);
3268#endif
3269/** Pointer to a high 128-bit YMM register state. */
3270typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3271/** Pointer to a const high 128-bit YMM register state. */
3272typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3273
3274/**
3275 * Intel MPX bound registers state (XSAVE_C_BNDREGS).
3276 */
3277typedef struct X86XSAVEBNDREGS
3278{
3279 /** Array of registers (BND0...BND3). */
3280 struct
3281 {
3282 /** Lower bound. */
3283 uint64_t uLowerBound;
3284 /** Upper bound. */
3285 uint64_t uUpperBound;
3286 } aRegs[4];
3287} X86XSAVEBNDREGS;
3288#ifndef VBOX_FOR_DTRACE_LIB
3289AssertCompileSize(X86XSAVEBNDREGS, 64);
3290#endif
3291/** Pointer to a MPX bound register state. */
3292typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3293/** Pointer to a const MPX bound register state. */
3294typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3295
3296/**
3297 * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3298 */
3299typedef struct X86XSAVEBNDCFG
3300{
3301 uint64_t fConfig;
3302 uint64_t fStatus;
3303} X86XSAVEBNDCFG;
3304#ifndef VBOX_FOR_DTRACE_LIB
3305AssertCompileSize(X86XSAVEBNDCFG, 16);
3306#endif
3307/** Pointer to a MPX bound config and status register state. */
3308typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3309/** Pointer to a const MPX bound config and status register state. */
3310typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3311
3312/**
3313 * AVX-512 opmask state (XSAVE_C_OPMASK).
3314 */
3315typedef struct X86XSAVEOPMASK
3316{
3317 /** The K0..K7 values. */
3318 uint64_t aKRegs[8];
3319} X86XSAVEOPMASK;
3320#ifndef VBOX_FOR_DTRACE_LIB
3321AssertCompileSize(X86XSAVEOPMASK, 64);
3322#endif
3323/** Pointer to a AVX-512 opmask state. */
3324typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3325/** Pointer to a const AVX-512 opmask state. */
3326typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3327
3328/**
3329 * ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3330 */
3331typedef struct X86XSAVEZMMHI256
3332{
3333 /** Upper 256-bits of ZMM0-15. */
3334 X86YMMREG aHi256Regs[16];
3335} X86XSAVEZMMHI256;
3336#ifndef VBOX_FOR_DTRACE_LIB
3337AssertCompileSize(X86XSAVEZMMHI256, 512);
3338#endif
3339/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3340typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3341/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3342typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3343
3344/**
3345 * ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3346 */
3347typedef struct X86XSAVEZMM16HI
3348{
3349 /** ZMM16 thru ZMM31. */
3350 X86ZMMREG aRegs[16];
3351} X86XSAVEZMM16HI;
3352#ifndef VBOX_FOR_DTRACE_LIB
3353AssertCompileSize(X86XSAVEZMM16HI, 1024);
3354#endif
3355/** Pointer to a state comprising ZMM16-32. */
3356typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3357/** Pointer to a const state comprising ZMM16-32. */
3358typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3359
3360/**
3361 * AMD Light weight profiling state (XSAVE_C_LWP).
3362 *
3363 * We probably won't play with this as AMD seems to be dropping from their "zen"
3364 * processor micro architecture.
3365 */
3366typedef struct X86XSAVELWP
3367{
3368 /** Details when needed. */
3369 uint64_t auLater[128/8];
3370} X86XSAVELWP;
3371#ifndef VBOX_FOR_DTRACE_LIB
3372AssertCompileSize(X86XSAVELWP, 128);
3373#endif
3374
3375
3376/**
3377 * x86 FPU/SSE/AVX/XXXX state.
3378 *
3379 * Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3380 * changes to this structure.
3381 */
3382typedef struct X86XSAVEAREA
3383{
3384 /** The x87 and SSE region (or legacy region if you like). */
3385 X86FXSTATE x87;
3386 /** The XSAVE header. */
3387 X86XSAVEHDR Hdr;
3388 /** Beyond the header, there isn't really a fixed layout, but we can
3389 generally assume the YMM (AVX) register extensions are present and
3390 follows immediately. */
3391 union
3392 {
3393 /** The high 128-bit AVX registers for easy access by IEM.
3394 * @note This ASSUMES they will always be here... */
3395 X86XSAVEYMMHI YmmHi;
3396
3397 /** This is a typical layout on intel CPUs (good for debuggers). */
3398 struct
3399 {
3400 X86XSAVEYMMHI YmmHi;
3401 X86XSAVEBNDREGS BndRegs;
3402 X86XSAVEBNDCFG BndCfg;
3403 uint8_t abFudgeToMatchDocs[0xB0];
3404 X86XSAVEOPMASK Opmask;
3405 X86XSAVEZMMHI256 ZmmHi256;
3406 X86XSAVEZMM16HI Zmm16Hi;
3407 } Intel;
3408
3409 /** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3410 struct
3411 {
3412 X86XSAVEYMMHI YmmHi;
3413 X86XSAVELWP Lwp;
3414 } AmdBd;
3415
3416 /** To enbling static deployments that have a reasonable chance of working for
3417 * the next 3-6 CPU generations without running short on space, we allocate a
3418 * lot of extra space here, making the structure a round 8KB in size. This
3419 * leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3420 * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3421 uint8_t ab[8192 - 512 - 64];
3422 } u;
3423} X86XSAVEAREA;
3424#ifndef VBOX_FOR_DTRACE_LIB
3425AssertCompileSize(X86XSAVEAREA, 8192);
3426AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
3427AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3428AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3429AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3430AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3431AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3432AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3433AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3434#endif
3435/** Pointer to a XSAVE area. */
3436typedef X86XSAVEAREA *PX86XSAVEAREA;
3437/** Pointer to a const XSAVE area. */
3438typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3439
3440
3441/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3442 * @{ */
3443/** Bit 0 - x87 - Legacy FPU state (bit number) */
3444#define XSAVE_C_X87_BIT 0
3445/** Bit 0 - x87 - Legacy FPU state. */
3446#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3447/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3448#define XSAVE_C_SSE_BIT 1
3449/** Bit 1 - SSE - 128-bit SSE state. */
3450#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3451/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3452#define XSAVE_C_YMM_BIT 2
3453/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3454#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3455/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3456#define XSAVE_C_BNDREGS_BIT 3
3457/** Bit 3 - BNDREGS - MPX bound register state. */
3458#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3459/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3460#define XSAVE_C_BNDCSR_BIT 4
3461/** Bit 4 - BNDCSR - MPX bound config and status state. */
3462#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3463/** Bit 5 - Opmask - opmask state (bit number). */
3464#define XSAVE_C_OPMASK_BIT 5
3465/** Bit 5 - Opmask - opmask state. */
3466#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3467/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3468#define XSAVE_C_ZMM_HI256_BIT 6
3469/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3470#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3471/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3472#define XSAVE_C_ZMM_16HI_BIT 7
3473/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3474#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3475/** Bit 9 - PKRU - Protection-key state (bit number). */
3476#define XSAVE_C_PKRU_BIT 9
3477/** Bit 9 - PKRU - Protection-key state. */
3478#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3479/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3480#define XSAVE_C_LWP_BIT 62
3481/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3482#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3483/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3484#define XSAVE_C_X_BIT 63
3485/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3486#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3487/** @} */
3488
3489
3490
3491/** @name Selector Descriptor
3492 * @{
3493 */
3494
3495#ifndef VBOX_FOR_DTRACE_LIB
3496/**
3497 * Descriptor attributes (as seen by VT-x).
3498 */
3499typedef struct X86DESCATTRBITS
3500{
3501 /** 00 - Segment Type. */
3502 unsigned u4Type : 4;
3503 /** 04 - Descriptor Type. System(=0) or code/data selector */
3504 unsigned u1DescType : 1;
3505 /** 05 - Descriptor Privilege level. */
3506 unsigned u2Dpl : 2;
3507 /** 07 - Flags selector present(=1) or not. */
3508 unsigned u1Present : 1;
3509 /** 08 - Segment limit 16-19. */
3510 unsigned u4LimitHigh : 4;
3511 /** 0c - Available for system software. */
3512 unsigned u1Available : 1;
3513 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3514 unsigned u1Long : 1;
3515 /** 0e - This flags meaning depends on the segment type. Try make sense out
3516 * of the intel manual yourself. */
3517 unsigned u1DefBig : 1;
3518 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
3519 * clear byte. */
3520 unsigned u1Granularity : 1;
3521 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3522 unsigned u1Unusable : 1;
3523} X86DESCATTRBITS;
3524#endif /* !VBOX_FOR_DTRACE_LIB */
3525
3526/** @name X86DESCATTR masks
3527 * @{ */
3528#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3529#define X86DESCATTR_DT UINT32_C(0x00000010)
3530#define X86DESCATTR_DPL UINT32_C(0x00000060)
3531#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
3532#define X86DESCATTR_P UINT32_C(0x00000080)
3533#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3534#define X86DESCATTR_AVL UINT32_C(0x00001000)
3535#define X86DESCATTR_L UINT32_C(0x00002000)
3536#define X86DESCATTR_D UINT32_C(0x00004000)
3537#define X86DESCATTR_G UINT32_C(0x00008000)
3538#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3539/** @} */
3540
3541#pragma pack(1)
3542typedef union X86DESCATTR
3543{
3544 /** Unsigned integer view. */
3545 uint32_t u;
3546#ifndef VBOX_FOR_DTRACE_LIB
3547 /** Normal view. */
3548 X86DESCATTRBITS n;
3549#endif
3550} X86DESCATTR;
3551#pragma pack()
3552/** Pointer to descriptor attributes. */
3553typedef X86DESCATTR *PX86DESCATTR;
3554/** Pointer to const descriptor attributes. */
3555typedef const X86DESCATTR *PCX86DESCATTR;
3556
3557#ifndef VBOX_FOR_DTRACE_LIB
3558
3559/**
3560 * Generic descriptor table entry
3561 */
3562#pragma pack(1)
3563typedef struct X86DESCGENERIC
3564{
3565 /** 00 - Limit - Low word. */
3566 unsigned u16LimitLow : 16;
3567 /** 10 - Base address - low word.
3568 * Don't try set this to 24 because MSC is doing stupid things then. */
3569 unsigned u16BaseLow : 16;
3570 /** 20 - Base address - first 8 bits of high word. */
3571 unsigned u8BaseHigh1 : 8;
3572 /** 28 - Segment Type. */
3573 unsigned u4Type : 4;
3574 /** 2c - Descriptor Type. System(=0) or code/data selector */
3575 unsigned u1DescType : 1;
3576 /** 2d - Descriptor Privilege level. */
3577 unsigned u2Dpl : 2;
3578 /** 2f - Flags selector present(=1) or not. */
3579 unsigned u1Present : 1;
3580 /** 30 - Segment limit 16-19. */
3581 unsigned u4LimitHigh : 4;
3582 /** 34 - Available for system software. */
3583 unsigned u1Available : 1;
3584 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3585 unsigned u1Long : 1;
3586 /** 36 - This flags meaning depends on the segment type. Try make sense out
3587 * of the intel manual yourself. */
3588 unsigned u1DefBig : 1;
3589 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
3590 * clear byte. */
3591 unsigned u1Granularity : 1;
3592 /** 38 - Base address - highest 8 bits. */
3593 unsigned u8BaseHigh2 : 8;
3594} X86DESCGENERIC;
3595#pragma pack()
3596/** Pointer to a generic descriptor entry. */
3597typedef X86DESCGENERIC *PX86DESCGENERIC;
3598/** Pointer to a const generic descriptor entry. */
3599typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3600
3601/** @name Bit offsets of X86DESCGENERIC members.
3602 * @{*/
3603#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
3604#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
3605#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
3606#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
3607#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
3608#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
3609#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
3610#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
3611#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
3612#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
3613#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
3614#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
3615#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
3616/** @} */
3617
3618
3619/** @name LAR mask
3620 * @{ */
3621#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3622#define X86LAR_F_DT UINT16_C( 0x1000)
3623#define X86LAR_F_DPL UINT16_C( 0x6000)
3624#define X86LAR_F_DPL_SHIFT 13 /**< Shift count for the DPL value. */
3625#define X86LAR_F_P UINT16_C( 0x8000)
3626#define X86LAR_F_AVL UINT32_C(0x00100000)
3627#define X86LAR_F_L UINT32_C(0x00200000)
3628#define X86LAR_F_D UINT32_C(0x00400000)
3629#define X86LAR_F_G UINT32_C(0x00800000)
3630/** @} */
3631
3632
3633/**
3634 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3635 */
3636typedef struct X86DESCGATE
3637{
3638 /** 00 - Target code segment offset - Low word.
3639 * Ignored if task-gate. */
3640 unsigned u16OffsetLow : 16;
3641 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3642 * TSS selector if task-gate. */
3643 unsigned u16Sel : 16;
3644 /** 20 - Number of parameters for a call-gate.
3645 * Ignored if interrupt-, trap- or task-gate. */
3646 unsigned u5ParmCount : 5;
3647 /** 25 - Reserved / ignored. */
3648 unsigned u3Reserved : 3;
3649 /** 28 - Segment Type. */
3650 unsigned u4Type : 4;
3651 /** 2c - Descriptor Type (0 = system). */
3652 unsigned u1DescType : 1;
3653 /** 2d - Descriptor Privilege level. */
3654 unsigned u2Dpl : 2;
3655 /** 2f - Flags selector present(=1) or not. */
3656 unsigned u1Present : 1;
3657 /** 30 - Target code segment offset - High word.
3658 * Ignored if task-gate. */
3659 unsigned u16OffsetHigh : 16;
3660} X86DESCGATE;
3661/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3662typedef X86DESCGATE *PX86DESCGATE;
3663/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3664typedef const X86DESCGATE *PCX86DESCGATE;
3665
3666#endif /* VBOX_FOR_DTRACE_LIB */
3667
3668/**
3669 * Descriptor table entry.
3670 */
3671#pragma pack(1)
3672typedef union X86DESC
3673{
3674#ifndef VBOX_FOR_DTRACE_LIB
3675 /** Generic descriptor view. */
3676 X86DESCGENERIC Gen;
3677 /** Gate descriptor view. */
3678 X86DESCGATE Gate;
3679#endif
3680
3681 /** 8 bit unsigned integer view. */
3682 uint8_t au8[8];
3683 /** 16 bit unsigned integer view. */
3684 uint16_t au16[4];
3685 /** 32 bit unsigned integer view. */
3686 uint32_t au32[2];
3687 /** 64 bit unsigned integer view. */
3688 uint64_t au64[1];
3689 /** Unsigned integer view. */
3690 uint64_t u;
3691} X86DESC;
3692#ifndef VBOX_FOR_DTRACE_LIB
3693AssertCompileSize(X86DESC, 8);
3694#endif
3695#pragma pack()
3696/** Pointer to descriptor table entry. */
3697typedef X86DESC *PX86DESC;
3698/** Pointer to const descriptor table entry. */
3699typedef const X86DESC *PCX86DESC;
3700
3701/** @def X86DESC_BASE
3702 * Return the base address of a descriptor.
3703 */
3704#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
3705 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3706 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3707 | ( (a_pDesc)->Gen.u16BaseLow ) )
3708
3709/** @def X86DESC_LIMIT
3710 * Return the limit of a descriptor.
3711 */
3712#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
3713 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3714 | ( (a_pDesc)->Gen.u16LimitLow ) )
3715
3716/** @def X86DESC_LIMIT_G
3717 * Return the limit of a descriptor with the granularity bit taken into account.
3718 * @returns Selector limit (uint32_t).
3719 * @param a_pDesc Pointer to the descriptor.
3720 */
3721#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
3722 ( (a_pDesc)->Gen.u1Granularity \
3723 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
3724 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
3725 )
3726
3727/** @def X86DESC_GET_HID_ATTR
3728 * Get the descriptor attributes for the hidden register.
3729 */
3730#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
3731 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3732
3733#ifndef VBOX_FOR_DTRACE_LIB
3734
3735/**
3736 * 64 bits generic descriptor table entry
3737 * Note: most of these bits have no meaning in long mode.
3738 */
3739#pragma pack(1)
3740typedef struct X86DESC64GENERIC
3741{
3742 /** Limit - Low word - *IGNORED*. */
3743 uint32_t u16LimitLow : 16;
3744 /** Base address - low word. - *IGNORED*
3745 * Don't try set this to 24 because MSC is doing stupid things then. */
3746 uint32_t u16BaseLow : 16;
3747 /** Base address - first 8 bits of high word. - *IGNORED* */
3748 uint32_t u8BaseHigh1 : 8;
3749 /** Segment Type. */
3750 uint32_t u4Type : 4;
3751 /** Descriptor Type. System(=0) or code/data selector */
3752 uint32_t u1DescType : 1;
3753 /** Descriptor Privilege level. */
3754 uint32_t u2Dpl : 2;
3755 /** Flags selector present(=1) or not. */
3756 uint32_t u1Present : 1;
3757 /** Segment limit 16-19. - *IGNORED* */
3758 uint32_t u4LimitHigh : 4;
3759 /** Available for system software. - *IGNORED* */
3760 uint32_t u1Available : 1;
3761 /** Long mode flag. */
3762 uint32_t u1Long : 1;
3763 /** This flags meaning depends on the segment type. Try make sense out
3764 * of the intel manual yourself. */
3765 uint32_t u1DefBig : 1;
3766 /** Granularity of the limit. If set 4KB granularity is used, if
3767 * clear byte. - *IGNORED* */
3768 uint32_t u1Granularity : 1;
3769 /** Base address - highest 8 bits. - *IGNORED* */
3770 uint32_t u8BaseHigh2 : 8;
3771 /** Base address - bits 63-32. */
3772 uint32_t u32BaseHigh3 : 32;
3773 uint32_t u8Reserved : 8;
3774 uint32_t u5Zeros : 5;
3775 uint32_t u19Reserved : 19;
3776} X86DESC64GENERIC;
3777#pragma pack()
3778/** Pointer to a generic descriptor entry. */
3779typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3780/** Pointer to a const generic descriptor entry. */
3781typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3782
3783/**
3784 * System descriptor table entry (64 bits)
3785 *
3786 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3787 */
3788#pragma pack(1)
3789typedef struct X86DESC64SYSTEM
3790{
3791 /** Limit - Low word. */
3792 uint32_t u16LimitLow : 16;
3793 /** Base address - low word.
3794 * Don't try set this to 24 because MSC is doing stupid things then. */
3795 uint32_t u16BaseLow : 16;
3796 /** Base address - first 8 bits of high word. */
3797 uint32_t u8BaseHigh1 : 8;
3798 /** Segment Type. */
3799 uint32_t u4Type : 4;
3800 /** Descriptor Type. System(=0) or code/data selector */
3801 uint32_t u1DescType : 1;
3802 /** Descriptor Privilege level. */
3803 uint32_t u2Dpl : 2;
3804 /** Flags selector present(=1) or not. */
3805 uint32_t u1Present : 1;
3806 /** Segment limit 16-19. */
3807 uint32_t u4LimitHigh : 4;
3808 /** Available for system software. */
3809 uint32_t u1Available : 1;
3810 /** Reserved - 0. */
3811 uint32_t u1Reserved : 1;
3812 /** This flags meaning depends on the segment type. Try make sense out
3813 * of the intel manual yourself. */
3814 uint32_t u1DefBig : 1;
3815 /** Granularity of the limit. If set 4KB granularity is used, if
3816 * clear byte. */
3817 uint32_t u1Granularity : 1;
3818 /** Base address - bits 31-24. */
3819 uint32_t u8BaseHigh2 : 8;
3820 /** Base address - bits 63-32. */
3821 uint32_t u32BaseHigh3 : 32;
3822 uint32_t u8Reserved : 8;
3823 uint32_t u5Zeros : 5;
3824 uint32_t u19Reserved : 19;
3825} X86DESC64SYSTEM;
3826#pragma pack()
3827/** Pointer to a system descriptor entry. */
3828typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3829/** Pointer to a const system descriptor entry. */
3830typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3831
3832/**
3833 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3834 */
3835typedef struct X86DESC64GATE
3836{
3837 /** Target code segment offset - Low word. */
3838 uint32_t u16OffsetLow : 16;
3839 /** Target code segment selector. */
3840 uint32_t u16Sel : 16;
3841 /** Interrupt stack table for interrupt- and trap-gates.
3842 * Ignored by call-gates. */
3843 uint32_t u3IST : 3;
3844 /** Reserved / ignored. */
3845 uint32_t u5Reserved : 5;
3846 /** Segment Type. */
3847 uint32_t u4Type : 4;
3848 /** Descriptor Type (0 = system). */
3849 uint32_t u1DescType : 1;
3850 /** Descriptor Privilege level. */
3851 uint32_t u2Dpl : 2;
3852 /** Flags selector present(=1) or not. */
3853 uint32_t u1Present : 1;
3854 /** Target code segment offset - High word.
3855 * Ignored if task-gate. */
3856 uint32_t u16OffsetHigh : 16;
3857 /** Target code segment offset - Top dword.
3858 * Ignored if task-gate. */
3859 uint32_t u32OffsetTop : 32;
3860 /** Reserved / ignored / must be zero.
3861 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3862 uint32_t u32Reserved : 32;
3863} X86DESC64GATE;
3864AssertCompileSize(X86DESC64GATE, 16);
3865/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3866typedef X86DESC64GATE *PX86DESC64GATE;
3867/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3868typedef const X86DESC64GATE *PCX86DESC64GATE;
3869
3870#endif /* VBOX_FOR_DTRACE_LIB */
3871
3872/**
3873 * Descriptor table entry.
3874 */
3875#pragma pack(1)
3876typedef union X86DESC64
3877{
3878#ifndef VBOX_FOR_DTRACE_LIB
3879 /** Generic descriptor view. */
3880 X86DESC64GENERIC Gen;
3881 /** System descriptor view. */
3882 X86DESC64SYSTEM System;
3883 /** Gate descriptor view. */
3884 X86DESC64GATE Gate;
3885#endif
3886
3887 /** 8 bit unsigned integer view. */
3888 uint8_t au8[16];
3889 /** 16 bit unsigned integer view. */
3890 uint16_t au16[8];
3891 /** 32 bit unsigned integer view. */
3892 uint32_t au32[4];
3893 /** 64 bit unsigned integer view. */
3894 uint64_t au64[2];
3895} X86DESC64;
3896#ifndef VBOX_FOR_DTRACE_LIB
3897AssertCompileSize(X86DESC64, 16);
3898#endif
3899#pragma pack()
3900/** Pointer to descriptor table entry. */
3901typedef X86DESC64 *PX86DESC64;
3902/** Pointer to const descriptor table entry. */
3903typedef const X86DESC64 *PCX86DESC64;
3904
3905/** @def X86DESC64_BASE
3906 * Return the base of a 64-bit descriptor.
3907 */
3908#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
3909 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3910 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3911 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3912 | ( (a_pDesc)->Gen.u16BaseLow ) )
3913
3914
3915
3916/** @name Host system descriptor table entry - Use with care!
3917 * @{ */
3918/** Host system descriptor table entry. */
3919#if HC_ARCH_BITS == 64
3920typedef X86DESC64 X86DESCHC;
3921#else
3922typedef X86DESC X86DESCHC;
3923#endif
3924/** Pointer to a host system descriptor table entry. */
3925#if HC_ARCH_BITS == 64
3926typedef PX86DESC64 PX86DESCHC;
3927#else
3928typedef PX86DESC PX86DESCHC;
3929#endif
3930/** Pointer to a const host system descriptor table entry. */
3931#if HC_ARCH_BITS == 64
3932typedef PCX86DESC64 PCX86DESCHC;
3933#else
3934typedef PCX86DESC PCX86DESCHC;
3935#endif
3936/** @} */
3937
3938
3939/** @name Selector Descriptor Types.
3940 * @{
3941 */
3942
3943/** @name Non-System Selector Types.
3944 * @{ */
3945/** Code(=set)/Data(=clear) bit. */
3946#define X86_SEL_TYPE_CODE 8
3947/** Memory(=set)/System(=clear) bit. */
3948#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3949/** Accessed bit. */
3950#define X86_SEL_TYPE_ACCESSED 1
3951/** Expand down bit (for data selectors only). */
3952#define X86_SEL_TYPE_DOWN 4
3953/** Conforming bit (for code selectors only). */
3954#define X86_SEL_TYPE_CONF 4
3955/** Write bit (for data selectors only). */
3956#define X86_SEL_TYPE_WRITE 2
3957/** Read bit (for code selectors only). */
3958#define X86_SEL_TYPE_READ 2
3959/** The bit number of the code segment read bit (relative to u4Type). */
3960#define X86_SEL_TYPE_READ_BIT 1
3961
3962/** Read only selector type. */
3963#define X86_SEL_TYPE_RO 0
3964/** Accessed read only selector type. */
3965#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
3966/** Read write selector type. */
3967#define X86_SEL_TYPE_RW 2
3968/** Accessed read write selector type. */
3969#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
3970/** Expand down read only selector type. */
3971#define X86_SEL_TYPE_RO_DOWN 4
3972/** Accessed expand down read only selector type. */
3973#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
3974/** Expand down read write selector type. */
3975#define X86_SEL_TYPE_RW_DOWN 6
3976/** Accessed expand down read write selector type. */
3977#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
3978/** Execute only selector type. */
3979#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
3980/** Accessed execute only selector type. */
3981#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3982/** Execute and read selector type. */
3983#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
3984/** Accessed execute and read selector type. */
3985#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3986/** Conforming execute only selector type. */
3987#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
3988/** Accessed Conforming execute only selector type. */
3989#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3990/** Conforming execute and write selector type. */
3991#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
3992/** Accessed Conforming execute and write selector type. */
3993#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3994/** @} */
3995
3996
3997/** @name System Selector Types.
3998 * @{ */
3999/** The TSS busy bit mask. */
4000#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4001
4002/** Undefined system selector type. */
4003#define X86_SEL_TYPE_SYS_UNDEFINED 0
4004/** 286 TSS selector. */
4005#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4006/** LDT selector. */
4007#define X86_SEL_TYPE_SYS_LDT 2
4008/** 286 TSS selector - Busy. */
4009#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4010/** 286 Callgate selector. */
4011#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4012/** Taskgate selector. */
4013#define X86_SEL_TYPE_SYS_TASK_GATE 5
4014/** 286 Interrupt gate selector. */
4015#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4016/** 286 Trapgate selector. */
4017#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4018/** Undefined system selector. */
4019#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4020/** 386 TSS selector. */
4021#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4022/** Undefined system selector. */
4023#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4024/** 386 TSS selector - Busy. */
4025#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4026/** 386 Callgate selector. */
4027#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4028/** Undefined system selector. */
4029#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4030/** 386 Interruptgate selector. */
4031#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4032/** 386 Trapgate selector. */
4033#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4034/** @} */
4035
4036/** @name AMD64 System Selector Types.
4037 * @{ */
4038/** LDT selector. */
4039#define AMD64_SEL_TYPE_SYS_LDT 2
4040/** TSS selector - Busy. */
4041#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4042/** TSS selector - Busy. */
4043#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4044/** Callgate selector. */
4045#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4046/** Interruptgate selector. */
4047#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4048/** Trapgate selector. */
4049#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4050/** @} */
4051
4052/** @} */
4053
4054
4055/** @name Descriptor Table Entry Flag Masks.
4056 * These are for the 2nd 32-bit word of a descriptor.
4057 * @{ */
4058/** Bits 8-11 - TYPE - Descriptor type mask. */
4059#define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
4060/** Bit 12 - S - System (=0) or Code/Data (=1). */
4061#define X86_DESC_S RT_BIT_32(12)
4062/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4063#define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
4064/** Bit 15 - P - Present. */
4065#define X86_DESC_P RT_BIT_32(15)
4066/** Bit 20 - AVL - Available for system software. */
4067#define X86_DESC_AVL RT_BIT_32(20)
4068/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4069#define X86_DESC_DB RT_BIT_32(22)
4070/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4071 * used, if clear byte. */
4072#define X86_DESC_G RT_BIT_32(23)
4073/** @} */
4074
4075/** @} */
4076
4077
4078/** @name Task Segments.
4079 * @{
4080 */
4081
4082/**
4083 * The minimum TSS descriptor limit for 286 tasks.
4084 */
4085#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4086
4087/**
4088 * The minimum TSS descriptor segment limit for 386 tasks.
4089 */
4090#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4091
4092/**
4093 * 16-bit Task Segment (TSS).
4094 */
4095#pragma pack(1)
4096typedef struct X86TSS16
4097{
4098 /** Back link to previous task. (static) */
4099 RTSEL selPrev;
4100 /** Ring-0 stack pointer. (static) */
4101 uint16_t sp0;
4102 /** Ring-0 stack segment. (static) */
4103 RTSEL ss0;
4104 /** Ring-1 stack pointer. (static) */
4105 uint16_t sp1;
4106 /** Ring-1 stack segment. (static) */
4107 RTSEL ss1;
4108 /** Ring-2 stack pointer. (static) */
4109 uint16_t sp2;
4110 /** Ring-2 stack segment. (static) */
4111 RTSEL ss2;
4112 /** IP before task switch. */
4113 uint16_t ip;
4114 /** FLAGS before task switch. */
4115 uint16_t flags;
4116 /** AX before task switch. */
4117 uint16_t ax;
4118 /** CX before task switch. */
4119 uint16_t cx;
4120 /** DX before task switch. */
4121 uint16_t dx;
4122 /** BX before task switch. */
4123 uint16_t bx;
4124 /** SP before task switch. */
4125 uint16_t sp;
4126 /** BP before task switch. */
4127 uint16_t bp;
4128 /** SI before task switch. */
4129 uint16_t si;
4130 /** DI before task switch. */
4131 uint16_t di;
4132 /** ES before task switch. */
4133 RTSEL es;
4134 /** CS before task switch. */
4135 RTSEL cs;
4136 /** SS before task switch. */
4137 RTSEL ss;
4138 /** DS before task switch. */
4139 RTSEL ds;
4140 /** LDTR before task switch. */
4141 RTSEL selLdt;
4142} X86TSS16;
4143#ifndef VBOX_FOR_DTRACE_LIB
4144AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4145#endif
4146#pragma pack()
4147/** Pointer to a 16-bit task segment. */
4148typedef X86TSS16 *PX86TSS16;
4149/** Pointer to a const 16-bit task segment. */
4150typedef const X86TSS16 *PCX86TSS16;
4151
4152
4153/**
4154 * 32-bit Task Segment (TSS).
4155 */
4156#pragma pack(1)
4157typedef struct X86TSS32
4158{
4159 /** Back link to previous task. (static) */
4160 RTSEL selPrev;
4161 uint16_t padding1;
4162 /** Ring-0 stack pointer. (static) */
4163 uint32_t esp0;
4164 /** Ring-0 stack segment. (static) */
4165 RTSEL ss0;
4166 uint16_t padding_ss0;
4167 /** Ring-1 stack pointer. (static) */
4168 uint32_t esp1;
4169 /** Ring-1 stack segment. (static) */
4170 RTSEL ss1;
4171 uint16_t padding_ss1;
4172 /** Ring-2 stack pointer. (static) */
4173 uint32_t esp2;
4174 /** Ring-2 stack segment. (static) */
4175 RTSEL ss2;
4176 uint16_t padding_ss2;
4177 /** Page directory for the task. (static) */
4178 uint32_t cr3;
4179 /** EIP before task switch. */
4180 uint32_t eip;
4181 /** EFLAGS before task switch. */
4182 uint32_t eflags;
4183 /** EAX before task switch. */
4184 uint32_t eax;
4185 /** ECX before task switch. */
4186 uint32_t ecx;
4187 /** EDX before task switch. */
4188 uint32_t edx;
4189 /** EBX before task switch. */
4190 uint32_t ebx;
4191 /** ESP before task switch. */
4192 uint32_t esp;
4193 /** EBP before task switch. */
4194 uint32_t ebp;
4195 /** ESI before task switch. */
4196 uint32_t esi;
4197 /** EDI before task switch. */
4198 uint32_t edi;
4199 /** ES before task switch. */
4200 RTSEL es;
4201 uint16_t padding_es;
4202 /** CS before task switch. */
4203 RTSEL cs;
4204 uint16_t padding_cs;
4205 /** SS before task switch. */
4206 RTSEL ss;
4207 uint16_t padding_ss;
4208 /** DS before task switch. */
4209 RTSEL ds;
4210 uint16_t padding_ds;
4211 /** FS before task switch. */
4212 RTSEL fs;
4213 uint16_t padding_fs;
4214 /** GS before task switch. */
4215 RTSEL gs;
4216 uint16_t padding_gs;
4217 /** LDTR before task switch. */
4218 RTSEL selLdt;
4219 uint16_t padding_ldt;
4220 /** Debug trap flag */
4221 uint16_t fDebugTrap;
4222 /** Offset relative to the TSS of the start of the I/O Bitmap
4223 * and the end of the interrupt redirection bitmap. */
4224 uint16_t offIoBitmap;
4225} X86TSS32;
4226#pragma pack()
4227/** Pointer to task segment. */
4228typedef X86TSS32 *PX86TSS32;
4229/** Pointer to const task segment. */
4230typedef const X86TSS32 *PCX86TSS32;
4231#ifndef VBOX_FOR_DTRACE_LIB
4232AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4233AssertCompileMemberOffset(X86TSS32, cr3, 28);
4234AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4235#endif
4236
4237/**
4238 * 64-bit Task segment.
4239 */
4240#pragma pack(1)
4241typedef struct X86TSS64
4242{
4243 /** Reserved. */
4244 uint32_t u32Reserved;
4245 /** Ring-0 stack pointer. (static) */
4246 uint64_t rsp0;
4247 /** Ring-1 stack pointer. (static) */
4248 uint64_t rsp1;
4249 /** Ring-2 stack pointer. (static) */
4250 uint64_t rsp2;
4251 /** Reserved. */
4252 uint32_t u32Reserved2[2];
4253 /* IST */
4254 uint64_t ist1;
4255 uint64_t ist2;
4256 uint64_t ist3;
4257 uint64_t ist4;
4258 uint64_t ist5;
4259 uint64_t ist6;
4260 uint64_t ist7;
4261 /* Reserved. */
4262 uint16_t u16Reserved[5];
4263 /** Offset relative to the TSS of the start of the I/O Bitmap
4264 * and the end of the interrupt redirection bitmap. */
4265 uint16_t offIoBitmap;
4266} X86TSS64;
4267#pragma pack()
4268/** Pointer to a 64-bit task segment. */
4269typedef X86TSS64 *PX86TSS64;
4270/** Pointer to a const 64-bit task segment. */
4271typedef const X86TSS64 *PCX86TSS64;
4272#ifndef VBOX_FOR_DTRACE_LIB
4273AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4274#endif
4275
4276/** @} */
4277
4278
4279/** @name Selectors.
4280 * @{
4281 */
4282
4283/**
4284 * The shift used to convert a selector from and to index an index (C).
4285 */
4286#define X86_SEL_SHIFT 3
4287
4288/**
4289 * The mask used to mask off the table indicator and RPL of an selector.
4290 */
4291#define X86_SEL_MASK 0xfff8U
4292
4293/**
4294 * The mask used to mask off the RPL of an selector.
4295 * This is suitable for checking for NULL selectors.
4296 */
4297#define X86_SEL_MASK_OFF_RPL 0xfffcU
4298
4299/**
4300 * The bit indicating that a selector is in the LDT and not in the GDT.
4301 */
4302#define X86_SEL_LDT 0x0004U
4303
4304/**
4305 * The bit mask for getting the RPL of a selector.
4306 */
4307#define X86_SEL_RPL 0x0003U
4308
4309/**
4310 * The mask covering both RPL and LDT.
4311 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4312 * checks.
4313 */
4314#define X86_SEL_RPL_LDT 0x0007U
4315
4316/** @} */
4317
4318
4319/**
4320 * x86 Exceptions/Faults/Traps.
4321 */
4322typedef enum X86XCPT
4323{
4324 /** \#DE - Divide error. */
4325 X86_XCPT_DE = 0x00,
4326 /** \#DB - Debug event (single step, DRx, ..) */
4327 X86_XCPT_DB = 0x01,
4328 /** NMI - Non-Maskable Interrupt */
4329 X86_XCPT_NMI = 0x02,
4330 /** \#BP - Breakpoint (INT3). */
4331 X86_XCPT_BP = 0x03,
4332 /** \#OF - Overflow (INTO). */
4333 X86_XCPT_OF = 0x04,
4334 /** \#BR - Bound range exceeded (BOUND). */
4335 X86_XCPT_BR = 0x05,
4336 /** \#UD - Undefined opcode. */
4337 X86_XCPT_UD = 0x06,
4338 /** \#NM - Device not available (math coprocessor device). */
4339 X86_XCPT_NM = 0x07,
4340 /** \#DF - Double fault. */
4341 X86_XCPT_DF = 0x08,
4342 /** ??? - Coprocessor segment overrun (obsolete). */
4343 X86_XCPT_CO_SEG_OVERRUN = 0x09,
4344 /** \#TS - Taskswitch (TSS). */
4345 X86_XCPT_TS = 0x0a,
4346 /** \#NP - Segment no present. */
4347 X86_XCPT_NP = 0x0b,
4348 /** \#SS - Stack segment fault. */
4349 X86_XCPT_SS = 0x0c,
4350 /** \#GP - General protection fault. */
4351 X86_XCPT_GP = 0x0d,
4352 /** \#PF - Page fault. */
4353 X86_XCPT_PF = 0x0e,
4354 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4355 /** \#MF - Math fault (FPU). */
4356 X86_XCPT_MF = 0x10,
4357 /** \#AC - Alignment check. */
4358 X86_XCPT_AC = 0x11,
4359 /** \#MC - Machine check. */
4360 X86_XCPT_MC = 0x12,
4361 /** \#XF - SIMD Floating-Point Exception. */
4362 X86_XCPT_XF = 0x13,
4363 /** \#VE - Virtualization Exception (Intel only). */
4364 X86_XCPT_VE = 0x14,
4365 /** \#CP - Control Protection Exception (Intel only). */
4366 X86_XCPT_CP = 0x15,
4367 /** \#VC - VMM Communication Exception (AMD only). */
4368 X86_XCPT_VC = 0x1d,
4369 /** \#SX - Security Exception (AMD only). */
4370 X86_XCPT_SX = 0x1e
4371} X86XCPT;
4372/** Pointer to a x86 exception code. */
4373typedef X86XCPT *PX86XCPT;
4374/** Pointer to a const x86 exception code. */
4375typedef const X86XCPT *PCX86XCPT;
4376/** The last valid (currently reserved) exception value. */
4377#define X86_XCPT_LAST 0x1f
4378
4379
4380/** @name Trap Error Codes
4381 * @{
4382 */
4383/** External indicator. */
4384#define X86_TRAP_ERR_EXTERNAL 1
4385/** IDT indicator. */
4386#define X86_TRAP_ERR_IDT 2
4387/** Descriptor table indicator - If set LDT, if clear GDT. */
4388#define X86_TRAP_ERR_TI 4
4389/** Mask for getting the selector. */
4390#define X86_TRAP_ERR_SEL_MASK 0xfff8
4391/** Shift for getting the selector table index (C type index). */
4392#define X86_TRAP_ERR_SEL_SHIFT 3
4393/** @} */
4394
4395
4396/** @name \#PF Trap Error Codes
4397 * @{
4398 */
4399/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4400#define X86_TRAP_PF_P RT_BIT_32(0)
4401/** Bit 1 - R/W - Read (clear) or write (set) access. */
4402#define X86_TRAP_PF_RW RT_BIT_32(1)
4403/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4404#define X86_TRAP_PF_US RT_BIT_32(2)
4405/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4406#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4407/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4408#define X86_TRAP_PF_ID RT_BIT_32(4)
4409/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4410#define X86_TRAP_PF_PK RT_BIT_32(5)
4411/** @} */
4412
4413#pragma pack(1)
4414/**
4415 * 16-bit IDTR.
4416 */
4417typedef struct X86IDTR16
4418{
4419 /** Offset. */
4420 uint16_t offSel;
4421 /** Selector. */
4422 uint16_t uSel;
4423} X86IDTR16, *PX86IDTR16;
4424#pragma pack()
4425
4426#pragma pack(1)
4427/**
4428 * 32-bit IDTR/GDTR.
4429 */
4430typedef struct X86XDTR32
4431{
4432 /** Size of the descriptor table. */
4433 uint16_t cb;
4434 /** Address of the descriptor table. */
4435#ifndef VBOX_FOR_DTRACE_LIB
4436 uint32_t uAddr;
4437#else
4438 uint16_t au16Addr[2];
4439#endif
4440} X86XDTR32, *PX86XDTR32;
4441#pragma pack()
4442
4443#pragma pack(1)
4444/**
4445 * 64-bit IDTR/GDTR.
4446 */
4447typedef struct X86XDTR64
4448{
4449 /** Size of the descriptor table. */
4450 uint16_t cb;
4451 /** Address of the descriptor table. */
4452#ifndef VBOX_FOR_DTRACE_LIB
4453 uint64_t uAddr;
4454#else
4455 uint16_t au16Addr[4];
4456#endif
4457} X86XDTR64, *PX86XDTR64;
4458#pragma pack()
4459
4460
4461/** @name ModR/M
4462 * @{ */
4463#define X86_MODRM_RM_MASK UINT8_C(0x07)
4464#define X86_MODRM_REG_MASK UINT8_C(0x38)
4465#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4466#define X86_MODRM_REG_SHIFT 3
4467#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4468#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4469#define X86_MODRM_MOD_SHIFT 6
4470#ifndef VBOX_FOR_DTRACE_LIB
4471AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
4472AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4473AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4474/** @def X86_MODRM_MAKE
4475 * @param a_Mod The mod value (0..3).
4476 * @param a_Reg The register value (0..7).
4477 * @param a_RegMem The register or memory value (0..7). */
4478# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
4479#endif
4480/** @} */
4481
4482/** @name SIB
4483 * @{ */
4484#define X86_SIB_BASE_MASK UINT8_C(0x07)
4485#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4486#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4487#define X86_SIB_INDEX_SHIFT 3
4488#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4489#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4490#define X86_SIB_SCALE_SHIFT 6
4491#ifndef VBOX_FOR_DTRACE_LIB
4492AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
4493AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4494AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4495#endif
4496/** @} */
4497
4498/** @name General register indexes.
4499 * @{ */
4500#define X86_GREG_xAX 0
4501#define X86_GREG_xCX 1
4502#define X86_GREG_xDX 2
4503#define X86_GREG_xBX 3
4504#define X86_GREG_xSP 4
4505#define X86_GREG_xBP 5
4506#define X86_GREG_xSI 6
4507#define X86_GREG_xDI 7
4508#define X86_GREG_x8 8
4509#define X86_GREG_x9 9
4510#define X86_GREG_x10 10
4511#define X86_GREG_x11 11
4512#define X86_GREG_x12 12
4513#define X86_GREG_x13 13
4514#define X86_GREG_x14 14
4515#define X86_GREG_x15 15
4516/** @} */
4517/** General register count. */
4518#define X86_GREG_COUNT 16
4519
4520/** @name X86_SREG_XXX - Segment register indexes.
4521 * @{ */
4522#define X86_SREG_ES 0
4523#define X86_SREG_CS 1
4524#define X86_SREG_SS 2
4525#define X86_SREG_DS 3
4526#define X86_SREG_FS 4
4527#define X86_SREG_GS 5
4528/** @} */
4529/** Segment register count. */
4530#define X86_SREG_COUNT 6
4531
4532
4533/** @name X86_OP_XXX - Prefixes
4534 * @{ */
4535#define X86_OP_PRF_CS UINT8_C(0x2e)
4536#define X86_OP_PRF_SS UINT8_C(0x36)
4537#define X86_OP_PRF_DS UINT8_C(0x3e)
4538#define X86_OP_PRF_ES UINT8_C(0x26)
4539#define X86_OP_PRF_FS UINT8_C(0x64)
4540#define X86_OP_PRF_GS UINT8_C(0x65)
4541#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4542#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4543#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4544#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4545#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4546#define X86_OP_REX_B UINT8_C(0x41)
4547#define X86_OP_REX_X UINT8_C(0x42)
4548#define X86_OP_REX_R UINT8_C(0x44)
4549#define X86_OP_REX_W UINT8_C(0x48)
4550/** @} */
4551
4552
4553/** @} */
4554
4555#endif /* !IPRT_INCLUDED_x86_h */
4556
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