VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 76553

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1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2019 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef ___iprt_x86_h
29#define ___iprt_x86_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#ifndef VBOX_FOR_DTRACE_LIB
35# include <iprt/types.h>
36# include <iprt/assert.h>
37#else
38# pragma D depends_on library vbox-types.d
39#endif
40
41/* Workaround for Solaris sys/regset.h defining CS, DS */
42#ifdef RT_OS_SOLARIS
43# undef CS
44# undef DS
45#endif
46
47/** @defgroup grp_rt_x86 x86 Types and Definitions
48 * @ingroup grp_rt
49 * @{
50 */
51
52#ifndef VBOX_FOR_DTRACE_LIB
53/**
54 * EFLAGS Bits.
55 */
56typedef struct X86EFLAGSBITS
57{
58 /** Bit 0 - CF - Carry flag - Status flag. */
59 unsigned u1CF : 1;
60 /** Bit 1 - 1 - Reserved flag. */
61 unsigned u1Reserved0 : 1;
62 /** Bit 2 - PF - Parity flag - Status flag. */
63 unsigned u1PF : 1;
64 /** Bit 3 - 0 - Reserved flag. */
65 unsigned u1Reserved1 : 1;
66 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
67 unsigned u1AF : 1;
68 /** Bit 5 - 0 - Reserved flag. */
69 unsigned u1Reserved2 : 1;
70 /** Bit 6 - ZF - Zero flag - Status flag. */
71 unsigned u1ZF : 1;
72 /** Bit 7 - SF - Signed flag - Status flag. */
73 unsigned u1SF : 1;
74 /** Bit 8 - TF - Trap flag - System flag. */
75 unsigned u1TF : 1;
76 /** Bit 9 - IF - Interrupt flag - System flag. */
77 unsigned u1IF : 1;
78 /** Bit 10 - DF - Direction flag - Control flag. */
79 unsigned u1DF : 1;
80 /** Bit 11 - OF - Overflow flag - Status flag. */
81 unsigned u1OF : 1;
82 /** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
83 unsigned u2IOPL : 2;
84 /** Bit 14 - NT - Nested task flag - System flag. */
85 unsigned u1NT : 1;
86 /** Bit 15 - 0 - Reserved flag. */
87 unsigned u1Reserved3 : 1;
88 /** Bit 16 - RF - Resume flag - System flag. */
89 unsigned u1RF : 1;
90 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
91 unsigned u1VM : 1;
92 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
93 unsigned u1AC : 1;
94 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
95 unsigned u1VIF : 1;
96 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
97 unsigned u1VIP : 1;
98 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
99 unsigned u1ID : 1;
100 /** Bit 22-31 - 0 - Reserved flag. */
101 unsigned u10Reserved4 : 10;
102} X86EFLAGSBITS;
103/** Pointer to EFLAGS bits. */
104typedef X86EFLAGSBITS *PX86EFLAGSBITS;
105/** Pointer to const EFLAGS bits. */
106typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
107#endif /* !VBOX_FOR_DTRACE_LIB */
108
109/**
110 * EFLAGS.
111 */
112typedef union X86EFLAGS
113{
114 /** The plain unsigned view. */
115 uint32_t u;
116#ifndef VBOX_FOR_DTRACE_LIB
117 /** The bitfield view. */
118 X86EFLAGSBITS Bits;
119#endif
120 /** The 8-bit view. */
121 uint8_t au8[4];
122 /** The 16-bit view. */
123 uint16_t au16[2];
124 /** The 32-bit view. */
125 uint32_t au32[1];
126 /** The 32-bit view. */
127 uint32_t u32;
128} X86EFLAGS;
129/** Pointer to EFLAGS. */
130typedef X86EFLAGS *PX86EFLAGS;
131/** Pointer to const EFLAGS. */
132typedef const X86EFLAGS *PCX86EFLAGS;
133
134/**
135 * RFLAGS (32 upper bits are reserved).
136 */
137typedef union X86RFLAGS
138{
139 /** The plain unsigned view. */
140 uint64_t u;
141#ifndef VBOX_FOR_DTRACE_LIB
142 /** The bitfield view. */
143 X86EFLAGSBITS Bits;
144#endif
145 /** The 8-bit view. */
146 uint8_t au8[8];
147 /** The 16-bit view. */
148 uint16_t au16[4];
149 /** The 32-bit view. */
150 uint32_t au32[2];
151 /** The 64-bit view. */
152 uint64_t au64[1];
153 /** The 64-bit view. */
154 uint64_t u64;
155} X86RFLAGS;
156/** Pointer to RFLAGS. */
157typedef X86RFLAGS *PX86RFLAGS;
158/** Pointer to const RFLAGS. */
159typedef const X86RFLAGS *PCX86RFLAGS;
160
161
162/** @name EFLAGS
163 * @{
164 */
165/** Bit 0 - CF - Carry flag - Status flag. */
166#define X86_EFL_CF RT_BIT_32(0)
167#define X86_EFL_CF_BIT 0
168/** Bit 1 - Reserved, reads as 1. */
169#define X86_EFL_1 RT_BIT_32(1)
170/** Bit 2 - PF - Parity flag - Status flag. */
171#define X86_EFL_PF RT_BIT_32(2)
172/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
173#define X86_EFL_AF RT_BIT_32(4)
174#define X86_EFL_AF_BIT 4
175/** Bit 6 - ZF - Zero flag - Status flag. */
176#define X86_EFL_ZF RT_BIT_32(6)
177#define X86_EFL_ZF_BIT 6
178/** Bit 7 - SF - Signed flag - Status flag. */
179#define X86_EFL_SF RT_BIT_32(7)
180#define X86_EFL_SF_BIT 7
181/** Bit 8 - TF - Trap flag - System flag. */
182#define X86_EFL_TF RT_BIT_32(8)
183/** Bit 9 - IF - Interrupt flag - System flag. */
184#define X86_EFL_IF RT_BIT_32(9)
185/** Bit 10 - DF - Direction flag - Control flag. */
186#define X86_EFL_DF RT_BIT_32(10)
187/** Bit 11 - OF - Overflow flag - Status flag. */
188#define X86_EFL_OF RT_BIT_32(11)
189#define X86_EFL_OF_BIT 11
190/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
191#define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
192/** Bit 14 - NT - Nested task flag - System flag. */
193#define X86_EFL_NT RT_BIT_32(14)
194/** Bit 16 - RF - Resume flag - System flag. */
195#define X86_EFL_RF RT_BIT_32(16)
196/** Bit 17 - VM - Virtual 8086 mode - System flag. */
197#define X86_EFL_VM RT_BIT_32(17)
198/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
199#define X86_EFL_AC RT_BIT_32(18)
200/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
201#define X86_EFL_VIF RT_BIT_32(19)
202/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
203#define X86_EFL_VIP RT_BIT_32(20)
204/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
205#define X86_EFL_ID RT_BIT_32(21)
206/** All live bits. */
207#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
208/** Read as 1 bits. */
209#define X86_EFL_RA1_MASK RT_BIT_32(1)
210/** IOPL shift. */
211#define X86_EFL_IOPL_SHIFT 12
212/** The IOPL level from the flags. */
213#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
214/** Bits restored by popf */
215#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
216 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
217/** Bits restored by popf */
218#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
219 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
220/** The status bits commonly updated by arithmetic instructions. */
221#define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
222/** @} */
223
224
225/** CPUID Feature information - ECX.
226 * CPUID query with EAX=1.
227 */
228#ifndef VBOX_FOR_DTRACE_LIB
229typedef struct X86CPUIDFEATECX
230{
231 /** Bit 0 - SSE3 - Supports SSE3 or not. */
232 unsigned u1SSE3 : 1;
233 /** Bit 1 - PCLMULQDQ. */
234 unsigned u1PCLMULQDQ : 1;
235 /** Bit 2 - DS Area 64-bit layout. */
236 unsigned u1DTE64 : 1;
237 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
238 unsigned u1Monitor : 1;
239 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
240 unsigned u1CPLDS : 1;
241 /** Bit 5 - VMX - Virtual Machine Technology. */
242 unsigned u1VMX : 1;
243 /** Bit 6 - SMX: Safer Mode Extensions. */
244 unsigned u1SMX : 1;
245 /** Bit 7 - EST - Enh. SpeedStep Tech. */
246 unsigned u1EST : 1;
247 /** Bit 8 - TM2 - Terminal Monitor 2. */
248 unsigned u1TM2 : 1;
249 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
250 unsigned u1SSSE3 : 1;
251 /** Bit 10 - CNTX-ID - L1 Context ID. */
252 unsigned u1CNTXID : 1;
253 /** Bit 11 - Reserved. */
254 unsigned u1Reserved1 : 1;
255 /** Bit 12 - FMA. */
256 unsigned u1FMA : 1;
257 /** Bit 13 - CX16 - CMPXCHG16B. */
258 unsigned u1CX16 : 1;
259 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
260 unsigned u1TPRUpdate : 1;
261 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
262 unsigned u1PDCM : 1;
263 /** Bit 16 - Reserved. */
264 unsigned u1Reserved2 : 1;
265 /** Bit 17 - PCID - Process-context identifiers. */
266 unsigned u1PCID : 1;
267 /** Bit 18 - Direct Cache Access. */
268 unsigned u1DCA : 1;
269 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
270 unsigned u1SSE4_1 : 1;
271 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
272 unsigned u1SSE4_2 : 1;
273 /** Bit 21 - x2APIC. */
274 unsigned u1x2APIC : 1;
275 /** Bit 22 - MOVBE - Supports MOVBE. */
276 unsigned u1MOVBE : 1;
277 /** Bit 23 - POPCNT - Supports POPCNT. */
278 unsigned u1POPCNT : 1;
279 /** Bit 24 - TSC-Deadline. */
280 unsigned u1TSCDEADLINE : 1;
281 /** Bit 25 - AES. */
282 unsigned u1AES : 1;
283 /** Bit 26 - XSAVE - Supports XSAVE. */
284 unsigned u1XSAVE : 1;
285 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
286 unsigned u1OSXSAVE : 1;
287 /** Bit 28 - AVX - Supports AVX instruction extensions. */
288 unsigned u1AVX : 1;
289 /** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
290 unsigned u1F16C : 1;
291 /** Bit 30 - RDRAND - Supports RDRAND. */
292 unsigned u1RDRAND : 1;
293 /** Bit 31 - Hypervisor present (we're a guest). */
294 unsigned u1HVP : 1;
295} X86CPUIDFEATECX;
296#else /* VBOX_FOR_DTRACE_LIB */
297typedef uint32_t X86CPUIDFEATECX;
298#endif /* VBOX_FOR_DTRACE_LIB */
299/** Pointer to CPUID Feature Information - ECX. */
300typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
301/** Pointer to const CPUID Feature Information - ECX. */
302typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
303
304
305/** CPUID Feature Information - EDX.
306 * CPUID query with EAX=1.
307 */
308#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
309typedef struct X86CPUIDFEATEDX
310{
311 /** Bit 0 - FPU - x87 FPU on Chip. */
312 unsigned u1FPU : 1;
313 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
314 unsigned u1VME : 1;
315 /** Bit 2 - DE - Debugging extensions. */
316 unsigned u1DE : 1;
317 /** Bit 3 - PSE - Page Size Extension. */
318 unsigned u1PSE : 1;
319 /** Bit 4 - TSC - Time Stamp Counter. */
320 unsigned u1TSC : 1;
321 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
322 unsigned u1MSR : 1;
323 /** Bit 6 - PAE - Physical Address Extension. */
324 unsigned u1PAE : 1;
325 /** Bit 7 - MCE - Machine Check Exception. */
326 unsigned u1MCE : 1;
327 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
328 unsigned u1CX8 : 1;
329 /** Bit 9 - APIC - APIC On-Chip. */
330 unsigned u1APIC : 1;
331 /** Bit 10 - Reserved. */
332 unsigned u1Reserved1 : 1;
333 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
334 unsigned u1SEP : 1;
335 /** Bit 12 - MTRR - Memory Type Range Registers. */
336 unsigned u1MTRR : 1;
337 /** Bit 13 - PGE - PTE Global Bit. */
338 unsigned u1PGE : 1;
339 /** Bit 14 - MCA - Machine Check Architecture. */
340 unsigned u1MCA : 1;
341 /** Bit 15 - CMOV - Conditional Move Instructions. */
342 unsigned u1CMOV : 1;
343 /** Bit 16 - PAT - Page Attribute Table. */
344 unsigned u1PAT : 1;
345 /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
346 unsigned u1PSE36 : 1;
347 /** Bit 18 - PSN - Processor Serial Number. */
348 unsigned u1PSN : 1;
349 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
350 unsigned u1CLFSH : 1;
351 /** Bit 20 - Reserved. */
352 unsigned u1Reserved2 : 1;
353 /** Bit 21 - DS - Debug Store. */
354 unsigned u1DS : 1;
355 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
356 unsigned u1ACPI : 1;
357 /** Bit 23 - MMX - Intel MMX 'Technology'. */
358 unsigned u1MMX : 1;
359 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
360 unsigned u1FXSR : 1;
361 /** Bit 25 - SSE - SSE Support. */
362 unsigned u1SSE : 1;
363 /** Bit 26 - SSE2 - SSE2 Support. */
364 unsigned u1SSE2 : 1;
365 /** Bit 27 - SS - Self Snoop. */
366 unsigned u1SS : 1;
367 /** Bit 28 - HTT - Hyper-Threading Technology. */
368 unsigned u1HTT : 1;
369 /** Bit 29 - TM - Thermal Monitor. */
370 unsigned u1TM : 1;
371 /** Bit 30 - Reserved - . */
372 unsigned u1Reserved3 : 1;
373 /** Bit 31 - PBE - Pending Break Enabled. */
374 unsigned u1PBE : 1;
375} X86CPUIDFEATEDX;
376#else /* VBOX_FOR_DTRACE_LIB */
377typedef uint32_t X86CPUIDFEATEDX;
378#endif /* VBOX_FOR_DTRACE_LIB */
379/** Pointer to CPUID Feature Information - EDX. */
380typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
381/** Pointer to const CPUID Feature Information - EDX. */
382typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
383
384/** @name CPUID Vendor information.
385 * CPUID query with EAX=0.
386 * @{
387 */
388#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
389#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
390#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
391
392#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
393#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
394#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
395
396#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
397#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
398#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
399/** @} */
400
401
402/** @name CPUID Feature information.
403 * CPUID query with EAX=1.
404 * @{
405 */
406/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
407#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
408/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
409#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
410/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
411#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
412/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
413#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
414/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
415#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
416/** ECX Bit 5 - VMX - Virtual Machine Technology. */
417#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
418/** ECX Bit 6 - SMX - Safer Mode Extensions. */
419#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
420/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
421#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
422/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
423#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
424/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
425#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
426/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
427#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
428/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
429 * See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
430#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
431/** ECX Bit 12 - FMA. */
432#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
433/** ECX Bit 13 - CX16 - CMPXCHG16B. */
434#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
435/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
436#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
437/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
438#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
439/** ECX Bit 17 - PCID - Process-context identifiers. */
440#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
441/** ECX Bit 18 - DCA - Direct Cache Access. */
442#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
443/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
444#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
445/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
446#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
447/** ECX Bit 21 - x2APIC support. */
448#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
449/** ECX Bit 22 - MOVBE instruction. */
450#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
451/** ECX Bit 23 - POPCNT instruction. */
452#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
453/** ECX Bir 24 - TSC-Deadline. */
454#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
455/** ECX Bit 25 - AES instructions. */
456#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
457/** ECX Bit 26 - XSAVE instruction. */
458#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
459/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
460#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
461/** ECX Bit 28 - AVX. */
462#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
463/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
464#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
465/** ECX Bit 30 - RDRAND instruction. */
466#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
467/** ECX Bit 31 - Hypervisor Present (software only). */
468#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
469
470
471/** Bit 0 - FPU - x87 FPU on Chip. */
472#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
473/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
474#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
475/** Bit 2 - DE - Debugging extensions. */
476#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
477/** Bit 3 - PSE - Page Size Extension. */
478#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
479#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /**< Bit number for X86_CPUID_FEATURE_EDX_PSE. */
480/** Bit 4 - TSC - Time Stamp Counter. */
481#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
482/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
483#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
484/** Bit 6 - PAE - Physical Address Extension. */
485#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
486#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /**< Bit number for X86_CPUID_FEATURE_EDX_PAE. */
487/** Bit 7 - MCE - Machine Check Exception. */
488#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
489/** Bit 8 - CX8 - CMPXCHG8B instruction. */
490#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
491/** Bit 9 - APIC - APIC On-Chip. */
492#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
493/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
494#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
495/** Bit 12 - MTRR - Memory Type Range Registers. */
496#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
497/** Bit 13 - PGE - PTE Global Bit. */
498#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
499/** Bit 14 - MCA - Machine Check Architecture. */
500#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
501/** Bit 15 - CMOV - Conditional Move Instructions. */
502#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
503/** Bit 16 - PAT - Page Attribute Table. */
504#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
505/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
506#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
507/** Bit 18 - PSN - Processor Serial Number. */
508#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
509/** Bit 19 - CLFSH - CLFLUSH Instruction. */
510#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
511/** Bit 21 - DS - Debug Store. */
512#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
513/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
514#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
515/** Bit 23 - MMX - Intel MMX Technology. */
516#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
517/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
518#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
519/** Bit 25 - SSE - SSE Support. */
520#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
521/** Bit 26 - SSE2 - SSE2 Support. */
522#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
523/** Bit 27 - SS - Self Snoop. */
524#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
525/** Bit 28 - HTT - Hyper-Threading Technology. */
526#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
527/** Bit 29 - TM - Therm. Monitor. */
528#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
529/** Bit 31 - PBE - Pending Break Enabled. */
530#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
531/** @} */
532
533/** @name CPUID mwait/monitor information.
534 * CPUID query with EAX=5.
535 * @{
536 */
537/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
538#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
539/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
540#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
541/** @} */
542
543
544/** @name CPUID Structured Extended Feature information.
545 * CPUID query with EAX=7.
546 * @{
547 */
548/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
549#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
550/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
551#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
552/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
553#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
554/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
555#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
556/** EBX Bit 4 - HLE - Hardware Lock Elision. */
557#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
558/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
559#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
560/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
561#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
562/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
563#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
564/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
565#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
566/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
567#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
568/** EBX Bit 10 - INVPCID - Supports INVPCID. */
569#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
570/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
571#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
572/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
573#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
574/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
575#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
576/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
577#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
578/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
579#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
580/** EBX Bit 16 - AVX512F - Supports AVX512F. */
581#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
582/** EBX Bit 18 - RDSEED - Supports RDSEED. */
583#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
584/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
585#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
586/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
587#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
588/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
589#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
590/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
591#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
592/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
593#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
594/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
595#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
596/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
597#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
598/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
599#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
600
601/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
602#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
603/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
604#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
605/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
606#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
607/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
608#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
609/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
610#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
611/** ECX Bit 22 - RDPID - Support pread process ID. */
612#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
613/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
614#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
615
616/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
617 * IBPB command in IA32_PRED_CMD. */
618#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
619/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
620#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
621
622/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
623#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
624
625/** @} */
626
627
628/** @name CPUID Extended Feature information.
629 * CPUID query with EAX=0x80000001.
630 * @{
631 */
632/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
633#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
634
635/** EDX Bit 11 - SYSCALL/SYSRET. */
636#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
637/** EDX Bit 20 - No-Execute/Execute-Disable. */
638#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
639/** EDX Bit 26 - 1 GB large page. */
640#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
641/** EDX Bit 27 - RDTSCP. */
642#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
643/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
644#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
645/** @}*/
646
647/** @name CPUID AMD Feature information.
648 * CPUID query with EAX=0x80000001.
649 * @{
650 */
651/** Bit 0 - FPU - x87 FPU on Chip. */
652#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
653/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
654#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
655/** Bit 2 - DE - Debugging extensions. */
656#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
657/** Bit 3 - PSE - Page Size Extension. */
658#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
659/** Bit 4 - TSC - Time Stamp Counter. */
660#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
661/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
662#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
663/** Bit 6 - PAE - Physical Address Extension. */
664#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
665/** Bit 7 - MCE - Machine Check Exception. */
666#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
667/** Bit 8 - CX8 - CMPXCHG8B instruction. */
668#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
669/** Bit 9 - APIC - APIC On-Chip. */
670#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
671/** Bit 12 - MTRR - Memory Type Range Registers. */
672#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
673/** Bit 13 - PGE - PTE Global Bit. */
674#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
675/** Bit 14 - MCA - Machine Check Architecture. */
676#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
677/** Bit 15 - CMOV - Conditional Move Instructions. */
678#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
679/** Bit 16 - PAT - Page Attribute Table. */
680#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
681/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
682#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
683/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
684#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
685/** Bit 23 - MMX - Intel MMX Technology. */
686#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
687/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
688#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
689/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
690#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
691/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
692#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
693/** Bit 31 - 3DNOW - AMD 3DNow. */
694#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
695
696/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
697#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
698/** Bit 2 - SVM - AMD VM extensions. */
699#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
700/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
701#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
702/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
703#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
704/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
705#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
706/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
707#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
708/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
709#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
710/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
711#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
712/** Bit 9 - OSVW - AMD OS visible workaround. */
713#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
714/** Bit 10 - IBS - Instruct based sampling. */
715#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
716/** Bit 11 - XOP - Extended operation support (see APM6). */
717#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
718/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
719#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
720/** Bit 13 - WDT - AMD Watchdog timer support. */
721#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
722/** Bit 15 - LWP - Lightweight profiling support. */
723#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
724/** Bit 16 - FMA4 - Four operand FMA instruction support. */
725#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
726/** Bit 19 - NodeId - Indicates support for
727 * MSR_C001_100C[NodeId,NodesPerProcessr]. */
728#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
729/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
730#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
731/** Bit 22 - TopologyExtensions - . */
732#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
733/** @} */
734
735
736/** @name CPUID AMD Feature information.
737 * CPUID query with EAX=0x80000007.
738 * @{
739 */
740/** Bit 0 - TS - Temperature Sensor. */
741#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
742/** Bit 1 - FID - Frequency ID Control. */
743#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
744/** Bit 2 - VID - Voltage ID Control. */
745#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
746/** Bit 3 - TTP - THERMTRIP. */
747#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
748/** Bit 4 - TM - Hardware Thermal Control. */
749#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
750/** Bit 5 - STC - Software Thermal Control. */
751#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
752/** Bit 6 - MC - 100 Mhz Multiplier Control. */
753#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
754/** Bit 7 - HWPSTATE - Hardware P-State Control. */
755#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
756/** Bit 8 - TSCINVAR - TSC Invariant. */
757#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
758/** Bit 9 - CPB - TSC Invariant. */
759#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
760/** Bit 10 - EffFreqRO - MPERF/APERF. */
761#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
762/** Bit 11 - PFI - Processor feedback interface (see EAX). */
763#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
764/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
765#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
766/** @} */
767
768
769/** @name CPUID AMD extended feature extensions ID (EBX).
770 * CPUID query with EAX=0x80000008.
771 * @{
772 */
773/** Bit 0 - CLZERO - Clear zero instruction. */
774#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
775/** Bit 1 - IRPerf - Instructions retired count support. */
776#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
777/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
778#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
779/* AMD pipeline length: 9 feature bits ;-) */
780/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
781#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
782/** @} */
783
784
785/** @name CPUID AMD SVM Feature information.
786 * CPUID query with EAX=0x8000000a.
787 * @{
788 */
789/** Bit 0 - NP - Nested Paging supported. */
790#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
791/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
792#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
793/** Bit 2 - SVML - SVM locking bit supported. */
794#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
795/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
796#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
797/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
798#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
799/** Bit 5 - VmcbClean - Support VMCB clean bits. */
800#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
801/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
802 * VMCB.TLB_Control is supported. */
803#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
804/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
805#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
806/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
807#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
808/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
809 * intercept filter cycle count threshold. */
810#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
811/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
812#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
813/** Bit 15 - V_VMSAVE_VMLOAD - Supports virtualized VMSAVE/VMLOAD. */
814#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
815/** Bit 16 - V_VMSAVE_VMLOAD - Supports virtualized GIF. */
816#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
817/** @} */
818
819
820/** @name CR0
821 * @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
822 * reserved flags.
823 * @{ */
824/** Bit 0 - PE - Protection Enabled */
825#define X86_CR0_PE RT_BIT_32(0)
826#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
827/** Bit 1 - MP - Monitor Coprocessor */
828#define X86_CR0_MP RT_BIT_32(1)
829#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
830/** Bit 2 - EM - Emulation. */
831#define X86_CR0_EM RT_BIT_32(2)
832#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
833/** Bit 3 - TS - Task Switch. */
834#define X86_CR0_TS RT_BIT_32(3)
835#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
836/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
837#define X86_CR0_ET RT_BIT_32(4)
838#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
839/** Bit 5 - NE - Numeric error (486+). */
840#define X86_CR0_NE RT_BIT_32(5)
841#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
842/** Bit 16 - WP - Write Protect (486+). */
843#define X86_CR0_WP RT_BIT_32(16)
844#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
845/** Bit 18 - AM - Alignment Mask (486+). */
846#define X86_CR0_AM RT_BIT_32(18)
847#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
848/** Bit 29 - NW - Not Write-though (486+). */
849#define X86_CR0_NW RT_BIT_32(29)
850#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
851/** Bit 30 - WP - Cache Disable (486+). */
852#define X86_CR0_CD RT_BIT_32(30)
853#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
854/** Bit 31 - PG - Paging. */
855#define X86_CR0_PG RT_BIT_32(31)
856#define X86_CR0_PAGING RT_BIT_32(31)
857#define X86_CR0_BIT_PG 31 /**< Bit number of X86_CR0_PG */
858/** @} */
859
860
861/** @name CR3
862 * @{ */
863/** Bit 3 - PWT - Page-level Writes Transparent. */
864#define X86_CR3_PWT RT_BIT_32(3)
865/** Bit 4 - PCD - Page-level Cache Disable. */
866#define X86_CR3_PCD RT_BIT_32(4)
867/** Bits 12-31 - - Page directory page number. */
868#define X86_CR3_PAGE_MASK (0xfffff000)
869/** Bits 5-31 - - PAE Page directory page number. */
870#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
871/** Bits 12-51 - - AMD64 Page directory page number. */
872#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
873/** @} */
874
875
876/** @name CR4
877 * @{ */
878/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
879#define X86_CR4_VME RT_BIT_32(0)
880/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
881#define X86_CR4_PVI RT_BIT_32(1)
882/** Bit 2 - TSD - Time Stamp Disable. */
883#define X86_CR4_TSD RT_BIT_32(2)
884/** Bit 3 - DE - Debugging Extensions. */
885#define X86_CR4_DE RT_BIT_32(3)
886/** Bit 4 - PSE - Page Size Extension. */
887#define X86_CR4_PSE RT_BIT_32(4)
888/** Bit 5 - PAE - Physical Address Extension. */
889#define X86_CR4_PAE RT_BIT_32(5)
890/** Bit 6 - MCE - Machine-Check Enable. */
891#define X86_CR4_MCE RT_BIT_32(6)
892/** Bit 7 - PGE - Page Global Enable. */
893#define X86_CR4_PGE RT_BIT_32(7)
894/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
895#define X86_CR4_PCE RT_BIT_32(8)
896/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
897#define X86_CR4_OSFXSR RT_BIT_32(9)
898/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
899#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
900/** Bit 13 - VMXE - VMX mode is enabled. */
901#define X86_CR4_VMXE RT_BIT_32(13)
902/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
903#define X86_CR4_SMXE RT_BIT_32(14)
904/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
905#define X86_CR4_FSGSBASE RT_BIT_32(16)
906/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
907#define X86_CR4_PCIDE RT_BIT_32(17)
908/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
909 * extended states. */
910#define X86_CR4_OSXSAVE RT_BIT_32(18)
911/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
912#define X86_CR4_SMEP RT_BIT_32(20)
913/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
914#define X86_CR4_SMAP RT_BIT_32(21)
915/** Bit 22 - PKE - Protection Key Enable. */
916#define X86_CR4_PKE RT_BIT_32(22)
917/** @} */
918
919
920/** @name DR6
921 * @{ */
922/** Bit 0 - B0 - Breakpoint 0 condition detected. */
923#define X86_DR6_B0 RT_BIT_32(0)
924/** Bit 1 - B1 - Breakpoint 1 condition detected. */
925#define X86_DR6_B1 RT_BIT_32(1)
926/** Bit 2 - B2 - Breakpoint 2 condition detected. */
927#define X86_DR6_B2 RT_BIT_32(2)
928/** Bit 3 - B3 - Breakpoint 3 condition detected. */
929#define X86_DR6_B3 RT_BIT_32(3)
930/** Mask of all the Bx bits. */
931#define X86_DR6_B_MASK UINT64_C(0x0000000f)
932/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
933#define X86_DR6_BD RT_BIT_32(13)
934/** Bit 14 - BS - Single step */
935#define X86_DR6_BS RT_BIT_32(14)
936/** Bit 15 - BT - Task switch. (TSS T bit.) */
937#define X86_DR6_BT RT_BIT_32(15)
938/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
939#define X86_DR6_RTM RT_BIT_32(16)
940/** Value of DR6 after powerup/reset. */
941#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
942/** Bits which must be 1s in DR6. */
943#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
944/** Bits which must be 1s in DR6, when RTM is supported. */
945#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
946/** Bits which must be 0s in DR6. */
947#define X86_DR6_RAZ_MASK RT_BIT_64(12)
948/** Bits which must be 0s on writes to DR6. */
949#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
950/** @} */
951
952/** Get the DR6.Bx bit for a the given breakpoint. */
953#define X86_DR6_B(iBp) RT_BIT_64(iBp)
954
955
956/** @name DR7
957 * @{ */
958/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
959#define X86_DR7_L0 RT_BIT_32(0)
960/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
961#define X86_DR7_G0 RT_BIT_32(1)
962/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
963#define X86_DR7_L1 RT_BIT_32(2)
964/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
965#define X86_DR7_G1 RT_BIT_32(3)
966/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
967#define X86_DR7_L2 RT_BIT_32(4)
968/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
969#define X86_DR7_G2 RT_BIT_32(5)
970/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
971#define X86_DR7_L3 RT_BIT_32(6)
972/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
973#define X86_DR7_G3 RT_BIT_32(7)
974/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
975#define X86_DR7_LE RT_BIT_32(8)
976/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
977#define X86_DR7_GE RT_BIT_32(9)
978
979/** L0, L1, L2, and L3. */
980#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
981/** L0, L1, L2, and L3. */
982#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
983
984/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
985 * Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
986#define X86_DR7_RTM RT_BIT_32(11)
987/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
988 * Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
989 * May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
990 * instruction is executed.
991 * @see http://www.rcollins.org/secrets/DR7.html */
992#define X86_DR7_ICE_IR RT_BIT_32(12)
993/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
994 * any DR register is accessed. */
995#define X86_DR7_GD RT_BIT_32(13)
996/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
997 * Pentium. */
998#define X86_DR7_ICE_TR1 RT_BIT_32(14)
999/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1000#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1001/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
1002#define X86_DR7_RW0_MASK (3 << 16)
1003/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
1004#define X86_DR7_LEN0_MASK (3 << 18)
1005/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
1006#define X86_DR7_RW1_MASK (3 << 20)
1007/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
1008#define X86_DR7_LEN1_MASK (3 << 22)
1009/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
1010#define X86_DR7_RW2_MASK (3 << 24)
1011/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
1012#define X86_DR7_LEN2_MASK (3 << 26)
1013/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
1014#define X86_DR7_RW3_MASK (3 << 28)
1015/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
1016#define X86_DR7_LEN3_MASK (3 << 30)
1017
1018/** Bits which reads as 1s. */
1019#define X86_DR7_RA1_MASK RT_BIT_32(10)
1020/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1021#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1022/** Bits which must be 0s when writing to DR7. */
1023#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1024
1025/** Calcs the L bit of Nth breakpoint.
1026 * @param iBp The breakpoint number [0..3].
1027 */
1028#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1029
1030/** Calcs the G bit of Nth breakpoint.
1031 * @param iBp The breakpoint number [0..3].
1032 */
1033#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1034
1035/** Calcs the L and G bits of Nth breakpoint.
1036 * @param iBp The breakpoint number [0..3].
1037 */
1038#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1039
1040/** @name Read/Write values.
1041 * @{ */
1042/** Break on instruction fetch only. */
1043#define X86_DR7_RW_EO UINT32_C(0)
1044/** Break on write only. */
1045#define X86_DR7_RW_WO UINT32_C(1)
1046/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1047#define X86_DR7_RW_IO UINT32_C(2)
1048/** Break on read or write (but not instruction fetches). */
1049#define X86_DR7_RW_RW UINT32_C(3)
1050/** @} */
1051
1052/** Shifts a X86_DR7_RW_* value to its right place.
1053 * @param iBp The breakpoint number [0..3].
1054 * @param fRw One of the X86_DR7_RW_* value.
1055 */
1056#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1057
1058/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1059 * one of the X86_DR7_RW_XXX constants).
1060 *
1061 * @returns X86_DR7_RW_XXX
1062 * @param uDR7 DR7 value
1063 * @param iBp The breakpoint number [0..3].
1064 */
1065#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1066
1067/** R/W0, R/W1, R/W2, and R/W3. */
1068#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1069
1070#ifndef VBOX_FOR_DTRACE_LIB
1071/** Checks if there are any I/O breakpoint types configured in the RW
1072 * registers. Does NOT check if these are enabled, sorry. */
1073# define X86_DR7_ANY_RW_IO(uDR7) \
1074 ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1075 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1076AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1077AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1078AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1079AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1080AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1081AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1082AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1083AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1084AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1085#endif /* !VBOX_FOR_DTRACE_LIB */
1086
1087/** @name Length values.
1088 * @{ */
1089#define X86_DR7_LEN_BYTE UINT32_C(0)
1090#define X86_DR7_LEN_WORD UINT32_C(1)
1091#define X86_DR7_LEN_QWORD UINT32_C(2) /**< AMD64 long mode only. */
1092#define X86_DR7_LEN_DWORD UINT32_C(3)
1093/** @} */
1094
1095/** Shifts a X86_DR7_LEN_* value to its right place.
1096 * @param iBp The breakpoint number [0..3].
1097 * @param cb One of the X86_DR7_LEN_* values.
1098 */
1099#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1100
1101/** Fetch the breakpoint length bits from the DR7 value.
1102 * @param uDR7 DR7 value
1103 * @param iBp The breakpoint number [0..3].
1104 */
1105#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1106
1107/** Mask used to check if any breakpoints are enabled. */
1108#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1109
1110/** LEN0, LEN1, LEN2, and LEN3. */
1111#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1112/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1113#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1114
1115/** Value of DR7 after powerup/reset. */
1116#define X86_DR7_INIT_VAL 0x400
1117/** @} */
1118
1119
1120/** @name Machine Specific Registers
1121 * @{
1122 */
1123/** Machine check address register (P5). */
1124#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1125/** Machine check type register (P5). */
1126#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1127/** Time Stamp Counter. */
1128#define MSR_IA32_TSC 0x10
1129#define MSR_IA32_CESR UINT32_C(0x00000011)
1130#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1131#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1132
1133#define MSR_IA32_PLATFORM_ID 0x17
1134
1135#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1136# define MSR_IA32_APICBASE 0x1b
1137/** Local APIC enabled. */
1138# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1139/** X2APIC enabled (requires the EN bit to be set). */
1140# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1141/** The processor is the boot strap processor (BSP). */
1142# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1143/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1144 * width. */
1145# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1146/** The default physical base address of the APIC. */
1147# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1148/** Gets the physical base address from the MSR. */
1149# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1150#endif
1151
1152/** Undocumented intel MSR for reporting thread and core counts.
1153 * Judging from the XNU sources, it seems to be introduced in Nehalem. The
1154 * first 16 bits is the thread count. The next 16 bits the core count, except
1155 * on Westmere where it seems it's only the next 4 bits for some reason. */
1156#define MSR_CORE_THREAD_COUNT 0x35
1157
1158/** CPU Feature control. */
1159#define MSR_IA32_FEATURE_CONTROL 0x3A
1160/** Feature control - Lock MSR from writes (R/W0). */
1161#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1162/** Feature control - Enable VMX inside SMX operation (R/WL). */
1163#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1164/** Feature control - Enable VMX outside SMX operation (R/WL). */
1165#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1166/** Feature control - SENTER local functions enable (R/WL). */
1167#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1168#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1169#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1170#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1171#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1172#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1173#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1174/** Feature control - SENTER global enable (R/WL). */
1175#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1176/** Feature control - SGX launch control enable (R/WL). */
1177#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1178/** Feature control - SGX global enable (R/WL). */
1179#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1180/** Feature control - LMCE on (R/WL). */
1181#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1182
1183/** Per-processor TSC adjust MSR. */
1184#define MSR_IA32_TSC_ADJUST 0x3B
1185
1186/** Spectre control register.
1187 * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1188#define MSR_IA32_SPEC_CTRL 0x48
1189/** IBRS - Indirect branch restricted speculation. */
1190#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1191/** STIBP - Single thread indirect branch predictors. */
1192#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1193
1194/** Prediction command register.
1195 * Write only, logical processor scope, no state since write only. */
1196#define MSR_IA32_PRED_CMD 0x49
1197/** IBPB - Indirect branch prediction barrie when written as 1. */
1198#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1199
1200/** BIOS update trigger (microcode update). */
1201#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1202
1203/** BIOS update signature (microcode). */
1204#define MSR_IA32_BIOS_SIGN_ID 0x8B
1205
1206/** SMM monitor control. */
1207#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1208/** SMM control - Valid. */
1209#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1210/** SMM control - VMXOFF unblocks SMI. */
1211#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1212/** SMM control - MSEG base physical address. */
1213#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1214
1215/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1216#define MSR_IA32_SMBASE 0x9E
1217
1218/** General performance counter no. 0. */
1219#define MSR_IA32_PMC0 0xC1
1220/** General performance counter no. 1. */
1221#define MSR_IA32_PMC1 0xC2
1222/** General performance counter no. 2. */
1223#define MSR_IA32_PMC2 0xC3
1224/** General performance counter no. 3. */
1225#define MSR_IA32_PMC3 0xC4
1226
1227/** Nehalem power control. */
1228#define MSR_IA32_PLATFORM_INFO 0xCE
1229
1230/** Get FSB clock status (Intel-specific). */
1231#define MSR_IA32_FSB_CLOCK_STS 0xCD
1232
1233/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1234#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1235
1236/** C0 Maximum Frequency Clock Count */
1237#define MSR_IA32_MPERF 0xE7
1238/** C0 Actual Frequency Clock Count */
1239#define MSR_IA32_APERF 0xE8
1240
1241/** MTRR Capabilities. */
1242#define MSR_IA32_MTRR_CAP 0xFE
1243
1244/** Architecture capabilities (bugfixes).
1245 * @note May move */
1246#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1247/** CPU is no subject to spectre problems. */
1248#define MSR_IA32_ARCH_CAP_F_SPECTRE_FIX RT_BIT_32(0)
1249/** CPU has better IBRS and you can leave it on all the time. */
1250#define MSR_IA32_ARCH_CAP_F_BETTER_IBRS RT_BIT_32(1)
1251
1252/** Cache control/info. */
1253#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1254
1255#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1256/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1257 * R0 SS == CS + 8
1258 * R3 CS == CS + 16
1259 * R3 SS == CS + 24
1260 */
1261#define MSR_IA32_SYSENTER_CS 0x174
1262/** SYSENTER_ESP - the R0 ESP. */
1263#define MSR_IA32_SYSENTER_ESP 0x175
1264/** SYSENTER_EIP - the R0 EIP. */
1265#define MSR_IA32_SYSENTER_EIP 0x176
1266#endif
1267
1268/** Machine Check Global Capabilities Register. */
1269#define MSR_IA32_MCG_CAP 0x179
1270/** Machine Check Global Status Register. */
1271#define MSR_IA32_MCG_STATUS 0x17A
1272/** Machine Check Global Control Register. */
1273#define MSR_IA32_MCG_CTRL 0x17B
1274
1275/** Page Attribute Table. */
1276#define MSR_IA32_CR_PAT 0x277
1277/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1278 * "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1279#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1280
1281/** Performance counter MSRs. (Intel only) */
1282#define MSR_IA32_PERFEVTSEL0 0x186
1283#define MSR_IA32_PERFEVTSEL1 0x187
1284/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1285 * The 16th bit whether flex ratio is being used, in which case bits 15:8
1286 * holds a ratio that Apple takes for TSC granularity.
1287 *
1288 * @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1289#define MSR_FLEX_RATIO 0x194
1290/** Performance state value and starting with Intel core more.
1291 * Apple uses the >=core features to determine TSC granularity on older CPUs. */
1292#define MSR_IA32_PERF_STATUS 0x198
1293#define MSR_IA32_PERF_CTL 0x199
1294#define MSR_IA32_THERM_STATUS 0x19c
1295
1296/** Enable misc. processor features (R/W). */
1297#define MSR_IA32_MISC_ENABLE 0x1A0
1298/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1299#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1300/** Automatic Thermal Control Circuit Enable (R/W). */
1301#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1302/** Performance Monitoring Available (R). */
1303#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1304/** Branch Trace Storage Unavailable (R/O). */
1305#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1306/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1307#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1308/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1309#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1310/** If MONITOR/MWAIT is supported (R/W). */
1311#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1312/** Limit CPUID Maxval to 3 leafs (R/W). */
1313#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1314/** When set to 1, xTPR messages are disabled (R/W). */
1315#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1316/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1317#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1318
1319/** Trace/Profile Resource Control (R/W) */
1320#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1321/** Last branch record. */
1322#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1323/** Branch trace flag (single step on branches). */
1324#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1325/** Performance monitoring pin control (AMD only). */
1326#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1327#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1328#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1329#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1330/** Trace message enable (Intel only). */
1331#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1332/** Branch trace store (Intel only). */
1333#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1334/** Branch trace interrupt (Intel only). */
1335#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1336/** Branch trace off in privileged code (Intel only). */
1337#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1338/** Branch trace off in user code (Intel only). */
1339#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1340/** Freeze LBR on PMI flag (Intel only). */
1341#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1342/** Freeze PERFMON on PMI flag (Intel only). */
1343#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1344/** Freeze while SMM enabled (Intel only). */
1345#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1346/** Advanced debugging of RTM regions (Intel only). */
1347#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1348/** Debug control MSR valid bits (Intel only). */
1349#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \
1350 | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1351 | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1352 | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1353 | MSR_IA32_DEBUGCTL_RTM)
1354
1355/** The number (0..3 or 0..15) of the last branch record register on P4 and
1356 * related Xeons. */
1357#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1358/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1359 * @{ */
1360#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1361#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1362#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1363#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1364/** @} */
1365
1366
1367#define IA32_MTRR_PHYSBASE0 0x200
1368#define IA32_MTRR_PHYSMASK0 0x201
1369#define IA32_MTRR_PHYSBASE1 0x202
1370#define IA32_MTRR_PHYSMASK1 0x203
1371#define IA32_MTRR_PHYSBASE2 0x204
1372#define IA32_MTRR_PHYSMASK2 0x205
1373#define IA32_MTRR_PHYSBASE3 0x206
1374#define IA32_MTRR_PHYSMASK3 0x207
1375#define IA32_MTRR_PHYSBASE4 0x208
1376#define IA32_MTRR_PHYSMASK4 0x209
1377#define IA32_MTRR_PHYSBASE5 0x20a
1378#define IA32_MTRR_PHYSMASK5 0x20b
1379#define IA32_MTRR_PHYSBASE6 0x20c
1380#define IA32_MTRR_PHYSMASK6 0x20d
1381#define IA32_MTRR_PHYSBASE7 0x20e
1382#define IA32_MTRR_PHYSMASK7 0x20f
1383#define IA32_MTRR_PHYSBASE8 0x210
1384#define IA32_MTRR_PHYSMASK8 0x211
1385#define IA32_MTRR_PHYSBASE9 0x212
1386#define IA32_MTRR_PHYSMASK9 0x213
1387
1388/** Fixed range MTRRs.
1389 * @{ */
1390#define IA32_MTRR_FIX64K_00000 0x250
1391#define IA32_MTRR_FIX16K_80000 0x258
1392#define IA32_MTRR_FIX16K_A0000 0x259
1393#define IA32_MTRR_FIX4K_C0000 0x268
1394#define IA32_MTRR_FIX4K_C8000 0x269
1395#define IA32_MTRR_FIX4K_D0000 0x26a
1396#define IA32_MTRR_FIX4K_D8000 0x26b
1397#define IA32_MTRR_FIX4K_E0000 0x26c
1398#define IA32_MTRR_FIX4K_E8000 0x26d
1399#define IA32_MTRR_FIX4K_F0000 0x26e
1400#define IA32_MTRR_FIX4K_F8000 0x26f
1401/** @} */
1402
1403/** MTRR Default Range. */
1404#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1405
1406/** Global performance counter control facilities (Intel only). */
1407#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1408#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1409#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1410
1411/** Precise Event Based sampling (Intel only). */
1412#define MSR_IA32_PEBS_ENABLE 0x3F1
1413
1414#define MSR_IA32_MC0_CTL 0x400
1415#define MSR_IA32_MC0_STATUS 0x401
1416
1417/** Basic VMX information. */
1418#define MSR_IA32_VMX_BASIC 0x480
1419/** Allowed settings for pin-based VM execution controls. */
1420#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1421/** Allowed settings for proc-based VM execution controls. */
1422#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1423/** Allowed settings for the VM-exit controls. */
1424#define MSR_IA32_VMX_EXIT_CTLS 0x483
1425/** Allowed settings for the VM-entry controls. */
1426#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1427/** Misc VMX info. */
1428#define MSR_IA32_VMX_MISC 0x485
1429/** Fixed cleared bits in CR0. */
1430#define MSR_IA32_VMX_CR0_FIXED0 0x486
1431/** Fixed set bits in CR0. */
1432#define MSR_IA32_VMX_CR0_FIXED1 0x487
1433/** Fixed cleared bits in CR4. */
1434#define MSR_IA32_VMX_CR4_FIXED0 0x488
1435/** Fixed set bits in CR4. */
1436#define MSR_IA32_VMX_CR4_FIXED1 0x489
1437/** Information for enumerating fields in the VMCS. */
1438#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1439/** Allowed settings for secondary proc-based VM execution controls */
1440#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1441/** EPT capabilities. */
1442#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1443/** Allowed settings of all pin-based VM execution controls. */
1444#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1445/** Allowed settings of all proc-based VM execution controls. */
1446#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1447/** Allowed settings of all VMX exit controls. */
1448#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1449/** Allowed settings of all VMX entry controls. */
1450#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1451/** Allowed settings for the VM-function controls. */
1452#define MSR_IA32_VMX_VMFUNC 0x491
1453
1454/** Intel PT - Enable and control for trace packet generation. */
1455#define MSR_IA32_RTIT_CTL 0x570
1456
1457/** DS Save Area (R/W). */
1458#define MSR_IA32_DS_AREA 0x600
1459/** Running Average Power Limit (RAPL) power units. */
1460#define MSR_RAPL_POWER_UNIT 0x606
1461
1462/** X2APIC MSR range start. */
1463#define MSR_IA32_X2APIC_START 0x800
1464/** X2APIC MSR - APIC ID Register. */
1465#define MSR_IA32_X2APIC_ID 0x802
1466/** X2APIC MSR - APIC Version Register. */
1467#define MSR_IA32_X2APIC_VERSION 0x803
1468/** X2APIC MSR - Task Priority Register. */
1469#define MSR_IA32_X2APIC_TPR 0x808
1470/** X2APIC MSR - Processor Priority register. */
1471#define MSR_IA32_X2APIC_PPR 0x80A
1472/** X2APIC MSR - End Of Interrupt register. */
1473#define MSR_IA32_X2APIC_EOI 0x80B
1474/** X2APIC MSR - Logical Destination Register. */
1475#define MSR_IA32_X2APIC_LDR 0x80D
1476/** X2APIC MSR - Spurious Interrupt Vector Register. */
1477#define MSR_IA32_X2APIC_SVR 0x80F
1478/** X2APIC MSR - In-service Register (bits 31:0). */
1479#define MSR_IA32_X2APIC_ISR0 0x810
1480/** X2APIC MSR - In-service Register (bits 63:32). */
1481#define MSR_IA32_X2APIC_ISR1 0x811
1482/** X2APIC MSR - In-service Register (bits 95:64). */
1483#define MSR_IA32_X2APIC_ISR2 0x812
1484/** X2APIC MSR - In-service Register (bits 127:96). */
1485#define MSR_IA32_X2APIC_ISR3 0x813
1486/** X2APIC MSR - In-service Register (bits 159:128). */
1487#define MSR_IA32_X2APIC_ISR4 0x814
1488/** X2APIC MSR - In-service Register (bits 191:160). */
1489#define MSR_IA32_X2APIC_ISR5 0x815
1490/** X2APIC MSR - In-service Register (bits 223:192). */
1491#define MSR_IA32_X2APIC_ISR6 0x816
1492/** X2APIC MSR - In-service Register (bits 255:224). */
1493#define MSR_IA32_X2APIC_ISR7 0x817
1494/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1495#define MSR_IA32_X2APIC_TMR0 0x818
1496/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1497#define MSR_IA32_X2APIC_TMR1 0x819
1498/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1499#define MSR_IA32_X2APIC_TMR2 0x81A
1500/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1501#define MSR_IA32_X2APIC_TMR3 0x81B
1502/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1503#define MSR_IA32_X2APIC_TMR4 0x81C
1504/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1505#define MSR_IA32_X2APIC_TMR5 0x81D
1506/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1507#define MSR_IA32_X2APIC_TMR6 0x81E
1508/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1509#define MSR_IA32_X2APIC_TMR7 0x81F
1510/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1511#define MSR_IA32_X2APIC_IRR0 0x820
1512/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1513#define MSR_IA32_X2APIC_IRR1 0x821
1514/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1515#define MSR_IA32_X2APIC_IRR2 0x822
1516/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1517#define MSR_IA32_X2APIC_IRR3 0x823
1518/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1519#define MSR_IA32_X2APIC_IRR4 0x824
1520/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1521#define MSR_IA32_X2APIC_IRR5 0x825
1522/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1523#define MSR_IA32_X2APIC_IRR6 0x826
1524/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1525#define MSR_IA32_X2APIC_IRR7 0x827
1526/** X2APIC MSR - Error Status Register. */
1527#define MSR_IA32_X2APIC_ESR 0x828
1528/** X2APIC MSR - LVT CMCI Register. */
1529#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1530/** X2APIC MSR - Interrupt Command Register. */
1531#define MSR_IA32_X2APIC_ICR 0x830
1532/** X2APIC MSR - LVT Timer Register. */
1533#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1534/** X2APIC MSR - LVT Thermal Sensor Register. */
1535#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1536/** X2APIC MSR - LVT Performance Counter Register. */
1537#define MSR_IA32_X2APIC_LVT_PERF 0x834
1538/** X2APIC MSR - LVT LINT0 Register. */
1539#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1540/** X2APIC MSR - LVT LINT1 Register. */
1541#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1542/** X2APIC MSR - LVT Error Register . */
1543#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1544/** X2APIC MSR - Timer Initial Count Register. */
1545#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1546/** X2APIC MSR - Timer Current Count Register. */
1547#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1548/** X2APIC MSR - Timer Divide Configuration Register. */
1549#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1550/** X2APIC MSR - Self IPI. */
1551#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1552/** X2APIC MSR range end. */
1553#define MSR_IA32_X2APIC_END 0xBFF
1554/** X2APIC MSR - LVT start range. */
1555#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1556/** X2APIC MSR - LVT end range (inclusive). */
1557#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1558
1559/** K6 EFER - Extended Feature Enable Register. */
1560#define MSR_K6_EFER UINT32_C(0xc0000080)
1561/** @todo document EFER */
1562/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1563#define MSR_K6_EFER_SCE RT_BIT_32(0)
1564/** Bit 8 - LME - Long mode enabled. (R/W) */
1565#define MSR_K6_EFER_LME RT_BIT_32(8)
1566#define MSR_K6_EFER_BIT_LME 8 /**< Bit number of MSR_K6_EFER_LME */
1567/** Bit 10 - LMA - Long mode active. (R) */
1568#define MSR_K6_EFER_LMA RT_BIT_32(10)
1569#define MSR_K6_EFER_BIT_LMA 10 /**< Bit number of MSR_K6_EFER_LMA */
1570/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1571#define MSR_K6_EFER_NXE RT_BIT_32(11)
1572#define MSR_K6_EFER_BIT_NXE 11 /**< Bit number of MSR_K6_EFER_NXE */
1573/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1574#define MSR_K6_EFER_SVME RT_BIT_32(12)
1575/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1576#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1577/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1578#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1579/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1580#define MSR_K6_EFER_TCE RT_BIT_32(15)
1581/** K6 STAR - SYSCALL/RET targets. */
1582#define MSR_K6_STAR UINT32_C(0xc0000081)
1583/** Shift value for getting the SYSRET CS and SS value. */
1584#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1585/** Shift value for getting the SYSCALL CS and SS value. */
1586#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1587/** Selector mask for use after shifting. */
1588#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1589/** The mask which give the SYSCALL EIP. */
1590#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1591/** K6 WHCR - Write Handling Control Register. */
1592#define MSR_K6_WHCR UINT32_C(0xc0000082)
1593/** K6 UWCCR - UC/WC Cacheability Control Register. */
1594#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1595/** K6 PSOR - Processor State Observability Register. */
1596#define MSR_K6_PSOR UINT32_C(0xc0000087)
1597/** K6 PFIR - Page Flush/Invalidate Register. */
1598#define MSR_K6_PFIR UINT32_C(0xc0000088)
1599
1600/** Performance counter MSRs. (AMD only) */
1601#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1602#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1603#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1604#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1605#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1606#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1607#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1608#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1609
1610/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1611#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1612/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1613#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1614/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1615#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1616/** K8 FS.base - The 64-bit base FS register. */
1617#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1618/** K8 GS.base - The 64-bit base GS register. */
1619#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1620/** K8 KernelGSbase - Used with SWAPGS. */
1621#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1622/** K8 TSC_AUX - Used with RDTSCP. */
1623#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1624#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1625#define MSR_K8_HWCR UINT32_C(0xc0010015)
1626#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1627#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1628#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1629#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1630#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1631#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1632/** North bridge config? See BIOS & Kernel dev guides for
1633 * details. */
1634#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1635
1636/** Hypertransport interrupt pending register.
1637 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1638#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1639
1640/** SVM Control. */
1641#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1642/** Disables HDT (Hardware Debug Tool) and certain internal debug
1643 * features. */
1644#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1645/** If set, non-intercepted INIT signals are converted to \#SX
1646 * exceptions. */
1647#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1648/** Disables A20 masking. */
1649#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1650/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1651#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1652/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1653 * clear, EFER.SVME can be written normally. */
1654#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1655
1656#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1657#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1658/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1659 * host state during world switch. */
1660#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1661
1662/** @} */
1663
1664
1665/** @name Page Table / Directory / Directory Pointers / L4.
1666 * @{
1667 */
1668
1669/** Page table/directory entry as an unsigned integer. */
1670typedef uint32_t X86PGUINT;
1671/** Pointer to a page table/directory table entry as an unsigned integer. */
1672typedef X86PGUINT *PX86PGUINT;
1673/** Pointer to an const page table/directory table entry as an unsigned integer. */
1674typedef X86PGUINT const *PCX86PGUINT;
1675
1676/** Number of entries in a 32-bit PT/PD. */
1677#define X86_PG_ENTRIES 1024
1678
1679
1680/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1681typedef uint64_t X86PGPAEUINT;
1682/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1683typedef X86PGPAEUINT *PX86PGPAEUINT;
1684/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1685typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1686
1687/** Number of entries in a PAE PT/PD. */
1688#define X86_PG_PAE_ENTRIES 512
1689/** Number of entries in a PAE PDPT. */
1690#define X86_PG_PAE_PDPE_ENTRIES 4
1691
1692/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1693#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1694/** Number of entries in an AMD64 PDPT.
1695 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1696#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1697
1698/** The size of a default page. */
1699#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1700/** The page shift of a default page. */
1701#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1702/** The default page offset mask. */
1703#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1704/** The default page base mask for virtual addresses. */
1705#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1706/** The default page base mask for virtual addresses - 32bit version. */
1707#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1708
1709/** The size of a 4KB page. */
1710#define X86_PAGE_4K_SIZE _4K
1711/** The page shift of a 4KB page. */
1712#define X86_PAGE_4K_SHIFT 12
1713/** The 4KB page offset mask. */
1714#define X86_PAGE_4K_OFFSET_MASK 0xfff
1715/** The 4KB page base mask for virtual addresses. */
1716#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1717/** The 4KB page base mask for virtual addresses - 32bit version. */
1718#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1719
1720/** The size of a 2MB page. */
1721#define X86_PAGE_2M_SIZE _2M
1722/** The page shift of a 2MB page. */
1723#define X86_PAGE_2M_SHIFT 21
1724/** The 2MB page offset mask. */
1725#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1726/** The 2MB page base mask for virtual addresses. */
1727#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1728/** The 2MB page base mask for virtual addresses - 32bit version. */
1729#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1730
1731/** The size of a 4MB page. */
1732#define X86_PAGE_4M_SIZE _4M
1733/** The page shift of a 4MB page. */
1734#define X86_PAGE_4M_SHIFT 22
1735/** The 4MB page offset mask. */
1736#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1737/** The 4MB page base mask for virtual addresses. */
1738#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1739/** The 4MB page base mask for virtual addresses - 32bit version. */
1740#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1741
1742/** The size of a 1GB page. */
1743#define X86_PAGE_1G_SIZE _1G
1744/** The page shift of a 1GB page. */
1745#define X86_PAGE_1G_SHIFT 30
1746/** The 1GB page offset mask. */
1747#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
1748/** The 1GB page base mask for virtual addresses. */
1749#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
1750
1751/**
1752 * Check if the given address is canonical.
1753 */
1754#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1755
1756
1757/** @name Page Table Entry
1758 * @{
1759 */
1760/** Bit 0 - P - Present bit. */
1761#define X86_PTE_BIT_P 0
1762/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1763#define X86_PTE_BIT_RW 1
1764/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1765#define X86_PTE_BIT_US 2
1766/** Bit 3 - PWT - Page level write thru bit. */
1767#define X86_PTE_BIT_PWT 3
1768/** Bit 4 - PCD - Page level cache disable bit. */
1769#define X86_PTE_BIT_PCD 4
1770/** Bit 5 - A - Access bit. */
1771#define X86_PTE_BIT_A 5
1772/** Bit 6 - D - Dirty bit. */
1773#define X86_PTE_BIT_D 6
1774/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1775#define X86_PTE_BIT_PAT 7
1776/** Bit 8 - G - Global flag. */
1777#define X86_PTE_BIT_G 8
1778/** Bits 63 - NX - PAE/LM - No execution flag. */
1779#define X86_PTE_PAE_BIT_NX 63
1780
1781/** Bit 0 - P - Present bit mask. */
1782#define X86_PTE_P RT_BIT_32(0)
1783/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1784#define X86_PTE_RW RT_BIT_32(1)
1785/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1786#define X86_PTE_US RT_BIT_32(2)
1787/** Bit 3 - PWT - Page level write thru bit mask. */
1788#define X86_PTE_PWT RT_BIT_32(3)
1789/** Bit 4 - PCD - Page level cache disable bit mask. */
1790#define X86_PTE_PCD RT_BIT_32(4)
1791/** Bit 5 - A - Access bit mask. */
1792#define X86_PTE_A RT_BIT_32(5)
1793/** Bit 6 - D - Dirty bit mask. */
1794#define X86_PTE_D RT_BIT_32(6)
1795/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1796#define X86_PTE_PAT RT_BIT_32(7)
1797/** Bit 8 - G - Global bit mask. */
1798#define X86_PTE_G RT_BIT_32(8)
1799
1800/** Bits 9-11 - - Available for use to system software. */
1801#define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1802/** Bits 12-31 - - Physical Page number of the next level. */
1803#define X86_PTE_PG_MASK ( 0xfffff000 )
1804
1805/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1806#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1807/** Bits 63 - NX - PAE/LM - No execution flag. */
1808#define X86_PTE_PAE_NX RT_BIT_64(63)
1809/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1810#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1811/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1812#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1813/** No bits - - LM - MBZ bits when NX is active. */
1814#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1815/** Bits 63 - - LM - MBZ bits when no NX. */
1816#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1817
1818/**
1819 * Page table entry.
1820 */
1821typedef struct X86PTEBITS
1822{
1823 /** Flags whether(=1) or not the page is present. */
1824 uint32_t u1Present : 1;
1825 /** Read(=0) / Write(=1) flag. */
1826 uint32_t u1Write : 1;
1827 /** User(=1) / Supervisor (=0) flag. */
1828 uint32_t u1User : 1;
1829 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1830 uint32_t u1WriteThru : 1;
1831 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1832 uint32_t u1CacheDisable : 1;
1833 /** Accessed flag.
1834 * Indicates that the page have been read or written to. */
1835 uint32_t u1Accessed : 1;
1836 /** Dirty flag.
1837 * Indicates that the page has been written to. */
1838 uint32_t u1Dirty : 1;
1839 /** Reserved / If PAT enabled, bit 2 of the index. */
1840 uint32_t u1PAT : 1;
1841 /** Global flag. (Ignored in all but final level.) */
1842 uint32_t u1Global : 1;
1843 /** Available for use to system software. */
1844 uint32_t u3Available : 3;
1845 /** Physical Page number of the next level. */
1846 uint32_t u20PageNo : 20;
1847} X86PTEBITS;
1848#ifndef VBOX_FOR_DTRACE_LIB
1849AssertCompileSize(X86PTEBITS, 4);
1850#endif
1851/** Pointer to a page table entry. */
1852typedef X86PTEBITS *PX86PTEBITS;
1853/** Pointer to a const page table entry. */
1854typedef const X86PTEBITS *PCX86PTEBITS;
1855
1856/**
1857 * Page table entry.
1858 */
1859typedef union X86PTE
1860{
1861 /** Unsigned integer view */
1862 X86PGUINT u;
1863 /** Bit field view. */
1864 X86PTEBITS n;
1865 /** 32-bit view. */
1866 uint32_t au32[1];
1867 /** 16-bit view. */
1868 uint16_t au16[2];
1869 /** 8-bit view. */
1870 uint8_t au8[4];
1871} X86PTE;
1872#ifndef VBOX_FOR_DTRACE_LIB
1873AssertCompileSize(X86PTE, 4);
1874#endif
1875/** Pointer to a page table entry. */
1876typedef X86PTE *PX86PTE;
1877/** Pointer to a const page table entry. */
1878typedef const X86PTE *PCX86PTE;
1879
1880
1881/**
1882 * PAE page table entry.
1883 */
1884typedef struct X86PTEPAEBITS
1885{
1886 /** Flags whether(=1) or not the page is present. */
1887 uint32_t u1Present : 1;
1888 /** Read(=0) / Write(=1) flag. */
1889 uint32_t u1Write : 1;
1890 /** User(=1) / Supervisor(=0) flag. */
1891 uint32_t u1User : 1;
1892 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1893 uint32_t u1WriteThru : 1;
1894 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1895 uint32_t u1CacheDisable : 1;
1896 /** Accessed flag.
1897 * Indicates that the page have been read or written to. */
1898 uint32_t u1Accessed : 1;
1899 /** Dirty flag.
1900 * Indicates that the page has been written to. */
1901 uint32_t u1Dirty : 1;
1902 /** Reserved / If PAT enabled, bit 2 of the index. */
1903 uint32_t u1PAT : 1;
1904 /** Global flag. (Ignored in all but final level.) */
1905 uint32_t u1Global : 1;
1906 /** Available for use to system software. */
1907 uint32_t u3Available : 3;
1908 /** Physical Page number of the next level - Low Part. Don't use this. */
1909 uint32_t u20PageNoLow : 20;
1910 /** Physical Page number of the next level - High Part. Don't use this. */
1911 uint32_t u20PageNoHigh : 20;
1912 /** MBZ bits */
1913 uint32_t u11Reserved : 11;
1914 /** No Execute flag. */
1915 uint32_t u1NoExecute : 1;
1916} X86PTEPAEBITS;
1917#ifndef VBOX_FOR_DTRACE_LIB
1918AssertCompileSize(X86PTEPAEBITS, 8);
1919#endif
1920/** Pointer to a page table entry. */
1921typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1922/** Pointer to a page table entry. */
1923typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1924
1925/**
1926 * PAE Page table entry.
1927 */
1928typedef union X86PTEPAE
1929{
1930 /** Unsigned integer view */
1931 X86PGPAEUINT u;
1932 /** Bit field view. */
1933 X86PTEPAEBITS n;
1934 /** 32-bit view. */
1935 uint32_t au32[2];
1936 /** 16-bit view. */
1937 uint16_t au16[4];
1938 /** 8-bit view. */
1939 uint8_t au8[8];
1940} X86PTEPAE;
1941#ifndef VBOX_FOR_DTRACE_LIB
1942AssertCompileSize(X86PTEPAE, 8);
1943#endif
1944/** Pointer to a PAE page table entry. */
1945typedef X86PTEPAE *PX86PTEPAE;
1946/** Pointer to a const PAE page table entry. */
1947typedef const X86PTEPAE *PCX86PTEPAE;
1948/** @} */
1949
1950/**
1951 * Page table.
1952 */
1953typedef struct X86PT
1954{
1955 /** PTE Array. */
1956 X86PTE a[X86_PG_ENTRIES];
1957} X86PT;
1958#ifndef VBOX_FOR_DTRACE_LIB
1959AssertCompileSize(X86PT, 4096);
1960#endif
1961/** Pointer to a page table. */
1962typedef X86PT *PX86PT;
1963/** Pointer to a const page table. */
1964typedef const X86PT *PCX86PT;
1965
1966/** The page shift to get the PT index. */
1967#define X86_PT_SHIFT 12
1968/** The PT index mask (apply to a shifted page address). */
1969#define X86_PT_MASK 0x3ff
1970
1971
1972/**
1973 * Page directory.
1974 */
1975typedef struct X86PTPAE
1976{
1977 /** PTE Array. */
1978 X86PTEPAE a[X86_PG_PAE_ENTRIES];
1979} X86PTPAE;
1980#ifndef VBOX_FOR_DTRACE_LIB
1981AssertCompileSize(X86PTPAE, 4096);
1982#endif
1983/** Pointer to a page table. */
1984typedef X86PTPAE *PX86PTPAE;
1985/** Pointer to a const page table. */
1986typedef const X86PTPAE *PCX86PTPAE;
1987
1988/** The page shift to get the PA PTE index. */
1989#define X86_PT_PAE_SHIFT 12
1990/** The PAE PT index mask (apply to a shifted page address). */
1991#define X86_PT_PAE_MASK 0x1ff
1992
1993
1994/** @name 4KB Page Directory Entry
1995 * @{
1996 */
1997/** Bit 0 - P - Present bit. */
1998#define X86_PDE_P RT_BIT_32(0)
1999/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2000#define X86_PDE_RW RT_BIT_32(1)
2001/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2002#define X86_PDE_US RT_BIT_32(2)
2003/** Bit 3 - PWT - Page level write thru bit. */
2004#define X86_PDE_PWT RT_BIT_32(3)
2005/** Bit 4 - PCD - Page level cache disable bit. */
2006#define X86_PDE_PCD RT_BIT_32(4)
2007/** Bit 5 - A - Access bit. */
2008#define X86_PDE_A RT_BIT_32(5)
2009/** Bit 7 - PS - Page size attribute.
2010 * Clear mean 4KB pages, set means large pages (2/4MB). */
2011#define X86_PDE_PS RT_BIT_32(7)
2012/** Bits 9-11 - - Available for use to system software. */
2013#define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2014/** Bits 12-31 - - Physical Page number of the next level. */
2015#define X86_PDE_PG_MASK ( 0xfffff000 )
2016
2017/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2018#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2019/** Bits 63 - NX - PAE/LM - No execution flag. */
2020#define X86_PDE_PAE_NX RT_BIT_64(63)
2021/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2022#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2023/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2024#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2025/** Bit 7 - - LM - MBZ bits when NX is active. */
2026#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2027/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2028#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2029
2030/**
2031 * Page directory entry.
2032 */
2033typedef struct X86PDEBITS
2034{
2035 /** Flags whether(=1) or not the page is present. */
2036 uint32_t u1Present : 1;
2037 /** Read(=0) / Write(=1) flag. */
2038 uint32_t u1Write : 1;
2039 /** User(=1) / Supervisor (=0) flag. */
2040 uint32_t u1User : 1;
2041 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2042 uint32_t u1WriteThru : 1;
2043 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2044 uint32_t u1CacheDisable : 1;
2045 /** Accessed flag.
2046 * Indicates that the page has been read or written to. */
2047 uint32_t u1Accessed : 1;
2048 /** Reserved / Ignored (dirty bit). */
2049 uint32_t u1Reserved0 : 1;
2050 /** Size bit if PSE is enabled - in any event it's 0. */
2051 uint32_t u1Size : 1;
2052 /** Reserved / Ignored (global bit). */
2053 uint32_t u1Reserved1 : 1;
2054 /** Available for use to system software. */
2055 uint32_t u3Available : 3;
2056 /** Physical Page number of the next level. */
2057 uint32_t u20PageNo : 20;
2058} X86PDEBITS;
2059#ifndef VBOX_FOR_DTRACE_LIB
2060AssertCompileSize(X86PDEBITS, 4);
2061#endif
2062/** Pointer to a page directory entry. */
2063typedef X86PDEBITS *PX86PDEBITS;
2064/** Pointer to a const page directory entry. */
2065typedef const X86PDEBITS *PCX86PDEBITS;
2066
2067
2068/**
2069 * PAE page directory entry.
2070 */
2071typedef struct X86PDEPAEBITS
2072{
2073 /** Flags whether(=1) or not the page is present. */
2074 uint32_t u1Present : 1;
2075 /** Read(=0) / Write(=1) flag. */
2076 uint32_t u1Write : 1;
2077 /** User(=1) / Supervisor (=0) flag. */
2078 uint32_t u1User : 1;
2079 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2080 uint32_t u1WriteThru : 1;
2081 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2082 uint32_t u1CacheDisable : 1;
2083 /** Accessed flag.
2084 * Indicates that the page has been read or written to. */
2085 uint32_t u1Accessed : 1;
2086 /** Reserved / Ignored (dirty bit). */
2087 uint32_t u1Reserved0 : 1;
2088 /** Size bit if PSE is enabled - in any event it's 0. */
2089 uint32_t u1Size : 1;
2090 /** Reserved / Ignored (global bit). / */
2091 uint32_t u1Reserved1 : 1;
2092 /** Available for use to system software. */
2093 uint32_t u3Available : 3;
2094 /** Physical Page number of the next level - Low Part. Don't use! */
2095 uint32_t u20PageNoLow : 20;
2096 /** Physical Page number of the next level - High Part. Don't use! */
2097 uint32_t u20PageNoHigh : 20;
2098 /** MBZ bits */
2099 uint32_t u11Reserved : 11;
2100 /** No Execute flag. */
2101 uint32_t u1NoExecute : 1;
2102} X86PDEPAEBITS;
2103#ifndef VBOX_FOR_DTRACE_LIB
2104AssertCompileSize(X86PDEPAEBITS, 8);
2105#endif
2106/** Pointer to a page directory entry. */
2107typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2108/** Pointer to a const page directory entry. */
2109typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2110
2111/** @} */
2112
2113
2114/** @name 2/4MB Page Directory Entry
2115 * @{
2116 */
2117/** Bit 0 - P - Present bit. */
2118#define X86_PDE4M_P RT_BIT_32(0)
2119/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2120#define X86_PDE4M_RW RT_BIT_32(1)
2121/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2122#define X86_PDE4M_US RT_BIT_32(2)
2123/** Bit 3 - PWT - Page level write thru bit. */
2124#define X86_PDE4M_PWT RT_BIT_32(3)
2125/** Bit 4 - PCD - Page level cache disable bit. */
2126#define X86_PDE4M_PCD RT_BIT_32(4)
2127/** Bit 5 - A - Access bit. */
2128#define X86_PDE4M_A RT_BIT_32(5)
2129/** Bit 6 - D - Dirty bit. */
2130#define X86_PDE4M_D RT_BIT_32(6)
2131/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2132#define X86_PDE4M_PS RT_BIT_32(7)
2133/** Bit 8 - G - Global flag. */
2134#define X86_PDE4M_G RT_BIT_32(8)
2135/** Bits 9-11 - AVL - Available for use to system software. */
2136#define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2137/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2138#define X86_PDE4M_PAT RT_BIT_32(12)
2139/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2140#define X86_PDE4M_PAT_SHIFT (12 - 7)
2141/** Bits 22-31 - - Physical Page number. */
2142#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2143/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2144#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2145/** The number of bits to the high part of the page number. */
2146#define X86_PDE4M_PG_HIGH_SHIFT 19
2147/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2148#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2149
2150/** Bits 21-51 - - PAE/LM - Physical Page number.
2151 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2152#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2153/** Bits 63 - NX - PAE/LM - No execution flag. */
2154#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2155/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2156#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2157/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2158#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2159/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2160#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2161/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2162#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2163
2164/**
2165 * 4MB page directory entry.
2166 */
2167typedef struct X86PDE4MBITS
2168{
2169 /** Flags whether(=1) or not the page is present. */
2170 uint32_t u1Present : 1;
2171 /** Read(=0) / Write(=1) flag. */
2172 uint32_t u1Write : 1;
2173 /** User(=1) / Supervisor (=0) flag. */
2174 uint32_t u1User : 1;
2175 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2176 uint32_t u1WriteThru : 1;
2177 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2178 uint32_t u1CacheDisable : 1;
2179 /** Accessed flag.
2180 * Indicates that the page have been read or written to. */
2181 uint32_t u1Accessed : 1;
2182 /** Dirty flag.
2183 * Indicates that the page has been written to. */
2184 uint32_t u1Dirty : 1;
2185 /** Page size flag - always 1 for 4MB entries. */
2186 uint32_t u1Size : 1;
2187 /** Global flag. */
2188 uint32_t u1Global : 1;
2189 /** Available for use to system software. */
2190 uint32_t u3Available : 3;
2191 /** Reserved / If PAT enabled, bit 2 of the index. */
2192 uint32_t u1PAT : 1;
2193 /** Bits 32-39 of the page number on AMD64.
2194 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2195 uint32_t u8PageNoHigh : 8;
2196 /** Reserved. */
2197 uint32_t u1Reserved : 1;
2198 /** Physical Page number of the page. */
2199 uint32_t u10PageNo : 10;
2200} X86PDE4MBITS;
2201#ifndef VBOX_FOR_DTRACE_LIB
2202AssertCompileSize(X86PDE4MBITS, 4);
2203#endif
2204/** Pointer to a page table entry. */
2205typedef X86PDE4MBITS *PX86PDE4MBITS;
2206/** Pointer to a const page table entry. */
2207typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2208
2209
2210/**
2211 * 2MB PAE page directory entry.
2212 */
2213typedef struct X86PDE2MPAEBITS
2214{
2215 /** Flags whether(=1) or not the page is present. */
2216 uint32_t u1Present : 1;
2217 /** Read(=0) / Write(=1) flag. */
2218 uint32_t u1Write : 1;
2219 /** User(=1) / Supervisor(=0) flag. */
2220 uint32_t u1User : 1;
2221 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2222 uint32_t u1WriteThru : 1;
2223 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2224 uint32_t u1CacheDisable : 1;
2225 /** Accessed flag.
2226 * Indicates that the page have been read or written to. */
2227 uint32_t u1Accessed : 1;
2228 /** Dirty flag.
2229 * Indicates that the page has been written to. */
2230 uint32_t u1Dirty : 1;
2231 /** Page size flag - always 1 for 2MB entries. */
2232 uint32_t u1Size : 1;
2233 /** Global flag. */
2234 uint32_t u1Global : 1;
2235 /** Available for use to system software. */
2236 uint32_t u3Available : 3;
2237 /** Reserved / If PAT enabled, bit 2 of the index. */
2238 uint32_t u1PAT : 1;
2239 /** Reserved. */
2240 uint32_t u9Reserved : 9;
2241 /** Physical Page number of the next level - Low part. Don't use! */
2242 uint32_t u10PageNoLow : 10;
2243 /** Physical Page number of the next level - High part. Don't use! */
2244 uint32_t u20PageNoHigh : 20;
2245 /** MBZ bits */
2246 uint32_t u11Reserved : 11;
2247 /** No Execute flag. */
2248 uint32_t u1NoExecute : 1;
2249} X86PDE2MPAEBITS;
2250#ifndef VBOX_FOR_DTRACE_LIB
2251AssertCompileSize(X86PDE2MPAEBITS, 8);
2252#endif
2253/** Pointer to a 2MB PAE page table entry. */
2254typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2255/** Pointer to a 2MB PAE page table entry. */
2256typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2257
2258/** @} */
2259
2260/**
2261 * Page directory entry.
2262 */
2263typedef union X86PDE
2264{
2265 /** Unsigned integer view. */
2266 X86PGUINT u;
2267 /** Normal view. */
2268 X86PDEBITS n;
2269 /** 4MB view (big). */
2270 X86PDE4MBITS b;
2271 /** 8 bit unsigned integer view. */
2272 uint8_t au8[4];
2273 /** 16 bit unsigned integer view. */
2274 uint16_t au16[2];
2275 /** 32 bit unsigned integer view. */
2276 uint32_t au32[1];
2277} X86PDE;
2278#ifndef VBOX_FOR_DTRACE_LIB
2279AssertCompileSize(X86PDE, 4);
2280#endif
2281/** Pointer to a page directory entry. */
2282typedef X86PDE *PX86PDE;
2283/** Pointer to a const page directory entry. */
2284typedef const X86PDE *PCX86PDE;
2285
2286/**
2287 * PAE page directory entry.
2288 */
2289typedef union X86PDEPAE
2290{
2291 /** Unsigned integer view. */
2292 X86PGPAEUINT u;
2293 /** Normal view. */
2294 X86PDEPAEBITS n;
2295 /** 2MB page view (big). */
2296 X86PDE2MPAEBITS b;
2297 /** 8 bit unsigned integer view. */
2298 uint8_t au8[8];
2299 /** 16 bit unsigned integer view. */
2300 uint16_t au16[4];
2301 /** 32 bit unsigned integer view. */
2302 uint32_t au32[2];
2303} X86PDEPAE;
2304#ifndef VBOX_FOR_DTRACE_LIB
2305AssertCompileSize(X86PDEPAE, 8);
2306#endif
2307/** Pointer to a page directory entry. */
2308typedef X86PDEPAE *PX86PDEPAE;
2309/** Pointer to a const page directory entry. */
2310typedef const X86PDEPAE *PCX86PDEPAE;
2311
2312/**
2313 * Page directory.
2314 */
2315typedef struct X86PD
2316{
2317 /** PDE Array. */
2318 X86PDE a[X86_PG_ENTRIES];
2319} X86PD;
2320#ifndef VBOX_FOR_DTRACE_LIB
2321AssertCompileSize(X86PD, 4096);
2322#endif
2323/** Pointer to a page directory. */
2324typedef X86PD *PX86PD;
2325/** Pointer to a const page directory. */
2326typedef const X86PD *PCX86PD;
2327
2328/** The page shift to get the PD index. */
2329#define X86_PD_SHIFT 22
2330/** The PD index mask (apply to a shifted page address). */
2331#define X86_PD_MASK 0x3ff
2332
2333
2334/**
2335 * PAE page directory.
2336 */
2337typedef struct X86PDPAE
2338{
2339 /** PDE Array. */
2340 X86PDEPAE a[X86_PG_PAE_ENTRIES];
2341} X86PDPAE;
2342#ifndef VBOX_FOR_DTRACE_LIB
2343AssertCompileSize(X86PDPAE, 4096);
2344#endif
2345/** Pointer to a PAE page directory. */
2346typedef X86PDPAE *PX86PDPAE;
2347/** Pointer to a const PAE page directory. */
2348typedef const X86PDPAE *PCX86PDPAE;
2349
2350/** The page shift to get the PAE PD index. */
2351#define X86_PD_PAE_SHIFT 21
2352/** The PAE PD index mask (apply to a shifted page address). */
2353#define X86_PD_PAE_MASK 0x1ff
2354
2355
2356/** @name Page Directory Pointer Table Entry (PAE)
2357 * @{
2358 */
2359/** Bit 0 - P - Present bit. */
2360#define X86_PDPE_P RT_BIT_32(0)
2361/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2362#define X86_PDPE_RW RT_BIT_32(1)
2363/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2364#define X86_PDPE_US RT_BIT_32(2)
2365/** Bit 3 - PWT - Page level write thru bit. */
2366#define X86_PDPE_PWT RT_BIT_32(3)
2367/** Bit 4 - PCD - Page level cache disable bit. */
2368#define X86_PDPE_PCD RT_BIT_32(4)
2369/** Bit 5 - A - Access bit. Long Mode only. */
2370#define X86_PDPE_A RT_BIT_32(5)
2371/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2372#define X86_PDPE_LM_PS RT_BIT_32(7)
2373/** Bits 9-11 - - Available for use to system software. */
2374#define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2375/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2376#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2377/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2378#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2379/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2380#define X86_PDPE_LM_NX RT_BIT_64(63)
2381/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2382#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2383/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2384#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2385/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2386#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2387/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2388#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2389
2390
2391/**
2392 * Page directory pointer table entry.
2393 */
2394typedef struct X86PDPEBITS
2395{
2396 /** Flags whether(=1) or not the page is present. */
2397 uint32_t u1Present : 1;
2398 /** Chunk of reserved bits. */
2399 uint32_t u2Reserved : 2;
2400 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2401 uint32_t u1WriteThru : 1;
2402 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2403 uint32_t u1CacheDisable : 1;
2404 /** Chunk of reserved bits. */
2405 uint32_t u4Reserved : 4;
2406 /** Available for use to system software. */
2407 uint32_t u3Available : 3;
2408 /** Physical Page number of the next level - Low Part. Don't use! */
2409 uint32_t u20PageNoLow : 20;
2410 /** Physical Page number of the next level - High Part. Don't use! */
2411 uint32_t u20PageNoHigh : 20;
2412 /** MBZ bits */
2413 uint32_t u12Reserved : 12;
2414} X86PDPEBITS;
2415#ifndef VBOX_FOR_DTRACE_LIB
2416AssertCompileSize(X86PDPEBITS, 8);
2417#endif
2418/** Pointer to a page directory pointer table entry. */
2419typedef X86PDPEBITS *PX86PTPEBITS;
2420/** Pointer to a const page directory pointer table entry. */
2421typedef const X86PDPEBITS *PCX86PTPEBITS;
2422
2423/**
2424 * Page directory pointer table entry. AMD64 version
2425 */
2426typedef struct X86PDPEAMD64BITS
2427{
2428 /** Flags whether(=1) or not the page is present. */
2429 uint32_t u1Present : 1;
2430 /** Read(=0) / Write(=1) flag. */
2431 uint32_t u1Write : 1;
2432 /** User(=1) / Supervisor (=0) flag. */
2433 uint32_t u1User : 1;
2434 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2435 uint32_t u1WriteThru : 1;
2436 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2437 uint32_t u1CacheDisable : 1;
2438 /** Accessed flag.
2439 * Indicates that the page have been read or written to. */
2440 uint32_t u1Accessed : 1;
2441 /** Chunk of reserved bits. */
2442 uint32_t u3Reserved : 3;
2443 /** Available for use to system software. */
2444 uint32_t u3Available : 3;
2445 /** Physical Page number of the next level - Low Part. Don't use! */
2446 uint32_t u20PageNoLow : 20;
2447 /** Physical Page number of the next level - High Part. Don't use! */
2448 uint32_t u20PageNoHigh : 20;
2449 /** MBZ bits */
2450 uint32_t u11Reserved : 11;
2451 /** No Execute flag. */
2452 uint32_t u1NoExecute : 1;
2453} X86PDPEAMD64BITS;
2454#ifndef VBOX_FOR_DTRACE_LIB
2455AssertCompileSize(X86PDPEAMD64BITS, 8);
2456#endif
2457/** Pointer to a page directory pointer table entry. */
2458typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2459/** Pointer to a const page directory pointer table entry. */
2460typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2461
2462/**
2463 * Page directory pointer table entry for 1GB page. (AMD64 only)
2464 */
2465typedef struct X86PDPE1GB
2466{
2467 /** 0: Flags whether(=1) or not the page is present. */
2468 uint32_t u1Present : 1;
2469 /** 1: Read(=0) / Write(=1) flag. */
2470 uint32_t u1Write : 1;
2471 /** 2: User(=1) / Supervisor (=0) flag. */
2472 uint32_t u1User : 1;
2473 /** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2474 uint32_t u1WriteThru : 1;
2475 /** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2476 uint32_t u1CacheDisable : 1;
2477 /** 5: Accessed flag.
2478 * Indicates that the page have been read or written to. */
2479 uint32_t u1Accessed : 1;
2480 /** 6: Dirty flag for 1GB pages. */
2481 uint32_t u1Dirty : 1;
2482 /** 7: Indicates 1GB page if set. */
2483 uint32_t u1Size : 1;
2484 /** 8: Global 1GB page. */
2485 uint32_t u1Global: 1;
2486 /** 9-11: Available for use to system software. */
2487 uint32_t u3Available : 3;
2488 /** 12: PAT bit for 1GB page. */
2489 uint32_t u1PAT : 1;
2490 /** 13-29: MBZ bits. */
2491 uint32_t u17Reserved : 17;
2492 /** 30-31: Physical page number - Low Part. Don't use! */
2493 uint32_t u2PageNoLow : 2;
2494 /** 32-51: Physical Page number of the next level - High Part. Don't use! */
2495 uint32_t u20PageNoHigh : 20;
2496 /** 52-62: MBZ bits */
2497 uint32_t u11Reserved : 11;
2498 /** 63: No Execute flag. */
2499 uint32_t u1NoExecute : 1;
2500} X86PDPE1GB;
2501#ifndef VBOX_FOR_DTRACE_LIB
2502AssertCompileSize(X86PDPE1GB, 8);
2503#endif
2504/** Pointer to a page directory pointer table entry for a 1GB page. */
2505typedef X86PDPE1GB *PX86PDPE1GB;
2506/** Pointer to a const page directory pointer table entry for a 1GB page. */
2507typedef const X86PDPE1GB *PCX86PDPE1GB;
2508
2509/**
2510 * Page directory pointer table entry.
2511 */
2512typedef union X86PDPE
2513{
2514 /** Unsigned integer view. */
2515 X86PGPAEUINT u;
2516 /** Normal view. */
2517 X86PDPEBITS n;
2518 /** AMD64 view. */
2519 X86PDPEAMD64BITS lm;
2520 /** AMD64 big view. */
2521 X86PDPE1GB b;
2522 /** 8 bit unsigned integer view. */
2523 uint8_t au8[8];
2524 /** 16 bit unsigned integer view. */
2525 uint16_t au16[4];
2526 /** 32 bit unsigned integer view. */
2527 uint32_t au32[2];
2528} X86PDPE;
2529#ifndef VBOX_FOR_DTRACE_LIB
2530AssertCompileSize(X86PDPE, 8);
2531#endif
2532/** Pointer to a page directory pointer table entry. */
2533typedef X86PDPE *PX86PDPE;
2534/** Pointer to a const page directory pointer table entry. */
2535typedef const X86PDPE *PCX86PDPE;
2536
2537
2538/**
2539 * Page directory pointer table.
2540 */
2541typedef struct X86PDPT
2542{
2543 /** PDE Array. */
2544 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2545} X86PDPT;
2546#ifndef VBOX_FOR_DTRACE_LIB
2547AssertCompileSize(X86PDPT, 4096);
2548#endif
2549/** Pointer to a page directory pointer table. */
2550typedef X86PDPT *PX86PDPT;
2551/** Pointer to a const page directory pointer table. */
2552typedef const X86PDPT *PCX86PDPT;
2553
2554/** The page shift to get the PDPT index. */
2555#define X86_PDPT_SHIFT 30
2556/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2557#define X86_PDPT_MASK_PAE 0x3
2558/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2559#define X86_PDPT_MASK_AMD64 0x1ff
2560
2561/** @} */
2562
2563
2564/** @name Page Map Level-4 Entry (Long Mode PAE)
2565 * @{
2566 */
2567/** Bit 0 - P - Present bit. */
2568#define X86_PML4E_P RT_BIT_32(0)
2569/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2570#define X86_PML4E_RW RT_BIT_32(1)
2571/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2572#define X86_PML4E_US RT_BIT_32(2)
2573/** Bit 3 - PWT - Page level write thru bit. */
2574#define X86_PML4E_PWT RT_BIT_32(3)
2575/** Bit 4 - PCD - Page level cache disable bit. */
2576#define X86_PML4E_PCD RT_BIT_32(4)
2577/** Bit 5 - A - Access bit. */
2578#define X86_PML4E_A RT_BIT_32(5)
2579/** Bits 9-11 - - Available for use to system software. */
2580#define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2581/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2582#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2583/** Bits 8, 7 - - MBZ bits when NX is active. */
2584#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2585/** Bits 63, 7 - - MBZ bits when no NX. */
2586#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2587/** Bits 63 - NX - PAE - No execution flag. */
2588#define X86_PML4E_NX RT_BIT_64(63)
2589
2590/**
2591 * Page Map Level-4 Entry
2592 */
2593typedef struct X86PML4EBITS
2594{
2595 /** Flags whether(=1) or not the page is present. */
2596 uint32_t u1Present : 1;
2597 /** Read(=0) / Write(=1) flag. */
2598 uint32_t u1Write : 1;
2599 /** User(=1) / Supervisor (=0) flag. */
2600 uint32_t u1User : 1;
2601 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2602 uint32_t u1WriteThru : 1;
2603 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2604 uint32_t u1CacheDisable : 1;
2605 /** Accessed flag.
2606 * Indicates that the page have been read or written to. */
2607 uint32_t u1Accessed : 1;
2608 /** Chunk of reserved bits. */
2609 uint32_t u3Reserved : 3;
2610 /** Available for use to system software. */
2611 uint32_t u3Available : 3;
2612 /** Physical Page number of the next level - Low Part. Don't use! */
2613 uint32_t u20PageNoLow : 20;
2614 /** Physical Page number of the next level - High Part. Don't use! */
2615 uint32_t u20PageNoHigh : 20;
2616 /** MBZ bits */
2617 uint32_t u11Reserved : 11;
2618 /** No Execute flag. */
2619 uint32_t u1NoExecute : 1;
2620} X86PML4EBITS;
2621#ifndef VBOX_FOR_DTRACE_LIB
2622AssertCompileSize(X86PML4EBITS, 8);
2623#endif
2624/** Pointer to a page map level-4 entry. */
2625typedef X86PML4EBITS *PX86PML4EBITS;
2626/** Pointer to a const page map level-4 entry. */
2627typedef const X86PML4EBITS *PCX86PML4EBITS;
2628
2629/**
2630 * Page Map Level-4 Entry.
2631 */
2632typedef union X86PML4E
2633{
2634 /** Unsigned integer view. */
2635 X86PGPAEUINT u;
2636 /** Normal view. */
2637 X86PML4EBITS n;
2638 /** 8 bit unsigned integer view. */
2639 uint8_t au8[8];
2640 /** 16 bit unsigned integer view. */
2641 uint16_t au16[4];
2642 /** 32 bit unsigned integer view. */
2643 uint32_t au32[2];
2644} X86PML4E;
2645#ifndef VBOX_FOR_DTRACE_LIB
2646AssertCompileSize(X86PML4E, 8);
2647#endif
2648/** Pointer to a page map level-4 entry. */
2649typedef X86PML4E *PX86PML4E;
2650/** Pointer to a const page map level-4 entry. */
2651typedef const X86PML4E *PCX86PML4E;
2652
2653
2654/**
2655 * Page Map Level-4.
2656 */
2657typedef struct X86PML4
2658{
2659 /** PDE Array. */
2660 X86PML4E a[X86_PG_PAE_ENTRIES];
2661} X86PML4;
2662#ifndef VBOX_FOR_DTRACE_LIB
2663AssertCompileSize(X86PML4, 4096);
2664#endif
2665/** Pointer to a page map level-4. */
2666typedef X86PML4 *PX86PML4;
2667/** Pointer to a const page map level-4. */
2668typedef const X86PML4 *PCX86PML4;
2669
2670/** The page shift to get the PML4 index. */
2671#define X86_PML4_SHIFT 39
2672/** The PML4 index mask (apply to a shifted page address). */
2673#define X86_PML4_MASK 0x1ff
2674
2675/** @} */
2676
2677/** @} */
2678
2679/**
2680 * Intel PCID invalidation types.
2681 */
2682/** Individual address invalidation. */
2683#define X86_INVPCID_TYPE_INDV_ADDR 0
2684/** Single-context invalidation. */
2685#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2686/** All-context including globals invalidation. */
2687#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2688/** All-context excluding globals invalidation. */
2689#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2690/** The maximum valid invalidation type value. */
2691#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2692
2693/**
2694 * 32-bit protected mode FSTENV image.
2695 */
2696typedef struct X86FSTENV32P
2697{
2698 uint16_t FCW;
2699 uint16_t padding1;
2700 uint16_t FSW;
2701 uint16_t padding2;
2702 uint16_t FTW;
2703 uint16_t padding3;
2704 uint32_t FPUIP;
2705 uint16_t FPUCS;
2706 uint16_t FOP;
2707 uint32_t FPUDP;
2708 uint16_t FPUDS;
2709 uint16_t padding4;
2710} X86FSTENV32P;
2711/** Pointer to a 32-bit protected mode FSTENV image. */
2712typedef X86FSTENV32P *PX86FSTENV32P;
2713/** Pointer to a const 32-bit protected mode FSTENV image. */
2714typedef X86FSTENV32P const *PCX86FSTENV32P;
2715
2716
2717/**
2718 * 80-bit MMX/FPU register type.
2719 */
2720typedef struct X86FPUMMX
2721{
2722 uint8_t reg[10];
2723} X86FPUMMX;
2724#ifndef VBOX_FOR_DTRACE_LIB
2725AssertCompileSize(X86FPUMMX, 10);
2726#endif
2727/** Pointer to a 80-bit MMX/FPU register type. */
2728typedef X86FPUMMX *PX86FPUMMX;
2729/** Pointer to a const 80-bit MMX/FPU register type. */
2730typedef const X86FPUMMX *PCX86FPUMMX;
2731
2732/** FPU (x87) register. */
2733typedef union X86FPUREG
2734{
2735 /** MMX view. */
2736 uint64_t mmx;
2737 /** FPU view - todo. */
2738 X86FPUMMX fpu;
2739 /** Extended precision floating point view. */
2740 RTFLOAT80U r80;
2741 /** Extended precision floating point view v2 */
2742 RTFLOAT80U2 r80Ex;
2743 /** 8-bit view. */
2744 uint8_t au8[16];
2745 /** 16-bit view. */
2746 uint16_t au16[8];
2747 /** 32-bit view. */
2748 uint32_t au32[4];
2749 /** 64-bit view. */
2750 uint64_t au64[2];
2751 /** 128-bit view. (yeah, very helpful) */
2752 uint128_t au128[1];
2753} X86FPUREG;
2754#ifndef VBOX_FOR_DTRACE_LIB
2755AssertCompileSize(X86FPUREG, 16);
2756#endif
2757/** Pointer to a FPU register. */
2758typedef X86FPUREG *PX86FPUREG;
2759/** Pointer to a const FPU register. */
2760typedef X86FPUREG const *PCX86FPUREG;
2761
2762/**
2763 * XMM register union.
2764 */
2765typedef union X86XMMREG
2766{
2767 /** XMM Register view. */
2768 uint128_t xmm;
2769 /** 8-bit view. */
2770 uint8_t au8[16];
2771 /** 16-bit view. */
2772 uint16_t au16[8];
2773 /** 32-bit view. */
2774 uint32_t au32[4];
2775 /** 64-bit view. */
2776 uint64_t au64[2];
2777 /** 128-bit view. (yeah, very helpful) */
2778 uint128_t au128[1];
2779#ifndef VBOX_FOR_DTRACE_LIB
2780 /** Confusing nested 128-bit union view (this is what xmm should've been). */
2781 RTUINT128U uXmm;
2782#endif
2783} X86XMMREG;
2784#ifndef VBOX_FOR_DTRACE_LIB
2785AssertCompileSize(X86XMMREG, 16);
2786#endif
2787/** Pointer to an XMM register state. */
2788typedef X86XMMREG *PX86XMMREG;
2789/** Pointer to a const XMM register state. */
2790typedef X86XMMREG const *PCX86XMMREG;
2791
2792/**
2793 * YMM register union.
2794 */
2795typedef union X86YMMREG
2796{
2797 /** 8-bit view. */
2798 uint8_t au8[32];
2799 /** 16-bit view. */
2800 uint16_t au16[16];
2801 /** 32-bit view. */
2802 uint32_t au32[8];
2803 /** 64-bit view. */
2804 uint64_t au64[4];
2805 /** 128-bit view. (yeah, very helpful) */
2806 uint128_t au128[2];
2807 /** XMM sub register view. */
2808 X86XMMREG aXmm[2];
2809} X86YMMREG;
2810#ifndef VBOX_FOR_DTRACE_LIB
2811AssertCompileSize(X86YMMREG, 32);
2812#endif
2813/** Pointer to an YMM register state. */
2814typedef X86YMMREG *PX86YMMREG;
2815/** Pointer to a const YMM register state. */
2816typedef X86YMMREG const *PCX86YMMREG;
2817
2818/**
2819 * ZMM register union.
2820 */
2821typedef union X86ZMMREG
2822{
2823 /** 8-bit view. */
2824 uint8_t au8[64];
2825 /** 16-bit view. */
2826 uint16_t au16[32];
2827 /** 32-bit view. */
2828 uint32_t au32[16];
2829 /** 64-bit view. */
2830 uint64_t au64[8];
2831 /** 128-bit view. (yeah, very helpful) */
2832 uint128_t au128[4];
2833 /** XMM sub register view. */
2834 X86XMMREG aXmm[4];
2835 /** YMM sub register view. */
2836 X86YMMREG aYmm[2];
2837} X86ZMMREG;
2838#ifndef VBOX_FOR_DTRACE_LIB
2839AssertCompileSize(X86ZMMREG, 64);
2840#endif
2841/** Pointer to an ZMM register state. */
2842typedef X86ZMMREG *PX86ZMMREG;
2843/** Pointer to a const ZMM register state. */
2844typedef X86ZMMREG const *PCX86ZMMREG;
2845
2846
2847/**
2848 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2849 * @todo verify this...
2850 */
2851#pragma pack(1)
2852typedef struct X86FPUSTATE
2853{
2854 /** 0x00 - Control word. */
2855 uint16_t FCW;
2856 /** 0x02 - Alignment word */
2857 uint16_t Dummy1;
2858 /** 0x04 - Status word. */
2859 uint16_t FSW;
2860 /** 0x06 - Alignment word */
2861 uint16_t Dummy2;
2862 /** 0x08 - Tag word */
2863 uint16_t FTW;
2864 /** 0x0a - Alignment word */
2865 uint16_t Dummy3;
2866
2867 /** 0x0c - Instruction pointer. */
2868 uint32_t FPUIP;
2869 /** 0x10 - Code selector. */
2870 uint16_t CS;
2871 /** 0x12 - Opcode. */
2872 uint16_t FOP;
2873 /** 0x14 - FOO. */
2874 uint32_t FPUOO;
2875 /** 0x18 - FOS. */
2876 uint32_t FPUOS;
2877 /** 0x1c - FPU register. */
2878 X86FPUREG regs[8];
2879} X86FPUSTATE;
2880#pragma pack()
2881/** Pointer to a FPU state. */
2882typedef X86FPUSTATE *PX86FPUSTATE;
2883/** Pointer to a const FPU state. */
2884typedef const X86FPUSTATE *PCX86FPUSTATE;
2885
2886/**
2887 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2888 */
2889#pragma pack(1)
2890typedef struct X86FXSTATE
2891{
2892 /** 0x00 - Control word. */
2893 uint16_t FCW;
2894 /** 0x02 - Status word. */
2895 uint16_t FSW;
2896 /** 0x04 - Tag word. (The upper byte is always zero.) */
2897 uint16_t FTW;
2898 /** 0x06 - Opcode. */
2899 uint16_t FOP;
2900 /** 0x08 - Instruction pointer. */
2901 uint32_t FPUIP;
2902 /** 0x0c - Code selector. */
2903 uint16_t CS;
2904 uint16_t Rsrvd1;
2905 /** 0x10 - Data pointer. */
2906 uint32_t FPUDP;
2907 /** 0x14 - Data segment */
2908 uint16_t DS;
2909 /** 0x16 */
2910 uint16_t Rsrvd2;
2911 /** 0x18 */
2912 uint32_t MXCSR;
2913 /** 0x1c */
2914 uint32_t MXCSR_MASK;
2915 /** 0x20 - FPU registers. */
2916 X86FPUREG aRegs[8];
2917 /** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
2918 X86XMMREG aXMM[16];
2919 /* - offset 416 - */
2920 uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2921 /* - offset 464 - Software usable reserved bits. */
2922 uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2923} X86FXSTATE;
2924#pragma pack()
2925/** Pointer to a FPU Extended state. */
2926typedef X86FXSTATE *PX86FXSTATE;
2927/** Pointer to a const FPU Extended state. */
2928typedef const X86FXSTATE *PCX86FXSTATE;
2929
2930/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2931 * magic. Don't forget to update x86.mac if you change this! */
2932#define X86_OFF_FXSTATE_RSVD 0x1d0
2933/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2934 * forget to update x86.mac if you change this!
2935 * @todo r=bird: This has nothing what-so-ever to do here.... */
2936#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2937#ifndef VBOX_FOR_DTRACE_LIB
2938AssertCompileSize(X86FXSTATE, 512);
2939AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2940#endif
2941
2942/** @name FPU status word flags.
2943 * @{ */
2944/** Exception Flag: Invalid operation. */
2945#define X86_FSW_IE RT_BIT_32(0)
2946/** Exception Flag: Denormalized operand. */
2947#define X86_FSW_DE RT_BIT_32(1)
2948/** Exception Flag: Zero divide. */
2949#define X86_FSW_ZE RT_BIT_32(2)
2950/** Exception Flag: Overflow. */
2951#define X86_FSW_OE RT_BIT_32(3)
2952/** Exception Flag: Underflow. */
2953#define X86_FSW_UE RT_BIT_32(4)
2954/** Exception Flag: Precision. */
2955#define X86_FSW_PE RT_BIT_32(5)
2956/** Stack fault. */
2957#define X86_FSW_SF RT_BIT_32(6)
2958/** Error summary status. */
2959#define X86_FSW_ES RT_BIT_32(7)
2960/** Mask of exceptions flags, excluding the summary bit. */
2961#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2962/** Mask of exceptions flags, including the summary bit. */
2963#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2964/** Condition code 0. */
2965#define X86_FSW_C0 RT_BIT_32(8)
2966/** Condition code 1. */
2967#define X86_FSW_C1 RT_BIT_32(9)
2968/** Condition code 2. */
2969#define X86_FSW_C2 RT_BIT_32(10)
2970/** Top of the stack mask. */
2971#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2972/** TOP shift value. */
2973#define X86_FSW_TOP_SHIFT 11
2974/** Mask for getting TOP value after shifting it right. */
2975#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2976/** Get the TOP value. */
2977#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2978/** Condition code 3. */
2979#define X86_FSW_C3 RT_BIT_32(14)
2980/** Mask of exceptions flags, including the summary bit. */
2981#define X86_FSW_C_MASK UINT16_C(0x4700)
2982/** FPU busy. */
2983#define X86_FSW_B RT_BIT_32(15)
2984/** @} */
2985
2986
2987/** @name FPU control word flags.
2988 * @{ */
2989/** Exception Mask: Invalid operation. */
2990#define X86_FCW_IM RT_BIT_32(0)
2991/** Exception Mask: Denormalized operand. */
2992#define X86_FCW_DM RT_BIT_32(1)
2993/** Exception Mask: Zero divide. */
2994#define X86_FCW_ZM RT_BIT_32(2)
2995/** Exception Mask: Overflow. */
2996#define X86_FCW_OM RT_BIT_32(3)
2997/** Exception Mask: Underflow. */
2998#define X86_FCW_UM RT_BIT_32(4)
2999/** Exception Mask: Precision. */
3000#define X86_FCW_PM RT_BIT_32(5)
3001/** Mask all exceptions, the value typically loaded (by for instance fninit).
3002 * @remarks This includes reserved bit 6. */
3003#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3004/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3005#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3006/** Precision control mask. */
3007#define X86_FCW_PC_MASK UINT16_C(0x0300)
3008/** Precision control: 24-bit. */
3009#define X86_FCW_PC_24 UINT16_C(0x0000)
3010/** Precision control: Reserved. */
3011#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3012/** Precision control: 53-bit. */
3013#define X86_FCW_PC_53 UINT16_C(0x0200)
3014/** Precision control: 64-bit. */
3015#define X86_FCW_PC_64 UINT16_C(0x0300)
3016/** Rounding control mask. */
3017#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3018/** Rounding control: To nearest. */
3019#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3020/** Rounding control: Down. */
3021#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3022/** Rounding control: Up. */
3023#define X86_FCW_RC_UP UINT16_C(0x0800)
3024/** Rounding control: Towards zero. */
3025#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3026/** Bits which should be zero, apparently. */
3027#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3028/** @} */
3029
3030/** @name SSE MXCSR
3031 * @{ */
3032/** Exception Flag: Invalid operation. */
3033#define X86_MXCSR_IE RT_BIT_32(0)
3034/** Exception Flag: Denormalized operand. */
3035#define X86_MXCSR_DE RT_BIT_32(1)
3036/** Exception Flag: Zero divide. */
3037#define X86_MXCSR_ZE RT_BIT_32(2)
3038/** Exception Flag: Overflow. */
3039#define X86_MXCSR_OE RT_BIT_32(3)
3040/** Exception Flag: Underflow. */
3041#define X86_MXCSR_UE RT_BIT_32(4)
3042/** Exception Flag: Precision. */
3043#define X86_MXCSR_PE RT_BIT_32(5)
3044
3045/** Denormals are zero. */
3046#define X86_MXCSR_DAZ RT_BIT_32(6)
3047
3048/** Exception Mask: Invalid operation. */
3049#define X86_MXCSR_IM RT_BIT_32(7)
3050/** Exception Mask: Denormalized operand. */
3051#define X86_MXCSR_DM RT_BIT_32(8)
3052/** Exception Mask: Zero divide. */
3053#define X86_MXCSR_ZM RT_BIT_32(9)
3054/** Exception Mask: Overflow. */
3055#define X86_MXCSR_OM RT_BIT_32(10)
3056/** Exception Mask: Underflow. */
3057#define X86_MXCSR_UM RT_BIT_32(11)
3058/** Exception Mask: Precision. */
3059#define X86_MXCSR_PM RT_BIT_32(12)
3060
3061/** Rounding control mask. */
3062#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
3063/** Rounding control: To nearest. */
3064#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3065/** Rounding control: Down. */
3066#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3067/** Rounding control: Up. */
3068#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3069/** Rounding control: Towards zero. */
3070#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3071
3072/** Flush-to-zero for masked underflow. */
3073#define X86_MXCSR_FZ RT_BIT_32(15)
3074
3075/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3076#define X86_MXCSR_MM RT_BIT_32(17)
3077/** @} */
3078
3079/**
3080 * XSAVE header.
3081 */
3082typedef struct X86XSAVEHDR
3083{
3084 /** XTATE_BV - Bitmap indicating whether a component is in the state. */
3085 uint64_t bmXState;
3086 /** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3087 uint64_t bmXComp;
3088 /** Reserved for furture extensions, probably MBZ. */
3089 uint64_t au64Reserved[6];
3090} X86XSAVEHDR;
3091#ifndef VBOX_FOR_DTRACE_LIB
3092AssertCompileSize(X86XSAVEHDR, 64);
3093#endif
3094/** Pointer to an XSAVE header. */
3095typedef X86XSAVEHDR *PX86XSAVEHDR;
3096/** Pointer to a const XSAVE header. */
3097typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3098
3099
3100/**
3101 * The high 128-bit YMM register state (XSAVE_C_YMM).
3102 * (The lower 128-bits being in X86FXSTATE.)
3103 */
3104typedef struct X86XSAVEYMMHI
3105{
3106 /** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3107 X86XMMREG aYmmHi[16];
3108} X86XSAVEYMMHI;
3109#ifndef VBOX_FOR_DTRACE_LIB
3110AssertCompileSize(X86XSAVEYMMHI, 256);
3111#endif
3112/** Pointer to a high 128-bit YMM register state. */
3113typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3114/** Pointer to a const high 128-bit YMM register state. */
3115typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3116
3117/**
3118 * Intel MPX bound registers state (XSAVE_C_BNDREGS).
3119 */
3120typedef struct X86XSAVEBNDREGS
3121{
3122 /** Array of registers (BND0...BND3). */
3123 struct
3124 {
3125 /** Lower bound. */
3126 uint64_t uLowerBound;
3127 /** Upper bound. */
3128 uint64_t uUpperBound;
3129 } aRegs[4];
3130} X86XSAVEBNDREGS;
3131#ifndef VBOX_FOR_DTRACE_LIB
3132AssertCompileSize(X86XSAVEBNDREGS, 64);
3133#endif
3134/** Pointer to a MPX bound register state. */
3135typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3136/** Pointer to a const MPX bound register state. */
3137typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3138
3139/**
3140 * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3141 */
3142typedef struct X86XSAVEBNDCFG
3143{
3144 uint64_t fConfig;
3145 uint64_t fStatus;
3146} X86XSAVEBNDCFG;
3147#ifndef VBOX_FOR_DTRACE_LIB
3148AssertCompileSize(X86XSAVEBNDCFG, 16);
3149#endif
3150/** Pointer to a MPX bound config and status register state. */
3151typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3152/** Pointer to a const MPX bound config and status register state. */
3153typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3154
3155/**
3156 * AVX-512 opmask state (XSAVE_C_OPMASK).
3157 */
3158typedef struct X86XSAVEOPMASK
3159{
3160 /** The K0..K7 values. */
3161 uint64_t aKRegs[8];
3162} X86XSAVEOPMASK;
3163#ifndef VBOX_FOR_DTRACE_LIB
3164AssertCompileSize(X86XSAVEOPMASK, 64);
3165#endif
3166/** Pointer to a AVX-512 opmask state. */
3167typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3168/** Pointer to a const AVX-512 opmask state. */
3169typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3170
3171/**
3172 * ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3173 */
3174typedef struct X86XSAVEZMMHI256
3175{
3176 /** Upper 256-bits of ZMM0-15. */
3177 X86YMMREG aHi256Regs[16];
3178} X86XSAVEZMMHI256;
3179#ifndef VBOX_FOR_DTRACE_LIB
3180AssertCompileSize(X86XSAVEZMMHI256, 512);
3181#endif
3182/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3183typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3184/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3185typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3186
3187/**
3188 * ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3189 */
3190typedef struct X86XSAVEZMM16HI
3191{
3192 /** ZMM16 thru ZMM31. */
3193 X86ZMMREG aRegs[16];
3194} X86XSAVEZMM16HI;
3195#ifndef VBOX_FOR_DTRACE_LIB
3196AssertCompileSize(X86XSAVEZMM16HI, 1024);
3197#endif
3198/** Pointer to a state comprising ZMM16-32. */
3199typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3200/** Pointer to a const state comprising ZMM16-32. */
3201typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3202
3203/**
3204 * AMD Light weight profiling state (XSAVE_C_LWP).
3205 *
3206 * We probably won't play with this as AMD seems to be dropping from their "zen"
3207 * processor micro architecture.
3208 */
3209typedef struct X86XSAVELWP
3210{
3211 /** Details when needed. */
3212 uint64_t auLater[128/8];
3213} X86XSAVELWP;
3214#ifndef VBOX_FOR_DTRACE_LIB
3215AssertCompileSize(X86XSAVELWP, 128);
3216#endif
3217
3218
3219/**
3220 * x86 FPU/SSE/AVX/XXXX state.
3221 *
3222 * Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3223 * changes to this structure.
3224 */
3225typedef struct X86XSAVEAREA
3226{
3227 /** The x87 and SSE region (or legacy region if you like). */
3228 X86FXSTATE x87;
3229 /** The XSAVE header. */
3230 X86XSAVEHDR Hdr;
3231 /** Beyond the header, there isn't really a fixed layout, but we can
3232 generally assume the YMM (AVX) register extensions are present and
3233 follows immediately. */
3234 union
3235 {
3236 /** The high 128-bit AVX registers for easy access by IEM.
3237 * @note This ASSUMES they will always be here... */
3238 X86XSAVEYMMHI YmmHi;
3239
3240 /** This is a typical layout on intel CPUs (good for debuggers). */
3241 struct
3242 {
3243 X86XSAVEYMMHI YmmHi;
3244 X86XSAVEBNDREGS BndRegs;
3245 X86XSAVEBNDCFG BndCfg;
3246 uint8_t abFudgeToMatchDocs[0xB0];
3247 X86XSAVEOPMASK Opmask;
3248 X86XSAVEZMMHI256 ZmmHi256;
3249 X86XSAVEZMM16HI Zmm16Hi;
3250 } Intel;
3251
3252 /** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3253 struct
3254 {
3255 X86XSAVEYMMHI YmmHi;
3256 X86XSAVELWP Lwp;
3257 } AmdBd;
3258
3259 /** To enbling static deployments that have a reasonable chance of working for
3260 * the next 3-6 CPU generations without running short on space, we allocate a
3261 * lot of extra space here, making the structure a round 8KB in size. This
3262 * leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3263 * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3264 uint8_t ab[8192 - 512 - 64];
3265 } u;
3266} X86XSAVEAREA;
3267#ifndef VBOX_FOR_DTRACE_LIB
3268AssertCompileSize(X86XSAVEAREA, 8192);
3269AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
3270AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3271AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3272AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3273AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3274AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3275AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3276AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3277#endif
3278/** Pointer to a XSAVE area. */
3279typedef X86XSAVEAREA *PX86XSAVEAREA;
3280/** Pointer to a const XSAVE area. */
3281typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3282
3283
3284/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3285 * @{ */
3286/** Bit 0 - x87 - Legacy FPU state (bit number) */
3287#define XSAVE_C_X87_BIT 0
3288/** Bit 0 - x87 - Legacy FPU state. */
3289#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3290/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3291#define XSAVE_C_SSE_BIT 1
3292/** Bit 1 - SSE - 128-bit SSE state. */
3293#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3294/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3295#define XSAVE_C_YMM_BIT 2
3296/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3297#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3298/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3299#define XSAVE_C_BNDREGS_BIT 3
3300/** Bit 3 - BNDREGS - MPX bound register state. */
3301#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3302/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3303#define XSAVE_C_BNDCSR_BIT 4
3304/** Bit 4 - BNDCSR - MPX bound config and status state. */
3305#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3306/** Bit 5 - Opmask - opmask state (bit number). */
3307#define XSAVE_C_OPMASK_BIT 5
3308/** Bit 5 - Opmask - opmask state. */
3309#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3310/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3311#define XSAVE_C_ZMM_HI256_BIT 6
3312/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3313#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3314/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3315#define XSAVE_C_ZMM_16HI_BIT 7
3316/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3317#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3318/** Bit 9 - PKRU - Protection-key state (bit number). */
3319#define XSAVE_C_PKRU_BIT 9
3320/** Bit 9 - PKRU - Protection-key state. */
3321#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3322/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3323#define XSAVE_C_LWP_BIT 62
3324/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3325#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3326/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3327#define XSAVE_C_X_BIT 63
3328/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3329#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3330/** @} */
3331
3332
3333
3334/** @name Selector Descriptor
3335 * @{
3336 */
3337
3338#ifndef VBOX_FOR_DTRACE_LIB
3339/**
3340 * Descriptor attributes (as seen by VT-x).
3341 */
3342typedef struct X86DESCATTRBITS
3343{
3344 /** 00 - Segment Type. */
3345 unsigned u4Type : 4;
3346 /** 04 - Descriptor Type. System(=0) or code/data selector */
3347 unsigned u1DescType : 1;
3348 /** 05 - Descriptor Privilege level. */
3349 unsigned u2Dpl : 2;
3350 /** 07 - Flags selector present(=1) or not. */
3351 unsigned u1Present : 1;
3352 /** 08 - Segment limit 16-19. */
3353 unsigned u4LimitHigh : 4;
3354 /** 0c - Available for system software. */
3355 unsigned u1Available : 1;
3356 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3357 unsigned u1Long : 1;
3358 /** 0e - This flags meaning depends on the segment type. Try make sense out
3359 * of the intel manual yourself. */
3360 unsigned u1DefBig : 1;
3361 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
3362 * clear byte. */
3363 unsigned u1Granularity : 1;
3364 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3365 unsigned u1Unusable : 1;
3366} X86DESCATTRBITS;
3367#endif /* !VBOX_FOR_DTRACE_LIB */
3368
3369/** @name X86DESCATTR masks
3370 * @{ */
3371#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3372#define X86DESCATTR_DT UINT32_C(0x00000010)
3373#define X86DESCATTR_DPL UINT32_C(0x00000060)
3374#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
3375#define X86DESCATTR_P UINT32_C(0x00000080)
3376#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3377#define X86DESCATTR_AVL UINT32_C(0x00001000)
3378#define X86DESCATTR_L UINT32_C(0x00002000)
3379#define X86DESCATTR_D UINT32_C(0x00004000)
3380#define X86DESCATTR_G UINT32_C(0x00008000)
3381#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3382/** @} */
3383
3384#pragma pack(1)
3385typedef union X86DESCATTR
3386{
3387 /** Unsigned integer view. */
3388 uint32_t u;
3389#ifndef VBOX_FOR_DTRACE_LIB
3390 /** Normal view. */
3391 X86DESCATTRBITS n;
3392#endif
3393} X86DESCATTR;
3394#pragma pack()
3395/** Pointer to descriptor attributes. */
3396typedef X86DESCATTR *PX86DESCATTR;
3397/** Pointer to const descriptor attributes. */
3398typedef const X86DESCATTR *PCX86DESCATTR;
3399
3400#ifndef VBOX_FOR_DTRACE_LIB
3401
3402/**
3403 * Generic descriptor table entry
3404 */
3405#pragma pack(1)
3406typedef struct X86DESCGENERIC
3407{
3408 /** 00 - Limit - Low word. */
3409 unsigned u16LimitLow : 16;
3410 /** 10 - Base address - low word.
3411 * Don't try set this to 24 because MSC is doing stupid things then. */
3412 unsigned u16BaseLow : 16;
3413 /** 20 - Base address - first 8 bits of high word. */
3414 unsigned u8BaseHigh1 : 8;
3415 /** 28 - Segment Type. */
3416 unsigned u4Type : 4;
3417 /** 2c - Descriptor Type. System(=0) or code/data selector */
3418 unsigned u1DescType : 1;
3419 /** 2d - Descriptor Privilege level. */
3420 unsigned u2Dpl : 2;
3421 /** 2f - Flags selector present(=1) or not. */
3422 unsigned u1Present : 1;
3423 /** 30 - Segment limit 16-19. */
3424 unsigned u4LimitHigh : 4;
3425 /** 34 - Available for system software. */
3426 unsigned u1Available : 1;
3427 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3428 unsigned u1Long : 1;
3429 /** 36 - This flags meaning depends on the segment type. Try make sense out
3430 * of the intel manual yourself. */
3431 unsigned u1DefBig : 1;
3432 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
3433 * clear byte. */
3434 unsigned u1Granularity : 1;
3435 /** 38 - Base address - highest 8 bits. */
3436 unsigned u8BaseHigh2 : 8;
3437} X86DESCGENERIC;
3438#pragma pack()
3439/** Pointer to a generic descriptor entry. */
3440typedef X86DESCGENERIC *PX86DESCGENERIC;
3441/** Pointer to a const generic descriptor entry. */
3442typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3443
3444/** @name Bit offsets of X86DESCGENERIC members.
3445 * @{*/
3446#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
3447#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
3448#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
3449#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
3450#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
3451#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
3452#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
3453#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
3454#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
3455#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
3456#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
3457#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
3458#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
3459/** @} */
3460
3461
3462/** @name LAR mask
3463 * @{ */
3464#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3465#define X86LAR_F_DT UINT16_C( 0x1000)
3466#define X86LAR_F_DPL UINT16_C( 0x6000)
3467#define X86LAR_F_DPL_SHIFT 13 /**< Shift count for the DPL value. */
3468#define X86LAR_F_P UINT16_C( 0x8000)
3469#define X86LAR_F_AVL UINT32_C(0x00100000)
3470#define X86LAR_F_L UINT32_C(0x00200000)
3471#define X86LAR_F_D UINT32_C(0x00400000)
3472#define X86LAR_F_G UINT32_C(0x00800000)
3473/** @} */
3474
3475
3476/**
3477 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3478 */
3479typedef struct X86DESCGATE
3480{
3481 /** 00 - Target code segment offset - Low word.
3482 * Ignored if task-gate. */
3483 unsigned u16OffsetLow : 16;
3484 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3485 * TSS selector if task-gate. */
3486 unsigned u16Sel : 16;
3487 /** 20 - Number of parameters for a call-gate.
3488 * Ignored if interrupt-, trap- or task-gate. */
3489 unsigned u5ParmCount : 5;
3490 /** 25 - Reserved / ignored. */
3491 unsigned u3Reserved : 3;
3492 /** 28 - Segment Type. */
3493 unsigned u4Type : 4;
3494 /** 2c - Descriptor Type (0 = system). */
3495 unsigned u1DescType : 1;
3496 /** 2d - Descriptor Privilege level. */
3497 unsigned u2Dpl : 2;
3498 /** 2f - Flags selector present(=1) or not. */
3499 unsigned u1Present : 1;
3500 /** 30 - Target code segment offset - High word.
3501 * Ignored if task-gate. */
3502 unsigned u16OffsetHigh : 16;
3503} X86DESCGATE;
3504/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3505typedef X86DESCGATE *PX86DESCGATE;
3506/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3507typedef const X86DESCGATE *PCX86DESCGATE;
3508
3509#endif /* VBOX_FOR_DTRACE_LIB */
3510
3511/**
3512 * Descriptor table entry.
3513 */
3514#pragma pack(1)
3515typedef union X86DESC
3516{
3517#ifndef VBOX_FOR_DTRACE_LIB
3518 /** Generic descriptor view. */
3519 X86DESCGENERIC Gen;
3520 /** Gate descriptor view. */
3521 X86DESCGATE Gate;
3522#endif
3523
3524 /** 8 bit unsigned integer view. */
3525 uint8_t au8[8];
3526 /** 16 bit unsigned integer view. */
3527 uint16_t au16[4];
3528 /** 32 bit unsigned integer view. */
3529 uint32_t au32[2];
3530 /** 64 bit unsigned integer view. */
3531 uint64_t au64[1];
3532 /** Unsigned integer view. */
3533 uint64_t u;
3534} X86DESC;
3535#ifndef VBOX_FOR_DTRACE_LIB
3536AssertCompileSize(X86DESC, 8);
3537#endif
3538#pragma pack()
3539/** Pointer to descriptor table entry. */
3540typedef X86DESC *PX86DESC;
3541/** Pointer to const descriptor table entry. */
3542typedef const X86DESC *PCX86DESC;
3543
3544/** @def X86DESC_BASE
3545 * Return the base address of a descriptor.
3546 */
3547#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
3548 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3549 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3550 | ( (a_pDesc)->Gen.u16BaseLow ) )
3551
3552/** @def X86DESC_LIMIT
3553 * Return the limit of a descriptor.
3554 */
3555#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
3556 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3557 | ( (a_pDesc)->Gen.u16LimitLow ) )
3558
3559/** @def X86DESC_LIMIT_G
3560 * Return the limit of a descriptor with the granularity bit taken into account.
3561 * @returns Selector limit (uint32_t).
3562 * @param a_pDesc Pointer to the descriptor.
3563 */
3564#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
3565 ( (a_pDesc)->Gen.u1Granularity \
3566 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
3567 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
3568 )
3569
3570/** @def X86DESC_GET_HID_ATTR
3571 * Get the descriptor attributes for the hidden register.
3572 */
3573#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
3574 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3575
3576#ifndef VBOX_FOR_DTRACE_LIB
3577
3578/**
3579 * 64 bits generic descriptor table entry
3580 * Note: most of these bits have no meaning in long mode.
3581 */
3582#pragma pack(1)
3583typedef struct X86DESC64GENERIC
3584{
3585 /** Limit - Low word - *IGNORED*. */
3586 uint32_t u16LimitLow : 16;
3587 /** Base address - low word. - *IGNORED*
3588 * Don't try set this to 24 because MSC is doing stupid things then. */
3589 uint32_t u16BaseLow : 16;
3590 /** Base address - first 8 bits of high word. - *IGNORED* */
3591 uint32_t u8BaseHigh1 : 8;
3592 /** Segment Type. */
3593 uint32_t u4Type : 4;
3594 /** Descriptor Type. System(=0) or code/data selector */
3595 uint32_t u1DescType : 1;
3596 /** Descriptor Privilege level. */
3597 uint32_t u2Dpl : 2;
3598 /** Flags selector present(=1) or not. */
3599 uint32_t u1Present : 1;
3600 /** Segment limit 16-19. - *IGNORED* */
3601 uint32_t u4LimitHigh : 4;
3602 /** Available for system software. - *IGNORED* */
3603 uint32_t u1Available : 1;
3604 /** Long mode flag. */
3605 uint32_t u1Long : 1;
3606 /** This flags meaning depends on the segment type. Try make sense out
3607 * of the intel manual yourself. */
3608 uint32_t u1DefBig : 1;
3609 /** Granularity of the limit. If set 4KB granularity is used, if
3610 * clear byte. - *IGNORED* */
3611 uint32_t u1Granularity : 1;
3612 /** Base address - highest 8 bits. - *IGNORED* */
3613 uint32_t u8BaseHigh2 : 8;
3614 /** Base address - bits 63-32. */
3615 uint32_t u32BaseHigh3 : 32;
3616 uint32_t u8Reserved : 8;
3617 uint32_t u5Zeros : 5;
3618 uint32_t u19Reserved : 19;
3619} X86DESC64GENERIC;
3620#pragma pack()
3621/** Pointer to a generic descriptor entry. */
3622typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3623/** Pointer to a const generic descriptor entry. */
3624typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3625
3626/**
3627 * System descriptor table entry (64 bits)
3628 *
3629 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3630 */
3631#pragma pack(1)
3632typedef struct X86DESC64SYSTEM
3633{
3634 /** Limit - Low word. */
3635 uint32_t u16LimitLow : 16;
3636 /** Base address - low word.
3637 * Don't try set this to 24 because MSC is doing stupid things then. */
3638 uint32_t u16BaseLow : 16;
3639 /** Base address - first 8 bits of high word. */
3640 uint32_t u8BaseHigh1 : 8;
3641 /** Segment Type. */
3642 uint32_t u4Type : 4;
3643 /** Descriptor Type. System(=0) or code/data selector */
3644 uint32_t u1DescType : 1;
3645 /** Descriptor Privilege level. */
3646 uint32_t u2Dpl : 2;
3647 /** Flags selector present(=1) or not. */
3648 uint32_t u1Present : 1;
3649 /** Segment limit 16-19. */
3650 uint32_t u4LimitHigh : 4;
3651 /** Available for system software. */
3652 uint32_t u1Available : 1;
3653 /** Reserved - 0. */
3654 uint32_t u1Reserved : 1;
3655 /** This flags meaning depends on the segment type. Try make sense out
3656 * of the intel manual yourself. */
3657 uint32_t u1DefBig : 1;
3658 /** Granularity of the limit. If set 4KB granularity is used, if
3659 * clear byte. */
3660 uint32_t u1Granularity : 1;
3661 /** Base address - bits 31-24. */
3662 uint32_t u8BaseHigh2 : 8;
3663 /** Base address - bits 63-32. */
3664 uint32_t u32BaseHigh3 : 32;
3665 uint32_t u8Reserved : 8;
3666 uint32_t u5Zeros : 5;
3667 uint32_t u19Reserved : 19;
3668} X86DESC64SYSTEM;
3669#pragma pack()
3670/** Pointer to a system descriptor entry. */
3671typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3672/** Pointer to a const system descriptor entry. */
3673typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3674
3675/**
3676 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3677 */
3678typedef struct X86DESC64GATE
3679{
3680 /** Target code segment offset - Low word. */
3681 uint32_t u16OffsetLow : 16;
3682 /** Target code segment selector. */
3683 uint32_t u16Sel : 16;
3684 /** Interrupt stack table for interrupt- and trap-gates.
3685 * Ignored by call-gates. */
3686 uint32_t u3IST : 3;
3687 /** Reserved / ignored. */
3688 uint32_t u5Reserved : 5;
3689 /** Segment Type. */
3690 uint32_t u4Type : 4;
3691 /** Descriptor Type (0 = system). */
3692 uint32_t u1DescType : 1;
3693 /** Descriptor Privilege level. */
3694 uint32_t u2Dpl : 2;
3695 /** Flags selector present(=1) or not. */
3696 uint32_t u1Present : 1;
3697 /** Target code segment offset - High word.
3698 * Ignored if task-gate. */
3699 uint32_t u16OffsetHigh : 16;
3700 /** Target code segment offset - Top dword.
3701 * Ignored if task-gate. */
3702 uint32_t u32OffsetTop : 32;
3703 /** Reserved / ignored / must be zero.
3704 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3705 uint32_t u32Reserved : 32;
3706} X86DESC64GATE;
3707AssertCompileSize(X86DESC64GATE, 16);
3708/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3709typedef X86DESC64GATE *PX86DESC64GATE;
3710/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3711typedef const X86DESC64GATE *PCX86DESC64GATE;
3712
3713#endif /* VBOX_FOR_DTRACE_LIB */
3714
3715/**
3716 * Descriptor table entry.
3717 */
3718#pragma pack(1)
3719typedef union X86DESC64
3720{
3721#ifndef VBOX_FOR_DTRACE_LIB
3722 /** Generic descriptor view. */
3723 X86DESC64GENERIC Gen;
3724 /** System descriptor view. */
3725 X86DESC64SYSTEM System;
3726 /** Gate descriptor view. */
3727 X86DESC64GATE Gate;
3728#endif
3729
3730 /** 8 bit unsigned integer view. */
3731 uint8_t au8[16];
3732 /** 16 bit unsigned integer view. */
3733 uint16_t au16[8];
3734 /** 32 bit unsigned integer view. */
3735 uint32_t au32[4];
3736 /** 64 bit unsigned integer view. */
3737 uint64_t au64[2];
3738} X86DESC64;
3739#ifndef VBOX_FOR_DTRACE_LIB
3740AssertCompileSize(X86DESC64, 16);
3741#endif
3742#pragma pack()
3743/** Pointer to descriptor table entry. */
3744typedef X86DESC64 *PX86DESC64;
3745/** Pointer to const descriptor table entry. */
3746typedef const X86DESC64 *PCX86DESC64;
3747
3748/** @def X86DESC64_BASE
3749 * Return the base of a 64-bit descriptor.
3750 */
3751#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
3752 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3753 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3754 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3755 | ( (a_pDesc)->Gen.u16BaseLow ) )
3756
3757
3758
3759/** @name Host system descriptor table entry - Use with care!
3760 * @{ */
3761/** Host system descriptor table entry. */
3762#if HC_ARCH_BITS == 64
3763typedef X86DESC64 X86DESCHC;
3764#else
3765typedef X86DESC X86DESCHC;
3766#endif
3767/** Pointer to a host system descriptor table entry. */
3768#if HC_ARCH_BITS == 64
3769typedef PX86DESC64 PX86DESCHC;
3770#else
3771typedef PX86DESC PX86DESCHC;
3772#endif
3773/** Pointer to a const host system descriptor table entry. */
3774#if HC_ARCH_BITS == 64
3775typedef PCX86DESC64 PCX86DESCHC;
3776#else
3777typedef PCX86DESC PCX86DESCHC;
3778#endif
3779/** @} */
3780
3781
3782/** @name Selector Descriptor Types.
3783 * @{
3784 */
3785
3786/** @name Non-System Selector Types.
3787 * @{ */
3788/** Code(=set)/Data(=clear) bit. */
3789#define X86_SEL_TYPE_CODE 8
3790/** Memory(=set)/System(=clear) bit. */
3791#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3792/** Accessed bit. */
3793#define X86_SEL_TYPE_ACCESSED 1
3794/** Expand down bit (for data selectors only). */
3795#define X86_SEL_TYPE_DOWN 4
3796/** Conforming bit (for code selectors only). */
3797#define X86_SEL_TYPE_CONF 4
3798/** Write bit (for data selectors only). */
3799#define X86_SEL_TYPE_WRITE 2
3800/** Read bit (for code selectors only). */
3801#define X86_SEL_TYPE_READ 2
3802/** The bit number of the code segment read bit (relative to u4Type). */
3803#define X86_SEL_TYPE_READ_BIT 1
3804
3805/** Read only selector type. */
3806#define X86_SEL_TYPE_RO 0
3807/** Accessed read only selector type. */
3808#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
3809/** Read write selector type. */
3810#define X86_SEL_TYPE_RW 2
3811/** Accessed read write selector type. */
3812#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
3813/** Expand down read only selector type. */
3814#define X86_SEL_TYPE_RO_DOWN 4
3815/** Accessed expand down read only selector type. */
3816#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
3817/** Expand down read write selector type. */
3818#define X86_SEL_TYPE_RW_DOWN 6
3819/** Accessed expand down read write selector type. */
3820#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
3821/** Execute only selector type. */
3822#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
3823/** Accessed execute only selector type. */
3824#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3825/** Execute and read selector type. */
3826#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
3827/** Accessed execute and read selector type. */
3828#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3829/** Conforming execute only selector type. */
3830#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
3831/** Accessed Conforming execute only selector type. */
3832#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3833/** Conforming execute and write selector type. */
3834#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
3835/** Accessed Conforming execute and write selector type. */
3836#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3837/** @} */
3838
3839
3840/** @name System Selector Types.
3841 * @{ */
3842/** The TSS busy bit mask. */
3843#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3844
3845/** Undefined system selector type. */
3846#define X86_SEL_TYPE_SYS_UNDEFINED 0
3847/** 286 TSS selector. */
3848#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3849/** LDT selector. */
3850#define X86_SEL_TYPE_SYS_LDT 2
3851/** 286 TSS selector - Busy. */
3852#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3853/** 286 Callgate selector. */
3854#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3855/** Taskgate selector. */
3856#define X86_SEL_TYPE_SYS_TASK_GATE 5
3857/** 286 Interrupt gate selector. */
3858#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3859/** 286 Trapgate selector. */
3860#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3861/** Undefined system selector. */
3862#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3863/** 386 TSS selector. */
3864#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3865/** Undefined system selector. */
3866#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3867/** 386 TSS selector - Busy. */
3868#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3869/** 386 Callgate selector. */
3870#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3871/** Undefined system selector. */
3872#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3873/** 386 Interruptgate selector. */
3874#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3875/** 386 Trapgate selector. */
3876#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3877/** @} */
3878
3879/** @name AMD64 System Selector Types.
3880 * @{ */
3881/** LDT selector. */
3882#define AMD64_SEL_TYPE_SYS_LDT 2
3883/** TSS selector - Busy. */
3884#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3885/** TSS selector - Busy. */
3886#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3887/** Callgate selector. */
3888#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3889/** Interruptgate selector. */
3890#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3891/** Trapgate selector. */
3892#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3893/** @} */
3894
3895/** @} */
3896
3897
3898/** @name Descriptor Table Entry Flag Masks.
3899 * These are for the 2nd 32-bit word of a descriptor.
3900 * @{ */
3901/** Bits 8-11 - TYPE - Descriptor type mask. */
3902#define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
3903/** Bit 12 - S - System (=0) or Code/Data (=1). */
3904#define X86_DESC_S RT_BIT_32(12)
3905/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3906#define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
3907/** Bit 15 - P - Present. */
3908#define X86_DESC_P RT_BIT_32(15)
3909/** Bit 20 - AVL - Available for system software. */
3910#define X86_DESC_AVL RT_BIT_32(20)
3911/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3912#define X86_DESC_DB RT_BIT_32(22)
3913/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3914 * used, if clear byte. */
3915#define X86_DESC_G RT_BIT_32(23)
3916/** @} */
3917
3918/** @} */
3919
3920
3921/** @name Task Segments.
3922 * @{
3923 */
3924
3925/**
3926 * The minimum TSS descriptor limit for 286 tasks.
3927 */
3928#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3929
3930/**
3931 * The minimum TSS descriptor segment limit for 386 tasks.
3932 */
3933#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3934
3935/**
3936 * 16-bit Task Segment (TSS).
3937 */
3938#pragma pack(1)
3939typedef struct X86TSS16
3940{
3941 /** Back link to previous task. (static) */
3942 RTSEL selPrev;
3943 /** Ring-0 stack pointer. (static) */
3944 uint16_t sp0;
3945 /** Ring-0 stack segment. (static) */
3946 RTSEL ss0;
3947 /** Ring-1 stack pointer. (static) */
3948 uint16_t sp1;
3949 /** Ring-1 stack segment. (static) */
3950 RTSEL ss1;
3951 /** Ring-2 stack pointer. (static) */
3952 uint16_t sp2;
3953 /** Ring-2 stack segment. (static) */
3954 RTSEL ss2;
3955 /** IP before task switch. */
3956 uint16_t ip;
3957 /** FLAGS before task switch. */
3958 uint16_t flags;
3959 /** AX before task switch. */
3960 uint16_t ax;
3961 /** CX before task switch. */
3962 uint16_t cx;
3963 /** DX before task switch. */
3964 uint16_t dx;
3965 /** BX before task switch. */
3966 uint16_t bx;
3967 /** SP before task switch. */
3968 uint16_t sp;
3969 /** BP before task switch. */
3970 uint16_t bp;
3971 /** SI before task switch. */
3972 uint16_t si;
3973 /** DI before task switch. */
3974 uint16_t di;
3975 /** ES before task switch. */
3976 RTSEL es;
3977 /** CS before task switch. */
3978 RTSEL cs;
3979 /** SS before task switch. */
3980 RTSEL ss;
3981 /** DS before task switch. */
3982 RTSEL ds;
3983 /** LDTR before task switch. */
3984 RTSEL selLdt;
3985} X86TSS16;
3986#ifndef VBOX_FOR_DTRACE_LIB
3987AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
3988#endif
3989#pragma pack()
3990/** Pointer to a 16-bit task segment. */
3991typedef X86TSS16 *PX86TSS16;
3992/** Pointer to a const 16-bit task segment. */
3993typedef const X86TSS16 *PCX86TSS16;
3994
3995
3996/**
3997 * 32-bit Task Segment (TSS).
3998 */
3999#pragma pack(1)
4000typedef struct X86TSS32
4001{
4002 /** Back link to previous task. (static) */
4003 RTSEL selPrev;
4004 uint16_t padding1;
4005 /** Ring-0 stack pointer. (static) */
4006 uint32_t esp0;
4007 /** Ring-0 stack segment. (static) */
4008 RTSEL ss0;
4009 uint16_t padding_ss0;
4010 /** Ring-1 stack pointer. (static) */
4011 uint32_t esp1;
4012 /** Ring-1 stack segment. (static) */
4013 RTSEL ss1;
4014 uint16_t padding_ss1;
4015 /** Ring-2 stack pointer. (static) */
4016 uint32_t esp2;
4017 /** Ring-2 stack segment. (static) */
4018 RTSEL ss2;
4019 uint16_t padding_ss2;
4020 /** Page directory for the task. (static) */
4021 uint32_t cr3;
4022 /** EIP before task switch. */
4023 uint32_t eip;
4024 /** EFLAGS before task switch. */
4025 uint32_t eflags;
4026 /** EAX before task switch. */
4027 uint32_t eax;
4028 /** ECX before task switch. */
4029 uint32_t ecx;
4030 /** EDX before task switch. */
4031 uint32_t edx;
4032 /** EBX before task switch. */
4033 uint32_t ebx;
4034 /** ESP before task switch. */
4035 uint32_t esp;
4036 /** EBP before task switch. */
4037 uint32_t ebp;
4038 /** ESI before task switch. */
4039 uint32_t esi;
4040 /** EDI before task switch. */
4041 uint32_t edi;
4042 /** ES before task switch. */
4043 RTSEL es;
4044 uint16_t padding_es;
4045 /** CS before task switch. */
4046 RTSEL cs;
4047 uint16_t padding_cs;
4048 /** SS before task switch. */
4049 RTSEL ss;
4050 uint16_t padding_ss;
4051 /** DS before task switch. */
4052 RTSEL ds;
4053 uint16_t padding_ds;
4054 /** FS before task switch. */
4055 RTSEL fs;
4056 uint16_t padding_fs;
4057 /** GS before task switch. */
4058 RTSEL gs;
4059 uint16_t padding_gs;
4060 /** LDTR before task switch. */
4061 RTSEL selLdt;
4062 uint16_t padding_ldt;
4063 /** Debug trap flag */
4064 uint16_t fDebugTrap;
4065 /** Offset relative to the TSS of the start of the I/O Bitmap
4066 * and the end of the interrupt redirection bitmap. */
4067 uint16_t offIoBitmap;
4068} X86TSS32;
4069#pragma pack()
4070/** Pointer to task segment. */
4071typedef X86TSS32 *PX86TSS32;
4072/** Pointer to const task segment. */
4073typedef const X86TSS32 *PCX86TSS32;
4074#ifndef VBOX_FOR_DTRACE_LIB
4075AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4076AssertCompileMemberOffset(X86TSS32, cr3, 28);
4077AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4078#endif
4079
4080/**
4081 * 64-bit Task segment.
4082 */
4083#pragma pack(1)
4084typedef struct X86TSS64
4085{
4086 /** Reserved. */
4087 uint32_t u32Reserved;
4088 /** Ring-0 stack pointer. (static) */
4089 uint64_t rsp0;
4090 /** Ring-1 stack pointer. (static) */
4091 uint64_t rsp1;
4092 /** Ring-2 stack pointer. (static) */
4093 uint64_t rsp2;
4094 /** Reserved. */
4095 uint32_t u32Reserved2[2];
4096 /* IST */
4097 uint64_t ist1;
4098 uint64_t ist2;
4099 uint64_t ist3;
4100 uint64_t ist4;
4101 uint64_t ist5;
4102 uint64_t ist6;
4103 uint64_t ist7;
4104 /* Reserved. */
4105 uint16_t u16Reserved[5];
4106 /** Offset relative to the TSS of the start of the I/O Bitmap
4107 * and the end of the interrupt redirection bitmap. */
4108 uint16_t offIoBitmap;
4109} X86TSS64;
4110#pragma pack()
4111/** Pointer to a 64-bit task segment. */
4112typedef X86TSS64 *PX86TSS64;
4113/** Pointer to a const 64-bit task segment. */
4114typedef const X86TSS64 *PCX86TSS64;
4115#ifndef VBOX_FOR_DTRACE_LIB
4116AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4117#endif
4118
4119/** @} */
4120
4121
4122/** @name Selectors.
4123 * @{
4124 */
4125
4126/**
4127 * The shift used to convert a selector from and to index an index (C).
4128 */
4129#define X86_SEL_SHIFT 3
4130
4131/**
4132 * The mask used to mask off the table indicator and RPL of an selector.
4133 */
4134#define X86_SEL_MASK 0xfff8U
4135
4136/**
4137 * The mask used to mask off the RPL of an selector.
4138 * This is suitable for checking for NULL selectors.
4139 */
4140#define X86_SEL_MASK_OFF_RPL 0xfffcU
4141
4142/**
4143 * The bit indicating that a selector is in the LDT and not in the GDT.
4144 */
4145#define X86_SEL_LDT 0x0004U
4146
4147/**
4148 * The bit mask for getting the RPL of a selector.
4149 */
4150#define X86_SEL_RPL 0x0003U
4151
4152/**
4153 * The mask covering both RPL and LDT.
4154 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4155 * checks.
4156 */
4157#define X86_SEL_RPL_LDT 0x0007U
4158
4159/** @} */
4160
4161
4162/**
4163 * x86 Exceptions/Faults/Traps.
4164 */
4165typedef enum X86XCPT
4166{
4167 /** \#DE - Divide error. */
4168 X86_XCPT_DE = 0x00,
4169 /** \#DB - Debug event (single step, DRx, ..) */
4170 X86_XCPT_DB = 0x01,
4171 /** NMI - Non-Maskable Interrupt */
4172 X86_XCPT_NMI = 0x02,
4173 /** \#BP - Breakpoint (INT3). */
4174 X86_XCPT_BP = 0x03,
4175 /** \#OF - Overflow (INTO). */
4176 X86_XCPT_OF = 0x04,
4177 /** \#BR - Bound range exceeded (BOUND). */
4178 X86_XCPT_BR = 0x05,
4179 /** \#UD - Undefined opcode. */
4180 X86_XCPT_UD = 0x06,
4181 /** \#NM - Device not available (math coprocessor device). */
4182 X86_XCPT_NM = 0x07,
4183 /** \#DF - Double fault. */
4184 X86_XCPT_DF = 0x08,
4185 /** ??? - Coprocessor segment overrun (obsolete). */
4186 X86_XCPT_CO_SEG_OVERRUN = 0x09,
4187 /** \#TS - Taskswitch (TSS). */
4188 X86_XCPT_TS = 0x0a,
4189 /** \#NP - Segment no present. */
4190 X86_XCPT_NP = 0x0b,
4191 /** \#SS - Stack segment fault. */
4192 X86_XCPT_SS = 0x0c,
4193 /** \#GP - General protection fault. */
4194 X86_XCPT_GP = 0x0d,
4195 /** \#PF - Page fault. */
4196 X86_XCPT_PF = 0x0e,
4197 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4198 /** \#MF - Math fault (FPU). */
4199 X86_XCPT_MF = 0x10,
4200 /** \#AC - Alignment check. */
4201 X86_XCPT_AC = 0x11,
4202 /** \#MC - Machine check. */
4203 X86_XCPT_MC = 0x12,
4204 /** \#XF - SIMD Floating-Pointer Exception. */
4205 X86_XCPT_XF = 0x13,
4206 /** \#VE - Virtualization Exception. */
4207 X86_XCPT_VE = 0x14,
4208 /** \#SX - Security Exception. */
4209 X86_XCPT_SX = 0x1e
4210} X86XCPT;
4211/** Pointer to a x86 exception code. */
4212typedef X86XCPT *PX86XCPT;
4213/** Pointer to a const x86 exception code. */
4214typedef const X86XCPT *PCX86XCPT;
4215/** The last valid (currently reserved) exception value. */
4216#define X86_XCPT_LAST 0x1f
4217
4218
4219/** @name Trap Error Codes
4220 * @{
4221 */
4222/** External indicator. */
4223#define X86_TRAP_ERR_EXTERNAL 1
4224/** IDT indicator. */
4225#define X86_TRAP_ERR_IDT 2
4226/** Descriptor table indicator - If set LDT, if clear GDT. */
4227#define X86_TRAP_ERR_TI 4
4228/** Mask for getting the selector. */
4229#define X86_TRAP_ERR_SEL_MASK 0xfff8
4230/** Shift for getting the selector table index (C type index). */
4231#define X86_TRAP_ERR_SEL_SHIFT 3
4232/** @} */
4233
4234
4235/** @name \#PF Trap Error Codes
4236 * @{
4237 */
4238/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4239#define X86_TRAP_PF_P RT_BIT_32(0)
4240/** Bit 1 - R/W - Read (clear) or write (set) access. */
4241#define X86_TRAP_PF_RW RT_BIT_32(1)
4242/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4243#define X86_TRAP_PF_US RT_BIT_32(2)
4244/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4245#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4246/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4247#define X86_TRAP_PF_ID RT_BIT_32(4)
4248/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4249#define X86_TRAP_PF_PK RT_BIT_32(5)
4250/** @} */
4251
4252#pragma pack(1)
4253/**
4254 * 16-bit IDTR.
4255 */
4256typedef struct X86IDTR16
4257{
4258 /** Offset. */
4259 uint16_t offSel;
4260 /** Selector. */
4261 uint16_t uSel;
4262} X86IDTR16, *PX86IDTR16;
4263#pragma pack()
4264
4265#pragma pack(1)
4266/**
4267 * 32-bit IDTR/GDTR.
4268 */
4269typedef struct X86XDTR32
4270{
4271 /** Size of the descriptor table. */
4272 uint16_t cb;
4273 /** Address of the descriptor table. */
4274#ifndef VBOX_FOR_DTRACE_LIB
4275 uint32_t uAddr;
4276#else
4277 uint16_t au16Addr[2];
4278#endif
4279} X86XDTR32, *PX86XDTR32;
4280#pragma pack()
4281
4282#pragma pack(1)
4283/**
4284 * 64-bit IDTR/GDTR.
4285 */
4286typedef struct X86XDTR64
4287{
4288 /** Size of the descriptor table. */
4289 uint16_t cb;
4290 /** Address of the descriptor table. */
4291#ifndef VBOX_FOR_DTRACE_LIB
4292 uint64_t uAddr;
4293#else
4294 uint16_t au16Addr[4];
4295#endif
4296} X86XDTR64, *PX86XDTR64;
4297#pragma pack()
4298
4299
4300/** @name ModR/M
4301 * @{ */
4302#define X86_MODRM_RM_MASK UINT8_C(0x07)
4303#define X86_MODRM_REG_MASK UINT8_C(0x38)
4304#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4305#define X86_MODRM_REG_SHIFT 3
4306#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4307#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4308#define X86_MODRM_MOD_SHIFT 6
4309#ifndef VBOX_FOR_DTRACE_LIB
4310AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
4311AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4312AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4313/** @def X86_MODRM_MAKE
4314 * @param a_Mod The mod value (0..3).
4315 * @param a_Reg The register value (0..7).
4316 * @param a_RegMem The register or memory value (0..7). */
4317# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
4318#endif
4319/** @} */
4320
4321/** @name SIB
4322 * @{ */
4323#define X86_SIB_BASE_MASK UINT8_C(0x07)
4324#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4325#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4326#define X86_SIB_INDEX_SHIFT 3
4327#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4328#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4329#define X86_SIB_SCALE_SHIFT 6
4330#ifndef VBOX_FOR_DTRACE_LIB
4331AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
4332AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4333AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4334#endif
4335/** @} */
4336
4337/** @name General register indexes
4338 * @{ */
4339#define X86_GREG_xAX 0
4340#define X86_GREG_xCX 1
4341#define X86_GREG_xDX 2
4342#define X86_GREG_xBX 3
4343#define X86_GREG_xSP 4
4344#define X86_GREG_xBP 5
4345#define X86_GREG_xSI 6
4346#define X86_GREG_xDI 7
4347#define X86_GREG_x8 8
4348#define X86_GREG_x9 9
4349#define X86_GREG_x10 10
4350#define X86_GREG_x11 11
4351#define X86_GREG_x12 12
4352#define X86_GREG_x13 13
4353#define X86_GREG_x14 14
4354#define X86_GREG_x15 15
4355/** @} */
4356
4357/** @name X86_SREG_XXX - Segment register indexes.
4358 * @{ */
4359#define X86_SREG_ES 0
4360#define X86_SREG_CS 1
4361#define X86_SREG_SS 2
4362#define X86_SREG_DS 3
4363#define X86_SREG_FS 4
4364#define X86_SREG_GS 5
4365/** @} */
4366/** Segment register count. */
4367#define X86_SREG_COUNT 6
4368
4369
4370/** @name X86_OP_XXX - Prefixes
4371 * @{ */
4372#define X86_OP_PRF_CS UINT8_C(0x2e)
4373#define X86_OP_PRF_SS UINT8_C(0x36)
4374#define X86_OP_PRF_DS UINT8_C(0x3e)
4375#define X86_OP_PRF_ES UINT8_C(0x26)
4376#define X86_OP_PRF_FS UINT8_C(0x64)
4377#define X86_OP_PRF_GS UINT8_C(0x65)
4378#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4379#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4380#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4381#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4382#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4383#define X86_OP_REX_B UINT8_C(0x41)
4384#define X86_OP_REX_X UINT8_C(0x42)
4385#define X86_OP_REX_R UINT8_C(0x44)
4386#define X86_OP_REX_W UINT8_C(0x48)
4387/** @} */
4388
4389
4390/** @} */
4391
4392#endif
4393
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