x86.h@ 71755

Last change on this file since 71755 was 71755, checked in by vboxsync, 7 years ago
VMM: Nested Hw.virt: Fix overriding SVM nested-guest PAT MSR while executing with nested-guest w/ shadow paging. Also fixes loading, validating and restoring the PAT MSR when nested-paging is used by the nested-hypervisor.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 161.1 KB

Line
1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2017 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	#ifndef VBOX_FOR_DTRACE_LIB
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104	#endif /* !VBOX_FOR_DTRACE_LIB */
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	#ifndef VBOX_FOR_DTRACE_LIB
114	/** The bitfield view. */
115	X86EFLAGSBITS Bits;
116	#endif
117	/** The 8-bit view. */
118	uint8_t au8[4];
119	/** The 16-bit view. */
120	uint16_t au16[2];
121	/** The 32-bit view. */
122	uint32_t au32[1];
123	/** The 32-bit view. */
124	uint32_t u32;
125	} X86EFLAGS;
126	/** Pointer to EFLAGS. */
127	typedef X86EFLAGS *PX86EFLAGS;
128	/** Pointer to const EFLAGS. */
129	typedef const X86EFLAGS *PCX86EFLAGS;
130
131	/**
132	* RFLAGS (32 upper bits are reserved).
133	*/
134	typedef union X86RFLAGS
135	{
136	/** The plain unsigned view. */
137	uint64_t u;
138	#ifndef VBOX_FOR_DTRACE_LIB
139	/** The bitfield view. */
140	X86EFLAGSBITS Bits;
141	#endif
142	/** The 8-bit view. */
143	uint8_t au8[8];
144	/** The 16-bit view. */
145	uint16_t au16[4];
146	/** The 32-bit view. */
147	uint32_t au32[2];
148	/** The 64-bit view. */
149	uint64_t au64[1];
150	/** The 64-bit view. */
151	uint64_t u64;
152	} X86RFLAGS;
153	/** Pointer to RFLAGS. */
154	typedef X86RFLAGS *PX86RFLAGS;
155	/** Pointer to const RFLAGS. */
156	typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159	/** @name EFLAGS
160	* @{
161	*/
162	/** Bit 0 - CF - Carry flag - Status flag. */
163	#define X86_EFL_CF RT_BIT_32(0)
164	#define X86_EFL_CF_BIT 0
165	/** Bit 1 - Reserved, reads as 1. */
166	#define X86_EFL_1 RT_BIT_32(1)
167	/** Bit 2 - PF - Parity flag - Status flag. */
168	#define X86_EFL_PF RT_BIT_32(2)
169	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
170	#define X86_EFL_AF RT_BIT_32(4)
171	#define X86_EFL_AF_BIT 4
172	/** Bit 6 - ZF - Zero flag - Status flag. */
173	#define X86_EFL_ZF RT_BIT_32(6)
174	#define X86_EFL_ZF_BIT 6
175	/** Bit 7 - SF - Signed flag - Status flag. */
176	#define X86_EFL_SF RT_BIT_32(7)
177	#define X86_EFL_SF_BIT 7
178	/** Bit 8 - TF - Trap flag - System flag. */
179	#define X86_EFL_TF RT_BIT_32(8)
180	/** Bit 9 - IF - Interrupt flag - System flag. */
181	#define X86_EFL_IF RT_BIT_32(9)
182	/** Bit 10 - DF - Direction flag - Control flag. */
183	#define X86_EFL_DF RT_BIT_32(10)
184	/** Bit 11 - OF - Overflow flag - Status flag. */
185	#define X86_EFL_OF RT_BIT_32(11)
186	#define X86_EFL_OF_BIT 11
187	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
188	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
189	/** Bit 14 - NT - Nested task flag - System flag. */
190	#define X86_EFL_NT RT_BIT_32(14)
191	/** Bit 16 - RF - Resume flag - System flag. */
192	#define X86_EFL_RF RT_BIT_32(16)
193	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
194	#define X86_EFL_VM RT_BIT_32(17)
195	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
196	#define X86_EFL_AC RT_BIT_32(18)
197	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
198	#define X86_EFL_VIF RT_BIT_32(19)
199	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
200	#define X86_EFL_VIP RT_BIT_32(20)
201	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
202	#define X86_EFL_ID RT_BIT_32(21)
203	/** All live bits. */
204	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
205	/** Read as 1 bits. */
206	#define X86_EFL_RA1_MASK RT_BIT_32(1)
207	/** IOPL shift. */
208	#define X86_EFL_IOPL_SHIFT 12
209	/** The IOPL level from the flags. */
210	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
211	/** Bits restored by popf */
212	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
213	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
214	/** Bits restored by popf */
215	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
216	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
217	/** The status bits commonly updated by arithmetic instructions. */
218	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
219	/** @} */
220
221
222	/** CPUID Feature information - ECX.
223	* CPUID query with EAX=1.
224	*/
225	#ifndef VBOX_FOR_DTRACE_LIB
226	typedef struct X86CPUIDFEATECX
227	{
228	/** Bit 0 - SSE3 - Supports SSE3 or not. */
229	unsigned u1SSE3 : 1;
230	/** Bit 1 - PCLMULQDQ. */
231	unsigned u1PCLMULQDQ : 1;
232	/** Bit 2 - DS Area 64-bit layout. */
233	unsigned u1DTE64 : 1;
234	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
235	unsigned u1Monitor : 1;
236	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
237	unsigned u1CPLDS : 1;
238	/** Bit 5 - VMX - Virtual Machine Technology. */
239	unsigned u1VMX : 1;
240	/** Bit 6 - SMX: Safer Mode Extensions. */
241	unsigned u1SMX : 1;
242	/** Bit 7 - EST - Enh. SpeedStep Tech. */
243	unsigned u1EST : 1;
244	/** Bit 8 - TM2 - Terminal Monitor 2. */
245	unsigned u1TM2 : 1;
246	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
247	unsigned u1SSSE3 : 1;
248	/** Bit 10 - CNTX-ID - L1 Context ID. */
249	unsigned u1CNTXID : 1;
250	/** Bit 11 - Reserved. */
251	unsigned u1Reserved1 : 1;
252	/** Bit 12 - FMA. */
253	unsigned u1FMA : 1;
254	/** Bit 13 - CX16 - CMPXCHG16B. */
255	unsigned u1CX16 : 1;
256	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
257	unsigned u1TPRUpdate : 1;
258	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
259	unsigned u1PDCM : 1;
260	/** Bit 16 - Reserved. */
261	unsigned u1Reserved2 : 1;
262	/** Bit 17 - PCID - Process-context identifiers. */
263	unsigned u1PCID : 1;
264	/** Bit 18 - Direct Cache Access. */
265	unsigned u1DCA : 1;
266	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
267	unsigned u1SSE4_1 : 1;
268	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
269	unsigned u1SSE4_2 : 1;
270	/** Bit 21 - x2APIC. */
271	unsigned u1x2APIC : 1;
272	/** Bit 22 - MOVBE - Supports MOVBE. */
273	unsigned u1MOVBE : 1;
274	/** Bit 23 - POPCNT - Supports POPCNT. */
275	unsigned u1POPCNT : 1;
276	/** Bit 24 - TSC-Deadline. */
277	unsigned u1TSCDEADLINE : 1;
278	/** Bit 25 - AES. */
279	unsigned u1AES : 1;
280	/** Bit 26 - XSAVE - Supports XSAVE. */
281	unsigned u1XSAVE : 1;
282	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
283	unsigned u1OSXSAVE : 1;
284	/** Bit 28 - AVX - Supports AVX instruction extensions. */
285	unsigned u1AVX : 1;
286	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
287	unsigned u1F16C : 1;
288	/** Bit 30 - RDRAND - Supports RDRAND. */
289	unsigned u1RDRAND : 1;
290	/** Bit 31 - Hypervisor present (we're a guest). */
291	unsigned u1HVP : 1;
292	} X86CPUIDFEATECX;
293	#else /* VBOX_FOR_DTRACE_LIB */
294	typedef uint32_t X86CPUIDFEATECX;
295	#endif /* VBOX_FOR_DTRACE_LIB */
296	/** Pointer to CPUID Feature Information - ECX. */
297	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
298	/** Pointer to const CPUID Feature Information - ECX. */
299	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
300
301
302	/** CPUID Feature Information - EDX.
303	* CPUID query with EAX=1.
304	*/
305	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
306	typedef struct X86CPUIDFEATEDX
307	{
308	/** Bit 0 - FPU - x87 FPU on Chip. */
309	unsigned u1FPU : 1;
310	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
311	unsigned u1VME : 1;
312	/** Bit 2 - DE - Debugging extensions. */
313	unsigned u1DE : 1;
314	/** Bit 3 - PSE - Page Size Extension. */
315	unsigned u1PSE : 1;
316	/** Bit 4 - TSC - Time Stamp Counter. */
317	unsigned u1TSC : 1;
318	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
319	unsigned u1MSR : 1;
320	/** Bit 6 - PAE - Physical Address Extension. */
321	unsigned u1PAE : 1;
322	/** Bit 7 - MCE - Machine Check Exception. */
323	unsigned u1MCE : 1;
324	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
325	unsigned u1CX8 : 1;
326	/** Bit 9 - APIC - APIC On-Chip. */
327	unsigned u1APIC : 1;
328	/** Bit 10 - Reserved. */
329	unsigned u1Reserved1 : 1;
330	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
331	unsigned u1SEP : 1;
332	/** Bit 12 - MTRR - Memory Type Range Registers. */
333	unsigned u1MTRR : 1;
334	/** Bit 13 - PGE - PTE Global Bit. */
335	unsigned u1PGE : 1;
336	/** Bit 14 - MCA - Machine Check Architecture. */
337	unsigned u1MCA : 1;
338	/** Bit 15 - CMOV - Conditional Move Instructions. */
339	unsigned u1CMOV : 1;
340	/** Bit 16 - PAT - Page Attribute Table. */
341	unsigned u1PAT : 1;
342	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
343	unsigned u1PSE36 : 1;
344	/** Bit 18 - PSN - Processor Serial Number. */
345	unsigned u1PSN : 1;
346	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
347	unsigned u1CLFSH : 1;
348	/** Bit 20 - Reserved. */
349	unsigned u1Reserved2 : 1;
350	/** Bit 21 - DS - Debug Store. */
351	unsigned u1DS : 1;
352	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
353	unsigned u1ACPI : 1;
354	/** Bit 23 - MMX - Intel MMX 'Technology'. */
355	unsigned u1MMX : 1;
356	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
357	unsigned u1FXSR : 1;
358	/** Bit 25 - SSE - SSE Support. */
359	unsigned u1SSE : 1;
360	/** Bit 26 - SSE2 - SSE2 Support. */
361	unsigned u1SSE2 : 1;
362	/** Bit 27 - SS - Self Snoop. */
363	unsigned u1SS : 1;
364	/** Bit 28 - HTT - Hyper-Threading Technology. */
365	unsigned u1HTT : 1;
366	/** Bit 29 - TM - Thermal Monitor. */
367	unsigned u1TM : 1;
368	/** Bit 30 - Reserved - . */
369	unsigned u1Reserved3 : 1;
370	/** Bit 31 - PBE - Pending Break Enabled. */
371	unsigned u1PBE : 1;
372	} X86CPUIDFEATEDX;
373	#else /* VBOX_FOR_DTRACE_LIB */
374	typedef uint32_t X86CPUIDFEATEDX;
375	#endif /* VBOX_FOR_DTRACE_LIB */
376	/** Pointer to CPUID Feature Information - EDX. */
377	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
378	/** Pointer to const CPUID Feature Information - EDX. */
379	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
380
381	/** @name CPUID Vendor information.
382	* CPUID query with EAX=0.
383	* @{
384	*/
385	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
386	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
387	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
388
389	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
390	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
391	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
392
393	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
394	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
395	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
396	/** @} */
397
398
399	/** @name CPUID Feature information.
400	* CPUID query with EAX=1.
401	* @{
402	*/
403	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
404	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
405	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
406	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
407	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
408	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
409	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
410	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
411	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
412	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
413	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
414	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
415	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
416	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
417	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
418	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
419	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
420	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
421	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
422	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
423	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
424	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
425	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
426	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
427	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
428	/** ECX Bit 12 - FMA. */
429	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
430	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
431	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
432	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
433	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
434	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
435	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
436	/** ECX Bit 17 - PCID - Process-context identifiers. */
437	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
438	/** ECX Bit 18 - DCA - Direct Cache Access. */
439	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
440	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
441	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
442	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
443	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
444	/** ECX Bit 21 - x2APIC support. */
445	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
446	/** ECX Bit 22 - MOVBE instruction. */
447	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
448	/** ECX Bit 23 - POPCNT instruction. */
449	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
450	/** ECX Bir 24 - TSC-Deadline. */
451	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
452	/** ECX Bit 25 - AES instructions. */
453	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
454	/** ECX Bit 26 - XSAVE instruction. */
455	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
456	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
457	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
458	/** ECX Bit 28 - AVX. */
459	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
460	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
461	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
462	/** ECX Bit 30 - RDRAND instruction. */
463	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
464	/** ECX Bit 31 - Hypervisor Present (software only). */
465	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
466
467
468	/** Bit 0 - FPU - x87 FPU on Chip. */
469	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
470	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
471	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
472	/** Bit 2 - DE - Debugging extensions. */
473	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
474	/** Bit 3 - PSE - Page Size Extension. */
475	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
476	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
477	/** Bit 4 - TSC - Time Stamp Counter. */
478	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
479	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
480	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
481	/** Bit 6 - PAE - Physical Address Extension. */
482	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
483	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
484	/** Bit 7 - MCE - Machine Check Exception. */
485	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
486	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
487	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
488	/** Bit 9 - APIC - APIC On-Chip. */
489	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
490	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
491	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
492	/** Bit 12 - MTRR - Memory Type Range Registers. */
493	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
494	/** Bit 13 - PGE - PTE Global Bit. */
495	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
496	/** Bit 14 - MCA - Machine Check Architecture. */
497	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
498	/** Bit 15 - CMOV - Conditional Move Instructions. */
499	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
500	/** Bit 16 - PAT - Page Attribute Table. */
501	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
502	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
503	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
504	/** Bit 18 - PSN - Processor Serial Number. */
505	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
506	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
507	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
508	/** Bit 21 - DS - Debug Store. */
509	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
510	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
511	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
512	/** Bit 23 - MMX - Intel MMX Technology. */
513	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
514	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
515	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
516	/** Bit 25 - SSE - SSE Support. */
517	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
518	/** Bit 26 - SSE2 - SSE2 Support. */
519	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
520	/** Bit 27 - SS - Self Snoop. */
521	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
522	/** Bit 28 - HTT - Hyper-Threading Technology. */
523	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
524	/** Bit 29 - TM - Therm. Monitor. */
525	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
526	/** Bit 31 - PBE - Pending Break Enabled. */
527	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
528	/** @} */
529
530	/** @name CPUID mwait/monitor information.
531	* CPUID query with EAX=5.
532	* @{
533	*/
534	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
535	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
536	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
537	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
538	/** @} */
539
540
541	/** @name CPUID Structured Extended Feature information.
542	* CPUID query with EAX=7.
543	* @{
544	*/
545	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
546	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
547	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
548	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
549	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
550	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
551	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
552	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
553	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
554	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
555	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
556	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
557	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
558	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
559	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
560	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
561	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
562	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
563	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
564	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
565	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
566	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
567	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
568	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
569	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
570	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
571	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
572	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
573	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
574	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
575	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
576	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
577	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
578	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
579	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
580	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
581	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
582	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
583	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
584	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
585	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
586	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
587	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
588	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
589	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
590	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
591	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
592	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
593	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
594	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
595	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
596	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
597
598	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
599	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
600	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
601	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
602	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
603	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
604	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
605	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
606	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
607	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
608	/** ECX Bit 22 - RDPID - Support pread process ID. */
609	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
610	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
611	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
612
613	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
614	* IBPB command in IA32_PRED_CMD. */
615	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
616	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
617	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
618
619	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
620	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
621
622	/** @} */
623
624
625	/** @name CPUID Extended Feature information.
626	* CPUID query with EAX=0x80000001.
627	* @{
628	*/
629	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
630	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
631
632	/** EDX Bit 11 - SYSCALL/SYSRET. */
633	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
634	/** EDX Bit 20 - No-Execute/Execute-Disable. */
635	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
636	/** EDX Bit 26 - 1 GB large page. */
637	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
638	/** EDX Bit 27 - RDTSCP. */
639	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
640	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
641	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
642	/** @}*/
643
644	/** @name CPUID AMD Feature information.
645	* CPUID query with EAX=0x80000001.
646	* @{
647	*/
648	/** Bit 0 - FPU - x87 FPU on Chip. */
649	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
650	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
651	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
652	/** Bit 2 - DE - Debugging extensions. */
653	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
654	/** Bit 3 - PSE - Page Size Extension. */
655	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
656	/** Bit 4 - TSC - Time Stamp Counter. */
657	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
658	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
659	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
660	/** Bit 6 - PAE - Physical Address Extension. */
661	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
662	/** Bit 7 - MCE - Machine Check Exception. */
663	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
664	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
665	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
666	/** Bit 9 - APIC - APIC On-Chip. */
667	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
668	/** Bit 12 - MTRR - Memory Type Range Registers. */
669	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
670	/** Bit 13 - PGE - PTE Global Bit. */
671	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
672	/** Bit 14 - MCA - Machine Check Architecture. */
673	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
674	/** Bit 15 - CMOV - Conditional Move Instructions. */
675	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
676	/** Bit 16 - PAT - Page Attribute Table. */
677	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
678	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
679	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
680	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
681	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
682	/** Bit 23 - MMX - Intel MMX Technology. */
683	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
684	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
685	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
686	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
687	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
688	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
689	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
690	/** Bit 31 - 3DNOW - AMD 3DNow. */
691	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
692
693	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
694	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
695	/** Bit 2 - SVM - AMD VM extensions. */
696	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
697	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
698	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
699	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
700	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
701	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
702	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
703	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
704	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
705	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
706	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
707	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
708	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
709	/** Bit 9 - OSVW - AMD OS visible workaround. */
710	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
711	/** Bit 10 - IBS - Instruct based sampling. */
712	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
713	/** Bit 11 - XOP - Extended operation support (see APM6). */
714	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
715	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
716	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
717	/** Bit 13 - WDT - AMD Watchdog timer support. */
718	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
719	/** Bit 15 - LWP - Lightweight profiling support. */
720	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
721	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
722	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
723	/** Bit 19 - NodeId - Indicates support for
724	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
725	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
726	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
727	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
728	/** Bit 22 - TopologyExtensions - . */
729	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
730	/** @} */
731
732
733	/** @name CPUID AMD Feature information.
734	* CPUID query with EAX=0x80000007.
735	* @{
736	*/
737	/** Bit 0 - TS - Temperature Sensor. */
738	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
739	/** Bit 1 - FID - Frequency ID Control. */
740	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
741	/** Bit 2 - VID - Voltage ID Control. */
742	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
743	/** Bit 3 - TTP - THERMTRIP. */
744	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
745	/** Bit 4 - TM - Hardware Thermal Control. */
746	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
747	/** Bit 5 - STC - Software Thermal Control. */
748	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
749	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
750	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
751	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
752	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
753	/** Bit 8 - TSCINVAR - TSC Invariant. */
754	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
755	/** Bit 9 - CPB - TSC Invariant. */
756	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
757	/** Bit 10 - EffFreqRO - MPERF/APERF. */
758	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
759	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
760	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
761	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
762	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
763	/** @} */
764
765
766	/** @name CPUID AMD extended feature extensions ID (EBX).
767	* CPUID query with EAX=0x80000008.
768	* @{
769	*/
770	/** Bit 0 - CLZERO - Clear zero instruction. */
771	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
772	/** Bit 1 - IRPerf - Instructions retired count support. */
773	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
774	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
775	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
776	/* AMD pipeline length: 9 feature bits ;-) */
777	/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
778	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
779	/** @} */
780
781
782	/** @name CPUID AMD SVM Feature information.
783	* CPUID query with EAX=0x8000000a.
784	* @{
785	*/
786	/** Bit 0 - NP - Nested Paging supported. */
787	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
788	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
789	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
790	/** Bit 2 - SVML - SVM locking bit supported. */
791	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
792	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
793	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
794	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
795	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
796	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
797	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
798	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
799	* VMCB.TLB_Control is supported. */
800	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
801	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
802	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
803	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
804	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
805	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
806	* intercept filter cycle count threshold. */
807	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
808	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
809	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
810	/** Bit 15 - V_VMSAVE_VMLOAD - Supports virtualized VMSAVE/VMLOAD. */
811	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
812	/** Bit 16 - V_VMSAVE_VMLOAD - Supports virtualized GIF. */
813	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
814	/** @} */
815
816
817	/** @name CR0
818	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
819	* reserved flags.
820	* @{ */
821	/** Bit 0 - PE - Protection Enabled */
822	#define X86_CR0_PE RT_BIT_32(0)
823	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
824	/** Bit 1 - MP - Monitor Coprocessor */
825	#define X86_CR0_MP RT_BIT_32(1)
826	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
827	/** Bit 2 - EM - Emulation. */
828	#define X86_CR0_EM RT_BIT_32(2)
829	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
830	/** Bit 3 - TS - Task Switch. */
831	#define X86_CR0_TS RT_BIT_32(3)
832	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
833	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
834	#define X86_CR0_ET RT_BIT_32(4)
835	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
836	/** Bit 5 - NE - Numeric error (486+). */
837	#define X86_CR0_NE RT_BIT_32(5)
838	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
839	/** Bit 16 - WP - Write Protect (486+). */
840	#define X86_CR0_WP RT_BIT_32(16)
841	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
842	/** Bit 18 - AM - Alignment Mask (486+). */
843	#define X86_CR0_AM RT_BIT_32(18)
844	#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
845	/** Bit 29 - NW - Not Write-though (486+). */
846	#define X86_CR0_NW RT_BIT_32(29)
847	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
848	/** Bit 30 - WP - Cache Disable (486+). */
849	#define X86_CR0_CD RT_BIT_32(30)
850	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
851	/** Bit 31 - PG - Paging. */
852	#define X86_CR0_PG RT_BIT_32(31)
853	#define X86_CR0_PAGING RT_BIT_32(31)
854	/** @} */
855
856
857	/** @name CR3
858	* @{ */
859	/** Bit 3 - PWT - Page-level Writes Transparent. */
860	#define X86_CR3_PWT RT_BIT_32(3)
861	/** Bit 4 - PCD - Page-level Cache Disable. */
862	#define X86_CR3_PCD RT_BIT_32(4)
863	/** Bits 12-31 - - Page directory page number. */
864	#define X86_CR3_PAGE_MASK (0xfffff000)
865	/** Bits 5-31 - - PAE Page directory page number. */
866	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
867	/** Bits 12-51 - - AMD64 Page directory page number. */
868	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
869	/** @} */
870
871
872	/** @name CR4
873	* @{ */
874	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
875	#define X86_CR4_VME RT_BIT_32(0)
876	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
877	#define X86_CR4_PVI RT_BIT_32(1)
878	/** Bit 2 - TSD - Time Stamp Disable. */
879	#define X86_CR4_TSD RT_BIT_32(2)
880	/** Bit 3 - DE - Debugging Extensions. */
881	#define X86_CR4_DE RT_BIT_32(3)
882	/** Bit 4 - PSE - Page Size Extension. */
883	#define X86_CR4_PSE RT_BIT_32(4)
884	/** Bit 5 - PAE - Physical Address Extension. */
885	#define X86_CR4_PAE RT_BIT_32(5)
886	/** Bit 6 - MCE - Machine-Check Enable. */
887	#define X86_CR4_MCE RT_BIT_32(6)
888	/** Bit 7 - PGE - Page Global Enable. */
889	#define X86_CR4_PGE RT_BIT_32(7)
890	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
891	#define X86_CR4_PCE RT_BIT_32(8)
892	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
893	#define X86_CR4_OSFXSR RT_BIT_32(9)
894	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
895	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
896	/** Bit 13 - VMXE - VMX mode is enabled. */
897	#define X86_CR4_VMXE RT_BIT_32(13)
898	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
899	#define X86_CR4_SMXE RT_BIT_32(14)
900	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
901	#define X86_CR4_FSGSBASE RT_BIT_32(16)
902	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
903	#define X86_CR4_PCIDE RT_BIT_32(17)
904	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
905	* extended states. */
906	#define X86_CR4_OSXSAVE RT_BIT_32(18)
907	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
908	#define X86_CR4_SMEP RT_BIT_32(20)
909	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
910	#define X86_CR4_SMAP RT_BIT_32(21)
911	/** Bit 22 - PKE - Protection Key Enable. */
912	#define X86_CR4_PKE RT_BIT_32(22)
913	/** @} */
914
915
916	/** @name DR6
917	* @{ */
918	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
919	#define X86_DR6_B0 RT_BIT_32(0)
920	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
921	#define X86_DR6_B1 RT_BIT_32(1)
922	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
923	#define X86_DR6_B2 RT_BIT_32(2)
924	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
925	#define X86_DR6_B3 RT_BIT_32(3)
926	/** Mask of all the Bx bits. */
927	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
928	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
929	#define X86_DR6_BD RT_BIT_32(13)
930	/** Bit 14 - BS - Single step */
931	#define X86_DR6_BS RT_BIT_32(14)
932	/** Bit 15 - BT - Task switch. (TSS T bit.) */
933	#define X86_DR6_BT RT_BIT_32(15)
934	/** Value of DR6 after powerup/reset. */
935	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
936	/** Bits which must be 1s in DR6. */
937	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
938	/** Bits which must be 0s in DR6. */
939	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
940	/** Bits which must be 0s on writes to DR6. */
941	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
942	/** @} */
943
944	/** Get the DR6.Bx bit for a the given breakpoint. */
945	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
946
947
948	/** @name DR7
949	* @{ */
950	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
951	#define X86_DR7_L0 RT_BIT_32(0)
952	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
953	#define X86_DR7_G0 RT_BIT_32(1)
954	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
955	#define X86_DR7_L1 RT_BIT_32(2)
956	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
957	#define X86_DR7_G1 RT_BIT_32(3)
958	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
959	#define X86_DR7_L2 RT_BIT_32(4)
960	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
961	#define X86_DR7_G2 RT_BIT_32(5)
962	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
963	#define X86_DR7_L3 RT_BIT_32(6)
964	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
965	#define X86_DR7_G3 RT_BIT_32(7)
966	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
967	#define X86_DR7_LE RT_BIT_32(8)
968	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
969	#define X86_DR7_GE RT_BIT_32(9)
970
971	/** L0, L1, L2, and L3. */
972	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
973	/** L0, L1, L2, and L3. */
974	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
975
976	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
977	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
978	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
979	* instruction is executed.
980	* @see http://www.rcollins.org/secrets/DR7.html */
981	#define X86_DR7_ICE_IR RT_BIT_32(12)
982	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
983	* any DR register is accessed. */
984	#define X86_DR7_GD RT_BIT_32(13)
985	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
986	* Pentium. */
987	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
988	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
989	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
990	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
991	#define X86_DR7_RW0_MASK (3 << 16)
992	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
993	#define X86_DR7_LEN0_MASK (3 << 18)
994	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
995	#define X86_DR7_RW1_MASK (3 << 20)
996	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
997	#define X86_DR7_LEN1_MASK (3 << 22)
998	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
999	#define X86_DR7_RW2_MASK (3 << 24)
1000	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1001	#define X86_DR7_LEN2_MASK (3 << 26)
1002	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1003	#define X86_DR7_RW3_MASK (3 << 28)
1004	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1005	#define X86_DR7_LEN3_MASK (3 << 30)
1006
1007	/** Bits which reads as 1s. */
1008	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1009	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1010	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1011	/** Bits which must be 0s when writing to DR7. */
1012	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1013
1014	/** Calcs the L bit of Nth breakpoint.
1015	* @param iBp The breakpoint number [0..3].
1016	*/
1017	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1018
1019	/** Calcs the G bit of Nth breakpoint.
1020	* @param iBp The breakpoint number [0..3].
1021	*/
1022	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1023
1024	/** Calcs the L and G bits of Nth breakpoint.
1025	* @param iBp The breakpoint number [0..3].
1026	*/
1027	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1028
1029	/** @name Read/Write values.
1030	* @{ */
1031	/** Break on instruction fetch only. */
1032	#define X86_DR7_RW_EO 0U
1033	/** Break on write only. */
1034	#define X86_DR7_RW_WO 1U
1035	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1036	#define X86_DR7_RW_IO 2U
1037	/** Break on read or write (but not instruction fetches). */
1038	#define X86_DR7_RW_RW 3U
1039	/** @} */
1040
1041	/** Shifts a X86_DR7_RW_* value to its right place.
1042	* @param iBp The breakpoint number [0..3].
1043	* @param fRw One of the X86_DR7_RW_* value.
1044	*/
1045	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1046
1047	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1048	* one of the X86_DR7_RW_XXX constants).
1049	*
1050	* @returns X86_DR7_RW_XXX
1051	* @param uDR7 DR7 value
1052	* @param iBp The breakpoint number [0..3].
1053	*/
1054	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1055
1056	/** R/W0, R/W1, R/W2, and R/W3. */
1057	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1058
1059	#ifndef VBOX_FOR_DTRACE_LIB
1060	/** Checks if there are any I/O breakpoint types configured in the RW
1061	* registers. Does NOT check if these are enabled, sorry. */
1062	# define X86_DR7_ANY_RW_IO(uDR7) \
1063	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1064	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1065	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1066	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1067	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1068	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1069	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1070	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1071	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1072	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1073	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1074	#endif /* !VBOX_FOR_DTRACE_LIB */
1075
1076	/** @name Length values.
1077	* @{ */
1078	#define X86_DR7_LEN_BYTE 0U
1079	#define X86_DR7_LEN_WORD 1U
1080	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
1081	#define X86_DR7_LEN_DWORD 3U
1082	/** @} */
1083
1084	/** Shifts a X86_DR7_LEN_* value to its right place.
1085	* @param iBp The breakpoint number [0..3].
1086	* @param cb One of the X86_DR7_LEN_* values.
1087	*/
1088	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1089
1090	/** Fetch the breakpoint length bits from the DR7 value.
1091	* @param uDR7 DR7 value
1092	* @param iBp The breakpoint number [0..3].
1093	*/
1094	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1095
1096	/** Mask used to check if any breakpoints are enabled. */
1097	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1098
1099	/** LEN0, LEN1, LEN2, and LEN3. */
1100	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1101	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1102	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1103
1104	/** Value of DR7 after powerup/reset. */
1105	#define X86_DR7_INIT_VAL 0x400
1106	/** @} */
1107
1108
1109	/** @name Machine Specific Registers
1110	* @{
1111	*/
1112	/** Machine check address register (P5). */
1113	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1114	/** Machine check type register (P5). */
1115	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1116	/** Time Stamp Counter. */
1117	#define MSR_IA32_TSC 0x10
1118	#define MSR_IA32_CESR UINT32_C(0x00000011)
1119	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1120	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1121
1122	#define MSR_IA32_PLATFORM_ID 0x17
1123
1124	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1125	# define MSR_IA32_APICBASE 0x1b
1126	/** Local APIC enabled. */
1127	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1128	/** X2APIC enabled (requires the EN bit to be set). */
1129	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1130	/** The processor is the boot strap processor (BSP). */
1131	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1132	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1133	* width. */
1134	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1135	/** The default physical base address of the APIC. */
1136	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1137	/** Gets the physical base address from the MSR. */
1138	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1139	#endif
1140
1141	/** Undocumented intel MSR for reporting thread and core counts.
1142	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1143	* first 16 bits is the thread count. The next 16 bits the core count, except
1144	* on Westmere where it seems it's only the next 4 bits for some reason. */
1145	#define MSR_CORE_THREAD_COUNT 0x35
1146
1147	/** CPU Feature control. */
1148	#define MSR_IA32_FEATURE_CONTROL 0x3A
1149	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_32(0)
1150	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_32(1)
1151	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_32(2)
1152
1153	/** Per-processor TSC adjust MSR. */
1154	#define MSR_IA32_TSC_ADJUST 0x3B
1155
1156	/** Spectre control register.
1157	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1158	#define MSR_IA32_SPEC_CTRL 0x48
1159	/** IBRS - Indirect branch restricted speculation. */
1160	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1161	/** STIBP - Single thread indirect branch predictors. */
1162	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1163
1164	/** Prediction command register.
1165	* Write only, logical processor scope, no state since write only. */
1166	#define MSR_IA32_PRED_CMD 0x49
1167	/** IBPB - Indirect branch prediction barrie when written as 1. */
1168	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1169
1170	/** BIOS update trigger (microcode update). */
1171	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1172
1173	/** BIOS update signature (microcode). */
1174	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1175
1176	/** SMM monitor control. */
1177	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1178
1179	/** General performance counter no. 0. */
1180	#define MSR_IA32_PMC0 0xC1
1181	/** General performance counter no. 1. */
1182	#define MSR_IA32_PMC1 0xC2
1183	/** General performance counter no. 2. */
1184	#define MSR_IA32_PMC2 0xC3
1185	/** General performance counter no. 3. */
1186	#define MSR_IA32_PMC3 0xC4
1187
1188	/** Nehalem power control. */
1189	#define MSR_IA32_PLATFORM_INFO 0xCE
1190
1191	/** Get FSB clock status (Intel-specific). */
1192	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1193
1194	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1195	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1196
1197	/** C0 Maximum Frequency Clock Count */
1198	#define MSR_IA32_MPERF 0xE7
1199	/** C0 Actual Frequency Clock Count */
1200	#define MSR_IA32_APERF 0xE8
1201
1202	/** MTRR Capabilities. */
1203	#define MSR_IA32_MTRR_CAP 0xFE
1204
1205	/** Architecture capabilities (bugfixes).
1206	* @note May move */
1207	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1208	/** CPU is no subject to spectre problems. */
1209	#define MSR_IA32_ARCH_CAP_F_SPECTRE_FIX RT_BIT_32(0)
1210	/** CPU has better IBRS and you can leave it on all the time. */
1211	#define MSR_IA32_ARCH_CAP_F_BETTER_IBRS RT_BIT_32(1)
1212
1213	/** Cache control/info. */
1214	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1215
1216	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1217	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1218	* R0 SS == CS + 8
1219	* R3 CS == CS + 16
1220	* R3 SS == CS + 24
1221	*/
1222	#define MSR_IA32_SYSENTER_CS 0x174
1223	/** SYSENTER_ESP - the R0 ESP. */
1224	#define MSR_IA32_SYSENTER_ESP 0x175
1225	/** SYSENTER_EIP - the R0 EIP. */
1226	#define MSR_IA32_SYSENTER_EIP 0x176
1227	#endif
1228
1229	/** Machine Check Global Capabilities Register. */
1230	#define MSR_IA32_MCG_CAP 0x179
1231	/** Machine Check Global Status Register. */
1232	#define MSR_IA32_MCG_STATUS 0x17A
1233	/** Machine Check Global Control Register. */
1234	#define MSR_IA32_MCG_CTRL 0x17B
1235
1236	/** Page Attribute Table. */
1237	#define MSR_IA32_CR_PAT 0x277
1238	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1239	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1240	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1241
1242	/** Performance counter MSRs. (Intel only) */
1243	#define MSR_IA32_PERFEVTSEL0 0x186
1244	#define MSR_IA32_PERFEVTSEL1 0x187
1245	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1246	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1247	* holds a ratio that Apple takes for TSC granularity.
1248	*
1249	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1250	#define MSR_FLEX_RATIO 0x194
1251	/** Performance state value and starting with Intel core more.
1252	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1253	#define MSR_IA32_PERF_STATUS 0x198
1254	#define MSR_IA32_PERF_CTL 0x199
1255	#define MSR_IA32_THERM_STATUS 0x19c
1256
1257	/** Enable misc. processor features (R/W). */
1258	#define MSR_IA32_MISC_ENABLE 0x1A0
1259	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1260	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1261	/** Automatic Thermal Control Circuit Enable (R/W). */
1262	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1263	/** Performance Monitoring Available (R). */
1264	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1265	/** Branch Trace Storage Unavailable (R/O). */
1266	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1267	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1268	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1269	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1270	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1271	/** If MONITOR/MWAIT is supported (R/W). */
1272	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1273	/** Limit CPUID Maxval to 3 leafs (R/W). */
1274	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1275	/** When set to 1, xTPR messages are disabled (R/W). */
1276	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1277	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1278	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1279
1280	/** Trace/Profile Resource Control (R/W) */
1281	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1282	/** Last branch record. */
1283	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1284	/** Branch trace flag (single step on branches). */
1285	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1286	/** Performance monitoring pin control (AMD only). */
1287	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1288	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1289	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1290	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1291	/** Trace message enable (Intel only). */
1292	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1293	/** Branch trace store (Intel only). */
1294	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1295	/** Branch trace interrupt (Intel only). */
1296	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1297	/** Branch trace off in privileged code (Intel only). */
1298	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1299	/** Branch trace off in user code (Intel only). */
1300	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1301	/** Freeze LBR on PMI flag (Intel only). */
1302	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1303	/** Freeze PERFMON on PMI flag (Intel only). */
1304	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1305	/** Freeze while SMM enabled (Intel only). */
1306	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1307	/** Advanced debugging of RTM regions (Intel only). */
1308	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1309
1310	/** The number (0..3 or 0..15) of the last branch record register on P4 and
1311	* related Xeons. */
1312	#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1313	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1314	* @{ */
1315	#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1316	#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1317	#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1318	#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1319	/** @} */
1320
1321
1322	#define IA32_MTRR_PHYSBASE0 0x200
1323	#define IA32_MTRR_PHYSMASK0 0x201
1324	#define IA32_MTRR_PHYSBASE1 0x202
1325	#define IA32_MTRR_PHYSMASK1 0x203
1326	#define IA32_MTRR_PHYSBASE2 0x204
1327	#define IA32_MTRR_PHYSMASK2 0x205
1328	#define IA32_MTRR_PHYSBASE3 0x206
1329	#define IA32_MTRR_PHYSMASK3 0x207
1330	#define IA32_MTRR_PHYSBASE4 0x208
1331	#define IA32_MTRR_PHYSMASK4 0x209
1332	#define IA32_MTRR_PHYSBASE5 0x20a
1333	#define IA32_MTRR_PHYSMASK5 0x20b
1334	#define IA32_MTRR_PHYSBASE6 0x20c
1335	#define IA32_MTRR_PHYSMASK6 0x20d
1336	#define IA32_MTRR_PHYSBASE7 0x20e
1337	#define IA32_MTRR_PHYSMASK7 0x20f
1338	#define IA32_MTRR_PHYSBASE8 0x210
1339	#define IA32_MTRR_PHYSMASK8 0x211
1340	#define IA32_MTRR_PHYSBASE9 0x212
1341	#define IA32_MTRR_PHYSMASK9 0x213
1342
1343	/** Fixed range MTRRs.
1344	* @{ */
1345	#define IA32_MTRR_FIX64K_00000 0x250
1346	#define IA32_MTRR_FIX16K_80000 0x258
1347	#define IA32_MTRR_FIX16K_A0000 0x259
1348	#define IA32_MTRR_FIX4K_C0000 0x268
1349	#define IA32_MTRR_FIX4K_C8000 0x269
1350	#define IA32_MTRR_FIX4K_D0000 0x26a
1351	#define IA32_MTRR_FIX4K_D8000 0x26b
1352	#define IA32_MTRR_FIX4K_E0000 0x26c
1353	#define IA32_MTRR_FIX4K_E8000 0x26d
1354	#define IA32_MTRR_FIX4K_F0000 0x26e
1355	#define IA32_MTRR_FIX4K_F8000 0x26f
1356	/** @} */
1357
1358	/** MTRR Default Range. */
1359	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1360
1361	/** Global performance counter control facilities (Intel only). */
1362	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1363	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1364	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1365
1366	/** Precise Event Based sampling (Intel only). */
1367	#define MSR_IA32_PEBS_ENABLE 0x3F1
1368
1369	#define MSR_IA32_MC0_CTL 0x400
1370	#define MSR_IA32_MC0_STATUS 0x401
1371
1372	/** Basic VMX information. */
1373	#define MSR_IA32_VMX_BASIC_INFO 0x480
1374	/** Allowed settings for pin-based VM execution controls */
1375	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1376	/** Allowed settings for proc-based VM execution controls */
1377	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1378	/** Allowed settings for the VMX exit controls. */
1379	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1380	/** Allowed settings for the VMX entry controls. */
1381	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1382	/** Misc VMX info. */
1383	#define MSR_IA32_VMX_MISC 0x485
1384	/** Fixed cleared bits in CR0. */
1385	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1386	/** Fixed set bits in CR0. */
1387	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1388	/** Fixed cleared bits in CR4. */
1389	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1390	/** Fixed set bits in CR4. */
1391	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1392	/** Information for enumerating fields in the VMCS. */
1393	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1394	/** Allowed settings for the VM-functions controls. */
1395	#define MSR_IA32_VMX_VMFUNC 0x491
1396	/** Allowed settings for secondary proc-based VM execution controls */
1397	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1398	/** EPT capabilities. */
1399	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1400	/** Allowed settings of all pin-based VM execution controls. */
1401	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1402	/** Allowed settings of all proc-based VM execution controls. */
1403	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1404	/** Allowed settings of all VMX exit controls. */
1405	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1406	/** Allowed settings of all VMX entry controls. */
1407	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1408
1409	/** DS Save Area (R/W). */
1410	#define MSR_IA32_DS_AREA 0x600
1411	/** Running Average Power Limit (RAPL) power units. */
1412	#define MSR_RAPL_POWER_UNIT 0x606
1413
1414	/** X2APIC MSR range start. */
1415	#define MSR_IA32_X2APIC_START 0x800
1416	/** X2APIC MSR - APIC ID Register. */
1417	#define MSR_IA32_X2APIC_ID 0x802
1418	/** X2APIC MSR - APIC Version Register. */
1419	#define MSR_IA32_X2APIC_VERSION 0x803
1420	/** X2APIC MSR - Task Priority Register. */
1421	#define MSR_IA32_X2APIC_TPR 0x808
1422	/** X2APIC MSR - Processor Priority register. */
1423	#define MSR_IA32_X2APIC_PPR 0x80A
1424	/** X2APIC MSR - End Of Interrupt register. */
1425	#define MSR_IA32_X2APIC_EOI 0x80B
1426	/** X2APIC MSR - Logical Destination Register. */
1427	#define MSR_IA32_X2APIC_LDR 0x80D
1428	/** X2APIC MSR - Spurious Interrupt Vector Register. */
1429	#define MSR_IA32_X2APIC_SVR 0x80F
1430	/** X2APIC MSR - In-service Register (bits 31:0). */
1431	#define MSR_IA32_X2APIC_ISR0 0x810
1432	/** X2APIC MSR - In-service Register (bits 63:32). */
1433	#define MSR_IA32_X2APIC_ISR1 0x811
1434	/** X2APIC MSR - In-service Register (bits 95:64). */
1435	#define MSR_IA32_X2APIC_ISR2 0x812
1436	/** X2APIC MSR - In-service Register (bits 127:96). */
1437	#define MSR_IA32_X2APIC_ISR3 0x813
1438	/** X2APIC MSR - In-service Register (bits 159:128). */
1439	#define MSR_IA32_X2APIC_ISR4 0x814
1440	/** X2APIC MSR - In-service Register (bits 191:160). */
1441	#define MSR_IA32_X2APIC_ISR5 0x815
1442	/** X2APIC MSR - In-service Register (bits 223:192). */
1443	#define MSR_IA32_X2APIC_ISR6 0x816
1444	/** X2APIC MSR - In-service Register (bits 255:224). */
1445	#define MSR_IA32_X2APIC_ISR7 0x817
1446	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1447	#define MSR_IA32_X2APIC_TMR0 0x818
1448	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1449	#define MSR_IA32_X2APIC_TMR1 0x819
1450	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1451	#define MSR_IA32_X2APIC_TMR2 0x81A
1452	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1453	#define MSR_IA32_X2APIC_TMR3 0x81B
1454	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1455	#define MSR_IA32_X2APIC_TMR4 0x81C
1456	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1457	#define MSR_IA32_X2APIC_TMR5 0x81D
1458	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1459	#define MSR_IA32_X2APIC_TMR6 0x81E
1460	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1461	#define MSR_IA32_X2APIC_TMR7 0x81F
1462	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1463	#define MSR_IA32_X2APIC_IRR0 0x820
1464	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1465	#define MSR_IA32_X2APIC_IRR1 0x821
1466	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1467	#define MSR_IA32_X2APIC_IRR2 0x822
1468	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1469	#define MSR_IA32_X2APIC_IRR3 0x823
1470	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1471	#define MSR_IA32_X2APIC_IRR4 0x824
1472	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1473	#define MSR_IA32_X2APIC_IRR5 0x825
1474	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1475	#define MSR_IA32_X2APIC_IRR6 0x826
1476	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1477	#define MSR_IA32_X2APIC_IRR7 0x827
1478	/** X2APIC MSR - Error Status Register. */
1479	#define MSR_IA32_X2APIC_ESR 0x828
1480	/** X2APIC MSR - LVT CMCI Register. */
1481	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1482	/** X2APIC MSR - Interrupt Command Register. */
1483	#define MSR_IA32_X2APIC_ICR 0x830
1484	/** X2APIC MSR - LVT Timer Register. */
1485	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1486	/** X2APIC MSR - LVT Thermal Sensor Register. */
1487	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1488	/** X2APIC MSR - LVT Performance Counter Register. */
1489	#define MSR_IA32_X2APIC_LVT_PERF 0x834
1490	/** X2APIC MSR - LVT LINT0 Register. */
1491	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1492	/** X2APIC MSR - LVT LINT1 Register. */
1493	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1494	/** X2APIC MSR - LVT Error Register . */
1495	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1496	/** X2APIC MSR - Timer Initial Count Register. */
1497	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1498	/** X2APIC MSR - Timer Current Count Register. */
1499	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1500	/** X2APIC MSR - Timer Divide Configuration Register. */
1501	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1502	/** X2APIC MSR - Self IPI. */
1503	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1504	/** X2APIC MSR range end. */
1505	#define MSR_IA32_X2APIC_END 0xBFF
1506	/** X2APIC MSR - LVT start range. */
1507	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1508	/** X2APIC MSR - LVT end range (inclusive). */
1509	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1510
1511	/** K6 EFER - Extended Feature Enable Register. */
1512	#define MSR_K6_EFER UINT32_C(0xc0000080)
1513	/** @todo document EFER */
1514	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1515	#define MSR_K6_EFER_SCE RT_BIT_32(0)
1516	/** Bit 8 - LME - Long mode enabled. (R/W) */
1517	#define MSR_K6_EFER_LME RT_BIT_32(8)
1518	/** Bit 10 - LMA - Long mode active. (R) */
1519	#define MSR_K6_EFER_LMA RT_BIT_32(10)
1520	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1521	#define MSR_K6_EFER_NXE RT_BIT_32(11)
1522	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
1523	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1524	#define MSR_K6_EFER_SVME RT_BIT_32(12)
1525	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1526	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1527	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1528	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1529	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1530	#define MSR_K6_EFER_TCE RT_BIT_32(15)
1531	/** K6 STAR - SYSCALL/RET targets. */
1532	#define MSR_K6_STAR UINT32_C(0xc0000081)
1533	/** Shift value for getting the SYSRET CS and SS value. */
1534	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1535	/** Shift value for getting the SYSCALL CS and SS value. */
1536	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1537	/** Selector mask for use after shifting. */
1538	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1539	/** The mask which give the SYSCALL EIP. */
1540	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1541	/** K6 WHCR - Write Handling Control Register. */
1542	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1543	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1544	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1545	/** K6 PSOR - Processor State Observability Register. */
1546	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1547	/** K6 PFIR - Page Flush/Invalidate Register. */
1548	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1549
1550	/** Performance counter MSRs. (AMD only) */
1551	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1552	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1553	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1554	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1555	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1556	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1557	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1558	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1559
1560	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1561	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1562	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1563	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1564	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1565	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1566	/** K8 FS.base - The 64-bit base FS register. */
1567	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1568	/** K8 GS.base - The 64-bit base GS register. */
1569	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1570	/** K8 KernelGSbase - Used with SWAPGS. */
1571	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1572	/** K8 TSC_AUX - Used with RDTSCP. */
1573	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1574	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1575	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1576	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1577	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1578	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1579	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1580	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1581	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1582	/** North bridge config? See BIOS & Kernel dev guides for
1583	* details. */
1584	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1585
1586	/** Hypertransport interrupt pending register.
1587	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1588	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1589
1590	/** SVM Control. */
1591	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1592	/** Disables HDT (Hardware Debug Tool) and certain internal debug
1593	* features. */
1594	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1595	/** If set, non-intercepted INIT signals are converted to \#SX
1596	* exceptions. */
1597	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1598	/** Disables A20 masking. */
1599	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1600	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1601	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1602	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1603	* clear, EFER.SVME can be written normally. */
1604	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1605
1606	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1607	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1608	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1609	* host state during world switch. */
1610	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1611
1612	/** @} */
1613
1614
1615	/** @name Page Table / Directory / Directory Pointers / L4.
1616	* @{
1617	*/
1618
1619	/** Page table/directory entry as an unsigned integer. */
1620	typedef uint32_t X86PGUINT;
1621	/** Pointer to a page table/directory table entry as an unsigned integer. */
1622	typedef X86PGUINT *PX86PGUINT;
1623	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1624	typedef X86PGUINT const *PCX86PGUINT;
1625
1626	/** Number of entries in a 32-bit PT/PD. */
1627	#define X86_PG_ENTRIES 1024
1628
1629
1630	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1631	typedef uint64_t X86PGPAEUINT;
1632	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1633	typedef X86PGPAEUINT *PX86PGPAEUINT;
1634	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1635	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1636
1637	/** Number of entries in a PAE PT/PD. */
1638	#define X86_PG_PAE_ENTRIES 512
1639	/** Number of entries in a PAE PDPT. */
1640	#define X86_PG_PAE_PDPE_ENTRIES 4
1641
1642	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1643	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1644	/** Number of entries in an AMD64 PDPT.
1645	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1646	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1647
1648	/** The size of a default page. */
1649	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1650	/** The page shift of a default page. */
1651	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1652	/** The default page offset mask. */
1653	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1654	/** The default page base mask for virtual addresses. */
1655	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1656	/** The default page base mask for virtual addresses - 32bit version. */
1657	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1658
1659	/** The size of a 4KB page. */
1660	#define X86_PAGE_4K_SIZE _4K
1661	/** The page shift of a 4KB page. */
1662	#define X86_PAGE_4K_SHIFT 12
1663	/** The 4KB page offset mask. */
1664	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1665	/** The 4KB page base mask for virtual addresses. */
1666	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1667	/** The 4KB page base mask for virtual addresses - 32bit version. */
1668	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1669
1670	/** The size of a 2MB page. */
1671	#define X86_PAGE_2M_SIZE _2M
1672	/** The page shift of a 2MB page. */
1673	#define X86_PAGE_2M_SHIFT 21
1674	/** The 2MB page offset mask. */
1675	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1676	/** The 2MB page base mask for virtual addresses. */
1677	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1678	/** The 2MB page base mask for virtual addresses - 32bit version. */
1679	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1680
1681	/** The size of a 4MB page. */
1682	#define X86_PAGE_4M_SIZE _4M
1683	/** The page shift of a 4MB page. */
1684	#define X86_PAGE_4M_SHIFT 22
1685	/** The 4MB page offset mask. */
1686	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1687	/** The 4MB page base mask for virtual addresses. */
1688	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1689	/** The 4MB page base mask for virtual addresses - 32bit version. */
1690	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1691
1692	/**
1693	* Check if the given address is canonical.
1694	*/
1695	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1696
1697
1698	/** @name Page Table Entry
1699	* @{
1700	*/
1701	/** Bit 0 - P - Present bit. */
1702	#define X86_PTE_BIT_P 0
1703	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1704	#define X86_PTE_BIT_RW 1
1705	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1706	#define X86_PTE_BIT_US 2
1707	/** Bit 3 - PWT - Page level write thru bit. */
1708	#define X86_PTE_BIT_PWT 3
1709	/** Bit 4 - PCD - Page level cache disable bit. */
1710	#define X86_PTE_BIT_PCD 4
1711	/** Bit 5 - A - Access bit. */
1712	#define X86_PTE_BIT_A 5
1713	/** Bit 6 - D - Dirty bit. */
1714	#define X86_PTE_BIT_D 6
1715	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1716	#define X86_PTE_BIT_PAT 7
1717	/** Bit 8 - G - Global flag. */
1718	#define X86_PTE_BIT_G 8
1719	/** Bits 63 - NX - PAE/LM - No execution flag. */
1720	#define X86_PTE_PAE_BIT_NX 63
1721
1722	/** Bit 0 - P - Present bit mask. */
1723	#define X86_PTE_P RT_BIT_32(0)
1724	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1725	#define X86_PTE_RW RT_BIT_32(1)
1726	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1727	#define X86_PTE_US RT_BIT_32(2)
1728	/** Bit 3 - PWT - Page level write thru bit mask. */
1729	#define X86_PTE_PWT RT_BIT_32(3)
1730	/** Bit 4 - PCD - Page level cache disable bit mask. */
1731	#define X86_PTE_PCD RT_BIT_32(4)
1732	/** Bit 5 - A - Access bit mask. */
1733	#define X86_PTE_A RT_BIT_32(5)
1734	/** Bit 6 - D - Dirty bit mask. */
1735	#define X86_PTE_D RT_BIT_32(6)
1736	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1737	#define X86_PTE_PAT RT_BIT_32(7)
1738	/** Bit 8 - G - Global bit mask. */
1739	#define X86_PTE_G RT_BIT_32(8)
1740
1741	/** Bits 9-11 - - Available for use to system software. */
1742	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
1743	/** Bits 12-31 - - Physical Page number of the next level. */
1744	#define X86_PTE_PG_MASK ( 0xfffff000 )
1745
1746	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1747	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1748	/** Bits 63 - NX - PAE/LM - No execution flag. */
1749	#define X86_PTE_PAE_NX RT_BIT_64(63)
1750	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1751	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1752	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1753	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1754	/** No bits - - LM - MBZ bits when NX is active. */
1755	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1756	/** Bits 63 - - LM - MBZ bits when no NX. */
1757	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1758
1759	/**
1760	* Page table entry.
1761	*/
1762	typedef struct X86PTEBITS
1763	{
1764	/** Flags whether(=1) or not the page is present. */
1765	uint32_t u1Present : 1;
1766	/** Read(=0) / Write(=1) flag. */
1767	uint32_t u1Write : 1;
1768	/** User(=1) / Supervisor (=0) flag. */
1769	uint32_t u1User : 1;
1770	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1771	uint32_t u1WriteThru : 1;
1772	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1773	uint32_t u1CacheDisable : 1;
1774	/** Accessed flag.
1775	* Indicates that the page have been read or written to. */
1776	uint32_t u1Accessed : 1;
1777	/** Dirty flag.
1778	* Indicates that the page has been written to. */
1779	uint32_t u1Dirty : 1;
1780	/** Reserved / If PAT enabled, bit 2 of the index. */
1781	uint32_t u1PAT : 1;
1782	/** Global flag. (Ignored in all but final level.) */
1783	uint32_t u1Global : 1;
1784	/** Available for use to system software. */
1785	uint32_t u3Available : 3;
1786	/** Physical Page number of the next level. */
1787	uint32_t u20PageNo : 20;
1788	} X86PTEBITS;
1789	#ifndef VBOX_FOR_DTRACE_LIB
1790	AssertCompileSize(X86PTEBITS, 4);
1791	#endif
1792	/** Pointer to a page table entry. */
1793	typedef X86PTEBITS *PX86PTEBITS;
1794	/** Pointer to a const page table entry. */
1795	typedef const X86PTEBITS *PCX86PTEBITS;
1796
1797	/**
1798	* Page table entry.
1799	*/
1800	typedef union X86PTE
1801	{
1802	/** Unsigned integer view */
1803	X86PGUINT u;
1804	/** Bit field view. */
1805	X86PTEBITS n;
1806	/** 32-bit view. */
1807	uint32_t au32[1];
1808	/** 16-bit view. */
1809	uint16_t au16[2];
1810	/** 8-bit view. */
1811	uint8_t au8[4];
1812	} X86PTE;
1813	#ifndef VBOX_FOR_DTRACE_LIB
1814	AssertCompileSize(X86PTE, 4);
1815	#endif
1816	/** Pointer to a page table entry. */
1817	typedef X86PTE *PX86PTE;
1818	/** Pointer to a const page table entry. */
1819	typedef const X86PTE *PCX86PTE;
1820
1821
1822	/**
1823	* PAE page table entry.
1824	*/
1825	typedef struct X86PTEPAEBITS
1826	{
1827	/** Flags whether(=1) or not the page is present. */
1828	uint32_t u1Present : 1;
1829	/** Read(=0) / Write(=1) flag. */
1830	uint32_t u1Write : 1;
1831	/** User(=1) / Supervisor(=0) flag. */
1832	uint32_t u1User : 1;
1833	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1834	uint32_t u1WriteThru : 1;
1835	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1836	uint32_t u1CacheDisable : 1;
1837	/** Accessed flag.
1838	* Indicates that the page have been read or written to. */
1839	uint32_t u1Accessed : 1;
1840	/** Dirty flag.
1841	* Indicates that the page has been written to. */
1842	uint32_t u1Dirty : 1;
1843	/** Reserved / If PAT enabled, bit 2 of the index. */
1844	uint32_t u1PAT : 1;
1845	/** Global flag. (Ignored in all but final level.) */
1846	uint32_t u1Global : 1;
1847	/** Available for use to system software. */
1848	uint32_t u3Available : 3;
1849	/** Physical Page number of the next level - Low Part. Don't use this. */
1850	uint32_t u20PageNoLow : 20;
1851	/** Physical Page number of the next level - High Part. Don't use this. */
1852	uint32_t u20PageNoHigh : 20;
1853	/** MBZ bits */
1854	uint32_t u11Reserved : 11;
1855	/** No Execute flag. */
1856	uint32_t u1NoExecute : 1;
1857	} X86PTEPAEBITS;
1858	#ifndef VBOX_FOR_DTRACE_LIB
1859	AssertCompileSize(X86PTEPAEBITS, 8);
1860	#endif
1861	/** Pointer to a page table entry. */
1862	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1863	/** Pointer to a page table entry. */
1864	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1865
1866	/**
1867	* PAE Page table entry.
1868	*/
1869	typedef union X86PTEPAE
1870	{
1871	/** Unsigned integer view */
1872	X86PGPAEUINT u;
1873	/** Bit field view. */
1874	X86PTEPAEBITS n;
1875	/** 32-bit view. */
1876	uint32_t au32[2];
1877	/** 16-bit view. */
1878	uint16_t au16[4];
1879	/** 8-bit view. */
1880	uint8_t au8[8];
1881	} X86PTEPAE;
1882	#ifndef VBOX_FOR_DTRACE_LIB
1883	AssertCompileSize(X86PTEPAE, 8);
1884	#endif
1885	/** Pointer to a PAE page table entry. */
1886	typedef X86PTEPAE *PX86PTEPAE;
1887	/** Pointer to a const PAE page table entry. */
1888	typedef const X86PTEPAE *PCX86PTEPAE;
1889	/** @} */
1890
1891	/**
1892	* Page table.
1893	*/
1894	typedef struct X86PT
1895	{
1896	/** PTE Array. */
1897	X86PTE a[X86_PG_ENTRIES];
1898	} X86PT;
1899	#ifndef VBOX_FOR_DTRACE_LIB
1900	AssertCompileSize(X86PT, 4096);
1901	#endif
1902	/** Pointer to a page table. */
1903	typedef X86PT *PX86PT;
1904	/** Pointer to a const page table. */
1905	typedef const X86PT *PCX86PT;
1906
1907	/** The page shift to get the PT index. */
1908	#define X86_PT_SHIFT 12
1909	/** The PT index mask (apply to a shifted page address). */
1910	#define X86_PT_MASK 0x3ff
1911
1912
1913	/**
1914	* Page directory.
1915	*/
1916	typedef struct X86PTPAE
1917	{
1918	/** PTE Array. */
1919	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1920	} X86PTPAE;
1921	#ifndef VBOX_FOR_DTRACE_LIB
1922	AssertCompileSize(X86PTPAE, 4096);
1923	#endif
1924	/** Pointer to a page table. */
1925	typedef X86PTPAE *PX86PTPAE;
1926	/** Pointer to a const page table. */
1927	typedef const X86PTPAE *PCX86PTPAE;
1928
1929	/** The page shift to get the PA PTE index. */
1930	#define X86_PT_PAE_SHIFT 12
1931	/** The PAE PT index mask (apply to a shifted page address). */
1932	#define X86_PT_PAE_MASK 0x1ff
1933
1934
1935	/** @name 4KB Page Directory Entry
1936	* @{
1937	*/
1938	/** Bit 0 - P - Present bit. */
1939	#define X86_PDE_P RT_BIT_32(0)
1940	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1941	#define X86_PDE_RW RT_BIT_32(1)
1942	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1943	#define X86_PDE_US RT_BIT_32(2)
1944	/** Bit 3 - PWT - Page level write thru bit. */
1945	#define X86_PDE_PWT RT_BIT_32(3)
1946	/** Bit 4 - PCD - Page level cache disable bit. */
1947	#define X86_PDE_PCD RT_BIT_32(4)
1948	/** Bit 5 - A - Access bit. */
1949	#define X86_PDE_A RT_BIT_32(5)
1950	/** Bit 7 - PS - Page size attribute.
1951	* Clear mean 4KB pages, set means large pages (2/4MB). */
1952	#define X86_PDE_PS RT_BIT_32(7)
1953	/** Bits 9-11 - - Available for use to system software. */
1954	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
1955	/** Bits 12-31 - - Physical Page number of the next level. */
1956	#define X86_PDE_PG_MASK ( 0xfffff000 )
1957
1958	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1959	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1960	/** Bits 63 - NX - PAE/LM - No execution flag. */
1961	#define X86_PDE_PAE_NX RT_BIT_64(63)
1962	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1963	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1964	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1965	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1966	/** Bit 7 - - LM - MBZ bits when NX is active. */
1967	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1968	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1969	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1970
1971	/**
1972	* Page directory entry.
1973	*/
1974	typedef struct X86PDEBITS
1975	{
1976	/** Flags whether(=1) or not the page is present. */
1977	uint32_t u1Present : 1;
1978	/** Read(=0) / Write(=1) flag. */
1979	uint32_t u1Write : 1;
1980	/** User(=1) / Supervisor (=0) flag. */
1981	uint32_t u1User : 1;
1982	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1983	uint32_t u1WriteThru : 1;
1984	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1985	uint32_t u1CacheDisable : 1;
1986	/** Accessed flag.
1987	* Indicates that the page has been read or written to. */
1988	uint32_t u1Accessed : 1;
1989	/** Reserved / Ignored (dirty bit). */
1990	uint32_t u1Reserved0 : 1;
1991	/** Size bit if PSE is enabled - in any event it's 0. */
1992	uint32_t u1Size : 1;
1993	/** Reserved / Ignored (global bit). */
1994	uint32_t u1Reserved1 : 1;
1995	/** Available for use to system software. */
1996	uint32_t u3Available : 3;
1997	/** Physical Page number of the next level. */
1998	uint32_t u20PageNo : 20;
1999	} X86PDEBITS;
2000	#ifndef VBOX_FOR_DTRACE_LIB
2001	AssertCompileSize(X86PDEBITS, 4);
2002	#endif
2003	/** Pointer to a page directory entry. */
2004	typedef X86PDEBITS *PX86PDEBITS;
2005	/** Pointer to a const page directory entry. */
2006	typedef const X86PDEBITS *PCX86PDEBITS;
2007
2008
2009	/**
2010	* PAE page directory entry.
2011	*/
2012	typedef struct X86PDEPAEBITS
2013	{
2014	/** Flags whether(=1) or not the page is present. */
2015	uint32_t u1Present : 1;
2016	/** Read(=0) / Write(=1) flag. */
2017	uint32_t u1Write : 1;
2018	/** User(=1) / Supervisor (=0) flag. */
2019	uint32_t u1User : 1;
2020	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2021	uint32_t u1WriteThru : 1;
2022	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2023	uint32_t u1CacheDisable : 1;
2024	/** Accessed flag.
2025	* Indicates that the page has been read or written to. */
2026	uint32_t u1Accessed : 1;
2027	/** Reserved / Ignored (dirty bit). */
2028	uint32_t u1Reserved0 : 1;
2029	/** Size bit if PSE is enabled - in any event it's 0. */
2030	uint32_t u1Size : 1;
2031	/** Reserved / Ignored (global bit). / */
2032	uint32_t u1Reserved1 : 1;
2033	/** Available for use to system software. */
2034	uint32_t u3Available : 3;
2035	/** Physical Page number of the next level - Low Part. Don't use! */
2036	uint32_t u20PageNoLow : 20;
2037	/** Physical Page number of the next level - High Part. Don't use! */
2038	uint32_t u20PageNoHigh : 20;
2039	/** MBZ bits */
2040	uint32_t u11Reserved : 11;
2041	/** No Execute flag. */
2042	uint32_t u1NoExecute : 1;
2043	} X86PDEPAEBITS;
2044	#ifndef VBOX_FOR_DTRACE_LIB
2045	AssertCompileSize(X86PDEPAEBITS, 8);
2046	#endif
2047	/** Pointer to a page directory entry. */
2048	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2049	/** Pointer to a const page directory entry. */
2050	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2051
2052	/** @} */
2053
2054
2055	/** @name 2/4MB Page Directory Entry
2056	* @{
2057	*/
2058	/** Bit 0 - P - Present bit. */
2059	#define X86_PDE4M_P RT_BIT_32(0)
2060	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2061	#define X86_PDE4M_RW RT_BIT_32(1)
2062	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2063	#define X86_PDE4M_US RT_BIT_32(2)
2064	/** Bit 3 - PWT - Page level write thru bit. */
2065	#define X86_PDE4M_PWT RT_BIT_32(3)
2066	/** Bit 4 - PCD - Page level cache disable bit. */
2067	#define X86_PDE4M_PCD RT_BIT_32(4)
2068	/** Bit 5 - A - Access bit. */
2069	#define X86_PDE4M_A RT_BIT_32(5)
2070	/** Bit 6 - D - Dirty bit. */
2071	#define X86_PDE4M_D RT_BIT_32(6)
2072	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2073	#define X86_PDE4M_PS RT_BIT_32(7)
2074	/** Bit 8 - G - Global flag. */
2075	#define X86_PDE4M_G RT_BIT_32(8)
2076	/** Bits 9-11 - AVL - Available for use to system software. */
2077	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2078	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2079	#define X86_PDE4M_PAT RT_BIT_32(12)
2080	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2081	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2082	/** Bits 22-31 - - Physical Page number. */
2083	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2084	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2085	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2086	/** The number of bits to the high part of the page number. */
2087	#define X86_PDE4M_PG_HIGH_SHIFT 19
2088	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2089	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2090
2091	/** Bits 21-51 - - PAE/LM - Physical Page number.
2092	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2093	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2094	/** Bits 63 - NX - PAE/LM - No execution flag. */
2095	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2096	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2097	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2098	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2099	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2100	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2101	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2102	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2103	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2104
2105	/**
2106	* 4MB page directory entry.
2107	*/
2108	typedef struct X86PDE4MBITS
2109	{
2110	/** Flags whether(=1) or not the page is present. */
2111	uint32_t u1Present : 1;
2112	/** Read(=0) / Write(=1) flag. */
2113	uint32_t u1Write : 1;
2114	/** User(=1) / Supervisor (=0) flag. */
2115	uint32_t u1User : 1;
2116	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2117	uint32_t u1WriteThru : 1;
2118	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2119	uint32_t u1CacheDisable : 1;
2120	/** Accessed flag.
2121	* Indicates that the page have been read or written to. */
2122	uint32_t u1Accessed : 1;
2123	/** Dirty flag.
2124	* Indicates that the page has been written to. */
2125	uint32_t u1Dirty : 1;
2126	/** Page size flag - always 1 for 4MB entries. */
2127	uint32_t u1Size : 1;
2128	/** Global flag. */
2129	uint32_t u1Global : 1;
2130	/** Available for use to system software. */
2131	uint32_t u3Available : 3;
2132	/** Reserved / If PAT enabled, bit 2 of the index. */
2133	uint32_t u1PAT : 1;
2134	/** Bits 32-39 of the page number on AMD64.
2135	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2136	uint32_t u8PageNoHigh : 8;
2137	/** Reserved. */
2138	uint32_t u1Reserved : 1;
2139	/** Physical Page number of the page. */
2140	uint32_t u10PageNo : 10;
2141	} X86PDE4MBITS;
2142	#ifndef VBOX_FOR_DTRACE_LIB
2143	AssertCompileSize(X86PDE4MBITS, 4);
2144	#endif
2145	/** Pointer to a page table entry. */
2146	typedef X86PDE4MBITS *PX86PDE4MBITS;
2147	/** Pointer to a const page table entry. */
2148	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2149
2150
2151	/**
2152	* 2MB PAE page directory entry.
2153	*/
2154	typedef struct X86PDE2MPAEBITS
2155	{
2156	/** Flags whether(=1) or not the page is present. */
2157	uint32_t u1Present : 1;
2158	/** Read(=0) / Write(=1) flag. */
2159	uint32_t u1Write : 1;
2160	/** User(=1) / Supervisor(=0) flag. */
2161	uint32_t u1User : 1;
2162	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2163	uint32_t u1WriteThru : 1;
2164	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2165	uint32_t u1CacheDisable : 1;
2166	/** Accessed flag.
2167	* Indicates that the page have been read or written to. */
2168	uint32_t u1Accessed : 1;
2169	/** Dirty flag.
2170	* Indicates that the page has been written to. */
2171	uint32_t u1Dirty : 1;
2172	/** Page size flag - always 1 for 2MB entries. */
2173	uint32_t u1Size : 1;
2174	/** Global flag. */
2175	uint32_t u1Global : 1;
2176	/** Available for use to system software. */
2177	uint32_t u3Available : 3;
2178	/** Reserved / If PAT enabled, bit 2 of the index. */
2179	uint32_t u1PAT : 1;
2180	/** Reserved. */
2181	uint32_t u9Reserved : 9;
2182	/** Physical Page number of the next level - Low part. Don't use! */
2183	uint32_t u10PageNoLow : 10;
2184	/** Physical Page number of the next level - High part. Don't use! */
2185	uint32_t u20PageNoHigh : 20;
2186	/** MBZ bits */
2187	uint32_t u11Reserved : 11;
2188	/** No Execute flag. */
2189	uint32_t u1NoExecute : 1;
2190	} X86PDE2MPAEBITS;
2191	#ifndef VBOX_FOR_DTRACE_LIB
2192	AssertCompileSize(X86PDE2MPAEBITS, 8);
2193	#endif
2194	/** Pointer to a 2MB PAE page table entry. */
2195	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2196	/** Pointer to a 2MB PAE page table entry. */
2197	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2198
2199	/** @} */
2200
2201	/**
2202	* Page directory entry.
2203	*/
2204	typedef union X86PDE
2205	{
2206	/** Unsigned integer view. */
2207	X86PGUINT u;
2208	/** Normal view. */
2209	X86PDEBITS n;
2210	/** 4MB view (big). */
2211	X86PDE4MBITS b;
2212	/** 8 bit unsigned integer view. */
2213	uint8_t au8[4];
2214	/** 16 bit unsigned integer view. */
2215	uint16_t au16[2];
2216	/** 32 bit unsigned integer view. */
2217	uint32_t au32[1];
2218	} X86PDE;
2219	#ifndef VBOX_FOR_DTRACE_LIB
2220	AssertCompileSize(X86PDE, 4);
2221	#endif
2222	/** Pointer to a page directory entry. */
2223	typedef X86PDE *PX86PDE;
2224	/** Pointer to a const page directory entry. */
2225	typedef const X86PDE *PCX86PDE;
2226
2227	/**
2228	* PAE page directory entry.
2229	*/
2230	typedef union X86PDEPAE
2231	{
2232	/** Unsigned integer view. */
2233	X86PGPAEUINT u;
2234	/** Normal view. */
2235	X86PDEPAEBITS n;
2236	/** 2MB page view (big). */
2237	X86PDE2MPAEBITS b;
2238	/** 8 bit unsigned integer view. */
2239	uint8_t au8[8];
2240	/** 16 bit unsigned integer view. */
2241	uint16_t au16[4];
2242	/** 32 bit unsigned integer view. */
2243	uint32_t au32[2];
2244	} X86PDEPAE;
2245	#ifndef VBOX_FOR_DTRACE_LIB
2246	AssertCompileSize(X86PDEPAE, 8);
2247	#endif
2248	/** Pointer to a page directory entry. */
2249	typedef X86PDEPAE *PX86PDEPAE;
2250	/** Pointer to a const page directory entry. */
2251	typedef const X86PDEPAE *PCX86PDEPAE;
2252
2253	/**
2254	* Page directory.
2255	*/
2256	typedef struct X86PD
2257	{
2258	/** PDE Array. */
2259	X86PDE a[X86_PG_ENTRIES];
2260	} X86PD;
2261	#ifndef VBOX_FOR_DTRACE_LIB
2262	AssertCompileSize(X86PD, 4096);
2263	#endif
2264	/** Pointer to a page directory. */
2265	typedef X86PD *PX86PD;
2266	/** Pointer to a const page directory. */
2267	typedef const X86PD *PCX86PD;
2268
2269	/** The page shift to get the PD index. */
2270	#define X86_PD_SHIFT 22
2271	/** The PD index mask (apply to a shifted page address). */
2272	#define X86_PD_MASK 0x3ff
2273
2274
2275	/**
2276	* PAE page directory.
2277	*/
2278	typedef struct X86PDPAE
2279	{
2280	/** PDE Array. */
2281	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2282	} X86PDPAE;
2283	#ifndef VBOX_FOR_DTRACE_LIB
2284	AssertCompileSize(X86PDPAE, 4096);
2285	#endif
2286	/** Pointer to a PAE page directory. */
2287	typedef X86PDPAE *PX86PDPAE;
2288	/** Pointer to a const PAE page directory. */
2289	typedef const X86PDPAE *PCX86PDPAE;
2290
2291	/** The page shift to get the PAE PD index. */
2292	#define X86_PD_PAE_SHIFT 21
2293	/** The PAE PD index mask (apply to a shifted page address). */
2294	#define X86_PD_PAE_MASK 0x1ff
2295
2296
2297	/** @name Page Directory Pointer Table Entry (PAE)
2298	* @{
2299	*/
2300	/** Bit 0 - P - Present bit. */
2301	#define X86_PDPE_P RT_BIT_32(0)
2302	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2303	#define X86_PDPE_RW RT_BIT_32(1)
2304	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2305	#define X86_PDPE_US RT_BIT_32(2)
2306	/** Bit 3 - PWT - Page level write thru bit. */
2307	#define X86_PDPE_PWT RT_BIT_32(3)
2308	/** Bit 4 - PCD - Page level cache disable bit. */
2309	#define X86_PDPE_PCD RT_BIT_32(4)
2310	/** Bit 5 - A - Access bit. Long Mode only. */
2311	#define X86_PDPE_A RT_BIT_32(5)
2312	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2313	#define X86_PDPE_LM_PS RT_BIT_32(7)
2314	/** Bits 9-11 - - Available for use to system software. */
2315	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2316	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2317	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2318	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2319	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2320	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2321	#define X86_PDPE_LM_NX RT_BIT_64(63)
2322	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2323	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2324	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2325	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2326	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2327	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2328	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2329	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2330
2331
2332	/**
2333	* Page directory pointer table entry.
2334	*/
2335	typedef struct X86PDPEBITS
2336	{
2337	/** Flags whether(=1) or not the page is present. */
2338	uint32_t u1Present : 1;
2339	/** Chunk of reserved bits. */
2340	uint32_t u2Reserved : 2;
2341	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2342	uint32_t u1WriteThru : 1;
2343	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2344	uint32_t u1CacheDisable : 1;
2345	/** Chunk of reserved bits. */
2346	uint32_t u4Reserved : 4;
2347	/** Available for use to system software. */
2348	uint32_t u3Available : 3;
2349	/** Physical Page number of the next level - Low Part. Don't use! */
2350	uint32_t u20PageNoLow : 20;
2351	/** Physical Page number of the next level - High Part. Don't use! */
2352	uint32_t u20PageNoHigh : 20;
2353	/** MBZ bits */
2354	uint32_t u12Reserved : 12;
2355	} X86PDPEBITS;
2356	#ifndef VBOX_FOR_DTRACE_LIB
2357	AssertCompileSize(X86PDPEBITS, 8);
2358	#endif
2359	/** Pointer to a page directory pointer table entry. */
2360	typedef X86PDPEBITS *PX86PTPEBITS;
2361	/** Pointer to a const page directory pointer table entry. */
2362	typedef const X86PDPEBITS *PCX86PTPEBITS;
2363
2364	/**
2365	* Page directory pointer table entry. AMD64 version
2366	*/
2367	typedef struct X86PDPEAMD64BITS
2368	{
2369	/** Flags whether(=1) or not the page is present. */
2370	uint32_t u1Present : 1;
2371	/** Read(=0) / Write(=1) flag. */
2372	uint32_t u1Write : 1;
2373	/** User(=1) / Supervisor (=0) flag. */
2374	uint32_t u1User : 1;
2375	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2376	uint32_t u1WriteThru : 1;
2377	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2378	uint32_t u1CacheDisable : 1;
2379	/** Accessed flag.
2380	* Indicates that the page have been read or written to. */
2381	uint32_t u1Accessed : 1;
2382	/** Chunk of reserved bits. */
2383	uint32_t u3Reserved : 3;
2384	/** Available for use to system software. */
2385	uint32_t u3Available : 3;
2386	/** Physical Page number of the next level - Low Part. Don't use! */
2387	uint32_t u20PageNoLow : 20;
2388	/** Physical Page number of the next level - High Part. Don't use! */
2389	uint32_t u20PageNoHigh : 20;
2390	/** MBZ bits */
2391	uint32_t u11Reserved : 11;
2392	/** No Execute flag. */
2393	uint32_t u1NoExecute : 1;
2394	} X86PDPEAMD64BITS;
2395	#ifndef VBOX_FOR_DTRACE_LIB
2396	AssertCompileSize(X86PDPEAMD64BITS, 8);
2397	#endif
2398	/** Pointer to a page directory pointer table entry. */
2399	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2400	/** Pointer to a const page directory pointer table entry. */
2401	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2402
2403	/**
2404	* Page directory pointer table entry for 1GB page. (AMD64 only)
2405	*/
2406	typedef struct X86PDPE1GB
2407	{
2408	/** 0: Flags whether(=1) or not the page is present. */
2409	uint32_t u1Present : 1;
2410	/** 1: Read(=0) / Write(=1) flag. */
2411	uint32_t u1Write : 1;
2412	/** 2: User(=1) / Supervisor (=0) flag. */
2413	uint32_t u1User : 1;
2414	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2415	uint32_t u1WriteThru : 1;
2416	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2417	uint32_t u1CacheDisable : 1;
2418	/** 5: Accessed flag.
2419	* Indicates that the page have been read or written to. */
2420	uint32_t u1Accessed : 1;
2421	/** 6: Dirty flag for 1GB pages. */
2422	uint32_t u1Dirty : 1;
2423	/** 7: Indicates 1GB page if set. */
2424	uint32_t u1Size : 1;
2425	/** 8: Global 1GB page. */
2426	uint32_t u1Global: 1;
2427	/** 9-11: Available for use to system software. */
2428	uint32_t u3Available : 3;
2429	/** 12: PAT bit for 1GB page. */
2430	uint32_t u1PAT : 1;
2431	/** 13-29: MBZ bits. */
2432	uint32_t u17Reserved : 17;
2433	/** 30-31: Physical page number - Low Part. Don't use! */
2434	uint32_t u2PageNoLow : 2;
2435	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
2436	uint32_t u20PageNoHigh : 20;
2437	/** 52-62: MBZ bits */
2438	uint32_t u11Reserved : 11;
2439	/** 63: No Execute flag. */
2440	uint32_t u1NoExecute : 1;
2441	} X86PDPE1GB;
2442	#ifndef VBOX_FOR_DTRACE_LIB
2443	AssertCompileSize(X86PDPE1GB, 8);
2444	#endif
2445	/** Pointer to a page directory pointer table entry for a 1GB page. */
2446	typedef X86PDPE1GB *PX86PDPE1GB;
2447	/** Pointer to a const page directory pointer table entry for a 1GB page. */
2448	typedef const X86PDPE1GB *PCX86PDPE1GB;
2449
2450	/**
2451	* Page directory pointer table entry.
2452	*/
2453	typedef union X86PDPE
2454	{
2455	/** Unsigned integer view. */
2456	X86PGPAEUINT u;
2457	/** Normal view. */
2458	X86PDPEBITS n;
2459	/** AMD64 view. */
2460	X86PDPEAMD64BITS lm;
2461	/** AMD64 big view. */
2462	X86PDPE1GB b;
2463	/** 8 bit unsigned integer view. */
2464	uint8_t au8[8];
2465	/** 16 bit unsigned integer view. */
2466	uint16_t au16[4];
2467	/** 32 bit unsigned integer view. */
2468	uint32_t au32[2];
2469	} X86PDPE;
2470	#ifndef VBOX_FOR_DTRACE_LIB
2471	AssertCompileSize(X86PDPE, 8);
2472	#endif
2473	/** Pointer to a page directory pointer table entry. */
2474	typedef X86PDPE *PX86PDPE;
2475	/** Pointer to a const page directory pointer table entry. */
2476	typedef const X86PDPE *PCX86PDPE;
2477
2478
2479	/**
2480	* Page directory pointer table.
2481	*/
2482	typedef struct X86PDPT
2483	{
2484	/** PDE Array. */
2485	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2486	} X86PDPT;
2487	#ifndef VBOX_FOR_DTRACE_LIB
2488	AssertCompileSize(X86PDPT, 4096);
2489	#endif
2490	/** Pointer to a page directory pointer table. */
2491	typedef X86PDPT *PX86PDPT;
2492	/** Pointer to a const page directory pointer table. */
2493	typedef const X86PDPT *PCX86PDPT;
2494
2495	/** The page shift to get the PDPT index. */
2496	#define X86_PDPT_SHIFT 30
2497	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2498	#define X86_PDPT_MASK_PAE 0x3
2499	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2500	#define X86_PDPT_MASK_AMD64 0x1ff
2501
2502	/** @} */
2503
2504
2505	/** @name Page Map Level-4 Entry (Long Mode PAE)
2506	* @{
2507	*/
2508	/** Bit 0 - P - Present bit. */
2509	#define X86_PML4E_P RT_BIT_32(0)
2510	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2511	#define X86_PML4E_RW RT_BIT_32(1)
2512	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2513	#define X86_PML4E_US RT_BIT_32(2)
2514	/** Bit 3 - PWT - Page level write thru bit. */
2515	#define X86_PML4E_PWT RT_BIT_32(3)
2516	/** Bit 4 - PCD - Page level cache disable bit. */
2517	#define X86_PML4E_PCD RT_BIT_32(4)
2518	/** Bit 5 - A - Access bit. */
2519	#define X86_PML4E_A RT_BIT_32(5)
2520	/** Bits 9-11 - - Available for use to system software. */
2521	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2522	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2523	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2524	/** Bits 8, 7 - - MBZ bits when NX is active. */
2525	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2526	/** Bits 63, 7 - - MBZ bits when no NX. */
2527	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2528	/** Bits 63 - NX - PAE - No execution flag. */
2529	#define X86_PML4E_NX RT_BIT_64(63)
2530
2531	/**
2532	* Page Map Level-4 Entry
2533	*/
2534	typedef struct X86PML4EBITS
2535	{
2536	/** Flags whether(=1) or not the page is present. */
2537	uint32_t u1Present : 1;
2538	/** Read(=0) / Write(=1) flag. */
2539	uint32_t u1Write : 1;
2540	/** User(=1) / Supervisor (=0) flag. */
2541	uint32_t u1User : 1;
2542	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2543	uint32_t u1WriteThru : 1;
2544	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2545	uint32_t u1CacheDisable : 1;
2546	/** Accessed flag.
2547	* Indicates that the page have been read or written to. */
2548	uint32_t u1Accessed : 1;
2549	/** Chunk of reserved bits. */
2550	uint32_t u3Reserved : 3;
2551	/** Available for use to system software. */
2552	uint32_t u3Available : 3;
2553	/** Physical Page number of the next level - Low Part. Don't use! */
2554	uint32_t u20PageNoLow : 20;
2555	/** Physical Page number of the next level - High Part. Don't use! */
2556	uint32_t u20PageNoHigh : 20;
2557	/** MBZ bits */
2558	uint32_t u11Reserved : 11;
2559	/** No Execute flag. */
2560	uint32_t u1NoExecute : 1;
2561	} X86PML4EBITS;
2562	#ifndef VBOX_FOR_DTRACE_LIB
2563	AssertCompileSize(X86PML4EBITS, 8);
2564	#endif
2565	/** Pointer to a page map level-4 entry. */
2566	typedef X86PML4EBITS *PX86PML4EBITS;
2567	/** Pointer to a const page map level-4 entry. */
2568	typedef const X86PML4EBITS *PCX86PML4EBITS;
2569
2570	/**
2571	* Page Map Level-4 Entry.
2572	*/
2573	typedef union X86PML4E
2574	{
2575	/** Unsigned integer view. */
2576	X86PGPAEUINT u;
2577	/** Normal view. */
2578	X86PML4EBITS n;
2579	/** 8 bit unsigned integer view. */
2580	uint8_t au8[8];
2581	/** 16 bit unsigned integer view. */
2582	uint16_t au16[4];
2583	/** 32 bit unsigned integer view. */
2584	uint32_t au32[2];
2585	} X86PML4E;
2586	#ifndef VBOX_FOR_DTRACE_LIB
2587	AssertCompileSize(X86PML4E, 8);
2588	#endif
2589	/** Pointer to a page map level-4 entry. */
2590	typedef X86PML4E *PX86PML4E;
2591	/** Pointer to a const page map level-4 entry. */
2592	typedef const X86PML4E *PCX86PML4E;
2593
2594
2595	/**
2596	* Page Map Level-4.
2597	*/
2598	typedef struct X86PML4
2599	{
2600	/** PDE Array. */
2601	X86PML4E a[X86_PG_PAE_ENTRIES];
2602	} X86PML4;
2603	#ifndef VBOX_FOR_DTRACE_LIB
2604	AssertCompileSize(X86PML4, 4096);
2605	#endif
2606	/** Pointer to a page map level-4. */
2607	typedef X86PML4 *PX86PML4;
2608	/** Pointer to a const page map level-4. */
2609	typedef const X86PML4 *PCX86PML4;
2610
2611	/** The page shift to get the PML4 index. */
2612	#define X86_PML4_SHIFT 39
2613	/** The PML4 index mask (apply to a shifted page address). */
2614	#define X86_PML4_MASK 0x1ff
2615
2616	/** @} */
2617
2618	/** @} */
2619
2620	/**
2621	* Intel PCID invalidation types.
2622	*/
2623	/** Individual address invalidation. */
2624	#define X86_INVPCID_TYPE_INDV_ADDR 0
2625	/** Single-context invalidation. */
2626	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2627	/** All-context including globals invalidation. */
2628	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2629	/** All-context excluding globals invalidation. */
2630	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2631	/** The maximum valid invalidation type value. */
2632	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2633
2634	/**
2635	* 32-bit protected mode FSTENV image.
2636	*/
2637	typedef struct X86FSTENV32P
2638	{
2639	uint16_t FCW;
2640	uint16_t padding1;
2641	uint16_t FSW;
2642	uint16_t padding2;
2643	uint16_t FTW;
2644	uint16_t padding3;
2645	uint32_t FPUIP;
2646	uint16_t FPUCS;
2647	uint16_t FOP;
2648	uint32_t FPUDP;
2649	uint16_t FPUDS;
2650	uint16_t padding4;
2651	} X86FSTENV32P;
2652	/** Pointer to a 32-bit protected mode FSTENV image. */
2653	typedef X86FSTENV32P *PX86FSTENV32P;
2654	/** Pointer to a const 32-bit protected mode FSTENV image. */
2655	typedef X86FSTENV32P const *PCX86FSTENV32P;
2656
2657
2658	/**
2659	* 80-bit MMX/FPU register type.
2660	*/
2661	typedef struct X86FPUMMX
2662	{
2663	uint8_t reg[10];
2664	} X86FPUMMX;
2665	#ifndef VBOX_FOR_DTRACE_LIB
2666	AssertCompileSize(X86FPUMMX, 10);
2667	#endif
2668	/** Pointer to a 80-bit MMX/FPU register type. */
2669	typedef X86FPUMMX *PX86FPUMMX;
2670	/** Pointer to a const 80-bit MMX/FPU register type. */
2671	typedef const X86FPUMMX *PCX86FPUMMX;
2672
2673	/** FPU (x87) register. */
2674	typedef union X86FPUREG
2675	{
2676	/** MMX view. */
2677	uint64_t mmx;
2678	/** FPU view - todo. */
2679	X86FPUMMX fpu;
2680	/** Extended precision floating point view. */
2681	RTFLOAT80U r80;
2682	/** Extended precision floating point view v2 */
2683	RTFLOAT80U2 r80Ex;
2684	/** 8-bit view. */
2685	uint8_t au8[16];
2686	/** 16-bit view. */
2687	uint16_t au16[8];
2688	/** 32-bit view. */
2689	uint32_t au32[4];
2690	/** 64-bit view. */
2691	uint64_t au64[2];
2692	/** 128-bit view. (yeah, very helpful) */
2693	uint128_t au128[1];
2694	} X86FPUREG;
2695	#ifndef VBOX_FOR_DTRACE_LIB
2696	AssertCompileSize(X86FPUREG, 16);
2697	#endif
2698	/** Pointer to a FPU register. */
2699	typedef X86FPUREG *PX86FPUREG;
2700	/** Pointer to a const FPU register. */
2701	typedef X86FPUREG const *PCX86FPUREG;
2702
2703	/**
2704	* XMM register union.
2705	*/
2706	typedef union X86XMMREG
2707	{
2708	/** XMM Register view. */
2709	uint128_t xmm;
2710	/** 8-bit view. */
2711	uint8_t au8[16];
2712	/** 16-bit view. */
2713	uint16_t au16[8];
2714	/** 32-bit view. */
2715	uint32_t au32[4];
2716	/** 64-bit view. */
2717	uint64_t au64[2];
2718	/** 128-bit view. (yeah, very helpful) */
2719	uint128_t au128[1];
2720	/** Confusing nested 128-bit union view (this is what xmm should've been). */
2721	RTUINT128U uXmm;
2722	} X86XMMREG;
2723	#ifndef VBOX_FOR_DTRACE_LIB
2724	AssertCompileSize(X86XMMREG, 16);
2725	#endif
2726	/** Pointer to an XMM register state. */
2727	typedef X86XMMREG *PX86XMMREG;
2728	/** Pointer to a const XMM register state. */
2729	typedef X86XMMREG const *PCX86XMMREG;
2730
2731	/**
2732	* YMM register union.
2733	*/
2734	typedef union X86YMMREG
2735	{
2736	/** 8-bit view. */
2737	uint8_t au8[32];
2738	/** 16-bit view. */
2739	uint16_t au16[16];
2740	/** 32-bit view. */
2741	uint32_t au32[8];
2742	/** 64-bit view. */
2743	uint64_t au64[4];
2744	/** 128-bit view. (yeah, very helpful) */
2745	uint128_t au128[2];
2746	/** XMM sub register view. */
2747	X86XMMREG aXmm[2];
2748	} X86YMMREG;
2749	#ifndef VBOX_FOR_DTRACE_LIB
2750	AssertCompileSize(X86YMMREG, 32);
2751	#endif
2752	/** Pointer to an YMM register state. */
2753	typedef X86YMMREG *PX86YMMREG;
2754	/** Pointer to a const YMM register state. */
2755	typedef X86YMMREG const *PCX86YMMREG;
2756
2757	/**
2758	* ZMM register union.
2759	*/
2760	typedef union X86ZMMREG
2761	{
2762	/** 8-bit view. */
2763	uint8_t au8[64];
2764	/** 16-bit view. */
2765	uint16_t au16[32];
2766	/** 32-bit view. */
2767	uint32_t au32[16];
2768	/** 64-bit view. */
2769	uint64_t au64[8];
2770	/** 128-bit view. (yeah, very helpful) */
2771	uint128_t au128[4];
2772	/** XMM sub register view. */
2773	X86XMMREG aXmm[4];
2774	/** YMM sub register view. */
2775	X86YMMREG aYmm[2];
2776	} X86ZMMREG;
2777	#ifndef VBOX_FOR_DTRACE_LIB
2778	AssertCompileSize(X86ZMMREG, 64);
2779	#endif
2780	/** Pointer to an ZMM register state. */
2781	typedef X86ZMMREG *PX86ZMMREG;
2782	/** Pointer to a const ZMM register state. */
2783	typedef X86ZMMREG const *PCX86ZMMREG;
2784
2785
2786	/**
2787	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2788	* @todo verify this...
2789	*/
2790	#pragma pack(1)
2791	typedef struct X86FPUSTATE
2792	{
2793	/** 0x00 - Control word. */
2794	uint16_t FCW;
2795	/** 0x02 - Alignment word */
2796	uint16_t Dummy1;
2797	/** 0x04 - Status word. */
2798	uint16_t FSW;
2799	/** 0x06 - Alignment word */
2800	uint16_t Dummy2;
2801	/** 0x08 - Tag word */
2802	uint16_t FTW;
2803	/** 0x0a - Alignment word */
2804	uint16_t Dummy3;
2805
2806	/** 0x0c - Instruction pointer. */
2807	uint32_t FPUIP;
2808	/** 0x10 - Code selector. */
2809	uint16_t CS;
2810	/** 0x12 - Opcode. */
2811	uint16_t FOP;
2812	/** 0x14 - FOO. */
2813	uint32_t FPUOO;
2814	/** 0x18 - FOS. */
2815	uint32_t FPUOS;
2816	/** 0x1c - FPU register. */
2817	X86FPUREG regs[8];
2818	} X86FPUSTATE;
2819	#pragma pack()
2820	/** Pointer to a FPU state. */
2821	typedef X86FPUSTATE *PX86FPUSTATE;
2822	/** Pointer to a const FPU state. */
2823	typedef const X86FPUSTATE *PCX86FPUSTATE;
2824
2825	/**
2826	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2827	*/
2828	#pragma pack(1)
2829	typedef struct X86FXSTATE
2830	{
2831	/** 0x00 - Control word. */
2832	uint16_t FCW;
2833	/** 0x02 - Status word. */
2834	uint16_t FSW;
2835	/** 0x04 - Tag word. (The upper byte is always zero.) */
2836	uint16_t FTW;
2837	/** 0x06 - Opcode. */
2838	uint16_t FOP;
2839	/** 0x08 - Instruction pointer. */
2840	uint32_t FPUIP;
2841	/** 0x0c - Code selector. */
2842	uint16_t CS;
2843	uint16_t Rsrvd1;
2844	/** 0x10 - Data pointer. */
2845	uint32_t FPUDP;
2846	/** 0x14 - Data segment */
2847	uint16_t DS;
2848	/** 0x16 */
2849	uint16_t Rsrvd2;
2850	/** 0x18 */
2851	uint32_t MXCSR;
2852	/** 0x1c */
2853	uint32_t MXCSR_MASK;
2854	/** 0x20 - FPU registers. */
2855	X86FPUREG aRegs[8];
2856	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
2857	X86XMMREG aXMM[16];
2858	/* - offset 416 - */
2859	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2860	/* - offset 464 - Software usable reserved bits. */
2861	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2862	} X86FXSTATE;
2863	#pragma pack()
2864	/** Pointer to a FPU Extended state. */
2865	typedef X86FXSTATE *PX86FXSTATE;
2866	/** Pointer to a const FPU Extended state. */
2867	typedef const X86FXSTATE *PCX86FXSTATE;
2868
2869	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2870	* magic. Don't forget to update x86.mac if you change this! */
2871	#define X86_OFF_FXSTATE_RSVD 0x1d0
2872	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2873	* forget to update x86.mac if you change this!
2874	* @todo r=bird: This has nothing what-so-ever to do here.... */
2875	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2876	#ifndef VBOX_FOR_DTRACE_LIB
2877	AssertCompileSize(X86FXSTATE, 512);
2878	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2879	#endif
2880
2881	/** @name FPU status word flags.
2882	* @{ */
2883	/** Exception Flag: Invalid operation. */
2884	#define X86_FSW_IE RT_BIT_32(0)
2885	/** Exception Flag: Denormalized operand. */
2886	#define X86_FSW_DE RT_BIT_32(1)
2887	/** Exception Flag: Zero divide. */
2888	#define X86_FSW_ZE RT_BIT_32(2)
2889	/** Exception Flag: Overflow. */
2890	#define X86_FSW_OE RT_BIT_32(3)
2891	/** Exception Flag: Underflow. */
2892	#define X86_FSW_UE RT_BIT_32(4)
2893	/** Exception Flag: Precision. */
2894	#define X86_FSW_PE RT_BIT_32(5)
2895	/** Stack fault. */
2896	#define X86_FSW_SF RT_BIT_32(6)
2897	/** Error summary status. */
2898	#define X86_FSW_ES RT_BIT_32(7)
2899	/** Mask of exceptions flags, excluding the summary bit. */
2900	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2901	/** Mask of exceptions flags, including the summary bit. */
2902	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2903	/** Condition code 0. */
2904	#define X86_FSW_C0 RT_BIT_32(8)
2905	/** Condition code 1. */
2906	#define X86_FSW_C1 RT_BIT_32(9)
2907	/** Condition code 2. */
2908	#define X86_FSW_C2 RT_BIT_32(10)
2909	/** Top of the stack mask. */
2910	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2911	/** TOP shift value. */
2912	#define X86_FSW_TOP_SHIFT 11
2913	/** Mask for getting TOP value after shifting it right. */
2914	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2915	/** Get the TOP value. */
2916	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2917	/** Condition code 3. */
2918	#define X86_FSW_C3 RT_BIT_32(14)
2919	/** Mask of exceptions flags, including the summary bit. */
2920	#define X86_FSW_C_MASK UINT16_C(0x4700)
2921	/** FPU busy. */
2922	#define X86_FSW_B RT_BIT_32(15)
2923	/** @} */
2924
2925
2926	/** @name FPU control word flags.
2927	* @{ */
2928	/** Exception Mask: Invalid operation. */
2929	#define X86_FCW_IM RT_BIT_32(0)
2930	/** Exception Mask: Denormalized operand. */
2931	#define X86_FCW_DM RT_BIT_32(1)
2932	/** Exception Mask: Zero divide. */
2933	#define X86_FCW_ZM RT_BIT_32(2)
2934	/** Exception Mask: Overflow. */
2935	#define X86_FCW_OM RT_BIT_32(3)
2936	/** Exception Mask: Underflow. */
2937	#define X86_FCW_UM RT_BIT_32(4)
2938	/** Exception Mask: Precision. */
2939	#define X86_FCW_PM RT_BIT_32(5)
2940	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2941	* @remarks This includes reserved bit 6. */
2942	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2943	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2944	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2945	/** Precision control mask. */
2946	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2947	/** Precision control: 24-bit. */
2948	#define X86_FCW_PC_24 UINT16_C(0x0000)
2949	/** Precision control: Reserved. */
2950	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2951	/** Precision control: 53-bit. */
2952	#define X86_FCW_PC_53 UINT16_C(0x0200)
2953	/** Precision control: 64-bit. */
2954	#define X86_FCW_PC_64 UINT16_C(0x0300)
2955	/** Rounding control mask. */
2956	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2957	/** Rounding control: To nearest. */
2958	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2959	/** Rounding control: Down. */
2960	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2961	/** Rounding control: Up. */
2962	#define X86_FCW_RC_UP UINT16_C(0x0800)
2963	/** Rounding control: Towards zero. */
2964	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2965	/** Bits which should be zero, apparently. */
2966	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2967	/** @} */
2968
2969	/** @name SSE MXCSR
2970	* @{ */
2971	/** Exception Flag: Invalid operation. */
2972	#define X86_MXCSR_IE RT_BIT_32(0)
2973	/** Exception Flag: Denormalized operand. */
2974	#define X86_MXCSR_DE RT_BIT_32(1)
2975	/** Exception Flag: Zero divide. */
2976	#define X86_MXCSR_ZE RT_BIT_32(2)
2977	/** Exception Flag: Overflow. */
2978	#define X86_MXCSR_OE RT_BIT_32(3)
2979	/** Exception Flag: Underflow. */
2980	#define X86_MXCSR_UE RT_BIT_32(4)
2981	/** Exception Flag: Precision. */
2982	#define X86_MXCSR_PE RT_BIT_32(5)
2983
2984	/** Denormals are zero. */
2985	#define X86_MXCSR_DAZ RT_BIT_32(6)
2986
2987	/** Exception Mask: Invalid operation. */
2988	#define X86_MXCSR_IM RT_BIT_32(7)
2989	/** Exception Mask: Denormalized operand. */
2990	#define X86_MXCSR_DM RT_BIT_32(8)
2991	/** Exception Mask: Zero divide. */
2992	#define X86_MXCSR_ZM RT_BIT_32(9)
2993	/** Exception Mask: Overflow. */
2994	#define X86_MXCSR_OM RT_BIT_32(10)
2995	/** Exception Mask: Underflow. */
2996	#define X86_MXCSR_UM RT_BIT_32(11)
2997	/** Exception Mask: Precision. */
2998	#define X86_MXCSR_PM RT_BIT_32(12)
2999
3000	/** Rounding control mask. */
3001	#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
3002	/** Rounding control: To nearest. */
3003	#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3004	/** Rounding control: Down. */
3005	#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3006	/** Rounding control: Up. */
3007	#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3008	/** Rounding control: Towards zero. */
3009	#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3010
3011	/** Flush-to-zero for masked underflow. */
3012	#define X86_MXCSR_FZ RT_BIT_32(15)
3013
3014	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3015	#define X86_MXCSR_MM RT_BIT_32(17)
3016	/** @} */
3017
3018	/**
3019	* XSAVE header.
3020	*/
3021	typedef struct X86XSAVEHDR
3022	{
3023	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
3024	uint64_t bmXState;
3025	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3026	uint64_t bmXComp;
3027	/** Reserved for furture extensions, probably MBZ. */
3028	uint64_t au64Reserved[6];
3029	} X86XSAVEHDR;
3030	#ifndef VBOX_FOR_DTRACE_LIB
3031	AssertCompileSize(X86XSAVEHDR, 64);
3032	#endif
3033	/** Pointer to an XSAVE header. */
3034	typedef X86XSAVEHDR *PX86XSAVEHDR;
3035	/** Pointer to a const XSAVE header. */
3036	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3037
3038
3039	/**
3040	* The high 128-bit YMM register state (XSAVE_C_YMM).
3041	* (The lower 128-bits being in X86FXSTATE.)
3042	*/
3043	typedef struct X86XSAVEYMMHI
3044	{
3045	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3046	X86XMMREG aYmmHi[16];
3047	} X86XSAVEYMMHI;
3048	#ifndef VBOX_FOR_DTRACE_LIB
3049	AssertCompileSize(X86XSAVEYMMHI, 256);
3050	#endif
3051	/** Pointer to a high 128-bit YMM register state. */
3052	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3053	/** Pointer to a const high 128-bit YMM register state. */
3054	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3055
3056	/**
3057	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
3058	*/
3059	typedef struct X86XSAVEBNDREGS
3060	{
3061	/** Array of registers (BND0...BND3). */
3062	struct
3063	{
3064	/** Lower bound. */
3065	uint64_t uLowerBound;
3066	/** Upper bound. */
3067	uint64_t uUpperBound;
3068	} aRegs[4];
3069	} X86XSAVEBNDREGS;
3070	#ifndef VBOX_FOR_DTRACE_LIB
3071	AssertCompileSize(X86XSAVEBNDREGS, 64);
3072	#endif
3073	/** Pointer to a MPX bound register state. */
3074	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3075	/** Pointer to a const MPX bound register state. */
3076	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3077
3078	/**
3079	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3080	*/
3081	typedef struct X86XSAVEBNDCFG
3082	{
3083	uint64_t fConfig;
3084	uint64_t fStatus;
3085	} X86XSAVEBNDCFG;
3086	#ifndef VBOX_FOR_DTRACE_LIB
3087	AssertCompileSize(X86XSAVEBNDCFG, 16);
3088	#endif
3089	/** Pointer to a MPX bound config and status register state. */
3090	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3091	/** Pointer to a const MPX bound config and status register state. */
3092	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3093
3094	/**
3095	* AVX-512 opmask state (XSAVE_C_OPMASK).
3096	*/
3097	typedef struct X86XSAVEOPMASK
3098	{
3099	/** The K0..K7 values. */
3100	uint64_t aKRegs[8];
3101	} X86XSAVEOPMASK;
3102	#ifndef VBOX_FOR_DTRACE_LIB
3103	AssertCompileSize(X86XSAVEOPMASK, 64);
3104	#endif
3105	/** Pointer to a AVX-512 opmask state. */
3106	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3107	/** Pointer to a const AVX-512 opmask state. */
3108	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3109
3110	/**
3111	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3112	*/
3113	typedef struct X86XSAVEZMMHI256
3114	{
3115	/** Upper 256-bits of ZMM0-15. */
3116	X86YMMREG aHi256Regs[16];
3117	} X86XSAVEZMMHI256;
3118	#ifndef VBOX_FOR_DTRACE_LIB
3119	AssertCompileSize(X86XSAVEZMMHI256, 512);
3120	#endif
3121	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3122	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3123	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3124	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3125
3126	/**
3127	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3128	*/
3129	typedef struct X86XSAVEZMM16HI
3130	{
3131	/** ZMM16 thru ZMM31. */
3132	X86ZMMREG aRegs[16];
3133	} X86XSAVEZMM16HI;
3134	#ifndef VBOX_FOR_DTRACE_LIB
3135	AssertCompileSize(X86XSAVEZMM16HI, 1024);
3136	#endif
3137	/** Pointer to a state comprising ZMM16-32. */
3138	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3139	/** Pointer to a const state comprising ZMM16-32. */
3140	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3141
3142	/**
3143	* AMD Light weight profiling state (XSAVE_C_LWP).
3144	*
3145	* We probably won't play with this as AMD seems to be dropping from their "zen"
3146	* processor micro architecture.
3147	*/
3148	typedef struct X86XSAVELWP
3149	{
3150	/** Details when needed. */
3151	uint64_t auLater[128/8];
3152	} X86XSAVELWP;
3153	#ifndef VBOX_FOR_DTRACE_LIB
3154	AssertCompileSize(X86XSAVELWP, 128);
3155	#endif
3156
3157
3158	/**
3159	* x86 FPU/SSE/AVX/XXXX state.
3160	*
3161	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3162	* changes to this structure.
3163	*/
3164	typedef struct X86XSAVEAREA
3165	{
3166	/** The x87 and SSE region (or legacy region if you like). */
3167	X86FXSTATE x87;
3168	/** The XSAVE header. */
3169	X86XSAVEHDR Hdr;
3170	/** Beyond the header, there isn't really a fixed layout, but we can
3171	generally assume the YMM (AVX) register extensions are present and
3172	follows immediately. */
3173	union
3174	{
3175	/** The high 128-bit AVX registers for easy access by IEM.
3176	* @note This ASSUMES they will always be here... */
3177	X86XSAVEYMMHI YmmHi;
3178
3179	/** This is a typical layout on intel CPUs (good for debuggers). */
3180	struct
3181	{
3182	X86XSAVEYMMHI YmmHi;
3183	X86XSAVEBNDREGS BndRegs;
3184	X86XSAVEBNDCFG BndCfg;
3185	uint8_t abFudgeToMatchDocs[0xB0];
3186	X86XSAVEOPMASK Opmask;
3187	X86XSAVEZMMHI256 ZmmHi256;
3188	X86XSAVEZMM16HI Zmm16Hi;
3189	} Intel;
3190
3191	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3192	struct
3193	{
3194	X86XSAVEYMMHI YmmHi;
3195	X86XSAVELWP Lwp;
3196	} AmdBd;
3197
3198	/** To enbling static deployments that have a reasonable chance of working for
3199	* the next 3-6 CPU generations without running short on space, we allocate a
3200	* lot of extra space here, making the structure a round 8KB in size. This
3201	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3202	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3203	uint8_t ab[8192 - 512 - 64];
3204	} u;
3205	} X86XSAVEAREA;
3206	#ifndef VBOX_FOR_DTRACE_LIB
3207	AssertCompileSize(X86XSAVEAREA, 8192);
3208	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
3209	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3210	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3211	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3212	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3213	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3214	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3215	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3216	#endif
3217	/** Pointer to a XSAVE area. */
3218	typedef X86XSAVEAREA *PX86XSAVEAREA;
3219	/** Pointer to a const XSAVE area. */
3220	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3221
3222
3223	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3224	* @{ */
3225	/** Bit 0 - x87 - Legacy FPU state (bit number) */
3226	#define XSAVE_C_X87_BIT 0
3227	/** Bit 0 - x87 - Legacy FPU state. */
3228	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3229	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3230	#define XSAVE_C_SSE_BIT 1
3231	/** Bit 1 - SSE - 128-bit SSE state. */
3232	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3233	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3234	#define XSAVE_C_YMM_BIT 2
3235	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3236	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3237	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3238	#define XSAVE_C_BNDREGS_BIT 3
3239	/** Bit 3 - BNDREGS - MPX bound register state. */
3240	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3241	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3242	#define XSAVE_C_BNDCSR_BIT 4
3243	/** Bit 4 - BNDCSR - MPX bound config and status state. */
3244	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3245	/** Bit 5 - Opmask - opmask state (bit number). */
3246	#define XSAVE_C_OPMASK_BIT 5
3247	/** Bit 5 - Opmask - opmask state. */
3248	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3249	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3250	#define XSAVE_C_ZMM_HI256_BIT 6
3251	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3252	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3253	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3254	#define XSAVE_C_ZMM_16HI_BIT 7
3255	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3256	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3257	/** Bit 9 - PKRU - Protection-key state (bit number). */
3258	#define XSAVE_C_PKRU_BIT 9
3259	/** Bit 9 - PKRU - Protection-key state. */
3260	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3261	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3262	#define XSAVE_C_LWP_BIT 62
3263	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3264	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3265	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3266	#define XSAVE_C_X_BIT 63
3267	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3268	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3269	/** @} */
3270
3271
3272
3273	/** @name Selector Descriptor
3274	* @{
3275	*/
3276
3277	#ifndef VBOX_FOR_DTRACE_LIB
3278	/**
3279	* Descriptor attributes (as seen by VT-x).
3280	*/
3281	typedef struct X86DESCATTRBITS
3282	{
3283	/** 00 - Segment Type. */
3284	unsigned u4Type : 4;
3285	/** 04 - Descriptor Type. System(=0) or code/data selector */
3286	unsigned u1DescType : 1;
3287	/** 05 - Descriptor Privilege level. */
3288	unsigned u2Dpl : 2;
3289	/** 07 - Flags selector present(=1) or not. */
3290	unsigned u1Present : 1;
3291	/** 08 - Segment limit 16-19. */
3292	unsigned u4LimitHigh : 4;
3293	/** 0c - Available for system software. */
3294	unsigned u1Available : 1;
3295	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3296	unsigned u1Long : 1;
3297	/** 0e - This flags meaning depends on the segment type. Try make sense out
3298	* of the intel manual yourself. */
3299	unsigned u1DefBig : 1;
3300	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
3301	* clear byte. */
3302	unsigned u1Granularity : 1;
3303	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3304	unsigned u1Unusable : 1;
3305	} X86DESCATTRBITS;
3306	#endif /* !VBOX_FOR_DTRACE_LIB */
3307
3308	/** @name X86DESCATTR masks
3309	* @{ */
3310	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3311	#define X86DESCATTR_DT UINT32_C(0x00000010)
3312	#define X86DESCATTR_DPL UINT32_C(0x00000060)
3313	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
3314	#define X86DESCATTR_P UINT32_C(0x00000080)
3315	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3316	#define X86DESCATTR_AVL UINT32_C(0x00001000)
3317	#define X86DESCATTR_L UINT32_C(0x00002000)
3318	#define X86DESCATTR_D UINT32_C(0x00004000)
3319	#define X86DESCATTR_G UINT32_C(0x00008000)
3320	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3321	/** @} */
3322
3323	#pragma pack(1)
3324	typedef union X86DESCATTR
3325	{
3326	/** Unsigned integer view. */
3327	uint32_t u;
3328	#ifndef VBOX_FOR_DTRACE_LIB
3329	/** Normal view. */
3330	X86DESCATTRBITS n;
3331	#endif
3332	} X86DESCATTR;
3333	#pragma pack()
3334	/** Pointer to descriptor attributes. */
3335	typedef X86DESCATTR *PX86DESCATTR;
3336	/** Pointer to const descriptor attributes. */
3337	typedef const X86DESCATTR *PCX86DESCATTR;
3338
3339	#ifndef VBOX_FOR_DTRACE_LIB
3340
3341	/**
3342	* Generic descriptor table entry
3343	*/
3344	#pragma pack(1)
3345	typedef struct X86DESCGENERIC
3346	{
3347	/** 00 - Limit - Low word. */
3348	unsigned u16LimitLow : 16;
3349	/** 10 - Base address - low word.
3350	* Don't try set this to 24 because MSC is doing stupid things then. */
3351	unsigned u16BaseLow : 16;
3352	/** 20 - Base address - first 8 bits of high word. */
3353	unsigned u8BaseHigh1 : 8;
3354	/** 28 - Segment Type. */
3355	unsigned u4Type : 4;
3356	/** 2c - Descriptor Type. System(=0) or code/data selector */
3357	unsigned u1DescType : 1;
3358	/** 2d - Descriptor Privilege level. */
3359	unsigned u2Dpl : 2;
3360	/** 2f - Flags selector present(=1) or not. */
3361	unsigned u1Present : 1;
3362	/** 30 - Segment limit 16-19. */
3363	unsigned u4LimitHigh : 4;
3364	/** 34 - Available for system software. */
3365	unsigned u1Available : 1;
3366	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3367	unsigned u1Long : 1;
3368	/** 36 - This flags meaning depends on the segment type. Try make sense out
3369	* of the intel manual yourself. */
3370	unsigned u1DefBig : 1;
3371	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
3372	* clear byte. */
3373	unsigned u1Granularity : 1;
3374	/** 38 - Base address - highest 8 bits. */
3375	unsigned u8BaseHigh2 : 8;
3376	} X86DESCGENERIC;
3377	#pragma pack()
3378	/** Pointer to a generic descriptor entry. */
3379	typedef X86DESCGENERIC *PX86DESCGENERIC;
3380	/** Pointer to a const generic descriptor entry. */
3381	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3382
3383	/** @name Bit offsets of X86DESCGENERIC members.
3384	* @{*/
3385	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
3386	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
3387	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
3388	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
3389	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
3390	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
3391	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
3392	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
3393	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
3394	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
3395	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
3396	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
3397	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
3398	/** @} */
3399
3400
3401	/** @name LAR mask
3402	* @{ */
3403	#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3404	#define X86LAR_F_DT UINT16_C( 0x1000)
3405	#define X86LAR_F_DPL UINT16_C( 0x6000)
3406	#define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
3407	#define X86LAR_F_P UINT16_C( 0x8000)
3408	#define X86LAR_F_AVL UINT32_C(0x00100000)
3409	#define X86LAR_F_L UINT32_C(0x00200000)
3410	#define X86LAR_F_D UINT32_C(0x00400000)
3411	#define X86LAR_F_G UINT32_C(0x00800000)
3412	/** @} */
3413
3414
3415	/**
3416	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3417	*/
3418	typedef struct X86DESCGATE
3419	{
3420	/** 00 - Target code segment offset - Low word.
3421	* Ignored if task-gate. */
3422	unsigned u16OffsetLow : 16;
3423	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3424	* TSS selector if task-gate. */
3425	unsigned u16Sel : 16;
3426	/** 20 - Number of parameters for a call-gate.
3427	* Ignored if interrupt-, trap- or task-gate. */
3428	unsigned u5ParmCount : 5;
3429	/** 25 - Reserved / ignored. */
3430	unsigned u3Reserved : 3;
3431	/** 28 - Segment Type. */
3432	unsigned u4Type : 4;
3433	/** 2c - Descriptor Type (0 = system). */
3434	unsigned u1DescType : 1;
3435	/** 2d - Descriptor Privilege level. */
3436	unsigned u2Dpl : 2;
3437	/** 2f - Flags selector present(=1) or not. */
3438	unsigned u1Present : 1;
3439	/** 30 - Target code segment offset - High word.
3440	* Ignored if task-gate. */
3441	unsigned u16OffsetHigh : 16;
3442	} X86DESCGATE;
3443	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3444	typedef X86DESCGATE *PX86DESCGATE;
3445	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3446	typedef const X86DESCGATE *PCX86DESCGATE;
3447
3448	#endif /* VBOX_FOR_DTRACE_LIB */
3449
3450	/**
3451	* Descriptor table entry.
3452	*/
3453	#pragma pack(1)
3454	typedef union X86DESC
3455	{
3456	#ifndef VBOX_FOR_DTRACE_LIB
3457	/** Generic descriptor view. */
3458	X86DESCGENERIC Gen;
3459	/** Gate descriptor view. */
3460	X86DESCGATE Gate;
3461	#endif
3462
3463	/** 8 bit unsigned integer view. */
3464	uint8_t au8[8];
3465	/** 16 bit unsigned integer view. */
3466	uint16_t au16[4];
3467	/** 32 bit unsigned integer view. */
3468	uint32_t au32[2];
3469	/** 64 bit unsigned integer view. */
3470	uint64_t au64[1];
3471	/** Unsigned integer view. */
3472	uint64_t u;
3473	} X86DESC;
3474	#ifndef VBOX_FOR_DTRACE_LIB
3475	AssertCompileSize(X86DESC, 8);
3476	#endif
3477	#pragma pack()
3478	/** Pointer to descriptor table entry. */
3479	typedef X86DESC *PX86DESC;
3480	/** Pointer to const descriptor table entry. */
3481	typedef const X86DESC *PCX86DESC;
3482
3483	/** @def X86DESC_BASE
3484	* Return the base address of a descriptor.
3485	*/
3486	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
3487	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3488	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3489	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3490
3491	/** @def X86DESC_LIMIT
3492	* Return the limit of a descriptor.
3493	*/
3494	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
3495	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3496	\| ( (a_pDesc)->Gen.u16LimitLow ) )
3497
3498	/** @def X86DESC_LIMIT_G
3499	* Return the limit of a descriptor with the granularity bit taken into account.
3500	* @returns Selector limit (uint32_t).
3501	* @param a_pDesc Pointer to the descriptor.
3502	*/
3503	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
3504	( (a_pDesc)->Gen.u1Granularity \
3505	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
3506	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
3507	)
3508
3509	/** @def X86DESC_GET_HID_ATTR
3510	* Get the descriptor attributes for the hidden register.
3511	*/
3512	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
3513	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3514
3515	#ifndef VBOX_FOR_DTRACE_LIB
3516
3517	/**
3518	* 64 bits generic descriptor table entry
3519	* Note: most of these bits have no meaning in long mode.
3520	*/
3521	#pragma pack(1)
3522	typedef struct X86DESC64GENERIC
3523	{
3524	/** Limit - Low word - IGNORED. */
3525	uint32_t u16LimitLow : 16;
3526	/** Base address - low word. - IGNORED
3527	* Don't try set this to 24 because MSC is doing stupid things then. */
3528	uint32_t u16BaseLow : 16;
3529	/** Base address - first 8 bits of high word. - IGNORED */
3530	uint32_t u8BaseHigh1 : 8;
3531	/** Segment Type. */
3532	uint32_t u4Type : 4;
3533	/** Descriptor Type. System(=0) or code/data selector */
3534	uint32_t u1DescType : 1;
3535	/** Descriptor Privilege level. */
3536	uint32_t u2Dpl : 2;
3537	/** Flags selector present(=1) or not. */
3538	uint32_t u1Present : 1;
3539	/** Segment limit 16-19. - IGNORED */
3540	uint32_t u4LimitHigh : 4;
3541	/** Available for system software. - IGNORED */
3542	uint32_t u1Available : 1;
3543	/** Long mode flag. */
3544	uint32_t u1Long : 1;
3545	/** This flags meaning depends on the segment type. Try make sense out
3546	* of the intel manual yourself. */
3547	uint32_t u1DefBig : 1;
3548	/** Granularity of the limit. If set 4KB granularity is used, if
3549	* clear byte. - IGNORED */
3550	uint32_t u1Granularity : 1;
3551	/** Base address - highest 8 bits. - IGNORED */
3552	uint32_t u8BaseHigh2 : 8;
3553	/** Base address - bits 63-32. */
3554	uint32_t u32BaseHigh3 : 32;
3555	uint32_t u8Reserved : 8;
3556	uint32_t u5Zeros : 5;
3557	uint32_t u19Reserved : 19;
3558	} X86DESC64GENERIC;
3559	#pragma pack()
3560	/** Pointer to a generic descriptor entry. */
3561	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3562	/** Pointer to a const generic descriptor entry. */
3563	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3564
3565	/**
3566	* System descriptor table entry (64 bits)
3567	*
3568	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3569	*/
3570	#pragma pack(1)
3571	typedef struct X86DESC64SYSTEM
3572	{
3573	/** Limit - Low word. */
3574	uint32_t u16LimitLow : 16;
3575	/** Base address - low word.
3576	* Don't try set this to 24 because MSC is doing stupid things then. */
3577	uint32_t u16BaseLow : 16;
3578	/** Base address - first 8 bits of high word. */
3579	uint32_t u8BaseHigh1 : 8;
3580	/** Segment Type. */
3581	uint32_t u4Type : 4;
3582	/** Descriptor Type. System(=0) or code/data selector */
3583	uint32_t u1DescType : 1;
3584	/** Descriptor Privilege level. */
3585	uint32_t u2Dpl : 2;
3586	/** Flags selector present(=1) or not. */
3587	uint32_t u1Present : 1;
3588	/** Segment limit 16-19. */
3589	uint32_t u4LimitHigh : 4;
3590	/** Available for system software. */
3591	uint32_t u1Available : 1;
3592	/** Reserved - 0. */
3593	uint32_t u1Reserved : 1;
3594	/** This flags meaning depends on the segment type. Try make sense out
3595	* of the intel manual yourself. */
3596	uint32_t u1DefBig : 1;
3597	/** Granularity of the limit. If set 4KB granularity is used, if
3598	* clear byte. */
3599	uint32_t u1Granularity : 1;
3600	/** Base address - bits 31-24. */
3601	uint32_t u8BaseHigh2 : 8;
3602	/** Base address - bits 63-32. */
3603	uint32_t u32BaseHigh3 : 32;
3604	uint32_t u8Reserved : 8;
3605	uint32_t u5Zeros : 5;
3606	uint32_t u19Reserved : 19;
3607	} X86DESC64SYSTEM;
3608	#pragma pack()
3609	/** Pointer to a system descriptor entry. */
3610	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3611	/** Pointer to a const system descriptor entry. */
3612	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3613
3614	/**
3615	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3616	*/
3617	typedef struct X86DESC64GATE
3618	{
3619	/** Target code segment offset - Low word. */
3620	uint32_t u16OffsetLow : 16;
3621	/** Target code segment selector. */
3622	uint32_t u16Sel : 16;
3623	/** Interrupt stack table for interrupt- and trap-gates.
3624	* Ignored by call-gates. */
3625	uint32_t u3IST : 3;
3626	/** Reserved / ignored. */
3627	uint32_t u5Reserved : 5;
3628	/** Segment Type. */
3629	uint32_t u4Type : 4;
3630	/** Descriptor Type (0 = system). */
3631	uint32_t u1DescType : 1;
3632	/** Descriptor Privilege level. */
3633	uint32_t u2Dpl : 2;
3634	/** Flags selector present(=1) or not. */
3635	uint32_t u1Present : 1;
3636	/** Target code segment offset - High word.
3637	* Ignored if task-gate. */
3638	uint32_t u16OffsetHigh : 16;
3639	/** Target code segment offset - Top dword.
3640	* Ignored if task-gate. */
3641	uint32_t u32OffsetTop : 32;
3642	/** Reserved / ignored / must be zero.
3643	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3644	uint32_t u32Reserved : 32;
3645	} X86DESC64GATE;
3646	AssertCompileSize(X86DESC64GATE, 16);
3647	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3648	typedef X86DESC64GATE *PX86DESC64GATE;
3649	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3650	typedef const X86DESC64GATE *PCX86DESC64GATE;
3651
3652	#endif /* VBOX_FOR_DTRACE_LIB */
3653
3654	/**
3655	* Descriptor table entry.
3656	*/
3657	#pragma pack(1)
3658	typedef union X86DESC64
3659	{
3660	#ifndef VBOX_FOR_DTRACE_LIB
3661	/** Generic descriptor view. */
3662	X86DESC64GENERIC Gen;
3663	/** System descriptor view. */
3664	X86DESC64SYSTEM System;
3665	/** Gate descriptor view. */
3666	X86DESC64GATE Gate;
3667	#endif
3668
3669	/** 8 bit unsigned integer view. */
3670	uint8_t au8[16];
3671	/** 16 bit unsigned integer view. */
3672	uint16_t au16[8];
3673	/** 32 bit unsigned integer view. */
3674	uint32_t au32[4];
3675	/** 64 bit unsigned integer view. */
3676	uint64_t au64[2];
3677	} X86DESC64;
3678	#ifndef VBOX_FOR_DTRACE_LIB
3679	AssertCompileSize(X86DESC64, 16);
3680	#endif
3681	#pragma pack()
3682	/** Pointer to descriptor table entry. */
3683	typedef X86DESC64 *PX86DESC64;
3684	/** Pointer to const descriptor table entry. */
3685	typedef const X86DESC64 *PCX86DESC64;
3686
3687	/** @def X86DESC64_BASE
3688	* Return the base of a 64-bit descriptor.
3689	*/
3690	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
3691	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3692	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3693	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3694	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3695
3696
3697
3698	/** @name Host system descriptor table entry - Use with care!
3699	* @{ */
3700	/** Host system descriptor table entry. */
3701	#if HC_ARCH_BITS == 64
3702	typedef X86DESC64 X86DESCHC;
3703	#else
3704	typedef X86DESC X86DESCHC;
3705	#endif
3706	/** Pointer to a host system descriptor table entry. */
3707	#if HC_ARCH_BITS == 64
3708	typedef PX86DESC64 PX86DESCHC;
3709	#else
3710	typedef PX86DESC PX86DESCHC;
3711	#endif
3712	/** Pointer to a const host system descriptor table entry. */
3713	#if HC_ARCH_BITS == 64
3714	typedef PCX86DESC64 PCX86DESCHC;
3715	#else
3716	typedef PCX86DESC PCX86DESCHC;
3717	#endif
3718	/** @} */
3719
3720
3721	/** @name Selector Descriptor Types.
3722	* @{
3723	*/
3724
3725	/** @name Non-System Selector Types.
3726	* @{ */
3727	/** Code(=set)/Data(=clear) bit. */
3728	#define X86_SEL_TYPE_CODE 8
3729	/** Memory(=set)/System(=clear) bit. */
3730	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3731	/** Accessed bit. */
3732	#define X86_SEL_TYPE_ACCESSED 1
3733	/** Expand down bit (for data selectors only). */
3734	#define X86_SEL_TYPE_DOWN 4
3735	/** Conforming bit (for code selectors only). */
3736	#define X86_SEL_TYPE_CONF 4
3737	/** Write bit (for data selectors only). */
3738	#define X86_SEL_TYPE_WRITE 2
3739	/** Read bit (for code selectors only). */
3740	#define X86_SEL_TYPE_READ 2
3741	/** The bit number of the code segment read bit (relative to u4Type). */
3742	#define X86_SEL_TYPE_READ_BIT 1
3743
3744	/** Read only selector type. */
3745	#define X86_SEL_TYPE_RO 0
3746	/** Accessed read only selector type. */
3747	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
3748	/** Read write selector type. */
3749	#define X86_SEL_TYPE_RW 2
3750	/** Accessed read write selector type. */
3751	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
3752	/** Expand down read only selector type. */
3753	#define X86_SEL_TYPE_RO_DOWN 4
3754	/** Accessed expand down read only selector type. */
3755	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
3756	/** Expand down read write selector type. */
3757	#define X86_SEL_TYPE_RW_DOWN 6
3758	/** Accessed expand down read write selector type. */
3759	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
3760	/** Execute only selector type. */
3761	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
3762	/** Accessed execute only selector type. */
3763	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3764	/** Execute and read selector type. */
3765	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
3766	/** Accessed execute and read selector type. */
3767	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3768	/** Conforming execute only selector type. */
3769	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
3770	/** Accessed Conforming execute only selector type. */
3771	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3772	/** Conforming execute and write selector type. */
3773	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
3774	/** Accessed Conforming execute and write selector type. */
3775	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3776	/** @} */
3777
3778
3779	/** @name System Selector Types.
3780	* @{ */
3781	/** The TSS busy bit mask. */
3782	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3783
3784	/** Undefined system selector type. */
3785	#define X86_SEL_TYPE_SYS_UNDEFINED 0
3786	/** 286 TSS selector. */
3787	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3788	/** LDT selector. */
3789	#define X86_SEL_TYPE_SYS_LDT 2
3790	/** 286 TSS selector - Busy. */
3791	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3792	/** 286 Callgate selector. */
3793	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3794	/** Taskgate selector. */
3795	#define X86_SEL_TYPE_SYS_TASK_GATE 5
3796	/** 286 Interrupt gate selector. */
3797	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3798	/** 286 Trapgate selector. */
3799	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3800	/** Undefined system selector. */
3801	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3802	/** 386 TSS selector. */
3803	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3804	/** Undefined system selector. */
3805	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3806	/** 386 TSS selector - Busy. */
3807	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3808	/** 386 Callgate selector. */
3809	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3810	/** Undefined system selector. */
3811	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3812	/** 386 Interruptgate selector. */
3813	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3814	/** 386 Trapgate selector. */
3815	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3816	/** @} */
3817
3818	/** @name AMD64 System Selector Types.
3819	* @{ */
3820	/** LDT selector. */
3821	#define AMD64_SEL_TYPE_SYS_LDT 2
3822	/** TSS selector - Busy. */
3823	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3824	/** TSS selector - Busy. */
3825	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3826	/** Callgate selector. */
3827	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3828	/** Interruptgate selector. */
3829	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3830	/** Trapgate selector. */
3831	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3832	/** @} */
3833
3834	/** @} */
3835
3836
3837	/** @name Descriptor Table Entry Flag Masks.
3838	* These are for the 2nd 32-bit word of a descriptor.
3839	* @{ */
3840	/** Bits 8-11 - TYPE - Descriptor type mask. */
3841	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3842	/** Bit 12 - S - System (=0) or Code/Data (=1). */
3843	#define X86_DESC_S RT_BIT_32(12)
3844	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3845	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
3846	/** Bit 15 - P - Present. */
3847	#define X86_DESC_P RT_BIT_32(15)
3848	/** Bit 20 - AVL - Available for system software. */
3849	#define X86_DESC_AVL RT_BIT_32(20)
3850	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3851	#define X86_DESC_DB RT_BIT_32(22)
3852	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3853	* used, if clear byte. */
3854	#define X86_DESC_G RT_BIT_32(23)
3855	/** @} */
3856
3857	/** @} */
3858
3859
3860	/** @name Task Segments.
3861	* @{
3862	*/
3863
3864	/**
3865	* The minimum TSS descriptor limit for 286 tasks.
3866	*/
3867	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3868
3869	/**
3870	* The minimum TSS descriptor segment limit for 386 tasks.
3871	*/
3872	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3873
3874	/**
3875	* 16-bit Task Segment (TSS).
3876	*/
3877	#pragma pack(1)
3878	typedef struct X86TSS16
3879	{
3880	/** Back link to previous task. (static) */
3881	RTSEL selPrev;
3882	/** Ring-0 stack pointer. (static) */
3883	uint16_t sp0;
3884	/** Ring-0 stack segment. (static) */
3885	RTSEL ss0;
3886	/** Ring-1 stack pointer. (static) */
3887	uint16_t sp1;
3888	/** Ring-1 stack segment. (static) */
3889	RTSEL ss1;
3890	/** Ring-2 stack pointer. (static) */
3891	uint16_t sp2;
3892	/** Ring-2 stack segment. (static) */
3893	RTSEL ss2;
3894	/** IP before task switch. */
3895	uint16_t ip;
3896	/** FLAGS before task switch. */
3897	uint16_t flags;
3898	/** AX before task switch. */
3899	uint16_t ax;
3900	/** CX before task switch. */
3901	uint16_t cx;
3902	/** DX before task switch. */
3903	uint16_t dx;
3904	/** BX before task switch. */
3905	uint16_t bx;
3906	/** SP before task switch. */
3907	uint16_t sp;
3908	/** BP before task switch. */
3909	uint16_t bp;
3910	/** SI before task switch. */
3911	uint16_t si;
3912	/** DI before task switch. */
3913	uint16_t di;
3914	/** ES before task switch. */
3915	RTSEL es;
3916	/** CS before task switch. */
3917	RTSEL cs;
3918	/** SS before task switch. */
3919	RTSEL ss;
3920	/** DS before task switch. */
3921	RTSEL ds;
3922	/** LDTR before task switch. */
3923	RTSEL selLdt;
3924	} X86TSS16;
3925	#ifndef VBOX_FOR_DTRACE_LIB
3926	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
3927	#endif
3928	#pragma pack()
3929	/** Pointer to a 16-bit task segment. */
3930	typedef X86TSS16 *PX86TSS16;
3931	/** Pointer to a const 16-bit task segment. */
3932	typedef const X86TSS16 *PCX86TSS16;
3933
3934
3935	/**
3936	* 32-bit Task Segment (TSS).
3937	*/
3938	#pragma pack(1)
3939	typedef struct X86TSS32
3940	{
3941	/** Back link to previous task. (static) */
3942	RTSEL selPrev;
3943	uint16_t padding1;
3944	/** Ring-0 stack pointer. (static) */
3945	uint32_t esp0;
3946	/** Ring-0 stack segment. (static) */
3947	RTSEL ss0;
3948	uint16_t padding_ss0;
3949	/** Ring-1 stack pointer. (static) */
3950	uint32_t esp1;
3951	/** Ring-1 stack segment. (static) */
3952	RTSEL ss1;
3953	uint16_t padding_ss1;
3954	/** Ring-2 stack pointer. (static) */
3955	uint32_t esp2;
3956	/** Ring-2 stack segment. (static) */
3957	RTSEL ss2;
3958	uint16_t padding_ss2;
3959	/** Page directory for the task. (static) */
3960	uint32_t cr3;
3961	/** EIP before task switch. */
3962	uint32_t eip;
3963	/** EFLAGS before task switch. */
3964	uint32_t eflags;
3965	/** EAX before task switch. */
3966	uint32_t eax;
3967	/** ECX before task switch. */
3968	uint32_t ecx;
3969	/** EDX before task switch. */
3970	uint32_t edx;
3971	/** EBX before task switch. */
3972	uint32_t ebx;
3973	/** ESP before task switch. */
3974	uint32_t esp;
3975	/** EBP before task switch. */
3976	uint32_t ebp;
3977	/** ESI before task switch. */
3978	uint32_t esi;
3979	/** EDI before task switch. */
3980	uint32_t edi;
3981	/** ES before task switch. */
3982	RTSEL es;
3983	uint16_t padding_es;
3984	/** CS before task switch. */
3985	RTSEL cs;
3986	uint16_t padding_cs;
3987	/** SS before task switch. */
3988	RTSEL ss;
3989	uint16_t padding_ss;
3990	/** DS before task switch. */
3991	RTSEL ds;
3992	uint16_t padding_ds;
3993	/** FS before task switch. */
3994	RTSEL fs;
3995	uint16_t padding_fs;
3996	/** GS before task switch. */
3997	RTSEL gs;
3998	uint16_t padding_gs;
3999	/** LDTR before task switch. */
4000	RTSEL selLdt;
4001	uint16_t padding_ldt;
4002	/** Debug trap flag */
4003	uint16_t fDebugTrap;
4004	/** Offset relative to the TSS of the start of the I/O Bitmap
4005	* and the end of the interrupt redirection bitmap. */
4006	uint16_t offIoBitmap;
4007	} X86TSS32;
4008	#pragma pack()
4009	/** Pointer to task segment. */
4010	typedef X86TSS32 *PX86TSS32;
4011	/** Pointer to const task segment. */
4012	typedef const X86TSS32 *PCX86TSS32;
4013	#ifndef VBOX_FOR_DTRACE_LIB
4014	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4015	AssertCompileMemberOffset(X86TSS32, cr3, 28);
4016	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4017	#endif
4018
4019	/**
4020	* 64-bit Task segment.
4021	*/
4022	#pragma pack(1)
4023	typedef struct X86TSS64
4024	{
4025	/** Reserved. */
4026	uint32_t u32Reserved;
4027	/** Ring-0 stack pointer. (static) */
4028	uint64_t rsp0;
4029	/** Ring-1 stack pointer. (static) */
4030	uint64_t rsp1;
4031	/** Ring-2 stack pointer. (static) */
4032	uint64_t rsp2;
4033	/** Reserved. */
4034	uint32_t u32Reserved2[2];
4035	/* IST */
4036	uint64_t ist1;
4037	uint64_t ist2;
4038	uint64_t ist3;
4039	uint64_t ist4;
4040	uint64_t ist5;
4041	uint64_t ist6;
4042	uint64_t ist7;
4043	/* Reserved. */
4044	uint16_t u16Reserved[5];
4045	/** Offset relative to the TSS of the start of the I/O Bitmap
4046	* and the end of the interrupt redirection bitmap. */
4047	uint16_t offIoBitmap;
4048	} X86TSS64;
4049	#pragma pack()
4050	/** Pointer to a 64-bit task segment. */
4051	typedef X86TSS64 *PX86TSS64;
4052	/** Pointer to a const 64-bit task segment. */
4053	typedef const X86TSS64 *PCX86TSS64;
4054	#ifndef VBOX_FOR_DTRACE_LIB
4055	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4056	#endif
4057
4058	/** @} */
4059
4060
4061	/** @name Selectors.
4062	* @{
4063	*/
4064
4065	/**
4066	* The shift used to convert a selector from and to index an index (C).
4067	*/
4068	#define X86_SEL_SHIFT 3
4069
4070	/**
4071	* The mask used to mask off the table indicator and RPL of an selector.
4072	*/
4073	#define X86_SEL_MASK 0xfff8U
4074
4075	/**
4076	* The mask used to mask off the RPL of an selector.
4077	* This is suitable for checking for NULL selectors.
4078	*/
4079	#define X86_SEL_MASK_OFF_RPL 0xfffcU
4080
4081	/**
4082	* The bit indicating that a selector is in the LDT and not in the GDT.
4083	*/
4084	#define X86_SEL_LDT 0x0004U
4085
4086	/**
4087	* The bit mask for getting the RPL of a selector.
4088	*/
4089	#define X86_SEL_RPL 0x0003U
4090
4091	/**
4092	* The mask covering both RPL and LDT.
4093	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4094	* checks.
4095	*/
4096	#define X86_SEL_RPL_LDT 0x0007U
4097
4098	/** @} */
4099
4100
4101	/**
4102	* x86 Exceptions/Faults/Traps.
4103	*/
4104	typedef enum X86XCPT
4105	{
4106	/** \#DE - Divide error. */
4107	X86_XCPT_DE = 0x00,
4108	/** \#DB - Debug event (single step, DRx, ..) */
4109	X86_XCPT_DB = 0x01,
4110	/** NMI - Non-Maskable Interrupt */
4111	X86_XCPT_NMI = 0x02,
4112	/** \#BP - Breakpoint (INT3). */
4113	X86_XCPT_BP = 0x03,
4114	/** \#OF - Overflow (INTO). */
4115	X86_XCPT_OF = 0x04,
4116	/** \#BR - Bound range exceeded (BOUND). */
4117	X86_XCPT_BR = 0x05,
4118	/** \#UD - Undefined opcode. */
4119	X86_XCPT_UD = 0x06,
4120	/** \#NM - Device not available (math coprocessor device). */
4121	X86_XCPT_NM = 0x07,
4122	/** \#DF - Double fault. */
4123	X86_XCPT_DF = 0x08,
4124	/** ??? - Coprocessor segment overrun (obsolete). */
4125	X86_XCPT_CO_SEG_OVERRUN = 0x09,
4126	/** \#TS - Taskswitch (TSS). */
4127	X86_XCPT_TS = 0x0a,
4128	/** \#NP - Segment no present. */
4129	X86_XCPT_NP = 0x0b,
4130	/** \#SS - Stack segment fault. */
4131	X86_XCPT_SS = 0x0c,
4132	/** \#GP - General protection fault. */
4133	X86_XCPT_GP = 0x0d,
4134	/** \#PF - Page fault. */
4135	X86_XCPT_PF = 0x0e,
4136	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4137	/** \#MF - Math fault (FPU). */
4138	X86_XCPT_MF = 0x10,
4139	/** \#AC - Alignment check. */
4140	X86_XCPT_AC = 0x11,
4141	/** \#MC - Machine check. */
4142	X86_XCPT_MC = 0x12,
4143	/** \#XF - SIMD Floating-Pointer Exception. */
4144	X86_XCPT_XF = 0x13,
4145	/** \#VE - Virtualization Exception. */
4146	X86_XCPT_VE = 0x14,
4147	/** \#SX - Security Exception. */
4148	X86_XCPT_SX = 0x1e
4149	} X86XCPT;
4150	/** Pointer to a x86 exception code. */
4151	typedef X86XCPT *PX86XCPT;
4152	/** Pointer to a const x86 exception code. */
4153	typedef const X86XCPT *PCX86XCPT;
4154	/** The last valid (currently reserved) exception value. */
4155	#define X86_XCPT_LAST 0x1f
4156
4157
4158	/** @name Trap Error Codes
4159	* @{
4160	*/
4161	/** External indicator. */
4162	#define X86_TRAP_ERR_EXTERNAL 1
4163	/** IDT indicator. */
4164	#define X86_TRAP_ERR_IDT 2
4165	/** Descriptor table indicator - If set LDT, if clear GDT. */
4166	#define X86_TRAP_ERR_TI 4
4167	/** Mask for getting the selector. */
4168	#define X86_TRAP_ERR_SEL_MASK 0xfff8
4169	/** Shift for getting the selector table index (C type index). */
4170	#define X86_TRAP_ERR_SEL_SHIFT 3
4171	/** @} */
4172
4173
4174	/** @name \#PF Trap Error Codes
4175	* @{
4176	*/
4177	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4178	#define X86_TRAP_PF_P RT_BIT_32(0)
4179	/** Bit 1 - R/W - Read (clear) or write (set) access. */
4180	#define X86_TRAP_PF_RW RT_BIT_32(1)
4181	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4182	#define X86_TRAP_PF_US RT_BIT_32(2)
4183	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4184	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4185	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4186	#define X86_TRAP_PF_ID RT_BIT_32(4)
4187	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4188	#define X86_TRAP_PF_PK RT_BIT_32(5)
4189	/** @} */
4190
4191	#pragma pack(1)
4192	/**
4193	* 16-bit IDTR.
4194	*/
4195	typedef struct X86IDTR16
4196	{
4197	/** Offset. */
4198	uint16_t offSel;
4199	/** Selector. */
4200	uint16_t uSel;
4201	} X86IDTR16, *PX86IDTR16;
4202	#pragma pack()
4203
4204	#pragma pack(1)
4205	/**
4206	* 32-bit IDTR/GDTR.
4207	*/
4208	typedef struct X86XDTR32
4209	{
4210	/** Size of the descriptor table. */
4211	uint16_t cb;
4212	/** Address of the descriptor table. */
4213	#ifndef VBOX_FOR_DTRACE_LIB
4214	uint32_t uAddr;
4215	#else
4216	uint16_t au16Addr[2];
4217	#endif
4218	} X86XDTR32, *PX86XDTR32;
4219	#pragma pack()
4220
4221	#pragma pack(1)
4222	/**
4223	* 64-bit IDTR/GDTR.
4224	*/
4225	typedef struct X86XDTR64
4226	{
4227	/** Size of the descriptor table. */
4228	uint16_t cb;
4229	/** Address of the descriptor table. */
4230	#ifndef VBOX_FOR_DTRACE_LIB
4231	uint64_t uAddr;
4232	#else
4233	uint16_t au16Addr[4];
4234	#endif
4235	} X86XDTR64, *PX86XDTR64;
4236	#pragma pack()
4237
4238
4239	/** @name ModR/M
4240	* @{ */
4241	#define X86_MODRM_RM_MASK UINT8_C(0x07)
4242	#define X86_MODRM_REG_MASK UINT8_C(0x38)
4243	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4244	#define X86_MODRM_REG_SHIFT 3
4245	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4246	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4247	#define X86_MODRM_MOD_SHIFT 6
4248	#ifndef VBOX_FOR_DTRACE_LIB
4249	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
4250	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4251	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4252	/** @def X86_MODRM_MAKE
4253	* @param a_Mod The mod value (0..3).
4254	* @param a_Reg The register value (0..7).
4255	* @param a_RegMem The register or memory value (0..7). */
4256	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
4257	#endif
4258	/** @} */
4259
4260	/** @name SIB
4261	* @{ */
4262	#define X86_SIB_BASE_MASK UINT8_C(0x07)
4263	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4264	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4265	#define X86_SIB_INDEX_SHIFT 3
4266	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4267	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4268	#define X86_SIB_SCALE_SHIFT 6
4269	#ifndef VBOX_FOR_DTRACE_LIB
4270	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
4271	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4272	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4273	#endif
4274	/** @} */
4275
4276	/** @name General register indexes
4277	* @{ */
4278	#define X86_GREG_xAX 0
4279	#define X86_GREG_xCX 1
4280	#define X86_GREG_xDX 2
4281	#define X86_GREG_xBX 3
4282	#define X86_GREG_xSP 4
4283	#define X86_GREG_xBP 5
4284	#define X86_GREG_xSI 6
4285	#define X86_GREG_xDI 7
4286	#define X86_GREG_x8 8
4287	#define X86_GREG_x9 9
4288	#define X86_GREG_x10 10
4289	#define X86_GREG_x11 11
4290	#define X86_GREG_x12 12
4291	#define X86_GREG_x13 13
4292	#define X86_GREG_x14 14
4293	#define X86_GREG_x15 15
4294	/** @} */
4295
4296	/** @name X86_SREG_XXX - Segment register indexes.
4297	* @{ */
4298	#define X86_SREG_ES 0
4299	#define X86_SREG_CS 1
4300	#define X86_SREG_SS 2
4301	#define X86_SREG_DS 3
4302	#define X86_SREG_FS 4
4303	#define X86_SREG_GS 5
4304	/** @} */
4305	/** Segment register count. */
4306	#define X86_SREG_COUNT 6
4307
4308
4309	/** @name X86_OP_XXX - Prefixes
4310	* @{ */
4311	#define X86_OP_PRF_CS UINT8_C(0x2e)
4312	#define X86_OP_PRF_SS UINT8_C(0x36)
4313	#define X86_OP_PRF_DS UINT8_C(0x3e)
4314	#define X86_OP_PRF_ES UINT8_C(0x26)
4315	#define X86_OP_PRF_FS UINT8_C(0x64)
4316	#define X86_OP_PRF_GS UINT8_C(0x65)
4317	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4318	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4319	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4320	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4321	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4322	#define X86_OP_REX_B UINT8_C(0x41)
4323	#define X86_OP_REX_X UINT8_C(0x42)
4324	#define X86_OP_REX_R UINT8_C(0x44)
4325	#define X86_OP_REX_W UINT8_C(0x48)
4326	/** @} */
4327
4328
4329	/** @} */
4330
4331	#endif
4332

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source: vbox/trunk/include/iprt/x86.h@ 71755

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