VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 71586

Last change on this file since 71586 was 70913, checked in by vboxsync, 7 years ago

CPUM: Infrastructure for speculative execution control.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 160.9 KB
Line 
1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2017 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef ___iprt_x86_h
29#define ___iprt_x86_h
30
31#ifndef VBOX_FOR_DTRACE_LIB
32# include <iprt/types.h>
33# include <iprt/assert.h>
34#else
35# pragma D depends_on library vbox-types.d
36#endif
37
38/* Workaround for Solaris sys/regset.h defining CS, DS */
39#ifdef RT_OS_SOLARIS
40# undef CS
41# undef DS
42#endif
43
44/** @defgroup grp_rt_x86 x86 Types and Definitions
45 * @ingroup grp_rt
46 * @{
47 */
48
49#ifndef VBOX_FOR_DTRACE_LIB
50/**
51 * EFLAGS Bits.
52 */
53typedef struct X86EFLAGSBITS
54{
55 /** Bit 0 - CF - Carry flag - Status flag. */
56 unsigned u1CF : 1;
57 /** Bit 1 - 1 - Reserved flag. */
58 unsigned u1Reserved0 : 1;
59 /** Bit 2 - PF - Parity flag - Status flag. */
60 unsigned u1PF : 1;
61 /** Bit 3 - 0 - Reserved flag. */
62 unsigned u1Reserved1 : 1;
63 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64 unsigned u1AF : 1;
65 /** Bit 5 - 0 - Reserved flag. */
66 unsigned u1Reserved2 : 1;
67 /** Bit 6 - ZF - Zero flag - Status flag. */
68 unsigned u1ZF : 1;
69 /** Bit 7 - SF - Signed flag - Status flag. */
70 unsigned u1SF : 1;
71 /** Bit 8 - TF - Trap flag - System flag. */
72 unsigned u1TF : 1;
73 /** Bit 9 - IF - Interrupt flag - System flag. */
74 unsigned u1IF : 1;
75 /** Bit 10 - DF - Direction flag - Control flag. */
76 unsigned u1DF : 1;
77 /** Bit 11 - OF - Overflow flag - Status flag. */
78 unsigned u1OF : 1;
79 /** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
80 unsigned u2IOPL : 2;
81 /** Bit 14 - NT - Nested task flag - System flag. */
82 unsigned u1NT : 1;
83 /** Bit 15 - 0 - Reserved flag. */
84 unsigned u1Reserved3 : 1;
85 /** Bit 16 - RF - Resume flag - System flag. */
86 unsigned u1RF : 1;
87 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
88 unsigned u1VM : 1;
89 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90 unsigned u1AC : 1;
91 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92 unsigned u1VIF : 1;
93 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94 unsigned u1VIP : 1;
95 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96 unsigned u1ID : 1;
97 /** Bit 22-31 - 0 - Reserved flag. */
98 unsigned u10Reserved4 : 10;
99} X86EFLAGSBITS;
100/** Pointer to EFLAGS bits. */
101typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102/** Pointer to const EFLAGS bits. */
103typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104#endif /* !VBOX_FOR_DTRACE_LIB */
105
106/**
107 * EFLAGS.
108 */
109typedef union X86EFLAGS
110{
111 /** The plain unsigned view. */
112 uint32_t u;
113#ifndef VBOX_FOR_DTRACE_LIB
114 /** The bitfield view. */
115 X86EFLAGSBITS Bits;
116#endif
117 /** The 8-bit view. */
118 uint8_t au8[4];
119 /** The 16-bit view. */
120 uint16_t au16[2];
121 /** The 32-bit view. */
122 uint32_t au32[1];
123 /** The 32-bit view. */
124 uint32_t u32;
125} X86EFLAGS;
126/** Pointer to EFLAGS. */
127typedef X86EFLAGS *PX86EFLAGS;
128/** Pointer to const EFLAGS. */
129typedef const X86EFLAGS *PCX86EFLAGS;
130
131/**
132 * RFLAGS (32 upper bits are reserved).
133 */
134typedef union X86RFLAGS
135{
136 /** The plain unsigned view. */
137 uint64_t u;
138#ifndef VBOX_FOR_DTRACE_LIB
139 /** The bitfield view. */
140 X86EFLAGSBITS Bits;
141#endif
142 /** The 8-bit view. */
143 uint8_t au8[8];
144 /** The 16-bit view. */
145 uint16_t au16[4];
146 /** The 32-bit view. */
147 uint32_t au32[2];
148 /** The 64-bit view. */
149 uint64_t au64[1];
150 /** The 64-bit view. */
151 uint64_t u64;
152} X86RFLAGS;
153/** Pointer to RFLAGS. */
154typedef X86RFLAGS *PX86RFLAGS;
155/** Pointer to const RFLAGS. */
156typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159/** @name EFLAGS
160 * @{
161 */
162/** Bit 0 - CF - Carry flag - Status flag. */
163#define X86_EFL_CF RT_BIT_32(0)
164#define X86_EFL_CF_BIT 0
165/** Bit 1 - Reserved, reads as 1. */
166#define X86_EFL_1 RT_BIT_32(1)
167/** Bit 2 - PF - Parity flag - Status flag. */
168#define X86_EFL_PF RT_BIT_32(2)
169/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
170#define X86_EFL_AF RT_BIT_32(4)
171#define X86_EFL_AF_BIT 4
172/** Bit 6 - ZF - Zero flag - Status flag. */
173#define X86_EFL_ZF RT_BIT_32(6)
174#define X86_EFL_ZF_BIT 6
175/** Bit 7 - SF - Signed flag - Status flag. */
176#define X86_EFL_SF RT_BIT_32(7)
177#define X86_EFL_SF_BIT 7
178/** Bit 8 - TF - Trap flag - System flag. */
179#define X86_EFL_TF RT_BIT_32(8)
180/** Bit 9 - IF - Interrupt flag - System flag. */
181#define X86_EFL_IF RT_BIT_32(9)
182/** Bit 10 - DF - Direction flag - Control flag. */
183#define X86_EFL_DF RT_BIT_32(10)
184/** Bit 11 - OF - Overflow flag - Status flag. */
185#define X86_EFL_OF RT_BIT_32(11)
186#define X86_EFL_OF_BIT 11
187/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
188#define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
189/** Bit 14 - NT - Nested task flag - System flag. */
190#define X86_EFL_NT RT_BIT_32(14)
191/** Bit 16 - RF - Resume flag - System flag. */
192#define X86_EFL_RF RT_BIT_32(16)
193/** Bit 17 - VM - Virtual 8086 mode - System flag. */
194#define X86_EFL_VM RT_BIT_32(17)
195/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
196#define X86_EFL_AC RT_BIT_32(18)
197/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
198#define X86_EFL_VIF RT_BIT_32(19)
199/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
200#define X86_EFL_VIP RT_BIT_32(20)
201/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
202#define X86_EFL_ID RT_BIT_32(21)
203/** All live bits. */
204#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
205/** Read as 1 bits. */
206#define X86_EFL_RA1_MASK RT_BIT_32(1)
207/** IOPL shift. */
208#define X86_EFL_IOPL_SHIFT 12
209/** The IOPL level from the flags. */
210#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
211/** Bits restored by popf */
212#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
213 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
214/** Bits restored by popf */
215#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
216 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
217/** The status bits commonly updated by arithmetic instructions. */
218#define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
219/** @} */
220
221
222/** CPUID Feature information - ECX.
223 * CPUID query with EAX=1.
224 */
225#ifndef VBOX_FOR_DTRACE_LIB
226typedef struct X86CPUIDFEATECX
227{
228 /** Bit 0 - SSE3 - Supports SSE3 or not. */
229 unsigned u1SSE3 : 1;
230 /** Bit 1 - PCLMULQDQ. */
231 unsigned u1PCLMULQDQ : 1;
232 /** Bit 2 - DS Area 64-bit layout. */
233 unsigned u1DTE64 : 1;
234 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
235 unsigned u1Monitor : 1;
236 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
237 unsigned u1CPLDS : 1;
238 /** Bit 5 - VMX - Virtual Machine Technology. */
239 unsigned u1VMX : 1;
240 /** Bit 6 - SMX: Safer Mode Extensions. */
241 unsigned u1SMX : 1;
242 /** Bit 7 - EST - Enh. SpeedStep Tech. */
243 unsigned u1EST : 1;
244 /** Bit 8 - TM2 - Terminal Monitor 2. */
245 unsigned u1TM2 : 1;
246 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
247 unsigned u1SSSE3 : 1;
248 /** Bit 10 - CNTX-ID - L1 Context ID. */
249 unsigned u1CNTXID : 1;
250 /** Bit 11 - Reserved. */
251 unsigned u1Reserved1 : 1;
252 /** Bit 12 - FMA. */
253 unsigned u1FMA : 1;
254 /** Bit 13 - CX16 - CMPXCHG16B. */
255 unsigned u1CX16 : 1;
256 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
257 unsigned u1TPRUpdate : 1;
258 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
259 unsigned u1PDCM : 1;
260 /** Bit 16 - Reserved. */
261 unsigned u1Reserved2 : 1;
262 /** Bit 17 - PCID - Process-context identifiers. */
263 unsigned u1PCID : 1;
264 /** Bit 18 - Direct Cache Access. */
265 unsigned u1DCA : 1;
266 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
267 unsigned u1SSE4_1 : 1;
268 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
269 unsigned u1SSE4_2 : 1;
270 /** Bit 21 - x2APIC. */
271 unsigned u1x2APIC : 1;
272 /** Bit 22 - MOVBE - Supports MOVBE. */
273 unsigned u1MOVBE : 1;
274 /** Bit 23 - POPCNT - Supports POPCNT. */
275 unsigned u1POPCNT : 1;
276 /** Bit 24 - TSC-Deadline. */
277 unsigned u1TSCDEADLINE : 1;
278 /** Bit 25 - AES. */
279 unsigned u1AES : 1;
280 /** Bit 26 - XSAVE - Supports XSAVE. */
281 unsigned u1XSAVE : 1;
282 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
283 unsigned u1OSXSAVE : 1;
284 /** Bit 28 - AVX - Supports AVX instruction extensions. */
285 unsigned u1AVX : 1;
286 /** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
287 unsigned u1F16C : 1;
288 /** Bit 30 - RDRAND - Supports RDRAND. */
289 unsigned u1RDRAND : 1;
290 /** Bit 31 - Hypervisor present (we're a guest). */
291 unsigned u1HVP : 1;
292} X86CPUIDFEATECX;
293#else /* VBOX_FOR_DTRACE_LIB */
294typedef uint32_t X86CPUIDFEATECX;
295#endif /* VBOX_FOR_DTRACE_LIB */
296/** Pointer to CPUID Feature Information - ECX. */
297typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
298/** Pointer to const CPUID Feature Information - ECX. */
299typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
300
301
302/** CPUID Feature Information - EDX.
303 * CPUID query with EAX=1.
304 */
305#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
306typedef struct X86CPUIDFEATEDX
307{
308 /** Bit 0 - FPU - x87 FPU on Chip. */
309 unsigned u1FPU : 1;
310 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
311 unsigned u1VME : 1;
312 /** Bit 2 - DE - Debugging extensions. */
313 unsigned u1DE : 1;
314 /** Bit 3 - PSE - Page Size Extension. */
315 unsigned u1PSE : 1;
316 /** Bit 4 - TSC - Time Stamp Counter. */
317 unsigned u1TSC : 1;
318 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
319 unsigned u1MSR : 1;
320 /** Bit 6 - PAE - Physical Address Extension. */
321 unsigned u1PAE : 1;
322 /** Bit 7 - MCE - Machine Check Exception. */
323 unsigned u1MCE : 1;
324 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
325 unsigned u1CX8 : 1;
326 /** Bit 9 - APIC - APIC On-Chip. */
327 unsigned u1APIC : 1;
328 /** Bit 10 - Reserved. */
329 unsigned u1Reserved1 : 1;
330 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
331 unsigned u1SEP : 1;
332 /** Bit 12 - MTRR - Memory Type Range Registers. */
333 unsigned u1MTRR : 1;
334 /** Bit 13 - PGE - PTE Global Bit. */
335 unsigned u1PGE : 1;
336 /** Bit 14 - MCA - Machine Check Architecture. */
337 unsigned u1MCA : 1;
338 /** Bit 15 - CMOV - Conditional Move Instructions. */
339 unsigned u1CMOV : 1;
340 /** Bit 16 - PAT - Page Attribute Table. */
341 unsigned u1PAT : 1;
342 /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
343 unsigned u1PSE36 : 1;
344 /** Bit 18 - PSN - Processor Serial Number. */
345 unsigned u1PSN : 1;
346 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
347 unsigned u1CLFSH : 1;
348 /** Bit 20 - Reserved. */
349 unsigned u1Reserved2 : 1;
350 /** Bit 21 - DS - Debug Store. */
351 unsigned u1DS : 1;
352 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
353 unsigned u1ACPI : 1;
354 /** Bit 23 - MMX - Intel MMX 'Technology'. */
355 unsigned u1MMX : 1;
356 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
357 unsigned u1FXSR : 1;
358 /** Bit 25 - SSE - SSE Support. */
359 unsigned u1SSE : 1;
360 /** Bit 26 - SSE2 - SSE2 Support. */
361 unsigned u1SSE2 : 1;
362 /** Bit 27 - SS - Self Snoop. */
363 unsigned u1SS : 1;
364 /** Bit 28 - HTT - Hyper-Threading Technology. */
365 unsigned u1HTT : 1;
366 /** Bit 29 - TM - Thermal Monitor. */
367 unsigned u1TM : 1;
368 /** Bit 30 - Reserved - . */
369 unsigned u1Reserved3 : 1;
370 /** Bit 31 - PBE - Pending Break Enabled. */
371 unsigned u1PBE : 1;
372} X86CPUIDFEATEDX;
373#else /* VBOX_FOR_DTRACE_LIB */
374typedef uint32_t X86CPUIDFEATEDX;
375#endif /* VBOX_FOR_DTRACE_LIB */
376/** Pointer to CPUID Feature Information - EDX. */
377typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
378/** Pointer to const CPUID Feature Information - EDX. */
379typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
380
381/** @name CPUID Vendor information.
382 * CPUID query with EAX=0.
383 * @{
384 */
385#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
386#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
387#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
388
389#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
390#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
391#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
392
393#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
394#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
395#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
396/** @} */
397
398
399/** @name CPUID Feature information.
400 * CPUID query with EAX=1.
401 * @{
402 */
403/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
404#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
405/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
406#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
407/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
408#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
409/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
410#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
411/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
412#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
413/** ECX Bit 5 - VMX - Virtual Machine Technology. */
414#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
415/** ECX Bit 6 - SMX - Safer Mode Extensions. */
416#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
417/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
418#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
419/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
420#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
421/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
422#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
423/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
424#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
425/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
426 * See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
427#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
428/** ECX Bit 12 - FMA. */
429#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
430/** ECX Bit 13 - CX16 - CMPXCHG16B. */
431#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
432/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
433#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
434/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
435#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
436/** ECX Bit 17 - PCID - Process-context identifiers. */
437#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
438/** ECX Bit 18 - DCA - Direct Cache Access. */
439#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
440/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
441#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
442/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
443#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
444/** ECX Bit 21 - x2APIC support. */
445#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
446/** ECX Bit 22 - MOVBE instruction. */
447#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
448/** ECX Bit 23 - POPCNT instruction. */
449#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
450/** ECX Bir 24 - TSC-Deadline. */
451#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
452/** ECX Bit 25 - AES instructions. */
453#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
454/** ECX Bit 26 - XSAVE instruction. */
455#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
456/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
457#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
458/** ECX Bit 28 - AVX. */
459#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
460/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
461#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
462/** ECX Bit 30 - RDRAND instruction. */
463#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
464/** ECX Bit 31 - Hypervisor Present (software only). */
465#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
466
467
468/** Bit 0 - FPU - x87 FPU on Chip. */
469#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
470/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
471#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
472/** Bit 2 - DE - Debugging extensions. */
473#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
474/** Bit 3 - PSE - Page Size Extension. */
475#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
476#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /**< Bit number for X86_CPUID_FEATURE_EDX_PSE. */
477/** Bit 4 - TSC - Time Stamp Counter. */
478#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
479/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
480#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
481/** Bit 6 - PAE - Physical Address Extension. */
482#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
483#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /**< Bit number for X86_CPUID_FEATURE_EDX_PAE. */
484/** Bit 7 - MCE - Machine Check Exception. */
485#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
486/** Bit 8 - CX8 - CMPXCHG8B instruction. */
487#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
488/** Bit 9 - APIC - APIC On-Chip. */
489#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
490/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
491#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
492/** Bit 12 - MTRR - Memory Type Range Registers. */
493#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
494/** Bit 13 - PGE - PTE Global Bit. */
495#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
496/** Bit 14 - MCA - Machine Check Architecture. */
497#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
498/** Bit 15 - CMOV - Conditional Move Instructions. */
499#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
500/** Bit 16 - PAT - Page Attribute Table. */
501#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
502/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
503#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
504/** Bit 18 - PSN - Processor Serial Number. */
505#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
506/** Bit 19 - CLFSH - CLFLUSH Instruction. */
507#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
508/** Bit 21 - DS - Debug Store. */
509#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
510/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
511#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
512/** Bit 23 - MMX - Intel MMX Technology. */
513#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
514/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
515#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
516/** Bit 25 - SSE - SSE Support. */
517#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
518/** Bit 26 - SSE2 - SSE2 Support. */
519#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
520/** Bit 27 - SS - Self Snoop. */
521#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
522/** Bit 28 - HTT - Hyper-Threading Technology. */
523#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
524/** Bit 29 - TM - Therm. Monitor. */
525#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
526/** Bit 31 - PBE - Pending Break Enabled. */
527#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
528/** @} */
529
530/** @name CPUID mwait/monitor information.
531 * CPUID query with EAX=5.
532 * @{
533 */
534/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
535#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
536/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
537#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
538/** @} */
539
540
541/** @name CPUID Structured Extended Feature information.
542 * CPUID query with EAX=7.
543 * @{
544 */
545/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
546#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
547/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
548#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
549/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
550#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
551/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
552#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
553/** EBX Bit 4 - HLE - Hardware Lock Elision. */
554#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
555/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
556#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
557/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
558#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
559/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
560#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
561/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
562#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
563/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
564#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
565/** EBX Bit 10 - INVPCID - Supports INVPCID. */
566#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
567/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
568#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
569/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
570#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
571/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
572#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
573/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
574#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
575/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
576#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
577/** EBX Bit 16 - AVX512F - Supports AVX512F. */
578#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
579/** EBX Bit 18 - RDSEED - Supports RDSEED. */
580#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
581/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
582#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
583/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
584#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
585/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
586#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
587/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
588#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
589/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
590#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
591/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
592#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
593/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
594#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
595/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
596#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
597
598/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
599#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
600/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
601#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
602/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
603#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
604/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
605#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
606/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
607#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
608/** ECX Bit 22 - RDPID - Support pread process ID. */
609#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
610/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
611#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
612
613/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
614 * IBPB command in IA32_PRED_CMD. */
615#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
616/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
617#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
618
619/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
620#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
621
622/** @} */
623
624
625/** @name CPUID Extended Feature information.
626 * CPUID query with EAX=0x80000001.
627 * @{
628 */
629/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
630#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
631
632/** EDX Bit 11 - SYSCALL/SYSRET. */
633#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
634/** EDX Bit 20 - No-Execute/Execute-Disable. */
635#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
636/** EDX Bit 26 - 1 GB large page. */
637#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
638/** EDX Bit 27 - RDTSCP. */
639#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
640/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
641#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
642/** @}*/
643
644/** @name CPUID AMD Feature information.
645 * CPUID query with EAX=0x80000001.
646 * @{
647 */
648/** Bit 0 - FPU - x87 FPU on Chip. */
649#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
650/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
651#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
652/** Bit 2 - DE - Debugging extensions. */
653#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
654/** Bit 3 - PSE - Page Size Extension. */
655#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
656/** Bit 4 - TSC - Time Stamp Counter. */
657#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
658/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
659#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
660/** Bit 6 - PAE - Physical Address Extension. */
661#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
662/** Bit 7 - MCE - Machine Check Exception. */
663#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
664/** Bit 8 - CX8 - CMPXCHG8B instruction. */
665#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
666/** Bit 9 - APIC - APIC On-Chip. */
667#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
668/** Bit 12 - MTRR - Memory Type Range Registers. */
669#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
670/** Bit 13 - PGE - PTE Global Bit. */
671#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
672/** Bit 14 - MCA - Machine Check Architecture. */
673#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
674/** Bit 15 - CMOV - Conditional Move Instructions. */
675#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
676/** Bit 16 - PAT - Page Attribute Table. */
677#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
678/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
679#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
680/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
681#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
682/** Bit 23 - MMX - Intel MMX Technology. */
683#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
684/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
685#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
686/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
687#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
688/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
689#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
690/** Bit 31 - 3DNOW - AMD 3DNow. */
691#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
692
693/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
694#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
695/** Bit 2 - SVM - AMD VM extensions. */
696#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
697/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
698#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
699/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
700#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
701/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
702#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
703/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
704#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
705/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
706#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
707/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
708#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
709/** Bit 9 - OSVW - AMD OS visible workaround. */
710#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
711/** Bit 10 - IBS - Instruct based sampling. */
712#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
713/** Bit 11 - XOP - Extended operation support (see APM6). */
714#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
715/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
716#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
717/** Bit 13 - WDT - AMD Watchdog timer support. */
718#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
719/** Bit 15 - LWP - Lightweight profiling support. */
720#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
721/** Bit 16 - FMA4 - Four operand FMA instruction support. */
722#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
723/** Bit 19 - NodeId - Indicates support for
724 * MSR_C001_100C[NodeId,NodesPerProcessr]. */
725#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
726/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
727#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
728/** Bit 22 - TopologyExtensions - . */
729#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
730/** @} */
731
732
733/** @name CPUID AMD Feature information.
734 * CPUID query with EAX=0x80000007.
735 * @{
736 */
737/** Bit 0 - TS - Temperature Sensor. */
738#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
739/** Bit 1 - FID - Frequency ID Control. */
740#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
741/** Bit 2 - VID - Voltage ID Control. */
742#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
743/** Bit 3 - TTP - THERMTRIP. */
744#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
745/** Bit 4 - TM - Hardware Thermal Control. */
746#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
747/** Bit 5 - STC - Software Thermal Control. */
748#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
749/** Bit 6 - MC - 100 Mhz Multiplier Control. */
750#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
751/** Bit 7 - HWPSTATE - Hardware P-State Control. */
752#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
753/** Bit 8 - TSCINVAR - TSC Invariant. */
754#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
755/** Bit 9 - CPB - TSC Invariant. */
756#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
757/** Bit 10 - EffFreqRO - MPERF/APERF. */
758#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
759/** Bit 11 - PFI - Processor feedback interface (see EAX). */
760#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
761/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
762#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
763/** @} */
764
765
766/** @name CPUID AMD extended feature extensions ID (EBX).
767 * CPUID query with EAX=0x80000008.
768 * @{
769 */
770/** Bit 0 - CLZERO - Clear zero instruction. */
771#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
772/** Bit 1 - IRPerf - Instructions retired count support. */
773#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
774/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
775#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
776/* AMD pipeline length: 9 feature bits ;-) */
777/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
778#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
779/** @} */
780
781
782/** @name CPUID AMD SVM Feature information.
783 * CPUID query with EAX=0x8000000a.
784 * @{
785 */
786/** Bit 0 - NP - Nested Paging supported. */
787#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
788/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
789#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
790/** Bit 2 - SVML - SVM locking bit supported. */
791#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
792/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
793#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
794/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
795#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
796/** Bit 5 - VmcbClean - Support VMCB clean bits. */
797#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
798/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
799 * VMCB.TLB_Control is supported. */
800#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
801/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
802#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
803/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
804#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
805/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
806 * intercept filter cycle count threshold. */
807#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
808/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
809#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
810/** Bit 15 - V_VMSAVE_VMLOAD - Supports virtualized VMSAVE/VMLOAD. */
811#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
812/** Bit 16 - V_VMSAVE_VMLOAD - Supports virtualized GIF. */
813#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
814/** @} */
815
816
817/** @name CR0
818 * @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
819 * reserved flags.
820 * @{ */
821/** Bit 0 - PE - Protection Enabled */
822#define X86_CR0_PE RT_BIT_32(0)
823#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
824/** Bit 1 - MP - Monitor Coprocessor */
825#define X86_CR0_MP RT_BIT_32(1)
826#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
827/** Bit 2 - EM - Emulation. */
828#define X86_CR0_EM RT_BIT_32(2)
829#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
830/** Bit 3 - TS - Task Switch. */
831#define X86_CR0_TS RT_BIT_32(3)
832#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
833/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
834#define X86_CR0_ET RT_BIT_32(4)
835#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
836/** Bit 5 - NE - Numeric error (486+). */
837#define X86_CR0_NE RT_BIT_32(5)
838#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
839/** Bit 16 - WP - Write Protect (486+). */
840#define X86_CR0_WP RT_BIT_32(16)
841#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
842/** Bit 18 - AM - Alignment Mask (486+). */
843#define X86_CR0_AM RT_BIT_32(18)
844#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
845/** Bit 29 - NW - Not Write-though (486+). */
846#define X86_CR0_NW RT_BIT_32(29)
847#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
848/** Bit 30 - WP - Cache Disable (486+). */
849#define X86_CR0_CD RT_BIT_32(30)
850#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
851/** Bit 31 - PG - Paging. */
852#define X86_CR0_PG RT_BIT_32(31)
853#define X86_CR0_PAGING RT_BIT_32(31)
854/** @} */
855
856
857/** @name CR3
858 * @{ */
859/** Bit 3 - PWT - Page-level Writes Transparent. */
860#define X86_CR3_PWT RT_BIT_32(3)
861/** Bit 4 - PCD - Page-level Cache Disable. */
862#define X86_CR3_PCD RT_BIT_32(4)
863/** Bits 12-31 - - Page directory page number. */
864#define X86_CR3_PAGE_MASK (0xfffff000)
865/** Bits 5-31 - - PAE Page directory page number. */
866#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
867/** Bits 12-51 - - AMD64 Page directory page number. */
868#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
869/** @} */
870
871
872/** @name CR4
873 * @{ */
874/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
875#define X86_CR4_VME RT_BIT_32(0)
876/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
877#define X86_CR4_PVI RT_BIT_32(1)
878/** Bit 2 - TSD - Time Stamp Disable. */
879#define X86_CR4_TSD RT_BIT_32(2)
880/** Bit 3 - DE - Debugging Extensions. */
881#define X86_CR4_DE RT_BIT_32(3)
882/** Bit 4 - PSE - Page Size Extension. */
883#define X86_CR4_PSE RT_BIT_32(4)
884/** Bit 5 - PAE - Physical Address Extension. */
885#define X86_CR4_PAE RT_BIT_32(5)
886/** Bit 6 - MCE - Machine-Check Enable. */
887#define X86_CR4_MCE RT_BIT_32(6)
888/** Bit 7 - PGE - Page Global Enable. */
889#define X86_CR4_PGE RT_BIT_32(7)
890/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
891#define X86_CR4_PCE RT_BIT_32(8)
892/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
893#define X86_CR4_OSFXSR RT_BIT_32(9)
894/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
895#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
896/** Bit 13 - VMXE - VMX mode is enabled. */
897#define X86_CR4_VMXE RT_BIT_32(13)
898/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
899#define X86_CR4_SMXE RT_BIT_32(14)
900/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
901#define X86_CR4_FSGSBASE RT_BIT_32(16)
902/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
903#define X86_CR4_PCIDE RT_BIT_32(17)
904/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
905 * extended states. */
906#define X86_CR4_OSXSAVE RT_BIT_32(18)
907/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
908#define X86_CR4_SMEP RT_BIT_32(20)
909/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
910#define X86_CR4_SMAP RT_BIT_32(21)
911/** Bit 22 - PKE - Protection Key Enable. */
912#define X86_CR4_PKE RT_BIT_32(22)
913/** @} */
914
915
916/** @name DR6
917 * @{ */
918/** Bit 0 - B0 - Breakpoint 0 condition detected. */
919#define X86_DR6_B0 RT_BIT_32(0)
920/** Bit 1 - B1 - Breakpoint 1 condition detected. */
921#define X86_DR6_B1 RT_BIT_32(1)
922/** Bit 2 - B2 - Breakpoint 2 condition detected. */
923#define X86_DR6_B2 RT_BIT_32(2)
924/** Bit 3 - B3 - Breakpoint 3 condition detected. */
925#define X86_DR6_B3 RT_BIT_32(3)
926/** Mask of all the Bx bits. */
927#define X86_DR6_B_MASK UINT64_C(0x0000000f)
928/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
929#define X86_DR6_BD RT_BIT_32(13)
930/** Bit 14 - BS - Single step */
931#define X86_DR6_BS RT_BIT_32(14)
932/** Bit 15 - BT - Task switch. (TSS T bit.) */
933#define X86_DR6_BT RT_BIT_32(15)
934/** Value of DR6 after powerup/reset. */
935#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
936/** Bits which must be 1s in DR6. */
937#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
938/** Bits which must be 0s in DR6. */
939#define X86_DR6_RAZ_MASK RT_BIT_64(12)
940/** Bits which must be 0s on writes to DR6. */
941#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
942/** @} */
943
944/** Get the DR6.Bx bit for a the given breakpoint. */
945#define X86_DR6_B(iBp) RT_BIT_64(iBp)
946
947
948/** @name DR7
949 * @{ */
950/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
951#define X86_DR7_L0 RT_BIT_32(0)
952/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
953#define X86_DR7_G0 RT_BIT_32(1)
954/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
955#define X86_DR7_L1 RT_BIT_32(2)
956/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
957#define X86_DR7_G1 RT_BIT_32(3)
958/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
959#define X86_DR7_L2 RT_BIT_32(4)
960/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
961#define X86_DR7_G2 RT_BIT_32(5)
962/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
963#define X86_DR7_L3 RT_BIT_32(6)
964/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
965#define X86_DR7_G3 RT_BIT_32(7)
966/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
967#define X86_DR7_LE RT_BIT_32(8)
968/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
969#define X86_DR7_GE RT_BIT_32(9)
970
971/** L0, L1, L2, and L3. */
972#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
973/** L0, L1, L2, and L3. */
974#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
975
976/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
977 * Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
978 * May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
979 * instruction is executed.
980 * @see http://www.rcollins.org/secrets/DR7.html */
981#define X86_DR7_ICE_IR RT_BIT_32(12)
982/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
983 * any DR register is accessed. */
984#define X86_DR7_GD RT_BIT_32(13)
985/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
986 * Pentium. */
987#define X86_DR7_ICE_TR1 RT_BIT_32(14)
988/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
989#define X86_DR7_ICE_TR2 RT_BIT_32(15)
990/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
991#define X86_DR7_RW0_MASK (3 << 16)
992/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
993#define X86_DR7_LEN0_MASK (3 << 18)
994/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
995#define X86_DR7_RW1_MASK (3 << 20)
996/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
997#define X86_DR7_LEN1_MASK (3 << 22)
998/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
999#define X86_DR7_RW2_MASK (3 << 24)
1000/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
1001#define X86_DR7_LEN2_MASK (3 << 26)
1002/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
1003#define X86_DR7_RW3_MASK (3 << 28)
1004/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
1005#define X86_DR7_LEN3_MASK (3 << 30)
1006
1007/** Bits which reads as 1s. */
1008#define X86_DR7_RA1_MASK RT_BIT_32(10)
1009/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1010#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1011/** Bits which must be 0s when writing to DR7. */
1012#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1013
1014/** Calcs the L bit of Nth breakpoint.
1015 * @param iBp The breakpoint number [0..3].
1016 */
1017#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1018
1019/** Calcs the G bit of Nth breakpoint.
1020 * @param iBp The breakpoint number [0..3].
1021 */
1022#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1023
1024/** Calcs the L and G bits of Nth breakpoint.
1025 * @param iBp The breakpoint number [0..3].
1026 */
1027#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1028
1029/** @name Read/Write values.
1030 * @{ */
1031/** Break on instruction fetch only. */
1032#define X86_DR7_RW_EO 0U
1033/** Break on write only. */
1034#define X86_DR7_RW_WO 1U
1035/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1036#define X86_DR7_RW_IO 2U
1037/** Break on read or write (but not instruction fetches). */
1038#define X86_DR7_RW_RW 3U
1039/** @} */
1040
1041/** Shifts a X86_DR7_RW_* value to its right place.
1042 * @param iBp The breakpoint number [0..3].
1043 * @param fRw One of the X86_DR7_RW_* value.
1044 */
1045#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1046
1047/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1048 * one of the X86_DR7_RW_XXX constants).
1049 *
1050 * @returns X86_DR7_RW_XXX
1051 * @param uDR7 DR7 value
1052 * @param iBp The breakpoint number [0..3].
1053 */
1054#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1055
1056/** R/W0, R/W1, R/W2, and R/W3. */
1057#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1058
1059#ifndef VBOX_FOR_DTRACE_LIB
1060/** Checks if there are any I/O breakpoint types configured in the RW
1061 * registers. Does NOT check if these are enabled, sorry. */
1062# define X86_DR7_ANY_RW_IO(uDR7) \
1063 ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1064 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1065AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1066AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1067AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1068AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1069AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1070AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1071AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1072AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1073AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1074#endif /* !VBOX_FOR_DTRACE_LIB */
1075
1076/** @name Length values.
1077 * @{ */
1078#define X86_DR7_LEN_BYTE 0U
1079#define X86_DR7_LEN_WORD 1U
1080#define X86_DR7_LEN_QWORD 2U /**< AMD64 long mode only. */
1081#define X86_DR7_LEN_DWORD 3U
1082/** @} */
1083
1084/** Shifts a X86_DR7_LEN_* value to its right place.
1085 * @param iBp The breakpoint number [0..3].
1086 * @param cb One of the X86_DR7_LEN_* values.
1087 */
1088#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1089
1090/** Fetch the breakpoint length bits from the DR7 value.
1091 * @param uDR7 DR7 value
1092 * @param iBp The breakpoint number [0..3].
1093 */
1094#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1095
1096/** Mask used to check if any breakpoints are enabled. */
1097#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1098
1099/** LEN0, LEN1, LEN2, and LEN3. */
1100#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1101/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1102#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1103
1104/** Value of DR7 after powerup/reset. */
1105#define X86_DR7_INIT_VAL 0x400
1106/** @} */
1107
1108
1109/** @name Machine Specific Registers
1110 * @{
1111 */
1112/** Machine check address register (P5). */
1113#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1114/** Machine check type register (P5). */
1115#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1116/** Time Stamp Counter. */
1117#define MSR_IA32_TSC 0x10
1118#define MSR_IA32_CESR UINT32_C(0x00000011)
1119#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1120#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1121
1122#define MSR_IA32_PLATFORM_ID 0x17
1123
1124#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1125# define MSR_IA32_APICBASE 0x1b
1126/** Local APIC enabled. */
1127# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1128/** X2APIC enabled (requires the EN bit to be set). */
1129# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1130/** The processor is the boot strap processor (BSP). */
1131# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1132/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1133 * width. */
1134# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1135/** The default physical base address of the APIC. */
1136# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1137/** Gets the physical base address from the MSR. */
1138# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1139#endif
1140
1141/** Undocumented intel MSR for reporting thread and core counts.
1142 * Judging from the XNU sources, it seems to be introduced in Nehalem. The
1143 * first 16 bits is the thread count. The next 16 bits the core count, except
1144 * on Westmere where it seems it's only the next 4 bits for some reason. */
1145#define MSR_CORE_THREAD_COUNT 0x35
1146
1147/** CPU Feature control. */
1148#define MSR_IA32_FEATURE_CONTROL 0x3A
1149#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_32(0)
1150#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_32(1)
1151#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_32(2)
1152
1153/** Per-processor TSC adjust MSR. */
1154#define MSR_IA32_TSC_ADJUST 0x3B
1155
1156/** Spectre control register.
1157 * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1158#define MSR_IA32_SPEC_CTRL 0x48
1159/** IBRS - Indirect branch restricted speculation. */
1160#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1161/** STIBP - Single thread indirect branch predictors. */
1162#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1163
1164/** Prediction command register.
1165 * Write only, logical processor scope, no state since write only. */
1166#define MSR_IA32_PRED_CMD 0x49
1167/** IBPB - Indirect branch prediction barrie when written as 1. */
1168#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1169
1170/** BIOS update trigger (microcode update). */
1171#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1172
1173/** BIOS update signature (microcode). */
1174#define MSR_IA32_BIOS_SIGN_ID 0x8B
1175
1176/** SMM monitor control. */
1177#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1178
1179/** General performance counter no. 0. */
1180#define MSR_IA32_PMC0 0xC1
1181/** General performance counter no. 1. */
1182#define MSR_IA32_PMC1 0xC2
1183/** General performance counter no. 2. */
1184#define MSR_IA32_PMC2 0xC3
1185/** General performance counter no. 3. */
1186#define MSR_IA32_PMC3 0xC4
1187
1188/** Nehalem power control. */
1189#define MSR_IA32_PLATFORM_INFO 0xCE
1190
1191/** Get FSB clock status (Intel-specific). */
1192#define MSR_IA32_FSB_CLOCK_STS 0xCD
1193
1194/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1195#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1196
1197/** C0 Maximum Frequency Clock Count */
1198#define MSR_IA32_MPERF 0xE7
1199/** C0 Actual Frequency Clock Count */
1200#define MSR_IA32_APERF 0xE8
1201
1202/** MTRR Capabilities. */
1203#define MSR_IA32_MTRR_CAP 0xFE
1204
1205/** Architecture capabilities (bugfixes).
1206 * @note May move */
1207#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1208/** CPU is no subject to spectre problems. */
1209#define MSR_IA32_ARCH_CAP_F_SPECTRE_FIX RT_BIT_32(0)
1210/** CPU has better IBRS and you can leave it on all the time. */
1211#define MSR_IA32_ARCH_CAP_F_BETTER_IBRS RT_BIT_32(1)
1212
1213/** Cache control/info. */
1214#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1215
1216#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1217/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1218 * R0 SS == CS + 8
1219 * R3 CS == CS + 16
1220 * R3 SS == CS + 24
1221 */
1222#define MSR_IA32_SYSENTER_CS 0x174
1223/** SYSENTER_ESP - the R0 ESP. */
1224#define MSR_IA32_SYSENTER_ESP 0x175
1225/** SYSENTER_EIP - the R0 EIP. */
1226#define MSR_IA32_SYSENTER_EIP 0x176
1227#endif
1228
1229/** Machine Check Global Capabilities Register. */
1230#define MSR_IA32_MCG_CAP 0x179
1231/** Machine Check Global Status Register. */
1232#define MSR_IA32_MCG_STATUS 0x17A
1233/** Machine Check Global Control Register. */
1234#define MSR_IA32_MCG_CTRL 0x17B
1235
1236/** Page Attribute Table. */
1237#define MSR_IA32_CR_PAT 0x277
1238
1239/** Performance counter MSRs. (Intel only) */
1240#define MSR_IA32_PERFEVTSEL0 0x186
1241#define MSR_IA32_PERFEVTSEL1 0x187
1242/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1243 * The 16th bit whether flex ratio is being used, in which case bits 15:8
1244 * holds a ratio that Apple takes for TSC granularity.
1245 *
1246 * @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1247#define MSR_FLEX_RATIO 0x194
1248/** Performance state value and starting with Intel core more.
1249 * Apple uses the >=core features to determine TSC granularity on older CPUs. */
1250#define MSR_IA32_PERF_STATUS 0x198
1251#define MSR_IA32_PERF_CTL 0x199
1252#define MSR_IA32_THERM_STATUS 0x19c
1253
1254/** Enable misc. processor features (R/W). */
1255#define MSR_IA32_MISC_ENABLE 0x1A0
1256/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1257#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1258/** Automatic Thermal Control Circuit Enable (R/W). */
1259#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1260/** Performance Monitoring Available (R). */
1261#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1262/** Branch Trace Storage Unavailable (R/O). */
1263#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1264/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1265#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1266/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1267#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1268/** If MONITOR/MWAIT is supported (R/W). */
1269#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1270/** Limit CPUID Maxval to 3 leafs (R/W). */
1271#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1272/** When set to 1, xTPR messages are disabled (R/W). */
1273#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1274/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1275#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1276
1277/** Trace/Profile Resource Control (R/W) */
1278#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1279/** Last branch record. */
1280#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1281/** Branch trace flag (single step on branches). */
1282#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1283/** Performance monitoring pin control (AMD only). */
1284#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1285#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1286#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1287#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1288/** Trace message enable (Intel only). */
1289#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1290/** Branch trace store (Intel only). */
1291#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1292/** Branch trace interrupt (Intel only). */
1293#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1294/** Branch trace off in privileged code (Intel only). */
1295#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1296/** Branch trace off in user code (Intel only). */
1297#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1298/** Freeze LBR on PMI flag (Intel only). */
1299#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1300/** Freeze PERFMON on PMI flag (Intel only). */
1301#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1302/** Freeze while SMM enabled (Intel only). */
1303#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1304/** Advanced debugging of RTM regions (Intel only). */
1305#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1306
1307/** The number (0..3 or 0..15) of the last branch record register on P4 and
1308 * related Xeons. */
1309#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1310/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1311 * @{ */
1312#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1313#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1314#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1315#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1316/** @} */
1317
1318
1319#define IA32_MTRR_PHYSBASE0 0x200
1320#define IA32_MTRR_PHYSMASK0 0x201
1321#define IA32_MTRR_PHYSBASE1 0x202
1322#define IA32_MTRR_PHYSMASK1 0x203
1323#define IA32_MTRR_PHYSBASE2 0x204
1324#define IA32_MTRR_PHYSMASK2 0x205
1325#define IA32_MTRR_PHYSBASE3 0x206
1326#define IA32_MTRR_PHYSMASK3 0x207
1327#define IA32_MTRR_PHYSBASE4 0x208
1328#define IA32_MTRR_PHYSMASK4 0x209
1329#define IA32_MTRR_PHYSBASE5 0x20a
1330#define IA32_MTRR_PHYSMASK5 0x20b
1331#define IA32_MTRR_PHYSBASE6 0x20c
1332#define IA32_MTRR_PHYSMASK6 0x20d
1333#define IA32_MTRR_PHYSBASE7 0x20e
1334#define IA32_MTRR_PHYSMASK7 0x20f
1335#define IA32_MTRR_PHYSBASE8 0x210
1336#define IA32_MTRR_PHYSMASK8 0x211
1337#define IA32_MTRR_PHYSBASE9 0x212
1338#define IA32_MTRR_PHYSMASK9 0x213
1339
1340/** Fixed range MTRRs.
1341 * @{ */
1342#define IA32_MTRR_FIX64K_00000 0x250
1343#define IA32_MTRR_FIX16K_80000 0x258
1344#define IA32_MTRR_FIX16K_A0000 0x259
1345#define IA32_MTRR_FIX4K_C0000 0x268
1346#define IA32_MTRR_FIX4K_C8000 0x269
1347#define IA32_MTRR_FIX4K_D0000 0x26a
1348#define IA32_MTRR_FIX4K_D8000 0x26b
1349#define IA32_MTRR_FIX4K_E0000 0x26c
1350#define IA32_MTRR_FIX4K_E8000 0x26d
1351#define IA32_MTRR_FIX4K_F0000 0x26e
1352#define IA32_MTRR_FIX4K_F8000 0x26f
1353/** @} */
1354
1355/** MTRR Default Range. */
1356#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1357
1358/** Global performance counter control facilities (Intel only). */
1359#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1360#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1361#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1362
1363/** Precise Event Based sampling (Intel only). */
1364#define MSR_IA32_PEBS_ENABLE 0x3F1
1365
1366#define MSR_IA32_MC0_CTL 0x400
1367#define MSR_IA32_MC0_STATUS 0x401
1368
1369/** Basic VMX information. */
1370#define MSR_IA32_VMX_BASIC_INFO 0x480
1371/** Allowed settings for pin-based VM execution controls */
1372#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1373/** Allowed settings for proc-based VM execution controls */
1374#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1375/** Allowed settings for the VMX exit controls. */
1376#define MSR_IA32_VMX_EXIT_CTLS 0x483
1377/** Allowed settings for the VMX entry controls. */
1378#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1379/** Misc VMX info. */
1380#define MSR_IA32_VMX_MISC 0x485
1381/** Fixed cleared bits in CR0. */
1382#define MSR_IA32_VMX_CR0_FIXED0 0x486
1383/** Fixed set bits in CR0. */
1384#define MSR_IA32_VMX_CR0_FIXED1 0x487
1385/** Fixed cleared bits in CR4. */
1386#define MSR_IA32_VMX_CR4_FIXED0 0x488
1387/** Fixed set bits in CR4. */
1388#define MSR_IA32_VMX_CR4_FIXED1 0x489
1389/** Information for enumerating fields in the VMCS. */
1390#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1391/** Allowed settings for the VM-functions controls. */
1392#define MSR_IA32_VMX_VMFUNC 0x491
1393/** Allowed settings for secondary proc-based VM execution controls */
1394#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1395/** EPT capabilities. */
1396#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1397/** Allowed settings of all pin-based VM execution controls. */
1398#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1399/** Allowed settings of all proc-based VM execution controls. */
1400#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1401/** Allowed settings of all VMX exit controls. */
1402#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1403/** Allowed settings of all VMX entry controls. */
1404#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1405
1406/** DS Save Area (R/W). */
1407#define MSR_IA32_DS_AREA 0x600
1408/** Running Average Power Limit (RAPL) power units. */
1409#define MSR_RAPL_POWER_UNIT 0x606
1410
1411/** X2APIC MSR range start. */
1412#define MSR_IA32_X2APIC_START 0x800
1413/** X2APIC MSR - APIC ID Register. */
1414#define MSR_IA32_X2APIC_ID 0x802
1415/** X2APIC MSR - APIC Version Register. */
1416#define MSR_IA32_X2APIC_VERSION 0x803
1417/** X2APIC MSR - Task Priority Register. */
1418#define MSR_IA32_X2APIC_TPR 0x808
1419/** X2APIC MSR - Processor Priority register. */
1420#define MSR_IA32_X2APIC_PPR 0x80A
1421/** X2APIC MSR - End Of Interrupt register. */
1422#define MSR_IA32_X2APIC_EOI 0x80B
1423/** X2APIC MSR - Logical Destination Register. */
1424#define MSR_IA32_X2APIC_LDR 0x80D
1425/** X2APIC MSR - Spurious Interrupt Vector Register. */
1426#define MSR_IA32_X2APIC_SVR 0x80F
1427/** X2APIC MSR - In-service Register (bits 31:0). */
1428#define MSR_IA32_X2APIC_ISR0 0x810
1429/** X2APIC MSR - In-service Register (bits 63:32). */
1430#define MSR_IA32_X2APIC_ISR1 0x811
1431/** X2APIC MSR - In-service Register (bits 95:64). */
1432#define MSR_IA32_X2APIC_ISR2 0x812
1433/** X2APIC MSR - In-service Register (bits 127:96). */
1434#define MSR_IA32_X2APIC_ISR3 0x813
1435/** X2APIC MSR - In-service Register (bits 159:128). */
1436#define MSR_IA32_X2APIC_ISR4 0x814
1437/** X2APIC MSR - In-service Register (bits 191:160). */
1438#define MSR_IA32_X2APIC_ISR5 0x815
1439/** X2APIC MSR - In-service Register (bits 223:192). */
1440#define MSR_IA32_X2APIC_ISR6 0x816
1441/** X2APIC MSR - In-service Register (bits 255:224). */
1442#define MSR_IA32_X2APIC_ISR7 0x817
1443/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1444#define MSR_IA32_X2APIC_TMR0 0x818
1445/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1446#define MSR_IA32_X2APIC_TMR1 0x819
1447/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1448#define MSR_IA32_X2APIC_TMR2 0x81A
1449/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1450#define MSR_IA32_X2APIC_TMR3 0x81B
1451/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1452#define MSR_IA32_X2APIC_TMR4 0x81C
1453/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1454#define MSR_IA32_X2APIC_TMR5 0x81D
1455/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1456#define MSR_IA32_X2APIC_TMR6 0x81E
1457/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1458#define MSR_IA32_X2APIC_TMR7 0x81F
1459/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1460#define MSR_IA32_X2APIC_IRR0 0x820
1461/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1462#define MSR_IA32_X2APIC_IRR1 0x821
1463/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1464#define MSR_IA32_X2APIC_IRR2 0x822
1465/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1466#define MSR_IA32_X2APIC_IRR3 0x823
1467/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1468#define MSR_IA32_X2APIC_IRR4 0x824
1469/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1470#define MSR_IA32_X2APIC_IRR5 0x825
1471/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1472#define MSR_IA32_X2APIC_IRR6 0x826
1473/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1474#define MSR_IA32_X2APIC_IRR7 0x827
1475/** X2APIC MSR - Error Status Register. */
1476#define MSR_IA32_X2APIC_ESR 0x828
1477/** X2APIC MSR - LVT CMCI Register. */
1478#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1479/** X2APIC MSR - Interrupt Command Register. */
1480#define MSR_IA32_X2APIC_ICR 0x830
1481/** X2APIC MSR - LVT Timer Register. */
1482#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1483/** X2APIC MSR - LVT Thermal Sensor Register. */
1484#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1485/** X2APIC MSR - LVT Performance Counter Register. */
1486#define MSR_IA32_X2APIC_LVT_PERF 0x834
1487/** X2APIC MSR - LVT LINT0 Register. */
1488#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1489/** X2APIC MSR - LVT LINT1 Register. */
1490#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1491/** X2APIC MSR - LVT Error Register . */
1492#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1493/** X2APIC MSR - Timer Initial Count Register. */
1494#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1495/** X2APIC MSR - Timer Current Count Register. */
1496#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1497/** X2APIC MSR - Timer Divide Configuration Register. */
1498#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1499/** X2APIC MSR - Self IPI. */
1500#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1501/** X2APIC MSR range end. */
1502#define MSR_IA32_X2APIC_END 0xBFF
1503/** X2APIC MSR - LVT start range. */
1504#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1505/** X2APIC MSR - LVT end range (inclusive). */
1506#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1507
1508/** K6 EFER - Extended Feature Enable Register. */
1509#define MSR_K6_EFER UINT32_C(0xc0000080)
1510/** @todo document EFER */
1511/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1512#define MSR_K6_EFER_SCE RT_BIT_32(0)
1513/** Bit 8 - LME - Long mode enabled. (R/W) */
1514#define MSR_K6_EFER_LME RT_BIT_32(8)
1515/** Bit 10 - LMA - Long mode active. (R) */
1516#define MSR_K6_EFER_LMA RT_BIT_32(10)
1517/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1518#define MSR_K6_EFER_NXE RT_BIT_32(11)
1519#define MSR_K6_EFER_BIT_NXE 11 /**< Bit number of MSR_K6_EFER_NXE */
1520/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1521#define MSR_K6_EFER_SVME RT_BIT_32(12)
1522/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1523#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1524/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1525#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1526/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1527#define MSR_K6_EFER_TCE RT_BIT_32(15)
1528/** K6 STAR - SYSCALL/RET targets. */
1529#define MSR_K6_STAR UINT32_C(0xc0000081)
1530/** Shift value for getting the SYSRET CS and SS value. */
1531#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1532/** Shift value for getting the SYSCALL CS and SS value. */
1533#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1534/** Selector mask for use after shifting. */
1535#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1536/** The mask which give the SYSCALL EIP. */
1537#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1538/** K6 WHCR - Write Handling Control Register. */
1539#define MSR_K6_WHCR UINT32_C(0xc0000082)
1540/** K6 UWCCR - UC/WC Cacheability Control Register. */
1541#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1542/** K6 PSOR - Processor State Observability Register. */
1543#define MSR_K6_PSOR UINT32_C(0xc0000087)
1544/** K6 PFIR - Page Flush/Invalidate Register. */
1545#define MSR_K6_PFIR UINT32_C(0xc0000088)
1546
1547/** Performance counter MSRs. (AMD only) */
1548#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1549#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1550#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1551#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1552#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1553#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1554#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1555#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1556
1557/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1558#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1559/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1560#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1561/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1562#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1563/** K8 FS.base - The 64-bit base FS register. */
1564#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1565/** K8 GS.base - The 64-bit base GS register. */
1566#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1567/** K8 KernelGSbase - Used with SWAPGS. */
1568#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1569/** K8 TSC_AUX - Used with RDTSCP. */
1570#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1571#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1572#define MSR_K8_HWCR UINT32_C(0xc0010015)
1573#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1574#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1575#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1576#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1577#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1578#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1579/** North bridge config? See BIOS & Kernel dev guides for
1580 * details. */
1581#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1582
1583/** Hypertransport interrupt pending register.
1584 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1585#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1586
1587/** SVM Control. */
1588#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1589/** Disables HDT (Hardware Debug Tool) and certain internal debug
1590 * features. */
1591#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1592/** If set, non-intercepted INIT signals are converted to \#SX
1593 * exceptions. */
1594#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1595/** Disables A20 masking. */
1596#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1597/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1598#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1599/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1600 * clear, EFER.SVME can be written normally. */
1601#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1602
1603#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1604#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1605/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1606 * host state during world switch. */
1607#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1608
1609/** @} */
1610
1611
1612/** @name Page Table / Directory / Directory Pointers / L4.
1613 * @{
1614 */
1615
1616/** Page table/directory entry as an unsigned integer. */
1617typedef uint32_t X86PGUINT;
1618/** Pointer to a page table/directory table entry as an unsigned integer. */
1619typedef X86PGUINT *PX86PGUINT;
1620/** Pointer to an const page table/directory table entry as an unsigned integer. */
1621typedef X86PGUINT const *PCX86PGUINT;
1622
1623/** Number of entries in a 32-bit PT/PD. */
1624#define X86_PG_ENTRIES 1024
1625
1626
1627/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1628typedef uint64_t X86PGPAEUINT;
1629/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1630typedef X86PGPAEUINT *PX86PGPAEUINT;
1631/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1632typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1633
1634/** Number of entries in a PAE PT/PD. */
1635#define X86_PG_PAE_ENTRIES 512
1636/** Number of entries in a PAE PDPT. */
1637#define X86_PG_PAE_PDPE_ENTRIES 4
1638
1639/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1640#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1641/** Number of entries in an AMD64 PDPT.
1642 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1643#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1644
1645/** The size of a default page. */
1646#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1647/** The page shift of a default page. */
1648#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1649/** The default page offset mask. */
1650#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1651/** The default page base mask for virtual addresses. */
1652#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1653/** The default page base mask for virtual addresses - 32bit version. */
1654#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1655
1656/** The size of a 4KB page. */
1657#define X86_PAGE_4K_SIZE _4K
1658/** The page shift of a 4KB page. */
1659#define X86_PAGE_4K_SHIFT 12
1660/** The 4KB page offset mask. */
1661#define X86_PAGE_4K_OFFSET_MASK 0xfff
1662/** The 4KB page base mask for virtual addresses. */
1663#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1664/** The 4KB page base mask for virtual addresses - 32bit version. */
1665#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1666
1667/** The size of a 2MB page. */
1668#define X86_PAGE_2M_SIZE _2M
1669/** The page shift of a 2MB page. */
1670#define X86_PAGE_2M_SHIFT 21
1671/** The 2MB page offset mask. */
1672#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1673/** The 2MB page base mask for virtual addresses. */
1674#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1675/** The 2MB page base mask for virtual addresses - 32bit version. */
1676#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1677
1678/** The size of a 4MB page. */
1679#define X86_PAGE_4M_SIZE _4M
1680/** The page shift of a 4MB page. */
1681#define X86_PAGE_4M_SHIFT 22
1682/** The 4MB page offset mask. */
1683#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1684/** The 4MB page base mask for virtual addresses. */
1685#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1686/** The 4MB page base mask for virtual addresses - 32bit version. */
1687#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1688
1689/**
1690 * Check if the given address is canonical.
1691 */
1692#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1693
1694
1695/** @name Page Table Entry
1696 * @{
1697 */
1698/** Bit 0 - P - Present bit. */
1699#define X86_PTE_BIT_P 0
1700/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1701#define X86_PTE_BIT_RW 1
1702/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1703#define X86_PTE_BIT_US 2
1704/** Bit 3 - PWT - Page level write thru bit. */
1705#define X86_PTE_BIT_PWT 3
1706/** Bit 4 - PCD - Page level cache disable bit. */
1707#define X86_PTE_BIT_PCD 4
1708/** Bit 5 - A - Access bit. */
1709#define X86_PTE_BIT_A 5
1710/** Bit 6 - D - Dirty bit. */
1711#define X86_PTE_BIT_D 6
1712/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1713#define X86_PTE_BIT_PAT 7
1714/** Bit 8 - G - Global flag. */
1715#define X86_PTE_BIT_G 8
1716/** Bits 63 - NX - PAE/LM - No execution flag. */
1717#define X86_PTE_PAE_BIT_NX 63
1718
1719/** Bit 0 - P - Present bit mask. */
1720#define X86_PTE_P RT_BIT_32(0)
1721/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1722#define X86_PTE_RW RT_BIT_32(1)
1723/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1724#define X86_PTE_US RT_BIT_32(2)
1725/** Bit 3 - PWT - Page level write thru bit mask. */
1726#define X86_PTE_PWT RT_BIT_32(3)
1727/** Bit 4 - PCD - Page level cache disable bit mask. */
1728#define X86_PTE_PCD RT_BIT_32(4)
1729/** Bit 5 - A - Access bit mask. */
1730#define X86_PTE_A RT_BIT_32(5)
1731/** Bit 6 - D - Dirty bit mask. */
1732#define X86_PTE_D RT_BIT_32(6)
1733/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1734#define X86_PTE_PAT RT_BIT_32(7)
1735/** Bit 8 - G - Global bit mask. */
1736#define X86_PTE_G RT_BIT_32(8)
1737
1738/** Bits 9-11 - - Available for use to system software. */
1739#define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1740/** Bits 12-31 - - Physical Page number of the next level. */
1741#define X86_PTE_PG_MASK ( 0xfffff000 )
1742
1743/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1744#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1745/** Bits 63 - NX - PAE/LM - No execution flag. */
1746#define X86_PTE_PAE_NX RT_BIT_64(63)
1747/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1748#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1749/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1750#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1751/** No bits - - LM - MBZ bits when NX is active. */
1752#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1753/** Bits 63 - - LM - MBZ bits when no NX. */
1754#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1755
1756/**
1757 * Page table entry.
1758 */
1759typedef struct X86PTEBITS
1760{
1761 /** Flags whether(=1) or not the page is present. */
1762 uint32_t u1Present : 1;
1763 /** Read(=0) / Write(=1) flag. */
1764 uint32_t u1Write : 1;
1765 /** User(=1) / Supervisor (=0) flag. */
1766 uint32_t u1User : 1;
1767 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1768 uint32_t u1WriteThru : 1;
1769 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1770 uint32_t u1CacheDisable : 1;
1771 /** Accessed flag.
1772 * Indicates that the page have been read or written to. */
1773 uint32_t u1Accessed : 1;
1774 /** Dirty flag.
1775 * Indicates that the page has been written to. */
1776 uint32_t u1Dirty : 1;
1777 /** Reserved / If PAT enabled, bit 2 of the index. */
1778 uint32_t u1PAT : 1;
1779 /** Global flag. (Ignored in all but final level.) */
1780 uint32_t u1Global : 1;
1781 /** Available for use to system software. */
1782 uint32_t u3Available : 3;
1783 /** Physical Page number of the next level. */
1784 uint32_t u20PageNo : 20;
1785} X86PTEBITS;
1786#ifndef VBOX_FOR_DTRACE_LIB
1787AssertCompileSize(X86PTEBITS, 4);
1788#endif
1789/** Pointer to a page table entry. */
1790typedef X86PTEBITS *PX86PTEBITS;
1791/** Pointer to a const page table entry. */
1792typedef const X86PTEBITS *PCX86PTEBITS;
1793
1794/**
1795 * Page table entry.
1796 */
1797typedef union X86PTE
1798{
1799 /** Unsigned integer view */
1800 X86PGUINT u;
1801 /** Bit field view. */
1802 X86PTEBITS n;
1803 /** 32-bit view. */
1804 uint32_t au32[1];
1805 /** 16-bit view. */
1806 uint16_t au16[2];
1807 /** 8-bit view. */
1808 uint8_t au8[4];
1809} X86PTE;
1810#ifndef VBOX_FOR_DTRACE_LIB
1811AssertCompileSize(X86PTE, 4);
1812#endif
1813/** Pointer to a page table entry. */
1814typedef X86PTE *PX86PTE;
1815/** Pointer to a const page table entry. */
1816typedef const X86PTE *PCX86PTE;
1817
1818
1819/**
1820 * PAE page table entry.
1821 */
1822typedef struct X86PTEPAEBITS
1823{
1824 /** Flags whether(=1) or not the page is present. */
1825 uint32_t u1Present : 1;
1826 /** Read(=0) / Write(=1) flag. */
1827 uint32_t u1Write : 1;
1828 /** User(=1) / Supervisor(=0) flag. */
1829 uint32_t u1User : 1;
1830 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1831 uint32_t u1WriteThru : 1;
1832 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1833 uint32_t u1CacheDisable : 1;
1834 /** Accessed flag.
1835 * Indicates that the page have been read or written to. */
1836 uint32_t u1Accessed : 1;
1837 /** Dirty flag.
1838 * Indicates that the page has been written to. */
1839 uint32_t u1Dirty : 1;
1840 /** Reserved / If PAT enabled, bit 2 of the index. */
1841 uint32_t u1PAT : 1;
1842 /** Global flag. (Ignored in all but final level.) */
1843 uint32_t u1Global : 1;
1844 /** Available for use to system software. */
1845 uint32_t u3Available : 3;
1846 /** Physical Page number of the next level - Low Part. Don't use this. */
1847 uint32_t u20PageNoLow : 20;
1848 /** Physical Page number of the next level - High Part. Don't use this. */
1849 uint32_t u20PageNoHigh : 20;
1850 /** MBZ bits */
1851 uint32_t u11Reserved : 11;
1852 /** No Execute flag. */
1853 uint32_t u1NoExecute : 1;
1854} X86PTEPAEBITS;
1855#ifndef VBOX_FOR_DTRACE_LIB
1856AssertCompileSize(X86PTEPAEBITS, 8);
1857#endif
1858/** Pointer to a page table entry. */
1859typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1860/** Pointer to a page table entry. */
1861typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1862
1863/**
1864 * PAE Page table entry.
1865 */
1866typedef union X86PTEPAE
1867{
1868 /** Unsigned integer view */
1869 X86PGPAEUINT u;
1870 /** Bit field view. */
1871 X86PTEPAEBITS n;
1872 /** 32-bit view. */
1873 uint32_t au32[2];
1874 /** 16-bit view. */
1875 uint16_t au16[4];
1876 /** 8-bit view. */
1877 uint8_t au8[8];
1878} X86PTEPAE;
1879#ifndef VBOX_FOR_DTRACE_LIB
1880AssertCompileSize(X86PTEPAE, 8);
1881#endif
1882/** Pointer to a PAE page table entry. */
1883typedef X86PTEPAE *PX86PTEPAE;
1884/** Pointer to a const PAE page table entry. */
1885typedef const X86PTEPAE *PCX86PTEPAE;
1886/** @} */
1887
1888/**
1889 * Page table.
1890 */
1891typedef struct X86PT
1892{
1893 /** PTE Array. */
1894 X86PTE a[X86_PG_ENTRIES];
1895} X86PT;
1896#ifndef VBOX_FOR_DTRACE_LIB
1897AssertCompileSize(X86PT, 4096);
1898#endif
1899/** Pointer to a page table. */
1900typedef X86PT *PX86PT;
1901/** Pointer to a const page table. */
1902typedef const X86PT *PCX86PT;
1903
1904/** The page shift to get the PT index. */
1905#define X86_PT_SHIFT 12
1906/** The PT index mask (apply to a shifted page address). */
1907#define X86_PT_MASK 0x3ff
1908
1909
1910/**
1911 * Page directory.
1912 */
1913typedef struct X86PTPAE
1914{
1915 /** PTE Array. */
1916 X86PTEPAE a[X86_PG_PAE_ENTRIES];
1917} X86PTPAE;
1918#ifndef VBOX_FOR_DTRACE_LIB
1919AssertCompileSize(X86PTPAE, 4096);
1920#endif
1921/** Pointer to a page table. */
1922typedef X86PTPAE *PX86PTPAE;
1923/** Pointer to a const page table. */
1924typedef const X86PTPAE *PCX86PTPAE;
1925
1926/** The page shift to get the PA PTE index. */
1927#define X86_PT_PAE_SHIFT 12
1928/** The PAE PT index mask (apply to a shifted page address). */
1929#define X86_PT_PAE_MASK 0x1ff
1930
1931
1932/** @name 4KB Page Directory Entry
1933 * @{
1934 */
1935/** Bit 0 - P - Present bit. */
1936#define X86_PDE_P RT_BIT_32(0)
1937/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1938#define X86_PDE_RW RT_BIT_32(1)
1939/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1940#define X86_PDE_US RT_BIT_32(2)
1941/** Bit 3 - PWT - Page level write thru bit. */
1942#define X86_PDE_PWT RT_BIT_32(3)
1943/** Bit 4 - PCD - Page level cache disable bit. */
1944#define X86_PDE_PCD RT_BIT_32(4)
1945/** Bit 5 - A - Access bit. */
1946#define X86_PDE_A RT_BIT_32(5)
1947/** Bit 7 - PS - Page size attribute.
1948 * Clear mean 4KB pages, set means large pages (2/4MB). */
1949#define X86_PDE_PS RT_BIT_32(7)
1950/** Bits 9-11 - - Available for use to system software. */
1951#define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1952/** Bits 12-31 - - Physical Page number of the next level. */
1953#define X86_PDE_PG_MASK ( 0xfffff000 )
1954
1955/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1956#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1957/** Bits 63 - NX - PAE/LM - No execution flag. */
1958#define X86_PDE_PAE_NX RT_BIT_64(63)
1959/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1960#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1961/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1962#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1963/** Bit 7 - - LM - MBZ bits when NX is active. */
1964#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1965/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1966#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1967
1968/**
1969 * Page directory entry.
1970 */
1971typedef struct X86PDEBITS
1972{
1973 /** Flags whether(=1) or not the page is present. */
1974 uint32_t u1Present : 1;
1975 /** Read(=0) / Write(=1) flag. */
1976 uint32_t u1Write : 1;
1977 /** User(=1) / Supervisor (=0) flag. */
1978 uint32_t u1User : 1;
1979 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1980 uint32_t u1WriteThru : 1;
1981 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1982 uint32_t u1CacheDisable : 1;
1983 /** Accessed flag.
1984 * Indicates that the page has been read or written to. */
1985 uint32_t u1Accessed : 1;
1986 /** Reserved / Ignored (dirty bit). */
1987 uint32_t u1Reserved0 : 1;
1988 /** Size bit if PSE is enabled - in any event it's 0. */
1989 uint32_t u1Size : 1;
1990 /** Reserved / Ignored (global bit). */
1991 uint32_t u1Reserved1 : 1;
1992 /** Available for use to system software. */
1993 uint32_t u3Available : 3;
1994 /** Physical Page number of the next level. */
1995 uint32_t u20PageNo : 20;
1996} X86PDEBITS;
1997#ifndef VBOX_FOR_DTRACE_LIB
1998AssertCompileSize(X86PDEBITS, 4);
1999#endif
2000/** Pointer to a page directory entry. */
2001typedef X86PDEBITS *PX86PDEBITS;
2002/** Pointer to a const page directory entry. */
2003typedef const X86PDEBITS *PCX86PDEBITS;
2004
2005
2006/**
2007 * PAE page directory entry.
2008 */
2009typedef struct X86PDEPAEBITS
2010{
2011 /** Flags whether(=1) or not the page is present. */
2012 uint32_t u1Present : 1;
2013 /** Read(=0) / Write(=1) flag. */
2014 uint32_t u1Write : 1;
2015 /** User(=1) / Supervisor (=0) flag. */
2016 uint32_t u1User : 1;
2017 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2018 uint32_t u1WriteThru : 1;
2019 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2020 uint32_t u1CacheDisable : 1;
2021 /** Accessed flag.
2022 * Indicates that the page has been read or written to. */
2023 uint32_t u1Accessed : 1;
2024 /** Reserved / Ignored (dirty bit). */
2025 uint32_t u1Reserved0 : 1;
2026 /** Size bit if PSE is enabled - in any event it's 0. */
2027 uint32_t u1Size : 1;
2028 /** Reserved / Ignored (global bit). / */
2029 uint32_t u1Reserved1 : 1;
2030 /** Available for use to system software. */
2031 uint32_t u3Available : 3;
2032 /** Physical Page number of the next level - Low Part. Don't use! */
2033 uint32_t u20PageNoLow : 20;
2034 /** Physical Page number of the next level - High Part. Don't use! */
2035 uint32_t u20PageNoHigh : 20;
2036 /** MBZ bits */
2037 uint32_t u11Reserved : 11;
2038 /** No Execute flag. */
2039 uint32_t u1NoExecute : 1;
2040} X86PDEPAEBITS;
2041#ifndef VBOX_FOR_DTRACE_LIB
2042AssertCompileSize(X86PDEPAEBITS, 8);
2043#endif
2044/** Pointer to a page directory entry. */
2045typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2046/** Pointer to a const page directory entry. */
2047typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2048
2049/** @} */
2050
2051
2052/** @name 2/4MB Page Directory Entry
2053 * @{
2054 */
2055/** Bit 0 - P - Present bit. */
2056#define X86_PDE4M_P RT_BIT_32(0)
2057/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2058#define X86_PDE4M_RW RT_BIT_32(1)
2059/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2060#define X86_PDE4M_US RT_BIT_32(2)
2061/** Bit 3 - PWT - Page level write thru bit. */
2062#define X86_PDE4M_PWT RT_BIT_32(3)
2063/** Bit 4 - PCD - Page level cache disable bit. */
2064#define X86_PDE4M_PCD RT_BIT_32(4)
2065/** Bit 5 - A - Access bit. */
2066#define X86_PDE4M_A RT_BIT_32(5)
2067/** Bit 6 - D - Dirty bit. */
2068#define X86_PDE4M_D RT_BIT_32(6)
2069/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2070#define X86_PDE4M_PS RT_BIT_32(7)
2071/** Bit 8 - G - Global flag. */
2072#define X86_PDE4M_G RT_BIT_32(8)
2073/** Bits 9-11 - AVL - Available for use to system software. */
2074#define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2075/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2076#define X86_PDE4M_PAT RT_BIT_32(12)
2077/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2078#define X86_PDE4M_PAT_SHIFT (12 - 7)
2079/** Bits 22-31 - - Physical Page number. */
2080#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2081/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2082#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2083/** The number of bits to the high part of the page number. */
2084#define X86_PDE4M_PG_HIGH_SHIFT 19
2085/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2086#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2087
2088/** Bits 21-51 - - PAE/LM - Physical Page number.
2089 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2090#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2091/** Bits 63 - NX - PAE/LM - No execution flag. */
2092#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2093/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2094#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2095/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2096#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2097/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2098#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2099/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2100#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2101
2102/**
2103 * 4MB page directory entry.
2104 */
2105typedef struct X86PDE4MBITS
2106{
2107 /** Flags whether(=1) or not the page is present. */
2108 uint32_t u1Present : 1;
2109 /** Read(=0) / Write(=1) flag. */
2110 uint32_t u1Write : 1;
2111 /** User(=1) / Supervisor (=0) flag. */
2112 uint32_t u1User : 1;
2113 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2114 uint32_t u1WriteThru : 1;
2115 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2116 uint32_t u1CacheDisable : 1;
2117 /** Accessed flag.
2118 * Indicates that the page have been read or written to. */
2119 uint32_t u1Accessed : 1;
2120 /** Dirty flag.
2121 * Indicates that the page has been written to. */
2122 uint32_t u1Dirty : 1;
2123 /** Page size flag - always 1 for 4MB entries. */
2124 uint32_t u1Size : 1;
2125 /** Global flag. */
2126 uint32_t u1Global : 1;
2127 /** Available for use to system software. */
2128 uint32_t u3Available : 3;
2129 /** Reserved / If PAT enabled, bit 2 of the index. */
2130 uint32_t u1PAT : 1;
2131 /** Bits 32-39 of the page number on AMD64.
2132 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2133 uint32_t u8PageNoHigh : 8;
2134 /** Reserved. */
2135 uint32_t u1Reserved : 1;
2136 /** Physical Page number of the page. */
2137 uint32_t u10PageNo : 10;
2138} X86PDE4MBITS;
2139#ifndef VBOX_FOR_DTRACE_LIB
2140AssertCompileSize(X86PDE4MBITS, 4);
2141#endif
2142/** Pointer to a page table entry. */
2143typedef X86PDE4MBITS *PX86PDE4MBITS;
2144/** Pointer to a const page table entry. */
2145typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2146
2147
2148/**
2149 * 2MB PAE page directory entry.
2150 */
2151typedef struct X86PDE2MPAEBITS
2152{
2153 /** Flags whether(=1) or not the page is present. */
2154 uint32_t u1Present : 1;
2155 /** Read(=0) / Write(=1) flag. */
2156 uint32_t u1Write : 1;
2157 /** User(=1) / Supervisor(=0) flag. */
2158 uint32_t u1User : 1;
2159 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2160 uint32_t u1WriteThru : 1;
2161 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2162 uint32_t u1CacheDisable : 1;
2163 /** Accessed flag.
2164 * Indicates that the page have been read or written to. */
2165 uint32_t u1Accessed : 1;
2166 /** Dirty flag.
2167 * Indicates that the page has been written to. */
2168 uint32_t u1Dirty : 1;
2169 /** Page size flag - always 1 for 2MB entries. */
2170 uint32_t u1Size : 1;
2171 /** Global flag. */
2172 uint32_t u1Global : 1;
2173 /** Available for use to system software. */
2174 uint32_t u3Available : 3;
2175 /** Reserved / If PAT enabled, bit 2 of the index. */
2176 uint32_t u1PAT : 1;
2177 /** Reserved. */
2178 uint32_t u9Reserved : 9;
2179 /** Physical Page number of the next level - Low part. Don't use! */
2180 uint32_t u10PageNoLow : 10;
2181 /** Physical Page number of the next level - High part. Don't use! */
2182 uint32_t u20PageNoHigh : 20;
2183 /** MBZ bits */
2184 uint32_t u11Reserved : 11;
2185 /** No Execute flag. */
2186 uint32_t u1NoExecute : 1;
2187} X86PDE2MPAEBITS;
2188#ifndef VBOX_FOR_DTRACE_LIB
2189AssertCompileSize(X86PDE2MPAEBITS, 8);
2190#endif
2191/** Pointer to a 2MB PAE page table entry. */
2192typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2193/** Pointer to a 2MB PAE page table entry. */
2194typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2195
2196/** @} */
2197
2198/**
2199 * Page directory entry.
2200 */
2201typedef union X86PDE
2202{
2203 /** Unsigned integer view. */
2204 X86PGUINT u;
2205 /** Normal view. */
2206 X86PDEBITS n;
2207 /** 4MB view (big). */
2208 X86PDE4MBITS b;
2209 /** 8 bit unsigned integer view. */
2210 uint8_t au8[4];
2211 /** 16 bit unsigned integer view. */
2212 uint16_t au16[2];
2213 /** 32 bit unsigned integer view. */
2214 uint32_t au32[1];
2215} X86PDE;
2216#ifndef VBOX_FOR_DTRACE_LIB
2217AssertCompileSize(X86PDE, 4);
2218#endif
2219/** Pointer to a page directory entry. */
2220typedef X86PDE *PX86PDE;
2221/** Pointer to a const page directory entry. */
2222typedef const X86PDE *PCX86PDE;
2223
2224/**
2225 * PAE page directory entry.
2226 */
2227typedef union X86PDEPAE
2228{
2229 /** Unsigned integer view. */
2230 X86PGPAEUINT u;
2231 /** Normal view. */
2232 X86PDEPAEBITS n;
2233 /** 2MB page view (big). */
2234 X86PDE2MPAEBITS b;
2235 /** 8 bit unsigned integer view. */
2236 uint8_t au8[8];
2237 /** 16 bit unsigned integer view. */
2238 uint16_t au16[4];
2239 /** 32 bit unsigned integer view. */
2240 uint32_t au32[2];
2241} X86PDEPAE;
2242#ifndef VBOX_FOR_DTRACE_LIB
2243AssertCompileSize(X86PDEPAE, 8);
2244#endif
2245/** Pointer to a page directory entry. */
2246typedef X86PDEPAE *PX86PDEPAE;
2247/** Pointer to a const page directory entry. */
2248typedef const X86PDEPAE *PCX86PDEPAE;
2249
2250/**
2251 * Page directory.
2252 */
2253typedef struct X86PD
2254{
2255 /** PDE Array. */
2256 X86PDE a[X86_PG_ENTRIES];
2257} X86PD;
2258#ifndef VBOX_FOR_DTRACE_LIB
2259AssertCompileSize(X86PD, 4096);
2260#endif
2261/** Pointer to a page directory. */
2262typedef X86PD *PX86PD;
2263/** Pointer to a const page directory. */
2264typedef const X86PD *PCX86PD;
2265
2266/** The page shift to get the PD index. */
2267#define X86_PD_SHIFT 22
2268/** The PD index mask (apply to a shifted page address). */
2269#define X86_PD_MASK 0x3ff
2270
2271
2272/**
2273 * PAE page directory.
2274 */
2275typedef struct X86PDPAE
2276{
2277 /** PDE Array. */
2278 X86PDEPAE a[X86_PG_PAE_ENTRIES];
2279} X86PDPAE;
2280#ifndef VBOX_FOR_DTRACE_LIB
2281AssertCompileSize(X86PDPAE, 4096);
2282#endif
2283/** Pointer to a PAE page directory. */
2284typedef X86PDPAE *PX86PDPAE;
2285/** Pointer to a const PAE page directory. */
2286typedef const X86PDPAE *PCX86PDPAE;
2287
2288/** The page shift to get the PAE PD index. */
2289#define X86_PD_PAE_SHIFT 21
2290/** The PAE PD index mask (apply to a shifted page address). */
2291#define X86_PD_PAE_MASK 0x1ff
2292
2293
2294/** @name Page Directory Pointer Table Entry (PAE)
2295 * @{
2296 */
2297/** Bit 0 - P - Present bit. */
2298#define X86_PDPE_P RT_BIT_32(0)
2299/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2300#define X86_PDPE_RW RT_BIT_32(1)
2301/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2302#define X86_PDPE_US RT_BIT_32(2)
2303/** Bit 3 - PWT - Page level write thru bit. */
2304#define X86_PDPE_PWT RT_BIT_32(3)
2305/** Bit 4 - PCD - Page level cache disable bit. */
2306#define X86_PDPE_PCD RT_BIT_32(4)
2307/** Bit 5 - A - Access bit. Long Mode only. */
2308#define X86_PDPE_A RT_BIT_32(5)
2309/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2310#define X86_PDPE_LM_PS RT_BIT_32(7)
2311/** Bits 9-11 - - Available for use to system software. */
2312#define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2313/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2314#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2315/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2316#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2317/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2318#define X86_PDPE_LM_NX RT_BIT_64(63)
2319/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2320#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2321/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2322#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2323/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2324#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2325/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2326#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2327
2328
2329/**
2330 * Page directory pointer table entry.
2331 */
2332typedef struct X86PDPEBITS
2333{
2334 /** Flags whether(=1) or not the page is present. */
2335 uint32_t u1Present : 1;
2336 /** Chunk of reserved bits. */
2337 uint32_t u2Reserved : 2;
2338 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2339 uint32_t u1WriteThru : 1;
2340 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2341 uint32_t u1CacheDisable : 1;
2342 /** Chunk of reserved bits. */
2343 uint32_t u4Reserved : 4;
2344 /** Available for use to system software. */
2345 uint32_t u3Available : 3;
2346 /** Physical Page number of the next level - Low Part. Don't use! */
2347 uint32_t u20PageNoLow : 20;
2348 /** Physical Page number of the next level - High Part. Don't use! */
2349 uint32_t u20PageNoHigh : 20;
2350 /** MBZ bits */
2351 uint32_t u12Reserved : 12;
2352} X86PDPEBITS;
2353#ifndef VBOX_FOR_DTRACE_LIB
2354AssertCompileSize(X86PDPEBITS, 8);
2355#endif
2356/** Pointer to a page directory pointer table entry. */
2357typedef X86PDPEBITS *PX86PTPEBITS;
2358/** Pointer to a const page directory pointer table entry. */
2359typedef const X86PDPEBITS *PCX86PTPEBITS;
2360
2361/**
2362 * Page directory pointer table entry. AMD64 version
2363 */
2364typedef struct X86PDPEAMD64BITS
2365{
2366 /** Flags whether(=1) or not the page is present. */
2367 uint32_t u1Present : 1;
2368 /** Read(=0) / Write(=1) flag. */
2369 uint32_t u1Write : 1;
2370 /** User(=1) / Supervisor (=0) flag. */
2371 uint32_t u1User : 1;
2372 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2373 uint32_t u1WriteThru : 1;
2374 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2375 uint32_t u1CacheDisable : 1;
2376 /** Accessed flag.
2377 * Indicates that the page have been read or written to. */
2378 uint32_t u1Accessed : 1;
2379 /** Chunk of reserved bits. */
2380 uint32_t u3Reserved : 3;
2381 /** Available for use to system software. */
2382 uint32_t u3Available : 3;
2383 /** Physical Page number of the next level - Low Part. Don't use! */
2384 uint32_t u20PageNoLow : 20;
2385 /** Physical Page number of the next level - High Part. Don't use! */
2386 uint32_t u20PageNoHigh : 20;
2387 /** MBZ bits */
2388 uint32_t u11Reserved : 11;
2389 /** No Execute flag. */
2390 uint32_t u1NoExecute : 1;
2391} X86PDPEAMD64BITS;
2392#ifndef VBOX_FOR_DTRACE_LIB
2393AssertCompileSize(X86PDPEAMD64BITS, 8);
2394#endif
2395/** Pointer to a page directory pointer table entry. */
2396typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2397/** Pointer to a const page directory pointer table entry. */
2398typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2399
2400/**
2401 * Page directory pointer table entry for 1GB page. (AMD64 only)
2402 */
2403typedef struct X86PDPE1GB
2404{
2405 /** 0: Flags whether(=1) or not the page is present. */
2406 uint32_t u1Present : 1;
2407 /** 1: Read(=0) / Write(=1) flag. */
2408 uint32_t u1Write : 1;
2409 /** 2: User(=1) / Supervisor (=0) flag. */
2410 uint32_t u1User : 1;
2411 /** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2412 uint32_t u1WriteThru : 1;
2413 /** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2414 uint32_t u1CacheDisable : 1;
2415 /** 5: Accessed flag.
2416 * Indicates that the page have been read or written to. */
2417 uint32_t u1Accessed : 1;
2418 /** 6: Dirty flag for 1GB pages. */
2419 uint32_t u1Dirty : 1;
2420 /** 7: Indicates 1GB page if set. */
2421 uint32_t u1Size : 1;
2422 /** 8: Global 1GB page. */
2423 uint32_t u1Global: 1;
2424 /** 9-11: Available for use to system software. */
2425 uint32_t u3Available : 3;
2426 /** 12: PAT bit for 1GB page. */
2427 uint32_t u1PAT : 1;
2428 /** 13-29: MBZ bits. */
2429 uint32_t u17Reserved : 17;
2430 /** 30-31: Physical page number - Low Part. Don't use! */
2431 uint32_t u2PageNoLow : 2;
2432 /** 32-51: Physical Page number of the next level - High Part. Don't use! */
2433 uint32_t u20PageNoHigh : 20;
2434 /** 52-62: MBZ bits */
2435 uint32_t u11Reserved : 11;
2436 /** 63: No Execute flag. */
2437 uint32_t u1NoExecute : 1;
2438} X86PDPE1GB;
2439#ifndef VBOX_FOR_DTRACE_LIB
2440AssertCompileSize(X86PDPE1GB, 8);
2441#endif
2442/** Pointer to a page directory pointer table entry for a 1GB page. */
2443typedef X86PDPE1GB *PX86PDPE1GB;
2444/** Pointer to a const page directory pointer table entry for a 1GB page. */
2445typedef const X86PDPE1GB *PCX86PDPE1GB;
2446
2447/**
2448 * Page directory pointer table entry.
2449 */
2450typedef union X86PDPE
2451{
2452 /** Unsigned integer view. */
2453 X86PGPAEUINT u;
2454 /** Normal view. */
2455 X86PDPEBITS n;
2456 /** AMD64 view. */
2457 X86PDPEAMD64BITS lm;
2458 /** AMD64 big view. */
2459 X86PDPE1GB b;
2460 /** 8 bit unsigned integer view. */
2461 uint8_t au8[8];
2462 /** 16 bit unsigned integer view. */
2463 uint16_t au16[4];
2464 /** 32 bit unsigned integer view. */
2465 uint32_t au32[2];
2466} X86PDPE;
2467#ifndef VBOX_FOR_DTRACE_LIB
2468AssertCompileSize(X86PDPE, 8);
2469#endif
2470/** Pointer to a page directory pointer table entry. */
2471typedef X86PDPE *PX86PDPE;
2472/** Pointer to a const page directory pointer table entry. */
2473typedef const X86PDPE *PCX86PDPE;
2474
2475
2476/**
2477 * Page directory pointer table.
2478 */
2479typedef struct X86PDPT
2480{
2481 /** PDE Array. */
2482 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2483} X86PDPT;
2484#ifndef VBOX_FOR_DTRACE_LIB
2485AssertCompileSize(X86PDPT, 4096);
2486#endif
2487/** Pointer to a page directory pointer table. */
2488typedef X86PDPT *PX86PDPT;
2489/** Pointer to a const page directory pointer table. */
2490typedef const X86PDPT *PCX86PDPT;
2491
2492/** The page shift to get the PDPT index. */
2493#define X86_PDPT_SHIFT 30
2494/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2495#define X86_PDPT_MASK_PAE 0x3
2496/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2497#define X86_PDPT_MASK_AMD64 0x1ff
2498
2499/** @} */
2500
2501
2502/** @name Page Map Level-4 Entry (Long Mode PAE)
2503 * @{
2504 */
2505/** Bit 0 - P - Present bit. */
2506#define X86_PML4E_P RT_BIT_32(0)
2507/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2508#define X86_PML4E_RW RT_BIT_32(1)
2509/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2510#define X86_PML4E_US RT_BIT_32(2)
2511/** Bit 3 - PWT - Page level write thru bit. */
2512#define X86_PML4E_PWT RT_BIT_32(3)
2513/** Bit 4 - PCD - Page level cache disable bit. */
2514#define X86_PML4E_PCD RT_BIT_32(4)
2515/** Bit 5 - A - Access bit. */
2516#define X86_PML4E_A RT_BIT_32(5)
2517/** Bits 9-11 - - Available for use to system software. */
2518#define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2519/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2520#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2521/** Bits 8, 7 - - MBZ bits when NX is active. */
2522#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2523/** Bits 63, 7 - - MBZ bits when no NX. */
2524#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2525/** Bits 63 - NX - PAE - No execution flag. */
2526#define X86_PML4E_NX RT_BIT_64(63)
2527
2528/**
2529 * Page Map Level-4 Entry
2530 */
2531typedef struct X86PML4EBITS
2532{
2533 /** Flags whether(=1) or not the page is present. */
2534 uint32_t u1Present : 1;
2535 /** Read(=0) / Write(=1) flag. */
2536 uint32_t u1Write : 1;
2537 /** User(=1) / Supervisor (=0) flag. */
2538 uint32_t u1User : 1;
2539 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2540 uint32_t u1WriteThru : 1;
2541 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2542 uint32_t u1CacheDisable : 1;
2543 /** Accessed flag.
2544 * Indicates that the page have been read or written to. */
2545 uint32_t u1Accessed : 1;
2546 /** Chunk of reserved bits. */
2547 uint32_t u3Reserved : 3;
2548 /** Available for use to system software. */
2549 uint32_t u3Available : 3;
2550 /** Physical Page number of the next level - Low Part. Don't use! */
2551 uint32_t u20PageNoLow : 20;
2552 /** Physical Page number of the next level - High Part. Don't use! */
2553 uint32_t u20PageNoHigh : 20;
2554 /** MBZ bits */
2555 uint32_t u11Reserved : 11;
2556 /** No Execute flag. */
2557 uint32_t u1NoExecute : 1;
2558} X86PML4EBITS;
2559#ifndef VBOX_FOR_DTRACE_LIB
2560AssertCompileSize(X86PML4EBITS, 8);
2561#endif
2562/** Pointer to a page map level-4 entry. */
2563typedef X86PML4EBITS *PX86PML4EBITS;
2564/** Pointer to a const page map level-4 entry. */
2565typedef const X86PML4EBITS *PCX86PML4EBITS;
2566
2567/**
2568 * Page Map Level-4 Entry.
2569 */
2570typedef union X86PML4E
2571{
2572 /** Unsigned integer view. */
2573 X86PGPAEUINT u;
2574 /** Normal view. */
2575 X86PML4EBITS n;
2576 /** 8 bit unsigned integer view. */
2577 uint8_t au8[8];
2578 /** 16 bit unsigned integer view. */
2579 uint16_t au16[4];
2580 /** 32 bit unsigned integer view. */
2581 uint32_t au32[2];
2582} X86PML4E;
2583#ifndef VBOX_FOR_DTRACE_LIB
2584AssertCompileSize(X86PML4E, 8);
2585#endif
2586/** Pointer to a page map level-4 entry. */
2587typedef X86PML4E *PX86PML4E;
2588/** Pointer to a const page map level-4 entry. */
2589typedef const X86PML4E *PCX86PML4E;
2590
2591
2592/**
2593 * Page Map Level-4.
2594 */
2595typedef struct X86PML4
2596{
2597 /** PDE Array. */
2598 X86PML4E a[X86_PG_PAE_ENTRIES];
2599} X86PML4;
2600#ifndef VBOX_FOR_DTRACE_LIB
2601AssertCompileSize(X86PML4, 4096);
2602#endif
2603/** Pointer to a page map level-4. */
2604typedef X86PML4 *PX86PML4;
2605/** Pointer to a const page map level-4. */
2606typedef const X86PML4 *PCX86PML4;
2607
2608/** The page shift to get the PML4 index. */
2609#define X86_PML4_SHIFT 39
2610/** The PML4 index mask (apply to a shifted page address). */
2611#define X86_PML4_MASK 0x1ff
2612
2613/** @} */
2614
2615/** @} */
2616
2617/**
2618 * Intel PCID invalidation types.
2619 */
2620/** Individual address invalidation. */
2621#define X86_INVPCID_TYPE_INDV_ADDR 0
2622/** Single-context invalidation. */
2623#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2624/** All-context including globals invalidation. */
2625#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2626/** All-context excluding globals invalidation. */
2627#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2628/** The maximum valid invalidation type value. */
2629#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2630
2631/**
2632 * 32-bit protected mode FSTENV image.
2633 */
2634typedef struct X86FSTENV32P
2635{
2636 uint16_t FCW;
2637 uint16_t padding1;
2638 uint16_t FSW;
2639 uint16_t padding2;
2640 uint16_t FTW;
2641 uint16_t padding3;
2642 uint32_t FPUIP;
2643 uint16_t FPUCS;
2644 uint16_t FOP;
2645 uint32_t FPUDP;
2646 uint16_t FPUDS;
2647 uint16_t padding4;
2648} X86FSTENV32P;
2649/** Pointer to a 32-bit protected mode FSTENV image. */
2650typedef X86FSTENV32P *PX86FSTENV32P;
2651/** Pointer to a const 32-bit protected mode FSTENV image. */
2652typedef X86FSTENV32P const *PCX86FSTENV32P;
2653
2654
2655/**
2656 * 80-bit MMX/FPU register type.
2657 */
2658typedef struct X86FPUMMX
2659{
2660 uint8_t reg[10];
2661} X86FPUMMX;
2662#ifndef VBOX_FOR_DTRACE_LIB
2663AssertCompileSize(X86FPUMMX, 10);
2664#endif
2665/** Pointer to a 80-bit MMX/FPU register type. */
2666typedef X86FPUMMX *PX86FPUMMX;
2667/** Pointer to a const 80-bit MMX/FPU register type. */
2668typedef const X86FPUMMX *PCX86FPUMMX;
2669
2670/** FPU (x87) register. */
2671typedef union X86FPUREG
2672{
2673 /** MMX view. */
2674 uint64_t mmx;
2675 /** FPU view - todo. */
2676 X86FPUMMX fpu;
2677 /** Extended precision floating point view. */
2678 RTFLOAT80U r80;
2679 /** Extended precision floating point view v2 */
2680 RTFLOAT80U2 r80Ex;
2681 /** 8-bit view. */
2682 uint8_t au8[16];
2683 /** 16-bit view. */
2684 uint16_t au16[8];
2685 /** 32-bit view. */
2686 uint32_t au32[4];
2687 /** 64-bit view. */
2688 uint64_t au64[2];
2689 /** 128-bit view. (yeah, very helpful) */
2690 uint128_t au128[1];
2691} X86FPUREG;
2692#ifndef VBOX_FOR_DTRACE_LIB
2693AssertCompileSize(X86FPUREG, 16);
2694#endif
2695/** Pointer to a FPU register. */
2696typedef X86FPUREG *PX86FPUREG;
2697/** Pointer to a const FPU register. */
2698typedef X86FPUREG const *PCX86FPUREG;
2699
2700/**
2701 * XMM register union.
2702 */
2703typedef union X86XMMREG
2704{
2705 /** XMM Register view. */
2706 uint128_t xmm;
2707 /** 8-bit view. */
2708 uint8_t au8[16];
2709 /** 16-bit view. */
2710 uint16_t au16[8];
2711 /** 32-bit view. */
2712 uint32_t au32[4];
2713 /** 64-bit view. */
2714 uint64_t au64[2];
2715 /** 128-bit view. (yeah, very helpful) */
2716 uint128_t au128[1];
2717 /** Confusing nested 128-bit union view (this is what xmm should've been). */
2718 RTUINT128U uXmm;
2719} X86XMMREG;
2720#ifndef VBOX_FOR_DTRACE_LIB
2721AssertCompileSize(X86XMMREG, 16);
2722#endif
2723/** Pointer to an XMM register state. */
2724typedef X86XMMREG *PX86XMMREG;
2725/** Pointer to a const XMM register state. */
2726typedef X86XMMREG const *PCX86XMMREG;
2727
2728/**
2729 * YMM register union.
2730 */
2731typedef union X86YMMREG
2732{
2733 /** 8-bit view. */
2734 uint8_t au8[32];
2735 /** 16-bit view. */
2736 uint16_t au16[16];
2737 /** 32-bit view. */
2738 uint32_t au32[8];
2739 /** 64-bit view. */
2740 uint64_t au64[4];
2741 /** 128-bit view. (yeah, very helpful) */
2742 uint128_t au128[2];
2743 /** XMM sub register view. */
2744 X86XMMREG aXmm[2];
2745} X86YMMREG;
2746#ifndef VBOX_FOR_DTRACE_LIB
2747AssertCompileSize(X86YMMREG, 32);
2748#endif
2749/** Pointer to an YMM register state. */
2750typedef X86YMMREG *PX86YMMREG;
2751/** Pointer to a const YMM register state. */
2752typedef X86YMMREG const *PCX86YMMREG;
2753
2754/**
2755 * ZMM register union.
2756 */
2757typedef union X86ZMMREG
2758{
2759 /** 8-bit view. */
2760 uint8_t au8[64];
2761 /** 16-bit view. */
2762 uint16_t au16[32];
2763 /** 32-bit view. */
2764 uint32_t au32[16];
2765 /** 64-bit view. */
2766 uint64_t au64[8];
2767 /** 128-bit view. (yeah, very helpful) */
2768 uint128_t au128[4];
2769 /** XMM sub register view. */
2770 X86XMMREG aXmm[4];
2771 /** YMM sub register view. */
2772 X86YMMREG aYmm[2];
2773} X86ZMMREG;
2774#ifndef VBOX_FOR_DTRACE_LIB
2775AssertCompileSize(X86ZMMREG, 64);
2776#endif
2777/** Pointer to an ZMM register state. */
2778typedef X86ZMMREG *PX86ZMMREG;
2779/** Pointer to a const ZMM register state. */
2780typedef X86ZMMREG const *PCX86ZMMREG;
2781
2782
2783/**
2784 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2785 * @todo verify this...
2786 */
2787#pragma pack(1)
2788typedef struct X86FPUSTATE
2789{
2790 /** 0x00 - Control word. */
2791 uint16_t FCW;
2792 /** 0x02 - Alignment word */
2793 uint16_t Dummy1;
2794 /** 0x04 - Status word. */
2795 uint16_t FSW;
2796 /** 0x06 - Alignment word */
2797 uint16_t Dummy2;
2798 /** 0x08 - Tag word */
2799 uint16_t FTW;
2800 /** 0x0a - Alignment word */
2801 uint16_t Dummy3;
2802
2803 /** 0x0c - Instruction pointer. */
2804 uint32_t FPUIP;
2805 /** 0x10 - Code selector. */
2806 uint16_t CS;
2807 /** 0x12 - Opcode. */
2808 uint16_t FOP;
2809 /** 0x14 - FOO. */
2810 uint32_t FPUOO;
2811 /** 0x18 - FOS. */
2812 uint32_t FPUOS;
2813 /** 0x1c - FPU register. */
2814 X86FPUREG regs[8];
2815} X86FPUSTATE;
2816#pragma pack()
2817/** Pointer to a FPU state. */
2818typedef X86FPUSTATE *PX86FPUSTATE;
2819/** Pointer to a const FPU state. */
2820typedef const X86FPUSTATE *PCX86FPUSTATE;
2821
2822/**
2823 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2824 */
2825#pragma pack(1)
2826typedef struct X86FXSTATE
2827{
2828 /** 0x00 - Control word. */
2829 uint16_t FCW;
2830 /** 0x02 - Status word. */
2831 uint16_t FSW;
2832 /** 0x04 - Tag word. (The upper byte is always zero.) */
2833 uint16_t FTW;
2834 /** 0x06 - Opcode. */
2835 uint16_t FOP;
2836 /** 0x08 - Instruction pointer. */
2837 uint32_t FPUIP;
2838 /** 0x0c - Code selector. */
2839 uint16_t CS;
2840 uint16_t Rsrvd1;
2841 /** 0x10 - Data pointer. */
2842 uint32_t FPUDP;
2843 /** 0x14 - Data segment */
2844 uint16_t DS;
2845 /** 0x16 */
2846 uint16_t Rsrvd2;
2847 /** 0x18 */
2848 uint32_t MXCSR;
2849 /** 0x1c */
2850 uint32_t MXCSR_MASK;
2851 /** 0x20 - FPU registers. */
2852 X86FPUREG aRegs[8];
2853 /** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
2854 X86XMMREG aXMM[16];
2855 /* - offset 416 - */
2856 uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2857 /* - offset 464 - Software usable reserved bits. */
2858 uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2859} X86FXSTATE;
2860#pragma pack()
2861/** Pointer to a FPU Extended state. */
2862typedef X86FXSTATE *PX86FXSTATE;
2863/** Pointer to a const FPU Extended state. */
2864typedef const X86FXSTATE *PCX86FXSTATE;
2865
2866/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2867 * magic. Don't forget to update x86.mac if you change this! */
2868#define X86_OFF_FXSTATE_RSVD 0x1d0
2869/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2870 * forget to update x86.mac if you change this!
2871 * @todo r=bird: This has nothing what-so-ever to do here.... */
2872#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2873#ifndef VBOX_FOR_DTRACE_LIB
2874AssertCompileSize(X86FXSTATE, 512);
2875AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2876#endif
2877
2878/** @name FPU status word flags.
2879 * @{ */
2880/** Exception Flag: Invalid operation. */
2881#define X86_FSW_IE RT_BIT_32(0)
2882/** Exception Flag: Denormalized operand. */
2883#define X86_FSW_DE RT_BIT_32(1)
2884/** Exception Flag: Zero divide. */
2885#define X86_FSW_ZE RT_BIT_32(2)
2886/** Exception Flag: Overflow. */
2887#define X86_FSW_OE RT_BIT_32(3)
2888/** Exception Flag: Underflow. */
2889#define X86_FSW_UE RT_BIT_32(4)
2890/** Exception Flag: Precision. */
2891#define X86_FSW_PE RT_BIT_32(5)
2892/** Stack fault. */
2893#define X86_FSW_SF RT_BIT_32(6)
2894/** Error summary status. */
2895#define X86_FSW_ES RT_BIT_32(7)
2896/** Mask of exceptions flags, excluding the summary bit. */
2897#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2898/** Mask of exceptions flags, including the summary bit. */
2899#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2900/** Condition code 0. */
2901#define X86_FSW_C0 RT_BIT_32(8)
2902/** Condition code 1. */
2903#define X86_FSW_C1 RT_BIT_32(9)
2904/** Condition code 2. */
2905#define X86_FSW_C2 RT_BIT_32(10)
2906/** Top of the stack mask. */
2907#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2908/** TOP shift value. */
2909#define X86_FSW_TOP_SHIFT 11
2910/** Mask for getting TOP value after shifting it right. */
2911#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2912/** Get the TOP value. */
2913#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2914/** Condition code 3. */
2915#define X86_FSW_C3 RT_BIT_32(14)
2916/** Mask of exceptions flags, including the summary bit. */
2917#define X86_FSW_C_MASK UINT16_C(0x4700)
2918/** FPU busy. */
2919#define X86_FSW_B RT_BIT_32(15)
2920/** @} */
2921
2922
2923/** @name FPU control word flags.
2924 * @{ */
2925/** Exception Mask: Invalid operation. */
2926#define X86_FCW_IM RT_BIT_32(0)
2927/** Exception Mask: Denormalized operand. */
2928#define X86_FCW_DM RT_BIT_32(1)
2929/** Exception Mask: Zero divide. */
2930#define X86_FCW_ZM RT_BIT_32(2)
2931/** Exception Mask: Overflow. */
2932#define X86_FCW_OM RT_BIT_32(3)
2933/** Exception Mask: Underflow. */
2934#define X86_FCW_UM RT_BIT_32(4)
2935/** Exception Mask: Precision. */
2936#define X86_FCW_PM RT_BIT_32(5)
2937/** Mask all exceptions, the value typically loaded (by for instance fninit).
2938 * @remarks This includes reserved bit 6. */
2939#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2940/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2941#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2942/** Precision control mask. */
2943#define X86_FCW_PC_MASK UINT16_C(0x0300)
2944/** Precision control: 24-bit. */
2945#define X86_FCW_PC_24 UINT16_C(0x0000)
2946/** Precision control: Reserved. */
2947#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2948/** Precision control: 53-bit. */
2949#define X86_FCW_PC_53 UINT16_C(0x0200)
2950/** Precision control: 64-bit. */
2951#define X86_FCW_PC_64 UINT16_C(0x0300)
2952/** Rounding control mask. */
2953#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2954/** Rounding control: To nearest. */
2955#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2956/** Rounding control: Down. */
2957#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2958/** Rounding control: Up. */
2959#define X86_FCW_RC_UP UINT16_C(0x0800)
2960/** Rounding control: Towards zero. */
2961#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2962/** Bits which should be zero, apparently. */
2963#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2964/** @} */
2965
2966/** @name SSE MXCSR
2967 * @{ */
2968/** Exception Flag: Invalid operation. */
2969#define X86_MXCSR_IE RT_BIT_32(0)
2970/** Exception Flag: Denormalized operand. */
2971#define X86_MXCSR_DE RT_BIT_32(1)
2972/** Exception Flag: Zero divide. */
2973#define X86_MXCSR_ZE RT_BIT_32(2)
2974/** Exception Flag: Overflow. */
2975#define X86_MXCSR_OE RT_BIT_32(3)
2976/** Exception Flag: Underflow. */
2977#define X86_MXCSR_UE RT_BIT_32(4)
2978/** Exception Flag: Precision. */
2979#define X86_MXCSR_PE RT_BIT_32(5)
2980
2981/** Denormals are zero. */
2982#define X86_MXCSR_DAZ RT_BIT_32(6)
2983
2984/** Exception Mask: Invalid operation. */
2985#define X86_MXCSR_IM RT_BIT_32(7)
2986/** Exception Mask: Denormalized operand. */
2987#define X86_MXCSR_DM RT_BIT_32(8)
2988/** Exception Mask: Zero divide. */
2989#define X86_MXCSR_ZM RT_BIT_32(9)
2990/** Exception Mask: Overflow. */
2991#define X86_MXCSR_OM RT_BIT_32(10)
2992/** Exception Mask: Underflow. */
2993#define X86_MXCSR_UM RT_BIT_32(11)
2994/** Exception Mask: Precision. */
2995#define X86_MXCSR_PM RT_BIT_32(12)
2996
2997/** Rounding control mask. */
2998#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
2999/** Rounding control: To nearest. */
3000#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3001/** Rounding control: Down. */
3002#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3003/** Rounding control: Up. */
3004#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3005/** Rounding control: Towards zero. */
3006#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3007
3008/** Flush-to-zero for masked underflow. */
3009#define X86_MXCSR_FZ RT_BIT_32(15)
3010
3011/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3012#define X86_MXCSR_MM RT_BIT_32(17)
3013/** @} */
3014
3015/**
3016 * XSAVE header.
3017 */
3018typedef struct X86XSAVEHDR
3019{
3020 /** XTATE_BV - Bitmap indicating whether a component is in the state. */
3021 uint64_t bmXState;
3022 /** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3023 uint64_t bmXComp;
3024 /** Reserved for furture extensions, probably MBZ. */
3025 uint64_t au64Reserved[6];
3026} X86XSAVEHDR;
3027#ifndef VBOX_FOR_DTRACE_LIB
3028AssertCompileSize(X86XSAVEHDR, 64);
3029#endif
3030/** Pointer to an XSAVE header. */
3031typedef X86XSAVEHDR *PX86XSAVEHDR;
3032/** Pointer to a const XSAVE header. */
3033typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3034
3035
3036/**
3037 * The high 128-bit YMM register state (XSAVE_C_YMM).
3038 * (The lower 128-bits being in X86FXSTATE.)
3039 */
3040typedef struct X86XSAVEYMMHI
3041{
3042 /** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3043 X86XMMREG aYmmHi[16];
3044} X86XSAVEYMMHI;
3045#ifndef VBOX_FOR_DTRACE_LIB
3046AssertCompileSize(X86XSAVEYMMHI, 256);
3047#endif
3048/** Pointer to a high 128-bit YMM register state. */
3049typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3050/** Pointer to a const high 128-bit YMM register state. */
3051typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3052
3053/**
3054 * Intel MPX bound registers state (XSAVE_C_BNDREGS).
3055 */
3056typedef struct X86XSAVEBNDREGS
3057{
3058 /** Array of registers (BND0...BND3). */
3059 struct
3060 {
3061 /** Lower bound. */
3062 uint64_t uLowerBound;
3063 /** Upper bound. */
3064 uint64_t uUpperBound;
3065 } aRegs[4];
3066} X86XSAVEBNDREGS;
3067#ifndef VBOX_FOR_DTRACE_LIB
3068AssertCompileSize(X86XSAVEBNDREGS, 64);
3069#endif
3070/** Pointer to a MPX bound register state. */
3071typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3072/** Pointer to a const MPX bound register state. */
3073typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3074
3075/**
3076 * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3077 */
3078typedef struct X86XSAVEBNDCFG
3079{
3080 uint64_t fConfig;
3081 uint64_t fStatus;
3082} X86XSAVEBNDCFG;
3083#ifndef VBOX_FOR_DTRACE_LIB
3084AssertCompileSize(X86XSAVEBNDCFG, 16);
3085#endif
3086/** Pointer to a MPX bound config and status register state. */
3087typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3088/** Pointer to a const MPX bound config and status register state. */
3089typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3090
3091/**
3092 * AVX-512 opmask state (XSAVE_C_OPMASK).
3093 */
3094typedef struct X86XSAVEOPMASK
3095{
3096 /** The K0..K7 values. */
3097 uint64_t aKRegs[8];
3098} X86XSAVEOPMASK;
3099#ifndef VBOX_FOR_DTRACE_LIB
3100AssertCompileSize(X86XSAVEOPMASK, 64);
3101#endif
3102/** Pointer to a AVX-512 opmask state. */
3103typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3104/** Pointer to a const AVX-512 opmask state. */
3105typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3106
3107/**
3108 * ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3109 */
3110typedef struct X86XSAVEZMMHI256
3111{
3112 /** Upper 256-bits of ZMM0-15. */
3113 X86YMMREG aHi256Regs[16];
3114} X86XSAVEZMMHI256;
3115#ifndef VBOX_FOR_DTRACE_LIB
3116AssertCompileSize(X86XSAVEZMMHI256, 512);
3117#endif
3118/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3119typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3120/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3121typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3122
3123/**
3124 * ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3125 */
3126typedef struct X86XSAVEZMM16HI
3127{
3128 /** ZMM16 thru ZMM31. */
3129 X86ZMMREG aRegs[16];
3130} X86XSAVEZMM16HI;
3131#ifndef VBOX_FOR_DTRACE_LIB
3132AssertCompileSize(X86XSAVEZMM16HI, 1024);
3133#endif
3134/** Pointer to a state comprising ZMM16-32. */
3135typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3136/** Pointer to a const state comprising ZMM16-32. */
3137typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3138
3139/**
3140 * AMD Light weight profiling state (XSAVE_C_LWP).
3141 *
3142 * We probably won't play with this as AMD seems to be dropping from their "zen"
3143 * processor micro architecture.
3144 */
3145typedef struct X86XSAVELWP
3146{
3147 /** Details when needed. */
3148 uint64_t auLater[128/8];
3149} X86XSAVELWP;
3150#ifndef VBOX_FOR_DTRACE_LIB
3151AssertCompileSize(X86XSAVELWP, 128);
3152#endif
3153
3154
3155/**
3156 * x86 FPU/SSE/AVX/XXXX state.
3157 *
3158 * Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3159 * changes to this structure.
3160 */
3161typedef struct X86XSAVEAREA
3162{
3163 /** The x87 and SSE region (or legacy region if you like). */
3164 X86FXSTATE x87;
3165 /** The XSAVE header. */
3166 X86XSAVEHDR Hdr;
3167 /** Beyond the header, there isn't really a fixed layout, but we can
3168 generally assume the YMM (AVX) register extensions are present and
3169 follows immediately. */
3170 union
3171 {
3172 /** The high 128-bit AVX registers for easy access by IEM.
3173 * @note This ASSUMES they will always be here... */
3174 X86XSAVEYMMHI YmmHi;
3175
3176 /** This is a typical layout on intel CPUs (good for debuggers). */
3177 struct
3178 {
3179 X86XSAVEYMMHI YmmHi;
3180 X86XSAVEBNDREGS BndRegs;
3181 X86XSAVEBNDCFG BndCfg;
3182 uint8_t abFudgeToMatchDocs[0xB0];
3183 X86XSAVEOPMASK Opmask;
3184 X86XSAVEZMMHI256 ZmmHi256;
3185 X86XSAVEZMM16HI Zmm16Hi;
3186 } Intel;
3187
3188 /** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3189 struct
3190 {
3191 X86XSAVEYMMHI YmmHi;
3192 X86XSAVELWP Lwp;
3193 } AmdBd;
3194
3195 /** To enbling static deployments that have a reasonable chance of working for
3196 * the next 3-6 CPU generations without running short on space, we allocate a
3197 * lot of extra space here, making the structure a round 8KB in size. This
3198 * leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3199 * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3200 uint8_t ab[8192 - 512 - 64];
3201 } u;
3202} X86XSAVEAREA;
3203#ifndef VBOX_FOR_DTRACE_LIB
3204AssertCompileSize(X86XSAVEAREA, 8192);
3205AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
3206AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3207AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3208AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3209AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3210AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3211AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3212AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3213#endif
3214/** Pointer to a XSAVE area. */
3215typedef X86XSAVEAREA *PX86XSAVEAREA;
3216/** Pointer to a const XSAVE area. */
3217typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3218
3219
3220/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3221 * @{ */
3222/** Bit 0 - x87 - Legacy FPU state (bit number) */
3223#define XSAVE_C_X87_BIT 0
3224/** Bit 0 - x87 - Legacy FPU state. */
3225#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3226/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3227#define XSAVE_C_SSE_BIT 1
3228/** Bit 1 - SSE - 128-bit SSE state. */
3229#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3230/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3231#define XSAVE_C_YMM_BIT 2
3232/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3233#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3234/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3235#define XSAVE_C_BNDREGS_BIT 3
3236/** Bit 3 - BNDREGS - MPX bound register state. */
3237#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3238/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3239#define XSAVE_C_BNDCSR_BIT 4
3240/** Bit 4 - BNDCSR - MPX bound config and status state. */
3241#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3242/** Bit 5 - Opmask - opmask state (bit number). */
3243#define XSAVE_C_OPMASK_BIT 5
3244/** Bit 5 - Opmask - opmask state. */
3245#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3246/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3247#define XSAVE_C_ZMM_HI256_BIT 6
3248/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3249#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3250/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3251#define XSAVE_C_ZMM_16HI_BIT 7
3252/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3253#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3254/** Bit 9 - PKRU - Protection-key state (bit number). */
3255#define XSAVE_C_PKRU_BIT 9
3256/** Bit 9 - PKRU - Protection-key state. */
3257#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3258/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3259#define XSAVE_C_LWP_BIT 62
3260/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3261#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3262/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3263#define XSAVE_C_X_BIT 63
3264/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3265#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3266/** @} */
3267
3268
3269
3270/** @name Selector Descriptor
3271 * @{
3272 */
3273
3274#ifndef VBOX_FOR_DTRACE_LIB
3275/**
3276 * Descriptor attributes (as seen by VT-x).
3277 */
3278typedef struct X86DESCATTRBITS
3279{
3280 /** 00 - Segment Type. */
3281 unsigned u4Type : 4;
3282 /** 04 - Descriptor Type. System(=0) or code/data selector */
3283 unsigned u1DescType : 1;
3284 /** 05 - Descriptor Privilege level. */
3285 unsigned u2Dpl : 2;
3286 /** 07 - Flags selector present(=1) or not. */
3287 unsigned u1Present : 1;
3288 /** 08 - Segment limit 16-19. */
3289 unsigned u4LimitHigh : 4;
3290 /** 0c - Available for system software. */
3291 unsigned u1Available : 1;
3292 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3293 unsigned u1Long : 1;
3294 /** 0e - This flags meaning depends on the segment type. Try make sense out
3295 * of the intel manual yourself. */
3296 unsigned u1DefBig : 1;
3297 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
3298 * clear byte. */
3299 unsigned u1Granularity : 1;
3300 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3301 unsigned u1Unusable : 1;
3302} X86DESCATTRBITS;
3303#endif /* !VBOX_FOR_DTRACE_LIB */
3304
3305/** @name X86DESCATTR masks
3306 * @{ */
3307#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3308#define X86DESCATTR_DT UINT32_C(0x00000010)
3309#define X86DESCATTR_DPL UINT32_C(0x00000060)
3310#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
3311#define X86DESCATTR_P UINT32_C(0x00000080)
3312#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3313#define X86DESCATTR_AVL UINT32_C(0x00001000)
3314#define X86DESCATTR_L UINT32_C(0x00002000)
3315#define X86DESCATTR_D UINT32_C(0x00004000)
3316#define X86DESCATTR_G UINT32_C(0x00008000)
3317#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3318/** @} */
3319
3320#pragma pack(1)
3321typedef union X86DESCATTR
3322{
3323 /** Unsigned integer view. */
3324 uint32_t u;
3325#ifndef VBOX_FOR_DTRACE_LIB
3326 /** Normal view. */
3327 X86DESCATTRBITS n;
3328#endif
3329} X86DESCATTR;
3330#pragma pack()
3331/** Pointer to descriptor attributes. */
3332typedef X86DESCATTR *PX86DESCATTR;
3333/** Pointer to const descriptor attributes. */
3334typedef const X86DESCATTR *PCX86DESCATTR;
3335
3336#ifndef VBOX_FOR_DTRACE_LIB
3337
3338/**
3339 * Generic descriptor table entry
3340 */
3341#pragma pack(1)
3342typedef struct X86DESCGENERIC
3343{
3344 /** 00 - Limit - Low word. */
3345 unsigned u16LimitLow : 16;
3346 /** 10 - Base address - low word.
3347 * Don't try set this to 24 because MSC is doing stupid things then. */
3348 unsigned u16BaseLow : 16;
3349 /** 20 - Base address - first 8 bits of high word. */
3350 unsigned u8BaseHigh1 : 8;
3351 /** 28 - Segment Type. */
3352 unsigned u4Type : 4;
3353 /** 2c - Descriptor Type. System(=0) or code/data selector */
3354 unsigned u1DescType : 1;
3355 /** 2d - Descriptor Privilege level. */
3356 unsigned u2Dpl : 2;
3357 /** 2f - Flags selector present(=1) or not. */
3358 unsigned u1Present : 1;
3359 /** 30 - Segment limit 16-19. */
3360 unsigned u4LimitHigh : 4;
3361 /** 34 - Available for system software. */
3362 unsigned u1Available : 1;
3363 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3364 unsigned u1Long : 1;
3365 /** 36 - This flags meaning depends on the segment type. Try make sense out
3366 * of the intel manual yourself. */
3367 unsigned u1DefBig : 1;
3368 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
3369 * clear byte. */
3370 unsigned u1Granularity : 1;
3371 /** 38 - Base address - highest 8 bits. */
3372 unsigned u8BaseHigh2 : 8;
3373} X86DESCGENERIC;
3374#pragma pack()
3375/** Pointer to a generic descriptor entry. */
3376typedef X86DESCGENERIC *PX86DESCGENERIC;
3377/** Pointer to a const generic descriptor entry. */
3378typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3379
3380/** @name Bit offsets of X86DESCGENERIC members.
3381 * @{*/
3382#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
3383#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
3384#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
3385#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
3386#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
3387#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
3388#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
3389#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
3390#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
3391#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
3392#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
3393#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
3394#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
3395/** @} */
3396
3397
3398/** @name LAR mask
3399 * @{ */
3400#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3401#define X86LAR_F_DT UINT16_C( 0x1000)
3402#define X86LAR_F_DPL UINT16_C( 0x6000)
3403#define X86LAR_F_DPL_SHIFT 13 /**< Shift count for the DPL value. */
3404#define X86LAR_F_P UINT16_C( 0x8000)
3405#define X86LAR_F_AVL UINT32_C(0x00100000)
3406#define X86LAR_F_L UINT32_C(0x00200000)
3407#define X86LAR_F_D UINT32_C(0x00400000)
3408#define X86LAR_F_G UINT32_C(0x00800000)
3409/** @} */
3410
3411
3412/**
3413 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3414 */
3415typedef struct X86DESCGATE
3416{
3417 /** 00 - Target code segment offset - Low word.
3418 * Ignored if task-gate. */
3419 unsigned u16OffsetLow : 16;
3420 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3421 * TSS selector if task-gate. */
3422 unsigned u16Sel : 16;
3423 /** 20 - Number of parameters for a call-gate.
3424 * Ignored if interrupt-, trap- or task-gate. */
3425 unsigned u5ParmCount : 5;
3426 /** 25 - Reserved / ignored. */
3427 unsigned u3Reserved : 3;
3428 /** 28 - Segment Type. */
3429 unsigned u4Type : 4;
3430 /** 2c - Descriptor Type (0 = system). */
3431 unsigned u1DescType : 1;
3432 /** 2d - Descriptor Privilege level. */
3433 unsigned u2Dpl : 2;
3434 /** 2f - Flags selector present(=1) or not. */
3435 unsigned u1Present : 1;
3436 /** 30 - Target code segment offset - High word.
3437 * Ignored if task-gate. */
3438 unsigned u16OffsetHigh : 16;
3439} X86DESCGATE;
3440/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3441typedef X86DESCGATE *PX86DESCGATE;
3442/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3443typedef const X86DESCGATE *PCX86DESCGATE;
3444
3445#endif /* VBOX_FOR_DTRACE_LIB */
3446
3447/**
3448 * Descriptor table entry.
3449 */
3450#pragma pack(1)
3451typedef union X86DESC
3452{
3453#ifndef VBOX_FOR_DTRACE_LIB
3454 /** Generic descriptor view. */
3455 X86DESCGENERIC Gen;
3456 /** Gate descriptor view. */
3457 X86DESCGATE Gate;
3458#endif
3459
3460 /** 8 bit unsigned integer view. */
3461 uint8_t au8[8];
3462 /** 16 bit unsigned integer view. */
3463 uint16_t au16[4];
3464 /** 32 bit unsigned integer view. */
3465 uint32_t au32[2];
3466 /** 64 bit unsigned integer view. */
3467 uint64_t au64[1];
3468 /** Unsigned integer view. */
3469 uint64_t u;
3470} X86DESC;
3471#ifndef VBOX_FOR_DTRACE_LIB
3472AssertCompileSize(X86DESC, 8);
3473#endif
3474#pragma pack()
3475/** Pointer to descriptor table entry. */
3476typedef X86DESC *PX86DESC;
3477/** Pointer to const descriptor table entry. */
3478typedef const X86DESC *PCX86DESC;
3479
3480/** @def X86DESC_BASE
3481 * Return the base address of a descriptor.
3482 */
3483#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
3484 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3485 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3486 | ( (a_pDesc)->Gen.u16BaseLow ) )
3487
3488/** @def X86DESC_LIMIT
3489 * Return the limit of a descriptor.
3490 */
3491#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
3492 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3493 | ( (a_pDesc)->Gen.u16LimitLow ) )
3494
3495/** @def X86DESC_LIMIT_G
3496 * Return the limit of a descriptor with the granularity bit taken into account.
3497 * @returns Selector limit (uint32_t).
3498 * @param a_pDesc Pointer to the descriptor.
3499 */
3500#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
3501 ( (a_pDesc)->Gen.u1Granularity \
3502 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
3503 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
3504 )
3505
3506/** @def X86DESC_GET_HID_ATTR
3507 * Get the descriptor attributes for the hidden register.
3508 */
3509#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
3510 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3511
3512#ifndef VBOX_FOR_DTRACE_LIB
3513
3514/**
3515 * 64 bits generic descriptor table entry
3516 * Note: most of these bits have no meaning in long mode.
3517 */
3518#pragma pack(1)
3519typedef struct X86DESC64GENERIC
3520{
3521 /** Limit - Low word - *IGNORED*. */
3522 uint32_t u16LimitLow : 16;
3523 /** Base address - low word. - *IGNORED*
3524 * Don't try set this to 24 because MSC is doing stupid things then. */
3525 uint32_t u16BaseLow : 16;
3526 /** Base address - first 8 bits of high word. - *IGNORED* */
3527 uint32_t u8BaseHigh1 : 8;
3528 /** Segment Type. */
3529 uint32_t u4Type : 4;
3530 /** Descriptor Type. System(=0) or code/data selector */
3531 uint32_t u1DescType : 1;
3532 /** Descriptor Privilege level. */
3533 uint32_t u2Dpl : 2;
3534 /** Flags selector present(=1) or not. */
3535 uint32_t u1Present : 1;
3536 /** Segment limit 16-19. - *IGNORED* */
3537 uint32_t u4LimitHigh : 4;
3538 /** Available for system software. - *IGNORED* */
3539 uint32_t u1Available : 1;
3540 /** Long mode flag. */
3541 uint32_t u1Long : 1;
3542 /** This flags meaning depends on the segment type. Try make sense out
3543 * of the intel manual yourself. */
3544 uint32_t u1DefBig : 1;
3545 /** Granularity of the limit. If set 4KB granularity is used, if
3546 * clear byte. - *IGNORED* */
3547 uint32_t u1Granularity : 1;
3548 /** Base address - highest 8 bits. - *IGNORED* */
3549 uint32_t u8BaseHigh2 : 8;
3550 /** Base address - bits 63-32. */
3551 uint32_t u32BaseHigh3 : 32;
3552 uint32_t u8Reserved : 8;
3553 uint32_t u5Zeros : 5;
3554 uint32_t u19Reserved : 19;
3555} X86DESC64GENERIC;
3556#pragma pack()
3557/** Pointer to a generic descriptor entry. */
3558typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3559/** Pointer to a const generic descriptor entry. */
3560typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3561
3562/**
3563 * System descriptor table entry (64 bits)
3564 *
3565 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3566 */
3567#pragma pack(1)
3568typedef struct X86DESC64SYSTEM
3569{
3570 /** Limit - Low word. */
3571 uint32_t u16LimitLow : 16;
3572 /** Base address - low word.
3573 * Don't try set this to 24 because MSC is doing stupid things then. */
3574 uint32_t u16BaseLow : 16;
3575 /** Base address - first 8 bits of high word. */
3576 uint32_t u8BaseHigh1 : 8;
3577 /** Segment Type. */
3578 uint32_t u4Type : 4;
3579 /** Descriptor Type. System(=0) or code/data selector */
3580 uint32_t u1DescType : 1;
3581 /** Descriptor Privilege level. */
3582 uint32_t u2Dpl : 2;
3583 /** Flags selector present(=1) or not. */
3584 uint32_t u1Present : 1;
3585 /** Segment limit 16-19. */
3586 uint32_t u4LimitHigh : 4;
3587 /** Available for system software. */
3588 uint32_t u1Available : 1;
3589 /** Reserved - 0. */
3590 uint32_t u1Reserved : 1;
3591 /** This flags meaning depends on the segment type. Try make sense out
3592 * of the intel manual yourself. */
3593 uint32_t u1DefBig : 1;
3594 /** Granularity of the limit. If set 4KB granularity is used, if
3595 * clear byte. */
3596 uint32_t u1Granularity : 1;
3597 /** Base address - bits 31-24. */
3598 uint32_t u8BaseHigh2 : 8;
3599 /** Base address - bits 63-32. */
3600 uint32_t u32BaseHigh3 : 32;
3601 uint32_t u8Reserved : 8;
3602 uint32_t u5Zeros : 5;
3603 uint32_t u19Reserved : 19;
3604} X86DESC64SYSTEM;
3605#pragma pack()
3606/** Pointer to a system descriptor entry. */
3607typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3608/** Pointer to a const system descriptor entry. */
3609typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3610
3611/**
3612 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3613 */
3614typedef struct X86DESC64GATE
3615{
3616 /** Target code segment offset - Low word. */
3617 uint32_t u16OffsetLow : 16;
3618 /** Target code segment selector. */
3619 uint32_t u16Sel : 16;
3620 /** Interrupt stack table for interrupt- and trap-gates.
3621 * Ignored by call-gates. */
3622 uint32_t u3IST : 3;
3623 /** Reserved / ignored. */
3624 uint32_t u5Reserved : 5;
3625 /** Segment Type. */
3626 uint32_t u4Type : 4;
3627 /** Descriptor Type (0 = system). */
3628 uint32_t u1DescType : 1;
3629 /** Descriptor Privilege level. */
3630 uint32_t u2Dpl : 2;
3631 /** Flags selector present(=1) or not. */
3632 uint32_t u1Present : 1;
3633 /** Target code segment offset - High word.
3634 * Ignored if task-gate. */
3635 uint32_t u16OffsetHigh : 16;
3636 /** Target code segment offset - Top dword.
3637 * Ignored if task-gate. */
3638 uint32_t u32OffsetTop : 32;
3639 /** Reserved / ignored / must be zero.
3640 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3641 uint32_t u32Reserved : 32;
3642} X86DESC64GATE;
3643AssertCompileSize(X86DESC64GATE, 16);
3644/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3645typedef X86DESC64GATE *PX86DESC64GATE;
3646/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3647typedef const X86DESC64GATE *PCX86DESC64GATE;
3648
3649#endif /* VBOX_FOR_DTRACE_LIB */
3650
3651/**
3652 * Descriptor table entry.
3653 */
3654#pragma pack(1)
3655typedef union X86DESC64
3656{
3657#ifndef VBOX_FOR_DTRACE_LIB
3658 /** Generic descriptor view. */
3659 X86DESC64GENERIC Gen;
3660 /** System descriptor view. */
3661 X86DESC64SYSTEM System;
3662 /** Gate descriptor view. */
3663 X86DESC64GATE Gate;
3664#endif
3665
3666 /** 8 bit unsigned integer view. */
3667 uint8_t au8[16];
3668 /** 16 bit unsigned integer view. */
3669 uint16_t au16[8];
3670 /** 32 bit unsigned integer view. */
3671 uint32_t au32[4];
3672 /** 64 bit unsigned integer view. */
3673 uint64_t au64[2];
3674} X86DESC64;
3675#ifndef VBOX_FOR_DTRACE_LIB
3676AssertCompileSize(X86DESC64, 16);
3677#endif
3678#pragma pack()
3679/** Pointer to descriptor table entry. */
3680typedef X86DESC64 *PX86DESC64;
3681/** Pointer to const descriptor table entry. */
3682typedef const X86DESC64 *PCX86DESC64;
3683
3684/** @def X86DESC64_BASE
3685 * Return the base of a 64-bit descriptor.
3686 */
3687#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
3688 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3689 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3690 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3691 | ( (a_pDesc)->Gen.u16BaseLow ) )
3692
3693
3694
3695/** @name Host system descriptor table entry - Use with care!
3696 * @{ */
3697/** Host system descriptor table entry. */
3698#if HC_ARCH_BITS == 64
3699typedef X86DESC64 X86DESCHC;
3700#else
3701typedef X86DESC X86DESCHC;
3702#endif
3703/** Pointer to a host system descriptor table entry. */
3704#if HC_ARCH_BITS == 64
3705typedef PX86DESC64 PX86DESCHC;
3706#else
3707typedef PX86DESC PX86DESCHC;
3708#endif
3709/** Pointer to a const host system descriptor table entry. */
3710#if HC_ARCH_BITS == 64
3711typedef PCX86DESC64 PCX86DESCHC;
3712#else
3713typedef PCX86DESC PCX86DESCHC;
3714#endif
3715/** @} */
3716
3717
3718/** @name Selector Descriptor Types.
3719 * @{
3720 */
3721
3722/** @name Non-System Selector Types.
3723 * @{ */
3724/** Code(=set)/Data(=clear) bit. */
3725#define X86_SEL_TYPE_CODE 8
3726/** Memory(=set)/System(=clear) bit. */
3727#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3728/** Accessed bit. */
3729#define X86_SEL_TYPE_ACCESSED 1
3730/** Expand down bit (for data selectors only). */
3731#define X86_SEL_TYPE_DOWN 4
3732/** Conforming bit (for code selectors only). */
3733#define X86_SEL_TYPE_CONF 4
3734/** Write bit (for data selectors only). */
3735#define X86_SEL_TYPE_WRITE 2
3736/** Read bit (for code selectors only). */
3737#define X86_SEL_TYPE_READ 2
3738/** The bit number of the code segment read bit (relative to u4Type). */
3739#define X86_SEL_TYPE_READ_BIT 1
3740
3741/** Read only selector type. */
3742#define X86_SEL_TYPE_RO 0
3743/** Accessed read only selector type. */
3744#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
3745/** Read write selector type. */
3746#define X86_SEL_TYPE_RW 2
3747/** Accessed read write selector type. */
3748#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
3749/** Expand down read only selector type. */
3750#define X86_SEL_TYPE_RO_DOWN 4
3751/** Accessed expand down read only selector type. */
3752#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
3753/** Expand down read write selector type. */
3754#define X86_SEL_TYPE_RW_DOWN 6
3755/** Accessed expand down read write selector type. */
3756#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
3757/** Execute only selector type. */
3758#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
3759/** Accessed execute only selector type. */
3760#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3761/** Execute and read selector type. */
3762#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
3763/** Accessed execute and read selector type. */
3764#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3765/** Conforming execute only selector type. */
3766#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
3767/** Accessed Conforming execute only selector type. */
3768#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3769/** Conforming execute and write selector type. */
3770#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
3771/** Accessed Conforming execute and write selector type. */
3772#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3773/** @} */
3774
3775
3776/** @name System Selector Types.
3777 * @{ */
3778/** The TSS busy bit mask. */
3779#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3780
3781/** Undefined system selector type. */
3782#define X86_SEL_TYPE_SYS_UNDEFINED 0
3783/** 286 TSS selector. */
3784#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3785/** LDT selector. */
3786#define X86_SEL_TYPE_SYS_LDT 2
3787/** 286 TSS selector - Busy. */
3788#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3789/** 286 Callgate selector. */
3790#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3791/** Taskgate selector. */
3792#define X86_SEL_TYPE_SYS_TASK_GATE 5
3793/** 286 Interrupt gate selector. */
3794#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3795/** 286 Trapgate selector. */
3796#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3797/** Undefined system selector. */
3798#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3799/** 386 TSS selector. */
3800#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3801/** Undefined system selector. */
3802#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3803/** 386 TSS selector - Busy. */
3804#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3805/** 386 Callgate selector. */
3806#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3807/** Undefined system selector. */
3808#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3809/** 386 Interruptgate selector. */
3810#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3811/** 386 Trapgate selector. */
3812#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3813/** @} */
3814
3815/** @name AMD64 System Selector Types.
3816 * @{ */
3817/** LDT selector. */
3818#define AMD64_SEL_TYPE_SYS_LDT 2
3819/** TSS selector - Busy. */
3820#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3821/** TSS selector - Busy. */
3822#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3823/** Callgate selector. */
3824#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3825/** Interruptgate selector. */
3826#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3827/** Trapgate selector. */
3828#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3829/** @} */
3830
3831/** @} */
3832
3833
3834/** @name Descriptor Table Entry Flag Masks.
3835 * These are for the 2nd 32-bit word of a descriptor.
3836 * @{ */
3837/** Bits 8-11 - TYPE - Descriptor type mask. */
3838#define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
3839/** Bit 12 - S - System (=0) or Code/Data (=1). */
3840#define X86_DESC_S RT_BIT_32(12)
3841/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3842#define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
3843/** Bit 15 - P - Present. */
3844#define X86_DESC_P RT_BIT_32(15)
3845/** Bit 20 - AVL - Available for system software. */
3846#define X86_DESC_AVL RT_BIT_32(20)
3847/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3848#define X86_DESC_DB RT_BIT_32(22)
3849/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3850 * used, if clear byte. */
3851#define X86_DESC_G RT_BIT_32(23)
3852/** @} */
3853
3854/** @} */
3855
3856
3857/** @name Task Segments.
3858 * @{
3859 */
3860
3861/**
3862 * The minimum TSS descriptor limit for 286 tasks.
3863 */
3864#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3865
3866/**
3867 * The minimum TSS descriptor segment limit for 386 tasks.
3868 */
3869#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3870
3871/**
3872 * 16-bit Task Segment (TSS).
3873 */
3874#pragma pack(1)
3875typedef struct X86TSS16
3876{
3877 /** Back link to previous task. (static) */
3878 RTSEL selPrev;
3879 /** Ring-0 stack pointer. (static) */
3880 uint16_t sp0;
3881 /** Ring-0 stack segment. (static) */
3882 RTSEL ss0;
3883 /** Ring-1 stack pointer. (static) */
3884 uint16_t sp1;
3885 /** Ring-1 stack segment. (static) */
3886 RTSEL ss1;
3887 /** Ring-2 stack pointer. (static) */
3888 uint16_t sp2;
3889 /** Ring-2 stack segment. (static) */
3890 RTSEL ss2;
3891 /** IP before task switch. */
3892 uint16_t ip;
3893 /** FLAGS before task switch. */
3894 uint16_t flags;
3895 /** AX before task switch. */
3896 uint16_t ax;
3897 /** CX before task switch. */
3898 uint16_t cx;
3899 /** DX before task switch. */
3900 uint16_t dx;
3901 /** BX before task switch. */
3902 uint16_t bx;
3903 /** SP before task switch. */
3904 uint16_t sp;
3905 /** BP before task switch. */
3906 uint16_t bp;
3907 /** SI before task switch. */
3908 uint16_t si;
3909 /** DI before task switch. */
3910 uint16_t di;
3911 /** ES before task switch. */
3912 RTSEL es;
3913 /** CS before task switch. */
3914 RTSEL cs;
3915 /** SS before task switch. */
3916 RTSEL ss;
3917 /** DS before task switch. */
3918 RTSEL ds;
3919 /** LDTR before task switch. */
3920 RTSEL selLdt;
3921} X86TSS16;
3922#ifndef VBOX_FOR_DTRACE_LIB
3923AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
3924#endif
3925#pragma pack()
3926/** Pointer to a 16-bit task segment. */
3927typedef X86TSS16 *PX86TSS16;
3928/** Pointer to a const 16-bit task segment. */
3929typedef const X86TSS16 *PCX86TSS16;
3930
3931
3932/**
3933 * 32-bit Task Segment (TSS).
3934 */
3935#pragma pack(1)
3936typedef struct X86TSS32
3937{
3938 /** Back link to previous task. (static) */
3939 RTSEL selPrev;
3940 uint16_t padding1;
3941 /** Ring-0 stack pointer. (static) */
3942 uint32_t esp0;
3943 /** Ring-0 stack segment. (static) */
3944 RTSEL ss0;
3945 uint16_t padding_ss0;
3946 /** Ring-1 stack pointer. (static) */
3947 uint32_t esp1;
3948 /** Ring-1 stack segment. (static) */
3949 RTSEL ss1;
3950 uint16_t padding_ss1;
3951 /** Ring-2 stack pointer. (static) */
3952 uint32_t esp2;
3953 /** Ring-2 stack segment. (static) */
3954 RTSEL ss2;
3955 uint16_t padding_ss2;
3956 /** Page directory for the task. (static) */
3957 uint32_t cr3;
3958 /** EIP before task switch. */
3959 uint32_t eip;
3960 /** EFLAGS before task switch. */
3961 uint32_t eflags;
3962 /** EAX before task switch. */
3963 uint32_t eax;
3964 /** ECX before task switch. */
3965 uint32_t ecx;
3966 /** EDX before task switch. */
3967 uint32_t edx;
3968 /** EBX before task switch. */
3969 uint32_t ebx;
3970 /** ESP before task switch. */
3971 uint32_t esp;
3972 /** EBP before task switch. */
3973 uint32_t ebp;
3974 /** ESI before task switch. */
3975 uint32_t esi;
3976 /** EDI before task switch. */
3977 uint32_t edi;
3978 /** ES before task switch. */
3979 RTSEL es;
3980 uint16_t padding_es;
3981 /** CS before task switch. */
3982 RTSEL cs;
3983 uint16_t padding_cs;
3984 /** SS before task switch. */
3985 RTSEL ss;
3986 uint16_t padding_ss;
3987 /** DS before task switch. */
3988 RTSEL ds;
3989 uint16_t padding_ds;
3990 /** FS before task switch. */
3991 RTSEL fs;
3992 uint16_t padding_fs;
3993 /** GS before task switch. */
3994 RTSEL gs;
3995 uint16_t padding_gs;
3996 /** LDTR before task switch. */
3997 RTSEL selLdt;
3998 uint16_t padding_ldt;
3999 /** Debug trap flag */
4000 uint16_t fDebugTrap;
4001 /** Offset relative to the TSS of the start of the I/O Bitmap
4002 * and the end of the interrupt redirection bitmap. */
4003 uint16_t offIoBitmap;
4004} X86TSS32;
4005#pragma pack()
4006/** Pointer to task segment. */
4007typedef X86TSS32 *PX86TSS32;
4008/** Pointer to const task segment. */
4009typedef const X86TSS32 *PCX86TSS32;
4010#ifndef VBOX_FOR_DTRACE_LIB
4011AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4012AssertCompileMemberOffset(X86TSS32, cr3, 28);
4013AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4014#endif
4015
4016/**
4017 * 64-bit Task segment.
4018 */
4019#pragma pack(1)
4020typedef struct X86TSS64
4021{
4022 /** Reserved. */
4023 uint32_t u32Reserved;
4024 /** Ring-0 stack pointer. (static) */
4025 uint64_t rsp0;
4026 /** Ring-1 stack pointer. (static) */
4027 uint64_t rsp1;
4028 /** Ring-2 stack pointer. (static) */
4029 uint64_t rsp2;
4030 /** Reserved. */
4031 uint32_t u32Reserved2[2];
4032 /* IST */
4033 uint64_t ist1;
4034 uint64_t ist2;
4035 uint64_t ist3;
4036 uint64_t ist4;
4037 uint64_t ist5;
4038 uint64_t ist6;
4039 uint64_t ist7;
4040 /* Reserved. */
4041 uint16_t u16Reserved[5];
4042 /** Offset relative to the TSS of the start of the I/O Bitmap
4043 * and the end of the interrupt redirection bitmap. */
4044 uint16_t offIoBitmap;
4045} X86TSS64;
4046#pragma pack()
4047/** Pointer to a 64-bit task segment. */
4048typedef X86TSS64 *PX86TSS64;
4049/** Pointer to a const 64-bit task segment. */
4050typedef const X86TSS64 *PCX86TSS64;
4051#ifndef VBOX_FOR_DTRACE_LIB
4052AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4053#endif
4054
4055/** @} */
4056
4057
4058/** @name Selectors.
4059 * @{
4060 */
4061
4062/**
4063 * The shift used to convert a selector from and to index an index (C).
4064 */
4065#define X86_SEL_SHIFT 3
4066
4067/**
4068 * The mask used to mask off the table indicator and RPL of an selector.
4069 */
4070#define X86_SEL_MASK 0xfff8U
4071
4072/**
4073 * The mask used to mask off the RPL of an selector.
4074 * This is suitable for checking for NULL selectors.
4075 */
4076#define X86_SEL_MASK_OFF_RPL 0xfffcU
4077
4078/**
4079 * The bit indicating that a selector is in the LDT and not in the GDT.
4080 */
4081#define X86_SEL_LDT 0x0004U
4082
4083/**
4084 * The bit mask for getting the RPL of a selector.
4085 */
4086#define X86_SEL_RPL 0x0003U
4087
4088/**
4089 * The mask covering both RPL and LDT.
4090 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4091 * checks.
4092 */
4093#define X86_SEL_RPL_LDT 0x0007U
4094
4095/** @} */
4096
4097
4098/**
4099 * x86 Exceptions/Faults/Traps.
4100 */
4101typedef enum X86XCPT
4102{
4103 /** \#DE - Divide error. */
4104 X86_XCPT_DE = 0x00,
4105 /** \#DB - Debug event (single step, DRx, ..) */
4106 X86_XCPT_DB = 0x01,
4107 /** NMI - Non-Maskable Interrupt */
4108 X86_XCPT_NMI = 0x02,
4109 /** \#BP - Breakpoint (INT3). */
4110 X86_XCPT_BP = 0x03,
4111 /** \#OF - Overflow (INTO). */
4112 X86_XCPT_OF = 0x04,
4113 /** \#BR - Bound range exceeded (BOUND). */
4114 X86_XCPT_BR = 0x05,
4115 /** \#UD - Undefined opcode. */
4116 X86_XCPT_UD = 0x06,
4117 /** \#NM - Device not available (math coprocessor device). */
4118 X86_XCPT_NM = 0x07,
4119 /** \#DF - Double fault. */
4120 X86_XCPT_DF = 0x08,
4121 /** ??? - Coprocessor segment overrun (obsolete). */
4122 X86_XCPT_CO_SEG_OVERRUN = 0x09,
4123 /** \#TS - Taskswitch (TSS). */
4124 X86_XCPT_TS = 0x0a,
4125 /** \#NP - Segment no present. */
4126 X86_XCPT_NP = 0x0b,
4127 /** \#SS - Stack segment fault. */
4128 X86_XCPT_SS = 0x0c,
4129 /** \#GP - General protection fault. */
4130 X86_XCPT_GP = 0x0d,
4131 /** \#PF - Page fault. */
4132 X86_XCPT_PF = 0x0e,
4133 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4134 /** \#MF - Math fault (FPU). */
4135 X86_XCPT_MF = 0x10,
4136 /** \#AC - Alignment check. */
4137 X86_XCPT_AC = 0x11,
4138 /** \#MC - Machine check. */
4139 X86_XCPT_MC = 0x12,
4140 /** \#XF - SIMD Floating-Pointer Exception. */
4141 X86_XCPT_XF = 0x13,
4142 /** \#VE - Virtualization Exception. */
4143 X86_XCPT_VE = 0x14,
4144 /** \#SX - Security Exception. */
4145 X86_XCPT_SX = 0x1e
4146} X86XCPT;
4147/** Pointer to a x86 exception code. */
4148typedef X86XCPT *PX86XCPT;
4149/** Pointer to a const x86 exception code. */
4150typedef const X86XCPT *PCX86XCPT;
4151/** The last valid (currently reserved) exception value. */
4152#define X86_XCPT_LAST 0x1f
4153
4154
4155/** @name Trap Error Codes
4156 * @{
4157 */
4158/** External indicator. */
4159#define X86_TRAP_ERR_EXTERNAL 1
4160/** IDT indicator. */
4161#define X86_TRAP_ERR_IDT 2
4162/** Descriptor table indicator - If set LDT, if clear GDT. */
4163#define X86_TRAP_ERR_TI 4
4164/** Mask for getting the selector. */
4165#define X86_TRAP_ERR_SEL_MASK 0xfff8
4166/** Shift for getting the selector table index (C type index). */
4167#define X86_TRAP_ERR_SEL_SHIFT 3
4168/** @} */
4169
4170
4171/** @name \#PF Trap Error Codes
4172 * @{
4173 */
4174/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4175#define X86_TRAP_PF_P RT_BIT_32(0)
4176/** Bit 1 - R/W - Read (clear) or write (set) access. */
4177#define X86_TRAP_PF_RW RT_BIT_32(1)
4178/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4179#define X86_TRAP_PF_US RT_BIT_32(2)
4180/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4181#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4182/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4183#define X86_TRAP_PF_ID RT_BIT_32(4)
4184/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4185#define X86_TRAP_PF_PK RT_BIT_32(5)
4186/** @} */
4187
4188#pragma pack(1)
4189/**
4190 * 16-bit IDTR.
4191 */
4192typedef struct X86IDTR16
4193{
4194 /** Offset. */
4195 uint16_t offSel;
4196 /** Selector. */
4197 uint16_t uSel;
4198} X86IDTR16, *PX86IDTR16;
4199#pragma pack()
4200
4201#pragma pack(1)
4202/**
4203 * 32-bit IDTR/GDTR.
4204 */
4205typedef struct X86XDTR32
4206{
4207 /** Size of the descriptor table. */
4208 uint16_t cb;
4209 /** Address of the descriptor table. */
4210#ifndef VBOX_FOR_DTRACE_LIB
4211 uint32_t uAddr;
4212#else
4213 uint16_t au16Addr[2];
4214#endif
4215} X86XDTR32, *PX86XDTR32;
4216#pragma pack()
4217
4218#pragma pack(1)
4219/**
4220 * 64-bit IDTR/GDTR.
4221 */
4222typedef struct X86XDTR64
4223{
4224 /** Size of the descriptor table. */
4225 uint16_t cb;
4226 /** Address of the descriptor table. */
4227#ifndef VBOX_FOR_DTRACE_LIB
4228 uint64_t uAddr;
4229#else
4230 uint16_t au16Addr[4];
4231#endif
4232} X86XDTR64, *PX86XDTR64;
4233#pragma pack()
4234
4235
4236/** @name ModR/M
4237 * @{ */
4238#define X86_MODRM_RM_MASK UINT8_C(0x07)
4239#define X86_MODRM_REG_MASK UINT8_C(0x38)
4240#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4241#define X86_MODRM_REG_SHIFT 3
4242#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4243#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4244#define X86_MODRM_MOD_SHIFT 6
4245#ifndef VBOX_FOR_DTRACE_LIB
4246AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
4247AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4248AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4249/** @def X86_MODRM_MAKE
4250 * @param a_Mod The mod value (0..3).
4251 * @param a_Reg The register value (0..7).
4252 * @param a_RegMem The register or memory value (0..7). */
4253# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
4254#endif
4255/** @} */
4256
4257/** @name SIB
4258 * @{ */
4259#define X86_SIB_BASE_MASK UINT8_C(0x07)
4260#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4261#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4262#define X86_SIB_INDEX_SHIFT 3
4263#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4264#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4265#define X86_SIB_SCALE_SHIFT 6
4266#ifndef VBOX_FOR_DTRACE_LIB
4267AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
4268AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4269AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4270#endif
4271/** @} */
4272
4273/** @name General register indexes
4274 * @{ */
4275#define X86_GREG_xAX 0
4276#define X86_GREG_xCX 1
4277#define X86_GREG_xDX 2
4278#define X86_GREG_xBX 3
4279#define X86_GREG_xSP 4
4280#define X86_GREG_xBP 5
4281#define X86_GREG_xSI 6
4282#define X86_GREG_xDI 7
4283#define X86_GREG_x8 8
4284#define X86_GREG_x9 9
4285#define X86_GREG_x10 10
4286#define X86_GREG_x11 11
4287#define X86_GREG_x12 12
4288#define X86_GREG_x13 13
4289#define X86_GREG_x14 14
4290#define X86_GREG_x15 15
4291/** @} */
4292
4293/** @name X86_SREG_XXX - Segment register indexes.
4294 * @{ */
4295#define X86_SREG_ES 0
4296#define X86_SREG_CS 1
4297#define X86_SREG_SS 2
4298#define X86_SREG_DS 3
4299#define X86_SREG_FS 4
4300#define X86_SREG_GS 5
4301/** @} */
4302/** Segment register count. */
4303#define X86_SREG_COUNT 6
4304
4305
4306/** @name X86_OP_XXX - Prefixes
4307 * @{ */
4308#define X86_OP_PRF_CS UINT8_C(0x2e)
4309#define X86_OP_PRF_SS UINT8_C(0x36)
4310#define X86_OP_PRF_DS UINT8_C(0x3e)
4311#define X86_OP_PRF_ES UINT8_C(0x26)
4312#define X86_OP_PRF_FS UINT8_C(0x64)
4313#define X86_OP_PRF_GS UINT8_C(0x65)
4314#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4315#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4316#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4317#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4318#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4319#define X86_OP_REX_B UINT8_C(0x41)
4320#define X86_OP_REX_X UINT8_C(0x42)
4321#define X86_OP_REX_R UINT8_C(0x44)
4322#define X86_OP_REX_W UINT8_C(0x48)
4323/** @} */
4324
4325
4326/** @} */
4327
4328#endif
4329
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette