x86.h@ 70286

Last change on this file since 70286 was 70265, checked in by vboxsync, 7 years ago
x86.h: DebugCtl MSR bits.
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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2017 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	#ifndef VBOX_FOR_DTRACE_LIB
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104	#endif /* !VBOX_FOR_DTRACE_LIB */
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	#ifndef VBOX_FOR_DTRACE_LIB
114	/** The bitfield view. */
115	X86EFLAGSBITS Bits;
116	#endif
117	/** The 8-bit view. */
118	uint8_t au8[4];
119	/** The 16-bit view. */
120	uint16_t au16[2];
121	/** The 32-bit view. */
122	uint32_t au32[1];
123	/** The 32-bit view. */
124	uint32_t u32;
125	} X86EFLAGS;
126	/** Pointer to EFLAGS. */
127	typedef X86EFLAGS *PX86EFLAGS;
128	/** Pointer to const EFLAGS. */
129	typedef const X86EFLAGS *PCX86EFLAGS;
130
131	/**
132	* RFLAGS (32 upper bits are reserved).
133	*/
134	typedef union X86RFLAGS
135	{
136	/** The plain unsigned view. */
137	uint64_t u;
138	#ifndef VBOX_FOR_DTRACE_LIB
139	/** The bitfield view. */
140	X86EFLAGSBITS Bits;
141	#endif
142	/** The 8-bit view. */
143	uint8_t au8[8];
144	/** The 16-bit view. */
145	uint16_t au16[4];
146	/** The 32-bit view. */
147	uint32_t au32[2];
148	/** The 64-bit view. */
149	uint64_t au64[1];
150	/** The 64-bit view. */
151	uint64_t u64;
152	} X86RFLAGS;
153	/** Pointer to RFLAGS. */
154	typedef X86RFLAGS *PX86RFLAGS;
155	/** Pointer to const RFLAGS. */
156	typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159	/** @name EFLAGS
160	* @{
161	*/
162	/** Bit 0 - CF - Carry flag - Status flag. */
163	#define X86_EFL_CF RT_BIT_32(0)
164	#define X86_EFL_CF_BIT 0
165	/** Bit 1 - Reserved, reads as 1. */
166	#define X86_EFL_1 RT_BIT_32(1)
167	/** Bit 2 - PF - Parity flag - Status flag. */
168	#define X86_EFL_PF RT_BIT_32(2)
169	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
170	#define X86_EFL_AF RT_BIT_32(4)
171	#define X86_EFL_AF_BIT 4
172	/** Bit 6 - ZF - Zero flag - Status flag. */
173	#define X86_EFL_ZF RT_BIT_32(6)
174	#define X86_EFL_ZF_BIT 6
175	/** Bit 7 - SF - Signed flag - Status flag. */
176	#define X86_EFL_SF RT_BIT_32(7)
177	#define X86_EFL_SF_BIT 7
178	/** Bit 8 - TF - Trap flag - System flag. */
179	#define X86_EFL_TF RT_BIT_32(8)
180	/** Bit 9 - IF - Interrupt flag - System flag. */
181	#define X86_EFL_IF RT_BIT_32(9)
182	/** Bit 10 - DF - Direction flag - Control flag. */
183	#define X86_EFL_DF RT_BIT_32(10)
184	/** Bit 11 - OF - Overflow flag - Status flag. */
185	#define X86_EFL_OF RT_BIT_32(11)
186	#define X86_EFL_OF_BIT 11
187	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
188	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
189	/** Bit 14 - NT - Nested task flag - System flag. */
190	#define X86_EFL_NT RT_BIT_32(14)
191	/** Bit 16 - RF - Resume flag - System flag. */
192	#define X86_EFL_RF RT_BIT_32(16)
193	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
194	#define X86_EFL_VM RT_BIT_32(17)
195	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
196	#define X86_EFL_AC RT_BIT_32(18)
197	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
198	#define X86_EFL_VIF RT_BIT_32(19)
199	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
200	#define X86_EFL_VIP RT_BIT_32(20)
201	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
202	#define X86_EFL_ID RT_BIT_32(21)
203	/** All live bits. */
204	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
205	/** Read as 1 bits. */
206	#define X86_EFL_RA1_MASK RT_BIT_32(1)
207	/** IOPL shift. */
208	#define X86_EFL_IOPL_SHIFT 12
209	/** The IOPL level from the flags. */
210	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
211	/** Bits restored by popf */
212	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
213	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
214	/** Bits restored by popf */
215	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
216	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
217	/** The status bits commonly updated by arithmetic instructions. */
218	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
219	/** @} */
220
221
222	/** CPUID Feature information - ECX.
223	* CPUID query with EAX=1.
224	*/
225	#ifndef VBOX_FOR_DTRACE_LIB
226	typedef struct X86CPUIDFEATECX
227	{
228	/** Bit 0 - SSE3 - Supports SSE3 or not. */
229	unsigned u1SSE3 : 1;
230	/** Bit 1 - PCLMULQDQ. */
231	unsigned u1PCLMULQDQ : 1;
232	/** Bit 2 - DS Area 64-bit layout. */
233	unsigned u1DTE64 : 1;
234	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
235	unsigned u1Monitor : 1;
236	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
237	unsigned u1CPLDS : 1;
238	/** Bit 5 - VMX - Virtual Machine Technology. */
239	unsigned u1VMX : 1;
240	/** Bit 6 - SMX: Safer Mode Extensions. */
241	unsigned u1SMX : 1;
242	/** Bit 7 - EST - Enh. SpeedStep Tech. */
243	unsigned u1EST : 1;
244	/** Bit 8 - TM2 - Terminal Monitor 2. */
245	unsigned u1TM2 : 1;
246	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
247	unsigned u1SSSE3 : 1;
248	/** Bit 10 - CNTX-ID - L1 Context ID. */
249	unsigned u1CNTXID : 1;
250	/** Bit 11 - Reserved. */
251	unsigned u1Reserved1 : 1;
252	/** Bit 12 - FMA. */
253	unsigned u1FMA : 1;
254	/** Bit 13 - CX16 - CMPXCHG16B. */
255	unsigned u1CX16 : 1;
256	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
257	unsigned u1TPRUpdate : 1;
258	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
259	unsigned u1PDCM : 1;
260	/** Bit 16 - Reserved. */
261	unsigned u1Reserved2 : 1;
262	/** Bit 17 - PCID - Process-context identifiers. */
263	unsigned u1PCID : 1;
264	/** Bit 18 - Direct Cache Access. */
265	unsigned u1DCA : 1;
266	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
267	unsigned u1SSE4_1 : 1;
268	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
269	unsigned u1SSE4_2 : 1;
270	/** Bit 21 - x2APIC. */
271	unsigned u1x2APIC : 1;
272	/** Bit 22 - MOVBE - Supports MOVBE. */
273	unsigned u1MOVBE : 1;
274	/** Bit 23 - POPCNT - Supports POPCNT. */
275	unsigned u1POPCNT : 1;
276	/** Bit 24 - TSC-Deadline. */
277	unsigned u1TSCDEADLINE : 1;
278	/** Bit 25 - AES. */
279	unsigned u1AES : 1;
280	/** Bit 26 - XSAVE - Supports XSAVE. */
281	unsigned u1XSAVE : 1;
282	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
283	unsigned u1OSXSAVE : 1;
284	/** Bit 28 - AVX - Supports AVX instruction extensions. */
285	unsigned u1AVX : 1;
286	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
287	unsigned u1F16C : 1;
288	/** Bit 30 - RDRAND - Supports RDRAND. */
289	unsigned u1RDRAND : 1;
290	/** Bit 31 - Hypervisor present (we're a guest). */
291	unsigned u1HVP : 1;
292	} X86CPUIDFEATECX;
293	#else /* VBOX_FOR_DTRACE_LIB */
294	typedef uint32_t X86CPUIDFEATECX;
295	#endif /* VBOX_FOR_DTRACE_LIB */
296	/** Pointer to CPUID Feature Information - ECX. */
297	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
298	/** Pointer to const CPUID Feature Information - ECX. */
299	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
300
301
302	/** CPUID Feature Information - EDX.
303	* CPUID query with EAX=1.
304	*/
305	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
306	typedef struct X86CPUIDFEATEDX
307	{
308	/** Bit 0 - FPU - x87 FPU on Chip. */
309	unsigned u1FPU : 1;
310	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
311	unsigned u1VME : 1;
312	/** Bit 2 - DE - Debugging extensions. */
313	unsigned u1DE : 1;
314	/** Bit 3 - PSE - Page Size Extension. */
315	unsigned u1PSE : 1;
316	/** Bit 4 - TSC - Time Stamp Counter. */
317	unsigned u1TSC : 1;
318	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
319	unsigned u1MSR : 1;
320	/** Bit 6 - PAE - Physical Address Extension. */
321	unsigned u1PAE : 1;
322	/** Bit 7 - MCE - Machine Check Exception. */
323	unsigned u1MCE : 1;
324	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
325	unsigned u1CX8 : 1;
326	/** Bit 9 - APIC - APIC On-Chip. */
327	unsigned u1APIC : 1;
328	/** Bit 10 - Reserved. */
329	unsigned u1Reserved1 : 1;
330	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
331	unsigned u1SEP : 1;
332	/** Bit 12 - MTRR - Memory Type Range Registers. */
333	unsigned u1MTRR : 1;
334	/** Bit 13 - PGE - PTE Global Bit. */
335	unsigned u1PGE : 1;
336	/** Bit 14 - MCA - Machine Check Architecture. */
337	unsigned u1MCA : 1;
338	/** Bit 15 - CMOV - Conditional Move Instructions. */
339	unsigned u1CMOV : 1;
340	/** Bit 16 - PAT - Page Attribute Table. */
341	unsigned u1PAT : 1;
342	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
343	unsigned u1PSE36 : 1;
344	/** Bit 18 - PSN - Processor Serial Number. */
345	unsigned u1PSN : 1;
346	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
347	unsigned u1CLFSH : 1;
348	/** Bit 20 - Reserved. */
349	unsigned u1Reserved2 : 1;
350	/** Bit 21 - DS - Debug Store. */
351	unsigned u1DS : 1;
352	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
353	unsigned u1ACPI : 1;
354	/** Bit 23 - MMX - Intel MMX 'Technology'. */
355	unsigned u1MMX : 1;
356	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
357	unsigned u1FXSR : 1;
358	/** Bit 25 - SSE - SSE Support. */
359	unsigned u1SSE : 1;
360	/** Bit 26 - SSE2 - SSE2 Support. */
361	unsigned u1SSE2 : 1;
362	/** Bit 27 - SS - Self Snoop. */
363	unsigned u1SS : 1;
364	/** Bit 28 - HTT - Hyper-Threading Technology. */
365	unsigned u1HTT : 1;
366	/** Bit 29 - TM - Thermal Monitor. */
367	unsigned u1TM : 1;
368	/** Bit 30 - Reserved - . */
369	unsigned u1Reserved3 : 1;
370	/** Bit 31 - PBE - Pending Break Enabled. */
371	unsigned u1PBE : 1;
372	} X86CPUIDFEATEDX;
373	#else /* VBOX_FOR_DTRACE_LIB */
374	typedef uint32_t X86CPUIDFEATEDX;
375	#endif /* VBOX_FOR_DTRACE_LIB */
376	/** Pointer to CPUID Feature Information - EDX. */
377	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
378	/** Pointer to const CPUID Feature Information - EDX. */
379	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
380
381	/** @name CPUID Vendor information.
382	* CPUID query with EAX=0.
383	* @{
384	*/
385	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
386	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
387	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
388
389	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
390	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
391	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
392
393	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
394	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
395	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
396	/** @} */
397
398
399	/** @name CPUID Feature information.
400	* CPUID query with EAX=1.
401	* @{
402	*/
403	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
404	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
405	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
406	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
407	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
408	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
409	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
410	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
411	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
412	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
413	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
414	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
415	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
416	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
417	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
418	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
419	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
420	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
421	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
422	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
423	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
424	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
425	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
426	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
427	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
428	/** ECX Bit 12 - FMA. */
429	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
430	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
431	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
432	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
433	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
434	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
435	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
436	/** ECX Bit 17 - PCID - Process-context identifiers. */
437	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
438	/** ECX Bit 18 - DCA - Direct Cache Access. */
439	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
440	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
441	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
442	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
443	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
444	/** ECX Bit 21 - x2APIC support. */
445	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
446	/** ECX Bit 22 - MOVBE instruction. */
447	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
448	/** ECX Bit 23 - POPCNT instruction. */
449	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
450	/** ECX Bir 24 - TSC-Deadline. */
451	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
452	/** ECX Bit 25 - AES instructions. */
453	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
454	/** ECX Bit 26 - XSAVE instruction. */
455	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
456	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
457	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
458	/** ECX Bit 28 - AVX. */
459	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
460	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
461	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
462	/** ECX Bit 30 - RDRAND instruction. */
463	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
464	/** ECX Bit 31 - Hypervisor Present (software only). */
465	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
466
467
468	/** Bit 0 - FPU - x87 FPU on Chip. */
469	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
470	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
471	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
472	/** Bit 2 - DE - Debugging extensions. */
473	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
474	/** Bit 3 - PSE - Page Size Extension. */
475	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
476	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
477	/** Bit 4 - TSC - Time Stamp Counter. */
478	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
479	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
480	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
481	/** Bit 6 - PAE - Physical Address Extension. */
482	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
483	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
484	/** Bit 7 - MCE - Machine Check Exception. */
485	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
486	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
487	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
488	/** Bit 9 - APIC - APIC On-Chip. */
489	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
490	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
491	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
492	/** Bit 12 - MTRR - Memory Type Range Registers. */
493	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
494	/** Bit 13 - PGE - PTE Global Bit. */
495	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
496	/** Bit 14 - MCA - Machine Check Architecture. */
497	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
498	/** Bit 15 - CMOV - Conditional Move Instructions. */
499	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
500	/** Bit 16 - PAT - Page Attribute Table. */
501	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
502	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
503	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
504	/** Bit 18 - PSN - Processor Serial Number. */
505	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
506	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
507	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
508	/** Bit 21 - DS - Debug Store. */
509	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
510	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
511	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
512	/** Bit 23 - MMX - Intel MMX Technology. */
513	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
514	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
515	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
516	/** Bit 25 - SSE - SSE Support. */
517	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
518	/** Bit 26 - SSE2 - SSE2 Support. */
519	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
520	/** Bit 27 - SS - Self Snoop. */
521	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
522	/** Bit 28 - HTT - Hyper-Threading Technology. */
523	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
524	/** Bit 29 - TM - Therm. Monitor. */
525	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
526	/** Bit 31 - PBE - Pending Break Enabled. */
527	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
528	/** @} */
529
530	/** @name CPUID mwait/monitor information.
531	* CPUID query with EAX=5.
532	* @{
533	*/
534	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
535	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
536	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
537	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
538	/** @} */
539
540
541	/** @name CPUID Structured Extended Feature information.
542	* CPUID query with EAX=7.
543	* @{
544	*/
545	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
546	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
547	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
548	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
549	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
550	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
551	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
552	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
553	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
554	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
555	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
556	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
557	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
558	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
559	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
560	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
561	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
562	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
563	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
564	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
565	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
566	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
567	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
568	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
569	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
570	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
571	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
572	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
573	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
574	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
575	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
576	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
577	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
578	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
579	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
580	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
581	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
582	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
583	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
584	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
585	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
586	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
587	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
588	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
589	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
590	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
591	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
592	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
593	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
594	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
595	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
596	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
597
598	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
599	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
600	/** @} */
601
602
603	/** @name CPUID Extended Feature information.
604	* CPUID query with EAX=0x80000001.
605	* @{
606	*/
607	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
608	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
609
610	/** EDX Bit 11 - SYSCALL/SYSRET. */
611	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
612	/** EDX Bit 20 - No-Execute/Execute-Disable. */
613	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
614	/** EDX Bit 26 - 1 GB large page. */
615	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
616	/** EDX Bit 27 - RDTSCP. */
617	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
618	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
619	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
620	/** @}*/
621
622	/** @name CPUID AMD Feature information.
623	* CPUID query with EAX=0x80000001.
624	* @{
625	*/
626	/** Bit 0 - FPU - x87 FPU on Chip. */
627	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
628	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
629	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
630	/** Bit 2 - DE - Debugging extensions. */
631	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
632	/** Bit 3 - PSE - Page Size Extension. */
633	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
634	/** Bit 4 - TSC - Time Stamp Counter. */
635	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
636	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
637	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
638	/** Bit 6 - PAE - Physical Address Extension. */
639	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
640	/** Bit 7 - MCE - Machine Check Exception. */
641	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
642	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
643	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
644	/** Bit 9 - APIC - APIC On-Chip. */
645	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
646	/** Bit 12 - MTRR - Memory Type Range Registers. */
647	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
648	/** Bit 13 - PGE - PTE Global Bit. */
649	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
650	/** Bit 14 - MCA - Machine Check Architecture. */
651	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
652	/** Bit 15 - CMOV - Conditional Move Instructions. */
653	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
654	/** Bit 16 - PAT - Page Attribute Table. */
655	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
656	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
657	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
658	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
659	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
660	/** Bit 23 - MMX - Intel MMX Technology. */
661	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
662	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
663	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
664	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
665	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
666	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
667	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
668	/** Bit 31 - 3DNOW - AMD 3DNow. */
669	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
670
671	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
672	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
673	/** Bit 2 - SVM - AMD VM extensions. */
674	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
675	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
676	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
677	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
678	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
679	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
680	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
681	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
682	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
683	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
684	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
685	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
686	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
687	/** Bit 9 - OSVW - AMD OS visible workaround. */
688	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
689	/** Bit 10 - IBS - Instruct based sampling. */
690	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
691	/** Bit 11 - XOP - Extended operation support (see APM6). */
692	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
693	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
694	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
695	/** Bit 13 - WDT - AMD Watchdog timer support. */
696	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
697	/** Bit 15 - LWP - Lightweight profiling support. */
698	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
699	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
700	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
701	/** Bit 19 - NodeId - Indicates support for
702	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
703	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
704	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
705	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
706	/** Bit 22 - TopologyExtensions - . */
707	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
708	/** @} */
709
710
711	/** @name CPUID AMD Feature information.
712	* CPUID query with EAX=0x80000007.
713	* @{
714	*/
715	/** Bit 0 - TS - Temperature Sensor. */
716	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
717	/** Bit 1 - FID - Frequency ID Control. */
718	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
719	/** Bit 2 - VID - Voltage ID Control. */
720	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
721	/** Bit 3 - TTP - THERMTRIP. */
722	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
723	/** Bit 4 - TM - Hardware Thermal Control. */
724	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
725	/** Bit 5 - STC - Software Thermal Control. */
726	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
727	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
728	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
729	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
730	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
731	/** Bit 8 - TSCINVAR - TSC Invariant. */
732	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
733	/** Bit 9 - CPB - TSC Invariant. */
734	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
735	/** Bit 10 - EffFreqRO - MPERF/APERF. */
736	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
737	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
738	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
739	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
740	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
741	/** @} */
742
743
744	/** @name CPUID AMD SVM Feature information.
745	* CPUID query with EAX=0x8000000a.
746	* @{
747	*/
748	/** Bit 0 - NP - Nested Paging supported. */
749	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
750	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
751	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
752	/** Bit 2 - SVML - SVM locking bit supported. */
753	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
754	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
755	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
756	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
757	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
758	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
759	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
760	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
761	* VMCB.TLB_Control is supported. */
762	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
763	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
764	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
765	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
766	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
767	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
768	* intercept filter cycle count threshold. */
769	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
770	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
771	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
772	/** Bit 15 - V_VMSAVE_VMLOAD - Supports virtualized VMSAVE/VMLOAD. */
773	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
774	/** Bit 16 - V_VMSAVE_VMLOAD - Supports virtualized GIF. */
775	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
776	/** @} */
777
778
779	/** @name CR0
780	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
781	* reserved flags.
782	* @{ */
783	/** Bit 0 - PE - Protection Enabled */
784	#define X86_CR0_PE RT_BIT_32(0)
785	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
786	/** Bit 1 - MP - Monitor Coprocessor */
787	#define X86_CR0_MP RT_BIT_32(1)
788	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
789	/** Bit 2 - EM - Emulation. */
790	#define X86_CR0_EM RT_BIT_32(2)
791	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
792	/** Bit 3 - TS - Task Switch. */
793	#define X86_CR0_TS RT_BIT_32(3)
794	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
795	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
796	#define X86_CR0_ET RT_BIT_32(4)
797	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
798	/** Bit 5 - NE - Numeric error (486+). */
799	#define X86_CR0_NE RT_BIT_32(5)
800	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
801	/** Bit 16 - WP - Write Protect (486+). */
802	#define X86_CR0_WP RT_BIT_32(16)
803	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
804	/** Bit 18 - AM - Alignment Mask (486+). */
805	#define X86_CR0_AM RT_BIT_32(18)
806	#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
807	/** Bit 29 - NW - Not Write-though (486+). */
808	#define X86_CR0_NW RT_BIT_32(29)
809	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
810	/** Bit 30 - WP - Cache Disable (486+). */
811	#define X86_CR0_CD RT_BIT_32(30)
812	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
813	/** Bit 31 - PG - Paging. */
814	#define X86_CR0_PG RT_BIT_32(31)
815	#define X86_CR0_PAGING RT_BIT_32(31)
816	/** @} */
817
818
819	/** @name CR3
820	* @{ */
821	/** Bit 3 - PWT - Page-level Writes Transparent. */
822	#define X86_CR3_PWT RT_BIT_32(3)
823	/** Bit 4 - PCD - Page-level Cache Disable. */
824	#define X86_CR3_PCD RT_BIT_32(4)
825	/** Bits 12-31 - - Page directory page number. */
826	#define X86_CR3_PAGE_MASK (0xfffff000)
827	/** Bits 5-31 - - PAE Page directory page number. */
828	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
829	/** Bits 12-51 - - AMD64 Page directory page number. */
830	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
831	/** @} */
832
833
834	/** @name CR4
835	* @{ */
836	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
837	#define X86_CR4_VME RT_BIT_32(0)
838	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
839	#define X86_CR4_PVI RT_BIT_32(1)
840	/** Bit 2 - TSD - Time Stamp Disable. */
841	#define X86_CR4_TSD RT_BIT_32(2)
842	/** Bit 3 - DE - Debugging Extensions. */
843	#define X86_CR4_DE RT_BIT_32(3)
844	/** Bit 4 - PSE - Page Size Extension. */
845	#define X86_CR4_PSE RT_BIT_32(4)
846	/** Bit 5 - PAE - Physical Address Extension. */
847	#define X86_CR4_PAE RT_BIT_32(5)
848	/** Bit 6 - MCE - Machine-Check Enable. */
849	#define X86_CR4_MCE RT_BIT_32(6)
850	/** Bit 7 - PGE - Page Global Enable. */
851	#define X86_CR4_PGE RT_BIT_32(7)
852	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
853	#define X86_CR4_PCE RT_BIT_32(8)
854	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
855	#define X86_CR4_OSFXSR RT_BIT_32(9)
856	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
857	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
858	/** Bit 13 - VMXE - VMX mode is enabled. */
859	#define X86_CR4_VMXE RT_BIT_32(13)
860	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
861	#define X86_CR4_SMXE RT_BIT_32(14)
862	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
863	#define X86_CR4_PCIDE RT_BIT_32(17)
864	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
865	* extended states. */
866	#define X86_CR4_OSXSAVE RT_BIT_32(18)
867	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
868	#define X86_CR4_SMEP RT_BIT_32(20)
869	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
870	#define X86_CR4_SMAP RT_BIT_32(21)
871	/** Bit 22 - PKE - Protection Key Enable. */
872	#define X86_CR4_PKE RT_BIT_32(22)
873	/** @} */
874
875
876	/** @name DR6
877	* @{ */
878	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
879	#define X86_DR6_B0 RT_BIT_32(0)
880	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
881	#define X86_DR6_B1 RT_BIT_32(1)
882	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
883	#define X86_DR6_B2 RT_BIT_32(2)
884	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
885	#define X86_DR6_B3 RT_BIT_32(3)
886	/** Mask of all the Bx bits. */
887	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
888	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
889	#define X86_DR6_BD RT_BIT_32(13)
890	/** Bit 14 - BS - Single step */
891	#define X86_DR6_BS RT_BIT_32(14)
892	/** Bit 15 - BT - Task switch. (TSS T bit.) */
893	#define X86_DR6_BT RT_BIT_32(15)
894	/** Value of DR6 after powerup/reset. */
895	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
896	/** Bits which must be 1s in DR6. */
897	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
898	/** Bits which must be 0s in DR6. */
899	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
900	/** Bits which must be 0s on writes to DR6. */
901	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
902	/** @} */
903
904	/** Get the DR6.Bx bit for a the given breakpoint. */
905	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
906
907
908	/** @name DR7
909	* @{ */
910	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
911	#define X86_DR7_L0 RT_BIT_32(0)
912	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
913	#define X86_DR7_G0 RT_BIT_32(1)
914	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
915	#define X86_DR7_L1 RT_BIT_32(2)
916	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
917	#define X86_DR7_G1 RT_BIT_32(3)
918	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
919	#define X86_DR7_L2 RT_BIT_32(4)
920	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
921	#define X86_DR7_G2 RT_BIT_32(5)
922	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
923	#define X86_DR7_L3 RT_BIT_32(6)
924	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
925	#define X86_DR7_G3 RT_BIT_32(7)
926	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
927	#define X86_DR7_LE RT_BIT_32(8)
928	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
929	#define X86_DR7_GE RT_BIT_32(9)
930
931	/** L0, L1, L2, and L3. */
932	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
933	/** L0, L1, L2, and L3. */
934	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
935
936	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
937	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
938	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
939	* instruction is executed.
940	* @see http://www.rcollins.org/secrets/DR7.html */
941	#define X86_DR7_ICE_IR RT_BIT_32(12)
942	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
943	* any DR register is accessed. */
944	#define X86_DR7_GD RT_BIT_32(13)
945	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
946	* Pentium. */
947	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
948	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
949	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
950	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
951	#define X86_DR7_RW0_MASK (3 << 16)
952	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
953	#define X86_DR7_LEN0_MASK (3 << 18)
954	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
955	#define X86_DR7_RW1_MASK (3 << 20)
956	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
957	#define X86_DR7_LEN1_MASK (3 << 22)
958	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
959	#define X86_DR7_RW2_MASK (3 << 24)
960	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
961	#define X86_DR7_LEN2_MASK (3 << 26)
962	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
963	#define X86_DR7_RW3_MASK (3 << 28)
964	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
965	#define X86_DR7_LEN3_MASK (3 << 30)
966
967	/** Bits which reads as 1s. */
968	#define X86_DR7_RA1_MASK RT_BIT_32(10)
969	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
970	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
971	/** Bits which must be 0s when writing to DR7. */
972	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
973
974	/** Calcs the L bit of Nth breakpoint.
975	* @param iBp The breakpoint number [0..3].
976	*/
977	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
978
979	/** Calcs the G bit of Nth breakpoint.
980	* @param iBp The breakpoint number [0..3].
981	*/
982	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
983
984	/** Calcs the L and G bits of Nth breakpoint.
985	* @param iBp The breakpoint number [0..3].
986	*/
987	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
988
989	/** @name Read/Write values.
990	* @{ */
991	/** Break on instruction fetch only. */
992	#define X86_DR7_RW_EO 0U
993	/** Break on write only. */
994	#define X86_DR7_RW_WO 1U
995	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
996	#define X86_DR7_RW_IO 2U
997	/** Break on read or write (but not instruction fetches). */
998	#define X86_DR7_RW_RW 3U
999	/** @} */
1000
1001	/** Shifts a X86_DR7_RW_* value to its right place.
1002	* @param iBp The breakpoint number [0..3].
1003	* @param fRw One of the X86_DR7_RW_* value.
1004	*/
1005	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1006
1007	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1008	* one of the X86_DR7_RW_XXX constants).
1009	*
1010	* @returns X86_DR7_RW_XXX
1011	* @param uDR7 DR7 value
1012	* @param iBp The breakpoint number [0..3].
1013	*/
1014	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1015
1016	/** R/W0, R/W1, R/W2, and R/W3. */
1017	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1018
1019	#ifndef VBOX_FOR_DTRACE_LIB
1020	/** Checks if there are any I/O breakpoint types configured in the RW
1021	* registers. Does NOT check if these are enabled, sorry. */
1022	# define X86_DR7_ANY_RW_IO(uDR7) \
1023	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1024	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1025	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1026	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1027	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1028	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1029	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1030	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1031	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1032	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1033	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1034	#endif /* !VBOX_FOR_DTRACE_LIB */
1035
1036	/** @name Length values.
1037	* @{ */
1038	#define X86_DR7_LEN_BYTE 0U
1039	#define X86_DR7_LEN_WORD 1U
1040	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
1041	#define X86_DR7_LEN_DWORD 3U
1042	/** @} */
1043
1044	/** Shifts a X86_DR7_LEN_* value to its right place.
1045	* @param iBp The breakpoint number [0..3].
1046	* @param cb One of the X86_DR7_LEN_* values.
1047	*/
1048	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1049
1050	/** Fetch the breakpoint length bits from the DR7 value.
1051	* @param uDR7 DR7 value
1052	* @param iBp The breakpoint number [0..3].
1053	*/
1054	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1055
1056	/** Mask used to check if any breakpoints are enabled. */
1057	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1058
1059	/** LEN0, LEN1, LEN2, and LEN3. */
1060	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1061	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1062	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1063
1064	/** Value of DR7 after powerup/reset. */
1065	#define X86_DR7_INIT_VAL 0x400
1066	/** @} */
1067
1068
1069	/** @name Machine Specific Registers
1070	* @{
1071	*/
1072	/** Machine check address register (P5). */
1073	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1074	/** Machine check type register (P5). */
1075	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1076	/** Time Stamp Counter. */
1077	#define MSR_IA32_TSC 0x10
1078	#define MSR_IA32_CESR UINT32_C(0x00000011)
1079	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1080	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1081
1082	#define MSR_IA32_PLATFORM_ID 0x17
1083
1084	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1085	# define MSR_IA32_APICBASE 0x1b
1086	/** Local APIC enabled. */
1087	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1088	/** X2APIC enabled (requires the EN bit to be set). */
1089	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1090	/** The processor is the boot strap processor (BSP). */
1091	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1092	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1093	* width. */
1094	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1095	/** The default physical base address of the APIC. */
1096	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1097	/** Gets the physical base address from the MSR. */
1098	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1099	#endif
1100
1101	/** Undocumented intel MSR for reporting thread and core counts.
1102	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1103	* first 16 bits is the thread count. The next 16 bits the core count, except
1104	* on Westmere where it seems it's only the next 4 bits for some reason. */
1105	#define MSR_CORE_THREAD_COUNT 0x35
1106
1107	/** CPU Feature control. */
1108	#define MSR_IA32_FEATURE_CONTROL 0x3A
1109	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_32(0)
1110	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_32(1)
1111	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_32(2)
1112
1113	/** Per-processor TSC adjust MSR. */
1114	#define MSR_IA32_TSC_ADJUST 0x3B
1115
1116	/** BIOS update trigger (microcode update). */
1117	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1118
1119	/** BIOS update signature (microcode). */
1120	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1121
1122	/** SMM monitor control. */
1123	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1124
1125	/** General performance counter no. 0. */
1126	#define MSR_IA32_PMC0 0xC1
1127	/** General performance counter no. 1. */
1128	#define MSR_IA32_PMC1 0xC2
1129	/** General performance counter no. 2. */
1130	#define MSR_IA32_PMC2 0xC3
1131	/** General performance counter no. 3. */
1132	#define MSR_IA32_PMC3 0xC4
1133
1134	/** Nehalem power control. */
1135	#define MSR_IA32_PLATFORM_INFO 0xCE
1136
1137	/** Get FSB clock status (Intel-specific). */
1138	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1139
1140	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1141	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1142
1143	/** C0 Maximum Frequency Clock Count */
1144	#define MSR_IA32_MPERF 0xE7
1145	/** C0 Actual Frequency Clock Count */
1146	#define MSR_IA32_APERF 0xE8
1147
1148	/** MTRR Capabilities. */
1149	#define MSR_IA32_MTRR_CAP 0xFE
1150
1151	/** Cache control/info. */
1152	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1153
1154	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1155	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1156	* R0 SS == CS + 8
1157	* R3 CS == CS + 16
1158	* R3 SS == CS + 24
1159	*/
1160	#define MSR_IA32_SYSENTER_CS 0x174
1161	/** SYSENTER_ESP - the R0 ESP. */
1162	#define MSR_IA32_SYSENTER_ESP 0x175
1163	/** SYSENTER_EIP - the R0 EIP. */
1164	#define MSR_IA32_SYSENTER_EIP 0x176
1165	#endif
1166
1167	/** Machine Check Global Capabilities Register. */
1168	#define MSR_IA32_MCG_CAP 0x179
1169	/** Machine Check Global Status Register. */
1170	#define MSR_IA32_MCG_STATUS 0x17A
1171	/** Machine Check Global Control Register. */
1172	#define MSR_IA32_MCG_CTRL 0x17B
1173
1174	/** Page Attribute Table. */
1175	#define MSR_IA32_CR_PAT 0x277
1176
1177	/** Performance counter MSRs. (Intel only) */
1178	#define MSR_IA32_PERFEVTSEL0 0x186
1179	#define MSR_IA32_PERFEVTSEL1 0x187
1180	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1181	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1182	* holds a ratio that Apple takes for TSC granularity.
1183	*
1184	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1185	#define MSR_FLEX_RATIO 0x194
1186	/** Performance state value and starting with Intel core more.
1187	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1188	#define MSR_IA32_PERF_STATUS 0x198
1189	#define MSR_IA32_PERF_CTL 0x199
1190	#define MSR_IA32_THERM_STATUS 0x19c
1191
1192	/** Enable misc. processor features (R/W). */
1193	#define MSR_IA32_MISC_ENABLE 0x1A0
1194	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1195	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1196	/** Automatic Thermal Control Circuit Enable (R/W). */
1197	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1198	/** Performance Monitoring Available (R). */
1199	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1200	/** Branch Trace Storage Unavailable (R/O). */
1201	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1202	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1203	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1204	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1205	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1206	/** If MONITOR/MWAIT is supported (R/W). */
1207	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1208	/** Limit CPUID Maxval to 3 leafs (R/W). */
1209	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1210	/** When set to 1, xTPR messages are disabled (R/W). */
1211	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1212	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1213	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1214
1215	/** Trace/Profile Resource Control (R/W) */
1216	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1217	/** Last branch record. */
1218	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1219	/** Branch trace flag (single step on branches). */
1220	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1221	/** Performance monitoring pin control (AMD only). */
1222	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1223	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1224	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1225	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1226	/** Trace message enable (Intel only). */
1227	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1228	/** Branch trace store (Intel only). */
1229	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1230	/** Branch trace interrupt (Intel only). */
1231	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1232	/** Branch trace off in privileged code (Intel only). */
1233	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1234	/** Branch trace off in user code (Intel only). */
1235	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1236	/** Freeze LBR on PMI flag (Intel only). */
1237	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1238	/** Freeze PERFMON on PMI flag (Intel only). */
1239	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1240	/** Freeze while SMM enabled (Intel only). */
1241	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1242	/** Advanced debugging of RTM regions (Intel only). */
1243	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1244
1245	/** The number (0..3 or 0..15) of the last branch record register on P4 and
1246	* related Xeons. */
1247	#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1248	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1249	* @{ */
1250	#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1251	#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1252	#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1253	#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1254	/** @} */
1255
1256
1257	#define IA32_MTRR_PHYSBASE0 0x200
1258	#define IA32_MTRR_PHYSMASK0 0x201
1259	#define IA32_MTRR_PHYSBASE1 0x202
1260	#define IA32_MTRR_PHYSMASK1 0x203
1261	#define IA32_MTRR_PHYSBASE2 0x204
1262	#define IA32_MTRR_PHYSMASK2 0x205
1263	#define IA32_MTRR_PHYSBASE3 0x206
1264	#define IA32_MTRR_PHYSMASK3 0x207
1265	#define IA32_MTRR_PHYSBASE4 0x208
1266	#define IA32_MTRR_PHYSMASK4 0x209
1267	#define IA32_MTRR_PHYSBASE5 0x20a
1268	#define IA32_MTRR_PHYSMASK5 0x20b
1269	#define IA32_MTRR_PHYSBASE6 0x20c
1270	#define IA32_MTRR_PHYSMASK6 0x20d
1271	#define IA32_MTRR_PHYSBASE7 0x20e
1272	#define IA32_MTRR_PHYSMASK7 0x20f
1273	#define IA32_MTRR_PHYSBASE8 0x210
1274	#define IA32_MTRR_PHYSMASK8 0x211
1275	#define IA32_MTRR_PHYSBASE9 0x212
1276	#define IA32_MTRR_PHYSMASK9 0x213
1277
1278	/** Fixed range MTRRs.
1279	* @{ */
1280	#define IA32_MTRR_FIX64K_00000 0x250
1281	#define IA32_MTRR_FIX16K_80000 0x258
1282	#define IA32_MTRR_FIX16K_A0000 0x259
1283	#define IA32_MTRR_FIX4K_C0000 0x268
1284	#define IA32_MTRR_FIX4K_C8000 0x269
1285	#define IA32_MTRR_FIX4K_D0000 0x26a
1286	#define IA32_MTRR_FIX4K_D8000 0x26b
1287	#define IA32_MTRR_FIX4K_E0000 0x26c
1288	#define IA32_MTRR_FIX4K_E8000 0x26d
1289	#define IA32_MTRR_FIX4K_F0000 0x26e
1290	#define IA32_MTRR_FIX4K_F8000 0x26f
1291	/** @} */
1292
1293	/** MTRR Default Range. */
1294	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1295
1296	/** Global performance counter control facilities (Intel only). */
1297	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1298	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1299	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1300
1301	/** Precise Event Based sampling (Intel only). */
1302	#define MSR_IA32_PEBS_ENABLE 0x3F1
1303
1304	#define MSR_IA32_MC0_CTL 0x400
1305	#define MSR_IA32_MC0_STATUS 0x401
1306
1307	/** Basic VMX information. */
1308	#define MSR_IA32_VMX_BASIC_INFO 0x480
1309	/** Allowed settings for pin-based VM execution controls */
1310	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1311	/** Allowed settings for proc-based VM execution controls */
1312	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1313	/** Allowed settings for the VMX exit controls. */
1314	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1315	/** Allowed settings for the VMX entry controls. */
1316	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1317	/** Misc VMX info. */
1318	#define MSR_IA32_VMX_MISC 0x485
1319	/** Fixed cleared bits in CR0. */
1320	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1321	/** Fixed set bits in CR0. */
1322	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1323	/** Fixed cleared bits in CR4. */
1324	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1325	/** Fixed set bits in CR4. */
1326	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1327	/** Information for enumerating fields in the VMCS. */
1328	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1329	/** Allowed settings for the VM-functions controls. */
1330	#define MSR_IA32_VMX_VMFUNC 0x491
1331	/** Allowed settings for secondary proc-based VM execution controls */
1332	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1333	/** EPT capabilities. */
1334	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1335	/** Allowed settings of all pin-based VM execution controls. */
1336	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1337	/** Allowed settings of all proc-based VM execution controls. */
1338	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1339	/** Allowed settings of all VMX exit controls. */
1340	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1341	/** Allowed settings of all VMX entry controls. */
1342	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1343
1344	/** DS Save Area (R/W). */
1345	#define MSR_IA32_DS_AREA 0x600
1346	/** Running Average Power Limit (RAPL) power units. */
1347	#define MSR_RAPL_POWER_UNIT 0x606
1348
1349	/** X2APIC MSR range start. */
1350	#define MSR_IA32_X2APIC_START 0x800
1351	/** X2APIC MSR - APIC ID Register. */
1352	#define MSR_IA32_X2APIC_ID 0x802
1353	/** X2APIC MSR - APIC Version Register. */
1354	#define MSR_IA32_X2APIC_VERSION 0x803
1355	/** X2APIC MSR - Task Priority Register. */
1356	#define MSR_IA32_X2APIC_TPR 0x808
1357	/** X2APIC MSR - Processor Priority register. */
1358	#define MSR_IA32_X2APIC_PPR 0x80A
1359	/** X2APIC MSR - End Of Interrupt register. */
1360	#define MSR_IA32_X2APIC_EOI 0x80B
1361	/** X2APIC MSR - Logical Destination Register. */
1362	#define MSR_IA32_X2APIC_LDR 0x80D
1363	/** X2APIC MSR - Spurious Interrupt Vector Register. */
1364	#define MSR_IA32_X2APIC_SVR 0x80F
1365	/** X2APIC MSR - In-service Register (bits 31:0). */
1366	#define MSR_IA32_X2APIC_ISR0 0x810
1367	/** X2APIC MSR - In-service Register (bits 63:32). */
1368	#define MSR_IA32_X2APIC_ISR1 0x811
1369	/** X2APIC MSR - In-service Register (bits 95:64). */
1370	#define MSR_IA32_X2APIC_ISR2 0x812
1371	/** X2APIC MSR - In-service Register (bits 127:96). */
1372	#define MSR_IA32_X2APIC_ISR3 0x813
1373	/** X2APIC MSR - In-service Register (bits 159:128). */
1374	#define MSR_IA32_X2APIC_ISR4 0x814
1375	/** X2APIC MSR - In-service Register (bits 191:160). */
1376	#define MSR_IA32_X2APIC_ISR5 0x815
1377	/** X2APIC MSR - In-service Register (bits 223:192). */
1378	#define MSR_IA32_X2APIC_ISR6 0x816
1379	/** X2APIC MSR - In-service Register (bits 255:224). */
1380	#define MSR_IA32_X2APIC_ISR7 0x817
1381	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1382	#define MSR_IA32_X2APIC_TMR0 0x818
1383	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1384	#define MSR_IA32_X2APIC_TMR1 0x819
1385	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1386	#define MSR_IA32_X2APIC_TMR2 0x81A
1387	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1388	#define MSR_IA32_X2APIC_TMR3 0x81B
1389	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1390	#define MSR_IA32_X2APIC_TMR4 0x81C
1391	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1392	#define MSR_IA32_X2APIC_TMR5 0x81D
1393	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1394	#define MSR_IA32_X2APIC_TMR6 0x81E
1395	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1396	#define MSR_IA32_X2APIC_TMR7 0x81F
1397	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1398	#define MSR_IA32_X2APIC_IRR0 0x820
1399	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1400	#define MSR_IA32_X2APIC_IRR1 0x821
1401	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1402	#define MSR_IA32_X2APIC_IRR2 0x822
1403	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1404	#define MSR_IA32_X2APIC_IRR3 0x823
1405	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1406	#define MSR_IA32_X2APIC_IRR4 0x824
1407	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1408	#define MSR_IA32_X2APIC_IRR5 0x825
1409	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1410	#define MSR_IA32_X2APIC_IRR6 0x826
1411	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1412	#define MSR_IA32_X2APIC_IRR7 0x827
1413	/** X2APIC MSR - Error Status Register. */
1414	#define MSR_IA32_X2APIC_ESR 0x828
1415	/** X2APIC MSR - LVT CMCI Register. */
1416	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1417	/** X2APIC MSR - Interrupt Command Register. */
1418	#define MSR_IA32_X2APIC_ICR 0x830
1419	/** X2APIC MSR - LVT Timer Register. */
1420	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1421	/** X2APIC MSR - LVT Thermal Sensor Register. */
1422	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1423	/** X2APIC MSR - LVT Performance Counter Register. */
1424	#define MSR_IA32_X2APIC_LVT_PERF 0x834
1425	/** X2APIC MSR - LVT LINT0 Register. */
1426	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1427	/** X2APIC MSR - LVT LINT1 Register. */
1428	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1429	/** X2APIC MSR - LVT Error Register . */
1430	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1431	/** X2APIC MSR - Timer Initial Count Register. */
1432	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1433	/** X2APIC MSR - Timer Current Count Register. */
1434	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1435	/** X2APIC MSR - Timer Divide Configuration Register. */
1436	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1437	/** X2APIC MSR - Self IPI. */
1438	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1439	/** X2APIC MSR range end. */
1440	#define MSR_IA32_X2APIC_END 0xBFF
1441	/** X2APIC MSR - LVT start range. */
1442	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1443	/** X2APIC MSR - LVT end range (inclusive). */
1444	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1445
1446	/** K6 EFER - Extended Feature Enable Register. */
1447	#define MSR_K6_EFER UINT32_C(0xc0000080)
1448	/** @todo document EFER */
1449	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1450	#define MSR_K6_EFER_SCE RT_BIT_32(0)
1451	/** Bit 8 - LME - Long mode enabled. (R/W) */
1452	#define MSR_K6_EFER_LME RT_BIT_32(8)
1453	/** Bit 10 - LMA - Long mode active. (R) */
1454	#define MSR_K6_EFER_LMA RT_BIT_32(10)
1455	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1456	#define MSR_K6_EFER_NXE RT_BIT_32(11)
1457	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
1458	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1459	#define MSR_K6_EFER_SVME RT_BIT_32(12)
1460	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1461	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1462	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1463	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1464	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1465	#define MSR_K6_EFER_TCE RT_BIT_32(15)
1466	/** K6 STAR - SYSCALL/RET targets. */
1467	#define MSR_K6_STAR UINT32_C(0xc0000081)
1468	/** Shift value for getting the SYSRET CS and SS value. */
1469	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1470	/** Shift value for getting the SYSCALL CS and SS value. */
1471	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1472	/** Selector mask for use after shifting. */
1473	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1474	/** The mask which give the SYSCALL EIP. */
1475	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1476	/** K6 WHCR - Write Handling Control Register. */
1477	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1478	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1479	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1480	/** K6 PSOR - Processor State Observability Register. */
1481	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1482	/** K6 PFIR - Page Flush/Invalidate Register. */
1483	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1484
1485	/** Performance counter MSRs. (AMD only) */
1486	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1487	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1488	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1489	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1490	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1491	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1492	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1493	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1494
1495	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1496	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1497	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1498	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1499	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1500	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1501	/** K8 FS.base - The 64-bit base FS register. */
1502	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1503	/** K8 GS.base - The 64-bit base GS register. */
1504	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1505	/** K8 KernelGSbase - Used with SWAPGS. */
1506	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1507	/** K8 TSC_AUX - Used with RDTSCP. */
1508	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1509	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1510	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1511	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1512	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1513	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1514	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1515	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1516	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1517	/** North bridge config? See BIOS & Kernel dev guides for
1518	* details. */
1519	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1520
1521	/** Hypertransport interrupt pending register.
1522	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1523	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1524
1525	/** SVM Control. */
1526	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1527	/** Disables HDT (Hardware Debug Tool) and certain internal debug
1528	* features. */
1529	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1530	/** If set, non-intercepted INIT signals are converted to \#SX
1531	* exceptions. */
1532	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1533	/** Disables A20 masking. */
1534	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1535	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1536	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1537	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1538	* clear, EFER.SVME can be written normally. */
1539	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1540
1541	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1542	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1543	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1544	* host state during world switch. */
1545	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1546
1547	/** @} */
1548
1549
1550	/** @name Page Table / Directory / Directory Pointers / L4.
1551	* @{
1552	*/
1553
1554	/** Page table/directory entry as an unsigned integer. */
1555	typedef uint32_t X86PGUINT;
1556	/** Pointer to a page table/directory table entry as an unsigned integer. */
1557	typedef X86PGUINT *PX86PGUINT;
1558	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1559	typedef X86PGUINT const *PCX86PGUINT;
1560
1561	/** Number of entries in a 32-bit PT/PD. */
1562	#define X86_PG_ENTRIES 1024
1563
1564
1565	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1566	typedef uint64_t X86PGPAEUINT;
1567	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1568	typedef X86PGPAEUINT *PX86PGPAEUINT;
1569	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1570	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1571
1572	/** Number of entries in a PAE PT/PD. */
1573	#define X86_PG_PAE_ENTRIES 512
1574	/** Number of entries in a PAE PDPT. */
1575	#define X86_PG_PAE_PDPE_ENTRIES 4
1576
1577	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1578	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1579	/** Number of entries in an AMD64 PDPT.
1580	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1581	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1582
1583	/** The size of a default page. */
1584	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1585	/** The page shift of a default page. */
1586	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1587	/** The default page offset mask. */
1588	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1589	/** The default page base mask for virtual addresses. */
1590	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1591	/** The default page base mask for virtual addresses - 32bit version. */
1592	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1593
1594	/** The size of a 4KB page. */
1595	#define X86_PAGE_4K_SIZE _4K
1596	/** The page shift of a 4KB page. */
1597	#define X86_PAGE_4K_SHIFT 12
1598	/** The 4KB page offset mask. */
1599	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1600	/** The 4KB page base mask for virtual addresses. */
1601	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1602	/** The 4KB page base mask for virtual addresses - 32bit version. */
1603	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1604
1605	/** The size of a 2MB page. */
1606	#define X86_PAGE_2M_SIZE _2M
1607	/** The page shift of a 2MB page. */
1608	#define X86_PAGE_2M_SHIFT 21
1609	/** The 2MB page offset mask. */
1610	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1611	/** The 2MB page base mask for virtual addresses. */
1612	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1613	/** The 2MB page base mask for virtual addresses - 32bit version. */
1614	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1615
1616	/** The size of a 4MB page. */
1617	#define X86_PAGE_4M_SIZE _4M
1618	/** The page shift of a 4MB page. */
1619	#define X86_PAGE_4M_SHIFT 22
1620	/** The 4MB page offset mask. */
1621	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1622	/** The 4MB page base mask for virtual addresses. */
1623	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1624	/** The 4MB page base mask for virtual addresses - 32bit version. */
1625	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1626
1627	/**
1628	* Check if the given address is canonical.
1629	*/
1630	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1631
1632
1633	/** @name Page Table Entry
1634	* @{
1635	*/
1636	/** Bit 0 - P - Present bit. */
1637	#define X86_PTE_BIT_P 0
1638	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1639	#define X86_PTE_BIT_RW 1
1640	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1641	#define X86_PTE_BIT_US 2
1642	/** Bit 3 - PWT - Page level write thru bit. */
1643	#define X86_PTE_BIT_PWT 3
1644	/** Bit 4 - PCD - Page level cache disable bit. */
1645	#define X86_PTE_BIT_PCD 4
1646	/** Bit 5 - A - Access bit. */
1647	#define X86_PTE_BIT_A 5
1648	/** Bit 6 - D - Dirty bit. */
1649	#define X86_PTE_BIT_D 6
1650	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1651	#define X86_PTE_BIT_PAT 7
1652	/** Bit 8 - G - Global flag. */
1653	#define X86_PTE_BIT_G 8
1654	/** Bits 63 - NX - PAE/LM - No execution flag. */
1655	#define X86_PTE_PAE_BIT_NX 63
1656
1657	/** Bit 0 - P - Present bit mask. */
1658	#define X86_PTE_P RT_BIT_32(0)
1659	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1660	#define X86_PTE_RW RT_BIT_32(1)
1661	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1662	#define X86_PTE_US RT_BIT_32(2)
1663	/** Bit 3 - PWT - Page level write thru bit mask. */
1664	#define X86_PTE_PWT RT_BIT_32(3)
1665	/** Bit 4 - PCD - Page level cache disable bit mask. */
1666	#define X86_PTE_PCD RT_BIT_32(4)
1667	/** Bit 5 - A - Access bit mask. */
1668	#define X86_PTE_A RT_BIT_32(5)
1669	/** Bit 6 - D - Dirty bit mask. */
1670	#define X86_PTE_D RT_BIT_32(6)
1671	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1672	#define X86_PTE_PAT RT_BIT_32(7)
1673	/** Bit 8 - G - Global bit mask. */
1674	#define X86_PTE_G RT_BIT_32(8)
1675
1676	/** Bits 9-11 - - Available for use to system software. */
1677	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
1678	/** Bits 12-31 - - Physical Page number of the next level. */
1679	#define X86_PTE_PG_MASK ( 0xfffff000 )
1680
1681	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1682	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1683	/** Bits 63 - NX - PAE/LM - No execution flag. */
1684	#define X86_PTE_PAE_NX RT_BIT_64(63)
1685	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1686	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1687	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1688	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1689	/** No bits - - LM - MBZ bits when NX is active. */
1690	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1691	/** Bits 63 - - LM - MBZ bits when no NX. */
1692	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1693
1694	/**
1695	* Page table entry.
1696	*/
1697	typedef struct X86PTEBITS
1698	{
1699	/** Flags whether(=1) or not the page is present. */
1700	uint32_t u1Present : 1;
1701	/** Read(=0) / Write(=1) flag. */
1702	uint32_t u1Write : 1;
1703	/** User(=1) / Supervisor (=0) flag. */
1704	uint32_t u1User : 1;
1705	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1706	uint32_t u1WriteThru : 1;
1707	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1708	uint32_t u1CacheDisable : 1;
1709	/** Accessed flag.
1710	* Indicates that the page have been read or written to. */
1711	uint32_t u1Accessed : 1;
1712	/** Dirty flag.
1713	* Indicates that the page has been written to. */
1714	uint32_t u1Dirty : 1;
1715	/** Reserved / If PAT enabled, bit 2 of the index. */
1716	uint32_t u1PAT : 1;
1717	/** Global flag. (Ignored in all but final level.) */
1718	uint32_t u1Global : 1;
1719	/** Available for use to system software. */
1720	uint32_t u3Available : 3;
1721	/** Physical Page number of the next level. */
1722	uint32_t u20PageNo : 20;
1723	} X86PTEBITS;
1724	#ifndef VBOX_FOR_DTRACE_LIB
1725	AssertCompileSize(X86PTEBITS, 4);
1726	#endif
1727	/** Pointer to a page table entry. */
1728	typedef X86PTEBITS *PX86PTEBITS;
1729	/** Pointer to a const page table entry. */
1730	typedef const X86PTEBITS *PCX86PTEBITS;
1731
1732	/**
1733	* Page table entry.
1734	*/
1735	typedef union X86PTE
1736	{
1737	/** Unsigned integer view */
1738	X86PGUINT u;
1739	/** Bit field view. */
1740	X86PTEBITS n;
1741	/** 32-bit view. */
1742	uint32_t au32[1];
1743	/** 16-bit view. */
1744	uint16_t au16[2];
1745	/** 8-bit view. */
1746	uint8_t au8[4];
1747	} X86PTE;
1748	#ifndef VBOX_FOR_DTRACE_LIB
1749	AssertCompileSize(X86PTE, 4);
1750	#endif
1751	/** Pointer to a page table entry. */
1752	typedef X86PTE *PX86PTE;
1753	/** Pointer to a const page table entry. */
1754	typedef const X86PTE *PCX86PTE;
1755
1756
1757	/**
1758	* PAE page table entry.
1759	*/
1760	typedef struct X86PTEPAEBITS
1761	{
1762	/** Flags whether(=1) or not the page is present. */
1763	uint32_t u1Present : 1;
1764	/** Read(=0) / Write(=1) flag. */
1765	uint32_t u1Write : 1;
1766	/** User(=1) / Supervisor(=0) flag. */
1767	uint32_t u1User : 1;
1768	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1769	uint32_t u1WriteThru : 1;
1770	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1771	uint32_t u1CacheDisable : 1;
1772	/** Accessed flag.
1773	* Indicates that the page have been read or written to. */
1774	uint32_t u1Accessed : 1;
1775	/** Dirty flag.
1776	* Indicates that the page has been written to. */
1777	uint32_t u1Dirty : 1;
1778	/** Reserved / If PAT enabled, bit 2 of the index. */
1779	uint32_t u1PAT : 1;
1780	/** Global flag. (Ignored in all but final level.) */
1781	uint32_t u1Global : 1;
1782	/** Available for use to system software. */
1783	uint32_t u3Available : 3;
1784	/** Physical Page number of the next level - Low Part. Don't use this. */
1785	uint32_t u20PageNoLow : 20;
1786	/** Physical Page number of the next level - High Part. Don't use this. */
1787	uint32_t u20PageNoHigh : 20;
1788	/** MBZ bits */
1789	uint32_t u11Reserved : 11;
1790	/** No Execute flag. */
1791	uint32_t u1NoExecute : 1;
1792	} X86PTEPAEBITS;
1793	#ifndef VBOX_FOR_DTRACE_LIB
1794	AssertCompileSize(X86PTEPAEBITS, 8);
1795	#endif
1796	/** Pointer to a page table entry. */
1797	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1798	/** Pointer to a page table entry. */
1799	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1800
1801	/**
1802	* PAE Page table entry.
1803	*/
1804	typedef union X86PTEPAE
1805	{
1806	/** Unsigned integer view */
1807	X86PGPAEUINT u;
1808	/** Bit field view. */
1809	X86PTEPAEBITS n;
1810	/** 32-bit view. */
1811	uint32_t au32[2];
1812	/** 16-bit view. */
1813	uint16_t au16[4];
1814	/** 8-bit view. */
1815	uint8_t au8[8];
1816	} X86PTEPAE;
1817	#ifndef VBOX_FOR_DTRACE_LIB
1818	AssertCompileSize(X86PTEPAE, 8);
1819	#endif
1820	/** Pointer to a PAE page table entry. */
1821	typedef X86PTEPAE *PX86PTEPAE;
1822	/** Pointer to a const PAE page table entry. */
1823	typedef const X86PTEPAE *PCX86PTEPAE;
1824	/** @} */
1825
1826	/**
1827	* Page table.
1828	*/
1829	typedef struct X86PT
1830	{
1831	/** PTE Array. */
1832	X86PTE a[X86_PG_ENTRIES];
1833	} X86PT;
1834	#ifndef VBOX_FOR_DTRACE_LIB
1835	AssertCompileSize(X86PT, 4096);
1836	#endif
1837	/** Pointer to a page table. */
1838	typedef X86PT *PX86PT;
1839	/** Pointer to a const page table. */
1840	typedef const X86PT *PCX86PT;
1841
1842	/** The page shift to get the PT index. */
1843	#define X86_PT_SHIFT 12
1844	/** The PT index mask (apply to a shifted page address). */
1845	#define X86_PT_MASK 0x3ff
1846
1847
1848	/**
1849	* Page directory.
1850	*/
1851	typedef struct X86PTPAE
1852	{
1853	/** PTE Array. */
1854	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1855	} X86PTPAE;
1856	#ifndef VBOX_FOR_DTRACE_LIB
1857	AssertCompileSize(X86PTPAE, 4096);
1858	#endif
1859	/** Pointer to a page table. */
1860	typedef X86PTPAE *PX86PTPAE;
1861	/** Pointer to a const page table. */
1862	typedef const X86PTPAE *PCX86PTPAE;
1863
1864	/** The page shift to get the PA PTE index. */
1865	#define X86_PT_PAE_SHIFT 12
1866	/** The PAE PT index mask (apply to a shifted page address). */
1867	#define X86_PT_PAE_MASK 0x1ff
1868
1869
1870	/** @name 4KB Page Directory Entry
1871	* @{
1872	*/
1873	/** Bit 0 - P - Present bit. */
1874	#define X86_PDE_P RT_BIT_32(0)
1875	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1876	#define X86_PDE_RW RT_BIT_32(1)
1877	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1878	#define X86_PDE_US RT_BIT_32(2)
1879	/** Bit 3 - PWT - Page level write thru bit. */
1880	#define X86_PDE_PWT RT_BIT_32(3)
1881	/** Bit 4 - PCD - Page level cache disable bit. */
1882	#define X86_PDE_PCD RT_BIT_32(4)
1883	/** Bit 5 - A - Access bit. */
1884	#define X86_PDE_A RT_BIT_32(5)
1885	/** Bit 7 - PS - Page size attribute.
1886	* Clear mean 4KB pages, set means large pages (2/4MB). */
1887	#define X86_PDE_PS RT_BIT_32(7)
1888	/** Bits 9-11 - - Available for use to system software. */
1889	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
1890	/** Bits 12-31 - - Physical Page number of the next level. */
1891	#define X86_PDE_PG_MASK ( 0xfffff000 )
1892
1893	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1894	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1895	/** Bits 63 - NX - PAE/LM - No execution flag. */
1896	#define X86_PDE_PAE_NX RT_BIT_64(63)
1897	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1898	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1899	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1900	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1901	/** Bit 7 - - LM - MBZ bits when NX is active. */
1902	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1903	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1904	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1905
1906	/**
1907	* Page directory entry.
1908	*/
1909	typedef struct X86PDEBITS
1910	{
1911	/** Flags whether(=1) or not the page is present. */
1912	uint32_t u1Present : 1;
1913	/** Read(=0) / Write(=1) flag. */
1914	uint32_t u1Write : 1;
1915	/** User(=1) / Supervisor (=0) flag. */
1916	uint32_t u1User : 1;
1917	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1918	uint32_t u1WriteThru : 1;
1919	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1920	uint32_t u1CacheDisable : 1;
1921	/** Accessed flag.
1922	* Indicates that the page has been read or written to. */
1923	uint32_t u1Accessed : 1;
1924	/** Reserved / Ignored (dirty bit). */
1925	uint32_t u1Reserved0 : 1;
1926	/** Size bit if PSE is enabled - in any event it's 0. */
1927	uint32_t u1Size : 1;
1928	/** Reserved / Ignored (global bit). */
1929	uint32_t u1Reserved1 : 1;
1930	/** Available for use to system software. */
1931	uint32_t u3Available : 3;
1932	/** Physical Page number of the next level. */
1933	uint32_t u20PageNo : 20;
1934	} X86PDEBITS;
1935	#ifndef VBOX_FOR_DTRACE_LIB
1936	AssertCompileSize(X86PDEBITS, 4);
1937	#endif
1938	/** Pointer to a page directory entry. */
1939	typedef X86PDEBITS *PX86PDEBITS;
1940	/** Pointer to a const page directory entry. */
1941	typedef const X86PDEBITS *PCX86PDEBITS;
1942
1943
1944	/**
1945	* PAE page directory entry.
1946	*/
1947	typedef struct X86PDEPAEBITS
1948	{
1949	/** Flags whether(=1) or not the page is present. */
1950	uint32_t u1Present : 1;
1951	/** Read(=0) / Write(=1) flag. */
1952	uint32_t u1Write : 1;
1953	/** User(=1) / Supervisor (=0) flag. */
1954	uint32_t u1User : 1;
1955	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1956	uint32_t u1WriteThru : 1;
1957	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1958	uint32_t u1CacheDisable : 1;
1959	/** Accessed flag.
1960	* Indicates that the page has been read or written to. */
1961	uint32_t u1Accessed : 1;
1962	/** Reserved / Ignored (dirty bit). */
1963	uint32_t u1Reserved0 : 1;
1964	/** Size bit if PSE is enabled - in any event it's 0. */
1965	uint32_t u1Size : 1;
1966	/** Reserved / Ignored (global bit). / */
1967	uint32_t u1Reserved1 : 1;
1968	/** Available for use to system software. */
1969	uint32_t u3Available : 3;
1970	/** Physical Page number of the next level - Low Part. Don't use! */
1971	uint32_t u20PageNoLow : 20;
1972	/** Physical Page number of the next level - High Part. Don't use! */
1973	uint32_t u20PageNoHigh : 20;
1974	/** MBZ bits */
1975	uint32_t u11Reserved : 11;
1976	/** No Execute flag. */
1977	uint32_t u1NoExecute : 1;
1978	} X86PDEPAEBITS;
1979	#ifndef VBOX_FOR_DTRACE_LIB
1980	AssertCompileSize(X86PDEPAEBITS, 8);
1981	#endif
1982	/** Pointer to a page directory entry. */
1983	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1984	/** Pointer to a const page directory entry. */
1985	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1986
1987	/** @} */
1988
1989
1990	/** @name 2/4MB Page Directory Entry
1991	* @{
1992	*/
1993	/** Bit 0 - P - Present bit. */
1994	#define X86_PDE4M_P RT_BIT_32(0)
1995	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1996	#define X86_PDE4M_RW RT_BIT_32(1)
1997	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1998	#define X86_PDE4M_US RT_BIT_32(2)
1999	/** Bit 3 - PWT - Page level write thru bit. */
2000	#define X86_PDE4M_PWT RT_BIT_32(3)
2001	/** Bit 4 - PCD - Page level cache disable bit. */
2002	#define X86_PDE4M_PCD RT_BIT_32(4)
2003	/** Bit 5 - A - Access bit. */
2004	#define X86_PDE4M_A RT_BIT_32(5)
2005	/** Bit 6 - D - Dirty bit. */
2006	#define X86_PDE4M_D RT_BIT_32(6)
2007	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2008	#define X86_PDE4M_PS RT_BIT_32(7)
2009	/** Bit 8 - G - Global flag. */
2010	#define X86_PDE4M_G RT_BIT_32(8)
2011	/** Bits 9-11 - AVL - Available for use to system software. */
2012	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2013	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2014	#define X86_PDE4M_PAT RT_BIT_32(12)
2015	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2016	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2017	/** Bits 22-31 - - Physical Page number. */
2018	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2019	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2020	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2021	/** The number of bits to the high part of the page number. */
2022	#define X86_PDE4M_PG_HIGH_SHIFT 19
2023	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2024	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2025
2026	/** Bits 21-51 - - PAE/LM - Physical Page number.
2027	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2028	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2029	/** Bits 63 - NX - PAE/LM - No execution flag. */
2030	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2031	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2032	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2033	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2034	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2035	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2036	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2037	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2038	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2039
2040	/**
2041	* 4MB page directory entry.
2042	*/
2043	typedef struct X86PDE4MBITS
2044	{
2045	/** Flags whether(=1) or not the page is present. */
2046	uint32_t u1Present : 1;
2047	/** Read(=0) / Write(=1) flag. */
2048	uint32_t u1Write : 1;
2049	/** User(=1) / Supervisor (=0) flag. */
2050	uint32_t u1User : 1;
2051	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2052	uint32_t u1WriteThru : 1;
2053	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2054	uint32_t u1CacheDisable : 1;
2055	/** Accessed flag.
2056	* Indicates that the page have been read or written to. */
2057	uint32_t u1Accessed : 1;
2058	/** Dirty flag.
2059	* Indicates that the page has been written to. */
2060	uint32_t u1Dirty : 1;
2061	/** Page size flag - always 1 for 4MB entries. */
2062	uint32_t u1Size : 1;
2063	/** Global flag. */
2064	uint32_t u1Global : 1;
2065	/** Available for use to system software. */
2066	uint32_t u3Available : 3;
2067	/** Reserved / If PAT enabled, bit 2 of the index. */
2068	uint32_t u1PAT : 1;
2069	/** Bits 32-39 of the page number on AMD64.
2070	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2071	uint32_t u8PageNoHigh : 8;
2072	/** Reserved. */
2073	uint32_t u1Reserved : 1;
2074	/** Physical Page number of the page. */
2075	uint32_t u10PageNo : 10;
2076	} X86PDE4MBITS;
2077	#ifndef VBOX_FOR_DTRACE_LIB
2078	AssertCompileSize(X86PDE4MBITS, 4);
2079	#endif
2080	/** Pointer to a page table entry. */
2081	typedef X86PDE4MBITS *PX86PDE4MBITS;
2082	/** Pointer to a const page table entry. */
2083	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2084
2085
2086	/**
2087	* 2MB PAE page directory entry.
2088	*/
2089	typedef struct X86PDE2MPAEBITS
2090	{
2091	/** Flags whether(=1) or not the page is present. */
2092	uint32_t u1Present : 1;
2093	/** Read(=0) / Write(=1) flag. */
2094	uint32_t u1Write : 1;
2095	/** User(=1) / Supervisor(=0) flag. */
2096	uint32_t u1User : 1;
2097	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2098	uint32_t u1WriteThru : 1;
2099	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2100	uint32_t u1CacheDisable : 1;
2101	/** Accessed flag.
2102	* Indicates that the page have been read or written to. */
2103	uint32_t u1Accessed : 1;
2104	/** Dirty flag.
2105	* Indicates that the page has been written to. */
2106	uint32_t u1Dirty : 1;
2107	/** Page size flag - always 1 for 2MB entries. */
2108	uint32_t u1Size : 1;
2109	/** Global flag. */
2110	uint32_t u1Global : 1;
2111	/** Available for use to system software. */
2112	uint32_t u3Available : 3;
2113	/** Reserved / If PAT enabled, bit 2 of the index. */
2114	uint32_t u1PAT : 1;
2115	/** Reserved. */
2116	uint32_t u9Reserved : 9;
2117	/** Physical Page number of the next level - Low part. Don't use! */
2118	uint32_t u10PageNoLow : 10;
2119	/** Physical Page number of the next level - High part. Don't use! */
2120	uint32_t u20PageNoHigh : 20;
2121	/** MBZ bits */
2122	uint32_t u11Reserved : 11;
2123	/** No Execute flag. */
2124	uint32_t u1NoExecute : 1;
2125	} X86PDE2MPAEBITS;
2126	#ifndef VBOX_FOR_DTRACE_LIB
2127	AssertCompileSize(X86PDE2MPAEBITS, 8);
2128	#endif
2129	/** Pointer to a 2MB PAE page table entry. */
2130	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2131	/** Pointer to a 2MB PAE page table entry. */
2132	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2133
2134	/** @} */
2135
2136	/**
2137	* Page directory entry.
2138	*/
2139	typedef union X86PDE
2140	{
2141	/** Unsigned integer view. */
2142	X86PGUINT u;
2143	/** Normal view. */
2144	X86PDEBITS n;
2145	/** 4MB view (big). */
2146	X86PDE4MBITS b;
2147	/** 8 bit unsigned integer view. */
2148	uint8_t au8[4];
2149	/** 16 bit unsigned integer view. */
2150	uint16_t au16[2];
2151	/** 32 bit unsigned integer view. */
2152	uint32_t au32[1];
2153	} X86PDE;
2154	#ifndef VBOX_FOR_DTRACE_LIB
2155	AssertCompileSize(X86PDE, 4);
2156	#endif
2157	/** Pointer to a page directory entry. */
2158	typedef X86PDE *PX86PDE;
2159	/** Pointer to a const page directory entry. */
2160	typedef const X86PDE *PCX86PDE;
2161
2162	/**
2163	* PAE page directory entry.
2164	*/
2165	typedef union X86PDEPAE
2166	{
2167	/** Unsigned integer view. */
2168	X86PGPAEUINT u;
2169	/** Normal view. */
2170	X86PDEPAEBITS n;
2171	/** 2MB page view (big). */
2172	X86PDE2MPAEBITS b;
2173	/** 8 bit unsigned integer view. */
2174	uint8_t au8[8];
2175	/** 16 bit unsigned integer view. */
2176	uint16_t au16[4];
2177	/** 32 bit unsigned integer view. */
2178	uint32_t au32[2];
2179	} X86PDEPAE;
2180	#ifndef VBOX_FOR_DTRACE_LIB
2181	AssertCompileSize(X86PDEPAE, 8);
2182	#endif
2183	/** Pointer to a page directory entry. */
2184	typedef X86PDEPAE *PX86PDEPAE;
2185	/** Pointer to a const page directory entry. */
2186	typedef const X86PDEPAE *PCX86PDEPAE;
2187
2188	/**
2189	* Page directory.
2190	*/
2191	typedef struct X86PD
2192	{
2193	/** PDE Array. */
2194	X86PDE a[X86_PG_ENTRIES];
2195	} X86PD;
2196	#ifndef VBOX_FOR_DTRACE_LIB
2197	AssertCompileSize(X86PD, 4096);
2198	#endif
2199	/** Pointer to a page directory. */
2200	typedef X86PD *PX86PD;
2201	/** Pointer to a const page directory. */
2202	typedef const X86PD *PCX86PD;
2203
2204	/** The page shift to get the PD index. */
2205	#define X86_PD_SHIFT 22
2206	/** The PD index mask (apply to a shifted page address). */
2207	#define X86_PD_MASK 0x3ff
2208
2209
2210	/**
2211	* PAE page directory.
2212	*/
2213	typedef struct X86PDPAE
2214	{
2215	/** PDE Array. */
2216	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2217	} X86PDPAE;
2218	#ifndef VBOX_FOR_DTRACE_LIB
2219	AssertCompileSize(X86PDPAE, 4096);
2220	#endif
2221	/** Pointer to a PAE page directory. */
2222	typedef X86PDPAE *PX86PDPAE;
2223	/** Pointer to a const PAE page directory. */
2224	typedef const X86PDPAE *PCX86PDPAE;
2225
2226	/** The page shift to get the PAE PD index. */
2227	#define X86_PD_PAE_SHIFT 21
2228	/** The PAE PD index mask (apply to a shifted page address). */
2229	#define X86_PD_PAE_MASK 0x1ff
2230
2231
2232	/** @name Page Directory Pointer Table Entry (PAE)
2233	* @{
2234	*/
2235	/** Bit 0 - P - Present bit. */
2236	#define X86_PDPE_P RT_BIT_32(0)
2237	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2238	#define X86_PDPE_RW RT_BIT_32(1)
2239	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2240	#define X86_PDPE_US RT_BIT_32(2)
2241	/** Bit 3 - PWT - Page level write thru bit. */
2242	#define X86_PDPE_PWT RT_BIT_32(3)
2243	/** Bit 4 - PCD - Page level cache disable bit. */
2244	#define X86_PDPE_PCD RT_BIT_32(4)
2245	/** Bit 5 - A - Access bit. Long Mode only. */
2246	#define X86_PDPE_A RT_BIT_32(5)
2247	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2248	#define X86_PDPE_LM_PS RT_BIT_32(7)
2249	/** Bits 9-11 - - Available for use to system software. */
2250	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2251	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2252	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2253	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2254	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2255	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2256	#define X86_PDPE_LM_NX RT_BIT_64(63)
2257	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2258	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2259	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2260	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2261	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2262	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2263	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2264	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2265
2266
2267	/**
2268	* Page directory pointer table entry.
2269	*/
2270	typedef struct X86PDPEBITS
2271	{
2272	/** Flags whether(=1) or not the page is present. */
2273	uint32_t u1Present : 1;
2274	/** Chunk of reserved bits. */
2275	uint32_t u2Reserved : 2;
2276	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2277	uint32_t u1WriteThru : 1;
2278	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2279	uint32_t u1CacheDisable : 1;
2280	/** Chunk of reserved bits. */
2281	uint32_t u4Reserved : 4;
2282	/** Available for use to system software. */
2283	uint32_t u3Available : 3;
2284	/** Physical Page number of the next level - Low Part. Don't use! */
2285	uint32_t u20PageNoLow : 20;
2286	/** Physical Page number of the next level - High Part. Don't use! */
2287	uint32_t u20PageNoHigh : 20;
2288	/** MBZ bits */
2289	uint32_t u12Reserved : 12;
2290	} X86PDPEBITS;
2291	#ifndef VBOX_FOR_DTRACE_LIB
2292	AssertCompileSize(X86PDPEBITS, 8);
2293	#endif
2294	/** Pointer to a page directory pointer table entry. */
2295	typedef X86PDPEBITS *PX86PTPEBITS;
2296	/** Pointer to a const page directory pointer table entry. */
2297	typedef const X86PDPEBITS *PCX86PTPEBITS;
2298
2299	/**
2300	* Page directory pointer table entry. AMD64 version
2301	*/
2302	typedef struct X86PDPEAMD64BITS
2303	{
2304	/** Flags whether(=1) or not the page is present. */
2305	uint32_t u1Present : 1;
2306	/** Read(=0) / Write(=1) flag. */
2307	uint32_t u1Write : 1;
2308	/** User(=1) / Supervisor (=0) flag. */
2309	uint32_t u1User : 1;
2310	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2311	uint32_t u1WriteThru : 1;
2312	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2313	uint32_t u1CacheDisable : 1;
2314	/** Accessed flag.
2315	* Indicates that the page have been read or written to. */
2316	uint32_t u1Accessed : 1;
2317	/** Chunk of reserved bits. */
2318	uint32_t u3Reserved : 3;
2319	/** Available for use to system software. */
2320	uint32_t u3Available : 3;
2321	/** Physical Page number of the next level - Low Part. Don't use! */
2322	uint32_t u20PageNoLow : 20;
2323	/** Physical Page number of the next level - High Part. Don't use! */
2324	uint32_t u20PageNoHigh : 20;
2325	/** MBZ bits */
2326	uint32_t u11Reserved : 11;
2327	/** No Execute flag. */
2328	uint32_t u1NoExecute : 1;
2329	} X86PDPEAMD64BITS;
2330	#ifndef VBOX_FOR_DTRACE_LIB
2331	AssertCompileSize(X86PDPEAMD64BITS, 8);
2332	#endif
2333	/** Pointer to a page directory pointer table entry. */
2334	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2335	/** Pointer to a const page directory pointer table entry. */
2336	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2337
2338	/**
2339	* Page directory pointer table entry for 1GB page. (AMD64 only)
2340	*/
2341	typedef struct X86PDPE1GB
2342	{
2343	/** 0: Flags whether(=1) or not the page is present. */
2344	uint32_t u1Present : 1;
2345	/** 1: Read(=0) / Write(=1) flag. */
2346	uint32_t u1Write : 1;
2347	/** 2: User(=1) / Supervisor (=0) flag. */
2348	uint32_t u1User : 1;
2349	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2350	uint32_t u1WriteThru : 1;
2351	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2352	uint32_t u1CacheDisable : 1;
2353	/** 5: Accessed flag.
2354	* Indicates that the page have been read or written to. */
2355	uint32_t u1Accessed : 1;
2356	/** 6: Dirty flag for 1GB pages. */
2357	uint32_t u1Dirty : 1;
2358	/** 7: Indicates 1GB page if set. */
2359	uint32_t u1Size : 1;
2360	/** 8: Global 1GB page. */
2361	uint32_t u1Global: 1;
2362	/** 9-11: Available for use to system software. */
2363	uint32_t u3Available : 3;
2364	/** 12: PAT bit for 1GB page. */
2365	uint32_t u1PAT : 1;
2366	/** 13-29: MBZ bits. */
2367	uint32_t u17Reserved : 17;
2368	/** 30-31: Physical page number - Low Part. Don't use! */
2369	uint32_t u2PageNoLow : 2;
2370	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
2371	uint32_t u20PageNoHigh : 20;
2372	/** 52-62: MBZ bits */
2373	uint32_t u11Reserved : 11;
2374	/** 63: No Execute flag. */
2375	uint32_t u1NoExecute : 1;
2376	} X86PDPE1GB;
2377	#ifndef VBOX_FOR_DTRACE_LIB
2378	AssertCompileSize(X86PDPE1GB, 8);
2379	#endif
2380	/** Pointer to a page directory pointer table entry for a 1GB page. */
2381	typedef X86PDPE1GB *PX86PDPE1GB;
2382	/** Pointer to a const page directory pointer table entry for a 1GB page. */
2383	typedef const X86PDPE1GB *PCX86PDPE1GB;
2384
2385	/**
2386	* Page directory pointer table entry.
2387	*/
2388	typedef union X86PDPE
2389	{
2390	/** Unsigned integer view. */
2391	X86PGPAEUINT u;
2392	/** Normal view. */
2393	X86PDPEBITS n;
2394	/** AMD64 view. */
2395	X86PDPEAMD64BITS lm;
2396	/** AMD64 big view. */
2397	X86PDPE1GB b;
2398	/** 8 bit unsigned integer view. */
2399	uint8_t au8[8];
2400	/** 16 bit unsigned integer view. */
2401	uint16_t au16[4];
2402	/** 32 bit unsigned integer view. */
2403	uint32_t au32[2];
2404	} X86PDPE;
2405	#ifndef VBOX_FOR_DTRACE_LIB
2406	AssertCompileSize(X86PDPE, 8);
2407	#endif
2408	/** Pointer to a page directory pointer table entry. */
2409	typedef X86PDPE *PX86PDPE;
2410	/** Pointer to a const page directory pointer table entry. */
2411	typedef const X86PDPE *PCX86PDPE;
2412
2413
2414	/**
2415	* Page directory pointer table.
2416	*/
2417	typedef struct X86PDPT
2418	{
2419	/** PDE Array. */
2420	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2421	} X86PDPT;
2422	#ifndef VBOX_FOR_DTRACE_LIB
2423	AssertCompileSize(X86PDPT, 4096);
2424	#endif
2425	/** Pointer to a page directory pointer table. */
2426	typedef X86PDPT *PX86PDPT;
2427	/** Pointer to a const page directory pointer table. */
2428	typedef const X86PDPT *PCX86PDPT;
2429
2430	/** The page shift to get the PDPT index. */
2431	#define X86_PDPT_SHIFT 30
2432	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2433	#define X86_PDPT_MASK_PAE 0x3
2434	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2435	#define X86_PDPT_MASK_AMD64 0x1ff
2436
2437	/** @} */
2438
2439
2440	/** @name Page Map Level-4 Entry (Long Mode PAE)
2441	* @{
2442	*/
2443	/** Bit 0 - P - Present bit. */
2444	#define X86_PML4E_P RT_BIT_32(0)
2445	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2446	#define X86_PML4E_RW RT_BIT_32(1)
2447	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2448	#define X86_PML4E_US RT_BIT_32(2)
2449	/** Bit 3 - PWT - Page level write thru bit. */
2450	#define X86_PML4E_PWT RT_BIT_32(3)
2451	/** Bit 4 - PCD - Page level cache disable bit. */
2452	#define X86_PML4E_PCD RT_BIT_32(4)
2453	/** Bit 5 - A - Access bit. */
2454	#define X86_PML4E_A RT_BIT_32(5)
2455	/** Bits 9-11 - - Available for use to system software. */
2456	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2457	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2458	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2459	/** Bits 8, 7 - - MBZ bits when NX is active. */
2460	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2461	/** Bits 63, 7 - - MBZ bits when no NX. */
2462	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2463	/** Bits 63 - NX - PAE - No execution flag. */
2464	#define X86_PML4E_NX RT_BIT_64(63)
2465
2466	/**
2467	* Page Map Level-4 Entry
2468	*/
2469	typedef struct X86PML4EBITS
2470	{
2471	/** Flags whether(=1) or not the page is present. */
2472	uint32_t u1Present : 1;
2473	/** Read(=0) / Write(=1) flag. */
2474	uint32_t u1Write : 1;
2475	/** User(=1) / Supervisor (=0) flag. */
2476	uint32_t u1User : 1;
2477	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2478	uint32_t u1WriteThru : 1;
2479	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2480	uint32_t u1CacheDisable : 1;
2481	/** Accessed flag.
2482	* Indicates that the page have been read or written to. */
2483	uint32_t u1Accessed : 1;
2484	/** Chunk of reserved bits. */
2485	uint32_t u3Reserved : 3;
2486	/** Available for use to system software. */
2487	uint32_t u3Available : 3;
2488	/** Physical Page number of the next level - Low Part. Don't use! */
2489	uint32_t u20PageNoLow : 20;
2490	/** Physical Page number of the next level - High Part. Don't use! */
2491	uint32_t u20PageNoHigh : 20;
2492	/** MBZ bits */
2493	uint32_t u11Reserved : 11;
2494	/** No Execute flag. */
2495	uint32_t u1NoExecute : 1;
2496	} X86PML4EBITS;
2497	#ifndef VBOX_FOR_DTRACE_LIB
2498	AssertCompileSize(X86PML4EBITS, 8);
2499	#endif
2500	/** Pointer to a page map level-4 entry. */
2501	typedef X86PML4EBITS *PX86PML4EBITS;
2502	/** Pointer to a const page map level-4 entry. */
2503	typedef const X86PML4EBITS *PCX86PML4EBITS;
2504
2505	/**
2506	* Page Map Level-4 Entry.
2507	*/
2508	typedef union X86PML4E
2509	{
2510	/** Unsigned integer view. */
2511	X86PGPAEUINT u;
2512	/** Normal view. */
2513	X86PML4EBITS n;
2514	/** 8 bit unsigned integer view. */
2515	uint8_t au8[8];
2516	/** 16 bit unsigned integer view. */
2517	uint16_t au16[4];
2518	/** 32 bit unsigned integer view. */
2519	uint32_t au32[2];
2520	} X86PML4E;
2521	#ifndef VBOX_FOR_DTRACE_LIB
2522	AssertCompileSize(X86PML4E, 8);
2523	#endif
2524	/** Pointer to a page map level-4 entry. */
2525	typedef X86PML4E *PX86PML4E;
2526	/** Pointer to a const page map level-4 entry. */
2527	typedef const X86PML4E *PCX86PML4E;
2528
2529
2530	/**
2531	* Page Map Level-4.
2532	*/
2533	typedef struct X86PML4
2534	{
2535	/** PDE Array. */
2536	X86PML4E a[X86_PG_PAE_ENTRIES];
2537	} X86PML4;
2538	#ifndef VBOX_FOR_DTRACE_LIB
2539	AssertCompileSize(X86PML4, 4096);
2540	#endif
2541	/** Pointer to a page map level-4. */
2542	typedef X86PML4 *PX86PML4;
2543	/** Pointer to a const page map level-4. */
2544	typedef const X86PML4 *PCX86PML4;
2545
2546	/** The page shift to get the PML4 index. */
2547	#define X86_PML4_SHIFT 39
2548	/** The PML4 index mask (apply to a shifted page address). */
2549	#define X86_PML4_MASK 0x1ff
2550
2551	/** @} */
2552
2553	/** @} */
2554
2555	/**
2556	* 32-bit protected mode FSTENV image.
2557	*/
2558	typedef struct X86FSTENV32P
2559	{
2560	uint16_t FCW;
2561	uint16_t padding1;
2562	uint16_t FSW;
2563	uint16_t padding2;
2564	uint16_t FTW;
2565	uint16_t padding3;
2566	uint32_t FPUIP;
2567	uint16_t FPUCS;
2568	uint16_t FOP;
2569	uint32_t FPUDP;
2570	uint16_t FPUDS;
2571	uint16_t padding4;
2572	} X86FSTENV32P;
2573	/** Pointer to a 32-bit protected mode FSTENV image. */
2574	typedef X86FSTENV32P *PX86FSTENV32P;
2575	/** Pointer to a const 32-bit protected mode FSTENV image. */
2576	typedef X86FSTENV32P const *PCX86FSTENV32P;
2577
2578
2579	/**
2580	* 80-bit MMX/FPU register type.
2581	*/
2582	typedef struct X86FPUMMX
2583	{
2584	uint8_t reg[10];
2585	} X86FPUMMX;
2586	#ifndef VBOX_FOR_DTRACE_LIB
2587	AssertCompileSize(X86FPUMMX, 10);
2588	#endif
2589	/** Pointer to a 80-bit MMX/FPU register type. */
2590	typedef X86FPUMMX *PX86FPUMMX;
2591	/** Pointer to a const 80-bit MMX/FPU register type. */
2592	typedef const X86FPUMMX *PCX86FPUMMX;
2593
2594	/** FPU (x87) register. */
2595	typedef union X86FPUREG
2596	{
2597	/** MMX view. */
2598	uint64_t mmx;
2599	/** FPU view - todo. */
2600	X86FPUMMX fpu;
2601	/** Extended precision floating point view. */
2602	RTFLOAT80U r80;
2603	/** Extended precision floating point view v2 */
2604	RTFLOAT80U2 r80Ex;
2605	/** 8-bit view. */
2606	uint8_t au8[16];
2607	/** 16-bit view. */
2608	uint16_t au16[8];
2609	/** 32-bit view. */
2610	uint32_t au32[4];
2611	/** 64-bit view. */
2612	uint64_t au64[2];
2613	/** 128-bit view. (yeah, very helpful) */
2614	uint128_t au128[1];
2615	} X86FPUREG;
2616	#ifndef VBOX_FOR_DTRACE_LIB
2617	AssertCompileSize(X86FPUREG, 16);
2618	#endif
2619	/** Pointer to a FPU register. */
2620	typedef X86FPUREG *PX86FPUREG;
2621	/** Pointer to a const FPU register. */
2622	typedef X86FPUREG const *PCX86FPUREG;
2623
2624	/**
2625	* XMM register union.
2626	*/
2627	typedef union X86XMMREG
2628	{
2629	/** XMM Register view. */
2630	uint128_t xmm;
2631	/** 8-bit view. */
2632	uint8_t au8[16];
2633	/** 16-bit view. */
2634	uint16_t au16[8];
2635	/** 32-bit view. */
2636	uint32_t au32[4];
2637	/** 64-bit view. */
2638	uint64_t au64[2];
2639	/** 128-bit view. (yeah, very helpful) */
2640	uint128_t au128[1];
2641	/** Confusing nested 128-bit union view (this is what xmm should've been). */
2642	RTUINT128U uXmm;
2643	} X86XMMREG;
2644	#ifndef VBOX_FOR_DTRACE_LIB
2645	AssertCompileSize(X86XMMREG, 16);
2646	#endif
2647	/** Pointer to an XMM register state. */
2648	typedef X86XMMREG *PX86XMMREG;
2649	/** Pointer to a const XMM register state. */
2650	typedef X86XMMREG const *PCX86XMMREG;
2651
2652	/**
2653	* YMM register union.
2654	*/
2655	typedef union X86YMMREG
2656	{
2657	/** 8-bit view. */
2658	uint8_t au8[32];
2659	/** 16-bit view. */
2660	uint16_t au16[16];
2661	/** 32-bit view. */
2662	uint32_t au32[8];
2663	/** 64-bit view. */
2664	uint64_t au64[4];
2665	/** 128-bit view. (yeah, very helpful) */
2666	uint128_t au128[2];
2667	/** XMM sub register view. */
2668	X86XMMREG aXmm[2];
2669	} X86YMMREG;
2670	#ifndef VBOX_FOR_DTRACE_LIB
2671	AssertCompileSize(X86YMMREG, 32);
2672	#endif
2673	/** Pointer to an YMM register state. */
2674	typedef X86YMMREG *PX86YMMREG;
2675	/** Pointer to a const YMM register state. */
2676	typedef X86YMMREG const *PCX86YMMREG;
2677
2678	/**
2679	* ZMM register union.
2680	*/
2681	typedef union X86ZMMREG
2682	{
2683	/** 8-bit view. */
2684	uint8_t au8[64];
2685	/** 16-bit view. */
2686	uint16_t au16[32];
2687	/** 32-bit view. */
2688	uint32_t au32[16];
2689	/** 64-bit view. */
2690	uint64_t au64[8];
2691	/** 128-bit view. (yeah, very helpful) */
2692	uint128_t au128[4];
2693	/** XMM sub register view. */
2694	X86XMMREG aXmm[4];
2695	/** YMM sub register view. */
2696	X86YMMREG aYmm[2];
2697	} X86ZMMREG;
2698	#ifndef VBOX_FOR_DTRACE_LIB
2699	AssertCompileSize(X86ZMMREG, 64);
2700	#endif
2701	/** Pointer to an ZMM register state. */
2702	typedef X86ZMMREG *PX86ZMMREG;
2703	/** Pointer to a const ZMM register state. */
2704	typedef X86ZMMREG const *PCX86ZMMREG;
2705
2706
2707	/**
2708	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2709	* @todo verify this...
2710	*/
2711	#pragma pack(1)
2712	typedef struct X86FPUSTATE
2713	{
2714	/** 0x00 - Control word. */
2715	uint16_t FCW;
2716	/** 0x02 - Alignment word */
2717	uint16_t Dummy1;
2718	/** 0x04 - Status word. */
2719	uint16_t FSW;
2720	/** 0x06 - Alignment word */
2721	uint16_t Dummy2;
2722	/** 0x08 - Tag word */
2723	uint16_t FTW;
2724	/** 0x0a - Alignment word */
2725	uint16_t Dummy3;
2726
2727	/** 0x0c - Instruction pointer. */
2728	uint32_t FPUIP;
2729	/** 0x10 - Code selector. */
2730	uint16_t CS;
2731	/** 0x12 - Opcode. */
2732	uint16_t FOP;
2733	/** 0x14 - FOO. */
2734	uint32_t FPUOO;
2735	/** 0x18 - FOS. */
2736	uint32_t FPUOS;
2737	/** 0x1c - FPU register. */
2738	X86FPUREG regs[8];
2739	} X86FPUSTATE;
2740	#pragma pack()
2741	/** Pointer to a FPU state. */
2742	typedef X86FPUSTATE *PX86FPUSTATE;
2743	/** Pointer to a const FPU state. */
2744	typedef const X86FPUSTATE *PCX86FPUSTATE;
2745
2746	/**
2747	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2748	*/
2749	#pragma pack(1)
2750	typedef struct X86FXSTATE
2751	{
2752	/** 0x00 - Control word. */
2753	uint16_t FCW;
2754	/** 0x02 - Status word. */
2755	uint16_t FSW;
2756	/** 0x04 - Tag word. (The upper byte is always zero.) */
2757	uint16_t FTW;
2758	/** 0x06 - Opcode. */
2759	uint16_t FOP;
2760	/** 0x08 - Instruction pointer. */
2761	uint32_t FPUIP;
2762	/** 0x0c - Code selector. */
2763	uint16_t CS;
2764	uint16_t Rsrvd1;
2765	/** 0x10 - Data pointer. */
2766	uint32_t FPUDP;
2767	/** 0x14 - Data segment */
2768	uint16_t DS;
2769	/** 0x16 */
2770	uint16_t Rsrvd2;
2771	/** 0x18 */
2772	uint32_t MXCSR;
2773	/** 0x1c */
2774	uint32_t MXCSR_MASK;
2775	/** 0x20 - FPU registers. */
2776	X86FPUREG aRegs[8];
2777	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
2778	X86XMMREG aXMM[16];
2779	/* - offset 416 - */
2780	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2781	/* - offset 464 - Software usable reserved bits. */
2782	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2783	} X86FXSTATE;
2784	#pragma pack()
2785	/** Pointer to a FPU Extended state. */
2786	typedef X86FXSTATE *PX86FXSTATE;
2787	/** Pointer to a const FPU Extended state. */
2788	typedef const X86FXSTATE *PCX86FXSTATE;
2789
2790	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2791	* magic. Don't forget to update x86.mac if you change this! */
2792	#define X86_OFF_FXSTATE_RSVD 0x1d0
2793	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2794	* forget to update x86.mac if you change this!
2795	* @todo r=bird: This has nothing what-so-ever to do here.... */
2796	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2797	#ifndef VBOX_FOR_DTRACE_LIB
2798	AssertCompileSize(X86FXSTATE, 512);
2799	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2800	#endif
2801
2802	/** @name FPU status word flags.
2803	* @{ */
2804	/** Exception Flag: Invalid operation. */
2805	#define X86_FSW_IE RT_BIT_32(0)
2806	/** Exception Flag: Denormalized operand. */
2807	#define X86_FSW_DE RT_BIT_32(1)
2808	/** Exception Flag: Zero divide. */
2809	#define X86_FSW_ZE RT_BIT_32(2)
2810	/** Exception Flag: Overflow. */
2811	#define X86_FSW_OE RT_BIT_32(3)
2812	/** Exception Flag: Underflow. */
2813	#define X86_FSW_UE RT_BIT_32(4)
2814	/** Exception Flag: Precision. */
2815	#define X86_FSW_PE RT_BIT_32(5)
2816	/** Stack fault. */
2817	#define X86_FSW_SF RT_BIT_32(6)
2818	/** Error summary status. */
2819	#define X86_FSW_ES RT_BIT_32(7)
2820	/** Mask of exceptions flags, excluding the summary bit. */
2821	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2822	/** Mask of exceptions flags, including the summary bit. */
2823	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2824	/** Condition code 0. */
2825	#define X86_FSW_C0 RT_BIT_32(8)
2826	/** Condition code 1. */
2827	#define X86_FSW_C1 RT_BIT_32(9)
2828	/** Condition code 2. */
2829	#define X86_FSW_C2 RT_BIT_32(10)
2830	/** Top of the stack mask. */
2831	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2832	/** TOP shift value. */
2833	#define X86_FSW_TOP_SHIFT 11
2834	/** Mask for getting TOP value after shifting it right. */
2835	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2836	/** Get the TOP value. */
2837	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2838	/** Condition code 3. */
2839	#define X86_FSW_C3 RT_BIT_32(14)
2840	/** Mask of exceptions flags, including the summary bit. */
2841	#define X86_FSW_C_MASK UINT16_C(0x4700)
2842	/** FPU busy. */
2843	#define X86_FSW_B RT_BIT_32(15)
2844	/** @} */
2845
2846
2847	/** @name FPU control word flags.
2848	* @{ */
2849	/** Exception Mask: Invalid operation. */
2850	#define X86_FCW_IM RT_BIT_32(0)
2851	/** Exception Mask: Denormalized operand. */
2852	#define X86_FCW_DM RT_BIT_32(1)
2853	/** Exception Mask: Zero divide. */
2854	#define X86_FCW_ZM RT_BIT_32(2)
2855	/** Exception Mask: Overflow. */
2856	#define X86_FCW_OM RT_BIT_32(3)
2857	/** Exception Mask: Underflow. */
2858	#define X86_FCW_UM RT_BIT_32(4)
2859	/** Exception Mask: Precision. */
2860	#define X86_FCW_PM RT_BIT_32(5)
2861	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2862	* @remarks This includes reserved bit 6. */
2863	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2864	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2865	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2866	/** Precision control mask. */
2867	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2868	/** Precision control: 24-bit. */
2869	#define X86_FCW_PC_24 UINT16_C(0x0000)
2870	/** Precision control: Reserved. */
2871	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2872	/** Precision control: 53-bit. */
2873	#define X86_FCW_PC_53 UINT16_C(0x0200)
2874	/** Precision control: 64-bit. */
2875	#define X86_FCW_PC_64 UINT16_C(0x0300)
2876	/** Rounding control mask. */
2877	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2878	/** Rounding control: To nearest. */
2879	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2880	/** Rounding control: Down. */
2881	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2882	/** Rounding control: Up. */
2883	#define X86_FCW_RC_UP UINT16_C(0x0800)
2884	/** Rounding control: Towards zero. */
2885	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2886	/** Bits which should be zero, apparently. */
2887	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2888	/** @} */
2889
2890	/** @name SSE MXCSR
2891	* @{ */
2892	/** Exception Flag: Invalid operation. */
2893	#define X86_MXCSR_IE RT_BIT_32(0)
2894	/** Exception Flag: Denormalized operand. */
2895	#define X86_MXCSR_DE RT_BIT_32(1)
2896	/** Exception Flag: Zero divide. */
2897	#define X86_MXCSR_ZE RT_BIT_32(2)
2898	/** Exception Flag: Overflow. */
2899	#define X86_MXCSR_OE RT_BIT_32(3)
2900	/** Exception Flag: Underflow. */
2901	#define X86_MXCSR_UE RT_BIT_32(4)
2902	/** Exception Flag: Precision. */
2903	#define X86_MXCSR_PE RT_BIT_32(5)
2904
2905	/** Denormals are zero. */
2906	#define X86_MXCSR_DAZ RT_BIT_32(6)
2907
2908	/** Exception Mask: Invalid operation. */
2909	#define X86_MXCSR_IM RT_BIT_32(7)
2910	/** Exception Mask: Denormalized operand. */
2911	#define X86_MXCSR_DM RT_BIT_32(8)
2912	/** Exception Mask: Zero divide. */
2913	#define X86_MXCSR_ZM RT_BIT_32(9)
2914	/** Exception Mask: Overflow. */
2915	#define X86_MXCSR_OM RT_BIT_32(10)
2916	/** Exception Mask: Underflow. */
2917	#define X86_MXCSR_UM RT_BIT_32(11)
2918	/** Exception Mask: Precision. */
2919	#define X86_MXCSR_PM RT_BIT_32(12)
2920
2921	/** Rounding control mask. */
2922	#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
2923	/** Rounding control: To nearest. */
2924	#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
2925	/** Rounding control: Down. */
2926	#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
2927	/** Rounding control: Up. */
2928	#define X86_MXCSR_RC_UP UINT16_C(0x4000)
2929	/** Rounding control: Towards zero. */
2930	#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
2931
2932	/** Flush-to-zero for masked underflow. */
2933	#define X86_MXCSR_FZ RT_BIT_32(15)
2934
2935	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
2936	#define X86_MXCSR_MM RT_BIT_32(17)
2937	/** @} */
2938
2939	/**
2940	* XSAVE header.
2941	*/
2942	typedef struct X86XSAVEHDR
2943	{
2944	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
2945	uint64_t bmXState;
2946	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
2947	uint64_t bmXComp;
2948	/** Reserved for furture extensions, probably MBZ. */
2949	uint64_t au64Reserved[6];
2950	} X86XSAVEHDR;
2951	#ifndef VBOX_FOR_DTRACE_LIB
2952	AssertCompileSize(X86XSAVEHDR, 64);
2953	#endif
2954	/** Pointer to an XSAVE header. */
2955	typedef X86XSAVEHDR *PX86XSAVEHDR;
2956	/** Pointer to a const XSAVE header. */
2957	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
2958
2959
2960	/**
2961	* The high 128-bit YMM register state (XSAVE_C_YMM).
2962	* (The lower 128-bits being in X86FXSTATE.)
2963	*/
2964	typedef struct X86XSAVEYMMHI
2965	{
2966	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
2967	X86XMMREG aYmmHi[16];
2968	} X86XSAVEYMMHI;
2969	#ifndef VBOX_FOR_DTRACE_LIB
2970	AssertCompileSize(X86XSAVEYMMHI, 256);
2971	#endif
2972	/** Pointer to a high 128-bit YMM register state. */
2973	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
2974	/** Pointer to a const high 128-bit YMM register state. */
2975	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
2976
2977	/**
2978	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
2979	*/
2980	typedef struct X86XSAVEBNDREGS
2981	{
2982	/** Array of registers (BND0...BND3). */
2983	struct
2984	{
2985	/** Lower bound. */
2986	uint64_t uLowerBound;
2987	/** Upper bound. */
2988	uint64_t uUpperBound;
2989	} aRegs[4];
2990	} X86XSAVEBNDREGS;
2991	#ifndef VBOX_FOR_DTRACE_LIB
2992	AssertCompileSize(X86XSAVEBNDREGS, 64);
2993	#endif
2994	/** Pointer to a MPX bound register state. */
2995	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
2996	/** Pointer to a const MPX bound register state. */
2997	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
2998
2999	/**
3000	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3001	*/
3002	typedef struct X86XSAVEBNDCFG
3003	{
3004	uint64_t fConfig;
3005	uint64_t fStatus;
3006	} X86XSAVEBNDCFG;
3007	#ifndef VBOX_FOR_DTRACE_LIB
3008	AssertCompileSize(X86XSAVEBNDCFG, 16);
3009	#endif
3010	/** Pointer to a MPX bound config and status register state. */
3011	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3012	/** Pointer to a const MPX bound config and status register state. */
3013	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3014
3015	/**
3016	* AVX-512 opmask state (XSAVE_C_OPMASK).
3017	*/
3018	typedef struct X86XSAVEOPMASK
3019	{
3020	/** The K0..K7 values. */
3021	uint64_t aKRegs[8];
3022	} X86XSAVEOPMASK;
3023	#ifndef VBOX_FOR_DTRACE_LIB
3024	AssertCompileSize(X86XSAVEOPMASK, 64);
3025	#endif
3026	/** Pointer to a AVX-512 opmask state. */
3027	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3028	/** Pointer to a const AVX-512 opmask state. */
3029	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3030
3031	/**
3032	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3033	*/
3034	typedef struct X86XSAVEZMMHI256
3035	{
3036	/** Upper 256-bits of ZMM0-15. */
3037	X86YMMREG aHi256Regs[16];
3038	} X86XSAVEZMMHI256;
3039	#ifndef VBOX_FOR_DTRACE_LIB
3040	AssertCompileSize(X86XSAVEZMMHI256, 512);
3041	#endif
3042	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3043	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3044	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3045	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3046
3047	/**
3048	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3049	*/
3050	typedef struct X86XSAVEZMM16HI
3051	{
3052	/** ZMM16 thru ZMM31. */
3053	X86ZMMREG aRegs[16];
3054	} X86XSAVEZMM16HI;
3055	#ifndef VBOX_FOR_DTRACE_LIB
3056	AssertCompileSize(X86XSAVEZMM16HI, 1024);
3057	#endif
3058	/** Pointer to a state comprising ZMM16-32. */
3059	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3060	/** Pointer to a const state comprising ZMM16-32. */
3061	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3062
3063	/**
3064	* AMD Light weight profiling state (XSAVE_C_LWP).
3065	*
3066	* We probably won't play with this as AMD seems to be dropping from their "zen"
3067	* processor micro architecture.
3068	*/
3069	typedef struct X86XSAVELWP
3070	{
3071	/** Details when needed. */
3072	uint64_t auLater[128/8];
3073	} X86XSAVELWP;
3074	#ifndef VBOX_FOR_DTRACE_LIB
3075	AssertCompileSize(X86XSAVELWP, 128);
3076	#endif
3077
3078
3079	/**
3080	* x86 FPU/SSE/AVX/XXXX state.
3081	*
3082	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3083	* changes to this structure.
3084	*/
3085	typedef struct X86XSAVEAREA
3086	{
3087	/** The x87 and SSE region (or legacy region if you like). */
3088	X86FXSTATE x87;
3089	/** The XSAVE header. */
3090	X86XSAVEHDR Hdr;
3091	/** Beyond the header, there isn't really a fixed layout, but we can
3092	generally assume the YMM (AVX) register extensions are present and
3093	follows immediately. */
3094	union
3095	{
3096	/** The high 128-bit AVX registers for easy access by IEM.
3097	* @note This ASSUMES they will always be here... */
3098	X86XSAVEYMMHI YmmHi;
3099
3100	/** This is a typical layout on intel CPUs (good for debuggers). */
3101	struct
3102	{
3103	X86XSAVEYMMHI YmmHi;
3104	X86XSAVEBNDREGS BndRegs;
3105	X86XSAVEBNDCFG BndCfg;
3106	uint8_t abFudgeToMatchDocs[0xB0];
3107	X86XSAVEOPMASK Opmask;
3108	X86XSAVEZMMHI256 ZmmHi256;
3109	X86XSAVEZMM16HI Zmm16Hi;
3110	} Intel;
3111
3112	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3113	struct
3114	{
3115	X86XSAVEYMMHI YmmHi;
3116	X86XSAVELWP Lwp;
3117	} AmdBd;
3118
3119	/** To enbling static deployments that have a reasonable chance of working for
3120	* the next 3-6 CPU generations without running short on space, we allocate a
3121	* lot of extra space here, making the structure a round 8KB in size. This
3122	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3123	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3124	uint8_t ab[8192 - 512 - 64];
3125	} u;
3126	} X86XSAVEAREA;
3127	#ifndef VBOX_FOR_DTRACE_LIB
3128	AssertCompileSize(X86XSAVEAREA, 8192);
3129	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
3130	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3131	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3132	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3133	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3134	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3135	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3136	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3137	#endif
3138	/** Pointer to a XSAVE area. */
3139	typedef X86XSAVEAREA *PX86XSAVEAREA;
3140	/** Pointer to a const XSAVE area. */
3141	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3142
3143
3144	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3145	* @{ */
3146	/** Bit 0 - x87 - Legacy FPU state (bit number) */
3147	#define XSAVE_C_X87_BIT 0
3148	/** Bit 0 - x87 - Legacy FPU state. */
3149	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3150	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3151	#define XSAVE_C_SSE_BIT 1
3152	/** Bit 1 - SSE - 128-bit SSE state. */
3153	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3154	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3155	#define XSAVE_C_YMM_BIT 2
3156	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3157	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3158	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3159	#define XSAVE_C_BNDREGS_BIT 3
3160	/** Bit 3 - BNDREGS - MPX bound register state. */
3161	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3162	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3163	#define XSAVE_C_BNDCSR_BIT 4
3164	/** Bit 4 - BNDCSR - MPX bound config and status state. */
3165	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3166	/** Bit 5 - Opmask - opmask state (bit number). */
3167	#define XSAVE_C_OPMASK_BIT 5
3168	/** Bit 5 - Opmask - opmask state. */
3169	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3170	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3171	#define XSAVE_C_ZMM_HI256_BIT 6
3172	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3173	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3174	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3175	#define XSAVE_C_ZMM_16HI_BIT 7
3176	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3177	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3178	/** Bit 9 - PKRU - Protection-key state (bit number). */
3179	#define XSAVE_C_PKRU_BIT 9
3180	/** Bit 9 - PKRU - Protection-key state. */
3181	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3182	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3183	#define XSAVE_C_LWP_BIT 62
3184	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3185	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3186	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3187	#define XSAVE_C_X_BIT 63
3188	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3189	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3190	/** @} */
3191
3192
3193
3194	/** @name Selector Descriptor
3195	* @{
3196	*/
3197
3198	#ifndef VBOX_FOR_DTRACE_LIB
3199	/**
3200	* Descriptor attributes (as seen by VT-x).
3201	*/
3202	typedef struct X86DESCATTRBITS
3203	{
3204	/** 00 - Segment Type. */
3205	unsigned u4Type : 4;
3206	/** 04 - Descriptor Type. System(=0) or code/data selector */
3207	unsigned u1DescType : 1;
3208	/** 05 - Descriptor Privilege level. */
3209	unsigned u2Dpl : 2;
3210	/** 07 - Flags selector present(=1) or not. */
3211	unsigned u1Present : 1;
3212	/** 08 - Segment limit 16-19. */
3213	unsigned u4LimitHigh : 4;
3214	/** 0c - Available for system software. */
3215	unsigned u1Available : 1;
3216	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3217	unsigned u1Long : 1;
3218	/** 0e - This flags meaning depends on the segment type. Try make sense out
3219	* of the intel manual yourself. */
3220	unsigned u1DefBig : 1;
3221	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
3222	* clear byte. */
3223	unsigned u1Granularity : 1;
3224	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3225	unsigned u1Unusable : 1;
3226	} X86DESCATTRBITS;
3227	#endif /* !VBOX_FOR_DTRACE_LIB */
3228
3229	/** @name X86DESCATTR masks
3230	* @{ */
3231	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3232	#define X86DESCATTR_DT UINT32_C(0x00000010)
3233	#define X86DESCATTR_DPL UINT32_C(0x00000060)
3234	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
3235	#define X86DESCATTR_P UINT32_C(0x00000080)
3236	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3237	#define X86DESCATTR_AVL UINT32_C(0x00001000)
3238	#define X86DESCATTR_L UINT32_C(0x00002000)
3239	#define X86DESCATTR_D UINT32_C(0x00004000)
3240	#define X86DESCATTR_G UINT32_C(0x00008000)
3241	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3242	/** @} */
3243
3244	#pragma pack(1)
3245	typedef union X86DESCATTR
3246	{
3247	/** Unsigned integer view. */
3248	uint32_t u;
3249	#ifndef VBOX_FOR_DTRACE_LIB
3250	/** Normal view. */
3251	X86DESCATTRBITS n;
3252	#endif
3253	} X86DESCATTR;
3254	#pragma pack()
3255	/** Pointer to descriptor attributes. */
3256	typedef X86DESCATTR *PX86DESCATTR;
3257	/** Pointer to const descriptor attributes. */
3258	typedef const X86DESCATTR *PCX86DESCATTR;
3259
3260	#ifndef VBOX_FOR_DTRACE_LIB
3261
3262	/**
3263	* Generic descriptor table entry
3264	*/
3265	#pragma pack(1)
3266	typedef struct X86DESCGENERIC
3267	{
3268	/** 00 - Limit - Low word. */
3269	unsigned u16LimitLow : 16;
3270	/** 10 - Base address - low word.
3271	* Don't try set this to 24 because MSC is doing stupid things then. */
3272	unsigned u16BaseLow : 16;
3273	/** 20 - Base address - first 8 bits of high word. */
3274	unsigned u8BaseHigh1 : 8;
3275	/** 28 - Segment Type. */
3276	unsigned u4Type : 4;
3277	/** 2c - Descriptor Type. System(=0) or code/data selector */
3278	unsigned u1DescType : 1;
3279	/** 2d - Descriptor Privilege level. */
3280	unsigned u2Dpl : 2;
3281	/** 2f - Flags selector present(=1) or not. */
3282	unsigned u1Present : 1;
3283	/** 30 - Segment limit 16-19. */
3284	unsigned u4LimitHigh : 4;
3285	/** 34 - Available for system software. */
3286	unsigned u1Available : 1;
3287	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3288	unsigned u1Long : 1;
3289	/** 36 - This flags meaning depends on the segment type. Try make sense out
3290	* of the intel manual yourself. */
3291	unsigned u1DefBig : 1;
3292	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
3293	* clear byte. */
3294	unsigned u1Granularity : 1;
3295	/** 38 - Base address - highest 8 bits. */
3296	unsigned u8BaseHigh2 : 8;
3297	} X86DESCGENERIC;
3298	#pragma pack()
3299	/** Pointer to a generic descriptor entry. */
3300	typedef X86DESCGENERIC *PX86DESCGENERIC;
3301	/** Pointer to a const generic descriptor entry. */
3302	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3303
3304	/** @name Bit offsets of X86DESCGENERIC members.
3305	* @{*/
3306	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
3307	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
3308	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
3309	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
3310	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
3311	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
3312	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
3313	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
3314	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
3315	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
3316	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
3317	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
3318	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
3319	/** @} */
3320
3321
3322	/** @name LAR mask
3323	* @{ */
3324	#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3325	#define X86LAR_F_DT UINT16_C( 0x1000)
3326	#define X86LAR_F_DPL UINT16_C( 0x6000)
3327	#define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
3328	#define X86LAR_F_P UINT16_C( 0x8000)
3329	#define X86LAR_F_AVL UINT32_C(0x00100000)
3330	#define X86LAR_F_L UINT32_C(0x00200000)
3331	#define X86LAR_F_D UINT32_C(0x00400000)
3332	#define X86LAR_F_G UINT32_C(0x00800000)
3333	/** @} */
3334
3335
3336	/**
3337	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3338	*/
3339	typedef struct X86DESCGATE
3340	{
3341	/** 00 - Target code segment offset - Low word.
3342	* Ignored if task-gate. */
3343	unsigned u16OffsetLow : 16;
3344	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3345	* TSS selector if task-gate. */
3346	unsigned u16Sel : 16;
3347	/** 20 - Number of parameters for a call-gate.
3348	* Ignored if interrupt-, trap- or task-gate. */
3349	unsigned u5ParmCount : 5;
3350	/** 25 - Reserved / ignored. */
3351	unsigned u3Reserved : 3;
3352	/** 28 - Segment Type. */
3353	unsigned u4Type : 4;
3354	/** 2c - Descriptor Type (0 = system). */
3355	unsigned u1DescType : 1;
3356	/** 2d - Descriptor Privilege level. */
3357	unsigned u2Dpl : 2;
3358	/** 2f - Flags selector present(=1) or not. */
3359	unsigned u1Present : 1;
3360	/** 30 - Target code segment offset - High word.
3361	* Ignored if task-gate. */
3362	unsigned u16OffsetHigh : 16;
3363	} X86DESCGATE;
3364	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3365	typedef X86DESCGATE *PX86DESCGATE;
3366	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3367	typedef const X86DESCGATE *PCX86DESCGATE;
3368
3369	#endif /* VBOX_FOR_DTRACE_LIB */
3370
3371	/**
3372	* Descriptor table entry.
3373	*/
3374	#pragma pack(1)
3375	typedef union X86DESC
3376	{
3377	#ifndef VBOX_FOR_DTRACE_LIB
3378	/** Generic descriptor view. */
3379	X86DESCGENERIC Gen;
3380	/** Gate descriptor view. */
3381	X86DESCGATE Gate;
3382	#endif
3383
3384	/** 8 bit unsigned integer view. */
3385	uint8_t au8[8];
3386	/** 16 bit unsigned integer view. */
3387	uint16_t au16[4];
3388	/** 32 bit unsigned integer view. */
3389	uint32_t au32[2];
3390	/** 64 bit unsigned integer view. */
3391	uint64_t au64[1];
3392	/** Unsigned integer view. */
3393	uint64_t u;
3394	} X86DESC;
3395	#ifndef VBOX_FOR_DTRACE_LIB
3396	AssertCompileSize(X86DESC, 8);
3397	#endif
3398	#pragma pack()
3399	/** Pointer to descriptor table entry. */
3400	typedef X86DESC *PX86DESC;
3401	/** Pointer to const descriptor table entry. */
3402	typedef const X86DESC *PCX86DESC;
3403
3404	/** @def X86DESC_BASE
3405	* Return the base address of a descriptor.
3406	*/
3407	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
3408	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3409	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3410	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3411
3412	/** @def X86DESC_LIMIT
3413	* Return the limit of a descriptor.
3414	*/
3415	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
3416	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3417	\| ( (a_pDesc)->Gen.u16LimitLow ) )
3418
3419	/** @def X86DESC_LIMIT_G
3420	* Return the limit of a descriptor with the granularity bit taken into account.
3421	* @returns Selector limit (uint32_t).
3422	* @param a_pDesc Pointer to the descriptor.
3423	*/
3424	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
3425	( (a_pDesc)->Gen.u1Granularity \
3426	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
3427	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
3428	)
3429
3430	/** @def X86DESC_GET_HID_ATTR
3431	* Get the descriptor attributes for the hidden register.
3432	*/
3433	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
3434	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3435
3436	#ifndef VBOX_FOR_DTRACE_LIB
3437
3438	/**
3439	* 64 bits generic descriptor table entry
3440	* Note: most of these bits have no meaning in long mode.
3441	*/
3442	#pragma pack(1)
3443	typedef struct X86DESC64GENERIC
3444	{
3445	/** Limit - Low word - IGNORED. */
3446	uint32_t u16LimitLow : 16;
3447	/** Base address - low word. - IGNORED
3448	* Don't try set this to 24 because MSC is doing stupid things then. */
3449	uint32_t u16BaseLow : 16;
3450	/** Base address - first 8 bits of high word. - IGNORED */
3451	uint32_t u8BaseHigh1 : 8;
3452	/** Segment Type. */
3453	uint32_t u4Type : 4;
3454	/** Descriptor Type. System(=0) or code/data selector */
3455	uint32_t u1DescType : 1;
3456	/** Descriptor Privilege level. */
3457	uint32_t u2Dpl : 2;
3458	/** Flags selector present(=1) or not. */
3459	uint32_t u1Present : 1;
3460	/** Segment limit 16-19. - IGNORED */
3461	uint32_t u4LimitHigh : 4;
3462	/** Available for system software. - IGNORED */
3463	uint32_t u1Available : 1;
3464	/** Long mode flag. */
3465	uint32_t u1Long : 1;
3466	/** This flags meaning depends on the segment type. Try make sense out
3467	* of the intel manual yourself. */
3468	uint32_t u1DefBig : 1;
3469	/** Granularity of the limit. If set 4KB granularity is used, if
3470	* clear byte. - IGNORED */
3471	uint32_t u1Granularity : 1;
3472	/** Base address - highest 8 bits. - IGNORED */
3473	uint32_t u8BaseHigh2 : 8;
3474	/** Base address - bits 63-32. */
3475	uint32_t u32BaseHigh3 : 32;
3476	uint32_t u8Reserved : 8;
3477	uint32_t u5Zeros : 5;
3478	uint32_t u19Reserved : 19;
3479	} X86DESC64GENERIC;
3480	#pragma pack()
3481	/** Pointer to a generic descriptor entry. */
3482	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3483	/** Pointer to a const generic descriptor entry. */
3484	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3485
3486	/**
3487	* System descriptor table entry (64 bits)
3488	*
3489	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3490	*/
3491	#pragma pack(1)
3492	typedef struct X86DESC64SYSTEM
3493	{
3494	/** Limit - Low word. */
3495	uint32_t u16LimitLow : 16;
3496	/** Base address - low word.
3497	* Don't try set this to 24 because MSC is doing stupid things then. */
3498	uint32_t u16BaseLow : 16;
3499	/** Base address - first 8 bits of high word. */
3500	uint32_t u8BaseHigh1 : 8;
3501	/** Segment Type. */
3502	uint32_t u4Type : 4;
3503	/** Descriptor Type. System(=0) or code/data selector */
3504	uint32_t u1DescType : 1;
3505	/** Descriptor Privilege level. */
3506	uint32_t u2Dpl : 2;
3507	/** Flags selector present(=1) or not. */
3508	uint32_t u1Present : 1;
3509	/** Segment limit 16-19. */
3510	uint32_t u4LimitHigh : 4;
3511	/** Available for system software. */
3512	uint32_t u1Available : 1;
3513	/** Reserved - 0. */
3514	uint32_t u1Reserved : 1;
3515	/** This flags meaning depends on the segment type. Try make sense out
3516	* of the intel manual yourself. */
3517	uint32_t u1DefBig : 1;
3518	/** Granularity of the limit. If set 4KB granularity is used, if
3519	* clear byte. */
3520	uint32_t u1Granularity : 1;
3521	/** Base address - bits 31-24. */
3522	uint32_t u8BaseHigh2 : 8;
3523	/** Base address - bits 63-32. */
3524	uint32_t u32BaseHigh3 : 32;
3525	uint32_t u8Reserved : 8;
3526	uint32_t u5Zeros : 5;
3527	uint32_t u19Reserved : 19;
3528	} X86DESC64SYSTEM;
3529	#pragma pack()
3530	/** Pointer to a system descriptor entry. */
3531	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3532	/** Pointer to a const system descriptor entry. */
3533	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3534
3535	/**
3536	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3537	*/
3538	typedef struct X86DESC64GATE
3539	{
3540	/** Target code segment offset - Low word. */
3541	uint32_t u16OffsetLow : 16;
3542	/** Target code segment selector. */
3543	uint32_t u16Sel : 16;
3544	/** Interrupt stack table for interrupt- and trap-gates.
3545	* Ignored by call-gates. */
3546	uint32_t u3IST : 3;
3547	/** Reserved / ignored. */
3548	uint32_t u5Reserved : 5;
3549	/** Segment Type. */
3550	uint32_t u4Type : 4;
3551	/** Descriptor Type (0 = system). */
3552	uint32_t u1DescType : 1;
3553	/** Descriptor Privilege level. */
3554	uint32_t u2Dpl : 2;
3555	/** Flags selector present(=1) or not. */
3556	uint32_t u1Present : 1;
3557	/** Target code segment offset - High word.
3558	* Ignored if task-gate. */
3559	uint32_t u16OffsetHigh : 16;
3560	/** Target code segment offset - Top dword.
3561	* Ignored if task-gate. */
3562	uint32_t u32OffsetTop : 32;
3563	/** Reserved / ignored / must be zero.
3564	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3565	uint32_t u32Reserved : 32;
3566	} X86DESC64GATE;
3567	AssertCompileSize(X86DESC64GATE, 16);
3568	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3569	typedef X86DESC64GATE *PX86DESC64GATE;
3570	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3571	typedef const X86DESC64GATE *PCX86DESC64GATE;
3572
3573	#endif /* VBOX_FOR_DTRACE_LIB */
3574
3575	/**
3576	* Descriptor table entry.
3577	*/
3578	#pragma pack(1)
3579	typedef union X86DESC64
3580	{
3581	#ifndef VBOX_FOR_DTRACE_LIB
3582	/** Generic descriptor view. */
3583	X86DESC64GENERIC Gen;
3584	/** System descriptor view. */
3585	X86DESC64SYSTEM System;
3586	/** Gate descriptor view. */
3587	X86DESC64GATE Gate;
3588	#endif
3589
3590	/** 8 bit unsigned integer view. */
3591	uint8_t au8[16];
3592	/** 16 bit unsigned integer view. */
3593	uint16_t au16[8];
3594	/** 32 bit unsigned integer view. */
3595	uint32_t au32[4];
3596	/** 64 bit unsigned integer view. */
3597	uint64_t au64[2];
3598	} X86DESC64;
3599	#ifndef VBOX_FOR_DTRACE_LIB
3600	AssertCompileSize(X86DESC64, 16);
3601	#endif
3602	#pragma pack()
3603	/** Pointer to descriptor table entry. */
3604	typedef X86DESC64 *PX86DESC64;
3605	/** Pointer to const descriptor table entry. */
3606	typedef const X86DESC64 *PCX86DESC64;
3607
3608	/** @def X86DESC64_BASE
3609	* Return the base of a 64-bit descriptor.
3610	*/
3611	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
3612	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3613	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3614	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3615	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3616
3617
3618
3619	/** @name Host system descriptor table entry - Use with care!
3620	* @{ */
3621	/** Host system descriptor table entry. */
3622	#if HC_ARCH_BITS == 64
3623	typedef X86DESC64 X86DESCHC;
3624	#else
3625	typedef X86DESC X86DESCHC;
3626	#endif
3627	/** Pointer to a host system descriptor table entry. */
3628	#if HC_ARCH_BITS == 64
3629	typedef PX86DESC64 PX86DESCHC;
3630	#else
3631	typedef PX86DESC PX86DESCHC;
3632	#endif
3633	/** Pointer to a const host system descriptor table entry. */
3634	#if HC_ARCH_BITS == 64
3635	typedef PCX86DESC64 PCX86DESCHC;
3636	#else
3637	typedef PCX86DESC PCX86DESCHC;
3638	#endif
3639	/** @} */
3640
3641
3642	/** @name Selector Descriptor Types.
3643	* @{
3644	*/
3645
3646	/** @name Non-System Selector Types.
3647	* @{ */
3648	/** Code(=set)/Data(=clear) bit. */
3649	#define X86_SEL_TYPE_CODE 8
3650	/** Memory(=set)/System(=clear) bit. */
3651	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3652	/** Accessed bit. */
3653	#define X86_SEL_TYPE_ACCESSED 1
3654	/** Expand down bit (for data selectors only). */
3655	#define X86_SEL_TYPE_DOWN 4
3656	/** Conforming bit (for code selectors only). */
3657	#define X86_SEL_TYPE_CONF 4
3658	/** Write bit (for data selectors only). */
3659	#define X86_SEL_TYPE_WRITE 2
3660	/** Read bit (for code selectors only). */
3661	#define X86_SEL_TYPE_READ 2
3662	/** The bit number of the code segment read bit (relative to u4Type). */
3663	#define X86_SEL_TYPE_READ_BIT 1
3664
3665	/** Read only selector type. */
3666	#define X86_SEL_TYPE_RO 0
3667	/** Accessed read only selector type. */
3668	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
3669	/** Read write selector type. */
3670	#define X86_SEL_TYPE_RW 2
3671	/** Accessed read write selector type. */
3672	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
3673	/** Expand down read only selector type. */
3674	#define X86_SEL_TYPE_RO_DOWN 4
3675	/** Accessed expand down read only selector type. */
3676	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
3677	/** Expand down read write selector type. */
3678	#define X86_SEL_TYPE_RW_DOWN 6
3679	/** Accessed expand down read write selector type. */
3680	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
3681	/** Execute only selector type. */
3682	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
3683	/** Accessed execute only selector type. */
3684	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3685	/** Execute and read selector type. */
3686	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
3687	/** Accessed execute and read selector type. */
3688	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3689	/** Conforming execute only selector type. */
3690	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
3691	/** Accessed Conforming execute only selector type. */
3692	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3693	/** Conforming execute and write selector type. */
3694	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
3695	/** Accessed Conforming execute and write selector type. */
3696	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3697	/** @} */
3698
3699
3700	/** @name System Selector Types.
3701	* @{ */
3702	/** The TSS busy bit mask. */
3703	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3704
3705	/** Undefined system selector type. */
3706	#define X86_SEL_TYPE_SYS_UNDEFINED 0
3707	/** 286 TSS selector. */
3708	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3709	/** LDT selector. */
3710	#define X86_SEL_TYPE_SYS_LDT 2
3711	/** 286 TSS selector - Busy. */
3712	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3713	/** 286 Callgate selector. */
3714	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3715	/** Taskgate selector. */
3716	#define X86_SEL_TYPE_SYS_TASK_GATE 5
3717	/** 286 Interrupt gate selector. */
3718	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3719	/** 286 Trapgate selector. */
3720	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3721	/** Undefined system selector. */
3722	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3723	/** 386 TSS selector. */
3724	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3725	/** Undefined system selector. */
3726	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3727	/** 386 TSS selector - Busy. */
3728	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3729	/** 386 Callgate selector. */
3730	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3731	/** Undefined system selector. */
3732	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3733	/** 386 Interruptgate selector. */
3734	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3735	/** 386 Trapgate selector. */
3736	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3737	/** @} */
3738
3739	/** @name AMD64 System Selector Types.
3740	* @{ */
3741	/** LDT selector. */
3742	#define AMD64_SEL_TYPE_SYS_LDT 2
3743	/** TSS selector - Busy. */
3744	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3745	/** TSS selector - Busy. */
3746	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3747	/** Callgate selector. */
3748	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3749	/** Interruptgate selector. */
3750	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3751	/** Trapgate selector. */
3752	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3753	/** @} */
3754
3755	/** @} */
3756
3757
3758	/** @name Descriptor Table Entry Flag Masks.
3759	* These are for the 2nd 32-bit word of a descriptor.
3760	* @{ */
3761	/** Bits 8-11 - TYPE - Descriptor type mask. */
3762	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3763	/** Bit 12 - S - System (=0) or Code/Data (=1). */
3764	#define X86_DESC_S RT_BIT_32(12)
3765	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3766	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
3767	/** Bit 15 - P - Present. */
3768	#define X86_DESC_P RT_BIT_32(15)
3769	/** Bit 20 - AVL - Available for system software. */
3770	#define X86_DESC_AVL RT_BIT_32(20)
3771	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3772	#define X86_DESC_DB RT_BIT_32(22)
3773	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3774	* used, if clear byte. */
3775	#define X86_DESC_G RT_BIT_32(23)
3776	/** @} */
3777
3778	/** @} */
3779
3780
3781	/** @name Task Segments.
3782	* @{
3783	*/
3784
3785	/**
3786	* The minimum TSS descriptor limit for 286 tasks.
3787	*/
3788	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3789
3790	/**
3791	* The minimum TSS descriptor segment limit for 386 tasks.
3792	*/
3793	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3794
3795	/**
3796	* 16-bit Task Segment (TSS).
3797	*/
3798	#pragma pack(1)
3799	typedef struct X86TSS16
3800	{
3801	/** Back link to previous task. (static) */
3802	RTSEL selPrev;
3803	/** Ring-0 stack pointer. (static) */
3804	uint16_t sp0;
3805	/** Ring-0 stack segment. (static) */
3806	RTSEL ss0;
3807	/** Ring-1 stack pointer. (static) */
3808	uint16_t sp1;
3809	/** Ring-1 stack segment. (static) */
3810	RTSEL ss1;
3811	/** Ring-2 stack pointer. (static) */
3812	uint16_t sp2;
3813	/** Ring-2 stack segment. (static) */
3814	RTSEL ss2;
3815	/** IP before task switch. */
3816	uint16_t ip;
3817	/** FLAGS before task switch. */
3818	uint16_t flags;
3819	/** AX before task switch. */
3820	uint16_t ax;
3821	/** CX before task switch. */
3822	uint16_t cx;
3823	/** DX before task switch. */
3824	uint16_t dx;
3825	/** BX before task switch. */
3826	uint16_t bx;
3827	/** SP before task switch. */
3828	uint16_t sp;
3829	/** BP before task switch. */
3830	uint16_t bp;
3831	/** SI before task switch. */
3832	uint16_t si;
3833	/** DI before task switch. */
3834	uint16_t di;
3835	/** ES before task switch. */
3836	RTSEL es;
3837	/** CS before task switch. */
3838	RTSEL cs;
3839	/** SS before task switch. */
3840	RTSEL ss;
3841	/** DS before task switch. */
3842	RTSEL ds;
3843	/** LDTR before task switch. */
3844	RTSEL selLdt;
3845	} X86TSS16;
3846	#ifndef VBOX_FOR_DTRACE_LIB
3847	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
3848	#endif
3849	#pragma pack()
3850	/** Pointer to a 16-bit task segment. */
3851	typedef X86TSS16 *PX86TSS16;
3852	/** Pointer to a const 16-bit task segment. */
3853	typedef const X86TSS16 *PCX86TSS16;
3854
3855
3856	/**
3857	* 32-bit Task Segment (TSS).
3858	*/
3859	#pragma pack(1)
3860	typedef struct X86TSS32
3861	{
3862	/** Back link to previous task. (static) */
3863	RTSEL selPrev;
3864	uint16_t padding1;
3865	/** Ring-0 stack pointer. (static) */
3866	uint32_t esp0;
3867	/** Ring-0 stack segment. (static) */
3868	RTSEL ss0;
3869	uint16_t padding_ss0;
3870	/** Ring-1 stack pointer. (static) */
3871	uint32_t esp1;
3872	/** Ring-1 stack segment. (static) */
3873	RTSEL ss1;
3874	uint16_t padding_ss1;
3875	/** Ring-2 stack pointer. (static) */
3876	uint32_t esp2;
3877	/** Ring-2 stack segment. (static) */
3878	RTSEL ss2;
3879	uint16_t padding_ss2;
3880	/** Page directory for the task. (static) */
3881	uint32_t cr3;
3882	/** EIP before task switch. */
3883	uint32_t eip;
3884	/** EFLAGS before task switch. */
3885	uint32_t eflags;
3886	/** EAX before task switch. */
3887	uint32_t eax;
3888	/** ECX before task switch. */
3889	uint32_t ecx;
3890	/** EDX before task switch. */
3891	uint32_t edx;
3892	/** EBX before task switch. */
3893	uint32_t ebx;
3894	/** ESP before task switch. */
3895	uint32_t esp;
3896	/** EBP before task switch. */
3897	uint32_t ebp;
3898	/** ESI before task switch. */
3899	uint32_t esi;
3900	/** EDI before task switch. */
3901	uint32_t edi;
3902	/** ES before task switch. */
3903	RTSEL es;
3904	uint16_t padding_es;
3905	/** CS before task switch. */
3906	RTSEL cs;
3907	uint16_t padding_cs;
3908	/** SS before task switch. */
3909	RTSEL ss;
3910	uint16_t padding_ss;
3911	/** DS before task switch. */
3912	RTSEL ds;
3913	uint16_t padding_ds;
3914	/** FS before task switch. */
3915	RTSEL fs;
3916	uint16_t padding_fs;
3917	/** GS before task switch. */
3918	RTSEL gs;
3919	uint16_t padding_gs;
3920	/** LDTR before task switch. */
3921	RTSEL selLdt;
3922	uint16_t padding_ldt;
3923	/** Debug trap flag */
3924	uint16_t fDebugTrap;
3925	/** Offset relative to the TSS of the start of the I/O Bitmap
3926	* and the end of the interrupt redirection bitmap. */
3927	uint16_t offIoBitmap;
3928	} X86TSS32;
3929	#pragma pack()
3930	/** Pointer to task segment. */
3931	typedef X86TSS32 *PX86TSS32;
3932	/** Pointer to const task segment. */
3933	typedef const X86TSS32 *PCX86TSS32;
3934	#ifndef VBOX_FOR_DTRACE_LIB
3935	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
3936	AssertCompileMemberOffset(X86TSS32, cr3, 28);
3937	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
3938	#endif
3939
3940	/**
3941	* 64-bit Task segment.
3942	*/
3943	#pragma pack(1)
3944	typedef struct X86TSS64
3945	{
3946	/** Reserved. */
3947	uint32_t u32Reserved;
3948	/** Ring-0 stack pointer. (static) */
3949	uint64_t rsp0;
3950	/** Ring-1 stack pointer. (static) */
3951	uint64_t rsp1;
3952	/** Ring-2 stack pointer. (static) */
3953	uint64_t rsp2;
3954	/** Reserved. */
3955	uint32_t u32Reserved2[2];
3956	/* IST */
3957	uint64_t ist1;
3958	uint64_t ist2;
3959	uint64_t ist3;
3960	uint64_t ist4;
3961	uint64_t ist5;
3962	uint64_t ist6;
3963	uint64_t ist7;
3964	/* Reserved. */
3965	uint16_t u16Reserved[5];
3966	/** Offset relative to the TSS of the start of the I/O Bitmap
3967	* and the end of the interrupt redirection bitmap. */
3968	uint16_t offIoBitmap;
3969	} X86TSS64;
3970	#pragma pack()
3971	/** Pointer to a 64-bit task segment. */
3972	typedef X86TSS64 *PX86TSS64;
3973	/** Pointer to a const 64-bit task segment. */
3974	typedef const X86TSS64 *PCX86TSS64;
3975	#ifndef VBOX_FOR_DTRACE_LIB
3976	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
3977	#endif
3978
3979	/** @} */
3980
3981
3982	/** @name Selectors.
3983	* @{
3984	*/
3985
3986	/**
3987	* The shift used to convert a selector from and to index an index (C).
3988	*/
3989	#define X86_SEL_SHIFT 3
3990
3991	/**
3992	* The mask used to mask off the table indicator and RPL of an selector.
3993	*/
3994	#define X86_SEL_MASK 0xfff8U
3995
3996	/**
3997	* The mask used to mask off the RPL of an selector.
3998	* This is suitable for checking for NULL selectors.
3999	*/
4000	#define X86_SEL_MASK_OFF_RPL 0xfffcU
4001
4002	/**
4003	* The bit indicating that a selector is in the LDT and not in the GDT.
4004	*/
4005	#define X86_SEL_LDT 0x0004U
4006
4007	/**
4008	* The bit mask for getting the RPL of a selector.
4009	*/
4010	#define X86_SEL_RPL 0x0003U
4011
4012	/**
4013	* The mask covering both RPL and LDT.
4014	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4015	* checks.
4016	*/
4017	#define X86_SEL_RPL_LDT 0x0007U
4018
4019	/** @} */
4020
4021
4022	/**
4023	* x86 Exceptions/Faults/Traps.
4024	*/
4025	typedef enum X86XCPT
4026	{
4027	/** \#DE - Divide error. */
4028	X86_XCPT_DE = 0x00,
4029	/** \#DB - Debug event (single step, DRx, ..) */
4030	X86_XCPT_DB = 0x01,
4031	/** NMI - Non-Maskable Interrupt */
4032	X86_XCPT_NMI = 0x02,
4033	/** \#BP - Breakpoint (INT3). */
4034	X86_XCPT_BP = 0x03,
4035	/** \#OF - Overflow (INTO). */
4036	X86_XCPT_OF = 0x04,
4037	/** \#BR - Bound range exceeded (BOUND). */
4038	X86_XCPT_BR = 0x05,
4039	/** \#UD - Undefined opcode. */
4040	X86_XCPT_UD = 0x06,
4041	/** \#NM - Device not available (math coprocessor device). */
4042	X86_XCPT_NM = 0x07,
4043	/** \#DF - Double fault. */
4044	X86_XCPT_DF = 0x08,
4045	/** ??? - Coprocessor segment overrun (obsolete). */
4046	X86_XCPT_CO_SEG_OVERRUN = 0x09,
4047	/** \#TS - Taskswitch (TSS). */
4048	X86_XCPT_TS = 0x0a,
4049	/** \#NP - Segment no present. */
4050	X86_XCPT_NP = 0x0b,
4051	/** \#SS - Stack segment fault. */
4052	X86_XCPT_SS = 0x0c,
4053	/** \#GP - General protection fault. */
4054	X86_XCPT_GP = 0x0d,
4055	/** \#PF - Page fault. */
4056	X86_XCPT_PF = 0x0e,
4057	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4058	/** \#MF - Math fault (FPU). */
4059	X86_XCPT_MF = 0x10,
4060	/** \#AC - Alignment check. */
4061	X86_XCPT_AC = 0x11,
4062	/** \#MC - Machine check. */
4063	X86_XCPT_MC = 0x12,
4064	/** \#XF - SIMD Floating-Pointer Exception. */
4065	X86_XCPT_XF = 0x13,
4066	/** \#VE - Virtualization Exception. */
4067	X86_XCPT_VE = 0x14,
4068	/** \#SX - Security Exception. */
4069	X86_XCPT_SX = 0x1e
4070	} X86XCPT;
4071	/** Pointer to a x86 exception code. */
4072	typedef X86XCPT *PX86XCPT;
4073	/** Pointer to a const x86 exception code. */
4074	typedef const X86XCPT *PCX86XCPT;
4075	/** The last valid (currently reserved) exception value. */
4076	#define X86_XCPT_LAST 0x1f
4077
4078
4079	/** @name Trap Error Codes
4080	* @{
4081	*/
4082	/** External indicator. */
4083	#define X86_TRAP_ERR_EXTERNAL 1
4084	/** IDT indicator. */
4085	#define X86_TRAP_ERR_IDT 2
4086	/** Descriptor table indicator - If set LDT, if clear GDT. */
4087	#define X86_TRAP_ERR_TI 4
4088	/** Mask for getting the selector. */
4089	#define X86_TRAP_ERR_SEL_MASK 0xfff8
4090	/** Shift for getting the selector table index (C type index). */
4091	#define X86_TRAP_ERR_SEL_SHIFT 3
4092	/** @} */
4093
4094
4095	/** @name \#PF Trap Error Codes
4096	* @{
4097	*/
4098	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4099	#define X86_TRAP_PF_P RT_BIT_32(0)
4100	/** Bit 1 - R/W - Read (clear) or write (set) access. */
4101	#define X86_TRAP_PF_RW RT_BIT_32(1)
4102	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4103	#define X86_TRAP_PF_US RT_BIT_32(2)
4104	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4105	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4106	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4107	#define X86_TRAP_PF_ID RT_BIT_32(4)
4108	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4109	#define X86_TRAP_PF_PK RT_BIT_32(5)
4110	/** @} */
4111
4112	#pragma pack(1)
4113	/**
4114	* 16-bit IDTR.
4115	*/
4116	typedef struct X86IDTR16
4117	{
4118	/** Offset. */
4119	uint16_t offSel;
4120	/** Selector. */
4121	uint16_t uSel;
4122	} X86IDTR16, *PX86IDTR16;
4123	#pragma pack()
4124
4125	#pragma pack(1)
4126	/**
4127	* 32-bit IDTR/GDTR.
4128	*/
4129	typedef struct X86XDTR32
4130	{
4131	/** Size of the descriptor table. */
4132	uint16_t cb;
4133	/** Address of the descriptor table. */
4134	#ifndef VBOX_FOR_DTRACE_LIB
4135	uint32_t uAddr;
4136	#else
4137	uint16_t au16Addr[2];
4138	#endif
4139	} X86XDTR32, *PX86XDTR32;
4140	#pragma pack()
4141
4142	#pragma pack(1)
4143	/**
4144	* 64-bit IDTR/GDTR.
4145	*/
4146	typedef struct X86XDTR64
4147	{
4148	/** Size of the descriptor table. */
4149	uint16_t cb;
4150	/** Address of the descriptor table. */
4151	#ifndef VBOX_FOR_DTRACE_LIB
4152	uint64_t uAddr;
4153	#else
4154	uint16_t au16Addr[4];
4155	#endif
4156	} X86XDTR64, *PX86XDTR64;
4157	#pragma pack()
4158
4159
4160	/** @name ModR/M
4161	* @{ */
4162	#define X86_MODRM_RM_MASK UINT8_C(0x07)
4163	#define X86_MODRM_REG_MASK UINT8_C(0x38)
4164	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4165	#define X86_MODRM_REG_SHIFT 3
4166	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4167	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4168	#define X86_MODRM_MOD_SHIFT 6
4169	#ifndef VBOX_FOR_DTRACE_LIB
4170	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
4171	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4172	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4173	/** @def X86_MODRM_MAKE
4174	* @param a_Mod The mod value (0..3).
4175	* @param a_Reg The register value (0..7).
4176	* @param a_RegMem The register or memory value (0..7). */
4177	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
4178	#endif
4179	/** @} */
4180
4181	/** @name SIB
4182	* @{ */
4183	#define X86_SIB_BASE_MASK UINT8_C(0x07)
4184	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4185	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4186	#define X86_SIB_INDEX_SHIFT 3
4187	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4188	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4189	#define X86_SIB_SCALE_SHIFT 6
4190	#ifndef VBOX_FOR_DTRACE_LIB
4191	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
4192	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4193	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4194	#endif
4195	/** @} */
4196
4197	/** @name General register indexes
4198	* @{ */
4199	#define X86_GREG_xAX 0
4200	#define X86_GREG_xCX 1
4201	#define X86_GREG_xDX 2
4202	#define X86_GREG_xBX 3
4203	#define X86_GREG_xSP 4
4204	#define X86_GREG_xBP 5
4205	#define X86_GREG_xSI 6
4206	#define X86_GREG_xDI 7
4207	#define X86_GREG_x8 8
4208	#define X86_GREG_x9 9
4209	#define X86_GREG_x10 10
4210	#define X86_GREG_x11 11
4211	#define X86_GREG_x12 12
4212	#define X86_GREG_x13 13
4213	#define X86_GREG_x14 14
4214	#define X86_GREG_x15 15
4215	/** @} */
4216
4217	/** @name X86_SREG_XXX - Segment register indexes.
4218	* @{ */
4219	#define X86_SREG_ES 0
4220	#define X86_SREG_CS 1
4221	#define X86_SREG_SS 2
4222	#define X86_SREG_DS 3
4223	#define X86_SREG_FS 4
4224	#define X86_SREG_GS 5
4225	/** @} */
4226	/** Segment register count. */
4227	#define X86_SREG_COUNT 6
4228
4229
4230	/** @name X86_OP_XXX - Prefixes
4231	* @{ */
4232	#define X86_OP_PRF_CS UINT8_C(0x2e)
4233	#define X86_OP_PRF_SS UINT8_C(0x36)
4234	#define X86_OP_PRF_DS UINT8_C(0x3e)
4235	#define X86_OP_PRF_ES UINT8_C(0x26)
4236	#define X86_OP_PRF_FS UINT8_C(0x64)
4237	#define X86_OP_PRF_GS UINT8_C(0x65)
4238	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4239	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4240	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4241	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4242	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4243	#define X86_OP_REX_B UINT8_C(0x41)
4244	#define X86_OP_REX_X UINT8_C(0x42)
4245	#define X86_OP_REX_R UINT8_C(0x44)
4246	#define X86_OP_REX_W UINT8_C(0x48)
4247	/** @} */
4248
4249
4250	/** @} */
4251
4252	#endif
4253

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source: vbox/trunk/include/iprt/x86.h@ 70286

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