x86.h@ 59961

Last change on this file since 59961 was 59961, checked in by vboxsync, 9 years ago
iprt/x86.h: RT_BIT -> RT_BIT_32 (for 16-bit compilers).
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 147.6 KB

Line
1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2015 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	#ifndef VBOX_FOR_DTRACE_LIB
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104	#endif /* !VBOX_FOR_DTRACE_LIB */
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	#ifndef VBOX_FOR_DTRACE_LIB
114	/** The bitfield view. */
115	X86EFLAGSBITS Bits;
116	#endif
117	/** The 8-bit view. */
118	uint8_t au8[4];
119	/** The 16-bit view. */
120	uint16_t au16[2];
121	/** The 32-bit view. */
122	uint32_t au32[1];
123	/** The 32-bit view. */
124	uint32_t u32;
125	} X86EFLAGS;
126	/** Pointer to EFLAGS. */
127	typedef X86EFLAGS *PX86EFLAGS;
128	/** Pointer to const EFLAGS. */
129	typedef const X86EFLAGS *PCX86EFLAGS;
130
131	/**
132	* RFLAGS (32 upper bits are reserved).
133	*/
134	typedef union X86RFLAGS
135	{
136	/** The plain unsigned view. */
137	uint64_t u;
138	#ifndef VBOX_FOR_DTRACE_LIB
139	/** The bitfield view. */
140	X86EFLAGSBITS Bits;
141	#endif
142	/** The 8-bit view. */
143	uint8_t au8[8];
144	/** The 16-bit view. */
145	uint16_t au16[4];
146	/** The 32-bit view. */
147	uint32_t au32[2];
148	/** The 64-bit view. */
149	uint64_t au64[1];
150	/** The 64-bit view. */
151	uint64_t u64;
152	} X86RFLAGS;
153	/** Pointer to RFLAGS. */
154	typedef X86RFLAGS *PX86RFLAGS;
155	/** Pointer to const RFLAGS. */
156	typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159	/** @name EFLAGS
160	* @{
161	*/
162	/** Bit 0 - CF - Carry flag - Status flag. */
163	#define X86_EFL_CF RT_BIT_32(0)
164	#define X86_EFL_CF_BIT 0
165	/** Bit 1 - Reserved, reads as 1. */
166	#define X86_EFL_1 RT_BIT_32(1)
167	/** Bit 2 - PF - Parity flag - Status flag. */
168	#define X86_EFL_PF RT_BIT_32(2)
169	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
170	#define X86_EFL_AF RT_BIT_32(4)
171	#define X86_EFL_AF_BIT 4
172	/** Bit 6 - ZF - Zero flag - Status flag. */
173	#define X86_EFL_ZF RT_BIT_32(6)
174	#define X86_EFL_ZF_BIT 6
175	/** Bit 7 - SF - Signed flag - Status flag. */
176	#define X86_EFL_SF RT_BIT_32(7)
177	#define X86_EFL_SF_BIT 7
178	/** Bit 8 - TF - Trap flag - System flag. */
179	#define X86_EFL_TF RT_BIT_32(8)
180	/** Bit 9 - IF - Interrupt flag - System flag. */
181	#define X86_EFL_IF RT_BIT_32(9)
182	/** Bit 10 - DF - Direction flag - Control flag. */
183	#define X86_EFL_DF RT_BIT_32(10)
184	/** Bit 11 - OF - Overflow flag - Status flag. */
185	#define X86_EFL_OF RT_BIT_32(11)
186	#define X86_EFL_OF_BIT 11
187	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
188	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
189	/** Bit 14 - NT - Nested task flag - System flag. */
190	#define X86_EFL_NT RT_BIT_32(14)
191	/** Bit 16 - RF - Resume flag - System flag. */
192	#define X86_EFL_RF RT_BIT_32(16)
193	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
194	#define X86_EFL_VM RT_BIT_32(17)
195	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
196	#define X86_EFL_AC RT_BIT_32(18)
197	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
198	#define X86_EFL_VIF RT_BIT_32(19)
199	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
200	#define X86_EFL_VIP RT_BIT_32(20)
201	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
202	#define X86_EFL_ID RT_BIT_32(21)
203	/** All live bits. */
204	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
205	/** Read as 1 bits. */
206	#define X86_EFL_RA1_MASK RT_BIT_32(1)
207	/** IOPL shift. */
208	#define X86_EFL_IOPL_SHIFT 12
209	/** The IOPL level from the flags. */
210	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
211	/** Bits restored by popf */
212	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
213	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
214	/** The status bits commonly updated by arithmetic instructions. */
215	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
216	/** @} */
217
218
219	/** CPUID Feature information - ECX.
220	* CPUID query with EAX=1.
221	*/
222	#ifndef VBOX_FOR_DTRACE_LIB
223	typedef struct X86CPUIDFEATECX
224	{
225	/** Bit 0 - SSE3 - Supports SSE3 or not. */
226	unsigned u1SSE3 : 1;
227	/** Bit 1 - PCLMULQDQ. */
228	unsigned u1PCLMULQDQ : 1;
229	/** Bit 2 - DS Area 64-bit layout. */
230	unsigned u1DTE64 : 1;
231	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
232	unsigned u1Monitor : 1;
233	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
234	unsigned u1CPLDS : 1;
235	/** Bit 5 - VMX - Virtual Machine Technology. */
236	unsigned u1VMX : 1;
237	/** Bit 6 - SMX: Safer Mode Extensions. */
238	unsigned u1SMX : 1;
239	/** Bit 7 - EST - Enh. SpeedStep Tech. */
240	unsigned u1EST : 1;
241	/** Bit 8 - TM2 - Terminal Monitor 2. */
242	unsigned u1TM2 : 1;
243	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
244	unsigned u1SSSE3 : 1;
245	/** Bit 10 - CNTX-ID - L1 Context ID. */
246	unsigned u1CNTXID : 1;
247	/** Bit 11 - Reserved. */
248	unsigned u1Reserved1 : 1;
249	/** Bit 12 - FMA. */
250	unsigned u1FMA : 1;
251	/** Bit 13 - CX16 - CMPXCHG16B. */
252	unsigned u1CX16 : 1;
253	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
254	unsigned u1TPRUpdate : 1;
255	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
256	unsigned u1PDCM : 1;
257	/** Bit 16 - Reserved. */
258	unsigned u1Reserved2 : 1;
259	/** Bit 17 - PCID - Process-context identifiers. */
260	unsigned u1PCID : 1;
261	/** Bit 18 - Direct Cache Access. */
262	unsigned u1DCA : 1;
263	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
264	unsigned u1SSE4_1 : 1;
265	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
266	unsigned u1SSE4_2 : 1;
267	/** Bit 21 - x2APIC. */
268	unsigned u1x2APIC : 1;
269	/** Bit 22 - MOVBE - Supports MOVBE. */
270	unsigned u1MOVBE : 1;
271	/** Bit 23 - POPCNT - Supports POPCNT. */
272	unsigned u1POPCNT : 1;
273	/** Bit 24 - TSC-Deadline. */
274	unsigned u1TSCDEADLINE : 1;
275	/** Bit 25 - AES. */
276	unsigned u1AES : 1;
277	/** Bit 26 - XSAVE - Supports XSAVE. */
278	unsigned u1XSAVE : 1;
279	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
280	unsigned u1OSXSAVE : 1;
281	/** Bit 28 - AVX - Supports AVX instruction extensions. */
282	unsigned u1AVX : 1;
283	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
284	unsigned u1F16C : 1;
285	/** Bit 30 - RDRAND - Supports RDRAND. */
286	unsigned u1RDRAND : 1;
287	/** Bit 31 - Hypervisor present (we're a guest). */
288	unsigned u1HVP : 1;
289	} X86CPUIDFEATECX;
290	#else /* VBOX_FOR_DTRACE_LIB */
291	typedef uint32_t X86CPUIDFEATECX;
292	#endif /* VBOX_FOR_DTRACE_LIB */
293	/** Pointer to CPUID Feature Information - ECX. */
294	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
295	/** Pointer to const CPUID Feature Information - ECX. */
296	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
297
298
299	/** CPUID Feature Information - EDX.
300	* CPUID query with EAX=1.
301	*/
302	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
303	typedef struct X86CPUIDFEATEDX
304	{
305	/** Bit 0 - FPU - x87 FPU on Chip. */
306	unsigned u1FPU : 1;
307	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
308	unsigned u1VME : 1;
309	/** Bit 2 - DE - Debugging extensions. */
310	unsigned u1DE : 1;
311	/** Bit 3 - PSE - Page Size Extension. */
312	unsigned u1PSE : 1;
313	/** Bit 4 - TSC - Time Stamp Counter. */
314	unsigned u1TSC : 1;
315	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
316	unsigned u1MSR : 1;
317	/** Bit 6 - PAE - Physical Address Extension. */
318	unsigned u1PAE : 1;
319	/** Bit 7 - MCE - Machine Check Exception. */
320	unsigned u1MCE : 1;
321	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
322	unsigned u1CX8 : 1;
323	/** Bit 9 - APIC - APIC On-Chip. */
324	unsigned u1APIC : 1;
325	/** Bit 10 - Reserved. */
326	unsigned u1Reserved1 : 1;
327	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
328	unsigned u1SEP : 1;
329	/** Bit 12 - MTRR - Memory Type Range Registers. */
330	unsigned u1MTRR : 1;
331	/** Bit 13 - PGE - PTE Global Bit. */
332	unsigned u1PGE : 1;
333	/** Bit 14 - MCA - Machine Check Architecture. */
334	unsigned u1MCA : 1;
335	/** Bit 15 - CMOV - Conditional Move Instructions. */
336	unsigned u1CMOV : 1;
337	/** Bit 16 - PAT - Page Attribute Table. */
338	unsigned u1PAT : 1;
339	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
340	unsigned u1PSE36 : 1;
341	/** Bit 18 - PSN - Processor Serial Number. */
342	unsigned u1PSN : 1;
343	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
344	unsigned u1CLFSH : 1;
345	/** Bit 20 - Reserved. */
346	unsigned u1Reserved2 : 1;
347	/** Bit 21 - DS - Debug Store. */
348	unsigned u1DS : 1;
349	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
350	unsigned u1ACPI : 1;
351	/** Bit 23 - MMX - Intel MMX 'Technology'. */
352	unsigned u1MMX : 1;
353	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
354	unsigned u1FXSR : 1;
355	/** Bit 25 - SSE - SSE Support. */
356	unsigned u1SSE : 1;
357	/** Bit 26 - SSE2 - SSE2 Support. */
358	unsigned u1SSE2 : 1;
359	/** Bit 27 - SS - Self Snoop. */
360	unsigned u1SS : 1;
361	/** Bit 28 - HTT - Hyper-Threading Technology. */
362	unsigned u1HTT : 1;
363	/** Bit 29 - TM - Thermal Monitor. */
364	unsigned u1TM : 1;
365	/** Bit 30 - Reserved - . */
366	unsigned u1Reserved3 : 1;
367	/** Bit 31 - PBE - Pending Break Enabled. */
368	unsigned u1PBE : 1;
369	} X86CPUIDFEATEDX;
370	#else /* VBOX_FOR_DTRACE_LIB */
371	typedef uint32_t X86CPUIDFEATEDX;
372	#endif /* VBOX_FOR_DTRACE_LIB */
373	/** Pointer to CPUID Feature Information - EDX. */
374	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
375	/** Pointer to const CPUID Feature Information - EDX. */
376	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
377
378	/** @name CPUID Vendor information.
379	* CPUID query with EAX=0.
380	* @{
381	*/
382	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
383	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
384	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
385
386	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
387	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
388	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
389
390	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
391	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
392	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
393	/** @} */
394
395
396	/** @name CPUID Feature information.
397	* CPUID query with EAX=1.
398	* @{
399	*/
400	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
401	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
402	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
403	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
404	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
405	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
406	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
407	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
408	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
409	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
410	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
411	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
412	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
413	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
414	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
415	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
416	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
417	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
418	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
419	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
420	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
421	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
422	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
423	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
424	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
425	/** ECX Bit 12 - FMA. */
426	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
427	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
428	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
429	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
430	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
431	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
432	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
433	/** ECX Bit 17 - PCID - Process-context identifiers. */
434	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
435	/** ECX Bit 18 - DCA - Direct Cache Access. */
436	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
437	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
438	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
439	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
440	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
441	/** ECX Bit 21 - x2APIC support. */
442	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
443	/** ECX Bit 22 - MOVBE instruction. */
444	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
445	/** ECX Bit 23 - POPCNT instruction. */
446	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
447	/** ECX Bir 24 - TSC-Deadline. */
448	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
449	/** ECX Bit 25 - AES instructions. */
450	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
451	/** ECX Bit 26 - XSAVE instruction. */
452	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
453	/** ECX Bit 27 - OSXSAVE instruction. */
454	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
455	/** ECX Bit 28 - AVX. */
456	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
457	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
458	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
459	/** ECX Bit 30 - RDRAND instruction. */
460	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
461	/** ECX Bit 31 - Hypervisor Present (software only). */
462	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
463
464
465	/** Bit 0 - FPU - x87 FPU on Chip. */
466	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
467	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
468	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
469	/** Bit 2 - DE - Debugging extensions. */
470	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
471	/** Bit 3 - PSE - Page Size Extension. */
472	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
473	/** Bit 4 - TSC - Time Stamp Counter. */
474	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
475	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
476	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
477	/** Bit 6 - PAE - Physical Address Extension. */
478	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
479	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6
480	/** Bit 7 - MCE - Machine Check Exception. */
481	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
482	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
483	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
484	/** Bit 9 - APIC - APIC On-Chip. */
485	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
486	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
487	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
488	/** Bit 12 - MTRR - Memory Type Range Registers. */
489	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
490	/** Bit 13 - PGE - PTE Global Bit. */
491	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
492	/** Bit 14 - MCA - Machine Check Architecture. */
493	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
494	/** Bit 15 - CMOV - Conditional Move Instructions. */
495	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
496	/** Bit 16 - PAT - Page Attribute Table. */
497	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
498	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
499	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
500	/** Bit 18 - PSN - Processor Serial Number. */
501	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
502	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
503	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
504	/** Bit 21 - DS - Debug Store. */
505	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
506	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
507	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
508	/** Bit 23 - MMX - Intel MMX Technology. */
509	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
510	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
511	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
512	/** Bit 25 - SSE - SSE Support. */
513	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
514	/** Bit 26 - SSE2 - SSE2 Support. */
515	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
516	/** Bit 27 - SS - Self Snoop. */
517	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
518	/** Bit 28 - HTT - Hyper-Threading Technology. */
519	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
520	/** Bit 29 - TM - Therm. Monitor. */
521	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
522	/** Bit 31 - PBE - Pending Break Enabled. */
523	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
524	/** @} */
525
526	/** @name CPUID mwait/monitor information.
527	* CPUID query with EAX=5.
528	* @{
529	*/
530	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
531	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
532	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
533	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
534	/** @} */
535
536
537	/** @name CPUID Structured Extended Feature information.
538	* CPUID query with EAX=7.
539	* @{
540	*/
541	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
542	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
543	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
544	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
545	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
546	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
547	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
548	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
549	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
550	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
551	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
552	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
553	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
554	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
555	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
556	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
557	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
558	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
559	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
560	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
561	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
562	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
563	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
564	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
565	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
566	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
567	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
568	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
569	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
570	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
571	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
572	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
573	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
574	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
575	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
576	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
577	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
578	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
579	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
580	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
581	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
582	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
583	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
584	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
585	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
586	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
587	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
588	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
589
590	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
591	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
592	/** @} */
593
594
595	/** @name CPUID Extended Feature information.
596	* CPUID query with EAX=0x80000001.
597	* @{
598	*/
599	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
600	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
601
602	/** EDX Bit 11 - SYSCALL/SYSRET. */
603	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
604	/** EDX Bit 20 - No-Execute/Execute-Disable. */
605	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
606	/** EDX Bit 26 - 1 GB large page. */
607	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
608	/** EDX Bit 27 - RDTSCP. */
609	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
610	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
611	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
612	/** @}*/
613
614	/** @name CPUID AMD Feature information.
615	* CPUID query with EAX=0x80000001.
616	* @{
617	*/
618	/** Bit 0 - FPU - x87 FPU on Chip. */
619	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
620	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
621	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
622	/** Bit 2 - DE - Debugging extensions. */
623	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
624	/** Bit 3 - PSE - Page Size Extension. */
625	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
626	/** Bit 4 - TSC - Time Stamp Counter. */
627	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
628	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
629	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
630	/** Bit 6 - PAE - Physical Address Extension. */
631	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
632	/** Bit 7 - MCE - Machine Check Exception. */
633	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
634	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
635	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
636	/** Bit 9 - APIC - APIC On-Chip. */
637	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
638	/** Bit 12 - MTRR - Memory Type Range Registers. */
639	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
640	/** Bit 13 - PGE - PTE Global Bit. */
641	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
642	/** Bit 14 - MCA - Machine Check Architecture. */
643	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
644	/** Bit 15 - CMOV - Conditional Move Instructions. */
645	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
646	/** Bit 16 - PAT - Page Attribute Table. */
647	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
648	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
649	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
650	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
651	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
652	/** Bit 23 - MMX - Intel MMX Technology. */
653	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
654	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
655	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
656	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
657	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
658	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
659	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
660	/** Bit 31 - 3DNOW - AMD 3DNow. */
661	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
662
663	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
664	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
665	/** Bit 2 - SVM - AMD VM extensions. */
666	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
667	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
668	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
669	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
670	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
671	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
672	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
673	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
674	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
675	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
676	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
677	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
678	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
679	/** Bit 9 - OSVW - AMD OS visible workaround. */
680	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
681	/** Bit 10 - IBS - Instruct based sampling. */
682	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
683	/** Bit 11 - XOP - Extended operation support (see APM6). */
684	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
685	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
686	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
687	/** Bit 13 - WDT - AMD Watchdog timer support. */
688	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
689	/** Bit 15 - LWP - Lightweight profiling support. */
690	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
691	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
692	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
693	/** Bit 19 - NodeId - Indicates support for
694	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
695	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
696	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
697	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
698	/** Bit 22 - TopologyExtensions - . */
699	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
700	/** @} */
701
702
703	/** @name CPUID AMD Feature information.
704	* CPUID query with EAX=0x80000007.
705	* @{
706	*/
707	/** Bit 0 - TS - Temperature Sensor. */
708	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
709	/** Bit 1 - FID - Frequency ID Control. */
710	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
711	/** Bit 2 - VID - Voltage ID Control. */
712	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
713	/** Bit 3 - TTP - THERMTRIP. */
714	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
715	/** Bit 4 - TM - Hardware Thermal Control. */
716	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
717	/** Bit 5 - STC - Software Thermal Control. */
718	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
719	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
720	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
721	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
722	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
723	/** Bit 8 - TSCINVAR - TSC Invariant. */
724	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
725	/** Bit 9 - CPB - TSC Invariant. */
726	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
727	/** Bit 10 - EffFreqRO - MPERF/APERF. */
728	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
729	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
730	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
731	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
732	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
733	/** @} */
734
735
736	/** @name CR0
737	* @{ */
738	/** Bit 0 - PE - Protection Enabled */
739	#define X86_CR0_PE RT_BIT_32(0)
740	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
741	/** Bit 1 - MP - Monitor Coprocessor */
742	#define X86_CR0_MP RT_BIT_32(1)
743	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
744	/** Bit 2 - EM - Emulation. */
745	#define X86_CR0_EM RT_BIT_32(2)
746	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
747	/** Bit 3 - TS - Task Switch. */
748	#define X86_CR0_TS RT_BIT_32(3)
749	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
750	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
751	#define X86_CR0_ET RT_BIT_32(4)
752	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
753	/** Bit 5 - NE - Numeric error. */
754	#define X86_CR0_NE RT_BIT_32(5)
755	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
756	/** Bit 16 - WP - Write Protect. */
757	#define X86_CR0_WP RT_BIT_32(16)
758	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
759	/** Bit 18 - AM - Alignment Mask. */
760	#define X86_CR0_AM RT_BIT_32(18)
761	#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
762	/** Bit 29 - NW - Not Write-though. */
763	#define X86_CR0_NW RT_BIT_32(29)
764	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
765	/** Bit 30 - WP - Cache Disable. */
766	#define X86_CR0_CD RT_BIT_32(30)
767	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
768	/** Bit 31 - PG - Paging. */
769	#define X86_CR0_PG RT_BIT_32(31)
770	#define X86_CR0_PAGING RT_BIT_32(31)
771	/** @} */
772
773
774	/** @name CR3
775	* @{ */
776	/** Bit 3 - PWT - Page-level Writes Transparent. */
777	#define X86_CR3_PWT RT_BIT_32(3)
778	/** Bit 4 - PCD - Page-level Cache Disable. */
779	#define X86_CR3_PCD RT_BIT_32(4)
780	/** Bits 12-31 - - Page directory page number. */
781	#define X86_CR3_PAGE_MASK (0xfffff000)
782	/** Bits 5-31 - - PAE Page directory page number. */
783	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
784	/** Bits 12-51 - - AMD64 Page directory page number. */
785	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
786	/** @} */
787
788
789	/** @name CR4
790	* @{ */
791	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
792	#define X86_CR4_VME RT_BIT_32(0)
793	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
794	#define X86_CR4_PVI RT_BIT_32(1)
795	/** Bit 2 - TSD - Time Stamp Disable. */
796	#define X86_CR4_TSD RT_BIT_32(2)
797	/** Bit 3 - DE - Debugging Extensions. */
798	#define X86_CR4_DE RT_BIT_32(3)
799	/** Bit 4 - PSE - Page Size Extension. */
800	#define X86_CR4_PSE RT_BIT_32(4)
801	/** Bit 5 - PAE - Physical Address Extension. */
802	#define X86_CR4_PAE RT_BIT_32(5)
803	/** Bit 6 - MCE - Machine-Check Enable. */
804	#define X86_CR4_MCE RT_BIT_32(6)
805	/** Bit 7 - PGE - Page Global Enable. */
806	#define X86_CR4_PGE RT_BIT_32(7)
807	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
808	#define X86_CR4_PCE RT_BIT_32(8)
809	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
810	#define X86_CR4_OSFXSR RT_BIT_32(9)
811	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
812	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
813	/** Bit 13 - VMXE - VMX mode is enabled. */
814	#define X86_CR4_VMXE RT_BIT_32(13)
815	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
816	#define X86_CR4_SMXE RT_BIT_32(14)
817	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
818	#define X86_CR4_PCIDE RT_BIT_32(17)
819	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
820	* extended states. */
821	#define X86_CR4_OSXSAVE RT_BIT_32(18)
822	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
823	#define X86_CR4_SMEP RT_BIT_32(20)
824	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
825	#define X86_CR4_SMAP RT_BIT_32(21)
826	/** Bit 22 - PKE - Protection Key Enable. */
827	#define X86_CR4_PKE RT_BIT_32(22)
828	/** @} */
829
830
831	/** @name DR6
832	* @{ */
833	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
834	#define X86_DR6_B0 RT_BIT_32(0)
835	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
836	#define X86_DR6_B1 RT_BIT_32(1)
837	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
838	#define X86_DR6_B2 RT_BIT_32(2)
839	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
840	#define X86_DR6_B3 RT_BIT_32(3)
841	/** Mask of all the Bx bits. */
842	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
843	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
844	#define X86_DR6_BD RT_BIT_32(13)
845	/** Bit 14 - BS - Single step */
846	#define X86_DR6_BS RT_BIT_32(14)
847	/** Bit 15 - BT - Task switch. (TSS T bit.) */
848	#define X86_DR6_BT RT_BIT_32(15)
849	/** Value of DR6 after powerup/reset. */
850	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
851	/** Bits which must be 1s in DR6. */
852	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
853	/** Bits which must be 0s in DR6. */
854	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
855	/** Bits which must be 0s on writes to DR6. */
856	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
857	/** @} */
858
859	/** Get the DR6.Bx bit for a the given breakpoint. */
860	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
861
862
863	/** @name DR7
864	* @{ */
865	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
866	#define X86_DR7_L0 RT_BIT_32(0)
867	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
868	#define X86_DR7_G0 RT_BIT_32(1)
869	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
870	#define X86_DR7_L1 RT_BIT_32(2)
871	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
872	#define X86_DR7_G1 RT_BIT_32(3)
873	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
874	#define X86_DR7_L2 RT_BIT_32(4)
875	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
876	#define X86_DR7_G2 RT_BIT_32(5)
877	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
878	#define X86_DR7_L3 RT_BIT_32(6)
879	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
880	#define X86_DR7_G3 RT_BIT_32(7)
881	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
882	#define X86_DR7_LE RT_BIT_32(8)
883	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
884	#define X86_DR7_GE RT_BIT_32(9)
885
886	/** L0, L1, L2, and L3. */
887	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
888	/** L0, L1, L2, and L3. */
889	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
890
891	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
892	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
893	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
894	* instruction is executed.
895	* @see http://www.rcollins.org/secrets/DR7.html */
896	#define X86_DR7_ICE_IR RT_BIT_32(12)
897	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
898	* any DR register is accessed. */
899	#define X86_DR7_GD RT_BIT_32(13)
900	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
901	* Pentium. */
902	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
903	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
904	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
905	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
906	#define X86_DR7_RW0_MASK (3 << 16)
907	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
908	#define X86_DR7_LEN0_MASK (3 << 18)
909	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
910	#define X86_DR7_RW1_MASK (3 << 20)
911	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
912	#define X86_DR7_LEN1_MASK (3 << 22)
913	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
914	#define X86_DR7_RW2_MASK (3 << 24)
915	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
916	#define X86_DR7_LEN2_MASK (3 << 26)
917	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
918	#define X86_DR7_RW3_MASK (3 << 28)
919	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
920	#define X86_DR7_LEN3_MASK (3 << 30)
921
922	/** Bits which reads as 1s. */
923	#define X86_DR7_RA1_MASK RT_BIT_32(10)
924	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
925	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
926	/** Bits which must be 0s when writing to DR7. */
927	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
928
929	/** Calcs the L bit of Nth breakpoint.
930	* @param iBp The breakpoint number [0..3].
931	*/
932	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
933
934	/** Calcs the G bit of Nth breakpoint.
935	* @param iBp The breakpoint number [0..3].
936	*/
937	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
938
939	/** Calcs the L and G bits of Nth breakpoint.
940	* @param iBp The breakpoint number [0..3].
941	*/
942	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
943
944	/** @name Read/Write values.
945	* @{ */
946	/** Break on instruction fetch only. */
947	#define X86_DR7_RW_EO 0U
948	/** Break on write only. */
949	#define X86_DR7_RW_WO 1U
950	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
951	#define X86_DR7_RW_IO 2U
952	/** Break on read or write (but not instruction fetches). */
953	#define X86_DR7_RW_RW 3U
954	/** @} */
955
956	/** Shifts a X86_DR7_RW_* value to its right place.
957	* @param iBp The breakpoint number [0..3].
958	* @param fRw One of the X86_DR7_RW_* value.
959	*/
960	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
961
962	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
963	* one of the X86_DR7_RW_XXX constants).
964	*
965	* @returns X86_DR7_RW_XXX
966	* @param uDR7 DR7 value
967	* @param iBp The breakpoint number [0..3].
968	*/
969	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
970
971	/** R/W0, R/W1, R/W2, and R/W3. */
972	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
973
974	#ifndef VBOX_FOR_DTRACE_LIB
975	/** Checks if there are any I/O breakpoint types configured in the RW
976	* registers. Does NOT check if these are enabled, sorry. */
977	# define X86_DR7_ANY_RW_IO(uDR7) \
978	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
979	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
980	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
981	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
982	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
983	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
984	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
985	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
986	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
987	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
988	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
989	#endif /* !VBOX_FOR_DTRACE_LIB */
990
991	/** @name Length values.
992	* @{ */
993	#define X86_DR7_LEN_BYTE 0U
994	#define X86_DR7_LEN_WORD 1U
995	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
996	#define X86_DR7_LEN_DWORD 3U
997	/** @} */
998
999	/** Shifts a X86_DR7_LEN_* value to its right place.
1000	* @param iBp The breakpoint number [0..3].
1001	* @param cb One of the X86_DR7_LEN_* values.
1002	*/
1003	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1004
1005	/** Fetch the breakpoint length bits from the DR7 value.
1006	* @param uDR7 DR7 value
1007	* @param iBp The breakpoint number [0..3].
1008	*/
1009	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1010
1011	/** Mask used to check if any breakpoints are enabled. */
1012	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1013
1014	/** LEN0, LEN1, LEN2, and LEN3. */
1015	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1016	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1017	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1018
1019	/** Value of DR7 after powerup/reset. */
1020	#define X86_DR7_INIT_VAL 0x400
1021	/** @} */
1022
1023
1024	/** @name Machine Specific Registers
1025	* @{
1026	*/
1027	/** Machine check address register (P5). */
1028	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1029	/** Machine check type register (P5). */
1030	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1031	/** Time Stamp Counter. */
1032	#define MSR_IA32_TSC 0x10
1033	#define MSR_IA32_CESR UINT32_C(0x00000011)
1034	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1035	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1036
1037	#define MSR_IA32_PLATFORM_ID 0x17
1038
1039	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1040	# define MSR_IA32_APICBASE 0x1b
1041	/** Local APIC enabled. */
1042	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1043	/** X2APIC enabled (requires the EN bit to be set). */
1044	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1045	/** The processor is the boot strap processor (BSP). */
1046	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1047	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1048	* width. */
1049	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1050	#endif
1051
1052	/** Undocumented intel MSR for reporting thread and core counts.
1053	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1054	* first 16 bits is the thread count. The next 16 bits the core count, except
1055	* on Westmere where it seems it's only the next 4 bits for some reason. */
1056	#define MSR_CORE_THREAD_COUNT 0x35
1057
1058	/** CPU Feature control. */
1059	#define MSR_IA32_FEATURE_CONTROL 0x3A
1060	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_32(0)
1061	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_32(1)
1062	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_32(2)
1063
1064	/** Per-processor TSC adjust MSR. */
1065	#define MSR_IA32_TSC_ADJUST 0x3B
1066
1067	/** BIOS update trigger (microcode update). */
1068	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1069
1070	/** BIOS update signature (microcode). */
1071	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1072
1073	/** SMM monitor control. */
1074	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1075
1076	/** General performance counter no. 0. */
1077	#define MSR_IA32_PMC0 0xC1
1078	/** General performance counter no. 1. */
1079	#define MSR_IA32_PMC1 0xC2
1080	/** General performance counter no. 2. */
1081	#define MSR_IA32_PMC2 0xC3
1082	/** General performance counter no. 3. */
1083	#define MSR_IA32_PMC3 0xC4
1084
1085	/** Nehalem power control. */
1086	#define MSR_IA32_PLATFORM_INFO 0xCE
1087
1088	/** Get FSB clock status (Intel-specific). */
1089	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1090
1091	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1092	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1093
1094	/** C0 Maximum Frequency Clock Count */
1095	#define MSR_IA32_MPERF 0xE7
1096	/** C0 Actual Frequency Clock Count */
1097	#define MSR_IA32_APERF 0xE8
1098
1099	/** MTRR Capabilities. */
1100	#define MSR_IA32_MTRR_CAP 0xFE
1101
1102	/** Cache control/info. */
1103	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1104
1105	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1106	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1107	* R0 SS == CS + 8
1108	* R3 CS == CS + 16
1109	* R3 SS == CS + 24
1110	*/
1111	#define MSR_IA32_SYSENTER_CS 0x174
1112	/** SYSENTER_ESP - the R0 ESP. */
1113	#define MSR_IA32_SYSENTER_ESP 0x175
1114	/** SYSENTER_EIP - the R0 EIP. */
1115	#define MSR_IA32_SYSENTER_EIP 0x176
1116	#endif
1117
1118	/** Machine Check Global Capabilities Register. */
1119	#define MSR_IA32_MCG_CAP 0x179
1120	/** Machine Check Global Status Register. */
1121	#define MSR_IA32_MCG_STATUS 0x17A
1122	/** Machine Check Global Control Register. */
1123	#define MSR_IA32_MCG_CTRL 0x17B
1124
1125	/** Page Attribute Table. */
1126	#define MSR_IA32_CR_PAT 0x277
1127
1128	/** Performance counter MSRs. (Intel only) */
1129	#define MSR_IA32_PERFEVTSEL0 0x186
1130	#define MSR_IA32_PERFEVTSEL1 0x187
1131	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1132	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1133	* holds a ratio that Apple takes for TSC granularity.
1134	*
1135	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1136	#define MSR_FLEX_RATIO 0x194
1137	/** Performance state value and starting with Intel core more.
1138	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1139	#define MSR_IA32_PERF_STATUS 0x198
1140	#define MSR_IA32_PERF_CTL 0x199
1141	#define MSR_IA32_THERM_STATUS 0x19c
1142
1143	/** Enable misc. processor features (R/W). */
1144	#define MSR_IA32_MISC_ENABLE 0x1A0
1145	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1146	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1147	/** Automatic Thermal Control Circuit Enable (R/W). */
1148	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1149	/** Performance Monitoring Available (R). */
1150	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1151	/** Branch Trace Storage Unavailable (R/O). */
1152	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1153	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1154	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1155	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1156	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1157	/** If MONITOR/MWAIT is supported (R/W). */
1158	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1159	/** Limit CPUID Maxval to 3 leafs (R/W). */
1160	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1161	/** When set to 1, xTPR messages are disabled (R/W). */
1162	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1163	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1164	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1165
1166	/** Trace/Profile Resource Control (R/W) */
1167	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1168	/** The number (0..3 or 0..15) of the last branch record register on P4 and
1169	* related Xeons. */
1170	#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1171	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1172	* @{ */
1173	#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1174	#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1175	#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1176	#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1177	/** @} */
1178
1179
1180	#define IA32_MTRR_PHYSBASE0 0x200
1181	#define IA32_MTRR_PHYSMASK0 0x201
1182	#define IA32_MTRR_PHYSBASE1 0x202
1183	#define IA32_MTRR_PHYSMASK1 0x203
1184	#define IA32_MTRR_PHYSBASE2 0x204
1185	#define IA32_MTRR_PHYSMASK2 0x205
1186	#define IA32_MTRR_PHYSBASE3 0x206
1187	#define IA32_MTRR_PHYSMASK3 0x207
1188	#define IA32_MTRR_PHYSBASE4 0x208
1189	#define IA32_MTRR_PHYSMASK4 0x209
1190	#define IA32_MTRR_PHYSBASE5 0x20a
1191	#define IA32_MTRR_PHYSMASK5 0x20b
1192	#define IA32_MTRR_PHYSBASE6 0x20c
1193	#define IA32_MTRR_PHYSMASK6 0x20d
1194	#define IA32_MTRR_PHYSBASE7 0x20e
1195	#define IA32_MTRR_PHYSMASK7 0x20f
1196	#define IA32_MTRR_PHYSBASE8 0x210
1197	#define IA32_MTRR_PHYSMASK8 0x211
1198	#define IA32_MTRR_PHYSBASE9 0x212
1199	#define IA32_MTRR_PHYSMASK9 0x213
1200
1201	/** Fixed range MTRRs.
1202	* @{ */
1203	#define IA32_MTRR_FIX64K_00000 0x250
1204	#define IA32_MTRR_FIX16K_80000 0x258
1205	#define IA32_MTRR_FIX16K_A0000 0x259
1206	#define IA32_MTRR_FIX4K_C0000 0x268
1207	#define IA32_MTRR_FIX4K_C8000 0x269
1208	#define IA32_MTRR_FIX4K_D0000 0x26a
1209	#define IA32_MTRR_FIX4K_D8000 0x26b
1210	#define IA32_MTRR_FIX4K_E0000 0x26c
1211	#define IA32_MTRR_FIX4K_E8000 0x26d
1212	#define IA32_MTRR_FIX4K_F0000 0x26e
1213	#define IA32_MTRR_FIX4K_F8000 0x26f
1214	/** @} */
1215
1216	/** MTRR Default Range. */
1217	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1218
1219	#define MSR_IA32_MC0_CTL 0x400
1220	#define MSR_IA32_MC0_STATUS 0x401
1221
1222	/** Basic VMX information. */
1223	#define MSR_IA32_VMX_BASIC_INFO 0x480
1224	/** Allowed settings for pin-based VM execution controls */
1225	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1226	/** Allowed settings for proc-based VM execution controls */
1227	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1228	/** Allowed settings for the VMX exit controls. */
1229	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1230	/** Allowed settings for the VMX entry controls. */
1231	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1232	/** Misc VMX info. */
1233	#define MSR_IA32_VMX_MISC 0x485
1234	/** Fixed cleared bits in CR0. */
1235	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1236	/** Fixed set bits in CR0. */
1237	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1238	/** Fixed cleared bits in CR4. */
1239	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1240	/** Fixed set bits in CR4. */
1241	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1242	/** Information for enumerating fields in the VMCS. */
1243	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1244	/** Allowed settings for the VM-functions controls. */
1245	#define MSR_IA32_VMX_VMFUNC 0x491
1246	/** Allowed settings for secondary proc-based VM execution controls */
1247	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1248	/** EPT capabilities. */
1249	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1250	/** DS Save Area (R/W). */
1251	#define MSR_IA32_DS_AREA 0x600
1252	/** Running Average Power Limit (RAPL) power units. */
1253	#define MSR_RAPL_POWER_UNIT 0x606
1254
1255	/** X2APIC MSR range start. */
1256	#define MSR_IA32_X2APIC_START 0x800
1257	/** X2APIC MSR - APIC ID Register. */
1258	#define MSR_IA32_X2APIC_ID 0x802
1259	/** X2APIC MSR - APIC Version Register. */
1260	#define MSR_IA32_X2APIC_VERSION 0x803
1261	/** X2APIC MSR - Task Priority Register. */
1262	#define MSR_IA32_X2APIC_TPR 0x808
1263	/** X2APIC MSR - Processor Priority register. */
1264	#define MSR_IA32_X2APIC_PPR 0x80A
1265	/** X2APIC MSR - End Of Interrupt register. */
1266	#define MSR_IA32_X2APIC_EOI 0x80B
1267	/** X2APIC MSR - Logical Destination Register. */
1268	#define MSR_IA32_X2APIC_LDR 0x80D
1269	/** X2APIC MSR - Spurious Interrupt Vector Register. */
1270	#define MSR_IA32_X2APIC_SVR 0x80F
1271	/** X2APIC MSR - In-service Register (bits 31:0). */
1272	#define MSR_IA32_X2APIC_ISR0 0x810
1273	/** X2APIC MSR - In-service Register (bits 63:32). */
1274	#define MSR_IA32_X2APIC_ISR1 0x811
1275	/** X2APIC MSR - In-service Register (bits 95:64). */
1276	#define MSR_IA32_X2APIC_ISR2 0x812
1277	/** X2APIC MSR - In-service Register (bits 127:96). */
1278	#define MSR_IA32_X2APIC_ISR3 0x813
1279	/** X2APIC MSR - In-service Register (bits 159:128). */
1280	#define MSR_IA32_X2APIC_ISR4 0x814
1281	/** X2APIC MSR - In-service Register (bits 191:160). */
1282	#define MSR_IA32_X2APIC_ISR5 0x815
1283	/** X2APIC MSR - In-service Register (bits 223:192). */
1284	#define MSR_IA32_X2APIC_ISR6 0x816
1285	/** X2APIC MSR - In-service Register (bits 255:224). */
1286	#define MSR_IA32_X2APIC_ISR7 0x817
1287	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1288	#define MSR_IA32_X2APIC_TMR0 0x818
1289	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1290	#define MSR_IA32_X2APIC_TMR1 0x819
1291	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1292	#define MSR_IA32_X2APIC_TMR2 0x81A
1293	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1294	#define MSR_IA32_X2APIC_TMR3 0x81B
1295	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1296	#define MSR_IA32_X2APIC_TMR4 0x81C
1297	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1298	#define MSR_IA32_X2APIC_TMR5 0x81D
1299	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1300	#define MSR_IA32_X2APIC_TMR6 0x81E
1301	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1302	#define MSR_IA32_X2APIC_TMR7 0x81F
1303	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1304	#define MSR_IA32_X2APIC_IRR0 0x820
1305	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1306	#define MSR_IA32_X2APIC_IRR1 0x821
1307	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1308	#define MSR_IA32_X2APIC_IRR2 0x822
1309	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1310	#define MSR_IA32_X2APIC_IRR3 0x823
1311	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1312	#define MSR_IA32_X2APIC_IRR4 0x824
1313	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1314	#define MSR_IA32_X2APIC_IRR5 0x825
1315	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1316	#define MSR_IA32_X2APIC_IRR6 0x826
1317	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1318	#define MSR_IA32_X2APIC_IRR7 0x827
1319	/** X2APIC MSR - Error Status Register. */
1320	#define MSR_IA32_X2APIC_ESR 0x828
1321	/** X2APIC MSR - LVT CMCI Register. */
1322	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1323	/** X2APIC MSR - Interrupt Command Register. */
1324	#define MSR_IA32_X2APIC_ICR 0x830
1325	/** X2APIC MSR - LVT Timer Register. */
1326	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1327	/** X2APIC MSR - LVT Thermal Sensor Register. */
1328	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1329	/** X2APIC MSR - LVT Performance Counter Register. */
1330	#define MSR_IA32_X2APIC_LVT_PERF 0x834
1331	/** X2APIC MSR - LVT LINT0 Register. */
1332	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1333	/** X2APIC MSR - LVT LINT1 Register. */
1334	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1335	/** X2APIC MSR - LVT Error Register . */
1336	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1337	/** X2APIC MSR - Timer Initial Count Register. */
1338	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1339	/** X2APIC MSR - Timer Current Count Register. */
1340	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1341	/** X2APIC MSR - Timer Divide Configuration Register. */
1342	#define MSR_IA32_X2APIC_TIMER_DFR 0x83E
1343	/** X2APIC MSR - Self IPI. */
1344	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1345	/** X2APIC MSR range end. */
1346	#define MSR_IA32_X2APIC_END 0xBFF
1347
1348	/** K6 EFER - Extended Feature Enable Register. */
1349	#define MSR_K6_EFER UINT32_C(0xc0000080)
1350	/** @todo document EFER */
1351	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1352	#define MSR_K6_EFER_SCE RT_BIT_32(0)
1353	/** Bit 8 - LME - Long mode enabled. (R/W) */
1354	#define MSR_K6_EFER_LME RT_BIT_32(8)
1355	/** Bit 10 - LMA - Long mode active. (R) */
1356	#define MSR_K6_EFER_LMA RT_BIT_32(10)
1357	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1358	#define MSR_K6_EFER_NXE RT_BIT_32(11)
1359	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1360	#define MSR_K6_EFER_SVME RT_BIT_32(12)
1361	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1362	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1363	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1364	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1365	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1366	#define MSR_K6_EFER_TCE RT_BIT_32(15)
1367	/** K6 STAR - SYSCALL/RET targets. */
1368	#define MSR_K6_STAR UINT32_C(0xc0000081)
1369	/** Shift value for getting the SYSRET CS and SS value. */
1370	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1371	/** Shift value for getting the SYSCALL CS and SS value. */
1372	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1373	/** Selector mask for use after shifting. */
1374	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1375	/** The mask which give the SYSCALL EIP. */
1376	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1377	/** K6 WHCR - Write Handling Control Register. */
1378	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1379	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1380	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1381	/** K6 PSOR - Processor State Observability Register. */
1382	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1383	/** K6 PFIR - Page Flush/Invalidate Register. */
1384	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1385
1386	/** Performance counter MSRs. (AMD only) */
1387	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1388	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1389	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1390	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1391	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1392	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1393	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1394	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1395
1396	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1397	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1398	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1399	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1400	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1401	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1402	/** K8 FS.base - The 64-bit base FS register. */
1403	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1404	/** K8 GS.base - The 64-bit base GS register. */
1405	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1406	/** K8 KernelGSbase - Used with SWAPGS. */
1407	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1408	/** K8 TSC_AUX - Used with RDTSCP. */
1409	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1410	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1411	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1412	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1413	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1414	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1415	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1416	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1417	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1418	/** North bridge config? See BIOS & Kernel dev guides for
1419	* details. */
1420	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1421
1422	/** Hypertransport interrupt pending register.
1423	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1424	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1425	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1426	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1427
1428	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1429	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1430	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1431	* host state during world switch. */
1432	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1433
1434	/** @} */
1435
1436
1437	/** @name Page Table / Directory / Directory Pointers / L4.
1438	* @{
1439	*/
1440
1441	/** Page table/directory entry as an unsigned integer. */
1442	typedef uint32_t X86PGUINT;
1443	/** Pointer to a page table/directory table entry as an unsigned integer. */
1444	typedef X86PGUINT *PX86PGUINT;
1445	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1446	typedef X86PGUINT const *PCX86PGUINT;
1447
1448	/** Number of entries in a 32-bit PT/PD. */
1449	#define X86_PG_ENTRIES 1024
1450
1451
1452	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1453	typedef uint64_t X86PGPAEUINT;
1454	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1455	typedef X86PGPAEUINT *PX86PGPAEUINT;
1456	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1457	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1458
1459	/** Number of entries in a PAE PT/PD. */
1460	#define X86_PG_PAE_ENTRIES 512
1461	/** Number of entries in a PAE PDPT. */
1462	#define X86_PG_PAE_PDPE_ENTRIES 4
1463
1464	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1465	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1466	/** Number of entries in an AMD64 PDPT.
1467	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1468	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1469
1470	/** The size of a 4KB page. */
1471	#define X86_PAGE_4K_SIZE _4K
1472	/** The page shift of a 4KB page. */
1473	#define X86_PAGE_4K_SHIFT 12
1474	/** The 4KB page offset mask. */
1475	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1476	/** The 4KB page base mask for virtual addresses. */
1477	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1478	/** The 4KB page base mask for virtual addresses - 32bit version. */
1479	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1480
1481	/** The size of a 2MB page. */
1482	#define X86_PAGE_2M_SIZE _2M
1483	/** The page shift of a 2MB page. */
1484	#define X86_PAGE_2M_SHIFT 21
1485	/** The 2MB page offset mask. */
1486	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1487	/** The 2MB page base mask for virtual addresses. */
1488	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1489	/** The 2MB page base mask for virtual addresses - 32bit version. */
1490	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1491
1492	/** The size of a 4MB page. */
1493	#define X86_PAGE_4M_SIZE _4M
1494	/** The page shift of a 4MB page. */
1495	#define X86_PAGE_4M_SHIFT 22
1496	/** The 4MB page offset mask. */
1497	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1498	/** The 4MB page base mask for virtual addresses. */
1499	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1500	/** The 4MB page base mask for virtual addresses - 32bit version. */
1501	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1502
1503	/**
1504	* Check if the given address is canonical.
1505	*/
1506	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1507
1508
1509	/** @name Page Table Entry
1510	* @{
1511	*/
1512	/** Bit 0 - P - Present bit. */
1513	#define X86_PTE_BIT_P 0
1514	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1515	#define X86_PTE_BIT_RW 1
1516	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1517	#define X86_PTE_BIT_US 2
1518	/** Bit 3 - PWT - Page level write thru bit. */
1519	#define X86_PTE_BIT_PWT 3
1520	/** Bit 4 - PCD - Page level cache disable bit. */
1521	#define X86_PTE_BIT_PCD 4
1522	/** Bit 5 - A - Access bit. */
1523	#define X86_PTE_BIT_A 5
1524	/** Bit 6 - D - Dirty bit. */
1525	#define X86_PTE_BIT_D 6
1526	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1527	#define X86_PTE_BIT_PAT 7
1528	/** Bit 8 - G - Global flag. */
1529	#define X86_PTE_BIT_G 8
1530
1531	/** Bit 0 - P - Present bit mask. */
1532	#define X86_PTE_P RT_BIT_32(0)
1533	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1534	#define X86_PTE_RW RT_BIT_32(1)
1535	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1536	#define X86_PTE_US RT_BIT_32(2)
1537	/** Bit 3 - PWT - Page level write thru bit mask. */
1538	#define X86_PTE_PWT RT_BIT_32(3)
1539	/** Bit 4 - PCD - Page level cache disable bit mask. */
1540	#define X86_PTE_PCD RT_BIT_32(4)
1541	/** Bit 5 - A - Access bit mask. */
1542	#define X86_PTE_A RT_BIT_32(5)
1543	/** Bit 6 - D - Dirty bit mask. */
1544	#define X86_PTE_D RT_BIT_32(6)
1545	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1546	#define X86_PTE_PAT RT_BIT_32(7)
1547	/** Bit 8 - G - Global bit mask. */
1548	#define X86_PTE_G RT_BIT_32(8)
1549
1550	/** Bits 9-11 - - Available for use to system software. */
1551	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
1552	/** Bits 12-31 - - Physical Page number of the next level. */
1553	#define X86_PTE_PG_MASK ( 0xfffff000 )
1554
1555	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1556	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1557	/** Bits 63 - NX - PAE/LM - No execution flag. */
1558	#define X86_PTE_PAE_NX RT_BIT_64(63)
1559	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1560	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1561	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1562	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1563	/** No bits - - LM - MBZ bits when NX is active. */
1564	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1565	/** Bits 63 - - LM - MBZ bits when no NX. */
1566	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1567
1568	/**
1569	* Page table entry.
1570	*/
1571	typedef struct X86PTEBITS
1572	{
1573	/** Flags whether(=1) or not the page is present. */
1574	uint32_t u1Present : 1;
1575	/** Read(=0) / Write(=1) flag. */
1576	uint32_t u1Write : 1;
1577	/** User(=1) / Supervisor (=0) flag. */
1578	uint32_t u1User : 1;
1579	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1580	uint32_t u1WriteThru : 1;
1581	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1582	uint32_t u1CacheDisable : 1;
1583	/** Accessed flag.
1584	* Indicates that the page have been read or written to. */
1585	uint32_t u1Accessed : 1;
1586	/** Dirty flag.
1587	* Indicates that the page has been written to. */
1588	uint32_t u1Dirty : 1;
1589	/** Reserved / If PAT enabled, bit 2 of the index. */
1590	uint32_t u1PAT : 1;
1591	/** Global flag. (Ignored in all but final level.) */
1592	uint32_t u1Global : 1;
1593	/** Available for use to system software. */
1594	uint32_t u3Available : 3;
1595	/** Physical Page number of the next level. */
1596	uint32_t u20PageNo : 20;
1597	} X86PTEBITS;
1598	#ifndef VBOX_FOR_DTRACE_LIB
1599	AssertCompileSize(X86PTEBITS, 4);
1600	#endif
1601	/** Pointer to a page table entry. */
1602	typedef X86PTEBITS *PX86PTEBITS;
1603	/** Pointer to a const page table entry. */
1604	typedef const X86PTEBITS *PCX86PTEBITS;
1605
1606	/**
1607	* Page table entry.
1608	*/
1609	typedef union X86PTE
1610	{
1611	/** Unsigned integer view */
1612	X86PGUINT u;
1613	/** Bit field view. */
1614	X86PTEBITS n;
1615	/** 32-bit view. */
1616	uint32_t au32[1];
1617	/** 16-bit view. */
1618	uint16_t au16[2];
1619	/** 8-bit view. */
1620	uint8_t au8[4];
1621	} X86PTE;
1622	#ifndef VBOX_FOR_DTRACE_LIB
1623	AssertCompileSize(X86PTE, 4);
1624	#endif
1625	/** Pointer to a page table entry. */
1626	typedef X86PTE *PX86PTE;
1627	/** Pointer to a const page table entry. */
1628	typedef const X86PTE *PCX86PTE;
1629
1630
1631	/**
1632	* PAE page table entry.
1633	*/
1634	typedef struct X86PTEPAEBITS
1635	{
1636	/** Flags whether(=1) or not the page is present. */
1637	uint32_t u1Present : 1;
1638	/** Read(=0) / Write(=1) flag. */
1639	uint32_t u1Write : 1;
1640	/** User(=1) / Supervisor(=0) flag. */
1641	uint32_t u1User : 1;
1642	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1643	uint32_t u1WriteThru : 1;
1644	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1645	uint32_t u1CacheDisable : 1;
1646	/** Accessed flag.
1647	* Indicates that the page have been read or written to. */
1648	uint32_t u1Accessed : 1;
1649	/** Dirty flag.
1650	* Indicates that the page has been written to. */
1651	uint32_t u1Dirty : 1;
1652	/** Reserved / If PAT enabled, bit 2 of the index. */
1653	uint32_t u1PAT : 1;
1654	/** Global flag. (Ignored in all but final level.) */
1655	uint32_t u1Global : 1;
1656	/** Available for use to system software. */
1657	uint32_t u3Available : 3;
1658	/** Physical Page number of the next level - Low Part. Don't use this. */
1659	uint32_t u20PageNoLow : 20;
1660	/** Physical Page number of the next level - High Part. Don't use this. */
1661	uint32_t u20PageNoHigh : 20;
1662	/** MBZ bits */
1663	uint32_t u11Reserved : 11;
1664	/** No Execute flag. */
1665	uint32_t u1NoExecute : 1;
1666	} X86PTEPAEBITS;
1667	#ifndef VBOX_FOR_DTRACE_LIB
1668	AssertCompileSize(X86PTEPAEBITS, 8);
1669	#endif
1670	/** Pointer to a page table entry. */
1671	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1672	/** Pointer to a page table entry. */
1673	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1674
1675	/**
1676	* PAE Page table entry.
1677	*/
1678	typedef union X86PTEPAE
1679	{
1680	/** Unsigned integer view */
1681	X86PGPAEUINT u;
1682	/** Bit field view. */
1683	X86PTEPAEBITS n;
1684	/** 32-bit view. */
1685	uint32_t au32[2];
1686	/** 16-bit view. */
1687	uint16_t au16[4];
1688	/** 8-bit view. */
1689	uint8_t au8[8];
1690	} X86PTEPAE;
1691	#ifndef VBOX_FOR_DTRACE_LIB
1692	AssertCompileSize(X86PTEPAE, 8);
1693	#endif
1694	/** Pointer to a PAE page table entry. */
1695	typedef X86PTEPAE *PX86PTEPAE;
1696	/** Pointer to a const PAE page table entry. */
1697	typedef const X86PTEPAE *PCX86PTEPAE;
1698	/** @} */
1699
1700	/**
1701	* Page table.
1702	*/
1703	typedef struct X86PT
1704	{
1705	/** PTE Array. */
1706	X86PTE a[X86_PG_ENTRIES];
1707	} X86PT;
1708	#ifndef VBOX_FOR_DTRACE_LIB
1709	AssertCompileSize(X86PT, 4096);
1710	#endif
1711	/** Pointer to a page table. */
1712	typedef X86PT *PX86PT;
1713	/** Pointer to a const page table. */
1714	typedef const X86PT *PCX86PT;
1715
1716	/** The page shift to get the PT index. */
1717	#define X86_PT_SHIFT 12
1718	/** The PT index mask (apply to a shifted page address). */
1719	#define X86_PT_MASK 0x3ff
1720
1721
1722	/**
1723	* Page directory.
1724	*/
1725	typedef struct X86PTPAE
1726	{
1727	/** PTE Array. */
1728	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1729	} X86PTPAE;
1730	#ifndef VBOX_FOR_DTRACE_LIB
1731	AssertCompileSize(X86PTPAE, 4096);
1732	#endif
1733	/** Pointer to a page table. */
1734	typedef X86PTPAE *PX86PTPAE;
1735	/** Pointer to a const page table. */
1736	typedef const X86PTPAE *PCX86PTPAE;
1737
1738	/** The page shift to get the PA PTE index. */
1739	#define X86_PT_PAE_SHIFT 12
1740	/** The PAE PT index mask (apply to a shifted page address). */
1741	#define X86_PT_PAE_MASK 0x1ff
1742
1743
1744	/** @name 4KB Page Directory Entry
1745	* @{
1746	*/
1747	/** Bit 0 - P - Present bit. */
1748	#define X86_PDE_P RT_BIT_32(0)
1749	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1750	#define X86_PDE_RW RT_BIT_32(1)
1751	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1752	#define X86_PDE_US RT_BIT_32(2)
1753	/** Bit 3 - PWT - Page level write thru bit. */
1754	#define X86_PDE_PWT RT_BIT_32(3)
1755	/** Bit 4 - PCD - Page level cache disable bit. */
1756	#define X86_PDE_PCD RT_BIT_32(4)
1757	/** Bit 5 - A - Access bit. */
1758	#define X86_PDE_A RT_BIT_32(5)
1759	/** Bit 7 - PS - Page size attribute.
1760	* Clear mean 4KB pages, set means large pages (2/4MB). */
1761	#define X86_PDE_PS RT_BIT_32(7)
1762	/** Bits 9-11 - - Available for use to system software. */
1763	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
1764	/** Bits 12-31 - - Physical Page number of the next level. */
1765	#define X86_PDE_PG_MASK ( 0xfffff000 )
1766
1767	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1768	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1769	/** Bits 63 - NX - PAE/LM - No execution flag. */
1770	#define X86_PDE_PAE_NX RT_BIT_64(63)
1771	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1772	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1773	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1774	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1775	/** Bit 7 - - LM - MBZ bits when NX is active. */
1776	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1777	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1778	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1779
1780	/**
1781	* Page directory entry.
1782	*/
1783	typedef struct X86PDEBITS
1784	{
1785	/** Flags whether(=1) or not the page is present. */
1786	uint32_t u1Present : 1;
1787	/** Read(=0) / Write(=1) flag. */
1788	uint32_t u1Write : 1;
1789	/** User(=1) / Supervisor (=0) flag. */
1790	uint32_t u1User : 1;
1791	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1792	uint32_t u1WriteThru : 1;
1793	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1794	uint32_t u1CacheDisable : 1;
1795	/** Accessed flag.
1796	* Indicates that the page has been read or written to. */
1797	uint32_t u1Accessed : 1;
1798	/** Reserved / Ignored (dirty bit). */
1799	uint32_t u1Reserved0 : 1;
1800	/** Size bit if PSE is enabled - in any event it's 0. */
1801	uint32_t u1Size : 1;
1802	/** Reserved / Ignored (global bit). */
1803	uint32_t u1Reserved1 : 1;
1804	/** Available for use to system software. */
1805	uint32_t u3Available : 3;
1806	/** Physical Page number of the next level. */
1807	uint32_t u20PageNo : 20;
1808	} X86PDEBITS;
1809	#ifndef VBOX_FOR_DTRACE_LIB
1810	AssertCompileSize(X86PDEBITS, 4);
1811	#endif
1812	/** Pointer to a page directory entry. */
1813	typedef X86PDEBITS *PX86PDEBITS;
1814	/** Pointer to a const page directory entry. */
1815	typedef const X86PDEBITS *PCX86PDEBITS;
1816
1817
1818	/**
1819	* PAE page directory entry.
1820	*/
1821	typedef struct X86PDEPAEBITS
1822	{
1823	/** Flags whether(=1) or not the page is present. */
1824	uint32_t u1Present : 1;
1825	/** Read(=0) / Write(=1) flag. */
1826	uint32_t u1Write : 1;
1827	/** User(=1) / Supervisor (=0) flag. */
1828	uint32_t u1User : 1;
1829	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1830	uint32_t u1WriteThru : 1;
1831	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1832	uint32_t u1CacheDisable : 1;
1833	/** Accessed flag.
1834	* Indicates that the page has been read or written to. */
1835	uint32_t u1Accessed : 1;
1836	/** Reserved / Ignored (dirty bit). */
1837	uint32_t u1Reserved0 : 1;
1838	/** Size bit if PSE is enabled - in any event it's 0. */
1839	uint32_t u1Size : 1;
1840	/** Reserved / Ignored (global bit). / */
1841	uint32_t u1Reserved1 : 1;
1842	/** Available for use to system software. */
1843	uint32_t u3Available : 3;
1844	/** Physical Page number of the next level - Low Part. Don't use! */
1845	uint32_t u20PageNoLow : 20;
1846	/** Physical Page number of the next level - High Part. Don't use! */
1847	uint32_t u20PageNoHigh : 20;
1848	/** MBZ bits */
1849	uint32_t u11Reserved : 11;
1850	/** No Execute flag. */
1851	uint32_t u1NoExecute : 1;
1852	} X86PDEPAEBITS;
1853	#ifndef VBOX_FOR_DTRACE_LIB
1854	AssertCompileSize(X86PDEPAEBITS, 8);
1855	#endif
1856	/** Pointer to a page directory entry. */
1857	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1858	/** Pointer to a const page directory entry. */
1859	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1860
1861	/** @} */
1862
1863
1864	/** @name 2/4MB Page Directory Entry
1865	* @{
1866	*/
1867	/** Bit 0 - P - Present bit. */
1868	#define X86_PDE4M_P RT_BIT_32(0)
1869	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1870	#define X86_PDE4M_RW RT_BIT_32(1)
1871	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1872	#define X86_PDE4M_US RT_BIT_32(2)
1873	/** Bit 3 - PWT - Page level write thru bit. */
1874	#define X86_PDE4M_PWT RT_BIT_32(3)
1875	/** Bit 4 - PCD - Page level cache disable bit. */
1876	#define X86_PDE4M_PCD RT_BIT_32(4)
1877	/** Bit 5 - A - Access bit. */
1878	#define X86_PDE4M_A RT_BIT_32(5)
1879	/** Bit 6 - D - Dirty bit. */
1880	#define X86_PDE4M_D RT_BIT_32(6)
1881	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1882	#define X86_PDE4M_PS RT_BIT_32(7)
1883	/** Bit 8 - G - Global flag. */
1884	#define X86_PDE4M_G RT_BIT_32(8)
1885	/** Bits 9-11 - AVL - Available for use to system software. */
1886	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
1887	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1888	#define X86_PDE4M_PAT RT_BIT_32(12)
1889	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1890	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1891	/** Bits 22-31 - - Physical Page number. */
1892	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1893	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1894	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1895	/** The number of bits to the high part of the page number. */
1896	#define X86_PDE4M_PG_HIGH_SHIFT 19
1897	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1898	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1899
1900	/** Bits 21-51 - - PAE/LM - Physical Page number.
1901	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1902	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1903	/** Bits 63 - NX - PAE/LM - No execution flag. */
1904	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1905	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1906	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1907	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1908	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1909	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1910	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1911	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1912	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1913
1914	/**
1915	* 4MB page directory entry.
1916	*/
1917	typedef struct X86PDE4MBITS
1918	{
1919	/** Flags whether(=1) or not the page is present. */
1920	uint32_t u1Present : 1;
1921	/** Read(=0) / Write(=1) flag. */
1922	uint32_t u1Write : 1;
1923	/** User(=1) / Supervisor (=0) flag. */
1924	uint32_t u1User : 1;
1925	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1926	uint32_t u1WriteThru : 1;
1927	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1928	uint32_t u1CacheDisable : 1;
1929	/** Accessed flag.
1930	* Indicates that the page have been read or written to. */
1931	uint32_t u1Accessed : 1;
1932	/** Dirty flag.
1933	* Indicates that the page has been written to. */
1934	uint32_t u1Dirty : 1;
1935	/** Page size flag - always 1 for 4MB entries. */
1936	uint32_t u1Size : 1;
1937	/** Global flag. */
1938	uint32_t u1Global : 1;
1939	/** Available for use to system software. */
1940	uint32_t u3Available : 3;
1941	/** Reserved / If PAT enabled, bit 2 of the index. */
1942	uint32_t u1PAT : 1;
1943	/** Bits 32-39 of the page number on AMD64.
1944	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1945	uint32_t u8PageNoHigh : 8;
1946	/** Reserved. */
1947	uint32_t u1Reserved : 1;
1948	/** Physical Page number of the page. */
1949	uint32_t u10PageNo : 10;
1950	} X86PDE4MBITS;
1951	#ifndef VBOX_FOR_DTRACE_LIB
1952	AssertCompileSize(X86PDE4MBITS, 4);
1953	#endif
1954	/** Pointer to a page table entry. */
1955	typedef X86PDE4MBITS *PX86PDE4MBITS;
1956	/** Pointer to a const page table entry. */
1957	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1958
1959
1960	/**
1961	* 2MB PAE page directory entry.
1962	*/
1963	typedef struct X86PDE2MPAEBITS
1964	{
1965	/** Flags whether(=1) or not the page is present. */
1966	uint32_t u1Present : 1;
1967	/** Read(=0) / Write(=1) flag. */
1968	uint32_t u1Write : 1;
1969	/** User(=1) / Supervisor(=0) flag. */
1970	uint32_t u1User : 1;
1971	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1972	uint32_t u1WriteThru : 1;
1973	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1974	uint32_t u1CacheDisable : 1;
1975	/** Accessed flag.
1976	* Indicates that the page have been read or written to. */
1977	uint32_t u1Accessed : 1;
1978	/** Dirty flag.
1979	* Indicates that the page has been written to. */
1980	uint32_t u1Dirty : 1;
1981	/** Page size flag - always 1 for 2MB entries. */
1982	uint32_t u1Size : 1;
1983	/** Global flag. */
1984	uint32_t u1Global : 1;
1985	/** Available for use to system software. */
1986	uint32_t u3Available : 3;
1987	/** Reserved / If PAT enabled, bit 2 of the index. */
1988	uint32_t u1PAT : 1;
1989	/** Reserved. */
1990	uint32_t u9Reserved : 9;
1991	/** Physical Page number of the next level - Low part. Don't use! */
1992	uint32_t u10PageNoLow : 10;
1993	/** Physical Page number of the next level - High part. Don't use! */
1994	uint32_t u20PageNoHigh : 20;
1995	/** MBZ bits */
1996	uint32_t u11Reserved : 11;
1997	/** No Execute flag. */
1998	uint32_t u1NoExecute : 1;
1999	} X86PDE2MPAEBITS;
2000	#ifndef VBOX_FOR_DTRACE_LIB
2001	AssertCompileSize(X86PDE2MPAEBITS, 8);
2002	#endif
2003	/** Pointer to a 2MB PAE page table entry. */
2004	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2005	/** Pointer to a 2MB PAE page table entry. */
2006	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2007
2008	/** @} */
2009
2010	/**
2011	* Page directory entry.
2012	*/
2013	typedef union X86PDE
2014	{
2015	/** Unsigned integer view. */
2016	X86PGUINT u;
2017	/** Normal view. */
2018	X86PDEBITS n;
2019	/** 4MB view (big). */
2020	X86PDE4MBITS b;
2021	/** 8 bit unsigned integer view. */
2022	uint8_t au8[4];
2023	/** 16 bit unsigned integer view. */
2024	uint16_t au16[2];
2025	/** 32 bit unsigned integer view. */
2026	uint32_t au32[1];
2027	} X86PDE;
2028	#ifndef VBOX_FOR_DTRACE_LIB
2029	AssertCompileSize(X86PDE, 4);
2030	#endif
2031	/** Pointer to a page directory entry. */
2032	typedef X86PDE *PX86PDE;
2033	/** Pointer to a const page directory entry. */
2034	typedef const X86PDE *PCX86PDE;
2035
2036	/**
2037	* PAE page directory entry.
2038	*/
2039	typedef union X86PDEPAE
2040	{
2041	/** Unsigned integer view. */
2042	X86PGPAEUINT u;
2043	/** Normal view. */
2044	X86PDEPAEBITS n;
2045	/** 2MB page view (big). */
2046	X86PDE2MPAEBITS b;
2047	/** 8 bit unsigned integer view. */
2048	uint8_t au8[8];
2049	/** 16 bit unsigned integer view. */
2050	uint16_t au16[4];
2051	/** 32 bit unsigned integer view. */
2052	uint32_t au32[2];
2053	} X86PDEPAE;
2054	#ifndef VBOX_FOR_DTRACE_LIB
2055	AssertCompileSize(X86PDEPAE, 8);
2056	#endif
2057	/** Pointer to a page directory entry. */
2058	typedef X86PDEPAE *PX86PDEPAE;
2059	/** Pointer to a const page directory entry. */
2060	typedef const X86PDEPAE *PCX86PDEPAE;
2061
2062	/**
2063	* Page directory.
2064	*/
2065	typedef struct X86PD
2066	{
2067	/** PDE Array. */
2068	X86PDE a[X86_PG_ENTRIES];
2069	} X86PD;
2070	#ifndef VBOX_FOR_DTRACE_LIB
2071	AssertCompileSize(X86PD, 4096);
2072	#endif
2073	/** Pointer to a page directory. */
2074	typedef X86PD *PX86PD;
2075	/** Pointer to a const page directory. */
2076	typedef const X86PD *PCX86PD;
2077
2078	/** The page shift to get the PD index. */
2079	#define X86_PD_SHIFT 22
2080	/** The PD index mask (apply to a shifted page address). */
2081	#define X86_PD_MASK 0x3ff
2082
2083
2084	/**
2085	* PAE page directory.
2086	*/
2087	typedef struct X86PDPAE
2088	{
2089	/** PDE Array. */
2090	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2091	} X86PDPAE;
2092	#ifndef VBOX_FOR_DTRACE_LIB
2093	AssertCompileSize(X86PDPAE, 4096);
2094	#endif
2095	/** Pointer to a PAE page directory. */
2096	typedef X86PDPAE *PX86PDPAE;
2097	/** Pointer to a const PAE page directory. */
2098	typedef const X86PDPAE *PCX86PDPAE;
2099
2100	/** The page shift to get the PAE PD index. */
2101	#define X86_PD_PAE_SHIFT 21
2102	/** The PAE PD index mask (apply to a shifted page address). */
2103	#define X86_PD_PAE_MASK 0x1ff
2104
2105
2106	/** @name Page Directory Pointer Table Entry (PAE)
2107	* @{
2108	*/
2109	/** Bit 0 - P - Present bit. */
2110	#define X86_PDPE_P RT_BIT_32(0)
2111	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2112	#define X86_PDPE_RW RT_BIT_32(1)
2113	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2114	#define X86_PDPE_US RT_BIT_32(2)
2115	/** Bit 3 - PWT - Page level write thru bit. */
2116	#define X86_PDPE_PWT RT_BIT_32(3)
2117	/** Bit 4 - PCD - Page level cache disable bit. */
2118	#define X86_PDPE_PCD RT_BIT_32(4)
2119	/** Bit 5 - A - Access bit. Long Mode only. */
2120	#define X86_PDPE_A RT_BIT_32(5)
2121	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2122	#define X86_PDPE_LM_PS RT_BIT_32(7)
2123	/** Bits 9-11 - - Available for use to system software. */
2124	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2125	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2126	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2127	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2128	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2129	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2130	#define X86_PDPE_LM_NX RT_BIT_64(63)
2131	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2132	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2133	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2134	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2135	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2136	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2137	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2138	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2139
2140
2141	/**
2142	* Page directory pointer table entry.
2143	*/
2144	typedef struct X86PDPEBITS
2145	{
2146	/** Flags whether(=1) or not the page is present. */
2147	uint32_t u1Present : 1;
2148	/** Chunk of reserved bits. */
2149	uint32_t u2Reserved : 2;
2150	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2151	uint32_t u1WriteThru : 1;
2152	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2153	uint32_t u1CacheDisable : 1;
2154	/** Chunk of reserved bits. */
2155	uint32_t u4Reserved : 4;
2156	/** Available for use to system software. */
2157	uint32_t u3Available : 3;
2158	/** Physical Page number of the next level - Low Part. Don't use! */
2159	uint32_t u20PageNoLow : 20;
2160	/** Physical Page number of the next level - High Part. Don't use! */
2161	uint32_t u20PageNoHigh : 20;
2162	/** MBZ bits */
2163	uint32_t u12Reserved : 12;
2164	} X86PDPEBITS;
2165	#ifndef VBOX_FOR_DTRACE_LIB
2166	AssertCompileSize(X86PDPEBITS, 8);
2167	#endif
2168	/** Pointer to a page directory pointer table entry. */
2169	typedef X86PDPEBITS *PX86PTPEBITS;
2170	/** Pointer to a const page directory pointer table entry. */
2171	typedef const X86PDPEBITS *PCX86PTPEBITS;
2172
2173	/**
2174	* Page directory pointer table entry. AMD64 version
2175	*/
2176	typedef struct X86PDPEAMD64BITS
2177	{
2178	/** Flags whether(=1) or not the page is present. */
2179	uint32_t u1Present : 1;
2180	/** Read(=0) / Write(=1) flag. */
2181	uint32_t u1Write : 1;
2182	/** User(=1) / Supervisor (=0) flag. */
2183	uint32_t u1User : 1;
2184	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2185	uint32_t u1WriteThru : 1;
2186	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2187	uint32_t u1CacheDisable : 1;
2188	/** Accessed flag.
2189	* Indicates that the page have been read or written to. */
2190	uint32_t u1Accessed : 1;
2191	/** Chunk of reserved bits. */
2192	uint32_t u3Reserved : 3;
2193	/** Available for use to system software. */
2194	uint32_t u3Available : 3;
2195	/** Physical Page number of the next level - Low Part. Don't use! */
2196	uint32_t u20PageNoLow : 20;
2197	/** Physical Page number of the next level - High Part. Don't use! */
2198	uint32_t u20PageNoHigh : 20;
2199	/** MBZ bits */
2200	uint32_t u11Reserved : 11;
2201	/** No Execute flag. */
2202	uint32_t u1NoExecute : 1;
2203	} X86PDPEAMD64BITS;
2204	#ifndef VBOX_FOR_DTRACE_LIB
2205	AssertCompileSize(X86PDPEAMD64BITS, 8);
2206	#endif
2207	/** Pointer to a page directory pointer table entry. */
2208	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2209	/** Pointer to a const page directory pointer table entry. */
2210	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2211
2212	/**
2213	* Page directory pointer table entry.
2214	*/
2215	typedef union X86PDPE
2216	{
2217	/** Unsigned integer view. */
2218	X86PGPAEUINT u;
2219	/** Normal view. */
2220	X86PDPEBITS n;
2221	/** AMD64 view. */
2222	X86PDPEAMD64BITS lm;
2223	/** 8 bit unsigned integer view. */
2224	uint8_t au8[8];
2225	/** 16 bit unsigned integer view. */
2226	uint16_t au16[4];
2227	/** 32 bit unsigned integer view. */
2228	uint32_t au32[2];
2229	} X86PDPE;
2230	#ifndef VBOX_FOR_DTRACE_LIB
2231	AssertCompileSize(X86PDPE, 8);
2232	#endif
2233	/** Pointer to a page directory pointer table entry. */
2234	typedef X86PDPE *PX86PDPE;
2235	/** Pointer to a const page directory pointer table entry. */
2236	typedef const X86PDPE *PCX86PDPE;
2237
2238
2239	/**
2240	* Page directory pointer table.
2241	*/
2242	typedef struct X86PDPT
2243	{
2244	/** PDE Array. */
2245	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2246	} X86PDPT;
2247	#ifndef VBOX_FOR_DTRACE_LIB
2248	AssertCompileSize(X86PDPT, 4096);
2249	#endif
2250	/** Pointer to a page directory pointer table. */
2251	typedef X86PDPT *PX86PDPT;
2252	/** Pointer to a const page directory pointer table. */
2253	typedef const X86PDPT *PCX86PDPT;
2254
2255	/** The page shift to get the PDPT index. */
2256	#define X86_PDPT_SHIFT 30
2257	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2258	#define X86_PDPT_MASK_PAE 0x3
2259	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2260	#define X86_PDPT_MASK_AMD64 0x1ff
2261
2262	/** @} */
2263
2264
2265	/** @name Page Map Level-4 Entry (Long Mode PAE)
2266	* @{
2267	*/
2268	/** Bit 0 - P - Present bit. */
2269	#define X86_PML4E_P RT_BIT_32(0)
2270	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2271	#define X86_PML4E_RW RT_BIT_32(1)
2272	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2273	#define X86_PML4E_US RT_BIT_32(2)
2274	/** Bit 3 - PWT - Page level write thru bit. */
2275	#define X86_PML4E_PWT RT_BIT_32(3)
2276	/** Bit 4 - PCD - Page level cache disable bit. */
2277	#define X86_PML4E_PCD RT_BIT_32(4)
2278	/** Bit 5 - A - Access bit. */
2279	#define X86_PML4E_A RT_BIT_32(5)
2280	/** Bits 9-11 - - Available for use to system software. */
2281	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2282	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2283	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2284	/** Bits 8, 7 - - MBZ bits when NX is active. */
2285	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2286	/** Bits 63, 7 - - MBZ bits when no NX. */
2287	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2288	/** Bits 63 - NX - PAE - No execution flag. */
2289	#define X86_PML4E_NX RT_BIT_64(63)
2290
2291	/**
2292	* Page Map Level-4 Entry
2293	*/
2294	typedef struct X86PML4EBITS
2295	{
2296	/** Flags whether(=1) or not the page is present. */
2297	uint32_t u1Present : 1;
2298	/** Read(=0) / Write(=1) flag. */
2299	uint32_t u1Write : 1;
2300	/** User(=1) / Supervisor (=0) flag. */
2301	uint32_t u1User : 1;
2302	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2303	uint32_t u1WriteThru : 1;
2304	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2305	uint32_t u1CacheDisable : 1;
2306	/** Accessed flag.
2307	* Indicates that the page have been read or written to. */
2308	uint32_t u1Accessed : 1;
2309	/** Chunk of reserved bits. */
2310	uint32_t u3Reserved : 3;
2311	/** Available for use to system software. */
2312	uint32_t u3Available : 3;
2313	/** Physical Page number of the next level - Low Part. Don't use! */
2314	uint32_t u20PageNoLow : 20;
2315	/** Physical Page number of the next level - High Part. Don't use! */
2316	uint32_t u20PageNoHigh : 20;
2317	/** MBZ bits */
2318	uint32_t u11Reserved : 11;
2319	/** No Execute flag. */
2320	uint32_t u1NoExecute : 1;
2321	} X86PML4EBITS;
2322	#ifndef VBOX_FOR_DTRACE_LIB
2323	AssertCompileSize(X86PML4EBITS, 8);
2324	#endif
2325	/** Pointer to a page map level-4 entry. */
2326	typedef X86PML4EBITS *PX86PML4EBITS;
2327	/** Pointer to a const page map level-4 entry. */
2328	typedef const X86PML4EBITS *PCX86PML4EBITS;
2329
2330	/**
2331	* Page Map Level-4 Entry.
2332	*/
2333	typedef union X86PML4E
2334	{
2335	/** Unsigned integer view. */
2336	X86PGPAEUINT u;
2337	/** Normal view. */
2338	X86PML4EBITS n;
2339	/** 8 bit unsigned integer view. */
2340	uint8_t au8[8];
2341	/** 16 bit unsigned integer view. */
2342	uint16_t au16[4];
2343	/** 32 bit unsigned integer view. */
2344	uint32_t au32[2];
2345	} X86PML4E;
2346	#ifndef VBOX_FOR_DTRACE_LIB
2347	AssertCompileSize(X86PML4E, 8);
2348	#endif
2349	/** Pointer to a page map level-4 entry. */
2350	typedef X86PML4E *PX86PML4E;
2351	/** Pointer to a const page map level-4 entry. */
2352	typedef const X86PML4E *PCX86PML4E;
2353
2354
2355	/**
2356	* Page Map Level-4.
2357	*/
2358	typedef struct X86PML4
2359	{
2360	/** PDE Array. */
2361	X86PML4E a[X86_PG_PAE_ENTRIES];
2362	} X86PML4;
2363	#ifndef VBOX_FOR_DTRACE_LIB
2364	AssertCompileSize(X86PML4, 4096);
2365	#endif
2366	/** Pointer to a page map level-4. */
2367	typedef X86PML4 *PX86PML4;
2368	/** Pointer to a const page map level-4. */
2369	typedef const X86PML4 *PCX86PML4;
2370
2371	/** The page shift to get the PML4 index. */
2372	#define X86_PML4_SHIFT 39
2373	/** The PML4 index mask (apply to a shifted page address). */
2374	#define X86_PML4_MASK 0x1ff
2375
2376	/** @} */
2377
2378	/** @} */
2379
2380	/**
2381	* 32-bit protected mode FSTENV image.
2382	*/
2383	typedef struct X86FSTENV32P
2384	{
2385	uint16_t FCW;
2386	uint16_t padding1;
2387	uint16_t FSW;
2388	uint16_t padding2;
2389	uint16_t FTW;
2390	uint16_t padding3;
2391	uint32_t FPUIP;
2392	uint16_t FPUCS;
2393	uint16_t FOP;
2394	uint32_t FPUDP;
2395	uint16_t FPUDS;
2396	uint16_t padding4;
2397	} X86FSTENV32P;
2398	/** Pointer to a 32-bit protected mode FSTENV image. */
2399	typedef X86FSTENV32P *PX86FSTENV32P;
2400	/** Pointer to a const 32-bit protected mode FSTENV image. */
2401	typedef X86FSTENV32P const *PCX86FSTENV32P;
2402
2403
2404	/**
2405	* 80-bit MMX/FPU register type.
2406	*/
2407	typedef struct X86FPUMMX
2408	{
2409	uint8_t reg[10];
2410	} X86FPUMMX;
2411	#ifndef VBOX_FOR_DTRACE_LIB
2412	AssertCompileSize(X86FPUMMX, 10);
2413	#endif
2414	/** Pointer to a 80-bit MMX/FPU register type. */
2415	typedef X86FPUMMX *PX86FPUMMX;
2416	/** Pointer to a const 80-bit MMX/FPU register type. */
2417	typedef const X86FPUMMX *PCX86FPUMMX;
2418
2419	/** FPU (x87) register. */
2420	typedef union X86FPUREG
2421	{
2422	/** MMX view. */
2423	uint64_t mmx;
2424	/** FPU view - todo. */
2425	X86FPUMMX fpu;
2426	/** Extended precision floating point view. */
2427	RTFLOAT80U r80;
2428	/** Extended precision floating point view v2 */
2429	RTFLOAT80U2 r80Ex;
2430	/** 8-bit view. */
2431	uint8_t au8[16];
2432	/** 16-bit view. */
2433	uint16_t au16[8];
2434	/** 32-bit view. */
2435	uint32_t au32[4];
2436	/** 64-bit view. */
2437	uint64_t au64[2];
2438	/** 128-bit view. (yeah, very helpful) */
2439	uint128_t au128[1];
2440	} X86FPUREG;
2441	#ifndef VBOX_FOR_DTRACE_LIB
2442	AssertCompileSize(X86FPUREG, 16);
2443	#endif
2444	/** Pointer to a FPU register. */
2445	typedef X86FPUREG *PX86FPUREG;
2446	/** Pointer to a const FPU register. */
2447	typedef X86FPUREG const *PCX86FPUREG;
2448
2449	/**
2450	* XMM register union.
2451	*/
2452	typedef union X86XMMREG
2453	{
2454	/** XMM Register view . /
2455	uint128_t xmm;
2456	/** 8-bit view. */
2457	uint8_t au8[16];
2458	/** 16-bit view. */
2459	uint16_t au16[8];
2460	/** 32-bit view. */
2461	uint32_t au32[4];
2462	/** 64-bit view. */
2463	uint64_t au64[2];
2464	/** 128-bit view. (yeah, very helpful) */
2465	uint128_t au128[1];
2466	} X86XMMREG;
2467	#ifndef VBOX_FOR_DTRACE_LIB
2468	AssertCompileSize(X86XMMREG, 16);
2469	#endif
2470	/** Pointer to an XMM register state. */
2471	typedef X86XMMREG *PX86XMMREG;
2472	/** Pointer to a const XMM register state. */
2473	typedef X86XMMREG const *PCX86XMMREG;
2474
2475	/**
2476	* YMM register union.
2477	*/
2478	typedef union X86YMMREG
2479	{
2480	/** 8-bit view. */
2481	uint8_t au8[32];
2482	/** 16-bit view. */
2483	uint16_t au16[16];
2484	/** 32-bit view. */
2485	uint32_t au32[8];
2486	/** 64-bit view. */
2487	uint64_t au64[4];
2488	/** 128-bit view. (yeah, very helpful) */
2489	uint128_t au128[2];
2490	/** XMM sub register view. */
2491	X86XMMREG aXmm[2];
2492	} X86YMMREG;
2493	#ifndef VBOX_FOR_DTRACE_LIB
2494	AssertCompileSize(X86YMMREG, 32);
2495	#endif
2496	/** Pointer to an YMM register state. */
2497	typedef X86YMMREG *PX86YMMREG;
2498	/** Pointer to a const YMM register state. */
2499	typedef X86YMMREG const *PCX86YMMREG;
2500
2501	/**
2502	* ZMM register union.
2503	*/
2504	typedef union X86ZMMREG
2505	{
2506	/** 8-bit view. */
2507	uint8_t au8[64];
2508	/** 16-bit view. */
2509	uint16_t au16[32];
2510	/** 32-bit view. */
2511	uint32_t au32[16];
2512	/** 64-bit view. */
2513	uint64_t au64[8];
2514	/** 128-bit view. (yeah, very helpful) */
2515	uint128_t au128[4];
2516	/** XMM sub register view. */
2517	X86XMMREG aXmm[4];
2518	/** YMM sub register view. */
2519	X86YMMREG aYmm[2];
2520	} X86ZMMREG;
2521	#ifndef VBOX_FOR_DTRACE_LIB
2522	AssertCompileSize(X86ZMMREG, 64);
2523	#endif
2524	/** Pointer to an ZMM register state. */
2525	typedef X86ZMMREG *PX86ZMMREG;
2526	/** Pointer to a const ZMM register state. */
2527	typedef X86ZMMREG const *PCX86ZMMREG;
2528
2529
2530	/**
2531	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2532	* @todo verify this...
2533	*/
2534	#pragma pack(1)
2535	typedef struct X86FPUSTATE
2536	{
2537	/** 0x00 - Control word. */
2538	uint16_t FCW;
2539	/** 0x02 - Alignment word */
2540	uint16_t Dummy1;
2541	/** 0x04 - Status word. */
2542	uint16_t FSW;
2543	/** 0x06 - Alignment word */
2544	uint16_t Dummy2;
2545	/** 0x08 - Tag word */
2546	uint16_t FTW;
2547	/** 0x0a - Alignment word */
2548	uint16_t Dummy3;
2549
2550	/** 0x0c - Instruction pointer. */
2551	uint32_t FPUIP;
2552	/** 0x10 - Code selector. */
2553	uint16_t CS;
2554	/** 0x12 - Opcode. */
2555	uint16_t FOP;
2556	/** 0x14 - FOO. */
2557	uint32_t FPUOO;
2558	/** 0x18 - FOS. */
2559	uint32_t FPUOS;
2560	/** 0x1c - FPU register. */
2561	X86FPUREG regs[8];
2562	} X86FPUSTATE;
2563	#pragma pack()
2564	/** Pointer to a FPU state. */
2565	typedef X86FPUSTATE *PX86FPUSTATE;
2566	/** Pointer to a const FPU state. */
2567	typedef const X86FPUSTATE *PCX86FPUSTATE;
2568
2569	/**
2570	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2571	*/
2572	#pragma pack(1)
2573	typedef struct X86FXSTATE
2574	{
2575	/** 0x00 - Control word. */
2576	uint16_t FCW;
2577	/** 0x02 - Status word. */
2578	uint16_t FSW;
2579	/** 0x04 - Tag word. (The upper byte is always zero.) */
2580	uint16_t FTW;
2581	/** 0x06 - Opcode. */
2582	uint16_t FOP;
2583	/** 0x08 - Instruction pointer. */
2584	uint32_t FPUIP;
2585	/** 0x0c - Code selector. */
2586	uint16_t CS;
2587	uint16_t Rsrvd1;
2588	/** 0x10 - Data pointer. */
2589	uint32_t FPUDP;
2590	/** 0x14 - Data segment */
2591	uint16_t DS;
2592	/** 0x16 */
2593	uint16_t Rsrvd2;
2594	/** 0x18 */
2595	uint32_t MXCSR;
2596	/** 0x1c */
2597	uint32_t MXCSR_MASK;
2598	/** 0x20 - FPU registers. */
2599	X86FPUREG aRegs[8];
2600	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
2601	X86XMMREG aXMM[16];
2602	/* - offset 416 - */
2603	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2604	/* - offset 464 - Software usable reserved bits. */
2605	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2606	} X86FXSTATE;
2607	#pragma pack()
2608	/** Pointer to a FPU Extended state. */
2609	typedef X86FXSTATE *PX86FXSTATE;
2610	/** Pointer to a const FPU Extended state. */
2611	typedef const X86FXSTATE *PCX86FXSTATE;
2612
2613	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2614	* magic. Don't forget to update x86.mac if you change this! */
2615	#define X86_OFF_FXSTATE_RSVD 0x1d0
2616	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2617	* forget to update x86.mac if you change this!
2618	* @todo r=bird: This has nothing what-so-ever to do here.... */
2619	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2620	#ifndef VBOX_FOR_DTRACE_LIB
2621	AssertCompileSize(X86FXSTATE, 512);
2622	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2623	#endif
2624
2625	/** @name FPU status word flags.
2626	* @{ */
2627	/** Exception Flag: Invalid operation. */
2628	#define X86_FSW_IE RT_BIT_32(0)
2629	/** Exception Flag: Denormalized operand. */
2630	#define X86_FSW_DE RT_BIT_32(1)
2631	/** Exception Flag: Zero divide. */
2632	#define X86_FSW_ZE RT_BIT_32(2)
2633	/** Exception Flag: Overflow. */
2634	#define X86_FSW_OE RT_BIT_32(3)
2635	/** Exception Flag: Underflow. */
2636	#define X86_FSW_UE RT_BIT_32(4)
2637	/** Exception Flag: Precision. */
2638	#define X86_FSW_PE RT_BIT_32(5)
2639	/** Stack fault. */
2640	#define X86_FSW_SF RT_BIT_32(6)
2641	/** Error summary status. */
2642	#define X86_FSW_ES RT_BIT_32(7)
2643	/** Mask of exceptions flags, excluding the summary bit. */
2644	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2645	/** Mask of exceptions flags, including the summary bit. */
2646	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2647	/** Condition code 0. */
2648	#define X86_FSW_C0 RT_BIT_32(8)
2649	/** Condition code 1. */
2650	#define X86_FSW_C1 RT_BIT_32(9)
2651	/** Condition code 2. */
2652	#define X86_FSW_C2 RT_BIT_32(10)
2653	/** Top of the stack mask. */
2654	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2655	/** TOP shift value. */
2656	#define X86_FSW_TOP_SHIFT 11
2657	/** Mask for getting TOP value after shifting it right. */
2658	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2659	/** Get the TOP value. */
2660	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2661	/** Condition code 3. */
2662	#define X86_FSW_C3 RT_BIT_32(14)
2663	/** Mask of exceptions flags, including the summary bit. */
2664	#define X86_FSW_C_MASK UINT16_C(0x4700)
2665	/** FPU busy. */
2666	#define X86_FSW_B RT_BIT_32(15)
2667	/** @} */
2668
2669
2670	/** @name FPU control word flags.
2671	* @{ */
2672	/** Exception Mask: Invalid operation. */
2673	#define X86_FCW_IM RT_BIT_32(0)
2674	/** Exception Mask: Denormalized operand. */
2675	#define X86_FCW_DM RT_BIT_32(1)
2676	/** Exception Mask: Zero divide. */
2677	#define X86_FCW_ZM RT_BIT_32(2)
2678	/** Exception Mask: Overflow. */
2679	#define X86_FCW_OM RT_BIT_32(3)
2680	/** Exception Mask: Underflow. */
2681	#define X86_FCW_UM RT_BIT_32(4)
2682	/** Exception Mask: Precision. */
2683	#define X86_FCW_PM RT_BIT_32(5)
2684	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2685	* @remarks This includes reserved bit 6. */
2686	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2687	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2688	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2689	/** Precision control mask. */
2690	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2691	/** Precision control: 24-bit. */
2692	#define X86_FCW_PC_24 UINT16_C(0x0000)
2693	/** Precision control: Reserved. */
2694	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2695	/** Precision control: 53-bit. */
2696	#define X86_FCW_PC_53 UINT16_C(0x0200)
2697	/** Precision control: 64-bit. */
2698	#define X86_FCW_PC_64 UINT16_C(0x0300)
2699	/** Rounding control mask. */
2700	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2701	/** Rounding control: To nearest. */
2702	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2703	/** Rounding control: Down. */
2704	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2705	/** Rounding control: Up. */
2706	#define X86_FCW_RC_UP UINT16_C(0x0800)
2707	/** Rounding control: Towards zero. */
2708	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2709	/** Bits which should be zero, apparently. */
2710	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2711	/** @} */
2712
2713	/** @name SSE MXCSR
2714	* @{ */
2715	/** Exception Flag: Invalid operation. */
2716	#define X86_MXSCR_IE RT_BIT_32(0)
2717	/** Exception Flag: Denormalized operand. */
2718	#define X86_MXSCR_DE RT_BIT_32(1)
2719	/** Exception Flag: Zero divide. */
2720	#define X86_MXSCR_ZE RT_BIT_32(2)
2721	/** Exception Flag: Overflow. */
2722	#define X86_MXSCR_OE RT_BIT_32(3)
2723	/** Exception Flag: Underflow. */
2724	#define X86_MXSCR_UE RT_BIT_32(4)
2725	/** Exception Flag: Precision. */
2726	#define X86_MXSCR_PE RT_BIT_32(5)
2727
2728	/** Denormals are zero. */
2729	#define X86_MXSCR_DAZ RT_BIT_32(6)
2730
2731	/** Exception Mask: Invalid operation. */
2732	#define X86_MXSCR_IM RT_BIT_32(7)
2733	/** Exception Mask: Denormalized operand. */
2734	#define X86_MXSCR_DM RT_BIT_32(8)
2735	/** Exception Mask: Zero divide. */
2736	#define X86_MXSCR_ZM RT_BIT_32(9)
2737	/** Exception Mask: Overflow. */
2738	#define X86_MXSCR_OM RT_BIT_32(10)
2739	/** Exception Mask: Underflow. */
2740	#define X86_MXSCR_UM RT_BIT_32(11)
2741	/** Exception Mask: Precision. */
2742	#define X86_MXSCR_PM RT_BIT_32(12)
2743
2744	/** Rounding control mask. */
2745	#define X86_MXSCR_RC_MASK UINT16_C(0x6000)
2746	/** Rounding control: To nearest. */
2747	#define X86_MXSCR_RC_NEAREST UINT16_C(0x0000)
2748	/** Rounding control: Down. */
2749	#define X86_MXSCR_RC_DOWN UINT16_C(0x2000)
2750	/** Rounding control: Up. */
2751	#define X86_MXSCR_RC_UP UINT16_C(0x4000)
2752	/** Rounding control: Towards zero. */
2753	#define X86_MXSCR_RC_ZERO UINT16_C(0x6000)
2754
2755	/** Flush-to-zero for masked underflow. */
2756	#define X86_MXSCR_FZ RT_BIT_32(15)
2757
2758	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
2759	#define X86_MXSCR_MM RT_BIT_32(17)
2760	/** @} */
2761
2762	/**
2763	* XSAVE header.
2764	*/
2765	typedef struct X86XSAVEHDR
2766	{
2767	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
2768	uint64_t bmXState;
2769	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
2770	uint64_t bmXComp;
2771	/** Reserved for furture extensions, probably MBZ. */
2772	uint64_t au64Reserved[6];
2773	} X86XSAVEHDR;
2774	#ifndef VBOX_FOR_DTRACE_LIB
2775	AssertCompileSize(X86XSAVEHDR, 64);
2776	#endif
2777	/** Pointer to an XSAVE header. */
2778	typedef X86XSAVEHDR *PX86XSAVEHDR;
2779	/** Pointer to a const XSAVE header. */
2780	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
2781
2782
2783	/**
2784	* The high 128-bit YMM register state (XSAVE_C_YMM).
2785	* (The lower 128-bits being in X86FXSTATE.)
2786	*/
2787	typedef struct X86XSAVEYMMHI
2788	{
2789	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
2790	X86XMMREG aYmmHi[16];
2791	} X86XSAVEYMMHI;
2792	#ifndef VBOX_FOR_DTRACE_LIB
2793	AssertCompileSize(X86XSAVEYMMHI, 256);
2794	#endif
2795	/** Pointer to a high 128-bit YMM register state. */
2796	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
2797	/** Pointer to a const high 128-bit YMM register state. */
2798	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
2799
2800	/**
2801	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
2802	*/
2803	typedef struct X86XSAVEBNDREGS
2804	{
2805	/** Array of registers (BND0...BND3). */
2806	struct
2807	{
2808	/** Lower bound. */
2809	uint64_t uLowerBound;
2810	/** Upper bound. */
2811	uint64_t uUpperBound;
2812	} aRegs[4];
2813	} X86XSAVEBNDREGS;
2814	#ifndef VBOX_FOR_DTRACE_LIB
2815	AssertCompileSize(X86XSAVEBNDREGS, 64);
2816	#endif
2817	/** Pointer to a MPX bound register state. */
2818	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
2819	/** Pointer to a const MPX bound register state. */
2820	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
2821
2822	/**
2823	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
2824	*/
2825	typedef struct X86XSAVEBNDCFG
2826	{
2827	uint64_t fConfig;
2828	uint64_t fStatus;
2829	} X86XSAVEBNDCFG;
2830	#ifndef VBOX_FOR_DTRACE_LIB
2831	AssertCompileSize(X86XSAVEBNDCFG, 16);
2832	#endif
2833	/** Pointer to a MPX bound config and status register state. */
2834	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
2835	/** Pointer to a const MPX bound config and status register state. */
2836	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
2837
2838	/**
2839	* AVX-512 opmask state (XSAVE_C_OPMASK).
2840	*/
2841	typedef struct X86XSAVEOPMASK
2842	{
2843	/** The K0..K7 values. */
2844	uint64_t aKRegs[8];
2845	} X86XSAVEOPMASK;
2846	#ifndef VBOX_FOR_DTRACE_LIB
2847	AssertCompileSize(X86XSAVEOPMASK, 64);
2848	#endif
2849	/** Pointer to a AVX-512 opmask state. */
2850	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
2851	/** Pointer to a const AVX-512 opmask state. */
2852	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
2853
2854	/**
2855	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
2856	*/
2857	typedef struct X86XSAVEZMMHI256
2858	{
2859	/** Upper 256-bits of ZMM0-15. */
2860	X86YMMREG aHi256Regs[16];
2861	} X86XSAVEZMMHI256;
2862	#ifndef VBOX_FOR_DTRACE_LIB
2863	AssertCompileSize(X86XSAVEZMMHI256, 512);
2864	#endif
2865	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
2866	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
2867	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
2868	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
2869
2870	/**
2871	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
2872	*/
2873	typedef struct X86XSAVEZMM16HI
2874	{
2875	/** ZMM16 thru ZMM31. */
2876	X86ZMMREG aRegs[16];
2877	} X86XSAVEZMM16HI;
2878	#ifndef VBOX_FOR_DTRACE_LIB
2879	AssertCompileSize(X86XSAVEZMM16HI, 1024);
2880	#endif
2881	/** Pointer to a state comprising ZMM16-32. */
2882	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
2883	/** Pointer to a const state comprising ZMM16-32. */
2884	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
2885
2886	/**
2887	* AMD Light weight profiling state (XSAVE_C_LWP).
2888	*
2889	* We probably won't play with this as AMD seems to be dropping from their "zen"
2890	* processor micro architecture.
2891	*/
2892	typedef struct X86XSAVELWP
2893	{
2894	/** Details when needed. */
2895	uint64_t auLater[128/8];
2896	} X86XSAVELWP;
2897	#ifndef VBOX_FOR_DTRACE_LIB
2898	AssertCompileSize(X86XSAVELWP, 128);
2899	#endif
2900
2901
2902	/**
2903	* x86 FPU/SSE/AVX/XXXX state.
2904	*
2905	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
2906	* changes to this structure.
2907	*/
2908	typedef struct X86XSAVEAREA
2909	{
2910	/** The x87 and SSE region (or legacy region if you like). */
2911	X86FXSTATE x87;
2912	/** The XSAVE header. */
2913	X86XSAVEHDR Hdr;
2914	/** Beyond the header, there isn't really a fixed layout, but we can
2915	generally assume the YMM (AVX) register extensions are present and
2916	follows immediately. */
2917	union
2918	{
2919	/** This is a typical layout on intel CPUs (good for debuggers). */
2920	struct
2921	{
2922	X86XSAVEYMMHI YmmHi;
2923	X86XSAVEBNDREGS BndRegs;
2924	X86XSAVEBNDCFG BndCfg;
2925	uint8_t abFudgeToMatchDocs[0xB0];
2926	X86XSAVEOPMASK Opmask;
2927	X86XSAVEZMMHI256 ZmmHi256;
2928	X86XSAVEZMM16HI Zmm16Hi;
2929	} Intel;
2930
2931	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
2932	struct
2933	{
2934	X86XSAVEYMMHI YmmHi;
2935	X86XSAVELWP Lwp;
2936	} AmdBd;
2937
2938	/** To enbling static deployments that have a reasonable chance of working for
2939	* the next 3-6 CPU generations without running short on space, we allocate a
2940	* lot of extra space here, making the structure a round 8KB in size. This
2941	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
2942	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
2943	uint8_t ab[8192 - 512 - 64];
2944	} u;
2945	} X86XSAVEAREA;
2946	#ifndef VBOX_FOR_DTRACE_LIB
2947	AssertCompileSize(X86XSAVEAREA, 8192);
2948	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
2949	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
2950	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
2951	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
2952	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
2953	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
2954	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
2955	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
2956	#endif
2957	/** Pointer to a XSAVE area. */
2958	typedef X86XSAVEAREA *PX86XSAVEAREA;
2959	/** Pointer to a const XSAVE area. */
2960	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
2961
2962
2963	/** @name XSAVE_C_XXX - XSAVE State Components Bits.
2964	* @{ */
2965	/** Bit 0 - x87 - Legacy FPU state (bit number) */
2966	#define XSAVE_C_X87_BIT 0
2967	/** Bit 0 - x87 - Legacy FPU state. */
2968	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
2969	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
2970	#define XSAVE_C_SSE_BIT 1
2971	/** Bit 1 - SSE - 128-bit SSE state. */
2972	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
2973	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
2974	#define XSAVE_C_YMM_BIT 2
2975	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
2976	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
2977	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
2978	#define XSAVE_C_BNDREGS_BIT 3
2979	/** Bit 3 - BNDREGS - MPX bound register state. */
2980	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
2981	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
2982	#define XSAVE_C_BNDCSR_BIT 4
2983	/** Bit 4 - BNDCSR - MPX bound config and status state. */
2984	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
2985	/** Bit 5 - Opmask - opmask state (bit number). */
2986	#define XSAVE_C_OPMASK_BIT 5
2987	/** Bit 5 - Opmask - opmask state. */
2988	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
2989	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
2990	#define XSAVE_C_ZMM_HI256_BIT 6
2991	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
2992	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
2993	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
2994	#define XSAVE_C_ZMM_16HI_BIT 7
2995	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
2996	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
2997	/** Bit 9 - PKRU - Protection-key state (bit number). */
2998	#define XSAVE_C_PKRU_BIT 9
2999	/** Bit 9 - PKRU - Protection-key state. */
3000	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3001	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3002	#define XSAVE_C_LWP_BIT 62
3003	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3004	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3005	/** @} */
3006
3007
3008
3009	/** @name Selector Descriptor
3010	* @{
3011	*/
3012
3013	#ifndef VBOX_FOR_DTRACE_LIB
3014	/**
3015	* Descriptor attributes (as seen by VT-x).
3016	*/
3017	typedef struct X86DESCATTRBITS
3018	{
3019	/** 00 - Segment Type. */
3020	unsigned u4Type : 4;
3021	/** 04 - Descriptor Type. System(=0) or code/data selector */
3022	unsigned u1DescType : 1;
3023	/** 05 - Descriptor Privilege level. */
3024	unsigned u2Dpl : 2;
3025	/** 07 - Flags selector present(=1) or not. */
3026	unsigned u1Present : 1;
3027	/** 08 - Segment limit 16-19. */
3028	unsigned u4LimitHigh : 4;
3029	/** 0c - Available for system software. */
3030	unsigned u1Available : 1;
3031	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3032	unsigned u1Long : 1;
3033	/** 0e - This flags meaning depends on the segment type. Try make sense out
3034	* of the intel manual yourself. */
3035	unsigned u1DefBig : 1;
3036	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
3037	* clear byte. */
3038	unsigned u1Granularity : 1;
3039	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3040	unsigned u1Unusable : 1;
3041	} X86DESCATTRBITS;
3042	#endif /* !VBOX_FOR_DTRACE_LIB */
3043
3044	/** @name X86DESCATTR masks
3045	* @{ */
3046	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3047	#define X86DESCATTR_DT UINT32_C(0x00000010)
3048	#define X86DESCATTR_DPL UINT32_C(0x00000060)
3049	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
3050	#define X86DESCATTR_P UINT32_C(0x00000080)
3051	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3052	#define X86DESCATTR_AVL UINT32_C(0x00001000)
3053	#define X86DESCATTR_L UINT32_C(0x00002000)
3054	#define X86DESCATTR_D UINT32_C(0x00004000)
3055	#define X86DESCATTR_G UINT32_C(0x00008000)
3056	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3057	/** @} */
3058
3059	#pragma pack(1)
3060	typedef union X86DESCATTR
3061	{
3062	/** Unsigned integer view. */
3063	uint32_t u;
3064	#ifndef VBOX_FOR_DTRACE_LIB
3065	/** Normal view. */
3066	X86DESCATTRBITS n;
3067	#endif
3068	} X86DESCATTR;
3069	#pragma pack()
3070	/** Pointer to descriptor attributes. */
3071	typedef X86DESCATTR *PX86DESCATTR;
3072	/** Pointer to const descriptor attributes. */
3073	typedef const X86DESCATTR *PCX86DESCATTR;
3074
3075	#ifndef VBOX_FOR_DTRACE_LIB
3076
3077	/**
3078	* Generic descriptor table entry
3079	*/
3080	#pragma pack(1)
3081	typedef struct X86DESCGENERIC
3082	{
3083	/** 00 - Limit - Low word. */
3084	unsigned u16LimitLow : 16;
3085	/** 10 - Base address - lowe word.
3086	* Don't try set this to 24 because MSC is doing stupid things then. */
3087	unsigned u16BaseLow : 16;
3088	/** 20 - Base address - first 8 bits of high word. */
3089	unsigned u8BaseHigh1 : 8;
3090	/** 28 - Segment Type. */
3091	unsigned u4Type : 4;
3092	/** 2c - Descriptor Type. System(=0) or code/data selector */
3093	unsigned u1DescType : 1;
3094	/** 2d - Descriptor Privilege level. */
3095	unsigned u2Dpl : 2;
3096	/** 2f - Flags selector present(=1) or not. */
3097	unsigned u1Present : 1;
3098	/** 30 - Segment limit 16-19. */
3099	unsigned u4LimitHigh : 4;
3100	/** 34 - Available for system software. */
3101	unsigned u1Available : 1;
3102	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3103	unsigned u1Long : 1;
3104	/** 36 - This flags meaning depends on the segment type. Try make sense out
3105	* of the intel manual yourself. */
3106	unsigned u1DefBig : 1;
3107	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
3108	* clear byte. */
3109	unsigned u1Granularity : 1;
3110	/** 38 - Base address - highest 8 bits. */
3111	unsigned u8BaseHigh2 : 8;
3112	} X86DESCGENERIC;
3113	#pragma pack()
3114	/** Pointer to a generic descriptor entry. */
3115	typedef X86DESCGENERIC *PX86DESCGENERIC;
3116	/** Pointer to a const generic descriptor entry. */
3117	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3118
3119	/** @name Bit offsets of X86DESCGENERIC members.
3120	* @{*/
3121	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
3122	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
3123	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
3124	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
3125	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
3126	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
3127	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
3128	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
3129	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
3130	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
3131	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
3132	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
3133	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
3134	/** @} */
3135
3136	/**
3137	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3138	*/
3139	typedef struct X86DESCGATE
3140	{
3141	/** 00 - Target code segment offset - Low word.
3142	* Ignored if task-gate. */
3143	unsigned u16OffsetLow : 16;
3144	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3145	* TSS selector if task-gate. */
3146	unsigned u16Sel : 16;
3147	/** 20 - Number of parameters for a call-gate.
3148	* Ignored if interrupt-, trap- or task-gate. */
3149	unsigned u4ParmCount : 4;
3150	/** 24 - Reserved / ignored. */
3151	unsigned u4Reserved : 4;
3152	/** 28 - Segment Type. */
3153	unsigned u4Type : 4;
3154	/** 2c - Descriptor Type (0 = system). */
3155	unsigned u1DescType : 1;
3156	/** 2d - Descriptor Privilege level. */
3157	unsigned u2Dpl : 2;
3158	/** 2f - Flags selector present(=1) or not. */
3159	unsigned u1Present : 1;
3160	/** 30 - Target code segment offset - High word.
3161	* Ignored if task-gate. */
3162	unsigned u16OffsetHigh : 16;
3163	} X86DESCGATE;
3164	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3165	typedef X86DESCGATE *PX86DESCGATE;
3166	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3167	typedef const X86DESCGATE *PCX86DESCGATE;
3168
3169	#endif /* VBOX_FOR_DTRACE_LIB */
3170
3171	/**
3172	* Descriptor table entry.
3173	*/
3174	#pragma pack(1)
3175	typedef union X86DESC
3176	{
3177	#ifndef VBOX_FOR_DTRACE_LIB
3178	/** Generic descriptor view. */
3179	X86DESCGENERIC Gen;
3180	/** Gate descriptor view. */
3181	X86DESCGATE Gate;
3182	#endif
3183
3184	/** 8 bit unsigned integer view. */
3185	uint8_t au8[8];
3186	/** 16 bit unsigned integer view. */
3187	uint16_t au16[4];
3188	/** 32 bit unsigned integer view. */
3189	uint32_t au32[2];
3190	/** 64 bit unsigned integer view. */
3191	uint64_t au64[1];
3192	/** Unsigned integer view. */
3193	uint64_t u;
3194	} X86DESC;
3195	#ifndef VBOX_FOR_DTRACE_LIB
3196	AssertCompileSize(X86DESC, 8);
3197	#endif
3198	#pragma pack()
3199	/** Pointer to descriptor table entry. */
3200	typedef X86DESC *PX86DESC;
3201	/** Pointer to const descriptor table entry. */
3202	typedef const X86DESC *PCX86DESC;
3203
3204	/** @def X86DESC_BASE
3205	* Return the base address of a descriptor.
3206	*/
3207	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
3208	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3209	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3210	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3211
3212	/** @def X86DESC_LIMIT
3213	* Return the limit of a descriptor.
3214	*/
3215	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
3216	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3217	\| ( (a_pDesc)->Gen.u16LimitLow ) )
3218
3219	/** @def X86DESC_LIMIT_G
3220	* Return the limit of a descriptor with the granularity bit taken into account.
3221	* @returns Selector limit (uint32_t).
3222	* @param a_pDesc Pointer to the descriptor.
3223	*/
3224	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
3225	( (a_pDesc)->Gen.u1Granularity \
3226	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
3227	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
3228	)
3229
3230	/** @def X86DESC_GET_HID_ATTR
3231	* Get the descriptor attributes for the hidden register.
3232	*/
3233	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
3234	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3235
3236	#ifndef VBOX_FOR_DTRACE_LIB
3237
3238	/**
3239	* 64 bits generic descriptor table entry
3240	* Note: most of these bits have no meaning in long mode.
3241	*/
3242	#pragma pack(1)
3243	typedef struct X86DESC64GENERIC
3244	{
3245	/** Limit - Low word - IGNORED. */
3246	uint32_t u16LimitLow : 16;
3247	/** Base address - low word. - IGNORED
3248	* Don't try set this to 24 because MSC is doing stupid things then. */
3249	uint32_t u16BaseLow : 16;
3250	/** Base address - first 8 bits of high word. - IGNORED */
3251	uint32_t u8BaseHigh1 : 8;
3252	/** Segment Type. */
3253	uint32_t u4Type : 4;
3254	/** Descriptor Type. System(=0) or code/data selector */
3255	uint32_t u1DescType : 1;
3256	/** Descriptor Privilege level. */
3257	uint32_t u2Dpl : 2;
3258	/** Flags selector present(=1) or not. */
3259	uint32_t u1Present : 1;
3260	/** Segment limit 16-19. - IGNORED */
3261	uint32_t u4LimitHigh : 4;
3262	/** Available for system software. - IGNORED */
3263	uint32_t u1Available : 1;
3264	/** Long mode flag. */
3265	uint32_t u1Long : 1;
3266	/** This flags meaning depends on the segment type. Try make sense out
3267	* of the intel manual yourself. */
3268	uint32_t u1DefBig : 1;
3269	/** Granularity of the limit. If set 4KB granularity is used, if
3270	* clear byte. - IGNORED */
3271	uint32_t u1Granularity : 1;
3272	/** Base address - highest 8 bits. - IGNORED */
3273	uint32_t u8BaseHigh2 : 8;
3274	/** Base address - bits 63-32. */
3275	uint32_t u32BaseHigh3 : 32;
3276	uint32_t u8Reserved : 8;
3277	uint32_t u5Zeros : 5;
3278	uint32_t u19Reserved : 19;
3279	} X86DESC64GENERIC;
3280	#pragma pack()
3281	/** Pointer to a generic descriptor entry. */
3282	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3283	/** Pointer to a const generic descriptor entry. */
3284	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3285
3286	/**
3287	* System descriptor table entry (64 bits)
3288	*
3289	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3290	*/
3291	#pragma pack(1)
3292	typedef struct X86DESC64SYSTEM
3293	{
3294	/** Limit - Low word. */
3295	uint32_t u16LimitLow : 16;
3296	/** Base address - lowe word.
3297	* Don't try set this to 24 because MSC is doing stupid things then. */
3298	uint32_t u16BaseLow : 16;
3299	/** Base address - first 8 bits of high word. */
3300	uint32_t u8BaseHigh1 : 8;
3301	/** Segment Type. */
3302	uint32_t u4Type : 4;
3303	/** Descriptor Type. System(=0) or code/data selector */
3304	uint32_t u1DescType : 1;
3305	/** Descriptor Privilege level. */
3306	uint32_t u2Dpl : 2;
3307	/** Flags selector present(=1) or not. */
3308	uint32_t u1Present : 1;
3309	/** Segment limit 16-19. */
3310	uint32_t u4LimitHigh : 4;
3311	/** Available for system software. */
3312	uint32_t u1Available : 1;
3313	/** Reserved - 0. */
3314	uint32_t u1Reserved : 1;
3315	/** This flags meaning depends on the segment type. Try make sense out
3316	* of the intel manual yourself. */
3317	uint32_t u1DefBig : 1;
3318	/** Granularity of the limit. If set 4KB granularity is used, if
3319	* clear byte. */
3320	uint32_t u1Granularity : 1;
3321	/** Base address - bits 31-24. */
3322	uint32_t u8BaseHigh2 : 8;
3323	/** Base address - bits 63-32. */
3324	uint32_t u32BaseHigh3 : 32;
3325	uint32_t u8Reserved : 8;
3326	uint32_t u5Zeros : 5;
3327	uint32_t u19Reserved : 19;
3328	} X86DESC64SYSTEM;
3329	#pragma pack()
3330	/** Pointer to a system descriptor entry. */
3331	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3332	/** Pointer to a const system descriptor entry. */
3333	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3334
3335	/**
3336	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3337	*/
3338	typedef struct X86DESC64GATE
3339	{
3340	/** Target code segment offset - Low word. */
3341	uint32_t u16OffsetLow : 16;
3342	/** Target code segment selector. */
3343	uint32_t u16Sel : 16;
3344	/** Interrupt stack table for interrupt- and trap-gates.
3345	* Ignored by call-gates. */
3346	uint32_t u3IST : 3;
3347	/** Reserved / ignored. */
3348	uint32_t u5Reserved : 5;
3349	/** Segment Type. */
3350	uint32_t u4Type : 4;
3351	/** Descriptor Type (0 = system). */
3352	uint32_t u1DescType : 1;
3353	/** Descriptor Privilege level. */
3354	uint32_t u2Dpl : 2;
3355	/** Flags selector present(=1) or not. */
3356	uint32_t u1Present : 1;
3357	/** Target code segment offset - High word.
3358	* Ignored if task-gate. */
3359	uint32_t u16OffsetHigh : 16;
3360	/** Target code segment offset - Top dword.
3361	* Ignored if task-gate. */
3362	uint32_t u32OffsetTop : 32;
3363	/** Reserved / ignored / must be zero.
3364	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3365	uint32_t u32Reserved : 32;
3366	} X86DESC64GATE;
3367	AssertCompileSize(X86DESC64GATE, 16);
3368	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3369	typedef X86DESC64GATE *PX86DESC64GATE;
3370	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3371	typedef const X86DESC64GATE *PCX86DESC64GATE;
3372
3373	#endif /* VBOX_FOR_DTRACE_LIB */
3374
3375	/**
3376	* Descriptor table entry.
3377	*/
3378	#pragma pack(1)
3379	typedef union X86DESC64
3380	{
3381	#ifndef VBOX_FOR_DTRACE_LIB
3382	/** Generic descriptor view. */
3383	X86DESC64GENERIC Gen;
3384	/** System descriptor view. */
3385	X86DESC64SYSTEM System;
3386	/** Gate descriptor view. */
3387	X86DESC64GATE Gate;
3388	#endif
3389
3390	/** 8 bit unsigned integer view. */
3391	uint8_t au8[16];
3392	/** 16 bit unsigned integer view. */
3393	uint16_t au16[8];
3394	/** 32 bit unsigned integer view. */
3395	uint32_t au32[4];
3396	/** 64 bit unsigned integer view. */
3397	uint64_t au64[2];
3398	} X86DESC64;
3399	#ifndef VBOX_FOR_DTRACE_LIB
3400	AssertCompileSize(X86DESC64, 16);
3401	#endif
3402	#pragma pack()
3403	/** Pointer to descriptor table entry. */
3404	typedef X86DESC64 *PX86DESC64;
3405	/** Pointer to const descriptor table entry. */
3406	typedef const X86DESC64 *PCX86DESC64;
3407
3408	/** @def X86DESC64_BASE
3409	* Return the base of a 64-bit descriptor.
3410	*/
3411	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
3412	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3413	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3414	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3415	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3416
3417
3418
3419	/** @name Host system descriptor table entry - Use with care!
3420	* @{ */
3421	/** Host system descriptor table entry. */
3422	#if HC_ARCH_BITS == 64
3423	typedef X86DESC64 X86DESCHC;
3424	#else
3425	typedef X86DESC X86DESCHC;
3426	#endif
3427	/** Pointer to a host system descriptor table entry. */
3428	#if HC_ARCH_BITS == 64
3429	typedef PX86DESC64 PX86DESCHC;
3430	#else
3431	typedef PX86DESC PX86DESCHC;
3432	#endif
3433	/** Pointer to a const host system descriptor table entry. */
3434	#if HC_ARCH_BITS == 64
3435	typedef PCX86DESC64 PCX86DESCHC;
3436	#else
3437	typedef PCX86DESC PCX86DESCHC;
3438	#endif
3439	/** @} */
3440
3441
3442	/** @name Selector Descriptor Types.
3443	* @{
3444	*/
3445
3446	/** @name Non-System Selector Types.
3447	* @{ */
3448	/** Code(=set)/Data(=clear) bit. */
3449	#define X86_SEL_TYPE_CODE 8
3450	/** Memory(=set)/System(=clear) bit. */
3451	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3452	/** Accessed bit. */
3453	#define X86_SEL_TYPE_ACCESSED 1
3454	/** Expand down bit (for data selectors only). */
3455	#define X86_SEL_TYPE_DOWN 4
3456	/** Conforming bit (for code selectors only). */
3457	#define X86_SEL_TYPE_CONF 4
3458	/** Write bit (for data selectors only). */
3459	#define X86_SEL_TYPE_WRITE 2
3460	/** Read bit (for code selectors only). */
3461	#define X86_SEL_TYPE_READ 2
3462	/** The bit number of the code segment read bit (relative to u4Type). */
3463	#define X86_SEL_TYPE_READ_BIT 1
3464
3465	/** Read only selector type. */
3466	#define X86_SEL_TYPE_RO 0
3467	/** Accessed read only selector type. */
3468	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
3469	/** Read write selector type. */
3470	#define X86_SEL_TYPE_RW 2
3471	/** Accessed read write selector type. */
3472	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
3473	/** Expand down read only selector type. */
3474	#define X86_SEL_TYPE_RO_DOWN 4
3475	/** Accessed expand down read only selector type. */
3476	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
3477	/** Expand down read write selector type. */
3478	#define X86_SEL_TYPE_RW_DOWN 6
3479	/** Accessed expand down read write selector type. */
3480	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
3481	/** Execute only selector type. */
3482	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
3483	/** Accessed execute only selector type. */
3484	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3485	/** Execute and read selector type. */
3486	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
3487	/** Accessed execute and read selector type. */
3488	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3489	/** Conforming execute only selector type. */
3490	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
3491	/** Accessed Conforming execute only selector type. */
3492	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3493	/** Conforming execute and write selector type. */
3494	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
3495	/** Accessed Conforming execute and write selector type. */
3496	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3497	/** @} */
3498
3499
3500	/** @name System Selector Types.
3501	* @{ */
3502	/** The TSS busy bit mask. */
3503	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3504
3505	/** Undefined system selector type. */
3506	#define X86_SEL_TYPE_SYS_UNDEFINED 0
3507	/** 286 TSS selector. */
3508	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3509	/** LDT selector. */
3510	#define X86_SEL_TYPE_SYS_LDT 2
3511	/** 286 TSS selector - Busy. */
3512	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3513	/** 286 Callgate selector. */
3514	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3515	/** Taskgate selector. */
3516	#define X86_SEL_TYPE_SYS_TASK_GATE 5
3517	/** 286 Interrupt gate selector. */
3518	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3519	/** 286 Trapgate selector. */
3520	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3521	/** Undefined system selector. */
3522	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3523	/** 386 TSS selector. */
3524	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3525	/** Undefined system selector. */
3526	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3527	/** 386 TSS selector - Busy. */
3528	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3529	/** 386 Callgate selector. */
3530	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3531	/** Undefined system selector. */
3532	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3533	/** 386 Interruptgate selector. */
3534	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3535	/** 386 Trapgate selector. */
3536	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3537	/** @} */
3538
3539	/** @name AMD64 System Selector Types.
3540	* @{ */
3541	/** LDT selector. */
3542	#define AMD64_SEL_TYPE_SYS_LDT 2
3543	/** TSS selector - Busy. */
3544	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3545	/** TSS selector - Busy. */
3546	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3547	/** Callgate selector. */
3548	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3549	/** Interruptgate selector. */
3550	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3551	/** Trapgate selector. */
3552	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3553	/** @} */
3554
3555	/** @} */
3556
3557
3558	/** @name Descriptor Table Entry Flag Masks.
3559	* These are for the 2nd 32-bit word of a descriptor.
3560	* @{ */
3561	/** Bits 8-11 - TYPE - Descriptor type mask. */
3562	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3563	/** Bit 12 - S - System (=0) or Code/Data (=1). */
3564	#define X86_DESC_S RT_BIT_32(12)
3565	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3566	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
3567	/** Bit 15 - P - Present. */
3568	#define X86_DESC_P RT_BIT_32(15)
3569	/** Bit 20 - AVL - Available for system software. */
3570	#define X86_DESC_AVL RT_BIT_32(20)
3571	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3572	#define X86_DESC_DB RT_BIT_32(22)
3573	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3574	* used, if clear byte. */
3575	#define X86_DESC_G RT_BIT_32(23)
3576	/** @} */
3577
3578	/** @} */
3579
3580
3581	/** @name Task Segments.
3582	* @{
3583	*/
3584
3585	/**
3586	* The minimum TSS descriptor limit for 286 tasks.
3587	*/
3588	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3589
3590	/**
3591	* The minimum TSS descriptor segment limit for 386 tasks.
3592	*/
3593	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3594
3595	/**
3596	* 16-bit Task Segment (TSS).
3597	*/
3598	#pragma pack(1)
3599	typedef struct X86TSS16
3600	{
3601	/** Back link to previous task. (static) */
3602	RTSEL selPrev;
3603	/** Ring-0 stack pointer. (static) */
3604	uint16_t sp0;
3605	/** Ring-0 stack segment. (static) */
3606	RTSEL ss0;
3607	/** Ring-1 stack pointer. (static) */
3608	uint16_t sp1;
3609	/** Ring-1 stack segment. (static) */
3610	RTSEL ss1;
3611	/** Ring-2 stack pointer. (static) */
3612	uint16_t sp2;
3613	/** Ring-2 stack segment. (static) */
3614	RTSEL ss2;
3615	/** IP before task switch. */
3616	uint16_t ip;
3617	/** FLAGS before task switch. */
3618	uint16_t flags;
3619	/** AX before task switch. */
3620	uint16_t ax;
3621	/** CX before task switch. */
3622	uint16_t cx;
3623	/** DX before task switch. */
3624	uint16_t dx;
3625	/** BX before task switch. */
3626	uint16_t bx;
3627	/** SP before task switch. */
3628	uint16_t sp;
3629	/** BP before task switch. */
3630	uint16_t bp;
3631	/** SI before task switch. */
3632	uint16_t si;
3633	/** DI before task switch. */
3634	uint16_t di;
3635	/** ES before task switch. */
3636	RTSEL es;
3637	/** CS before task switch. */
3638	RTSEL cs;
3639	/** SS before task switch. */
3640	RTSEL ss;
3641	/** DS before task switch. */
3642	RTSEL ds;
3643	/** LDTR before task switch. */
3644	RTSEL selLdt;
3645	} X86TSS16;
3646	#ifndef VBOX_FOR_DTRACE_LIB
3647	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
3648	#endif
3649	#pragma pack()
3650	/** Pointer to a 16-bit task segment. */
3651	typedef X86TSS16 *PX86TSS16;
3652	/** Pointer to a const 16-bit task segment. */
3653	typedef const X86TSS16 *PCX86TSS16;
3654
3655
3656	/**
3657	* 32-bit Task Segment (TSS).
3658	*/
3659	#pragma pack(1)
3660	typedef struct X86TSS32
3661	{
3662	/** Back link to previous task. (static) */
3663	RTSEL selPrev;
3664	uint16_t padding1;
3665	/** Ring-0 stack pointer. (static) */
3666	uint32_t esp0;
3667	/** Ring-0 stack segment. (static) */
3668	RTSEL ss0;
3669	uint16_t padding_ss0;
3670	/** Ring-1 stack pointer. (static) */
3671	uint32_t esp1;
3672	/** Ring-1 stack segment. (static) */
3673	RTSEL ss1;
3674	uint16_t padding_ss1;
3675	/** Ring-2 stack pointer. (static) */
3676	uint32_t esp2;
3677	/** Ring-2 stack segment. (static) */
3678	RTSEL ss2;
3679	uint16_t padding_ss2;
3680	/** Page directory for the task. (static) */
3681	uint32_t cr3;
3682	/** EIP before task switch. */
3683	uint32_t eip;
3684	/** EFLAGS before task switch. */
3685	uint32_t eflags;
3686	/** EAX before task switch. */
3687	uint32_t eax;
3688	/** ECX before task switch. */
3689	uint32_t ecx;
3690	/** EDX before task switch. */
3691	uint32_t edx;
3692	/** EBX before task switch. */
3693	uint32_t ebx;
3694	/** ESP before task switch. */
3695	uint32_t esp;
3696	/** EBP before task switch. */
3697	uint32_t ebp;
3698	/** ESI before task switch. */
3699	uint32_t esi;
3700	/** EDI before task switch. */
3701	uint32_t edi;
3702	/** ES before task switch. */
3703	RTSEL es;
3704	uint16_t padding_es;
3705	/** CS before task switch. */
3706	RTSEL cs;
3707	uint16_t padding_cs;
3708	/** SS before task switch. */
3709	RTSEL ss;
3710	uint16_t padding_ss;
3711	/** DS before task switch. */
3712	RTSEL ds;
3713	uint16_t padding_ds;
3714	/** FS before task switch. */
3715	RTSEL fs;
3716	uint16_t padding_fs;
3717	/** GS before task switch. */
3718	RTSEL gs;
3719	uint16_t padding_gs;
3720	/** LDTR before task switch. */
3721	RTSEL selLdt;
3722	uint16_t padding_ldt;
3723	/** Debug trap flag */
3724	uint16_t fDebugTrap;
3725	/** Offset relative to the TSS of the start of the I/O Bitmap
3726	* and the end of the interrupt redirection bitmap. */
3727	uint16_t offIoBitmap;
3728	} X86TSS32;
3729	#pragma pack()
3730	/** Pointer to task segment. */
3731	typedef X86TSS32 *PX86TSS32;
3732	/** Pointer to const task segment. */
3733	typedef const X86TSS32 *PCX86TSS32;
3734	#ifndef VBOX_FOR_DTRACE_LIB
3735	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
3736	AssertCompileMemberOffset(X86TSS32, cr3, 28);
3737	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
3738	#endif
3739
3740	/**
3741	* 64-bit Task segment.
3742	*/
3743	#pragma pack(1)
3744	typedef struct X86TSS64
3745	{
3746	/** Reserved. */
3747	uint32_t u32Reserved;
3748	/** Ring-0 stack pointer. (static) */
3749	uint64_t rsp0;
3750	/** Ring-1 stack pointer. (static) */
3751	uint64_t rsp1;
3752	/** Ring-2 stack pointer. (static) */
3753	uint64_t rsp2;
3754	/** Reserved. */
3755	uint32_t u32Reserved2[2];
3756	/* IST */
3757	uint64_t ist1;
3758	uint64_t ist2;
3759	uint64_t ist3;
3760	uint64_t ist4;
3761	uint64_t ist5;
3762	uint64_t ist6;
3763	uint64_t ist7;
3764	/* Reserved. */
3765	uint16_t u16Reserved[5];
3766	/** Offset relative to the TSS of the start of the I/O Bitmap
3767	* and the end of the interrupt redirection bitmap. */
3768	uint16_t offIoBitmap;
3769	} X86TSS64;
3770	#pragma pack()
3771	/** Pointer to a 64-bit task segment. */
3772	typedef X86TSS64 *PX86TSS64;
3773	/** Pointer to a const 64-bit task segment. */
3774	typedef const X86TSS64 *PCX86TSS64;
3775	#ifndef VBOX_FOR_DTRACE_LIB
3776	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
3777	#endif
3778
3779	/** @} */
3780
3781
3782	/** @name Selectors.
3783	* @{
3784	*/
3785
3786	/**
3787	* The shift used to convert a selector from and to index an index (C).
3788	*/
3789	#define X86_SEL_SHIFT 3
3790
3791	/**
3792	* The mask used to mask off the table indicator and RPL of an selector.
3793	*/
3794	#define X86_SEL_MASK 0xfff8U
3795
3796	/**
3797	* The mask used to mask off the RPL of an selector.
3798	* This is suitable for checking for NULL selectors.
3799	*/
3800	#define X86_SEL_MASK_OFF_RPL 0xfffcU
3801
3802	/**
3803	* The bit indicating that a selector is in the LDT and not in the GDT.
3804	*/
3805	#define X86_SEL_LDT 0x0004U
3806
3807	/**
3808	* The bit mask for getting the RPL of a selector.
3809	*/
3810	#define X86_SEL_RPL 0x0003U
3811
3812	/**
3813	* The mask covering both RPL and LDT.
3814	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
3815	* checks.
3816	*/
3817	#define X86_SEL_RPL_LDT 0x0007U
3818
3819	/** @} */
3820
3821
3822	/**
3823	* x86 Exceptions/Faults/Traps.
3824	*/
3825	typedef enum X86XCPT
3826	{
3827	/** \#DE - Divide error. */
3828	X86_XCPT_DE = 0x00,
3829	/** \#DB - Debug event (single step, DRx, ..) */
3830	X86_XCPT_DB = 0x01,
3831	/** NMI - Non-Maskable Interrupt */
3832	X86_XCPT_NMI = 0x02,
3833	/** \#BP - Breakpoint (INT3). */
3834	X86_XCPT_BP = 0x03,
3835	/** \#OF - Overflow (INTO). */
3836	X86_XCPT_OF = 0x04,
3837	/** \#BR - Bound range exceeded (BOUND). */
3838	X86_XCPT_BR = 0x05,
3839	/** \#UD - Undefined opcode. */
3840	X86_XCPT_UD = 0x06,
3841	/** \#NM - Device not available (math coprocessor device). */
3842	X86_XCPT_NM = 0x07,
3843	/** \#DF - Double fault. */
3844	X86_XCPT_DF = 0x08,
3845	/** ??? - Coprocessor segment overrun (obsolete). */
3846	X86_XCPT_CO_SEG_OVERRUN = 0x09,
3847	/** \#TS - Taskswitch (TSS). */
3848	X86_XCPT_TS = 0x0a,
3849	/** \#NP - Segment no present. */
3850	X86_XCPT_NP = 0x0b,
3851	/** \#SS - Stack segment fault. */
3852	X86_XCPT_SS = 0x0c,
3853	/** \#GP - General protection fault. */
3854	X86_XCPT_GP = 0x0d,
3855	/** \#PF - Page fault. */
3856	X86_XCPT_PF = 0x0e,
3857	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
3858	/** \#MF - Math fault (FPU). */
3859	X86_XCPT_MF = 0x10,
3860	/** \#AC - Alignment check. */
3861	X86_XCPT_AC = 0x11,
3862	/** \#MC - Machine check. */
3863	X86_XCPT_MC = 0x12,
3864	/** \#XF - SIMD Floating-Pointer Exception. */
3865	X86_XCPT_XF = 0x13,
3866	/** \#VE - Virtualization Exception. */
3867	X86_XCPT_VE = 0x14,
3868	/** \#SX - Security Exception. */
3869	X86_XCPT_SX = 0x1f
3870	} X86XCPT;
3871	/** Pointer to a x86 exception code. */
3872	typedef X86XCPT *PX86XCPT;
3873	/** Pointer to a const x86 exception code. */
3874	typedef const X86XCPT *PCX86XCPT;
3875	/** The maximum exception value. */
3876	#define X86_XCPT_MAX (X86_XCPT_SX)
3877
3878
3879	/** @name Trap Error Codes
3880	* @{
3881	*/
3882	/** External indicator. */
3883	#define X86_TRAP_ERR_EXTERNAL 1
3884	/** IDT indicator. */
3885	#define X86_TRAP_ERR_IDT 2
3886	/** Descriptor table indicator - If set LDT, if clear GDT. */
3887	#define X86_TRAP_ERR_TI 4
3888	/** Mask for getting the selector. */
3889	#define X86_TRAP_ERR_SEL_MASK 0xfff8
3890	/** Shift for getting the selector table index (C type index). */
3891	#define X86_TRAP_ERR_SEL_SHIFT 3
3892	/** @} */
3893
3894
3895	/** @name \#PF Trap Error Codes
3896	* @{
3897	*/
3898	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3899	#define X86_TRAP_PF_P RT_BIT_32(0)
3900	/** Bit 1 - R/W - Read (clear) or write (set) access. */
3901	#define X86_TRAP_PF_RW RT_BIT_32(1)
3902	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3903	#define X86_TRAP_PF_US RT_BIT_32(2)
3904	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3905	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
3906	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3907	#define X86_TRAP_PF_ID RT_BIT_32(4)
3908	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
3909	#define X86_TRAP_PF_PK RT_BIT_32(5)
3910	/** @} */
3911
3912	#pragma pack(1)
3913	/**
3914	* 16-bit IDTR.
3915	*/
3916	typedef struct X86IDTR16
3917	{
3918	/** Offset. */
3919	uint16_t offSel;
3920	/** Selector. */
3921	uint16_t uSel;
3922	} X86IDTR16, *PX86IDTR16;
3923	#pragma pack()
3924
3925	#pragma pack(1)
3926	/**
3927	* 32-bit IDTR/GDTR.
3928	*/
3929	typedef struct X86XDTR32
3930	{
3931	/** Size of the descriptor table. */
3932	uint16_t cb;
3933	/** Address of the descriptor table. */
3934	#ifndef VBOX_FOR_DTRACE_LIB
3935	uint32_t uAddr;
3936	#else
3937	uint16_t au16Addr[2];
3938	#endif
3939	} X86XDTR32, *PX86XDTR32;
3940	#pragma pack()
3941
3942	#pragma pack(1)
3943	/**
3944	* 64-bit IDTR/GDTR.
3945	*/
3946	typedef struct X86XDTR64
3947	{
3948	/** Size of the descriptor table. */
3949	uint16_t cb;
3950	/** Address of the descriptor table. */
3951	#ifndef VBOX_FOR_DTRACE_LIB
3952	uint64_t uAddr;
3953	#else
3954	uint16_t au16Addr[4];
3955	#endif
3956	} X86XDTR64, *PX86XDTR64;
3957	#pragma pack()
3958
3959
3960	/** @name ModR/M
3961	* @{ */
3962	#define X86_MODRM_RM_MASK UINT8_C(0x07)
3963	#define X86_MODRM_REG_MASK UINT8_C(0x38)
3964	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3965	#define X86_MODRM_REG_SHIFT 3
3966	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3967	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3968	#define X86_MODRM_MOD_SHIFT 6
3969	#ifndef VBOX_FOR_DTRACE_LIB
3970	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
3971	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3972	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3973	#endif
3974	/** @} */
3975
3976	/** @name SIB
3977	* @{ */
3978	#define X86_SIB_BASE_MASK UINT8_C(0x07)
3979	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3980	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3981	#define X86_SIB_INDEX_SHIFT 3
3982	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3983	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3984	#define X86_SIB_SCALE_SHIFT 6
3985	#ifndef VBOX_FOR_DTRACE_LIB
3986	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
3987	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3988	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3989	#endif
3990	/** @} */
3991
3992	/** @name General register indexes
3993	* @{ */
3994	#define X86_GREG_xAX 0
3995	#define X86_GREG_xCX 1
3996	#define X86_GREG_xDX 2
3997	#define X86_GREG_xBX 3
3998	#define X86_GREG_xSP 4
3999	#define X86_GREG_xBP 5
4000	#define X86_GREG_xSI 6
4001	#define X86_GREG_xDI 7
4002	#define X86_GREG_x8 8
4003	#define X86_GREG_x9 9
4004	#define X86_GREG_x10 10
4005	#define X86_GREG_x11 11
4006	#define X86_GREG_x12 12
4007	#define X86_GREG_x13 13
4008	#define X86_GREG_x14 14
4009	#define X86_GREG_x15 15
4010	/** @} */
4011
4012	/** @name X86_SREG_XXX - Segment register indexes.
4013	* @{ */
4014	#define X86_SREG_ES 0
4015	#define X86_SREG_CS 1
4016	#define X86_SREG_SS 2
4017	#define X86_SREG_DS 3
4018	#define X86_SREG_FS 4
4019	#define X86_SREG_GS 5
4020	/** @} */
4021	/** Segment register count. */
4022	#define X86_SREG_COUNT 6
4023
4024
4025	/** @name X86_OP_XXX - Prefixes
4026	* @{ */
4027	#define X86_OP_PRF_CS UINT8_C(0x2e)
4028	#define X86_OP_PRF_SS UINT8_C(0x36)
4029	#define X86_OP_PRF_DS UINT8_C(0x3e)
4030	#define X86_OP_PRF_ES UINT8_C(0x26)
4031	#define X86_OP_PRF_FS UINT8_C(0x64)
4032	#define X86_OP_PRF_GS UINT8_C(0x65)
4033	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4034	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4035	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4036	#define X86_OP_PRF_REPZ UINT8_C(0xf2)
4037	#define X86_OP_PRF_REPNZ UINT8_C(0xf3)
4038	#define X86_OP_REX_B UINT8_C(0x41)
4039	#define X86_OP_REX_X UINT8_C(0x42)
4040	#define X86_OP_REX_R UINT8_C(0x44)
4041	#define X86_OP_REX_W UINT8_C(0x48)
4042	/** @} */
4043
4044
4045	/** @} */
4046
4047	#endif
4048

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source: vbox/trunk/include/iprt/x86.h@ 59961

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