x86.h@ 59868

Last change on this file since 59868 was 59868, checked in by vboxsync, 9 years ago
iprt/x86.h/mac: X86_CPUID_FEATURE_EDX_PAE_BIT
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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2015 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	#ifndef VBOX_FOR_DTRACE_LIB
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104	#endif /* !VBOX_FOR_DTRACE_LIB */
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	#ifndef VBOX_FOR_DTRACE_LIB
114	/** The bitfield view. */
115	X86EFLAGSBITS Bits;
116	#endif
117	/** The 8-bit view. */
118	uint8_t au8[4];
119	/** The 16-bit view. */
120	uint16_t au16[2];
121	/** The 32-bit view. */
122	uint32_t au32[1];
123	/** The 32-bit view. */
124	uint32_t u32;
125	} X86EFLAGS;
126	/** Pointer to EFLAGS. */
127	typedef X86EFLAGS *PX86EFLAGS;
128	/** Pointer to const EFLAGS. */
129	typedef const X86EFLAGS *PCX86EFLAGS;
130
131	/**
132	* RFLAGS (32 upper bits are reserved).
133	*/
134	typedef union X86RFLAGS
135	{
136	/** The plain unsigned view. */
137	uint64_t u;
138	#ifndef VBOX_FOR_DTRACE_LIB
139	/** The bitfield view. */
140	X86EFLAGSBITS Bits;
141	#endif
142	/** The 8-bit view. */
143	uint8_t au8[8];
144	/** The 16-bit view. */
145	uint16_t au16[4];
146	/** The 32-bit view. */
147	uint32_t au32[2];
148	/** The 64-bit view. */
149	uint64_t au64[1];
150	/** The 64-bit view. */
151	uint64_t u64;
152	} X86RFLAGS;
153	/** Pointer to RFLAGS. */
154	typedef X86RFLAGS *PX86RFLAGS;
155	/** Pointer to const RFLAGS. */
156	typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159	/** @name EFLAGS
160	* @{
161	*/
162	/** Bit 0 - CF - Carry flag - Status flag. */
163	#define X86_EFL_CF RT_BIT(0)
164	#define X86_EFL_CF_BIT 0
165	/** Bit 1 - Reserved, reads as 1. */
166	#define X86_EFL_1 RT_BIT(1)
167	/** Bit 2 - PF - Parity flag - Status flag. */
168	#define X86_EFL_PF RT_BIT(2)
169	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
170	#define X86_EFL_AF RT_BIT(4)
171	#define X86_EFL_AF_BIT 4
172	/** Bit 6 - ZF - Zero flag - Status flag. */
173	#define X86_EFL_ZF RT_BIT(6)
174	#define X86_EFL_ZF_BIT 6
175	/** Bit 7 - SF - Signed flag - Status flag. */
176	#define X86_EFL_SF RT_BIT(7)
177	#define X86_EFL_SF_BIT 7
178	/** Bit 8 - TF - Trap flag - System flag. */
179	#define X86_EFL_TF RT_BIT(8)
180	/** Bit 9 - IF - Interrupt flag - System flag. */
181	#define X86_EFL_IF RT_BIT(9)
182	/** Bit 10 - DF - Direction flag - Control flag. */
183	#define X86_EFL_DF RT_BIT(10)
184	/** Bit 11 - OF - Overflow flag - Status flag. */
185	#define X86_EFL_OF RT_BIT(11)
186	#define X86_EFL_OF_BIT 11
187	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
188	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
189	/** Bit 14 - NT - Nested task flag - System flag. */
190	#define X86_EFL_NT RT_BIT(14)
191	/** Bit 16 - RF - Resume flag - System flag. */
192	#define X86_EFL_RF RT_BIT(16)
193	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
194	#define X86_EFL_VM RT_BIT(17)
195	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
196	#define X86_EFL_AC RT_BIT(18)
197	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
198	#define X86_EFL_VIF RT_BIT(19)
199	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
200	#define X86_EFL_VIP RT_BIT(20)
201	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
202	#define X86_EFL_ID RT_BIT(21)
203	/** All live bits. */
204	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
205	/** Read as 1 bits. */
206	#define X86_EFL_RA1_MASK RT_BIT_32(1)
207	/** IOPL shift. */
208	#define X86_EFL_IOPL_SHIFT 12
209	/** The IOPL level from the flags. */
210	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
211	/** Bits restored by popf */
212	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
213	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
214	/** The status bits commonly updated by arithmetic instructions. */
215	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
216	/** @} */
217
218
219	/** CPUID Feature information - ECX.
220	* CPUID query with EAX=1.
221	*/
222	#ifndef VBOX_FOR_DTRACE_LIB
223	typedef struct X86CPUIDFEATECX
224	{
225	/** Bit 0 - SSE3 - Supports SSE3 or not. */
226	unsigned u1SSE3 : 1;
227	/** Bit 1 - PCLMULQDQ. */
228	unsigned u1PCLMULQDQ : 1;
229	/** Bit 2 - DS Area 64-bit layout. */
230	unsigned u1DTE64 : 1;
231	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
232	unsigned u1Monitor : 1;
233	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
234	unsigned u1CPLDS : 1;
235	/** Bit 5 - VMX - Virtual Machine Technology. */
236	unsigned u1VMX : 1;
237	/** Bit 6 - SMX: Safer Mode Extensions. */
238	unsigned u1SMX : 1;
239	/** Bit 7 - EST - Enh. SpeedStep Tech. */
240	unsigned u1EST : 1;
241	/** Bit 8 - TM2 - Terminal Monitor 2. */
242	unsigned u1TM2 : 1;
243	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
244	unsigned u1SSSE3 : 1;
245	/** Bit 10 - CNTX-ID - L1 Context ID. */
246	unsigned u1CNTXID : 1;
247	/** Bit 11 - Reserved. */
248	unsigned u1Reserved1 : 1;
249	/** Bit 12 - FMA. */
250	unsigned u1FMA : 1;
251	/** Bit 13 - CX16 - CMPXCHG16B. */
252	unsigned u1CX16 : 1;
253	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
254	unsigned u1TPRUpdate : 1;
255	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
256	unsigned u1PDCM : 1;
257	/** Bit 16 - Reserved. */
258	unsigned u1Reserved2 : 1;
259	/** Bit 17 - PCID - Process-context identifiers. */
260	unsigned u1PCID : 1;
261	/** Bit 18 - Direct Cache Access. */
262	unsigned u1DCA : 1;
263	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
264	unsigned u1SSE4_1 : 1;
265	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
266	unsigned u1SSE4_2 : 1;
267	/** Bit 21 - x2APIC. */
268	unsigned u1x2APIC : 1;
269	/** Bit 22 - MOVBE - Supports MOVBE. */
270	unsigned u1MOVBE : 1;
271	/** Bit 23 - POPCNT - Supports POPCNT. */
272	unsigned u1POPCNT : 1;
273	/** Bit 24 - TSC-Deadline. */
274	unsigned u1TSCDEADLINE : 1;
275	/** Bit 25 - AES. */
276	unsigned u1AES : 1;
277	/** Bit 26 - XSAVE - Supports XSAVE. */
278	unsigned u1XSAVE : 1;
279	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
280	unsigned u1OSXSAVE : 1;
281	/** Bit 28 - AVX - Supports AVX instruction extensions. */
282	unsigned u1AVX : 1;
283	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
284	unsigned u1F16C : 1;
285	/** Bit 30 - RDRAND - Supports RDRAND. */
286	unsigned u1RDRAND : 1;
287	/** Bit 31 - Hypervisor present (we're a guest). */
288	unsigned u1HVP : 1;
289	} X86CPUIDFEATECX;
290	#else /* VBOX_FOR_DTRACE_LIB */
291	typedef uint32_t X86CPUIDFEATECX;
292	#endif /* VBOX_FOR_DTRACE_LIB */
293	/** Pointer to CPUID Feature Information - ECX. */
294	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
295	/** Pointer to const CPUID Feature Information - ECX. */
296	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
297
298
299	/** CPUID Feature Information - EDX.
300	* CPUID query with EAX=1.
301	*/
302	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
303	typedef struct X86CPUIDFEATEDX
304	{
305	/** Bit 0 - FPU - x87 FPU on Chip. */
306	unsigned u1FPU : 1;
307	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
308	unsigned u1VME : 1;
309	/** Bit 2 - DE - Debugging extensions. */
310	unsigned u1DE : 1;
311	/** Bit 3 - PSE - Page Size Extension. */
312	unsigned u1PSE : 1;
313	/** Bit 4 - TSC - Time Stamp Counter. */
314	unsigned u1TSC : 1;
315	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
316	unsigned u1MSR : 1;
317	/** Bit 6 - PAE - Physical Address Extension. */
318	unsigned u1PAE : 1;
319	/** Bit 7 - MCE - Machine Check Exception. */
320	unsigned u1MCE : 1;
321	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
322	unsigned u1CX8 : 1;
323	/** Bit 9 - APIC - APIC On-Chip. */
324	unsigned u1APIC : 1;
325	/** Bit 10 - Reserved. */
326	unsigned u1Reserved1 : 1;
327	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
328	unsigned u1SEP : 1;
329	/** Bit 12 - MTRR - Memory Type Range Registers. */
330	unsigned u1MTRR : 1;
331	/** Bit 13 - PGE - PTE Global Bit. */
332	unsigned u1PGE : 1;
333	/** Bit 14 - MCA - Machine Check Architecture. */
334	unsigned u1MCA : 1;
335	/** Bit 15 - CMOV - Conditional Move Instructions. */
336	unsigned u1CMOV : 1;
337	/** Bit 16 - PAT - Page Attribute Table. */
338	unsigned u1PAT : 1;
339	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
340	unsigned u1PSE36 : 1;
341	/** Bit 18 - PSN - Processor Serial Number. */
342	unsigned u1PSN : 1;
343	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
344	unsigned u1CLFSH : 1;
345	/** Bit 20 - Reserved. */
346	unsigned u1Reserved2 : 1;
347	/** Bit 21 - DS - Debug Store. */
348	unsigned u1DS : 1;
349	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
350	unsigned u1ACPI : 1;
351	/** Bit 23 - MMX - Intel MMX 'Technology'. */
352	unsigned u1MMX : 1;
353	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
354	unsigned u1FXSR : 1;
355	/** Bit 25 - SSE - SSE Support. */
356	unsigned u1SSE : 1;
357	/** Bit 26 - SSE2 - SSE2 Support. */
358	unsigned u1SSE2 : 1;
359	/** Bit 27 - SS - Self Snoop. */
360	unsigned u1SS : 1;
361	/** Bit 28 - HTT - Hyper-Threading Technology. */
362	unsigned u1HTT : 1;
363	/** Bit 29 - TM - Thermal Monitor. */
364	unsigned u1TM : 1;
365	/** Bit 30 - Reserved - . */
366	unsigned u1Reserved3 : 1;
367	/** Bit 31 - PBE - Pending Break Enabled. */
368	unsigned u1PBE : 1;
369	} X86CPUIDFEATEDX;
370	#else /* VBOX_FOR_DTRACE_LIB */
371	typedef uint32_t X86CPUIDFEATEDX;
372	#endif /* VBOX_FOR_DTRACE_LIB */
373	/** Pointer to CPUID Feature Information - EDX. */
374	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
375	/** Pointer to const CPUID Feature Information - EDX. */
376	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
377
378	/** @name CPUID Vendor information.
379	* CPUID query with EAX=0.
380	* @{
381	*/
382	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
383	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
384	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
385
386	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
387	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
388	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
389
390	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
391	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
392	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
393	/** @} */
394
395
396	/** @name CPUID Feature information.
397	* CPUID query with EAX=1.
398	* @{
399	*/
400	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
401	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
402	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
403	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
404	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
405	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
406	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
407	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
408	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
409	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
410	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
411	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
412	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
413	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
414	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
415	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
416	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
417	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
418	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
419	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
420	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
421	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
422	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
423	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
424	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT(11)
425	/** ECX Bit 12 - FMA. */
426	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
427	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
428	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
429	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
430	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
431	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
432	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
433	/** ECX Bit 17 - PCID - Process-context identifiers. */
434	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
435	/** ECX Bit 18 - DCA - Direct Cache Access. */
436	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
437	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
438	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
439	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
440	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
441	/** ECX Bit 21 - x2APIC support. */
442	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
443	/** ECX Bit 22 - MOVBE instruction. */
444	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
445	/** ECX Bit 23 - POPCNT instruction. */
446	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
447	/** ECX Bir 24 - TSC-Deadline. */
448	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
449	/** ECX Bit 25 - AES instructions. */
450	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
451	/** ECX Bit 26 - XSAVE instruction. */
452	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
453	/** ECX Bit 27 - OSXSAVE instruction. */
454	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
455	/** ECX Bit 28 - AVX. */
456	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
457	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
458	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT(29)
459	/** ECX Bit 30 - RDRAND instruction. */
460	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT(30)
461	/** ECX Bit 31 - Hypervisor Present (software only). */
462	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
463
464
465	/** Bit 0 - FPU - x87 FPU on Chip. */
466	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
467	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
468	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
469	/** Bit 2 - DE - Debugging extensions. */
470	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
471	/** Bit 3 - PSE - Page Size Extension. */
472	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
473	/** Bit 4 - TSC - Time Stamp Counter. */
474	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
475	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
476	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
477	/** Bit 6 - PAE - Physical Address Extension. */
478	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
479	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6
480	/** Bit 7 - MCE - Machine Check Exception. */
481	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
482	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
483	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
484	/** Bit 9 - APIC - APIC On-Chip. */
485	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
486	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
487	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
488	/** Bit 12 - MTRR - Memory Type Range Registers. */
489	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
490	/** Bit 13 - PGE - PTE Global Bit. */
491	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
492	/** Bit 14 - MCA - Machine Check Architecture. */
493	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
494	/** Bit 15 - CMOV - Conditional Move Instructions. */
495	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
496	/** Bit 16 - PAT - Page Attribute Table. */
497	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
498	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
499	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
500	/** Bit 18 - PSN - Processor Serial Number. */
501	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
502	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
503	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
504	/** Bit 21 - DS - Debug Store. */
505	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
506	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
507	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
508	/** Bit 23 - MMX - Intel MMX Technology. */
509	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
510	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
511	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
512	/** Bit 25 - SSE - SSE Support. */
513	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
514	/** Bit 26 - SSE2 - SSE2 Support. */
515	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
516	/** Bit 27 - SS - Self Snoop. */
517	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
518	/** Bit 28 - HTT - Hyper-Threading Technology. */
519	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
520	/** Bit 29 - TM - Therm. Monitor. */
521	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
522	/** Bit 31 - PBE - Pending Break Enabled. */
523	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
524	/** @} */
525
526	/** @name CPUID mwait/monitor information.
527	* CPUID query with EAX=5.
528	* @{
529	*/
530	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
531	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
532	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
533	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
534	/** @} */
535
536
537	/** @name CPUID Structured Extended Feature information.
538	* CPUID query with EAX=7.
539	* @{
540	*/
541	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
542	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
543	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
544	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
545	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
546	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
547	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
548	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
549	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
550	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT(5)
551	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
552	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
553	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
554	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
555	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
556	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
557	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
558	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
559	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
560	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
561	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
562	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
563	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
564	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT(13)
565	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
566	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
567	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
568	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
569	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
570	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
571	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
572	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT(18)
573	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
574	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
575	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
576	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
577	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
578	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT(23)
579	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
580	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
581	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
582	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
583	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
584	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
585	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
586	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
587	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
588	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
589
590	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
591	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT(0)
592	/** @} */
593
594
595	/** @name CPUID Extended Feature information.
596	* CPUID query with EAX=0x80000001.
597	* @{
598	*/
599	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
600	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
601
602	/** EDX Bit 11 - SYSCALL/SYSRET. */
603	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
604	/** EDX Bit 20 - No-Execute/Execute-Disable. */
605	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
606	/** EDX Bit 26 - 1 GB large page. */
607	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
608	/** EDX Bit 27 - RDTSCP. */
609	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
610	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
611	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
612	/** @}*/
613
614	/** @name CPUID AMD Feature information.
615	* CPUID query with EAX=0x80000001.
616	* @{
617	*/
618	/** Bit 0 - FPU - x87 FPU on Chip. */
619	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
620	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
621	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
622	/** Bit 2 - DE - Debugging extensions. */
623	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
624	/** Bit 3 - PSE - Page Size Extension. */
625	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
626	/** Bit 4 - TSC - Time Stamp Counter. */
627	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
628	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
629	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
630	/** Bit 6 - PAE - Physical Address Extension. */
631	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
632	/** Bit 7 - MCE - Machine Check Exception. */
633	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
634	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
635	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
636	/** Bit 9 - APIC - APIC On-Chip. */
637	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
638	/** Bit 12 - MTRR - Memory Type Range Registers. */
639	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
640	/** Bit 13 - PGE - PTE Global Bit. */
641	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
642	/** Bit 14 - MCA - Machine Check Architecture. */
643	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
644	/** Bit 15 - CMOV - Conditional Move Instructions. */
645	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
646	/** Bit 16 - PAT - Page Attribute Table. */
647	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
648	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
649	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
650	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
651	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
652	/** Bit 23 - MMX - Intel MMX Technology. */
653	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
654	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
655	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
656	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
657	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
658	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
659	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
660	/** Bit 31 - 3DNOW - AMD 3DNow. */
661	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
662
663	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
664	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
665	/** Bit 2 - SVM - AMD VM extensions. */
666	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
667	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
668	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
669	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
670	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
671	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
672	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
673	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
674	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
675	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
676	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
677	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
678	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
679	/** Bit 9 - OSVW - AMD OS visible workaround. */
680	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
681	/** Bit 10 - IBS - Instruct based sampling. */
682	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
683	/** Bit 11 - XOP - Extended operation support (see APM6). */
684	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT(11)
685	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
686	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
687	/** Bit 13 - WDT - AMD Watchdog timer support. */
688	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
689	/** Bit 15 - LWP - Lightweight profiling support. */
690	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT(15)
691	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
692	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT(16)
693	/** Bit 19 - NodeId - Indicates support for
694	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
695	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT(19)
696	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
697	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT(21)
698	/** Bit 22 - TopologyExtensions - . */
699	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT(22)
700	/** @} */
701
702
703	/** @name CPUID AMD Feature information.
704	* CPUID query with EAX=0x80000007.
705	* @{
706	*/
707	/** Bit 0 - TS - Temperature Sensor. */
708	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
709	/** Bit 1 - FID - Frequency ID Control. */
710	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
711	/** Bit 2 - VID - Voltage ID Control. */
712	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
713	/** Bit 3 - TTP - THERMTRIP. */
714	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
715	/** Bit 4 - TM - Hardware Thermal Control. */
716	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
717	/** Bit 5 - STC - Software Thermal Control. */
718	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
719	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
720	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
721	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
722	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
723	/** Bit 8 - TSCINVAR - TSC Invariant. */
724	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
725	/** Bit 9 - CPB - TSC Invariant. */
726	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
727	/** Bit 10 - EffFreqRO - MPERF/APERF. */
728	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
729	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
730	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
731	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
732	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
733	/** @} */
734
735
736	/** @name CR0
737	* @{ */
738	/** Bit 0 - PE - Protection Enabled */
739	#define X86_CR0_PE RT_BIT(0)
740	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
741	/** Bit 1 - MP - Monitor Coprocessor */
742	#define X86_CR0_MP RT_BIT(1)
743	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
744	/** Bit 2 - EM - Emulation. */
745	#define X86_CR0_EM RT_BIT(2)
746	#define X86_CR0_EMULATE_FPU RT_BIT(2)
747	/** Bit 3 - TS - Task Switch. */
748	#define X86_CR0_TS RT_BIT(3)
749	#define X86_CR0_TASK_SWITCH RT_BIT(3)
750	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
751	#define X86_CR0_ET RT_BIT(4)
752	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
753	/** Bit 5 - NE - Numeric error. */
754	#define X86_CR0_NE RT_BIT(5)
755	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
756	/** Bit 16 - WP - Write Protect. */
757	#define X86_CR0_WP RT_BIT(16)
758	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
759	/** Bit 18 - AM - Alignment Mask. */
760	#define X86_CR0_AM RT_BIT(18)
761	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
762	/** Bit 29 - NW - Not Write-though. */
763	#define X86_CR0_NW RT_BIT(29)
764	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
765	/** Bit 30 - WP - Cache Disable. */
766	#define X86_CR0_CD RT_BIT(30)
767	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
768	/** Bit 31 - PG - Paging. */
769	#define X86_CR0_PG RT_BIT(31)
770	#define X86_CR0_PAGING RT_BIT(31)
771	/** @} */
772
773
774	/** @name CR3
775	* @{ */
776	/** Bit 3 - PWT - Page-level Writes Transparent. */
777	#define X86_CR3_PWT RT_BIT(3)
778	/** Bit 4 - PCD - Page-level Cache Disable. */
779	#define X86_CR3_PCD RT_BIT(4)
780	/** Bits 12-31 - - Page directory page number. */
781	#define X86_CR3_PAGE_MASK (0xfffff000)
782	/** Bits 5-31 - - PAE Page directory page number. */
783	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
784	/** Bits 12-51 - - AMD64 Page directory page number. */
785	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
786	/** @} */
787
788
789	/** @name CR4
790	* @{ */
791	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
792	#define X86_CR4_VME RT_BIT(0)
793	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
794	#define X86_CR4_PVI RT_BIT(1)
795	/** Bit 2 - TSD - Time Stamp Disable. */
796	#define X86_CR4_TSD RT_BIT(2)
797	/** Bit 3 - DE - Debugging Extensions. */
798	#define X86_CR4_DE RT_BIT(3)
799	/** Bit 4 - PSE - Page Size Extension. */
800	#define X86_CR4_PSE RT_BIT(4)
801	/** Bit 5 - PAE - Physical Address Extension. */
802	#define X86_CR4_PAE RT_BIT(5)
803	/** Bit 6 - MCE - Machine-Check Enable. */
804	#define X86_CR4_MCE RT_BIT(6)
805	/** Bit 7 - PGE - Page Global Enable. */
806	#define X86_CR4_PGE RT_BIT(7)
807	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
808	#define X86_CR4_PCE RT_BIT(8)
809	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
810	#define X86_CR4_OSFXSR RT_BIT(9)
811	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
812	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
813	/** Bit 13 - VMXE - VMX mode is enabled. */
814	#define X86_CR4_VMXE RT_BIT(13)
815	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
816	#define X86_CR4_SMXE RT_BIT(14)
817	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
818	#define X86_CR4_PCIDE RT_BIT(17)
819	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
820	* extended states. */
821	#define X86_CR4_OSXSAVE RT_BIT(18)
822	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
823	#define X86_CR4_SMEP RT_BIT(20)
824	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
825	#define X86_CR4_SMAP RT_BIT(21)
826	/** Bit 22 - PKE - Protection Key Enable. */
827	#define X86_CR4_PKE RT_BIT(22)
828	/** @} */
829
830
831	/** @name DR6
832	* @{ */
833	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
834	#define X86_DR6_B0 RT_BIT(0)
835	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
836	#define X86_DR6_B1 RT_BIT(1)
837	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
838	#define X86_DR6_B2 RT_BIT(2)
839	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
840	#define X86_DR6_B3 RT_BIT(3)
841	/** Mask of all the Bx bits. */
842	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
843	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
844	#define X86_DR6_BD RT_BIT(13)
845	/** Bit 14 - BS - Single step */
846	#define X86_DR6_BS RT_BIT(14)
847	/** Bit 15 - BT - Task switch. (TSS T bit.) */
848	#define X86_DR6_BT RT_BIT(15)
849	/** Value of DR6 after powerup/reset. */
850	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
851	/** Bits which must be 1s in DR6. */
852	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
853	/** Bits which must be 0s in DR6. */
854	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
855	/** Bits which must be 0s on writes to DR6. */
856	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
857	/** @} */
858
859	/** Get the DR6.Bx bit for a the given breakpoint. */
860	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
861
862
863	/** @name DR7
864	* @{ */
865	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
866	#define X86_DR7_L0 RT_BIT(0)
867	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
868	#define X86_DR7_G0 RT_BIT(1)
869	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
870	#define X86_DR7_L1 RT_BIT(2)
871	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
872	#define X86_DR7_G1 RT_BIT(3)
873	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
874	#define X86_DR7_L2 RT_BIT(4)
875	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
876	#define X86_DR7_G2 RT_BIT(5)
877	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
878	#define X86_DR7_L3 RT_BIT(6)
879	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
880	#define X86_DR7_G3 RT_BIT(7)
881	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
882	#define X86_DR7_LE RT_BIT(8)
883	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
884	#define X86_DR7_GE RT_BIT(9)
885
886	/** L0, L1, L2, and L3. */
887	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
888	/** L0, L1, L2, and L3. */
889	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
890
891	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
892	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
893	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
894	* instruction is executed.
895	* @see http://www.rcollins.org/secrets/DR7.html */
896	#define X86_DR7_ICE_IR RT_BIT(12)
897	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
898	* any DR register is accessed. */
899	#define X86_DR7_GD RT_BIT(13)
900	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
901	* Pentium. */
902	#define X86_DR7_ICE_TR1 RT_BIT(14)
903	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
904	#define X86_DR7_ICE_TR2 RT_BIT(15)
905	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
906	#define X86_DR7_RW0_MASK (3 << 16)
907	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
908	#define X86_DR7_LEN0_MASK (3 << 18)
909	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
910	#define X86_DR7_RW1_MASK (3 << 20)
911	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
912	#define X86_DR7_LEN1_MASK (3 << 22)
913	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
914	#define X86_DR7_RW2_MASK (3 << 24)
915	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
916	#define X86_DR7_LEN2_MASK (3 << 26)
917	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
918	#define X86_DR7_RW3_MASK (3 << 28)
919	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
920	#define X86_DR7_LEN3_MASK (3 << 30)
921
922	/** Bits which reads as 1s. */
923	#define X86_DR7_RA1_MASK (RT_BIT(10))
924	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
925	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
926	/** Bits which must be 0s when writing to DR7. */
927	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
928
929	/** Calcs the L bit of Nth breakpoint.
930	* @param iBp The breakpoint number [0..3].
931	*/
932	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
933
934	/** Calcs the G bit of Nth breakpoint.
935	* @param iBp The breakpoint number [0..3].
936	*/
937	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
938
939	/** Calcs the L and G bits of Nth breakpoint.
940	* @param iBp The breakpoint number [0..3].
941	*/
942	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
943
944	/** @name Read/Write values.
945	* @{ */
946	/** Break on instruction fetch only. */
947	#define X86_DR7_RW_EO 0U
948	/** Break on write only. */
949	#define X86_DR7_RW_WO 1U
950	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
951	#define X86_DR7_RW_IO 2U
952	/** Break on read or write (but not instruction fetches). */
953	#define X86_DR7_RW_RW 3U
954	/** @} */
955
956	/** Shifts a X86_DR7_RW_* value to its right place.
957	* @param iBp The breakpoint number [0..3].
958	* @param fRw One of the X86_DR7_RW_* value.
959	*/
960	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
961
962	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
963	* one of the X86_DR7_RW_XXX constants).
964	*
965	* @returns X86_DR7_RW_XXX
966	* @param uDR7 DR7 value
967	* @param iBp The breakpoint number [0..3].
968	*/
969	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
970
971	/** R/W0, R/W1, R/W2, and R/W3. */
972	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
973
974	#ifndef VBOX_FOR_DTRACE_LIB
975	/** Checks if there are any I/O breakpoint types configured in the RW
976	* registers. Does NOT check if these are enabled, sorry. */
977	# define X86_DR7_ANY_RW_IO(uDR7) \
978	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
979	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
980	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
981	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
982	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
983	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
984	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
985	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
986	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
987	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
988	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
989	#endif /* !VBOX_FOR_DTRACE_LIB */
990
991	/** @name Length values.
992	* @{ */
993	#define X86_DR7_LEN_BYTE 0U
994	#define X86_DR7_LEN_WORD 1U
995	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
996	#define X86_DR7_LEN_DWORD 3U
997	/** @} */
998
999	/** Shifts a X86_DR7_LEN_* value to its right place.
1000	* @param iBp The breakpoint number [0..3].
1001	* @param cb One of the X86_DR7_LEN_* values.
1002	*/
1003	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1004
1005	/** Fetch the breakpoint length bits from the DR7 value.
1006	* @param uDR7 DR7 value
1007	* @param iBp The breakpoint number [0..3].
1008	*/
1009	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1010
1011	/** Mask used to check if any breakpoints are enabled. */
1012	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1013
1014	/** LEN0, LEN1, LEN2, and LEN3. */
1015	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1016	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1017	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1018
1019	/** Value of DR7 after powerup/reset. */
1020	#define X86_DR7_INIT_VAL 0x400
1021	/** @} */
1022
1023
1024	/** @name Machine Specific Registers
1025	* @{
1026	*/
1027	/** Machine check address register (P5). */
1028	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1029	/** Machine check type register (P5). */
1030	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1031	/** Time Stamp Counter. */
1032	#define MSR_IA32_TSC 0x10
1033	#define MSR_IA32_CESR UINT32_C(0x00000011)
1034	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1035	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1036
1037	#define MSR_IA32_PLATFORM_ID 0x17
1038
1039	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1040	# define MSR_IA32_APICBASE 0x1b
1041	/** Local APIC enabled. */
1042	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1043	/** X2APIC enabled (requires the EN bit to be set). */
1044	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1045	/** The processor is the boot strap processor (BSP). */
1046	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1047	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1048	* width. */
1049	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1050	#endif
1051
1052	/** Undocumented intel MSR for reporting thread and core counts.
1053	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1054	* first 16 bits is the thread count. The next 16 bits the core count, except
1055	* on Westmere where it seems it's only the next 4 bits for some reason. */
1056	#define MSR_CORE_THREAD_COUNT 0x35
1057
1058	/** CPU Feature control. */
1059	#define MSR_IA32_FEATURE_CONTROL 0x3A
1060	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
1061	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT(1)
1062	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
1063
1064	/** Per-processor TSC adjust MSR. */
1065	#define MSR_IA32_TSC_ADJUST 0x3B
1066
1067	/** BIOS update trigger (microcode update). */
1068	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1069
1070	/** BIOS update signature (microcode). */
1071	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1072
1073	/** SMM monitor control. */
1074	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1075
1076	/** General performance counter no. 0. */
1077	#define MSR_IA32_PMC0 0xC1
1078	/** General performance counter no. 1. */
1079	#define MSR_IA32_PMC1 0xC2
1080	/** General performance counter no. 2. */
1081	#define MSR_IA32_PMC2 0xC3
1082	/** General performance counter no. 3. */
1083	#define MSR_IA32_PMC3 0xC4
1084
1085	/** Nehalem power control. */
1086	#define MSR_IA32_PLATFORM_INFO 0xCE
1087
1088	/** Get FSB clock status (Intel-specific). */
1089	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1090
1091	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1092	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1093
1094	/** C0 Maximum Frequency Clock Count */
1095	#define MSR_IA32_MPERF 0xE7
1096	/** C0 Actual Frequency Clock Count */
1097	#define MSR_IA32_APERF 0xE8
1098
1099	/** MTRR Capabilities. */
1100	#define MSR_IA32_MTRR_CAP 0xFE
1101
1102	/** Cache control/info. */
1103	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1104
1105	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1106	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1107	* R0 SS == CS + 8
1108	* R3 CS == CS + 16
1109	* R3 SS == CS + 24
1110	*/
1111	#define MSR_IA32_SYSENTER_CS 0x174
1112	/** SYSENTER_ESP - the R0 ESP. */
1113	#define MSR_IA32_SYSENTER_ESP 0x175
1114	/** SYSENTER_EIP - the R0 EIP. */
1115	#define MSR_IA32_SYSENTER_EIP 0x176
1116	#endif
1117
1118	/** Machine Check Global Capabilities Register. */
1119	#define MSR_IA32_MCG_CAP 0x179
1120	/** Machine Check Global Status Register. */
1121	#define MSR_IA32_MCG_STATUS 0x17A
1122	/** Machine Check Global Control Register. */
1123	#define MSR_IA32_MCG_CTRL 0x17B
1124
1125	/** Page Attribute Table. */
1126	#define MSR_IA32_CR_PAT 0x277
1127
1128	/** Performance counter MSRs. (Intel only) */
1129	#define MSR_IA32_PERFEVTSEL0 0x186
1130	#define MSR_IA32_PERFEVTSEL1 0x187
1131	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1132	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1133	* holds a ratio that Apple takes for TSC granularity.
1134	*
1135	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1136	#define MSR_FLEX_RATIO 0x194
1137	/** Performance state value and starting with Intel core more.
1138	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1139	#define MSR_IA32_PERF_STATUS 0x198
1140	#define MSR_IA32_PERF_CTL 0x199
1141	#define MSR_IA32_THERM_STATUS 0x19c
1142
1143	/** Enable misc. processor features (R/W). */
1144	#define MSR_IA32_MISC_ENABLE 0x1A0
1145	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1146	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1147	/** Automatic Thermal Control Circuit Enable (R/W). */
1148	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1149	/** Performance Monitoring Available (R). */
1150	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1151	/** Branch Trace Storage Unavailable (R/O). */
1152	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1153	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1154	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1155	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1156	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1157	/** If MONITOR/MWAIT is supported (R/W). */
1158	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1159	/** Limit CPUID Maxval to 3 leafs (R/W). */
1160	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1161	/** When set to 1, xTPR messages are disabled (R/W). */
1162	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1163	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1164	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1165
1166	/** Trace/Profile Resource Control (R/W) */
1167	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1168	/** The number (0..3 or 0..15) of the last branch record register on P4 and
1169	* related Xeons. */
1170	#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1171	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1172	* @{ */
1173	#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1174	#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1175	#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1176	#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1177	/** @} */
1178
1179
1180	#define IA32_MTRR_PHYSBASE0 0x200
1181	#define IA32_MTRR_PHYSMASK0 0x201
1182	#define IA32_MTRR_PHYSBASE1 0x202
1183	#define IA32_MTRR_PHYSMASK1 0x203
1184	#define IA32_MTRR_PHYSBASE2 0x204
1185	#define IA32_MTRR_PHYSMASK2 0x205
1186	#define IA32_MTRR_PHYSBASE3 0x206
1187	#define IA32_MTRR_PHYSMASK3 0x207
1188	#define IA32_MTRR_PHYSBASE4 0x208
1189	#define IA32_MTRR_PHYSMASK4 0x209
1190	#define IA32_MTRR_PHYSBASE5 0x20a
1191	#define IA32_MTRR_PHYSMASK5 0x20b
1192	#define IA32_MTRR_PHYSBASE6 0x20c
1193	#define IA32_MTRR_PHYSMASK6 0x20d
1194	#define IA32_MTRR_PHYSBASE7 0x20e
1195	#define IA32_MTRR_PHYSMASK7 0x20f
1196	#define IA32_MTRR_PHYSBASE8 0x210
1197	#define IA32_MTRR_PHYSMASK8 0x211
1198	#define IA32_MTRR_PHYSBASE9 0x212
1199	#define IA32_MTRR_PHYSMASK9 0x213
1200
1201	/** Fixed range MTRRs.
1202	* @{ */
1203	#define IA32_MTRR_FIX64K_00000 0x250
1204	#define IA32_MTRR_FIX16K_80000 0x258
1205	#define IA32_MTRR_FIX16K_A0000 0x259
1206	#define IA32_MTRR_FIX4K_C0000 0x268
1207	#define IA32_MTRR_FIX4K_C8000 0x269
1208	#define IA32_MTRR_FIX4K_D0000 0x26a
1209	#define IA32_MTRR_FIX4K_D8000 0x26b
1210	#define IA32_MTRR_FIX4K_E0000 0x26c
1211	#define IA32_MTRR_FIX4K_E8000 0x26d
1212	#define IA32_MTRR_FIX4K_F0000 0x26e
1213	#define IA32_MTRR_FIX4K_F8000 0x26f
1214	/** @} */
1215
1216	/** MTRR Default Range. */
1217	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1218
1219	#define MSR_IA32_MC0_CTL 0x400
1220	#define MSR_IA32_MC0_STATUS 0x401
1221
1222	/** Basic VMX information. */
1223	#define MSR_IA32_VMX_BASIC_INFO 0x480
1224	/** Allowed settings for pin-based VM execution controls */
1225	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1226	/** Allowed settings for proc-based VM execution controls */
1227	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1228	/** Allowed settings for the VMX exit controls. */
1229	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1230	/** Allowed settings for the VMX entry controls. */
1231	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1232	/** Misc VMX info. */
1233	#define MSR_IA32_VMX_MISC 0x485
1234	/** Fixed cleared bits in CR0. */
1235	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1236	/** Fixed set bits in CR0. */
1237	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1238	/** Fixed cleared bits in CR4. */
1239	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1240	/** Fixed set bits in CR4. */
1241	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1242	/** Information for enumerating fields in the VMCS. */
1243	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1244	/** Allowed settings for the VM-functions controls. */
1245	#define MSR_IA32_VMX_VMFUNC 0x491
1246	/** Allowed settings for secondary proc-based VM execution controls */
1247	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1248	/** EPT capabilities. */
1249	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1250	/** DS Save Area (R/W). */
1251	#define MSR_IA32_DS_AREA 0x600
1252	/** Running Average Power Limit (RAPL) power units. */
1253	#define MSR_RAPL_POWER_UNIT 0x606
1254	/** X2APIC MSR ranges. */
1255	#define MSR_IA32_X2APIC_START 0x800
1256	#define MSR_IA32_X2APIC_TPR 0x808
1257	#define MSR_IA32_X2APIC_END 0xBFF
1258
1259	/** K6 EFER - Extended Feature Enable Register. */
1260	#define MSR_K6_EFER UINT32_C(0xc0000080)
1261	/** @todo document EFER */
1262	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1263	#define MSR_K6_EFER_SCE RT_BIT(0)
1264	/** Bit 8 - LME - Long mode enabled. (R/W) */
1265	#define MSR_K6_EFER_LME RT_BIT(8)
1266	/** Bit 10 - LMA - Long mode active. (R) */
1267	#define MSR_K6_EFER_LMA RT_BIT(10)
1268	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1269	#define MSR_K6_EFER_NXE RT_BIT(11)
1270	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1271	#define MSR_K6_EFER_SVME RT_BIT(12)
1272	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1273	#define MSR_K6_EFER_LMSLE RT_BIT(13)
1274	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1275	#define MSR_K6_EFER_FFXSR RT_BIT(14)
1276	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1277	#define MSR_K6_EFER_TCE RT_BIT(15)
1278	/** K6 STAR - SYSCALL/RET targets. */
1279	#define MSR_K6_STAR UINT32_C(0xc0000081)
1280	/** Shift value for getting the SYSRET CS and SS value. */
1281	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1282	/** Shift value for getting the SYSCALL CS and SS value. */
1283	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1284	/** Selector mask for use after shifting. */
1285	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1286	/** The mask which give the SYSCALL EIP. */
1287	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1288	/** K6 WHCR - Write Handling Control Register. */
1289	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1290	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1291	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1292	/** K6 PSOR - Processor State Observability Register. */
1293	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1294	/** K6 PFIR - Page Flush/Invalidate Register. */
1295	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1296
1297	/** Performance counter MSRs. (AMD only) */
1298	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1299	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1300	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1301	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1302	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1303	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1304	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1305	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1306
1307	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1308	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1309	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1310	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1311	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1312	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1313	/** K8 FS.base - The 64-bit base FS register. */
1314	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1315	/** K8 GS.base - The 64-bit base GS register. */
1316	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1317	/** K8 KernelGSbase - Used with SWAPGS. */
1318	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1319	/** K8 TSC_AUX - Used with RDTSCP. */
1320	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1321	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1322	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1323	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1324	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1325	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1326	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1327	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1328	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1329	/** North bridge config? See BIOS & Kernel dev guides for
1330	* details. */
1331	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1332
1333	/** Hypertransport interrupt pending register.
1334	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1335	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1336	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1337	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1338
1339	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1340	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1341	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1342	* host state during world switch. */
1343	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1344
1345	/** @} */
1346
1347
1348	/** @name Page Table / Directory / Directory Pointers / L4.
1349	* @{
1350	*/
1351
1352	/** Page table/directory entry as an unsigned integer. */
1353	typedef uint32_t X86PGUINT;
1354	/** Pointer to a page table/directory table entry as an unsigned integer. */
1355	typedef X86PGUINT *PX86PGUINT;
1356	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1357	typedef X86PGUINT const *PCX86PGUINT;
1358
1359	/** Number of entries in a 32-bit PT/PD. */
1360	#define X86_PG_ENTRIES 1024
1361
1362
1363	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1364	typedef uint64_t X86PGPAEUINT;
1365	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1366	typedef X86PGPAEUINT *PX86PGPAEUINT;
1367	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1368	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1369
1370	/** Number of entries in a PAE PT/PD. */
1371	#define X86_PG_PAE_ENTRIES 512
1372	/** Number of entries in a PAE PDPT. */
1373	#define X86_PG_PAE_PDPE_ENTRIES 4
1374
1375	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1376	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1377	/** Number of entries in an AMD64 PDPT.
1378	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1379	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1380
1381	/** The size of a 4KB page. */
1382	#define X86_PAGE_4K_SIZE _4K
1383	/** The page shift of a 4KB page. */
1384	#define X86_PAGE_4K_SHIFT 12
1385	/** The 4KB page offset mask. */
1386	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1387	/** The 4KB page base mask for virtual addresses. */
1388	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1389	/** The 4KB page base mask for virtual addresses - 32bit version. */
1390	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1391
1392	/** The size of a 2MB page. */
1393	#define X86_PAGE_2M_SIZE _2M
1394	/** The page shift of a 2MB page. */
1395	#define X86_PAGE_2M_SHIFT 21
1396	/** The 2MB page offset mask. */
1397	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1398	/** The 2MB page base mask for virtual addresses. */
1399	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1400	/** The 2MB page base mask for virtual addresses - 32bit version. */
1401	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1402
1403	/** The size of a 4MB page. */
1404	#define X86_PAGE_4M_SIZE _4M
1405	/** The page shift of a 4MB page. */
1406	#define X86_PAGE_4M_SHIFT 22
1407	/** The 4MB page offset mask. */
1408	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1409	/** The 4MB page base mask for virtual addresses. */
1410	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1411	/** The 4MB page base mask for virtual addresses - 32bit version. */
1412	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1413
1414	/**
1415	* Check if the given address is canonical.
1416	*/
1417	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1418
1419
1420	/** @name Page Table Entry
1421	* @{
1422	*/
1423	/** Bit 0 - P - Present bit. */
1424	#define X86_PTE_BIT_P 0
1425	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1426	#define X86_PTE_BIT_RW 1
1427	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1428	#define X86_PTE_BIT_US 2
1429	/** Bit 3 - PWT - Page level write thru bit. */
1430	#define X86_PTE_BIT_PWT 3
1431	/** Bit 4 - PCD - Page level cache disable bit. */
1432	#define X86_PTE_BIT_PCD 4
1433	/** Bit 5 - A - Access bit. */
1434	#define X86_PTE_BIT_A 5
1435	/** Bit 6 - D - Dirty bit. */
1436	#define X86_PTE_BIT_D 6
1437	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1438	#define X86_PTE_BIT_PAT 7
1439	/** Bit 8 - G - Global flag. */
1440	#define X86_PTE_BIT_G 8
1441
1442	/** Bit 0 - P - Present bit mask. */
1443	#define X86_PTE_P RT_BIT(0)
1444	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1445	#define X86_PTE_RW RT_BIT(1)
1446	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1447	#define X86_PTE_US RT_BIT(2)
1448	/** Bit 3 - PWT - Page level write thru bit mask. */
1449	#define X86_PTE_PWT RT_BIT(3)
1450	/** Bit 4 - PCD - Page level cache disable bit mask. */
1451	#define X86_PTE_PCD RT_BIT(4)
1452	/** Bit 5 - A - Access bit mask. */
1453	#define X86_PTE_A RT_BIT(5)
1454	/** Bit 6 - D - Dirty bit mask. */
1455	#define X86_PTE_D RT_BIT(6)
1456	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1457	#define X86_PTE_PAT RT_BIT(7)
1458	/** Bit 8 - G - Global bit mask. */
1459	#define X86_PTE_G RT_BIT(8)
1460
1461	/** Bits 9-11 - - Available for use to system software. */
1462	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1463	/** Bits 12-31 - - Physical Page number of the next level. */
1464	#define X86_PTE_PG_MASK ( 0xfffff000 )
1465
1466	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1467	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1468	/** Bits 63 - NX - PAE/LM - No execution flag. */
1469	#define X86_PTE_PAE_NX RT_BIT_64(63)
1470	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1471	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1472	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1473	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1474	/** No bits - - LM - MBZ bits when NX is active. */
1475	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1476	/** Bits 63 - - LM - MBZ bits when no NX. */
1477	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1478
1479	/**
1480	* Page table entry.
1481	*/
1482	typedef struct X86PTEBITS
1483	{
1484	/** Flags whether(=1) or not the page is present. */
1485	uint32_t u1Present : 1;
1486	/** Read(=0) / Write(=1) flag. */
1487	uint32_t u1Write : 1;
1488	/** User(=1) / Supervisor (=0) flag. */
1489	uint32_t u1User : 1;
1490	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1491	uint32_t u1WriteThru : 1;
1492	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1493	uint32_t u1CacheDisable : 1;
1494	/** Accessed flag.
1495	* Indicates that the page have been read or written to. */
1496	uint32_t u1Accessed : 1;
1497	/** Dirty flag.
1498	* Indicates that the page has been written to. */
1499	uint32_t u1Dirty : 1;
1500	/** Reserved / If PAT enabled, bit 2 of the index. */
1501	uint32_t u1PAT : 1;
1502	/** Global flag. (Ignored in all but final level.) */
1503	uint32_t u1Global : 1;
1504	/** Available for use to system software. */
1505	uint32_t u3Available : 3;
1506	/** Physical Page number of the next level. */
1507	uint32_t u20PageNo : 20;
1508	} X86PTEBITS;
1509	#ifndef VBOX_FOR_DTRACE_LIB
1510	AssertCompileSize(X86PTEBITS, 4);
1511	#endif
1512	/** Pointer to a page table entry. */
1513	typedef X86PTEBITS *PX86PTEBITS;
1514	/** Pointer to a const page table entry. */
1515	typedef const X86PTEBITS *PCX86PTEBITS;
1516
1517	/**
1518	* Page table entry.
1519	*/
1520	typedef union X86PTE
1521	{
1522	/** Unsigned integer view */
1523	X86PGUINT u;
1524	/** Bit field view. */
1525	X86PTEBITS n;
1526	/** 32-bit view. */
1527	uint32_t au32[1];
1528	/** 16-bit view. */
1529	uint16_t au16[2];
1530	/** 8-bit view. */
1531	uint8_t au8[4];
1532	} X86PTE;
1533	#ifndef VBOX_FOR_DTRACE_LIB
1534	AssertCompileSize(X86PTE, 4);
1535	#endif
1536	/** Pointer to a page table entry. */
1537	typedef X86PTE *PX86PTE;
1538	/** Pointer to a const page table entry. */
1539	typedef const X86PTE *PCX86PTE;
1540
1541
1542	/**
1543	* PAE page table entry.
1544	*/
1545	typedef struct X86PTEPAEBITS
1546	{
1547	/** Flags whether(=1) or not the page is present. */
1548	uint32_t u1Present : 1;
1549	/** Read(=0) / Write(=1) flag. */
1550	uint32_t u1Write : 1;
1551	/** User(=1) / Supervisor(=0) flag. */
1552	uint32_t u1User : 1;
1553	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1554	uint32_t u1WriteThru : 1;
1555	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1556	uint32_t u1CacheDisable : 1;
1557	/** Accessed flag.
1558	* Indicates that the page have been read or written to. */
1559	uint32_t u1Accessed : 1;
1560	/** Dirty flag.
1561	* Indicates that the page has been written to. */
1562	uint32_t u1Dirty : 1;
1563	/** Reserved / If PAT enabled, bit 2 of the index. */
1564	uint32_t u1PAT : 1;
1565	/** Global flag. (Ignored in all but final level.) */
1566	uint32_t u1Global : 1;
1567	/** Available for use to system software. */
1568	uint32_t u3Available : 3;
1569	/** Physical Page number of the next level - Low Part. Don't use this. */
1570	uint32_t u20PageNoLow : 20;
1571	/** Physical Page number of the next level - High Part. Don't use this. */
1572	uint32_t u20PageNoHigh : 20;
1573	/** MBZ bits */
1574	uint32_t u11Reserved : 11;
1575	/** No Execute flag. */
1576	uint32_t u1NoExecute : 1;
1577	} X86PTEPAEBITS;
1578	#ifndef VBOX_FOR_DTRACE_LIB
1579	AssertCompileSize(X86PTEPAEBITS, 8);
1580	#endif
1581	/** Pointer to a page table entry. */
1582	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1583	/** Pointer to a page table entry. */
1584	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1585
1586	/**
1587	* PAE Page table entry.
1588	*/
1589	typedef union X86PTEPAE
1590	{
1591	/** Unsigned integer view */
1592	X86PGPAEUINT u;
1593	/** Bit field view. */
1594	X86PTEPAEBITS n;
1595	/** 32-bit view. */
1596	uint32_t au32[2];
1597	/** 16-bit view. */
1598	uint16_t au16[4];
1599	/** 8-bit view. */
1600	uint8_t au8[8];
1601	} X86PTEPAE;
1602	#ifndef VBOX_FOR_DTRACE_LIB
1603	AssertCompileSize(X86PTEPAE, 8);
1604	#endif
1605	/** Pointer to a PAE page table entry. */
1606	typedef X86PTEPAE *PX86PTEPAE;
1607	/** Pointer to a const PAE page table entry. */
1608	typedef const X86PTEPAE *PCX86PTEPAE;
1609	/** @} */
1610
1611	/**
1612	* Page table.
1613	*/
1614	typedef struct X86PT
1615	{
1616	/** PTE Array. */
1617	X86PTE a[X86_PG_ENTRIES];
1618	} X86PT;
1619	#ifndef VBOX_FOR_DTRACE_LIB
1620	AssertCompileSize(X86PT, 4096);
1621	#endif
1622	/** Pointer to a page table. */
1623	typedef X86PT *PX86PT;
1624	/** Pointer to a const page table. */
1625	typedef const X86PT *PCX86PT;
1626
1627	/** The page shift to get the PT index. */
1628	#define X86_PT_SHIFT 12
1629	/** The PT index mask (apply to a shifted page address). */
1630	#define X86_PT_MASK 0x3ff
1631
1632
1633	/**
1634	* Page directory.
1635	*/
1636	typedef struct X86PTPAE
1637	{
1638	/** PTE Array. */
1639	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1640	} X86PTPAE;
1641	#ifndef VBOX_FOR_DTRACE_LIB
1642	AssertCompileSize(X86PTPAE, 4096);
1643	#endif
1644	/** Pointer to a page table. */
1645	typedef X86PTPAE *PX86PTPAE;
1646	/** Pointer to a const page table. */
1647	typedef const X86PTPAE *PCX86PTPAE;
1648
1649	/** The page shift to get the PA PTE index. */
1650	#define X86_PT_PAE_SHIFT 12
1651	/** The PAE PT index mask (apply to a shifted page address). */
1652	#define X86_PT_PAE_MASK 0x1ff
1653
1654
1655	/** @name 4KB Page Directory Entry
1656	* @{
1657	*/
1658	/** Bit 0 - P - Present bit. */
1659	#define X86_PDE_P RT_BIT(0)
1660	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1661	#define X86_PDE_RW RT_BIT(1)
1662	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1663	#define X86_PDE_US RT_BIT(2)
1664	/** Bit 3 - PWT - Page level write thru bit. */
1665	#define X86_PDE_PWT RT_BIT(3)
1666	/** Bit 4 - PCD - Page level cache disable bit. */
1667	#define X86_PDE_PCD RT_BIT(4)
1668	/** Bit 5 - A - Access bit. */
1669	#define X86_PDE_A RT_BIT(5)
1670	/** Bit 7 - PS - Page size attribute.
1671	* Clear mean 4KB pages, set means large pages (2/4MB). */
1672	#define X86_PDE_PS RT_BIT(7)
1673	/** Bits 9-11 - - Available for use to system software. */
1674	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1675	/** Bits 12-31 - - Physical Page number of the next level. */
1676	#define X86_PDE_PG_MASK ( 0xfffff000 )
1677
1678	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1679	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1680	/** Bits 63 - NX - PAE/LM - No execution flag. */
1681	#define X86_PDE_PAE_NX RT_BIT_64(63)
1682	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1683	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1684	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1685	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1686	/** Bit 7 - - LM - MBZ bits when NX is active. */
1687	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1688	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1689	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1690
1691	/**
1692	* Page directory entry.
1693	*/
1694	typedef struct X86PDEBITS
1695	{
1696	/** Flags whether(=1) or not the page is present. */
1697	uint32_t u1Present : 1;
1698	/** Read(=0) / Write(=1) flag. */
1699	uint32_t u1Write : 1;
1700	/** User(=1) / Supervisor (=0) flag. */
1701	uint32_t u1User : 1;
1702	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1703	uint32_t u1WriteThru : 1;
1704	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1705	uint32_t u1CacheDisable : 1;
1706	/** Accessed flag.
1707	* Indicates that the page has been read or written to. */
1708	uint32_t u1Accessed : 1;
1709	/** Reserved / Ignored (dirty bit). */
1710	uint32_t u1Reserved0 : 1;
1711	/** Size bit if PSE is enabled - in any event it's 0. */
1712	uint32_t u1Size : 1;
1713	/** Reserved / Ignored (global bit). */
1714	uint32_t u1Reserved1 : 1;
1715	/** Available for use to system software. */
1716	uint32_t u3Available : 3;
1717	/** Physical Page number of the next level. */
1718	uint32_t u20PageNo : 20;
1719	} X86PDEBITS;
1720	#ifndef VBOX_FOR_DTRACE_LIB
1721	AssertCompileSize(X86PDEBITS, 4);
1722	#endif
1723	/** Pointer to a page directory entry. */
1724	typedef X86PDEBITS *PX86PDEBITS;
1725	/** Pointer to a const page directory entry. */
1726	typedef const X86PDEBITS *PCX86PDEBITS;
1727
1728
1729	/**
1730	* PAE page directory entry.
1731	*/
1732	typedef struct X86PDEPAEBITS
1733	{
1734	/** Flags whether(=1) or not the page is present. */
1735	uint32_t u1Present : 1;
1736	/** Read(=0) / Write(=1) flag. */
1737	uint32_t u1Write : 1;
1738	/** User(=1) / Supervisor (=0) flag. */
1739	uint32_t u1User : 1;
1740	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1741	uint32_t u1WriteThru : 1;
1742	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1743	uint32_t u1CacheDisable : 1;
1744	/** Accessed flag.
1745	* Indicates that the page has been read or written to. */
1746	uint32_t u1Accessed : 1;
1747	/** Reserved / Ignored (dirty bit). */
1748	uint32_t u1Reserved0 : 1;
1749	/** Size bit if PSE is enabled - in any event it's 0. */
1750	uint32_t u1Size : 1;
1751	/** Reserved / Ignored (global bit). / */
1752	uint32_t u1Reserved1 : 1;
1753	/** Available for use to system software. */
1754	uint32_t u3Available : 3;
1755	/** Physical Page number of the next level - Low Part. Don't use! */
1756	uint32_t u20PageNoLow : 20;
1757	/** Physical Page number of the next level - High Part. Don't use! */
1758	uint32_t u20PageNoHigh : 20;
1759	/** MBZ bits */
1760	uint32_t u11Reserved : 11;
1761	/** No Execute flag. */
1762	uint32_t u1NoExecute : 1;
1763	} X86PDEPAEBITS;
1764	#ifndef VBOX_FOR_DTRACE_LIB
1765	AssertCompileSize(X86PDEPAEBITS, 8);
1766	#endif
1767	/** Pointer to a page directory entry. */
1768	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1769	/** Pointer to a const page directory entry. */
1770	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1771
1772	/** @} */
1773
1774
1775	/** @name 2/4MB Page Directory Entry
1776	* @{
1777	*/
1778	/** Bit 0 - P - Present bit. */
1779	#define X86_PDE4M_P RT_BIT(0)
1780	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1781	#define X86_PDE4M_RW RT_BIT(1)
1782	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1783	#define X86_PDE4M_US RT_BIT(2)
1784	/** Bit 3 - PWT - Page level write thru bit. */
1785	#define X86_PDE4M_PWT RT_BIT(3)
1786	/** Bit 4 - PCD - Page level cache disable bit. */
1787	#define X86_PDE4M_PCD RT_BIT(4)
1788	/** Bit 5 - A - Access bit. */
1789	#define X86_PDE4M_A RT_BIT(5)
1790	/** Bit 6 - D - Dirty bit. */
1791	#define X86_PDE4M_D RT_BIT(6)
1792	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1793	#define X86_PDE4M_PS RT_BIT(7)
1794	/** Bit 8 - G - Global flag. */
1795	#define X86_PDE4M_G RT_BIT(8)
1796	/** Bits 9-11 - AVL - Available for use to system software. */
1797	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1798	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1799	#define X86_PDE4M_PAT RT_BIT(12)
1800	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1801	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1802	/** Bits 22-31 - - Physical Page number. */
1803	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1804	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1805	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1806	/** The number of bits to the high part of the page number. */
1807	#define X86_PDE4M_PG_HIGH_SHIFT 19
1808	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1809	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1810
1811	/** Bits 21-51 - - PAE/LM - Physical Page number.
1812	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1813	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1814	/** Bits 63 - NX - PAE/LM - No execution flag. */
1815	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1816	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1817	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1818	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1819	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1820	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1821	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1822	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1823	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1824
1825	/**
1826	* 4MB page directory entry.
1827	*/
1828	typedef struct X86PDE4MBITS
1829	{
1830	/** Flags whether(=1) or not the page is present. */
1831	uint32_t u1Present : 1;
1832	/** Read(=0) / Write(=1) flag. */
1833	uint32_t u1Write : 1;
1834	/** User(=1) / Supervisor (=0) flag. */
1835	uint32_t u1User : 1;
1836	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1837	uint32_t u1WriteThru : 1;
1838	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1839	uint32_t u1CacheDisable : 1;
1840	/** Accessed flag.
1841	* Indicates that the page have been read or written to. */
1842	uint32_t u1Accessed : 1;
1843	/** Dirty flag.
1844	* Indicates that the page has been written to. */
1845	uint32_t u1Dirty : 1;
1846	/** Page size flag - always 1 for 4MB entries. */
1847	uint32_t u1Size : 1;
1848	/** Global flag. */
1849	uint32_t u1Global : 1;
1850	/** Available for use to system software. */
1851	uint32_t u3Available : 3;
1852	/** Reserved / If PAT enabled, bit 2 of the index. */
1853	uint32_t u1PAT : 1;
1854	/** Bits 32-39 of the page number on AMD64.
1855	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1856	uint32_t u8PageNoHigh : 8;
1857	/** Reserved. */
1858	uint32_t u1Reserved : 1;
1859	/** Physical Page number of the page. */
1860	uint32_t u10PageNo : 10;
1861	} X86PDE4MBITS;
1862	#ifndef VBOX_FOR_DTRACE_LIB
1863	AssertCompileSize(X86PDE4MBITS, 4);
1864	#endif
1865	/** Pointer to a page table entry. */
1866	typedef X86PDE4MBITS *PX86PDE4MBITS;
1867	/** Pointer to a const page table entry. */
1868	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1869
1870
1871	/**
1872	* 2MB PAE page directory entry.
1873	*/
1874	typedef struct X86PDE2MPAEBITS
1875	{
1876	/** Flags whether(=1) or not the page is present. */
1877	uint32_t u1Present : 1;
1878	/** Read(=0) / Write(=1) flag. */
1879	uint32_t u1Write : 1;
1880	/** User(=1) / Supervisor(=0) flag. */
1881	uint32_t u1User : 1;
1882	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1883	uint32_t u1WriteThru : 1;
1884	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1885	uint32_t u1CacheDisable : 1;
1886	/** Accessed flag.
1887	* Indicates that the page have been read or written to. */
1888	uint32_t u1Accessed : 1;
1889	/** Dirty flag.
1890	* Indicates that the page has been written to. */
1891	uint32_t u1Dirty : 1;
1892	/** Page size flag - always 1 for 2MB entries. */
1893	uint32_t u1Size : 1;
1894	/** Global flag. */
1895	uint32_t u1Global : 1;
1896	/** Available for use to system software. */
1897	uint32_t u3Available : 3;
1898	/** Reserved / If PAT enabled, bit 2 of the index. */
1899	uint32_t u1PAT : 1;
1900	/** Reserved. */
1901	uint32_t u9Reserved : 9;
1902	/** Physical Page number of the next level - Low part. Don't use! */
1903	uint32_t u10PageNoLow : 10;
1904	/** Physical Page number of the next level - High part. Don't use! */
1905	uint32_t u20PageNoHigh : 20;
1906	/** MBZ bits */
1907	uint32_t u11Reserved : 11;
1908	/** No Execute flag. */
1909	uint32_t u1NoExecute : 1;
1910	} X86PDE2MPAEBITS;
1911	#ifndef VBOX_FOR_DTRACE_LIB
1912	AssertCompileSize(X86PDE2MPAEBITS, 8);
1913	#endif
1914	/** Pointer to a 2MB PAE page table entry. */
1915	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1916	/** Pointer to a 2MB PAE page table entry. */
1917	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1918
1919	/** @} */
1920
1921	/**
1922	* Page directory entry.
1923	*/
1924	typedef union X86PDE
1925	{
1926	/** Unsigned integer view. */
1927	X86PGUINT u;
1928	/** Normal view. */
1929	X86PDEBITS n;
1930	/** 4MB view (big). */
1931	X86PDE4MBITS b;
1932	/** 8 bit unsigned integer view. */
1933	uint8_t au8[4];
1934	/** 16 bit unsigned integer view. */
1935	uint16_t au16[2];
1936	/** 32 bit unsigned integer view. */
1937	uint32_t au32[1];
1938	} X86PDE;
1939	#ifndef VBOX_FOR_DTRACE_LIB
1940	AssertCompileSize(X86PDE, 4);
1941	#endif
1942	/** Pointer to a page directory entry. */
1943	typedef X86PDE *PX86PDE;
1944	/** Pointer to a const page directory entry. */
1945	typedef const X86PDE *PCX86PDE;
1946
1947	/**
1948	* PAE page directory entry.
1949	*/
1950	typedef union X86PDEPAE
1951	{
1952	/** Unsigned integer view. */
1953	X86PGPAEUINT u;
1954	/** Normal view. */
1955	X86PDEPAEBITS n;
1956	/** 2MB page view (big). */
1957	X86PDE2MPAEBITS b;
1958	/** 8 bit unsigned integer view. */
1959	uint8_t au8[8];
1960	/** 16 bit unsigned integer view. */
1961	uint16_t au16[4];
1962	/** 32 bit unsigned integer view. */
1963	uint32_t au32[2];
1964	} X86PDEPAE;
1965	#ifndef VBOX_FOR_DTRACE_LIB
1966	AssertCompileSize(X86PDEPAE, 8);
1967	#endif
1968	/** Pointer to a page directory entry. */
1969	typedef X86PDEPAE *PX86PDEPAE;
1970	/** Pointer to a const page directory entry. */
1971	typedef const X86PDEPAE *PCX86PDEPAE;
1972
1973	/**
1974	* Page directory.
1975	*/
1976	typedef struct X86PD
1977	{
1978	/** PDE Array. */
1979	X86PDE a[X86_PG_ENTRIES];
1980	} X86PD;
1981	#ifndef VBOX_FOR_DTRACE_LIB
1982	AssertCompileSize(X86PD, 4096);
1983	#endif
1984	/** Pointer to a page directory. */
1985	typedef X86PD *PX86PD;
1986	/** Pointer to a const page directory. */
1987	typedef const X86PD *PCX86PD;
1988
1989	/** The page shift to get the PD index. */
1990	#define X86_PD_SHIFT 22
1991	/** The PD index mask (apply to a shifted page address). */
1992	#define X86_PD_MASK 0x3ff
1993
1994
1995	/**
1996	* PAE page directory.
1997	*/
1998	typedef struct X86PDPAE
1999	{
2000	/** PDE Array. */
2001	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2002	} X86PDPAE;
2003	#ifndef VBOX_FOR_DTRACE_LIB
2004	AssertCompileSize(X86PDPAE, 4096);
2005	#endif
2006	/** Pointer to a PAE page directory. */
2007	typedef X86PDPAE *PX86PDPAE;
2008	/** Pointer to a const PAE page directory. */
2009	typedef const X86PDPAE *PCX86PDPAE;
2010
2011	/** The page shift to get the PAE PD index. */
2012	#define X86_PD_PAE_SHIFT 21
2013	/** The PAE PD index mask (apply to a shifted page address). */
2014	#define X86_PD_PAE_MASK 0x1ff
2015
2016
2017	/** @name Page Directory Pointer Table Entry (PAE)
2018	* @{
2019	*/
2020	/** Bit 0 - P - Present bit. */
2021	#define X86_PDPE_P RT_BIT(0)
2022	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2023	#define X86_PDPE_RW RT_BIT(1)
2024	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2025	#define X86_PDPE_US RT_BIT(2)
2026	/** Bit 3 - PWT - Page level write thru bit. */
2027	#define X86_PDPE_PWT RT_BIT(3)
2028	/** Bit 4 - PCD - Page level cache disable bit. */
2029	#define X86_PDPE_PCD RT_BIT(4)
2030	/** Bit 5 - A - Access bit. Long Mode only. */
2031	#define X86_PDPE_A RT_BIT(5)
2032	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2033	#define X86_PDPE_LM_PS RT_BIT(7)
2034	/** Bits 9-11 - - Available for use to system software. */
2035	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2036	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2037	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2038	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2039	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2040	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2041	#define X86_PDPE_LM_NX RT_BIT_64(63)
2042	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2043	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2044	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2045	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2046	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2047	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2048	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2049	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2050
2051
2052	/**
2053	* Page directory pointer table entry.
2054	*/
2055	typedef struct X86PDPEBITS
2056	{
2057	/** Flags whether(=1) or not the page is present. */
2058	uint32_t u1Present : 1;
2059	/** Chunk of reserved bits. */
2060	uint32_t u2Reserved : 2;
2061	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2062	uint32_t u1WriteThru : 1;
2063	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2064	uint32_t u1CacheDisable : 1;
2065	/** Chunk of reserved bits. */
2066	uint32_t u4Reserved : 4;
2067	/** Available for use to system software. */
2068	uint32_t u3Available : 3;
2069	/** Physical Page number of the next level - Low Part. Don't use! */
2070	uint32_t u20PageNoLow : 20;
2071	/** Physical Page number of the next level - High Part. Don't use! */
2072	uint32_t u20PageNoHigh : 20;
2073	/** MBZ bits */
2074	uint32_t u12Reserved : 12;
2075	} X86PDPEBITS;
2076	#ifndef VBOX_FOR_DTRACE_LIB
2077	AssertCompileSize(X86PDPEBITS, 8);
2078	#endif
2079	/** Pointer to a page directory pointer table entry. */
2080	typedef X86PDPEBITS *PX86PTPEBITS;
2081	/** Pointer to a const page directory pointer table entry. */
2082	typedef const X86PDPEBITS *PCX86PTPEBITS;
2083
2084	/**
2085	* Page directory pointer table entry. AMD64 version
2086	*/
2087	typedef struct X86PDPEAMD64BITS
2088	{
2089	/** Flags whether(=1) or not the page is present. */
2090	uint32_t u1Present : 1;
2091	/** Read(=0) / Write(=1) flag. */
2092	uint32_t u1Write : 1;
2093	/** User(=1) / Supervisor (=0) flag. */
2094	uint32_t u1User : 1;
2095	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2096	uint32_t u1WriteThru : 1;
2097	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2098	uint32_t u1CacheDisable : 1;
2099	/** Accessed flag.
2100	* Indicates that the page have been read or written to. */
2101	uint32_t u1Accessed : 1;
2102	/** Chunk of reserved bits. */
2103	uint32_t u3Reserved : 3;
2104	/** Available for use to system software. */
2105	uint32_t u3Available : 3;
2106	/** Physical Page number of the next level - Low Part. Don't use! */
2107	uint32_t u20PageNoLow : 20;
2108	/** Physical Page number of the next level - High Part. Don't use! */
2109	uint32_t u20PageNoHigh : 20;
2110	/** MBZ bits */
2111	uint32_t u11Reserved : 11;
2112	/** No Execute flag. */
2113	uint32_t u1NoExecute : 1;
2114	} X86PDPEAMD64BITS;
2115	#ifndef VBOX_FOR_DTRACE_LIB
2116	AssertCompileSize(X86PDPEAMD64BITS, 8);
2117	#endif
2118	/** Pointer to a page directory pointer table entry. */
2119	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2120	/** Pointer to a const page directory pointer table entry. */
2121	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2122
2123	/**
2124	* Page directory pointer table entry.
2125	*/
2126	typedef union X86PDPE
2127	{
2128	/** Unsigned integer view. */
2129	X86PGPAEUINT u;
2130	/** Normal view. */
2131	X86PDPEBITS n;
2132	/** AMD64 view. */
2133	X86PDPEAMD64BITS lm;
2134	/** 8 bit unsigned integer view. */
2135	uint8_t au8[8];
2136	/** 16 bit unsigned integer view. */
2137	uint16_t au16[4];
2138	/** 32 bit unsigned integer view. */
2139	uint32_t au32[2];
2140	} X86PDPE;
2141	#ifndef VBOX_FOR_DTRACE_LIB
2142	AssertCompileSize(X86PDPE, 8);
2143	#endif
2144	/** Pointer to a page directory pointer table entry. */
2145	typedef X86PDPE *PX86PDPE;
2146	/** Pointer to a const page directory pointer table entry. */
2147	typedef const X86PDPE *PCX86PDPE;
2148
2149
2150	/**
2151	* Page directory pointer table.
2152	*/
2153	typedef struct X86PDPT
2154	{
2155	/** PDE Array. */
2156	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2157	} X86PDPT;
2158	#ifndef VBOX_FOR_DTRACE_LIB
2159	AssertCompileSize(X86PDPT, 4096);
2160	#endif
2161	/** Pointer to a page directory pointer table. */
2162	typedef X86PDPT *PX86PDPT;
2163	/** Pointer to a const page directory pointer table. */
2164	typedef const X86PDPT *PCX86PDPT;
2165
2166	/** The page shift to get the PDPT index. */
2167	#define X86_PDPT_SHIFT 30
2168	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2169	#define X86_PDPT_MASK_PAE 0x3
2170	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2171	#define X86_PDPT_MASK_AMD64 0x1ff
2172
2173	/** @} */
2174
2175
2176	/** @name Page Map Level-4 Entry (Long Mode PAE)
2177	* @{
2178	*/
2179	/** Bit 0 - P - Present bit. */
2180	#define X86_PML4E_P RT_BIT(0)
2181	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2182	#define X86_PML4E_RW RT_BIT(1)
2183	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2184	#define X86_PML4E_US RT_BIT(2)
2185	/** Bit 3 - PWT - Page level write thru bit. */
2186	#define X86_PML4E_PWT RT_BIT(3)
2187	/** Bit 4 - PCD - Page level cache disable bit. */
2188	#define X86_PML4E_PCD RT_BIT(4)
2189	/** Bit 5 - A - Access bit. */
2190	#define X86_PML4E_A RT_BIT(5)
2191	/** Bits 9-11 - - Available for use to system software. */
2192	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2193	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2194	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2195	/** Bits 8, 7 - - MBZ bits when NX is active. */
2196	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2197	/** Bits 63, 7 - - MBZ bits when no NX. */
2198	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2199	/** Bits 63 - NX - PAE - No execution flag. */
2200	#define X86_PML4E_NX RT_BIT_64(63)
2201
2202	/**
2203	* Page Map Level-4 Entry
2204	*/
2205	typedef struct X86PML4EBITS
2206	{
2207	/** Flags whether(=1) or not the page is present. */
2208	uint32_t u1Present : 1;
2209	/** Read(=0) / Write(=1) flag. */
2210	uint32_t u1Write : 1;
2211	/** User(=1) / Supervisor (=0) flag. */
2212	uint32_t u1User : 1;
2213	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2214	uint32_t u1WriteThru : 1;
2215	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2216	uint32_t u1CacheDisable : 1;
2217	/** Accessed flag.
2218	* Indicates that the page have been read or written to. */
2219	uint32_t u1Accessed : 1;
2220	/** Chunk of reserved bits. */
2221	uint32_t u3Reserved : 3;
2222	/** Available for use to system software. */
2223	uint32_t u3Available : 3;
2224	/** Physical Page number of the next level - Low Part. Don't use! */
2225	uint32_t u20PageNoLow : 20;
2226	/** Physical Page number of the next level - High Part. Don't use! */
2227	uint32_t u20PageNoHigh : 20;
2228	/** MBZ bits */
2229	uint32_t u11Reserved : 11;
2230	/** No Execute flag. */
2231	uint32_t u1NoExecute : 1;
2232	} X86PML4EBITS;
2233	#ifndef VBOX_FOR_DTRACE_LIB
2234	AssertCompileSize(X86PML4EBITS, 8);
2235	#endif
2236	/** Pointer to a page map level-4 entry. */
2237	typedef X86PML4EBITS *PX86PML4EBITS;
2238	/** Pointer to a const page map level-4 entry. */
2239	typedef const X86PML4EBITS *PCX86PML4EBITS;
2240
2241	/**
2242	* Page Map Level-4 Entry.
2243	*/
2244	typedef union X86PML4E
2245	{
2246	/** Unsigned integer view. */
2247	X86PGPAEUINT u;
2248	/** Normal view. */
2249	X86PML4EBITS n;
2250	/** 8 bit unsigned integer view. */
2251	uint8_t au8[8];
2252	/** 16 bit unsigned integer view. */
2253	uint16_t au16[4];
2254	/** 32 bit unsigned integer view. */
2255	uint32_t au32[2];
2256	} X86PML4E;
2257	#ifndef VBOX_FOR_DTRACE_LIB
2258	AssertCompileSize(X86PML4E, 8);
2259	#endif
2260	/** Pointer to a page map level-4 entry. */
2261	typedef X86PML4E *PX86PML4E;
2262	/** Pointer to a const page map level-4 entry. */
2263	typedef const X86PML4E *PCX86PML4E;
2264
2265
2266	/**
2267	* Page Map Level-4.
2268	*/
2269	typedef struct X86PML4
2270	{
2271	/** PDE Array. */
2272	X86PML4E a[X86_PG_PAE_ENTRIES];
2273	} X86PML4;
2274	#ifndef VBOX_FOR_DTRACE_LIB
2275	AssertCompileSize(X86PML4, 4096);
2276	#endif
2277	/** Pointer to a page map level-4. */
2278	typedef X86PML4 *PX86PML4;
2279	/** Pointer to a const page map level-4. */
2280	typedef const X86PML4 *PCX86PML4;
2281
2282	/** The page shift to get the PML4 index. */
2283	#define X86_PML4_SHIFT 39
2284	/** The PML4 index mask (apply to a shifted page address). */
2285	#define X86_PML4_MASK 0x1ff
2286
2287	/** @} */
2288
2289	/** @} */
2290
2291	/**
2292	* 32-bit protected mode FSTENV image.
2293	*/
2294	typedef struct X86FSTENV32P
2295	{
2296	uint16_t FCW;
2297	uint16_t padding1;
2298	uint16_t FSW;
2299	uint16_t padding2;
2300	uint16_t FTW;
2301	uint16_t padding3;
2302	uint32_t FPUIP;
2303	uint16_t FPUCS;
2304	uint16_t FOP;
2305	uint32_t FPUDP;
2306	uint16_t FPUDS;
2307	uint16_t padding4;
2308	} X86FSTENV32P;
2309	/** Pointer to a 32-bit protected mode FSTENV image. */
2310	typedef X86FSTENV32P *PX86FSTENV32P;
2311	/** Pointer to a const 32-bit protected mode FSTENV image. */
2312	typedef X86FSTENV32P const *PCX86FSTENV32P;
2313
2314
2315	/**
2316	* 80-bit MMX/FPU register type.
2317	*/
2318	typedef struct X86FPUMMX
2319	{
2320	uint8_t reg[10];
2321	} X86FPUMMX;
2322	#ifndef VBOX_FOR_DTRACE_LIB
2323	AssertCompileSize(X86FPUMMX, 10);
2324	#endif
2325	/** Pointer to a 80-bit MMX/FPU register type. */
2326	typedef X86FPUMMX *PX86FPUMMX;
2327	/** Pointer to a const 80-bit MMX/FPU register type. */
2328	typedef const X86FPUMMX *PCX86FPUMMX;
2329
2330	/** FPU (x87) register. */
2331	typedef union X86FPUREG
2332	{
2333	/** MMX view. */
2334	uint64_t mmx;
2335	/** FPU view - todo. */
2336	X86FPUMMX fpu;
2337	/** Extended precision floating point view. */
2338	RTFLOAT80U r80;
2339	/** Extended precision floating point view v2 */
2340	RTFLOAT80U2 r80Ex;
2341	/** 8-bit view. */
2342	uint8_t au8[16];
2343	/** 16-bit view. */
2344	uint16_t au16[8];
2345	/** 32-bit view. */
2346	uint32_t au32[4];
2347	/** 64-bit view. */
2348	uint64_t au64[2];
2349	/** 128-bit view. (yeah, very helpful) */
2350	uint128_t au128[1];
2351	} X86FPUREG;
2352	#ifndef VBOX_FOR_DTRACE_LIB
2353	AssertCompileSize(X86FPUREG, 16);
2354	#endif
2355	/** Pointer to a FPU register. */
2356	typedef X86FPUREG *PX86FPUREG;
2357	/** Pointer to a const FPU register. */
2358	typedef X86FPUREG const *PCX86FPUREG;
2359
2360	/**
2361	* XMM register union.
2362	*/
2363	typedef union X86XMMREG
2364	{
2365	/** XMM Register view . /
2366	uint128_t xmm;
2367	/** 8-bit view. */
2368	uint8_t au8[16];
2369	/** 16-bit view. */
2370	uint16_t au16[8];
2371	/** 32-bit view. */
2372	uint32_t au32[4];
2373	/** 64-bit view. */
2374	uint64_t au64[2];
2375	/** 128-bit view. (yeah, very helpful) */
2376	uint128_t au128[1];
2377	} X86XMMREG;
2378	#ifndef VBOX_FOR_DTRACE_LIB
2379	AssertCompileSize(X86XMMREG, 16);
2380	#endif
2381	/** Pointer to an XMM register state. */
2382	typedef X86XMMREG *PX86XMMREG;
2383	/** Pointer to a const XMM register state. */
2384	typedef X86XMMREG const *PCX86XMMREG;
2385
2386	/**
2387	* YMM register union.
2388	*/
2389	typedef union X86YMMREG
2390	{
2391	/** 8-bit view. */
2392	uint8_t au8[32];
2393	/** 16-bit view. */
2394	uint16_t au16[16];
2395	/** 32-bit view. */
2396	uint32_t au32[8];
2397	/** 64-bit view. */
2398	uint64_t au64[4];
2399	/** 128-bit view. (yeah, very helpful) */
2400	uint128_t au128[2];
2401	/** XMM sub register view. */
2402	X86XMMREG aXmm[2];
2403	} X86YMMREG;
2404	#ifndef VBOX_FOR_DTRACE_LIB
2405	AssertCompileSize(X86YMMREG, 32);
2406	#endif
2407	/** Pointer to an YMM register state. */
2408	typedef X86YMMREG *PX86YMMREG;
2409	/** Pointer to a const YMM register state. */
2410	typedef X86YMMREG const *PCX86YMMREG;
2411
2412	/**
2413	* ZMM register union.
2414	*/
2415	typedef union X86ZMMREG
2416	{
2417	/** 8-bit view. */
2418	uint8_t au8[64];
2419	/** 16-bit view. */
2420	uint16_t au16[32];
2421	/** 32-bit view. */
2422	uint32_t au32[16];
2423	/** 64-bit view. */
2424	uint64_t au64[8];
2425	/** 128-bit view. (yeah, very helpful) */
2426	uint128_t au128[4];
2427	/** XMM sub register view. */
2428	X86XMMREG aXmm[4];
2429	/** YMM sub register view. */
2430	X86YMMREG aYmm[2];
2431	} X86ZMMREG;
2432	#ifndef VBOX_FOR_DTRACE_LIB
2433	AssertCompileSize(X86ZMMREG, 64);
2434	#endif
2435	/** Pointer to an ZMM register state. */
2436	typedef X86ZMMREG *PX86ZMMREG;
2437	/** Pointer to a const ZMM register state. */
2438	typedef X86ZMMREG const *PCX86ZMMREG;
2439
2440
2441	/**
2442	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2443	* @todo verify this...
2444	*/
2445	#pragma pack(1)
2446	typedef struct X86FPUSTATE
2447	{
2448	/** 0x00 - Control word. */
2449	uint16_t FCW;
2450	/** 0x02 - Alignment word */
2451	uint16_t Dummy1;
2452	/** 0x04 - Status word. */
2453	uint16_t FSW;
2454	/** 0x06 - Alignment word */
2455	uint16_t Dummy2;
2456	/** 0x08 - Tag word */
2457	uint16_t FTW;
2458	/** 0x0a - Alignment word */
2459	uint16_t Dummy3;
2460
2461	/** 0x0c - Instruction pointer. */
2462	uint32_t FPUIP;
2463	/** 0x10 - Code selector. */
2464	uint16_t CS;
2465	/** 0x12 - Opcode. */
2466	uint16_t FOP;
2467	/** 0x14 - FOO. */
2468	uint32_t FPUOO;
2469	/** 0x18 - FOS. */
2470	uint32_t FPUOS;
2471	/** 0x1c - FPU register. */
2472	X86FPUREG regs[8];
2473	} X86FPUSTATE;
2474	#pragma pack()
2475	/** Pointer to a FPU state. */
2476	typedef X86FPUSTATE *PX86FPUSTATE;
2477	/** Pointer to a const FPU state. */
2478	typedef const X86FPUSTATE *PCX86FPUSTATE;
2479
2480	/**
2481	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2482	*/
2483	#pragma pack(1)
2484	typedef struct X86FXSTATE
2485	{
2486	/** 0x00 - Control word. */
2487	uint16_t FCW;
2488	/** 0x02 - Status word. */
2489	uint16_t FSW;
2490	/** 0x04 - Tag word. (The upper byte is always zero.) */
2491	uint16_t FTW;
2492	/** 0x06 - Opcode. */
2493	uint16_t FOP;
2494	/** 0x08 - Instruction pointer. */
2495	uint32_t FPUIP;
2496	/** 0x0c - Code selector. */
2497	uint16_t CS;
2498	uint16_t Rsrvd1;
2499	/** 0x10 - Data pointer. */
2500	uint32_t FPUDP;
2501	/** 0x14 - Data segment */
2502	uint16_t DS;
2503	/** 0x16 */
2504	uint16_t Rsrvd2;
2505	/** 0x18 */
2506	uint32_t MXCSR;
2507	/** 0x1c */
2508	uint32_t MXCSR_MASK;
2509	/** 0x20 - FPU registers. */
2510	X86FPUREG aRegs[8];
2511	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
2512	X86XMMREG aXMM[16];
2513	/* - offset 416 - */
2514	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2515	/* - offset 464 - Software usable reserved bits. */
2516	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2517	} X86FXSTATE;
2518	#pragma pack()
2519	/** Pointer to a FPU Extended state. */
2520	typedef X86FXSTATE *PX86FXSTATE;
2521	/** Pointer to a const FPU Extended state. */
2522	typedef const X86FXSTATE *PCX86FXSTATE;
2523
2524	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2525	* magic. Don't forget to update x86.mac if you change this! */
2526	#define X86_OFF_FXSTATE_RSVD 0x1d0
2527	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2528	* forget to update x86.mac if you change this!
2529	* @todo r=bird: This has nothing what-so-ever to do here.... */
2530	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2531	#ifndef VBOX_FOR_DTRACE_LIB
2532	AssertCompileSize(X86FXSTATE, 512);
2533	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2534	#endif
2535
2536	/** @name FPU status word flags.
2537	* @{ */
2538	/** Exception Flag: Invalid operation. */
2539	#define X86_FSW_IE RT_BIT(0)
2540	/** Exception Flag: Denormalized operand. */
2541	#define X86_FSW_DE RT_BIT(1)
2542	/** Exception Flag: Zero divide. */
2543	#define X86_FSW_ZE RT_BIT(2)
2544	/** Exception Flag: Overflow. */
2545	#define X86_FSW_OE RT_BIT(3)
2546	/** Exception Flag: Underflow. */
2547	#define X86_FSW_UE RT_BIT(4)
2548	/** Exception Flag: Precision. */
2549	#define X86_FSW_PE RT_BIT(5)
2550	/** Stack fault. */
2551	#define X86_FSW_SF RT_BIT(6)
2552	/** Error summary status. */
2553	#define X86_FSW_ES RT_BIT(7)
2554	/** Mask of exceptions flags, excluding the summary bit. */
2555	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2556	/** Mask of exceptions flags, including the summary bit. */
2557	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2558	/** Condition code 0. */
2559	#define X86_FSW_C0 RT_BIT(8)
2560	/** Condition code 1. */
2561	#define X86_FSW_C1 RT_BIT(9)
2562	/** Condition code 2. */
2563	#define X86_FSW_C2 RT_BIT(10)
2564	/** Top of the stack mask. */
2565	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2566	/** TOP shift value. */
2567	#define X86_FSW_TOP_SHIFT 11
2568	/** Mask for getting TOP value after shifting it right. */
2569	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2570	/** Get the TOP value. */
2571	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2572	/** Condition code 3. */
2573	#define X86_FSW_C3 RT_BIT(14)
2574	/** Mask of exceptions flags, including the summary bit. */
2575	#define X86_FSW_C_MASK UINT16_C(0x4700)
2576	/** FPU busy. */
2577	#define X86_FSW_B RT_BIT(15)
2578	/** @} */
2579
2580
2581	/** @name FPU control word flags.
2582	* @{ */
2583	/** Exception Mask: Invalid operation. */
2584	#define X86_FCW_IM RT_BIT(0)
2585	/** Exception Mask: Denormalized operand. */
2586	#define X86_FCW_DM RT_BIT(1)
2587	/** Exception Mask: Zero divide. */
2588	#define X86_FCW_ZM RT_BIT(2)
2589	/** Exception Mask: Overflow. */
2590	#define X86_FCW_OM RT_BIT(3)
2591	/** Exception Mask: Underflow. */
2592	#define X86_FCW_UM RT_BIT(4)
2593	/** Exception Mask: Precision. */
2594	#define X86_FCW_PM RT_BIT(5)
2595	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2596	* @remarks This includes reserved bit 6. */
2597	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2598	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2599	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2600	/** Precision control mask. */
2601	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2602	/** Precision control: 24-bit. */
2603	#define X86_FCW_PC_24 UINT16_C(0x0000)
2604	/** Precision control: Reserved. */
2605	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2606	/** Precision control: 53-bit. */
2607	#define X86_FCW_PC_53 UINT16_C(0x0200)
2608	/** Precision control: 64-bit. */
2609	#define X86_FCW_PC_64 UINT16_C(0x0300)
2610	/** Rounding control mask. */
2611	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2612	/** Rounding control: To nearest. */
2613	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2614	/** Rounding control: Down. */
2615	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2616	/** Rounding control: Up. */
2617	#define X86_FCW_RC_UP UINT16_C(0x0800)
2618	/** Rounding control: Towards zero. */
2619	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2620	/** Bits which should be zero, apparently. */
2621	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2622	/** @} */
2623
2624	/** @name SSE MXCSR
2625	* @{ */
2626	/** Exception Flag: Invalid operation. */
2627	#define X86_MXSCR_IE RT_BIT(0)
2628	/** Exception Flag: Denormalized operand. */
2629	#define X86_MXSCR_DE RT_BIT(1)
2630	/** Exception Flag: Zero divide. */
2631	#define X86_MXSCR_ZE RT_BIT(2)
2632	/** Exception Flag: Overflow. */
2633	#define X86_MXSCR_OE RT_BIT(3)
2634	/** Exception Flag: Underflow. */
2635	#define X86_MXSCR_UE RT_BIT(4)
2636	/** Exception Flag: Precision. */
2637	#define X86_MXSCR_PE RT_BIT(5)
2638
2639	/** Denormals are zero. */
2640	#define X86_MXSCR_DAZ RT_BIT(6)
2641
2642	/** Exception Mask: Invalid operation. */
2643	#define X86_MXSCR_IM RT_BIT(7)
2644	/** Exception Mask: Denormalized operand. */
2645	#define X86_MXSCR_DM RT_BIT(8)
2646	/** Exception Mask: Zero divide. */
2647	#define X86_MXSCR_ZM RT_BIT(9)
2648	/** Exception Mask: Overflow. */
2649	#define X86_MXSCR_OM RT_BIT(10)
2650	/** Exception Mask: Underflow. */
2651	#define X86_MXSCR_UM RT_BIT(11)
2652	/** Exception Mask: Precision. */
2653	#define X86_MXSCR_PM RT_BIT(12)
2654
2655	/** Rounding control mask. */
2656	#define X86_MXSCR_RC_MASK UINT16_C(0x6000)
2657	/** Rounding control: To nearest. */
2658	#define X86_MXSCR_RC_NEAREST UINT16_C(0x0000)
2659	/** Rounding control: Down. */
2660	#define X86_MXSCR_RC_DOWN UINT16_C(0x2000)
2661	/** Rounding control: Up. */
2662	#define X86_MXSCR_RC_UP UINT16_C(0x4000)
2663	/** Rounding control: Towards zero. */
2664	#define X86_MXSCR_RC_ZERO UINT16_C(0x6000)
2665
2666	/** Flush-to-zero for masked underflow. */
2667	#define X86_MXSCR_FZ RT_BIT(15)
2668
2669	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
2670	#define X86_MXSCR_MM RT_BIT(17)
2671	/** @} */
2672
2673	/**
2674	* XSAVE header.
2675	*/
2676	typedef struct X86XSAVEHDR
2677	{
2678	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
2679	uint64_t bmXState;
2680	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
2681	uint64_t bmXComp;
2682	/** Reserved for furture extensions, probably MBZ. */
2683	uint64_t au64Reserved[6];
2684	} X86XSAVEHDR;
2685	#ifndef VBOX_FOR_DTRACE_LIB
2686	AssertCompileSize(X86XSAVEHDR, 64);
2687	#endif
2688	/** Pointer to an XSAVE header. */
2689	typedef X86XSAVEHDR *PX86XSAVEHDR;
2690	/** Pointer to a const XSAVE header. */
2691	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
2692
2693
2694	/**
2695	* The high 128-bit YMM register state (XSAVE_C_YMM).
2696	* (The lower 128-bits being in X86FXSTATE.)
2697	*/
2698	typedef struct X86XSAVEYMMHI
2699	{
2700	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
2701	X86XMMREG aYmmHi[16];
2702	} X86XSAVEYMMHI;
2703	#ifndef VBOX_FOR_DTRACE_LIB
2704	AssertCompileSize(X86XSAVEYMMHI, 256);
2705	#endif
2706	/** Pointer to a high 128-bit YMM register state. */
2707	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
2708	/** Pointer to a const high 128-bit YMM register state. */
2709	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
2710
2711	/**
2712	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
2713	*/
2714	typedef struct X86XSAVEBNDREGS
2715	{
2716	/** Array of registers (BND0...BND3). */
2717	struct
2718	{
2719	/** Lower bound. */
2720	uint64_t uLowerBound;
2721	/** Upper bound. */
2722	uint64_t uUpperBound;
2723	} aRegs[4];
2724	} X86XSAVEBNDREGS;
2725	#ifndef VBOX_FOR_DTRACE_LIB
2726	AssertCompileSize(X86XSAVEBNDREGS, 64);
2727	#endif
2728	/** Pointer to a MPX bound register state. */
2729	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
2730	/** Pointer to a const MPX bound register state. */
2731	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
2732
2733	/**
2734	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
2735	*/
2736	typedef struct X86XSAVEBNDCFG
2737	{
2738	uint64_t fConfig;
2739	uint64_t fStatus;
2740	} X86XSAVEBNDCFG;
2741	#ifndef VBOX_FOR_DTRACE_LIB
2742	AssertCompileSize(X86XSAVEBNDCFG, 16);
2743	#endif
2744	/** Pointer to a MPX bound config and status register state. */
2745	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
2746	/** Pointer to a const MPX bound config and status register state. */
2747	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
2748
2749	/**
2750	* AVX-512 opmask state (XSAVE_C_OPMASK).
2751	*/
2752	typedef struct X86XSAVEOPMASK
2753	{
2754	/** The K0..K7 values. */
2755	uint64_t aKRegs[8];
2756	} X86XSAVEOPMASK;
2757	#ifndef VBOX_FOR_DTRACE_LIB
2758	AssertCompileSize(X86XSAVEOPMASK, 64);
2759	#endif
2760	/** Pointer to a AVX-512 opmask state. */
2761	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
2762	/** Pointer to a const AVX-512 opmask state. */
2763	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
2764
2765	/**
2766	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
2767	*/
2768	typedef struct X86XSAVEZMMHI256
2769	{
2770	/** Upper 256-bits of ZMM0-15. */
2771	X86YMMREG aHi256Regs[16];
2772	} X86XSAVEZMMHI256;
2773	#ifndef VBOX_FOR_DTRACE_LIB
2774	AssertCompileSize(X86XSAVEZMMHI256, 512);
2775	#endif
2776	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
2777	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
2778	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
2779	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
2780
2781	/**
2782	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
2783	*/
2784	typedef struct X86XSAVEZMM16HI
2785	{
2786	/** ZMM16 thru ZMM31. */
2787	X86ZMMREG aRegs[16];
2788	} X86XSAVEZMM16HI;
2789	#ifndef VBOX_FOR_DTRACE_LIB
2790	AssertCompileSize(X86XSAVEZMM16HI, 1024);
2791	#endif
2792	/** Pointer to a state comprising ZMM16-32. */
2793	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
2794	/** Pointer to a const state comprising ZMM16-32. */
2795	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
2796
2797	/**
2798	* AMD Light weight profiling state (XSAVE_C_LWP).
2799	*
2800	* We probably won't play with this as AMD seems to be dropping from their "zen"
2801	* processor micro architecture.
2802	*/
2803	typedef struct X86XSAVELWP
2804	{
2805	/** Details when needed. */
2806	uint64_t auLater[128/8];
2807	} X86XSAVELWP;
2808	#ifndef VBOX_FOR_DTRACE_LIB
2809	AssertCompileSize(X86XSAVELWP, 128);
2810	#endif
2811
2812
2813	/**
2814	* x86 FPU/SSE/AVX/XXXX state.
2815	*
2816	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
2817	* changes to this structure.
2818	*/
2819	typedef struct X86XSAVEAREA
2820	{
2821	/** The x87 and SSE region (or legacy region if you like). */
2822	X86FXSTATE x87;
2823	/** The XSAVE header. */
2824	X86XSAVEHDR Hdr;
2825	/** Beyond the header, there isn't really a fixed layout, but we can
2826	generally assume the YMM (AVX) register extensions are present and
2827	follows immediately. */
2828	union
2829	{
2830	/** This is a typical layout on intel CPUs (good for debuggers). */
2831	struct
2832	{
2833	X86XSAVEYMMHI YmmHi;
2834	X86XSAVEBNDREGS BndRegs;
2835	X86XSAVEBNDCFG BndCfg;
2836	uint8_t abFudgeToMatchDocs[0xB0];
2837	X86XSAVEOPMASK Opmask;
2838	X86XSAVEZMMHI256 ZmmHi256;
2839	X86XSAVEZMM16HI Zmm16Hi;
2840	} Intel;
2841
2842	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
2843	struct
2844	{
2845	X86XSAVEYMMHI YmmHi;
2846	X86XSAVELWP Lwp;
2847	} AmdBd;
2848
2849	/** To enbling static deployments that have a reasonable chance of working for
2850	* the next 3-6 CPU generations without running short on space, we allocate a
2851	* lot of extra space here, making the structure a round 8KB in size. This
2852	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
2853	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
2854	uint8_t ab[8192 - 512 - 64];
2855	} u;
2856	} X86XSAVEAREA;
2857	#ifndef VBOX_FOR_DTRACE_LIB
2858	AssertCompileSize(X86XSAVEAREA, 8192);
2859	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
2860	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
2861	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
2862	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
2863	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
2864	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
2865	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
2866	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
2867	#endif
2868	/** Pointer to a XSAVE area. */
2869	typedef X86XSAVEAREA *PX86XSAVEAREA;
2870	/** Pointer to a const XSAVE area. */
2871	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
2872
2873
2874	/** @name XSAVE_C_XXX - XSAVE State Components Bits.
2875	* @{ */
2876	/** Bit 0 - x87 - Legacy FPU state (bit number) */
2877	#define XSAVE_C_X87_BIT 0
2878	/** Bit 0 - x87 - Legacy FPU state. */
2879	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
2880	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
2881	#define XSAVE_C_SSE_BIT 1
2882	/** Bit 1 - SSE - 128-bit SSE state. */
2883	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
2884	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
2885	#define XSAVE_C_YMM_BIT 2
2886	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
2887	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
2888	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
2889	#define XSAVE_C_BNDREGS_BIT 3
2890	/** Bit 3 - BNDREGS - MPX bound register state. */
2891	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
2892	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
2893	#define XSAVE_C_BNDCSR_BIT 4
2894	/** Bit 4 - BNDCSR - MPX bound config and status state. */
2895	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
2896	/** Bit 5 - Opmask - opmask state (bit number). */
2897	#define XSAVE_C_OPMASK_BIT 5
2898	/** Bit 5 - Opmask - opmask state. */
2899	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
2900	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
2901	#define XSAVE_C_ZMM_HI256_BIT 6
2902	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
2903	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
2904	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
2905	#define XSAVE_C_ZMM_16HI_BIT 7
2906	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
2907	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
2908	/** Bit 9 - PKRU - Protection-key state (bit number). */
2909	#define XSAVE_C_PKRU_BIT 9
2910	/** Bit 9 - PKRU - Protection-key state. */
2911	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
2912	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
2913	#define XSAVE_C_LWP_BIT 62
2914	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
2915	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
2916	/** @} */
2917
2918
2919
2920	/** @name Selector Descriptor
2921	* @{
2922	*/
2923
2924	#ifndef VBOX_FOR_DTRACE_LIB
2925	/**
2926	* Descriptor attributes (as seen by VT-x).
2927	*/
2928	typedef struct X86DESCATTRBITS
2929	{
2930	/** 00 - Segment Type. */
2931	unsigned u4Type : 4;
2932	/** 04 - Descriptor Type. System(=0) or code/data selector */
2933	unsigned u1DescType : 1;
2934	/** 05 - Descriptor Privilege level. */
2935	unsigned u2Dpl : 2;
2936	/** 07 - Flags selector present(=1) or not. */
2937	unsigned u1Present : 1;
2938	/** 08 - Segment limit 16-19. */
2939	unsigned u4LimitHigh : 4;
2940	/** 0c - Available for system software. */
2941	unsigned u1Available : 1;
2942	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2943	unsigned u1Long : 1;
2944	/** 0e - This flags meaning depends on the segment type. Try make sense out
2945	* of the intel manual yourself. */
2946	unsigned u1DefBig : 1;
2947	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2948	* clear byte. */
2949	unsigned u1Granularity : 1;
2950	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
2951	unsigned u1Unusable : 1;
2952	} X86DESCATTRBITS;
2953	#endif /* !VBOX_FOR_DTRACE_LIB */
2954
2955	/** @name X86DESCATTR masks
2956	* @{ */
2957	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
2958	#define X86DESCATTR_DT UINT32_C(0x00000010)
2959	#define X86DESCATTR_DPL UINT32_C(0x00000060)
2960	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
2961	#define X86DESCATTR_P UINT32_C(0x00000080)
2962	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
2963	#define X86DESCATTR_AVL UINT32_C(0x00001000)
2964	#define X86DESCATTR_L UINT32_C(0x00002000)
2965	#define X86DESCATTR_D UINT32_C(0x00004000)
2966	#define X86DESCATTR_G UINT32_C(0x00008000)
2967	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
2968	/** @} */
2969
2970	#pragma pack(1)
2971	typedef union X86DESCATTR
2972	{
2973	/** Unsigned integer view. */
2974	uint32_t u;
2975	#ifndef VBOX_FOR_DTRACE_LIB
2976	/** Normal view. */
2977	X86DESCATTRBITS n;
2978	#endif
2979	} X86DESCATTR;
2980	#pragma pack()
2981	/** Pointer to descriptor attributes. */
2982	typedef X86DESCATTR *PX86DESCATTR;
2983	/** Pointer to const descriptor attributes. */
2984	typedef const X86DESCATTR *PCX86DESCATTR;
2985
2986	#ifndef VBOX_FOR_DTRACE_LIB
2987
2988	/**
2989	* Generic descriptor table entry
2990	*/
2991	#pragma pack(1)
2992	typedef struct X86DESCGENERIC
2993	{
2994	/** 00 - Limit - Low word. */
2995	unsigned u16LimitLow : 16;
2996	/** 10 - Base address - lowe word.
2997	* Don't try set this to 24 because MSC is doing stupid things then. */
2998	unsigned u16BaseLow : 16;
2999	/** 20 - Base address - first 8 bits of high word. */
3000	unsigned u8BaseHigh1 : 8;
3001	/** 28 - Segment Type. */
3002	unsigned u4Type : 4;
3003	/** 2c - Descriptor Type. System(=0) or code/data selector */
3004	unsigned u1DescType : 1;
3005	/** 2d - Descriptor Privilege level. */
3006	unsigned u2Dpl : 2;
3007	/** 2f - Flags selector present(=1) or not. */
3008	unsigned u1Present : 1;
3009	/** 30 - Segment limit 16-19. */
3010	unsigned u4LimitHigh : 4;
3011	/** 34 - Available for system software. */
3012	unsigned u1Available : 1;
3013	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3014	unsigned u1Long : 1;
3015	/** 36 - This flags meaning depends on the segment type. Try make sense out
3016	* of the intel manual yourself. */
3017	unsigned u1DefBig : 1;
3018	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
3019	* clear byte. */
3020	unsigned u1Granularity : 1;
3021	/** 38 - Base address - highest 8 bits. */
3022	unsigned u8BaseHigh2 : 8;
3023	} X86DESCGENERIC;
3024	#pragma pack()
3025	/** Pointer to a generic descriptor entry. */
3026	typedef X86DESCGENERIC *PX86DESCGENERIC;
3027	/** Pointer to a const generic descriptor entry. */
3028	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3029
3030	/** @name Bit offsets of X86DESCGENERIC members.
3031	* @{*/
3032	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
3033	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
3034	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
3035	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
3036	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
3037	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
3038	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
3039	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
3040	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
3041	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
3042	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
3043	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
3044	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
3045	/** @} */
3046
3047	/**
3048	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3049	*/
3050	typedef struct X86DESCGATE
3051	{
3052	/** 00 - Target code segment offset - Low word.
3053	* Ignored if task-gate. */
3054	unsigned u16OffsetLow : 16;
3055	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3056	* TSS selector if task-gate. */
3057	unsigned u16Sel : 16;
3058	/** 20 - Number of parameters for a call-gate.
3059	* Ignored if interrupt-, trap- or task-gate. */
3060	unsigned u4ParmCount : 4;
3061	/** 24 - Reserved / ignored. */
3062	unsigned u4Reserved : 4;
3063	/** 28 - Segment Type. */
3064	unsigned u4Type : 4;
3065	/** 2c - Descriptor Type (0 = system). */
3066	unsigned u1DescType : 1;
3067	/** 2d - Descriptor Privilege level. */
3068	unsigned u2Dpl : 2;
3069	/** 2f - Flags selector present(=1) or not. */
3070	unsigned u1Present : 1;
3071	/** 30 - Target code segment offset - High word.
3072	* Ignored if task-gate. */
3073	unsigned u16OffsetHigh : 16;
3074	} X86DESCGATE;
3075	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3076	typedef X86DESCGATE *PX86DESCGATE;
3077	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3078	typedef const X86DESCGATE *PCX86DESCGATE;
3079
3080	#endif /* VBOX_FOR_DTRACE_LIB */
3081
3082	/**
3083	* Descriptor table entry.
3084	*/
3085	#pragma pack(1)
3086	typedef union X86DESC
3087	{
3088	#ifndef VBOX_FOR_DTRACE_LIB
3089	/** Generic descriptor view. */
3090	X86DESCGENERIC Gen;
3091	/** Gate descriptor view. */
3092	X86DESCGATE Gate;
3093	#endif
3094
3095	/** 8 bit unsigned integer view. */
3096	uint8_t au8[8];
3097	/** 16 bit unsigned integer view. */
3098	uint16_t au16[4];
3099	/** 32 bit unsigned integer view. */
3100	uint32_t au32[2];
3101	/** 64 bit unsigned integer view. */
3102	uint64_t au64[1];
3103	/** Unsigned integer view. */
3104	uint64_t u;
3105	} X86DESC;
3106	#ifndef VBOX_FOR_DTRACE_LIB
3107	AssertCompileSize(X86DESC, 8);
3108	#endif
3109	#pragma pack()
3110	/** Pointer to descriptor table entry. */
3111	typedef X86DESC *PX86DESC;
3112	/** Pointer to const descriptor table entry. */
3113	typedef const X86DESC *PCX86DESC;
3114
3115	/** @def X86DESC_BASE
3116	* Return the base address of a descriptor.
3117	*/
3118	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
3119	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3120	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3121	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3122
3123	/** @def X86DESC_LIMIT
3124	* Return the limit of a descriptor.
3125	*/
3126	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
3127	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3128	\| ( (a_pDesc)->Gen.u16LimitLow ) )
3129
3130	/** @def X86DESC_LIMIT_G
3131	* Return the limit of a descriptor with the granularity bit taken into account.
3132	* @returns Selector limit (uint32_t).
3133	* @param a_pDesc Pointer to the descriptor.
3134	*/
3135	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
3136	( (a_pDesc)->Gen.u1Granularity \
3137	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
3138	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
3139	)
3140
3141	/** @def X86DESC_GET_HID_ATTR
3142	* Get the descriptor attributes for the hidden register.
3143	*/
3144	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
3145	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3146
3147	#ifndef VBOX_FOR_DTRACE_LIB
3148
3149	/**
3150	* 64 bits generic descriptor table entry
3151	* Note: most of these bits have no meaning in long mode.
3152	*/
3153	#pragma pack(1)
3154	typedef struct X86DESC64GENERIC
3155	{
3156	/** Limit - Low word - IGNORED. */
3157	uint32_t u16LimitLow : 16;
3158	/** Base address - low word. - IGNORED
3159	* Don't try set this to 24 because MSC is doing stupid things then. */
3160	uint32_t u16BaseLow : 16;
3161	/** Base address - first 8 bits of high word. - IGNORED */
3162	uint32_t u8BaseHigh1 : 8;
3163	/** Segment Type. */
3164	uint32_t u4Type : 4;
3165	/** Descriptor Type. System(=0) or code/data selector */
3166	uint32_t u1DescType : 1;
3167	/** Descriptor Privilege level. */
3168	uint32_t u2Dpl : 2;
3169	/** Flags selector present(=1) or not. */
3170	uint32_t u1Present : 1;
3171	/** Segment limit 16-19. - IGNORED */
3172	uint32_t u4LimitHigh : 4;
3173	/** Available for system software. - IGNORED */
3174	uint32_t u1Available : 1;
3175	/** Long mode flag. */
3176	uint32_t u1Long : 1;
3177	/** This flags meaning depends on the segment type. Try make sense out
3178	* of the intel manual yourself. */
3179	uint32_t u1DefBig : 1;
3180	/** Granularity of the limit. If set 4KB granularity is used, if
3181	* clear byte. - IGNORED */
3182	uint32_t u1Granularity : 1;
3183	/** Base address - highest 8 bits. - IGNORED */
3184	uint32_t u8BaseHigh2 : 8;
3185	/** Base address - bits 63-32. */
3186	uint32_t u32BaseHigh3 : 32;
3187	uint32_t u8Reserved : 8;
3188	uint32_t u5Zeros : 5;
3189	uint32_t u19Reserved : 19;
3190	} X86DESC64GENERIC;
3191	#pragma pack()
3192	/** Pointer to a generic descriptor entry. */
3193	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3194	/** Pointer to a const generic descriptor entry. */
3195	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3196
3197	/**
3198	* System descriptor table entry (64 bits)
3199	*
3200	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3201	*/
3202	#pragma pack(1)
3203	typedef struct X86DESC64SYSTEM
3204	{
3205	/** Limit - Low word. */
3206	uint32_t u16LimitLow : 16;
3207	/** Base address - lowe word.
3208	* Don't try set this to 24 because MSC is doing stupid things then. */
3209	uint32_t u16BaseLow : 16;
3210	/** Base address - first 8 bits of high word. */
3211	uint32_t u8BaseHigh1 : 8;
3212	/** Segment Type. */
3213	uint32_t u4Type : 4;
3214	/** Descriptor Type. System(=0) or code/data selector */
3215	uint32_t u1DescType : 1;
3216	/** Descriptor Privilege level. */
3217	uint32_t u2Dpl : 2;
3218	/** Flags selector present(=1) or not. */
3219	uint32_t u1Present : 1;
3220	/** Segment limit 16-19. */
3221	uint32_t u4LimitHigh : 4;
3222	/** Available for system software. */
3223	uint32_t u1Available : 1;
3224	/** Reserved - 0. */
3225	uint32_t u1Reserved : 1;
3226	/** This flags meaning depends on the segment type. Try make sense out
3227	* of the intel manual yourself. */
3228	uint32_t u1DefBig : 1;
3229	/** Granularity of the limit. If set 4KB granularity is used, if
3230	* clear byte. */
3231	uint32_t u1Granularity : 1;
3232	/** Base address - bits 31-24. */
3233	uint32_t u8BaseHigh2 : 8;
3234	/** Base address - bits 63-32. */
3235	uint32_t u32BaseHigh3 : 32;
3236	uint32_t u8Reserved : 8;
3237	uint32_t u5Zeros : 5;
3238	uint32_t u19Reserved : 19;
3239	} X86DESC64SYSTEM;
3240	#pragma pack()
3241	/** Pointer to a system descriptor entry. */
3242	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3243	/** Pointer to a const system descriptor entry. */
3244	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3245
3246	/**
3247	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3248	*/
3249	typedef struct X86DESC64GATE
3250	{
3251	/** Target code segment offset - Low word. */
3252	uint32_t u16OffsetLow : 16;
3253	/** Target code segment selector. */
3254	uint32_t u16Sel : 16;
3255	/** Interrupt stack table for interrupt- and trap-gates.
3256	* Ignored by call-gates. */
3257	uint32_t u3IST : 3;
3258	/** Reserved / ignored. */
3259	uint32_t u5Reserved : 5;
3260	/** Segment Type. */
3261	uint32_t u4Type : 4;
3262	/** Descriptor Type (0 = system). */
3263	uint32_t u1DescType : 1;
3264	/** Descriptor Privilege level. */
3265	uint32_t u2Dpl : 2;
3266	/** Flags selector present(=1) or not. */
3267	uint32_t u1Present : 1;
3268	/** Target code segment offset - High word.
3269	* Ignored if task-gate. */
3270	uint32_t u16OffsetHigh : 16;
3271	/** Target code segment offset - Top dword.
3272	* Ignored if task-gate. */
3273	uint32_t u32OffsetTop : 32;
3274	/** Reserved / ignored / must be zero.
3275	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3276	uint32_t u32Reserved : 32;
3277	} X86DESC64GATE;
3278	AssertCompileSize(X86DESC64GATE, 16);
3279	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3280	typedef X86DESC64GATE *PX86DESC64GATE;
3281	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3282	typedef const X86DESC64GATE *PCX86DESC64GATE;
3283
3284	#endif /* VBOX_FOR_DTRACE_LIB */
3285
3286	/**
3287	* Descriptor table entry.
3288	*/
3289	#pragma pack(1)
3290	typedef union X86DESC64
3291	{
3292	#ifndef VBOX_FOR_DTRACE_LIB
3293	/** Generic descriptor view. */
3294	X86DESC64GENERIC Gen;
3295	/** System descriptor view. */
3296	X86DESC64SYSTEM System;
3297	/** Gate descriptor view. */
3298	X86DESC64GATE Gate;
3299	#endif
3300
3301	/** 8 bit unsigned integer view. */
3302	uint8_t au8[16];
3303	/** 16 bit unsigned integer view. */
3304	uint16_t au16[8];
3305	/** 32 bit unsigned integer view. */
3306	uint32_t au32[4];
3307	/** 64 bit unsigned integer view. */
3308	uint64_t au64[2];
3309	} X86DESC64;
3310	#ifndef VBOX_FOR_DTRACE_LIB
3311	AssertCompileSize(X86DESC64, 16);
3312	#endif
3313	#pragma pack()
3314	/** Pointer to descriptor table entry. */
3315	typedef X86DESC64 *PX86DESC64;
3316	/** Pointer to const descriptor table entry. */
3317	typedef const X86DESC64 *PCX86DESC64;
3318
3319	/** @def X86DESC64_BASE
3320	* Return the base of a 64-bit descriptor.
3321	*/
3322	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
3323	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3324	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3325	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3326	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3327
3328
3329
3330	/** @name Host system descriptor table entry - Use with care!
3331	* @{ */
3332	/** Host system descriptor table entry. */
3333	#if HC_ARCH_BITS == 64
3334	typedef X86DESC64 X86DESCHC;
3335	#else
3336	typedef X86DESC X86DESCHC;
3337	#endif
3338	/** Pointer to a host system descriptor table entry. */
3339	#if HC_ARCH_BITS == 64
3340	typedef PX86DESC64 PX86DESCHC;
3341	#else
3342	typedef PX86DESC PX86DESCHC;
3343	#endif
3344	/** Pointer to a const host system descriptor table entry. */
3345	#if HC_ARCH_BITS == 64
3346	typedef PCX86DESC64 PCX86DESCHC;
3347	#else
3348	typedef PCX86DESC PCX86DESCHC;
3349	#endif
3350	/** @} */
3351
3352
3353	/** @name Selector Descriptor Types.
3354	* @{
3355	*/
3356
3357	/** @name Non-System Selector Types.
3358	* @{ */
3359	/** Code(=set)/Data(=clear) bit. */
3360	#define X86_SEL_TYPE_CODE 8
3361	/** Memory(=set)/System(=clear) bit. */
3362	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
3363	/** Accessed bit. */
3364	#define X86_SEL_TYPE_ACCESSED 1
3365	/** Expand down bit (for data selectors only). */
3366	#define X86_SEL_TYPE_DOWN 4
3367	/** Conforming bit (for code selectors only). */
3368	#define X86_SEL_TYPE_CONF 4
3369	/** Write bit (for data selectors only). */
3370	#define X86_SEL_TYPE_WRITE 2
3371	/** Read bit (for code selectors only). */
3372	#define X86_SEL_TYPE_READ 2
3373	/** The bit number of the code segment read bit (relative to u4Type). */
3374	#define X86_SEL_TYPE_READ_BIT 1
3375
3376	/** Read only selector type. */
3377	#define X86_SEL_TYPE_RO 0
3378	/** Accessed read only selector type. */
3379	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
3380	/** Read write selector type. */
3381	#define X86_SEL_TYPE_RW 2
3382	/** Accessed read write selector type. */
3383	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
3384	/** Expand down read only selector type. */
3385	#define X86_SEL_TYPE_RO_DOWN 4
3386	/** Accessed expand down read only selector type. */
3387	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
3388	/** Expand down read write selector type. */
3389	#define X86_SEL_TYPE_RW_DOWN 6
3390	/** Accessed expand down read write selector type. */
3391	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
3392	/** Execute only selector type. */
3393	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
3394	/** Accessed execute only selector type. */
3395	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3396	/** Execute and read selector type. */
3397	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
3398	/** Accessed execute and read selector type. */
3399	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3400	/** Conforming execute only selector type. */
3401	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
3402	/** Accessed Conforming execute only selector type. */
3403	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3404	/** Conforming execute and write selector type. */
3405	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
3406	/** Accessed Conforming execute and write selector type. */
3407	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3408	/** @} */
3409
3410
3411	/** @name System Selector Types.
3412	* @{ */
3413	/** The TSS busy bit mask. */
3414	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3415
3416	/** Undefined system selector type. */
3417	#define X86_SEL_TYPE_SYS_UNDEFINED 0
3418	/** 286 TSS selector. */
3419	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3420	/** LDT selector. */
3421	#define X86_SEL_TYPE_SYS_LDT 2
3422	/** 286 TSS selector - Busy. */
3423	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3424	/** 286 Callgate selector. */
3425	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3426	/** Taskgate selector. */
3427	#define X86_SEL_TYPE_SYS_TASK_GATE 5
3428	/** 286 Interrupt gate selector. */
3429	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3430	/** 286 Trapgate selector. */
3431	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3432	/** Undefined system selector. */
3433	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3434	/** 386 TSS selector. */
3435	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3436	/** Undefined system selector. */
3437	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3438	/** 386 TSS selector - Busy. */
3439	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3440	/** 386 Callgate selector. */
3441	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3442	/** Undefined system selector. */
3443	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3444	/** 386 Interruptgate selector. */
3445	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3446	/** 386 Trapgate selector. */
3447	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3448	/** @} */
3449
3450	/** @name AMD64 System Selector Types.
3451	* @{ */
3452	/** LDT selector. */
3453	#define AMD64_SEL_TYPE_SYS_LDT 2
3454	/** TSS selector - Busy. */
3455	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3456	/** TSS selector - Busy. */
3457	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3458	/** Callgate selector. */
3459	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3460	/** Interruptgate selector. */
3461	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3462	/** Trapgate selector. */
3463	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3464	/** @} */
3465
3466	/** @} */
3467
3468
3469	/** @name Descriptor Table Entry Flag Masks.
3470	* These are for the 2nd 32-bit word of a descriptor.
3471	* @{ */
3472	/** Bits 8-11 - TYPE - Descriptor type mask. */
3473	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
3474	/** Bit 12 - S - System (=0) or Code/Data (=1). */
3475	#define X86_DESC_S RT_BIT(12)
3476	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3477	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
3478	/** Bit 15 - P - Present. */
3479	#define X86_DESC_P RT_BIT(15)
3480	/** Bit 20 - AVL - Available for system software. */
3481	#define X86_DESC_AVL RT_BIT(20)
3482	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3483	#define X86_DESC_DB RT_BIT(22)
3484	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3485	* used, if clear byte. */
3486	#define X86_DESC_G RT_BIT(23)
3487	/** @} */
3488
3489	/** @} */
3490
3491
3492	/** @name Task Segments.
3493	* @{
3494	*/
3495
3496	/**
3497	* The minimum TSS descriptor limit for 286 tasks.
3498	*/
3499	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3500
3501	/**
3502	* The minimum TSS descriptor segment limit for 386 tasks.
3503	*/
3504	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3505
3506	/**
3507	* 16-bit Task Segment (TSS).
3508	*/
3509	#pragma pack(1)
3510	typedef struct X86TSS16
3511	{
3512	/** Back link to previous task. (static) */
3513	RTSEL selPrev;
3514	/** Ring-0 stack pointer. (static) */
3515	uint16_t sp0;
3516	/** Ring-0 stack segment. (static) */
3517	RTSEL ss0;
3518	/** Ring-1 stack pointer. (static) */
3519	uint16_t sp1;
3520	/** Ring-1 stack segment. (static) */
3521	RTSEL ss1;
3522	/** Ring-2 stack pointer. (static) */
3523	uint16_t sp2;
3524	/** Ring-2 stack segment. (static) */
3525	RTSEL ss2;
3526	/** IP before task switch. */
3527	uint16_t ip;
3528	/** FLAGS before task switch. */
3529	uint16_t flags;
3530	/** AX before task switch. */
3531	uint16_t ax;
3532	/** CX before task switch. */
3533	uint16_t cx;
3534	/** DX before task switch. */
3535	uint16_t dx;
3536	/** BX before task switch. */
3537	uint16_t bx;
3538	/** SP before task switch. */
3539	uint16_t sp;
3540	/** BP before task switch. */
3541	uint16_t bp;
3542	/** SI before task switch. */
3543	uint16_t si;
3544	/** DI before task switch. */
3545	uint16_t di;
3546	/** ES before task switch. */
3547	RTSEL es;
3548	/** CS before task switch. */
3549	RTSEL cs;
3550	/** SS before task switch. */
3551	RTSEL ss;
3552	/** DS before task switch. */
3553	RTSEL ds;
3554	/** LDTR before task switch. */
3555	RTSEL selLdt;
3556	} X86TSS16;
3557	#ifndef VBOX_FOR_DTRACE_LIB
3558	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
3559	#endif
3560	#pragma pack()
3561	/** Pointer to a 16-bit task segment. */
3562	typedef X86TSS16 *PX86TSS16;
3563	/** Pointer to a const 16-bit task segment. */
3564	typedef const X86TSS16 *PCX86TSS16;
3565
3566
3567	/**
3568	* 32-bit Task Segment (TSS).
3569	*/
3570	#pragma pack(1)
3571	typedef struct X86TSS32
3572	{
3573	/** Back link to previous task. (static) */
3574	RTSEL selPrev;
3575	uint16_t padding1;
3576	/** Ring-0 stack pointer. (static) */
3577	uint32_t esp0;
3578	/** Ring-0 stack segment. (static) */
3579	RTSEL ss0;
3580	uint16_t padding_ss0;
3581	/** Ring-1 stack pointer. (static) */
3582	uint32_t esp1;
3583	/** Ring-1 stack segment. (static) */
3584	RTSEL ss1;
3585	uint16_t padding_ss1;
3586	/** Ring-2 stack pointer. (static) */
3587	uint32_t esp2;
3588	/** Ring-2 stack segment. (static) */
3589	RTSEL ss2;
3590	uint16_t padding_ss2;
3591	/** Page directory for the task. (static) */
3592	uint32_t cr3;
3593	/** EIP before task switch. */
3594	uint32_t eip;
3595	/** EFLAGS before task switch. */
3596	uint32_t eflags;
3597	/** EAX before task switch. */
3598	uint32_t eax;
3599	/** ECX before task switch. */
3600	uint32_t ecx;
3601	/** EDX before task switch. */
3602	uint32_t edx;
3603	/** EBX before task switch. */
3604	uint32_t ebx;
3605	/** ESP before task switch. */
3606	uint32_t esp;
3607	/** EBP before task switch. */
3608	uint32_t ebp;
3609	/** ESI before task switch. */
3610	uint32_t esi;
3611	/** EDI before task switch. */
3612	uint32_t edi;
3613	/** ES before task switch. */
3614	RTSEL es;
3615	uint16_t padding_es;
3616	/** CS before task switch. */
3617	RTSEL cs;
3618	uint16_t padding_cs;
3619	/** SS before task switch. */
3620	RTSEL ss;
3621	uint16_t padding_ss;
3622	/** DS before task switch. */
3623	RTSEL ds;
3624	uint16_t padding_ds;
3625	/** FS before task switch. */
3626	RTSEL fs;
3627	uint16_t padding_fs;
3628	/** GS before task switch. */
3629	RTSEL gs;
3630	uint16_t padding_gs;
3631	/** LDTR before task switch. */
3632	RTSEL selLdt;
3633	uint16_t padding_ldt;
3634	/** Debug trap flag */
3635	uint16_t fDebugTrap;
3636	/** Offset relative to the TSS of the start of the I/O Bitmap
3637	* and the end of the interrupt redirection bitmap. */
3638	uint16_t offIoBitmap;
3639	} X86TSS32;
3640	#pragma pack()
3641	/** Pointer to task segment. */
3642	typedef X86TSS32 *PX86TSS32;
3643	/** Pointer to const task segment. */
3644	typedef const X86TSS32 *PCX86TSS32;
3645	#ifndef VBOX_FOR_DTRACE_LIB
3646	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
3647	AssertCompileMemberOffset(X86TSS32, cr3, 28);
3648	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
3649	#endif
3650
3651	/**
3652	* 64-bit Task segment.
3653	*/
3654	#pragma pack(1)
3655	typedef struct X86TSS64
3656	{
3657	/** Reserved. */
3658	uint32_t u32Reserved;
3659	/** Ring-0 stack pointer. (static) */
3660	uint64_t rsp0;
3661	/** Ring-1 stack pointer. (static) */
3662	uint64_t rsp1;
3663	/** Ring-2 stack pointer. (static) */
3664	uint64_t rsp2;
3665	/** Reserved. */
3666	uint32_t u32Reserved2[2];
3667	/* IST */
3668	uint64_t ist1;
3669	uint64_t ist2;
3670	uint64_t ist3;
3671	uint64_t ist4;
3672	uint64_t ist5;
3673	uint64_t ist6;
3674	uint64_t ist7;
3675	/* Reserved. */
3676	uint16_t u16Reserved[5];
3677	/** Offset relative to the TSS of the start of the I/O Bitmap
3678	* and the end of the interrupt redirection bitmap. */
3679	uint16_t offIoBitmap;
3680	} X86TSS64;
3681	#pragma pack()
3682	/** Pointer to a 64-bit task segment. */
3683	typedef X86TSS64 *PX86TSS64;
3684	/** Pointer to a const 64-bit task segment. */
3685	typedef const X86TSS64 *PCX86TSS64;
3686	#ifndef VBOX_FOR_DTRACE_LIB
3687	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
3688	#endif
3689
3690	/** @} */
3691
3692
3693	/** @name Selectors.
3694	* @{
3695	*/
3696
3697	/**
3698	* The shift used to convert a selector from and to index an index (C).
3699	*/
3700	#define X86_SEL_SHIFT 3
3701
3702	/**
3703	* The mask used to mask off the table indicator and RPL of an selector.
3704	*/
3705	#define X86_SEL_MASK 0xfff8U
3706
3707	/**
3708	* The mask used to mask off the RPL of an selector.
3709	* This is suitable for checking for NULL selectors.
3710	*/
3711	#define X86_SEL_MASK_OFF_RPL 0xfffcU
3712
3713	/**
3714	* The bit indicating that a selector is in the LDT and not in the GDT.
3715	*/
3716	#define X86_SEL_LDT 0x0004U
3717
3718	/**
3719	* The bit mask for getting the RPL of a selector.
3720	*/
3721	#define X86_SEL_RPL 0x0003U
3722
3723	/**
3724	* The mask covering both RPL and LDT.
3725	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
3726	* checks.
3727	*/
3728	#define X86_SEL_RPL_LDT 0x0007U
3729
3730	/** @} */
3731
3732
3733	/**
3734	* x86 Exceptions/Faults/Traps.
3735	*/
3736	typedef enum X86XCPT
3737	{
3738	/** \#DE - Divide error. */
3739	X86_XCPT_DE = 0x00,
3740	/** \#DB - Debug event (single step, DRx, ..) */
3741	X86_XCPT_DB = 0x01,
3742	/** NMI - Non-Maskable Interrupt */
3743	X86_XCPT_NMI = 0x02,
3744	/** \#BP - Breakpoint (INT3). */
3745	X86_XCPT_BP = 0x03,
3746	/** \#OF - Overflow (INTO). */
3747	X86_XCPT_OF = 0x04,
3748	/** \#BR - Bound range exceeded (BOUND). */
3749	X86_XCPT_BR = 0x05,
3750	/** \#UD - Undefined opcode. */
3751	X86_XCPT_UD = 0x06,
3752	/** \#NM - Device not available (math coprocessor device). */
3753	X86_XCPT_NM = 0x07,
3754	/** \#DF - Double fault. */
3755	X86_XCPT_DF = 0x08,
3756	/** ??? - Coprocessor segment overrun (obsolete). */
3757	X86_XCPT_CO_SEG_OVERRUN = 0x09,
3758	/** \#TS - Taskswitch (TSS). */
3759	X86_XCPT_TS = 0x0a,
3760	/** \#NP - Segment no present. */
3761	X86_XCPT_NP = 0x0b,
3762	/** \#SS - Stack segment fault. */
3763	X86_XCPT_SS = 0x0c,
3764	/** \#GP - General protection fault. */
3765	X86_XCPT_GP = 0x0d,
3766	/** \#PF - Page fault. */
3767	X86_XCPT_PF = 0x0e,
3768	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
3769	/** \#MF - Math fault (FPU). */
3770	X86_XCPT_MF = 0x10,
3771	/** \#AC - Alignment check. */
3772	X86_XCPT_AC = 0x11,
3773	/** \#MC - Machine check. */
3774	X86_XCPT_MC = 0x12,
3775	/** \#XF - SIMD Floating-Pointer Exception. */
3776	X86_XCPT_XF = 0x13,
3777	/** \#VE - Virtualization Exception. */
3778	X86_XCPT_VE = 0x14,
3779	/** \#SX - Security Exception. */
3780	X86_XCPT_SX = 0x1f
3781	} X86XCPT;
3782	/** Pointer to a x86 exception code. */
3783	typedef X86XCPT *PX86XCPT;
3784	/** Pointer to a const x86 exception code. */
3785	typedef const X86XCPT *PCX86XCPT;
3786	/** The maximum exception value. */
3787	#define X86_XCPT_MAX (X86_XCPT_SX)
3788
3789
3790	/** @name Trap Error Codes
3791	* @{
3792	*/
3793	/** External indicator. */
3794	#define X86_TRAP_ERR_EXTERNAL 1
3795	/** IDT indicator. */
3796	#define X86_TRAP_ERR_IDT 2
3797	/** Descriptor table indicator - If set LDT, if clear GDT. */
3798	#define X86_TRAP_ERR_TI 4
3799	/** Mask for getting the selector. */
3800	#define X86_TRAP_ERR_SEL_MASK 0xfff8
3801	/** Shift for getting the selector table index (C type index). */
3802	#define X86_TRAP_ERR_SEL_SHIFT 3
3803	/** @} */
3804
3805
3806	/** @name \#PF Trap Error Codes
3807	* @{
3808	*/
3809	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3810	#define X86_TRAP_PF_P RT_BIT(0)
3811	/** Bit 1 - R/W - Read (clear) or write (set) access. */
3812	#define X86_TRAP_PF_RW RT_BIT(1)
3813	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3814	#define X86_TRAP_PF_US RT_BIT(2)
3815	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3816	#define X86_TRAP_PF_RSVD RT_BIT(3)
3817	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3818	#define X86_TRAP_PF_ID RT_BIT(4)
3819	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
3820	#define X86_TRAP_PF_PK RT_BIT(5)
3821	/** @} */
3822
3823	#pragma pack(1)
3824	/**
3825	* 16-bit IDTR.
3826	*/
3827	typedef struct X86IDTR16
3828	{
3829	/** Offset. */
3830	uint16_t offSel;
3831	/** Selector. */
3832	uint16_t uSel;
3833	} X86IDTR16, *PX86IDTR16;
3834	#pragma pack()
3835
3836	#pragma pack(1)
3837	/**
3838	* 32-bit IDTR/GDTR.
3839	*/
3840	typedef struct X86XDTR32
3841	{
3842	/** Size of the descriptor table. */
3843	uint16_t cb;
3844	/** Address of the descriptor table. */
3845	#ifndef VBOX_FOR_DTRACE_LIB
3846	uint32_t uAddr;
3847	#else
3848	uint16_t au16Addr[2];
3849	#endif
3850	} X86XDTR32, *PX86XDTR32;
3851	#pragma pack()
3852
3853	#pragma pack(1)
3854	/**
3855	* 64-bit IDTR/GDTR.
3856	*/
3857	typedef struct X86XDTR64
3858	{
3859	/** Size of the descriptor table. */
3860	uint16_t cb;
3861	/** Address of the descriptor table. */
3862	#ifndef VBOX_FOR_DTRACE_LIB
3863	uint64_t uAddr;
3864	#else
3865	uint16_t au16Addr[4];
3866	#endif
3867	} X86XDTR64, *PX86XDTR64;
3868	#pragma pack()
3869
3870
3871	/** @name ModR/M
3872	* @{ */
3873	#define X86_MODRM_RM_MASK UINT8_C(0x07)
3874	#define X86_MODRM_REG_MASK UINT8_C(0x38)
3875	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3876	#define X86_MODRM_REG_SHIFT 3
3877	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3878	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3879	#define X86_MODRM_MOD_SHIFT 6
3880	#ifndef VBOX_FOR_DTRACE_LIB
3881	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
3882	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3883	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3884	#endif
3885	/** @} */
3886
3887	/** @name SIB
3888	* @{ */
3889	#define X86_SIB_BASE_MASK UINT8_C(0x07)
3890	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3891	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3892	#define X86_SIB_INDEX_SHIFT 3
3893	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3894	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3895	#define X86_SIB_SCALE_SHIFT 6
3896	#ifndef VBOX_FOR_DTRACE_LIB
3897	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
3898	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3899	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3900	#endif
3901	/** @} */
3902
3903	/** @name General register indexes
3904	* @{ */
3905	#define X86_GREG_xAX 0
3906	#define X86_GREG_xCX 1
3907	#define X86_GREG_xDX 2
3908	#define X86_GREG_xBX 3
3909	#define X86_GREG_xSP 4
3910	#define X86_GREG_xBP 5
3911	#define X86_GREG_xSI 6
3912	#define X86_GREG_xDI 7
3913	#define X86_GREG_x8 8
3914	#define X86_GREG_x9 9
3915	#define X86_GREG_x10 10
3916	#define X86_GREG_x11 11
3917	#define X86_GREG_x12 12
3918	#define X86_GREG_x13 13
3919	#define X86_GREG_x14 14
3920	#define X86_GREG_x15 15
3921	/** @} */
3922
3923	/** @name X86_SREG_XXX - Segment register indexes.
3924	* @{ */
3925	#define X86_SREG_ES 0
3926	#define X86_SREG_CS 1
3927	#define X86_SREG_SS 2
3928	#define X86_SREG_DS 3
3929	#define X86_SREG_FS 4
3930	#define X86_SREG_GS 5
3931	/** @} */
3932	/** Segment register count. */
3933	#define X86_SREG_COUNT 6
3934
3935
3936	/** @name X86_OP_XXX - Prefixes
3937	* @{ */
3938	#define X86_OP_PRF_CS UINT8_C(0x2e)
3939	#define X86_OP_PRF_SS UINT8_C(0x36)
3940	#define X86_OP_PRF_DS UINT8_C(0x3e)
3941	#define X86_OP_PRF_ES UINT8_C(0x26)
3942	#define X86_OP_PRF_FS UINT8_C(0x64)
3943	#define X86_OP_PRF_GS UINT8_C(0x65)
3944	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
3945	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
3946	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
3947	#define X86_OP_PRF_REPZ UINT8_C(0xf2)
3948	#define X86_OP_PRF_REPNZ UINT8_C(0xf3)
3949	#define X86_OP_REX_B UINT8_C(0x41)
3950	#define X86_OP_REX_X UINT8_C(0x42)
3951	#define X86_OP_REX_R UINT8_C(0x44)
3952	#define X86_OP_REX_W UINT8_C(0x48)
3953	/** @} */
3954
3955
3956	/** @} */
3957
3958	#endif
3959

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source: vbox/trunk/include/iprt/x86.h@ 59868

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