x86.h@ 59285

Last change on this file since 59285 was 59285, checked in by vboxsync, 9 years ago
iprt/x86.h,*: Drop IntRedirBitmap from X86TSS32 and X86TSS64.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 142.1 KB

Line
1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2015 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	#ifndef VBOX_FOR_DTRACE_LIB
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104	#endif /* !VBOX_FOR_DTRACE_LIB */
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	#ifndef VBOX_FOR_DTRACE_LIB
114	/** The bitfield view. */
115	X86EFLAGSBITS Bits;
116	#endif
117	/** The 8-bit view. */
118	uint8_t au8[4];
119	/** The 16-bit view. */
120	uint16_t au16[2];
121	/** The 32-bit view. */
122	uint32_t au32[1];
123	/** The 32-bit view. */
124	uint32_t u32;
125	} X86EFLAGS;
126	/** Pointer to EFLAGS. */
127	typedef X86EFLAGS *PX86EFLAGS;
128	/** Pointer to const EFLAGS. */
129	typedef const X86EFLAGS *PCX86EFLAGS;
130
131	/**
132	* RFLAGS (32 upper bits are reserved).
133	*/
134	typedef union X86RFLAGS
135	{
136	/** The plain unsigned view. */
137	uint64_t u;
138	#ifndef VBOX_FOR_DTRACE_LIB
139	/** The bitfield view. */
140	X86EFLAGSBITS Bits;
141	#endif
142	/** The 8-bit view. */
143	uint8_t au8[8];
144	/** The 16-bit view. */
145	uint16_t au16[4];
146	/** The 32-bit view. */
147	uint32_t au32[2];
148	/** The 64-bit view. */
149	uint64_t au64[1];
150	/** The 64-bit view. */
151	uint64_t u64;
152	} X86RFLAGS;
153	/** Pointer to RFLAGS. */
154	typedef X86RFLAGS *PX86RFLAGS;
155	/** Pointer to const RFLAGS. */
156	typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159	/** @name EFLAGS
160	* @{
161	*/
162	/** Bit 0 - CF - Carry flag - Status flag. */
163	#define X86_EFL_CF RT_BIT(0)
164	#define X86_EFL_CF_BIT 0
165	/** Bit 1 - Reserved, reads as 1. */
166	#define X86_EFL_1 RT_BIT(1)
167	/** Bit 2 - PF - Parity flag - Status flag. */
168	#define X86_EFL_PF RT_BIT(2)
169	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
170	#define X86_EFL_AF RT_BIT(4)
171	#define X86_EFL_AF_BIT 4
172	/** Bit 6 - ZF - Zero flag - Status flag. */
173	#define X86_EFL_ZF RT_BIT(6)
174	#define X86_EFL_ZF_BIT 6
175	/** Bit 7 - SF - Signed flag - Status flag. */
176	#define X86_EFL_SF RT_BIT(7)
177	#define X86_EFL_SF_BIT 7
178	/** Bit 8 - TF - Trap flag - System flag. */
179	#define X86_EFL_TF RT_BIT(8)
180	/** Bit 9 - IF - Interrupt flag - System flag. */
181	#define X86_EFL_IF RT_BIT(9)
182	/** Bit 10 - DF - Direction flag - Control flag. */
183	#define X86_EFL_DF RT_BIT(10)
184	/** Bit 11 - OF - Overflow flag - Status flag. */
185	#define X86_EFL_OF RT_BIT(11)
186	#define X86_EFL_OF_BIT 11
187	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
188	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
189	/** Bit 14 - NT - Nested task flag - System flag. */
190	#define X86_EFL_NT RT_BIT(14)
191	/** Bit 16 - RF - Resume flag - System flag. */
192	#define X86_EFL_RF RT_BIT(16)
193	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
194	#define X86_EFL_VM RT_BIT(17)
195	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
196	#define X86_EFL_AC RT_BIT(18)
197	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
198	#define X86_EFL_VIF RT_BIT(19)
199	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
200	#define X86_EFL_VIP RT_BIT(20)
201	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
202	#define X86_EFL_ID RT_BIT(21)
203	/** All live bits. */
204	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
205	/** Read as 1 bits. */
206	#define X86_EFL_RA1_MASK RT_BIT_32(1)
207	/** IOPL shift. */
208	#define X86_EFL_IOPL_SHIFT 12
209	/** The IOPL level from the flags. */
210	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
211	/** Bits restored by popf */
212	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
213	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
214	/** The status bits commonly updated by arithmetic instructions. */
215	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
216	/** @} */
217
218
219	/** CPUID Feature information - ECX.
220	* CPUID query with EAX=1.
221	*/
222	#ifndef VBOX_FOR_DTRACE_LIB
223	typedef struct X86CPUIDFEATECX
224	{
225	/** Bit 0 - SSE3 - Supports SSE3 or not. */
226	unsigned u1SSE3 : 1;
227	/** Bit 1 - PCLMULQDQ. */
228	unsigned u1PCLMULQDQ : 1;
229	/** Bit 2 - DS Area 64-bit layout. */
230	unsigned u1DTE64 : 1;
231	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
232	unsigned u1Monitor : 1;
233	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
234	unsigned u1CPLDS : 1;
235	/** Bit 5 - VMX - Virtual Machine Technology. */
236	unsigned u1VMX : 1;
237	/** Bit 6 - SMX: Safer Mode Extensions. */
238	unsigned u1SMX : 1;
239	/** Bit 7 - EST - Enh. SpeedStep Tech. */
240	unsigned u1EST : 1;
241	/** Bit 8 - TM2 - Terminal Monitor 2. */
242	unsigned u1TM2 : 1;
243	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
244	unsigned u1SSSE3 : 1;
245	/** Bit 10 - CNTX-ID - L1 Context ID. */
246	unsigned u1CNTXID : 1;
247	/** Bit 11 - Reserved. */
248	unsigned u1Reserved1 : 1;
249	/** Bit 12 - FMA. */
250	unsigned u1FMA : 1;
251	/** Bit 13 - CX16 - CMPXCHG16B. */
252	unsigned u1CX16 : 1;
253	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
254	unsigned u1TPRUpdate : 1;
255	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
256	unsigned u1PDCM : 1;
257	/** Bit 16 - Reserved. */
258	unsigned u1Reserved2 : 1;
259	/** Bit 17 - PCID - Process-context identifiers. */
260	unsigned u1PCID : 1;
261	/** Bit 18 - Direct Cache Access. */
262	unsigned u1DCA : 1;
263	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
264	unsigned u1SSE4_1 : 1;
265	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
266	unsigned u1SSE4_2 : 1;
267	/** Bit 21 - x2APIC. */
268	unsigned u1x2APIC : 1;
269	/** Bit 22 - MOVBE - Supports MOVBE. */
270	unsigned u1MOVBE : 1;
271	/** Bit 23 - POPCNT - Supports POPCNT. */
272	unsigned u1POPCNT : 1;
273	/** Bit 24 - TSC-Deadline. */
274	unsigned u1TSCDEADLINE : 1;
275	/** Bit 25 - AES. */
276	unsigned u1AES : 1;
277	/** Bit 26 - XSAVE - Supports XSAVE. */
278	unsigned u1XSAVE : 1;
279	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
280	unsigned u1OSXSAVE : 1;
281	/** Bit 28 - AVX - Supports AVX instruction extensions. */
282	unsigned u1AVX : 1;
283	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
284	unsigned u1F16C : 1;
285	/** Bit 30 - RDRAND - Supports RDRAND. */
286	unsigned u1RDRAND : 1;
287	/** Bit 31 - Hypervisor present (we're a guest). */
288	unsigned u1HVP : 1;
289	} X86CPUIDFEATECX;
290	#else /* VBOX_FOR_DTRACE_LIB */
291	typedef uint32_t X86CPUIDFEATECX;
292	#endif /* VBOX_FOR_DTRACE_LIB */
293	/** Pointer to CPUID Feature Information - ECX. */
294	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
295	/** Pointer to const CPUID Feature Information - ECX. */
296	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
297
298
299	/** CPUID Feature Information - EDX.
300	* CPUID query with EAX=1.
301	*/
302	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
303	typedef struct X86CPUIDFEATEDX
304	{
305	/** Bit 0 - FPU - x87 FPU on Chip. */
306	unsigned u1FPU : 1;
307	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
308	unsigned u1VME : 1;
309	/** Bit 2 - DE - Debugging extensions. */
310	unsigned u1DE : 1;
311	/** Bit 3 - PSE - Page Size Extension. */
312	unsigned u1PSE : 1;
313	/** Bit 4 - TSC - Time Stamp Counter. */
314	unsigned u1TSC : 1;
315	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
316	unsigned u1MSR : 1;
317	/** Bit 6 - PAE - Physical Address Extension. */
318	unsigned u1PAE : 1;
319	/** Bit 7 - MCE - Machine Check Exception. */
320	unsigned u1MCE : 1;
321	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
322	unsigned u1CX8 : 1;
323	/** Bit 9 - APIC - APIC On-Chip. */
324	unsigned u1APIC : 1;
325	/** Bit 10 - Reserved. */
326	unsigned u1Reserved1 : 1;
327	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
328	unsigned u1SEP : 1;
329	/** Bit 12 - MTRR - Memory Type Range Registers. */
330	unsigned u1MTRR : 1;
331	/** Bit 13 - PGE - PTE Global Bit. */
332	unsigned u1PGE : 1;
333	/** Bit 14 - MCA - Machine Check Architecture. */
334	unsigned u1MCA : 1;
335	/** Bit 15 - CMOV - Conditional Move Instructions. */
336	unsigned u1CMOV : 1;
337	/** Bit 16 - PAT - Page Attribute Table. */
338	unsigned u1PAT : 1;
339	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
340	unsigned u1PSE36 : 1;
341	/** Bit 18 - PSN - Processor Serial Number. */
342	unsigned u1PSN : 1;
343	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
344	unsigned u1CLFSH : 1;
345	/** Bit 20 - Reserved. */
346	unsigned u1Reserved2 : 1;
347	/** Bit 21 - DS - Debug Store. */
348	unsigned u1DS : 1;
349	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
350	unsigned u1ACPI : 1;
351	/** Bit 23 - MMX - Intel MMX 'Technology'. */
352	unsigned u1MMX : 1;
353	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
354	unsigned u1FXSR : 1;
355	/** Bit 25 - SSE - SSE Support. */
356	unsigned u1SSE : 1;
357	/** Bit 26 - SSE2 - SSE2 Support. */
358	unsigned u1SSE2 : 1;
359	/** Bit 27 - SS - Self Snoop. */
360	unsigned u1SS : 1;
361	/** Bit 28 - HTT - Hyper-Threading Technology. */
362	unsigned u1HTT : 1;
363	/** Bit 29 - TM - Thermal Monitor. */
364	unsigned u1TM : 1;
365	/** Bit 30 - Reserved - . */
366	unsigned u1Reserved3 : 1;
367	/** Bit 31 - PBE - Pending Break Enabled. */
368	unsigned u1PBE : 1;
369	} X86CPUIDFEATEDX;
370	#else /* VBOX_FOR_DTRACE_LIB */
371	typedef uint32_t X86CPUIDFEATEDX;
372	#endif /* VBOX_FOR_DTRACE_LIB */
373	/** Pointer to CPUID Feature Information - EDX. */
374	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
375	/** Pointer to const CPUID Feature Information - EDX. */
376	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
377
378	/** @name CPUID Vendor information.
379	* CPUID query with EAX=0.
380	* @{
381	*/
382	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
383	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
384	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
385
386	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
387	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
388	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
389
390	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
391	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
392	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
393	/** @} */
394
395
396	/** @name CPUID Feature information.
397	* CPUID query with EAX=1.
398	* @{
399	*/
400	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
401	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
402	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
403	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
404	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
405	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
406	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
407	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
408	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
409	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
410	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
411	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
412	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
413	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
414	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
415	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
416	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
417	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
418	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
419	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
420	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
421	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
422	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
423	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
424	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT(11)
425	/** ECX Bit 12 - FMA. */
426	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
427	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
428	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
429	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
430	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
431	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
432	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
433	/** ECX Bit 17 - PCID - Process-context identifiers. */
434	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
435	/** ECX Bit 18 - DCA - Direct Cache Access. */
436	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
437	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
438	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
439	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
440	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
441	/** ECX Bit 21 - x2APIC support. */
442	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
443	/** ECX Bit 22 - MOVBE instruction. */
444	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
445	/** ECX Bit 23 - POPCNT instruction. */
446	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
447	/** ECX Bir 24 - TSC-Deadline. */
448	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
449	/** ECX Bit 25 - AES instructions. */
450	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
451	/** ECX Bit 26 - XSAVE instruction. */
452	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
453	/** ECX Bit 27 - OSXSAVE instruction. */
454	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
455	/** ECX Bit 28 - AVX. */
456	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
457	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
458	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT(29)
459	/** ECX Bit 30 - RDRAND instruction. */
460	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT(30)
461	/** ECX Bit 31 - Hypervisor Present (software only). */
462	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
463
464
465	/** Bit 0 - FPU - x87 FPU on Chip. */
466	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
467	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
468	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
469	/** Bit 2 - DE - Debugging extensions. */
470	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
471	/** Bit 3 - PSE - Page Size Extension. */
472	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
473	/** Bit 4 - TSC - Time Stamp Counter. */
474	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
475	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
476	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
477	/** Bit 6 - PAE - Physical Address Extension. */
478	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
479	/** Bit 7 - MCE - Machine Check Exception. */
480	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
481	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
482	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
483	/** Bit 9 - APIC - APIC On-Chip. */
484	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
485	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
486	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
487	/** Bit 12 - MTRR - Memory Type Range Registers. */
488	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
489	/** Bit 13 - PGE - PTE Global Bit. */
490	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
491	/** Bit 14 - MCA - Machine Check Architecture. */
492	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
493	/** Bit 15 - CMOV - Conditional Move Instructions. */
494	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
495	/** Bit 16 - PAT - Page Attribute Table. */
496	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
497	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
498	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
499	/** Bit 18 - PSN - Processor Serial Number. */
500	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
501	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
502	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
503	/** Bit 21 - DS - Debug Store. */
504	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
505	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
506	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
507	/** Bit 23 - MMX - Intel MMX Technology. */
508	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
509	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
510	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
511	/** Bit 25 - SSE - SSE Support. */
512	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
513	/** Bit 26 - SSE2 - SSE2 Support. */
514	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
515	/** Bit 27 - SS - Self Snoop. */
516	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
517	/** Bit 28 - HTT - Hyper-Threading Technology. */
518	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
519	/** Bit 29 - TM - Therm. Monitor. */
520	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
521	/** Bit 31 - PBE - Pending Break Enabled. */
522	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
523	/** @} */
524
525	/** @name CPUID mwait/monitor information.
526	* CPUID query with EAX=5.
527	* @{
528	*/
529	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
530	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
531	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
532	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
533	/** @} */
534
535
536	/** @name CPUID Structured Extended Feature information.
537	* CPUID query with EAX=7.
538	* @{
539	*/
540	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
541	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT(0)
542	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
543	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
544	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
545	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
546	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
547	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
548	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
549	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT(5)
550	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
551	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
552	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
553	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
554	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
555	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
556	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
557	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT(10)
558	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
559	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
560	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
561	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
562	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
563	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT(13)
564	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
565	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
566	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
567	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
568	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
569	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
570	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
571	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT(18)
572	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
573	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
574	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
575	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
576	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
577	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT(23)
578	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
579	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
580	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
581	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
582	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
583	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
584	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
585	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
586	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
587	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
588
589	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
590	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT(0)
591	/** @} */
592
593
594	/** @name CPUID Extended Feature information.
595	* CPUID query with EAX=0x80000001.
596	* @{
597	*/
598	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
599	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
600
601	/** EDX Bit 11 - SYSCALL/SYSRET. */
602	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
603	/** EDX Bit 20 - No-Execute/Execute-Disable. */
604	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
605	/** EDX Bit 26 - 1 GB large page. */
606	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
607	/** EDX Bit 27 - RDTSCP. */
608	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
609	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
610	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
611	/** @}*/
612
613	/** @name CPUID AMD Feature information.
614	* CPUID query with EAX=0x80000001.
615	* @{
616	*/
617	/** Bit 0 - FPU - x87 FPU on Chip. */
618	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
619	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
620	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
621	/** Bit 2 - DE - Debugging extensions. */
622	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
623	/** Bit 3 - PSE - Page Size Extension. */
624	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
625	/** Bit 4 - TSC - Time Stamp Counter. */
626	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
627	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
628	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
629	/** Bit 6 - PAE - Physical Address Extension. */
630	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
631	/** Bit 7 - MCE - Machine Check Exception. */
632	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
633	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
634	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
635	/** Bit 9 - APIC - APIC On-Chip. */
636	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
637	/** Bit 12 - MTRR - Memory Type Range Registers. */
638	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
639	/** Bit 13 - PGE - PTE Global Bit. */
640	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
641	/** Bit 14 - MCA - Machine Check Architecture. */
642	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
643	/** Bit 15 - CMOV - Conditional Move Instructions. */
644	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
645	/** Bit 16 - PAT - Page Attribute Table. */
646	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
647	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
648	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
649	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
650	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
651	/** Bit 23 - MMX - Intel MMX Technology. */
652	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
653	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
654	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
655	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
656	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
657	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
658	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
659	/** Bit 31 - 3DNOW - AMD 3DNow. */
660	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
661
662	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
663	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
664	/** Bit 2 - SVM - AMD VM extensions. */
665	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
666	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
667	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
668	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
669	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
670	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
671	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
672	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
673	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
674	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
675	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
676	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
677	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
678	/** Bit 9 - OSVW - AMD OS visible workaround. */
679	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
680	/** Bit 10 - IBS - Instruct based sampling. */
681	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
682	/** Bit 11 - XOP - Extended operation support (see APM6). */
683	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT(11)
684	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
685	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
686	/** Bit 13 - WDT - AMD Watchdog timer support. */
687	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
688	/** Bit 15 - LWP - Lightweight profiling support. */
689	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT(15)
690	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
691	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT(16)
692	/** Bit 19 - NodeId - Indicates support for
693	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
694	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT(19)
695	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
696	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT(21)
697	/** Bit 22 - TopologyExtensions - . */
698	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT(22)
699	/** @} */
700
701
702	/** @name CPUID AMD Feature information.
703	* CPUID query with EAX=0x80000007.
704	* @{
705	*/
706	/** Bit 0 - TS - Temperature Sensor. */
707	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
708	/** Bit 1 - FID - Frequency ID Control. */
709	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
710	/** Bit 2 - VID - Voltage ID Control. */
711	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
712	/** Bit 3 - TTP - THERMTRIP. */
713	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
714	/** Bit 4 - TM - Hardware Thermal Control. */
715	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
716	/** Bit 5 - STC - Software Thermal Control. */
717	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
718	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
719	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
720	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
721	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
722	/** Bit 8 - TSCINVAR - TSC Invariant. */
723	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
724	/** Bit 9 - CPB - TSC Invariant. */
725	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
726	/** Bit 10 - EffFreqRO - MPERF/APERF. */
727	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
728	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
729	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
730	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
731	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
732	/** @} */
733
734
735	/** @name CR0
736	* @{ */
737	/** Bit 0 - PE - Protection Enabled */
738	#define X86_CR0_PE RT_BIT(0)
739	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
740	/** Bit 1 - MP - Monitor Coprocessor */
741	#define X86_CR0_MP RT_BIT(1)
742	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
743	/** Bit 2 - EM - Emulation. */
744	#define X86_CR0_EM RT_BIT(2)
745	#define X86_CR0_EMULATE_FPU RT_BIT(2)
746	/** Bit 3 - TS - Task Switch. */
747	#define X86_CR0_TS RT_BIT(3)
748	#define X86_CR0_TASK_SWITCH RT_BIT(3)
749	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
750	#define X86_CR0_ET RT_BIT(4)
751	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
752	/** Bit 5 - NE - Numeric error. */
753	#define X86_CR0_NE RT_BIT(5)
754	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
755	/** Bit 16 - WP - Write Protect. */
756	#define X86_CR0_WP RT_BIT(16)
757	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
758	/** Bit 18 - AM - Alignment Mask. */
759	#define X86_CR0_AM RT_BIT(18)
760	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
761	/** Bit 29 - NW - Not Write-though. */
762	#define X86_CR0_NW RT_BIT(29)
763	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
764	/** Bit 30 - WP - Cache Disable. */
765	#define X86_CR0_CD RT_BIT(30)
766	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
767	/** Bit 31 - PG - Paging. */
768	#define X86_CR0_PG RT_BIT(31)
769	#define X86_CR0_PAGING RT_BIT(31)
770	/** @} */
771
772
773	/** @name CR3
774	* @{ */
775	/** Bit 3 - PWT - Page-level Writes Transparent. */
776	#define X86_CR3_PWT RT_BIT(3)
777	/** Bit 4 - PCD - Page-level Cache Disable. */
778	#define X86_CR3_PCD RT_BIT(4)
779	/** Bits 12-31 - - Page directory page number. */
780	#define X86_CR3_PAGE_MASK (0xfffff000)
781	/** Bits 5-31 - - PAE Page directory page number. */
782	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
783	/** Bits 12-51 - - AMD64 Page directory page number. */
784	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
785	/** @} */
786
787
788	/** @name CR4
789	* @{ */
790	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
791	#define X86_CR4_VME RT_BIT(0)
792	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
793	#define X86_CR4_PVI RT_BIT(1)
794	/** Bit 2 - TSD - Time Stamp Disable. */
795	#define X86_CR4_TSD RT_BIT(2)
796	/** Bit 3 - DE - Debugging Extensions. */
797	#define X86_CR4_DE RT_BIT(3)
798	/** Bit 4 - PSE - Page Size Extension. */
799	#define X86_CR4_PSE RT_BIT(4)
800	/** Bit 5 - PAE - Physical Address Extension. */
801	#define X86_CR4_PAE RT_BIT(5)
802	/** Bit 6 - MCE - Machine-Check Enable. */
803	#define X86_CR4_MCE RT_BIT(6)
804	/** Bit 7 - PGE - Page Global Enable. */
805	#define X86_CR4_PGE RT_BIT(7)
806	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
807	#define X86_CR4_PCE RT_BIT(8)
808	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
809	#define X86_CR4_OSFXSR RT_BIT(9)
810	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
811	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
812	/** Bit 13 - VMXE - VMX mode is enabled. */
813	#define X86_CR4_VMXE RT_BIT(13)
814	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
815	#define X86_CR4_SMXE RT_BIT(14)
816	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
817	#define X86_CR4_PCIDE RT_BIT(17)
818	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
819	* extended states. */
820	#define X86_CR4_OSXSAVE RT_BIT(18)
821	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
822	#define X86_CR4_SMEP RT_BIT(20)
823	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
824	#define X86_CR4_SMAP RT_BIT(21)
825	/** Bit 22 - PKE - Protection Key Enable. */
826	#define X86_CR4_PKE RT_BIT(22)
827	/** @} */
828
829
830	/** @name DR6
831	* @{ */
832	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
833	#define X86_DR6_B0 RT_BIT(0)
834	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
835	#define X86_DR6_B1 RT_BIT(1)
836	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
837	#define X86_DR6_B2 RT_BIT(2)
838	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
839	#define X86_DR6_B3 RT_BIT(3)
840	/** Mask of all the Bx bits. */
841	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
842	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
843	#define X86_DR6_BD RT_BIT(13)
844	/** Bit 14 - BS - Single step */
845	#define X86_DR6_BS RT_BIT(14)
846	/** Bit 15 - BT - Task switch. (TSS T bit.) */
847	#define X86_DR6_BT RT_BIT(15)
848	/** Value of DR6 after powerup/reset. */
849	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
850	/** Bits which must be 1s in DR6. */
851	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
852	/** Bits which must be 0s in DR6. */
853	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
854	/** Bits which must be 0s on writes to DR6. */
855	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
856	/** @} */
857
858	/** Get the DR6.Bx bit for a the given breakpoint. */
859	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
860
861
862	/** @name DR7
863	* @{ */
864	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
865	#define X86_DR7_L0 RT_BIT(0)
866	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
867	#define X86_DR7_G0 RT_BIT(1)
868	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
869	#define X86_DR7_L1 RT_BIT(2)
870	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
871	#define X86_DR7_G1 RT_BIT(3)
872	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
873	#define X86_DR7_L2 RT_BIT(4)
874	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
875	#define X86_DR7_G2 RT_BIT(5)
876	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
877	#define X86_DR7_L3 RT_BIT(6)
878	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
879	#define X86_DR7_G3 RT_BIT(7)
880	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
881	#define X86_DR7_LE RT_BIT(8)
882	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
883	#define X86_DR7_GE RT_BIT(9)
884
885	/** L0, L1, L2, and L3. */
886	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
887	/** L0, L1, L2, and L3. */
888	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
889
890	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
891	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
892	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
893	* instruction is executed.
894	* @see http://www.rcollins.org/secrets/DR7.html */
895	#define X86_DR7_ICE_IR RT_BIT(12)
896	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
897	* any DR register is accessed. */
898	#define X86_DR7_GD RT_BIT(13)
899	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
900	* Pentium. */
901	#define X86_DR7_ICE_TR1 RT_BIT(14)
902	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
903	#define X86_DR7_ICE_TR2 RT_BIT(15)
904	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
905	#define X86_DR7_RW0_MASK (3 << 16)
906	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
907	#define X86_DR7_LEN0_MASK (3 << 18)
908	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
909	#define X86_DR7_RW1_MASK (3 << 20)
910	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
911	#define X86_DR7_LEN1_MASK (3 << 22)
912	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
913	#define X86_DR7_RW2_MASK (3 << 24)
914	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
915	#define X86_DR7_LEN2_MASK (3 << 26)
916	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
917	#define X86_DR7_RW3_MASK (3 << 28)
918	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
919	#define X86_DR7_LEN3_MASK (3 << 30)
920
921	/** Bits which reads as 1s. */
922	#define X86_DR7_RA1_MASK (RT_BIT(10))
923	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
924	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
925	/** Bits which must be 0s when writing to DR7. */
926	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
927
928	/** Calcs the L bit of Nth breakpoint.
929	* @param iBp The breakpoint number [0..3].
930	*/
931	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
932
933	/** Calcs the G bit of Nth breakpoint.
934	* @param iBp The breakpoint number [0..3].
935	*/
936	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
937
938	/** Calcs the L and G bits of Nth breakpoint.
939	* @param iBp The breakpoint number [0..3].
940	*/
941	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
942
943	/** @name Read/Write values.
944	* @{ */
945	/** Break on instruction fetch only. */
946	#define X86_DR7_RW_EO 0U
947	/** Break on write only. */
948	#define X86_DR7_RW_WO 1U
949	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
950	#define X86_DR7_RW_IO 2U
951	/** Break on read or write (but not instruction fetches). */
952	#define X86_DR7_RW_RW 3U
953	/** @} */
954
955	/** Shifts a X86_DR7_RW_* value to its right place.
956	* @param iBp The breakpoint number [0..3].
957	* @param fRw One of the X86_DR7_RW_* value.
958	*/
959	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
960
961	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
962	* one of the X86_DR7_RW_XXX constants).
963	*
964	* @returns X86_DR7_RW_XXX
965	* @param uDR7 DR7 value
966	* @param iBp The breakpoint number [0..3].
967	*/
968	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
969
970	/** R/W0, R/W1, R/W2, and R/W3. */
971	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
972
973	#ifndef VBOX_FOR_DTRACE_LIB
974	/** Checks if there are any I/O breakpoint types configured in the RW
975	* registers. Does NOT check if these are enabled, sorry. */
976	# define X86_DR7_ANY_RW_IO(uDR7) \
977	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
978	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
979	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
980	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
981	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
982	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
983	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
984	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
985	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
986	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
987	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
988	#endif /* !VBOX_FOR_DTRACE_LIB */
989
990	/** @name Length values.
991	* @{ */
992	#define X86_DR7_LEN_BYTE 0U
993	#define X86_DR7_LEN_WORD 1U
994	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
995	#define X86_DR7_LEN_DWORD 3U
996	/** @} */
997
998	/** Shifts a X86_DR7_LEN_* value to its right place.
999	* @param iBp The breakpoint number [0..3].
1000	* @param cb One of the X86_DR7_LEN_* values.
1001	*/
1002	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1003
1004	/** Fetch the breakpoint length bits from the DR7 value.
1005	* @param uDR7 DR7 value
1006	* @param iBp The breakpoint number [0..3].
1007	*/
1008	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1009
1010	/** Mask used to check if any breakpoints are enabled. */
1011	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1012
1013	/** LEN0, LEN1, LEN2, and LEN3. */
1014	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1015	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1016	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1017
1018	/** Value of DR7 after powerup/reset. */
1019	#define X86_DR7_INIT_VAL 0x400
1020	/** @} */
1021
1022
1023	/** @name Machine Specific Registers
1024	* @{
1025	*/
1026	/** Machine check address register (P5). */
1027	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1028	/** Machine check type register (P5). */
1029	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1030	/** Time Stamp Counter. */
1031	#define MSR_IA32_TSC 0x10
1032	#define MSR_IA32_CESR UINT32_C(0x00000011)
1033	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1034	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1035
1036	#define MSR_IA32_PLATFORM_ID 0x17
1037
1038	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1039	# define MSR_IA32_APICBASE 0x1b
1040	/** Local APIC enabled. */
1041	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1042	/** X2APIC enabled (requires the EN bit to be set). */
1043	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1044	/** The processor is the boot strap processor (BSP). */
1045	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1046	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1047	* width. */
1048	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1049	#endif
1050
1051	/** Undocumented intel MSR for reporting thread and core counts.
1052	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1053	* first 16 bits is the thread count. The next 16 bits the core count, except
1054	* on Westmere where it seems it's only the next 4 bits for some reason. */
1055	#define MSR_CORE_THREAD_COUNT 0x35
1056
1057	/** CPU Feature control. */
1058	#define MSR_IA32_FEATURE_CONTROL 0x3A
1059	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
1060	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT(1)
1061	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
1062
1063	/** Per-processor TSC adjust MSR. */
1064	#define MSR_IA32_TSC_ADJUST 0x3B
1065
1066	/** BIOS update trigger (microcode update). */
1067	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1068
1069	/** BIOS update signature (microcode). */
1070	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1071
1072	/** SMM monitor control. */
1073	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1074
1075	/** General performance counter no. 0. */
1076	#define MSR_IA32_PMC0 0xC1
1077	/** General performance counter no. 1. */
1078	#define MSR_IA32_PMC1 0xC2
1079	/** General performance counter no. 2. */
1080	#define MSR_IA32_PMC2 0xC3
1081	/** General performance counter no. 3. */
1082	#define MSR_IA32_PMC3 0xC4
1083
1084	/** Nehalem power control. */
1085	#define MSR_IA32_PLATFORM_INFO 0xCE
1086
1087	/** Get FSB clock status (Intel-specific). */
1088	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1089
1090	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1091	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1092
1093	/** C0 Maximum Frequency Clock Count */
1094	#define MSR_IA32_MPERF 0xE7
1095	/** C0 Actual Frequency Clock Count */
1096	#define MSR_IA32_APERF 0xE8
1097
1098	/** MTRR Capabilities. */
1099	#define MSR_IA32_MTRR_CAP 0xFE
1100
1101	/** Cache control/info. */
1102	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1103
1104	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1105	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1106	* R0 SS == CS + 8
1107	* R3 CS == CS + 16
1108	* R3 SS == CS + 24
1109	*/
1110	#define MSR_IA32_SYSENTER_CS 0x174
1111	/** SYSENTER_ESP - the R0 ESP. */
1112	#define MSR_IA32_SYSENTER_ESP 0x175
1113	/** SYSENTER_EIP - the R0 EIP. */
1114	#define MSR_IA32_SYSENTER_EIP 0x176
1115	#endif
1116
1117	/** Machine Check Global Capabilities Register. */
1118	#define MSR_IA32_MCG_CAP 0x179
1119	/** Machine Check Global Status Register. */
1120	#define MSR_IA32_MCG_STATUS 0x17A
1121	/** Machine Check Global Control Register. */
1122	#define MSR_IA32_MCG_CTRL 0x17B
1123
1124	/** Page Attribute Table. */
1125	#define MSR_IA32_CR_PAT 0x277
1126
1127	/** Performance counter MSRs. (Intel only) */
1128	#define MSR_IA32_PERFEVTSEL0 0x186
1129	#define MSR_IA32_PERFEVTSEL1 0x187
1130	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1131	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1132	* holds a ratio that Apple takes for TSC granularity.
1133	*
1134	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1135	#define MSR_FLEX_RATIO 0x194
1136	/** Performance state value and starting with Intel core more.
1137	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1138	#define MSR_IA32_PERF_STATUS 0x198
1139	#define MSR_IA32_PERF_CTL 0x199
1140	#define MSR_IA32_THERM_STATUS 0x19c
1141
1142	/** Enable misc. processor features (R/W). */
1143	#define MSR_IA32_MISC_ENABLE 0x1A0
1144	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1145	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1146	/** Automatic Thermal Control Circuit Enable (R/W). */
1147	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1148	/** Performance Monitoring Available (R). */
1149	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1150	/** Branch Trace Storage Unavailable (R/O). */
1151	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1152	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1153	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1154	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1155	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1156	/** If MONITOR/MWAIT is supported (R/W). */
1157	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1158	/** Limit CPUID Maxval to 3 leafs (R/W). */
1159	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1160	/** When set to 1, xTPR messages are disabled (R/W). */
1161	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1162	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1163	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1164
1165	/** Trace/Profile Resource Control (R/W) */
1166	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1167	/** The number (0..3 or 0..15) of the last branch record register on P4 and
1168	* related Xeons. */
1169	#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1170	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1171	* @{ */
1172	#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1173	#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1174	#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1175	#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1176	/** @} */
1177
1178
1179	#define IA32_MTRR_PHYSBASE0 0x200
1180	#define IA32_MTRR_PHYSMASK0 0x201
1181	#define IA32_MTRR_PHYSBASE1 0x202
1182	#define IA32_MTRR_PHYSMASK1 0x203
1183	#define IA32_MTRR_PHYSBASE2 0x204
1184	#define IA32_MTRR_PHYSMASK2 0x205
1185	#define IA32_MTRR_PHYSBASE3 0x206
1186	#define IA32_MTRR_PHYSMASK3 0x207
1187	#define IA32_MTRR_PHYSBASE4 0x208
1188	#define IA32_MTRR_PHYSMASK4 0x209
1189	#define IA32_MTRR_PHYSBASE5 0x20a
1190	#define IA32_MTRR_PHYSMASK5 0x20b
1191	#define IA32_MTRR_PHYSBASE6 0x20c
1192	#define IA32_MTRR_PHYSMASK6 0x20d
1193	#define IA32_MTRR_PHYSBASE7 0x20e
1194	#define IA32_MTRR_PHYSMASK7 0x20f
1195	#define IA32_MTRR_PHYSBASE8 0x210
1196	#define IA32_MTRR_PHYSMASK8 0x211
1197	#define IA32_MTRR_PHYSBASE9 0x212
1198	#define IA32_MTRR_PHYSMASK9 0x213
1199
1200	/** Fixed range MTRRs.
1201	* @{ */
1202	#define IA32_MTRR_FIX64K_00000 0x250
1203	#define IA32_MTRR_FIX16K_80000 0x258
1204	#define IA32_MTRR_FIX16K_A0000 0x259
1205	#define IA32_MTRR_FIX4K_C0000 0x268
1206	#define IA32_MTRR_FIX4K_C8000 0x269
1207	#define IA32_MTRR_FIX4K_D0000 0x26a
1208	#define IA32_MTRR_FIX4K_D8000 0x26b
1209	#define IA32_MTRR_FIX4K_E0000 0x26c
1210	#define IA32_MTRR_FIX4K_E8000 0x26d
1211	#define IA32_MTRR_FIX4K_F0000 0x26e
1212	#define IA32_MTRR_FIX4K_F8000 0x26f
1213	/** @} */
1214
1215	/** MTRR Default Range. */
1216	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1217
1218	#define MSR_IA32_MC0_CTL 0x400
1219	#define MSR_IA32_MC0_STATUS 0x401
1220
1221	/** Basic VMX information. */
1222	#define MSR_IA32_VMX_BASIC_INFO 0x480
1223	/** Allowed settings for pin-based VM execution controls */
1224	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1225	/** Allowed settings for proc-based VM execution controls */
1226	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1227	/** Allowed settings for the VMX exit controls. */
1228	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1229	/** Allowed settings for the VMX entry controls. */
1230	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1231	/** Misc VMX info. */
1232	#define MSR_IA32_VMX_MISC 0x485
1233	/** Fixed cleared bits in CR0. */
1234	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1235	/** Fixed set bits in CR0. */
1236	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1237	/** Fixed cleared bits in CR4. */
1238	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1239	/** Fixed set bits in CR4. */
1240	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1241	/** Information for enumerating fields in the VMCS. */
1242	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1243	/** Allowed settings for the VM-functions controls. */
1244	#define MSR_IA32_VMX_VMFUNC 0x491
1245	/** Allowed settings for secondary proc-based VM execution controls */
1246	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1247	/** EPT capabilities. */
1248	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1249	/** DS Save Area (R/W). */
1250	#define MSR_IA32_DS_AREA 0x600
1251	/** Running Average Power Limit (RAPL) power units. */
1252	#define MSR_RAPL_POWER_UNIT 0x606
1253	/** X2APIC MSR ranges. */
1254	#define MSR_IA32_X2APIC_START 0x800
1255	#define MSR_IA32_X2APIC_TPR 0x808
1256	#define MSR_IA32_X2APIC_END 0xBFF
1257
1258	/** K6 EFER - Extended Feature Enable Register. */
1259	#define MSR_K6_EFER UINT32_C(0xc0000080)
1260	/** @todo document EFER */
1261	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1262	#define MSR_K6_EFER_SCE RT_BIT(0)
1263	/** Bit 8 - LME - Long mode enabled. (R/W) */
1264	#define MSR_K6_EFER_LME RT_BIT(8)
1265	/** Bit 10 - LMA - Long mode active. (R) */
1266	#define MSR_K6_EFER_LMA RT_BIT(10)
1267	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1268	#define MSR_K6_EFER_NXE RT_BIT(11)
1269	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1270	#define MSR_K6_EFER_SVME RT_BIT(12)
1271	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1272	#define MSR_K6_EFER_LMSLE RT_BIT(13)
1273	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1274	#define MSR_K6_EFER_FFXSR RT_BIT(14)
1275	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1276	#define MSR_K6_EFER_TCE RT_BIT(15)
1277	/** K6 STAR - SYSCALL/RET targets. */
1278	#define MSR_K6_STAR UINT32_C(0xc0000081)
1279	/** Shift value for getting the SYSRET CS and SS value. */
1280	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1281	/** Shift value for getting the SYSCALL CS and SS value. */
1282	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1283	/** Selector mask for use after shifting. */
1284	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1285	/** The mask which give the SYSCALL EIP. */
1286	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1287	/** K6 WHCR - Write Handling Control Register. */
1288	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1289	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1290	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1291	/** K6 PSOR - Processor State Observability Register. */
1292	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1293	/** K6 PFIR - Page Flush/Invalidate Register. */
1294	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1295
1296	/** Performance counter MSRs. (AMD only) */
1297	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1298	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1299	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1300	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1301	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1302	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1303	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1304	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1305
1306	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1307	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1308	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1309	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1310	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1311	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1312	/** K8 FS.base - The 64-bit base FS register. */
1313	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1314	/** K8 GS.base - The 64-bit base GS register. */
1315	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1316	/** K8 KernelGSbase - Used with SWAPGS. */
1317	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1318	/** K8 TSC_AUX - Used with RDTSCP. */
1319	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1320	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1321	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1322	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1323	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1324	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1325	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1326	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1327	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1328	/** North bridge config? See BIOS & Kernel dev guides for
1329	* details. */
1330	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1331
1332	/** Hypertransport interrupt pending register.
1333	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1334	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1335	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1336	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1337
1338	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1339	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1340	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1341	* host state during world switch. */
1342	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1343
1344	/** @} */
1345
1346
1347	/** @name Page Table / Directory / Directory Pointers / L4.
1348	* @{
1349	*/
1350
1351	/** Page table/directory entry as an unsigned integer. */
1352	typedef uint32_t X86PGUINT;
1353	/** Pointer to a page table/directory table entry as an unsigned integer. */
1354	typedef X86PGUINT *PX86PGUINT;
1355	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1356	typedef X86PGUINT const *PCX86PGUINT;
1357
1358	/** Number of entries in a 32-bit PT/PD. */
1359	#define X86_PG_ENTRIES 1024
1360
1361
1362	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1363	typedef uint64_t X86PGPAEUINT;
1364	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1365	typedef X86PGPAEUINT *PX86PGPAEUINT;
1366	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1367	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1368
1369	/** Number of entries in a PAE PT/PD. */
1370	#define X86_PG_PAE_ENTRIES 512
1371	/** Number of entries in a PAE PDPT. */
1372	#define X86_PG_PAE_PDPE_ENTRIES 4
1373
1374	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1375	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1376	/** Number of entries in an AMD64 PDPT.
1377	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1378	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1379
1380	/** The size of a 4KB page. */
1381	#define X86_PAGE_4K_SIZE _4K
1382	/** The page shift of a 4KB page. */
1383	#define X86_PAGE_4K_SHIFT 12
1384	/** The 4KB page offset mask. */
1385	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1386	/** The 4KB page base mask for virtual addresses. */
1387	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1388	/** The 4KB page base mask for virtual addresses - 32bit version. */
1389	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1390
1391	/** The size of a 2MB page. */
1392	#define X86_PAGE_2M_SIZE _2M
1393	/** The page shift of a 2MB page. */
1394	#define X86_PAGE_2M_SHIFT 21
1395	/** The 2MB page offset mask. */
1396	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1397	/** The 2MB page base mask for virtual addresses. */
1398	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1399	/** The 2MB page base mask for virtual addresses - 32bit version. */
1400	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1401
1402	/** The size of a 4MB page. */
1403	#define X86_PAGE_4M_SIZE _4M
1404	/** The page shift of a 4MB page. */
1405	#define X86_PAGE_4M_SHIFT 22
1406	/** The 4MB page offset mask. */
1407	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1408	/** The 4MB page base mask for virtual addresses. */
1409	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1410	/** The 4MB page base mask for virtual addresses - 32bit version. */
1411	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1412
1413	/**
1414	* Check if the given address is canonical.
1415	*/
1416	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1417
1418
1419	/** @name Page Table Entry
1420	* @{
1421	*/
1422	/** Bit 0 - P - Present bit. */
1423	#define X86_PTE_BIT_P 0
1424	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1425	#define X86_PTE_BIT_RW 1
1426	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1427	#define X86_PTE_BIT_US 2
1428	/** Bit 3 - PWT - Page level write thru bit. */
1429	#define X86_PTE_BIT_PWT 3
1430	/** Bit 4 - PCD - Page level cache disable bit. */
1431	#define X86_PTE_BIT_PCD 4
1432	/** Bit 5 - A - Access bit. */
1433	#define X86_PTE_BIT_A 5
1434	/** Bit 6 - D - Dirty bit. */
1435	#define X86_PTE_BIT_D 6
1436	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1437	#define X86_PTE_BIT_PAT 7
1438	/** Bit 8 - G - Global flag. */
1439	#define X86_PTE_BIT_G 8
1440
1441	/** Bit 0 - P - Present bit mask. */
1442	#define X86_PTE_P RT_BIT(0)
1443	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1444	#define X86_PTE_RW RT_BIT(1)
1445	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1446	#define X86_PTE_US RT_BIT(2)
1447	/** Bit 3 - PWT - Page level write thru bit mask. */
1448	#define X86_PTE_PWT RT_BIT(3)
1449	/** Bit 4 - PCD - Page level cache disable bit mask. */
1450	#define X86_PTE_PCD RT_BIT(4)
1451	/** Bit 5 - A - Access bit mask. */
1452	#define X86_PTE_A RT_BIT(5)
1453	/** Bit 6 - D - Dirty bit mask. */
1454	#define X86_PTE_D RT_BIT(6)
1455	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1456	#define X86_PTE_PAT RT_BIT(7)
1457	/** Bit 8 - G - Global bit mask. */
1458	#define X86_PTE_G RT_BIT(8)
1459
1460	/** Bits 9-11 - - Available for use to system software. */
1461	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1462	/** Bits 12-31 - - Physical Page number of the next level. */
1463	#define X86_PTE_PG_MASK ( 0xfffff000 )
1464
1465	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1466	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1467	/** Bits 63 - NX - PAE/LM - No execution flag. */
1468	#define X86_PTE_PAE_NX RT_BIT_64(63)
1469	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1470	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1471	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1472	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1473	/** No bits - - LM - MBZ bits when NX is active. */
1474	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1475	/** Bits 63 - - LM - MBZ bits when no NX. */
1476	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1477
1478	/**
1479	* Page table entry.
1480	*/
1481	typedef struct X86PTEBITS
1482	{
1483	/** Flags whether(=1) or not the page is present. */
1484	uint32_t u1Present : 1;
1485	/** Read(=0) / Write(=1) flag. */
1486	uint32_t u1Write : 1;
1487	/** User(=1) / Supervisor (=0) flag. */
1488	uint32_t u1User : 1;
1489	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1490	uint32_t u1WriteThru : 1;
1491	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1492	uint32_t u1CacheDisable : 1;
1493	/** Accessed flag.
1494	* Indicates that the page have been read or written to. */
1495	uint32_t u1Accessed : 1;
1496	/** Dirty flag.
1497	* Indicates that the page has been written to. */
1498	uint32_t u1Dirty : 1;
1499	/** Reserved / If PAT enabled, bit 2 of the index. */
1500	uint32_t u1PAT : 1;
1501	/** Global flag. (Ignored in all but final level.) */
1502	uint32_t u1Global : 1;
1503	/** Available for use to system software. */
1504	uint32_t u3Available : 3;
1505	/** Physical Page number of the next level. */
1506	uint32_t u20PageNo : 20;
1507	} X86PTEBITS;
1508	#ifndef VBOX_FOR_DTRACE_LIB
1509	AssertCompileSize(X86PTEBITS, 4);
1510	#endif
1511	/** Pointer to a page table entry. */
1512	typedef X86PTEBITS *PX86PTEBITS;
1513	/** Pointer to a const page table entry. */
1514	typedef const X86PTEBITS *PCX86PTEBITS;
1515
1516	/**
1517	* Page table entry.
1518	*/
1519	typedef union X86PTE
1520	{
1521	/** Unsigned integer view */
1522	X86PGUINT u;
1523	/** Bit field view. */
1524	X86PTEBITS n;
1525	/** 32-bit view. */
1526	uint32_t au32[1];
1527	/** 16-bit view. */
1528	uint16_t au16[2];
1529	/** 8-bit view. */
1530	uint8_t au8[4];
1531	} X86PTE;
1532	#ifndef VBOX_FOR_DTRACE_LIB
1533	AssertCompileSize(X86PTE, 4);
1534	#endif
1535	/** Pointer to a page table entry. */
1536	typedef X86PTE *PX86PTE;
1537	/** Pointer to a const page table entry. */
1538	typedef const X86PTE *PCX86PTE;
1539
1540
1541	/**
1542	* PAE page table entry.
1543	*/
1544	typedef struct X86PTEPAEBITS
1545	{
1546	/** Flags whether(=1) or not the page is present. */
1547	uint32_t u1Present : 1;
1548	/** Read(=0) / Write(=1) flag. */
1549	uint32_t u1Write : 1;
1550	/** User(=1) / Supervisor(=0) flag. */
1551	uint32_t u1User : 1;
1552	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1553	uint32_t u1WriteThru : 1;
1554	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1555	uint32_t u1CacheDisable : 1;
1556	/** Accessed flag.
1557	* Indicates that the page have been read or written to. */
1558	uint32_t u1Accessed : 1;
1559	/** Dirty flag.
1560	* Indicates that the page has been written to. */
1561	uint32_t u1Dirty : 1;
1562	/** Reserved / If PAT enabled, bit 2 of the index. */
1563	uint32_t u1PAT : 1;
1564	/** Global flag. (Ignored in all but final level.) */
1565	uint32_t u1Global : 1;
1566	/** Available for use to system software. */
1567	uint32_t u3Available : 3;
1568	/** Physical Page number of the next level - Low Part. Don't use this. */
1569	uint32_t u20PageNoLow : 20;
1570	/** Physical Page number of the next level - High Part. Don't use this. */
1571	uint32_t u20PageNoHigh : 20;
1572	/** MBZ bits */
1573	uint32_t u11Reserved : 11;
1574	/** No Execute flag. */
1575	uint32_t u1NoExecute : 1;
1576	} X86PTEPAEBITS;
1577	#ifndef VBOX_FOR_DTRACE_LIB
1578	AssertCompileSize(X86PTEPAEBITS, 8);
1579	#endif
1580	/** Pointer to a page table entry. */
1581	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1582	/** Pointer to a page table entry. */
1583	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1584
1585	/**
1586	* PAE Page table entry.
1587	*/
1588	typedef union X86PTEPAE
1589	{
1590	/** Unsigned integer view */
1591	X86PGPAEUINT u;
1592	/** Bit field view. */
1593	X86PTEPAEBITS n;
1594	/** 32-bit view. */
1595	uint32_t au32[2];
1596	/** 16-bit view. */
1597	uint16_t au16[4];
1598	/** 8-bit view. */
1599	uint8_t au8[8];
1600	} X86PTEPAE;
1601	#ifndef VBOX_FOR_DTRACE_LIB
1602	AssertCompileSize(X86PTEPAE, 8);
1603	#endif
1604	/** Pointer to a PAE page table entry. */
1605	typedef X86PTEPAE *PX86PTEPAE;
1606	/** Pointer to a const PAE page table entry. */
1607	typedef const X86PTEPAE *PCX86PTEPAE;
1608	/** @} */
1609
1610	/**
1611	* Page table.
1612	*/
1613	typedef struct X86PT
1614	{
1615	/** PTE Array. */
1616	X86PTE a[X86_PG_ENTRIES];
1617	} X86PT;
1618	#ifndef VBOX_FOR_DTRACE_LIB
1619	AssertCompileSize(X86PT, 4096);
1620	#endif
1621	/** Pointer to a page table. */
1622	typedef X86PT *PX86PT;
1623	/** Pointer to a const page table. */
1624	typedef const X86PT *PCX86PT;
1625
1626	/** The page shift to get the PT index. */
1627	#define X86_PT_SHIFT 12
1628	/** The PT index mask (apply to a shifted page address). */
1629	#define X86_PT_MASK 0x3ff
1630
1631
1632	/**
1633	* Page directory.
1634	*/
1635	typedef struct X86PTPAE
1636	{
1637	/** PTE Array. */
1638	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1639	} X86PTPAE;
1640	#ifndef VBOX_FOR_DTRACE_LIB
1641	AssertCompileSize(X86PTPAE, 4096);
1642	#endif
1643	/** Pointer to a page table. */
1644	typedef X86PTPAE *PX86PTPAE;
1645	/** Pointer to a const page table. */
1646	typedef const X86PTPAE *PCX86PTPAE;
1647
1648	/** The page shift to get the PA PTE index. */
1649	#define X86_PT_PAE_SHIFT 12
1650	/** The PAE PT index mask (apply to a shifted page address). */
1651	#define X86_PT_PAE_MASK 0x1ff
1652
1653
1654	/** @name 4KB Page Directory Entry
1655	* @{
1656	*/
1657	/** Bit 0 - P - Present bit. */
1658	#define X86_PDE_P RT_BIT(0)
1659	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1660	#define X86_PDE_RW RT_BIT(1)
1661	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1662	#define X86_PDE_US RT_BIT(2)
1663	/** Bit 3 - PWT - Page level write thru bit. */
1664	#define X86_PDE_PWT RT_BIT(3)
1665	/** Bit 4 - PCD - Page level cache disable bit. */
1666	#define X86_PDE_PCD RT_BIT(4)
1667	/** Bit 5 - A - Access bit. */
1668	#define X86_PDE_A RT_BIT(5)
1669	/** Bit 7 - PS - Page size attribute.
1670	* Clear mean 4KB pages, set means large pages (2/4MB). */
1671	#define X86_PDE_PS RT_BIT(7)
1672	/** Bits 9-11 - - Available for use to system software. */
1673	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1674	/** Bits 12-31 - - Physical Page number of the next level. */
1675	#define X86_PDE_PG_MASK ( 0xfffff000 )
1676
1677	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1678	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1679	/** Bits 63 - NX - PAE/LM - No execution flag. */
1680	#define X86_PDE_PAE_NX RT_BIT_64(63)
1681	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1682	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1683	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1684	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1685	/** Bit 7 - - LM - MBZ bits when NX is active. */
1686	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1687	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1688	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1689
1690	/**
1691	* Page directory entry.
1692	*/
1693	typedef struct X86PDEBITS
1694	{
1695	/** Flags whether(=1) or not the page is present. */
1696	uint32_t u1Present : 1;
1697	/** Read(=0) / Write(=1) flag. */
1698	uint32_t u1Write : 1;
1699	/** User(=1) / Supervisor (=0) flag. */
1700	uint32_t u1User : 1;
1701	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1702	uint32_t u1WriteThru : 1;
1703	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1704	uint32_t u1CacheDisable : 1;
1705	/** Accessed flag.
1706	* Indicates that the page has been read or written to. */
1707	uint32_t u1Accessed : 1;
1708	/** Reserved / Ignored (dirty bit). */
1709	uint32_t u1Reserved0 : 1;
1710	/** Size bit if PSE is enabled - in any event it's 0. */
1711	uint32_t u1Size : 1;
1712	/** Reserved / Ignored (global bit). */
1713	uint32_t u1Reserved1 : 1;
1714	/** Available for use to system software. */
1715	uint32_t u3Available : 3;
1716	/** Physical Page number of the next level. */
1717	uint32_t u20PageNo : 20;
1718	} X86PDEBITS;
1719	#ifndef VBOX_FOR_DTRACE_LIB
1720	AssertCompileSize(X86PDEBITS, 4);
1721	#endif
1722	/** Pointer to a page directory entry. */
1723	typedef X86PDEBITS *PX86PDEBITS;
1724	/** Pointer to a const page directory entry. */
1725	typedef const X86PDEBITS *PCX86PDEBITS;
1726
1727
1728	/**
1729	* PAE page directory entry.
1730	*/
1731	typedef struct X86PDEPAEBITS
1732	{
1733	/** Flags whether(=1) or not the page is present. */
1734	uint32_t u1Present : 1;
1735	/** Read(=0) / Write(=1) flag. */
1736	uint32_t u1Write : 1;
1737	/** User(=1) / Supervisor (=0) flag. */
1738	uint32_t u1User : 1;
1739	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1740	uint32_t u1WriteThru : 1;
1741	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1742	uint32_t u1CacheDisable : 1;
1743	/** Accessed flag.
1744	* Indicates that the page has been read or written to. */
1745	uint32_t u1Accessed : 1;
1746	/** Reserved / Ignored (dirty bit). */
1747	uint32_t u1Reserved0 : 1;
1748	/** Size bit if PSE is enabled - in any event it's 0. */
1749	uint32_t u1Size : 1;
1750	/** Reserved / Ignored (global bit). / */
1751	uint32_t u1Reserved1 : 1;
1752	/** Available for use to system software. */
1753	uint32_t u3Available : 3;
1754	/** Physical Page number of the next level - Low Part. Don't use! */
1755	uint32_t u20PageNoLow : 20;
1756	/** Physical Page number of the next level - High Part. Don't use! */
1757	uint32_t u20PageNoHigh : 20;
1758	/** MBZ bits */
1759	uint32_t u11Reserved : 11;
1760	/** No Execute flag. */
1761	uint32_t u1NoExecute : 1;
1762	} X86PDEPAEBITS;
1763	#ifndef VBOX_FOR_DTRACE_LIB
1764	AssertCompileSize(X86PDEPAEBITS, 8);
1765	#endif
1766	/** Pointer to a page directory entry. */
1767	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1768	/** Pointer to a const page directory entry. */
1769	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1770
1771	/** @} */
1772
1773
1774	/** @name 2/4MB Page Directory Entry
1775	* @{
1776	*/
1777	/** Bit 0 - P - Present bit. */
1778	#define X86_PDE4M_P RT_BIT(0)
1779	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1780	#define X86_PDE4M_RW RT_BIT(1)
1781	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1782	#define X86_PDE4M_US RT_BIT(2)
1783	/** Bit 3 - PWT - Page level write thru bit. */
1784	#define X86_PDE4M_PWT RT_BIT(3)
1785	/** Bit 4 - PCD - Page level cache disable bit. */
1786	#define X86_PDE4M_PCD RT_BIT(4)
1787	/** Bit 5 - A - Access bit. */
1788	#define X86_PDE4M_A RT_BIT(5)
1789	/** Bit 6 - D - Dirty bit. */
1790	#define X86_PDE4M_D RT_BIT(6)
1791	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1792	#define X86_PDE4M_PS RT_BIT(7)
1793	/** Bit 8 - G - Global flag. */
1794	#define X86_PDE4M_G RT_BIT(8)
1795	/** Bits 9-11 - AVL - Available for use to system software. */
1796	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1797	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1798	#define X86_PDE4M_PAT RT_BIT(12)
1799	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1800	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1801	/** Bits 22-31 - - Physical Page number. */
1802	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1803	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1804	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1805	/** The number of bits to the high part of the page number. */
1806	#define X86_PDE4M_PG_HIGH_SHIFT 19
1807	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1808	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1809
1810	/** Bits 21-51 - - PAE/LM - Physical Page number.
1811	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1812	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1813	/** Bits 63 - NX - PAE/LM - No execution flag. */
1814	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1815	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1816	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1817	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1818	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1819	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1820	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1821	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1822	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1823
1824	/**
1825	* 4MB page directory entry.
1826	*/
1827	typedef struct X86PDE4MBITS
1828	{
1829	/** Flags whether(=1) or not the page is present. */
1830	uint32_t u1Present : 1;
1831	/** Read(=0) / Write(=1) flag. */
1832	uint32_t u1Write : 1;
1833	/** User(=1) / Supervisor (=0) flag. */
1834	uint32_t u1User : 1;
1835	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1836	uint32_t u1WriteThru : 1;
1837	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1838	uint32_t u1CacheDisable : 1;
1839	/** Accessed flag.
1840	* Indicates that the page have been read or written to. */
1841	uint32_t u1Accessed : 1;
1842	/** Dirty flag.
1843	* Indicates that the page has been written to. */
1844	uint32_t u1Dirty : 1;
1845	/** Page size flag - always 1 for 4MB entries. */
1846	uint32_t u1Size : 1;
1847	/** Global flag. */
1848	uint32_t u1Global : 1;
1849	/** Available for use to system software. */
1850	uint32_t u3Available : 3;
1851	/** Reserved / If PAT enabled, bit 2 of the index. */
1852	uint32_t u1PAT : 1;
1853	/** Bits 32-39 of the page number on AMD64.
1854	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1855	uint32_t u8PageNoHigh : 8;
1856	/** Reserved. */
1857	uint32_t u1Reserved : 1;
1858	/** Physical Page number of the page. */
1859	uint32_t u10PageNo : 10;
1860	} X86PDE4MBITS;
1861	#ifndef VBOX_FOR_DTRACE_LIB
1862	AssertCompileSize(X86PDE4MBITS, 4);
1863	#endif
1864	/** Pointer to a page table entry. */
1865	typedef X86PDE4MBITS *PX86PDE4MBITS;
1866	/** Pointer to a const page table entry. */
1867	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1868
1869
1870	/**
1871	* 2MB PAE page directory entry.
1872	*/
1873	typedef struct X86PDE2MPAEBITS
1874	{
1875	/** Flags whether(=1) or not the page is present. */
1876	uint32_t u1Present : 1;
1877	/** Read(=0) / Write(=1) flag. */
1878	uint32_t u1Write : 1;
1879	/** User(=1) / Supervisor(=0) flag. */
1880	uint32_t u1User : 1;
1881	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1882	uint32_t u1WriteThru : 1;
1883	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1884	uint32_t u1CacheDisable : 1;
1885	/** Accessed flag.
1886	* Indicates that the page have been read or written to. */
1887	uint32_t u1Accessed : 1;
1888	/** Dirty flag.
1889	* Indicates that the page has been written to. */
1890	uint32_t u1Dirty : 1;
1891	/** Page size flag - always 1 for 2MB entries. */
1892	uint32_t u1Size : 1;
1893	/** Global flag. */
1894	uint32_t u1Global : 1;
1895	/** Available for use to system software. */
1896	uint32_t u3Available : 3;
1897	/** Reserved / If PAT enabled, bit 2 of the index. */
1898	uint32_t u1PAT : 1;
1899	/** Reserved. */
1900	uint32_t u9Reserved : 9;
1901	/** Physical Page number of the next level - Low part. Don't use! */
1902	uint32_t u10PageNoLow : 10;
1903	/** Physical Page number of the next level - High part. Don't use! */
1904	uint32_t u20PageNoHigh : 20;
1905	/** MBZ bits */
1906	uint32_t u11Reserved : 11;
1907	/** No Execute flag. */
1908	uint32_t u1NoExecute : 1;
1909	} X86PDE2MPAEBITS;
1910	#ifndef VBOX_FOR_DTRACE_LIB
1911	AssertCompileSize(X86PDE2MPAEBITS, 8);
1912	#endif
1913	/** Pointer to a 2MB PAE page table entry. */
1914	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1915	/** Pointer to a 2MB PAE page table entry. */
1916	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1917
1918	/** @} */
1919
1920	/**
1921	* Page directory entry.
1922	*/
1923	typedef union X86PDE
1924	{
1925	/** Unsigned integer view. */
1926	X86PGUINT u;
1927	/** Normal view. */
1928	X86PDEBITS n;
1929	/** 4MB view (big). */
1930	X86PDE4MBITS b;
1931	/** 8 bit unsigned integer view. */
1932	uint8_t au8[4];
1933	/** 16 bit unsigned integer view. */
1934	uint16_t au16[2];
1935	/** 32 bit unsigned integer view. */
1936	uint32_t au32[1];
1937	} X86PDE;
1938	#ifndef VBOX_FOR_DTRACE_LIB
1939	AssertCompileSize(X86PDE, 4);
1940	#endif
1941	/** Pointer to a page directory entry. */
1942	typedef X86PDE *PX86PDE;
1943	/** Pointer to a const page directory entry. */
1944	typedef const X86PDE *PCX86PDE;
1945
1946	/**
1947	* PAE page directory entry.
1948	*/
1949	typedef union X86PDEPAE
1950	{
1951	/** Unsigned integer view. */
1952	X86PGPAEUINT u;
1953	/** Normal view. */
1954	X86PDEPAEBITS n;
1955	/** 2MB page view (big). */
1956	X86PDE2MPAEBITS b;
1957	/** 8 bit unsigned integer view. */
1958	uint8_t au8[8];
1959	/** 16 bit unsigned integer view. */
1960	uint16_t au16[4];
1961	/** 32 bit unsigned integer view. */
1962	uint32_t au32[2];
1963	} X86PDEPAE;
1964	#ifndef VBOX_FOR_DTRACE_LIB
1965	AssertCompileSize(X86PDEPAE, 8);
1966	#endif
1967	/** Pointer to a page directory entry. */
1968	typedef X86PDEPAE *PX86PDEPAE;
1969	/** Pointer to a const page directory entry. */
1970	typedef const X86PDEPAE *PCX86PDEPAE;
1971
1972	/**
1973	* Page directory.
1974	*/
1975	typedef struct X86PD
1976	{
1977	/** PDE Array. */
1978	X86PDE a[X86_PG_ENTRIES];
1979	} X86PD;
1980	#ifndef VBOX_FOR_DTRACE_LIB
1981	AssertCompileSize(X86PD, 4096);
1982	#endif
1983	/** Pointer to a page directory. */
1984	typedef X86PD *PX86PD;
1985	/** Pointer to a const page directory. */
1986	typedef const X86PD *PCX86PD;
1987
1988	/** The page shift to get the PD index. */
1989	#define X86_PD_SHIFT 22
1990	/** The PD index mask (apply to a shifted page address). */
1991	#define X86_PD_MASK 0x3ff
1992
1993
1994	/**
1995	* PAE page directory.
1996	*/
1997	typedef struct X86PDPAE
1998	{
1999	/** PDE Array. */
2000	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2001	} X86PDPAE;
2002	#ifndef VBOX_FOR_DTRACE_LIB
2003	AssertCompileSize(X86PDPAE, 4096);
2004	#endif
2005	/** Pointer to a PAE page directory. */
2006	typedef X86PDPAE *PX86PDPAE;
2007	/** Pointer to a const PAE page directory. */
2008	typedef const X86PDPAE *PCX86PDPAE;
2009
2010	/** The page shift to get the PAE PD index. */
2011	#define X86_PD_PAE_SHIFT 21
2012	/** The PAE PD index mask (apply to a shifted page address). */
2013	#define X86_PD_PAE_MASK 0x1ff
2014
2015
2016	/** @name Page Directory Pointer Table Entry (PAE)
2017	* @{
2018	*/
2019	/** Bit 0 - P - Present bit. */
2020	#define X86_PDPE_P RT_BIT(0)
2021	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2022	#define X86_PDPE_RW RT_BIT(1)
2023	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2024	#define X86_PDPE_US RT_BIT(2)
2025	/** Bit 3 - PWT - Page level write thru bit. */
2026	#define X86_PDPE_PWT RT_BIT(3)
2027	/** Bit 4 - PCD - Page level cache disable bit. */
2028	#define X86_PDPE_PCD RT_BIT(4)
2029	/** Bit 5 - A - Access bit. Long Mode only. */
2030	#define X86_PDPE_A RT_BIT(5)
2031	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2032	#define X86_PDPE_LM_PS RT_BIT(7)
2033	/** Bits 9-11 - - Available for use to system software. */
2034	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2035	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2036	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2037	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2038	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2039	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2040	#define X86_PDPE_LM_NX RT_BIT_64(63)
2041	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2042	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2043	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2044	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2045	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2046	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2047	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2048	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2049
2050
2051	/**
2052	* Page directory pointer table entry.
2053	*/
2054	typedef struct X86PDPEBITS
2055	{
2056	/** Flags whether(=1) or not the page is present. */
2057	uint32_t u1Present : 1;
2058	/** Chunk of reserved bits. */
2059	uint32_t u2Reserved : 2;
2060	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2061	uint32_t u1WriteThru : 1;
2062	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2063	uint32_t u1CacheDisable : 1;
2064	/** Chunk of reserved bits. */
2065	uint32_t u4Reserved : 4;
2066	/** Available for use to system software. */
2067	uint32_t u3Available : 3;
2068	/** Physical Page number of the next level - Low Part. Don't use! */
2069	uint32_t u20PageNoLow : 20;
2070	/** Physical Page number of the next level - High Part. Don't use! */
2071	uint32_t u20PageNoHigh : 20;
2072	/** MBZ bits */
2073	uint32_t u12Reserved : 12;
2074	} X86PDPEBITS;
2075	#ifndef VBOX_FOR_DTRACE_LIB
2076	AssertCompileSize(X86PDPEBITS, 8);
2077	#endif
2078	/** Pointer to a page directory pointer table entry. */
2079	typedef X86PDPEBITS *PX86PTPEBITS;
2080	/** Pointer to a const page directory pointer table entry. */
2081	typedef const X86PDPEBITS *PCX86PTPEBITS;
2082
2083	/**
2084	* Page directory pointer table entry. AMD64 version
2085	*/
2086	typedef struct X86PDPEAMD64BITS
2087	{
2088	/** Flags whether(=1) or not the page is present. */
2089	uint32_t u1Present : 1;
2090	/** Read(=0) / Write(=1) flag. */
2091	uint32_t u1Write : 1;
2092	/** User(=1) / Supervisor (=0) flag. */
2093	uint32_t u1User : 1;
2094	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2095	uint32_t u1WriteThru : 1;
2096	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2097	uint32_t u1CacheDisable : 1;
2098	/** Accessed flag.
2099	* Indicates that the page have been read or written to. */
2100	uint32_t u1Accessed : 1;
2101	/** Chunk of reserved bits. */
2102	uint32_t u3Reserved : 3;
2103	/** Available for use to system software. */
2104	uint32_t u3Available : 3;
2105	/** Physical Page number of the next level - Low Part. Don't use! */
2106	uint32_t u20PageNoLow : 20;
2107	/** Physical Page number of the next level - High Part. Don't use! */
2108	uint32_t u20PageNoHigh : 20;
2109	/** MBZ bits */
2110	uint32_t u11Reserved : 11;
2111	/** No Execute flag. */
2112	uint32_t u1NoExecute : 1;
2113	} X86PDPEAMD64BITS;
2114	#ifndef VBOX_FOR_DTRACE_LIB
2115	AssertCompileSize(X86PDPEAMD64BITS, 8);
2116	#endif
2117	/** Pointer to a page directory pointer table entry. */
2118	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2119	/** Pointer to a const page directory pointer table entry. */
2120	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2121
2122	/**
2123	* Page directory pointer table entry.
2124	*/
2125	typedef union X86PDPE
2126	{
2127	/** Unsigned integer view. */
2128	X86PGPAEUINT u;
2129	/** Normal view. */
2130	X86PDPEBITS n;
2131	/** AMD64 view. */
2132	X86PDPEAMD64BITS lm;
2133	/** 8 bit unsigned integer view. */
2134	uint8_t au8[8];
2135	/** 16 bit unsigned integer view. */
2136	uint16_t au16[4];
2137	/** 32 bit unsigned integer view. */
2138	uint32_t au32[2];
2139	} X86PDPE;
2140	#ifndef VBOX_FOR_DTRACE_LIB
2141	AssertCompileSize(X86PDPE, 8);
2142	#endif
2143	/** Pointer to a page directory pointer table entry. */
2144	typedef X86PDPE *PX86PDPE;
2145	/** Pointer to a const page directory pointer table entry. */
2146	typedef const X86PDPE *PCX86PDPE;
2147
2148
2149	/**
2150	* Page directory pointer table.
2151	*/
2152	typedef struct X86PDPT
2153	{
2154	/** PDE Array. */
2155	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2156	} X86PDPT;
2157	#ifndef VBOX_FOR_DTRACE_LIB
2158	AssertCompileSize(X86PDPT, 4096);
2159	#endif
2160	/** Pointer to a page directory pointer table. */
2161	typedef X86PDPT *PX86PDPT;
2162	/** Pointer to a const page directory pointer table. */
2163	typedef const X86PDPT *PCX86PDPT;
2164
2165	/** The page shift to get the PDPT index. */
2166	#define X86_PDPT_SHIFT 30
2167	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2168	#define X86_PDPT_MASK_PAE 0x3
2169	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2170	#define X86_PDPT_MASK_AMD64 0x1ff
2171
2172	/** @} */
2173
2174
2175	/** @name Page Map Level-4 Entry (Long Mode PAE)
2176	* @{
2177	*/
2178	/** Bit 0 - P - Present bit. */
2179	#define X86_PML4E_P RT_BIT(0)
2180	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2181	#define X86_PML4E_RW RT_BIT(1)
2182	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2183	#define X86_PML4E_US RT_BIT(2)
2184	/** Bit 3 - PWT - Page level write thru bit. */
2185	#define X86_PML4E_PWT RT_BIT(3)
2186	/** Bit 4 - PCD - Page level cache disable bit. */
2187	#define X86_PML4E_PCD RT_BIT(4)
2188	/** Bit 5 - A - Access bit. */
2189	#define X86_PML4E_A RT_BIT(5)
2190	/** Bits 9-11 - - Available for use to system software. */
2191	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2192	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2193	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2194	/** Bits 8, 7 - - MBZ bits when NX is active. */
2195	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2196	/** Bits 63, 7 - - MBZ bits when no NX. */
2197	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2198	/** Bits 63 - NX - PAE - No execution flag. */
2199	#define X86_PML4E_NX RT_BIT_64(63)
2200
2201	/**
2202	* Page Map Level-4 Entry
2203	*/
2204	typedef struct X86PML4EBITS
2205	{
2206	/** Flags whether(=1) or not the page is present. */
2207	uint32_t u1Present : 1;
2208	/** Read(=0) / Write(=1) flag. */
2209	uint32_t u1Write : 1;
2210	/** User(=1) / Supervisor (=0) flag. */
2211	uint32_t u1User : 1;
2212	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2213	uint32_t u1WriteThru : 1;
2214	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2215	uint32_t u1CacheDisable : 1;
2216	/** Accessed flag.
2217	* Indicates that the page have been read or written to. */
2218	uint32_t u1Accessed : 1;
2219	/** Chunk of reserved bits. */
2220	uint32_t u3Reserved : 3;
2221	/** Available for use to system software. */
2222	uint32_t u3Available : 3;
2223	/** Physical Page number of the next level - Low Part. Don't use! */
2224	uint32_t u20PageNoLow : 20;
2225	/** Physical Page number of the next level - High Part. Don't use! */
2226	uint32_t u20PageNoHigh : 20;
2227	/** MBZ bits */
2228	uint32_t u11Reserved : 11;
2229	/** No Execute flag. */
2230	uint32_t u1NoExecute : 1;
2231	} X86PML4EBITS;
2232	#ifndef VBOX_FOR_DTRACE_LIB
2233	AssertCompileSize(X86PML4EBITS, 8);
2234	#endif
2235	/** Pointer to a page map level-4 entry. */
2236	typedef X86PML4EBITS *PX86PML4EBITS;
2237	/** Pointer to a const page map level-4 entry. */
2238	typedef const X86PML4EBITS *PCX86PML4EBITS;
2239
2240	/**
2241	* Page Map Level-4 Entry.
2242	*/
2243	typedef union X86PML4E
2244	{
2245	/** Unsigned integer view. */
2246	X86PGPAEUINT u;
2247	/** Normal view. */
2248	X86PML4EBITS n;
2249	/** 8 bit unsigned integer view. */
2250	uint8_t au8[8];
2251	/** 16 bit unsigned integer view. */
2252	uint16_t au16[4];
2253	/** 32 bit unsigned integer view. */
2254	uint32_t au32[2];
2255	} X86PML4E;
2256	#ifndef VBOX_FOR_DTRACE_LIB
2257	AssertCompileSize(X86PML4E, 8);
2258	#endif
2259	/** Pointer to a page map level-4 entry. */
2260	typedef X86PML4E *PX86PML4E;
2261	/** Pointer to a const page map level-4 entry. */
2262	typedef const X86PML4E *PCX86PML4E;
2263
2264
2265	/**
2266	* Page Map Level-4.
2267	*/
2268	typedef struct X86PML4
2269	{
2270	/** PDE Array. */
2271	X86PML4E a[X86_PG_PAE_ENTRIES];
2272	} X86PML4;
2273	#ifndef VBOX_FOR_DTRACE_LIB
2274	AssertCompileSize(X86PML4, 4096);
2275	#endif
2276	/** Pointer to a page map level-4. */
2277	typedef X86PML4 *PX86PML4;
2278	/** Pointer to a const page map level-4. */
2279	typedef const X86PML4 *PCX86PML4;
2280
2281	/** The page shift to get the PML4 index. */
2282	#define X86_PML4_SHIFT 39
2283	/** The PML4 index mask (apply to a shifted page address). */
2284	#define X86_PML4_MASK 0x1ff
2285
2286	/** @} */
2287
2288	/** @} */
2289
2290	/**
2291	* 32-bit protected mode FSTENV image.
2292	*/
2293	typedef struct X86FSTENV32P
2294	{
2295	uint16_t FCW;
2296	uint16_t padding1;
2297	uint16_t FSW;
2298	uint16_t padding2;
2299	uint16_t FTW;
2300	uint16_t padding3;
2301	uint32_t FPUIP;
2302	uint16_t FPUCS;
2303	uint16_t FOP;
2304	uint32_t FPUDP;
2305	uint16_t FPUDS;
2306	uint16_t padding4;
2307	} X86FSTENV32P;
2308	/** Pointer to a 32-bit protected mode FSTENV image. */
2309	typedef X86FSTENV32P *PX86FSTENV32P;
2310	/** Pointer to a const 32-bit protected mode FSTENV image. */
2311	typedef X86FSTENV32P const *PCX86FSTENV32P;
2312
2313
2314	/**
2315	* 80-bit MMX/FPU register type.
2316	*/
2317	typedef struct X86FPUMMX
2318	{
2319	uint8_t reg[10];
2320	} X86FPUMMX;
2321	#ifndef VBOX_FOR_DTRACE_LIB
2322	AssertCompileSize(X86FPUMMX, 10);
2323	#endif
2324	/** Pointer to a 80-bit MMX/FPU register type. */
2325	typedef X86FPUMMX *PX86FPUMMX;
2326	/** Pointer to a const 80-bit MMX/FPU register type. */
2327	typedef const X86FPUMMX *PCX86FPUMMX;
2328
2329	/** FPU (x87) register. */
2330	typedef union X86FPUREG
2331	{
2332	/** MMX view. */
2333	uint64_t mmx;
2334	/** FPU view - todo. */
2335	X86FPUMMX fpu;
2336	/** Extended precision floating point view. */
2337	RTFLOAT80U r80;
2338	/** Extended precision floating point view v2 */
2339	RTFLOAT80U2 r80Ex;
2340	/** 8-bit view. */
2341	uint8_t au8[16];
2342	/** 16-bit view. */
2343	uint16_t au16[8];
2344	/** 32-bit view. */
2345	uint32_t au32[4];
2346	/** 64-bit view. */
2347	uint64_t au64[2];
2348	/** 128-bit view. (yeah, very helpful) */
2349	uint128_t au128[1];
2350	} X86FPUREG;
2351	#ifndef VBOX_FOR_DTRACE_LIB
2352	AssertCompileSize(X86FPUREG, 16);
2353	#endif
2354	/** Pointer to a FPU register. */
2355	typedef X86FPUREG *PX86FPUREG;
2356	/** Pointer to a const FPU register. */
2357	typedef X86FPUREG const *PCX86FPUREG;
2358
2359	/**
2360	* XMM register union.
2361	*/
2362	typedef union X86XMMREG
2363	{
2364	/** XMM Register view . /
2365	uint128_t xmm;
2366	/** 8-bit view. */
2367	uint8_t au8[16];
2368	/** 16-bit view. */
2369	uint16_t au16[8];
2370	/** 32-bit view. */
2371	uint32_t au32[4];
2372	/** 64-bit view. */
2373	uint64_t au64[2];
2374	/** 128-bit view. (yeah, very helpful) */
2375	uint128_t au128[1];
2376	} X86XMMREG;
2377	#ifndef VBOX_FOR_DTRACE_LIB
2378	AssertCompileSize(X86XMMREG, 16);
2379	#endif
2380	/** Pointer to an XMM register state. */
2381	typedef X86XMMREG *PX86XMMREG;
2382	/** Pointer to a const XMM register state. */
2383	typedef X86XMMREG const *PCX86XMMREG;
2384
2385	/**
2386	* YMM register union.
2387	*/
2388	typedef union X86YMMREG
2389	{
2390	/** 8-bit view. */
2391	uint8_t au8[32];
2392	/** 16-bit view. */
2393	uint16_t au16[16];
2394	/** 32-bit view. */
2395	uint32_t au32[8];
2396	/** 64-bit view. */
2397	uint64_t au64[4];
2398	/** 128-bit view. (yeah, very helpful) */
2399	uint128_t au128[2];
2400	/** XMM sub register view. */
2401	X86XMMREG aXmm[2];
2402	} X86YMMREG;
2403	#ifndef VBOX_FOR_DTRACE_LIB
2404	AssertCompileSize(X86YMMREG, 32);
2405	#endif
2406	/** Pointer to an YMM register state. */
2407	typedef X86YMMREG *PX86YMMREG;
2408	/** Pointer to a const YMM register state. */
2409	typedef X86YMMREG const *PCX86YMMREG;
2410
2411	/**
2412	* ZMM register union.
2413	*/
2414	typedef union X86ZMMREG
2415	{
2416	/** 8-bit view. */
2417	uint8_t au8[64];
2418	/** 16-bit view. */
2419	uint16_t au16[32];
2420	/** 32-bit view. */
2421	uint32_t au32[16];
2422	/** 64-bit view. */
2423	uint64_t au64[8];
2424	/** 128-bit view. (yeah, very helpful) */
2425	uint128_t au128[4];
2426	/** XMM sub register view. */
2427	X86XMMREG aXmm[4];
2428	/** YMM sub register view. */
2429	X86YMMREG aYmm[2];
2430	} X86ZMMREG;
2431	#ifndef VBOX_FOR_DTRACE_LIB
2432	AssertCompileSize(X86ZMMREG, 64);
2433	#endif
2434	/** Pointer to an ZMM register state. */
2435	typedef X86ZMMREG *PX86ZMMREG;
2436	/** Pointer to a const ZMM register state. */
2437	typedef X86ZMMREG const *PCX86ZMMREG;
2438
2439
2440	/**
2441	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2442	* @todo verify this...
2443	*/
2444	#pragma pack(1)
2445	typedef struct X86FPUSTATE
2446	{
2447	/** 0x00 - Control word. */
2448	uint16_t FCW;
2449	/** 0x02 - Alignment word */
2450	uint16_t Dummy1;
2451	/** 0x04 - Status word. */
2452	uint16_t FSW;
2453	/** 0x06 - Alignment word */
2454	uint16_t Dummy2;
2455	/** 0x08 - Tag word */
2456	uint16_t FTW;
2457	/** 0x0a - Alignment word */
2458	uint16_t Dummy3;
2459
2460	/** 0x0c - Instruction pointer. */
2461	uint32_t FPUIP;
2462	/** 0x10 - Code selector. */
2463	uint16_t CS;
2464	/** 0x12 - Opcode. */
2465	uint16_t FOP;
2466	/** 0x14 - FOO. */
2467	uint32_t FPUOO;
2468	/** 0x18 - FOS. */
2469	uint32_t FPUOS;
2470	/** 0x1c - FPU register. */
2471	X86FPUREG regs[8];
2472	} X86FPUSTATE;
2473	#pragma pack()
2474	/** Pointer to a FPU state. */
2475	typedef X86FPUSTATE *PX86FPUSTATE;
2476	/** Pointer to a const FPU state. */
2477	typedef const X86FPUSTATE *PCX86FPUSTATE;
2478
2479	/**
2480	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2481	*/
2482	#pragma pack(1)
2483	typedef struct X86FXSTATE
2484	{
2485	/** 0x00 - Control word. */
2486	uint16_t FCW;
2487	/** 0x02 - Status word. */
2488	uint16_t FSW;
2489	/** 0x04 - Tag word. (The upper byte is always zero.) */
2490	uint16_t FTW;
2491	/** 0x06 - Opcode. */
2492	uint16_t FOP;
2493	/** 0x08 - Instruction pointer. */
2494	uint32_t FPUIP;
2495	/** 0x0c - Code selector. */
2496	uint16_t CS;
2497	uint16_t Rsrvd1;
2498	/** 0x10 - Data pointer. */
2499	uint32_t FPUDP;
2500	/** 0x14 - Data segment */
2501	uint16_t DS;
2502	/** 0x16 */
2503	uint16_t Rsrvd2;
2504	/** 0x18 */
2505	uint32_t MXCSR;
2506	/** 0x1c */
2507	uint32_t MXCSR_MASK;
2508	/** 0x20 - FPU registers. */
2509	X86FPUREG aRegs[8];
2510	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
2511	X86XMMREG aXMM[16];
2512	/* - offset 416 - */
2513	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2514	/* - offset 464 - Software usable reserved bits. */
2515	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2516	} X86FXSTATE;
2517	#pragma pack()
2518	/** Pointer to a FPU Extended state. */
2519	typedef X86FXSTATE *PX86FXSTATE;
2520	/** Pointer to a const FPU Extended state. */
2521	typedef const X86FXSTATE *PCX86FXSTATE;
2522
2523	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2524	* magic. Don't forget to update x86.mac if you change this! */
2525	#define X86_OFF_FXSTATE_RSVD 0x1d0
2526	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2527	* forget to update x86.mac if you change this!
2528	* @todo r=bird: This has nothing what-so-ever to do here.... */
2529	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2530	#ifndef VBOX_FOR_DTRACE_LIB
2531	AssertCompileSize(X86FXSTATE, 512);
2532	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2533	#endif
2534
2535	/** @name FPU status word flags.
2536	* @{ */
2537	/** Exception Flag: Invalid operation. */
2538	#define X86_FSW_IE RT_BIT(0)
2539	/** Exception Flag: Denormalized operand. */
2540	#define X86_FSW_DE RT_BIT(1)
2541	/** Exception Flag: Zero divide. */
2542	#define X86_FSW_ZE RT_BIT(2)
2543	/** Exception Flag: Overflow. */
2544	#define X86_FSW_OE RT_BIT(3)
2545	/** Exception Flag: Underflow. */
2546	#define X86_FSW_UE RT_BIT(4)
2547	/** Exception Flag: Precision. */
2548	#define X86_FSW_PE RT_BIT(5)
2549	/** Stack fault. */
2550	#define X86_FSW_SF RT_BIT(6)
2551	/** Error summary status. */
2552	#define X86_FSW_ES RT_BIT(7)
2553	/** Mask of exceptions flags, excluding the summary bit. */
2554	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2555	/** Mask of exceptions flags, including the summary bit. */
2556	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2557	/** Condition code 0. */
2558	#define X86_FSW_C0 RT_BIT(8)
2559	/** Condition code 1. */
2560	#define X86_FSW_C1 RT_BIT(9)
2561	/** Condition code 2. */
2562	#define X86_FSW_C2 RT_BIT(10)
2563	/** Top of the stack mask. */
2564	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2565	/** TOP shift value. */
2566	#define X86_FSW_TOP_SHIFT 11
2567	/** Mask for getting TOP value after shifting it right. */
2568	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2569	/** Get the TOP value. */
2570	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2571	/** Condition code 3. */
2572	#define X86_FSW_C3 RT_BIT(14)
2573	/** Mask of exceptions flags, including the summary bit. */
2574	#define X86_FSW_C_MASK UINT16_C(0x4700)
2575	/** FPU busy. */
2576	#define X86_FSW_B RT_BIT(15)
2577	/** @} */
2578
2579
2580	/** @name FPU control word flags.
2581	* @{ */
2582	/** Exception Mask: Invalid operation. */
2583	#define X86_FCW_IM RT_BIT(0)
2584	/** Exception Mask: Denormalized operand. */
2585	#define X86_FCW_DM RT_BIT(1)
2586	/** Exception Mask: Zero divide. */
2587	#define X86_FCW_ZM RT_BIT(2)
2588	/** Exception Mask: Overflow. */
2589	#define X86_FCW_OM RT_BIT(3)
2590	/** Exception Mask: Underflow. */
2591	#define X86_FCW_UM RT_BIT(4)
2592	/** Exception Mask: Precision. */
2593	#define X86_FCW_PM RT_BIT(5)
2594	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2595	* @remarks This includes reserved bit 6. */
2596	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2597	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2598	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2599	/** Precision control mask. */
2600	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2601	/** Precision control: 24-bit. */
2602	#define X86_FCW_PC_24 UINT16_C(0x0000)
2603	/** Precision control: Reserved. */
2604	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2605	/** Precision control: 53-bit. */
2606	#define X86_FCW_PC_53 UINT16_C(0x0200)
2607	/** Precision control: 64-bit. */
2608	#define X86_FCW_PC_64 UINT16_C(0x0300)
2609	/** Rounding control mask. */
2610	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2611	/** Rounding control: To nearest. */
2612	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2613	/** Rounding control: Down. */
2614	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2615	/** Rounding control: Up. */
2616	#define X86_FCW_RC_UP UINT16_C(0x0800)
2617	/** Rounding control: Towards zero. */
2618	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2619	/** Bits which should be zero, apparently. */
2620	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2621	/** @} */
2622
2623	/** @name SSE MXCSR
2624	* @{ */
2625	/** Exception Flag: Invalid operation. */
2626	#define X86_MXSCR_IE RT_BIT(0)
2627	/** Exception Flag: Denormalized operand. */
2628	#define X86_MXSCR_DE RT_BIT(1)
2629	/** Exception Flag: Zero divide. */
2630	#define X86_MXSCR_ZE RT_BIT(2)
2631	/** Exception Flag: Overflow. */
2632	#define X86_MXSCR_OE RT_BIT(3)
2633	/** Exception Flag: Underflow. */
2634	#define X86_MXSCR_UE RT_BIT(4)
2635	/** Exception Flag: Precision. */
2636	#define X86_MXSCR_PE RT_BIT(5)
2637
2638	/** Denormals are zero. */
2639	#define X86_MXSCR_DAZ RT_BIT(6)
2640
2641	/** Exception Mask: Invalid operation. */
2642	#define X86_MXSCR_IM RT_BIT(7)
2643	/** Exception Mask: Denormalized operand. */
2644	#define X86_MXSCR_DM RT_BIT(8)
2645	/** Exception Mask: Zero divide. */
2646	#define X86_MXSCR_ZM RT_BIT(9)
2647	/** Exception Mask: Overflow. */
2648	#define X86_MXSCR_OM RT_BIT(10)
2649	/** Exception Mask: Underflow. */
2650	#define X86_MXSCR_UM RT_BIT(11)
2651	/** Exception Mask: Precision. */
2652	#define X86_MXSCR_PM RT_BIT(12)
2653
2654	/** Rounding control mask. */
2655	#define X86_MXSCR_RC_MASK UINT16_C(0x6000)
2656	/** Rounding control: To nearest. */
2657	#define X86_MXSCR_RC_NEAREST UINT16_C(0x0000)
2658	/** Rounding control: Down. */
2659	#define X86_MXSCR_RC_DOWN UINT16_C(0x2000)
2660	/** Rounding control: Up. */
2661	#define X86_MXSCR_RC_UP UINT16_C(0x4000)
2662	/** Rounding control: Towards zero. */
2663	#define X86_MXSCR_RC_ZERO UINT16_C(0x6000)
2664
2665	/** Flush-to-zero for masked underflow. */
2666	#define X86_MXSCR_FZ RT_BIT(15)
2667
2668	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
2669	#define X86_MXSCR_MM RT_BIT(17)
2670	/** @} */
2671
2672	/**
2673	* XSAVE header.
2674	*/
2675	typedef struct X86XSAVEHDR
2676	{
2677	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
2678	uint64_t bmXState;
2679	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
2680	uint64_t bmXComp;
2681	/** Reserved for furture extensions, probably MBZ. */
2682	uint64_t au64Reserved[6];
2683	} X86XSAVEHDR;
2684	#ifndef VBOX_FOR_DTRACE_LIB
2685	AssertCompileSize(X86XSAVEHDR, 64);
2686	#endif
2687	/** Pointer to an XSAVE header. */
2688	typedef X86XSAVEHDR *PX86XSAVEHDR;
2689	/** Pointer to a const XSAVE header. */
2690	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
2691
2692
2693	/**
2694	* The high 128-bit YMM register state (XSAVE_C_YMM).
2695	* (The lower 128-bits being in X86FXSTATE.)
2696	*/
2697	typedef struct X86XSAVEYMMHI
2698	{
2699	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
2700	X86XMMREG aYmmHi[16];
2701	} X86XSAVEYMMHI;
2702	#ifndef VBOX_FOR_DTRACE_LIB
2703	AssertCompileSize(X86XSAVEYMMHI, 256);
2704	#endif
2705	/** Pointer to a high 128-bit YMM register state. */
2706	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
2707	/** Pointer to a const high 128-bit YMM register state. */
2708	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
2709
2710	/**
2711	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
2712	*/
2713	typedef struct X86XSAVEBNDREGS
2714	{
2715	/** Array of registers (BND0...BND3). */
2716	struct
2717	{
2718	/** Lower bound. */
2719	uint64_t uLowerBound;
2720	/** Upper bound. */
2721	uint64_t uUpperBound;
2722	} aRegs[4];
2723	} X86XSAVEBNDREGS;
2724	#ifndef VBOX_FOR_DTRACE_LIB
2725	AssertCompileSize(X86XSAVEBNDREGS, 64);
2726	#endif
2727	/** Pointer to a MPX bound register state. */
2728	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
2729	/** Pointer to a const MPX bound register state. */
2730	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
2731
2732	/**
2733	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
2734	*/
2735	typedef struct X86XSAVEBNDCFG
2736	{
2737	uint64_t fConfig;
2738	uint64_t fStatus;
2739	} X86XSAVEBNDCFG;
2740	#ifndef VBOX_FOR_DTRACE_LIB
2741	AssertCompileSize(X86XSAVEBNDCFG, 16);
2742	#endif
2743	/** Pointer to a MPX bound config and status register state. */
2744	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
2745	/** Pointer to a const MPX bound config and status register state. */
2746	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
2747
2748	/**
2749	* AVX-512 opmask state (XSAVE_C_OPMASK).
2750	*/
2751	typedef struct X86XSAVEOPMASK
2752	{
2753	/** The K0..K7 values. */
2754	uint64_t aKRegs[8];
2755	} X86XSAVEOPMASK;
2756	#ifndef VBOX_FOR_DTRACE_LIB
2757	AssertCompileSize(X86XSAVEOPMASK, 64);
2758	#endif
2759	/** Pointer to a AVX-512 opmask state. */
2760	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
2761	/** Pointer to a const AVX-512 opmask state. */
2762	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
2763
2764	/**
2765	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
2766	*/
2767	typedef struct X86XSAVEZMMHI256
2768	{
2769	/** Upper 256-bits of ZMM0-15. */
2770	X86YMMREG aHi256Regs[16];
2771	} X86XSAVEZMMHI256;
2772	#ifndef VBOX_FOR_DTRACE_LIB
2773	AssertCompileSize(X86XSAVEZMMHI256, 512);
2774	#endif
2775	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
2776	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
2777	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
2778	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
2779
2780	/**
2781	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
2782	*/
2783	typedef struct X86XSAVEZMM16HI
2784	{
2785	/** ZMM16 thru ZMM31. */
2786	X86ZMMREG aRegs[16];
2787	} X86XSAVEZMM16HI;
2788	#ifndef VBOX_FOR_DTRACE_LIB
2789	AssertCompileSize(X86XSAVEZMM16HI, 1024);
2790	#endif
2791	/** Pointer to a state comprising ZMM16-32. */
2792	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
2793	/** Pointer to a const state comprising ZMM16-32. */
2794	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
2795
2796	/**
2797	* AMD Light weight profiling state (XSAVE_C_LWP).
2798	*
2799	* We probably won't play with this as AMD seems to be dropping from their "zen"
2800	* processor micro architecture.
2801	*/
2802	typedef struct X86XSAVELWP
2803	{
2804	/** Details when needed. */
2805	uint64_t auLater[128/8];
2806	} X86XSAVELWP;
2807	#ifndef VBOX_FOR_DTRACE_LIB
2808	AssertCompileSize(X86XSAVELWP, 128);
2809	#endif
2810
2811
2812	/**
2813	* x86 FPU/SSE/AVX/XXXX state.
2814	*
2815	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
2816	* changes to this structure.
2817	*/
2818	typedef struct X86XSAVEAREA
2819	{
2820	/** The x87 and SSE region (or legacy region if you like). */
2821	X86FXSTATE x87;
2822	/** The XSAVE header. */
2823	X86XSAVEHDR Hdr;
2824	/** Beyond the header, there isn't really a fixed layout, but we can
2825	generally assume the YMM (AVX) register extensions are present and
2826	follows immediately. */
2827	union
2828	{
2829	/** This is a typical layout on intel CPUs (good for debuggers). */
2830	struct
2831	{
2832	X86XSAVEYMMHI YmmHi;
2833	X86XSAVEBNDREGS BndRegs;
2834	X86XSAVEBNDCFG BndCfg;
2835	uint8_t abFudgeToMatchDocs[0xB0];
2836	X86XSAVEOPMASK Opmask;
2837	X86XSAVEZMMHI256 ZmmHi256;
2838	X86XSAVEZMM16HI Zmm16Hi;
2839	} Intel;
2840
2841	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
2842	struct
2843	{
2844	X86XSAVEYMMHI YmmHi;
2845	X86XSAVELWP Lwp;
2846	} AmdBd;
2847
2848	/** To enbling static deployments that have a reasonable chance of working for
2849	* the next 3-6 CPU generations without running short on space, we allocate a
2850	* lot of extra space here, making the structure a round 8KB in size. This
2851	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
2852	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
2853	uint8_t ab[8192 - 512 - 64];
2854	} u;
2855	} X86XSAVEAREA;
2856	#ifndef VBOX_FOR_DTRACE_LIB
2857	AssertCompileSize(X86XSAVEAREA, 8192);
2858	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
2859	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
2860	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
2861	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
2862	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
2863	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
2864	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
2865	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
2866	#endif
2867	/** Pointer to a XSAVE area. */
2868	typedef X86XSAVEAREA *PX86XSAVEAREA;
2869	/** Pointer to a const XSAVE area. */
2870	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
2871
2872
2873	/** @name XSAVE_C_XXX - XSAVE State Components Bits.
2874	* @{ */
2875	/** Bit 0 - x87 - Legacy FPU state (bit number) */
2876	#define XSAVE_C_X87_BIT 0
2877	/** Bit 0 - x87 - Legacy FPU state. */
2878	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
2879	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
2880	#define XSAVE_C_SSE_BIT 1
2881	/** Bit 1 - SSE - 128-bit SSE state. */
2882	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
2883	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
2884	#define XSAVE_C_YMM_BIT 2
2885	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
2886	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
2887	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
2888	#define XSAVE_C_BNDREGS_BIT 3
2889	/** Bit 3 - BNDREGS - MPX bound register state. */
2890	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
2891	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
2892	#define XSAVE_C_BNDCSR_BIT 4
2893	/** Bit 4 - BNDCSR - MPX bound config and status state. */
2894	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
2895	/** Bit 5 - Opmask - opmask state (bit number). */
2896	#define XSAVE_C_OPMASK_BIT 5
2897	/** Bit 5 - Opmask - opmask state. */
2898	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
2899	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
2900	#define XSAVE_C_ZMM_HI256_BIT 6
2901	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
2902	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
2903	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
2904	#define XSAVE_C_ZMM_16HI_BIT 7
2905	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
2906	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
2907	/** Bit 9 - PKRU - Protection-key state (bit number). */
2908	#define XSAVE_C_PKRU_BIT 9
2909	/** Bit 9 - PKRU - Protection-key state. */
2910	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
2911	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
2912	#define XSAVE_C_LWP_BIT 62
2913	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
2914	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
2915	/** @} */
2916
2917
2918
2919	/** @name Selector Descriptor
2920	* @{
2921	*/
2922
2923	#ifndef VBOX_FOR_DTRACE_LIB
2924	/**
2925	* Descriptor attributes (as seen by VT-x).
2926	*/
2927	typedef struct X86DESCATTRBITS
2928	{
2929	/** 00 - Segment Type. */
2930	unsigned u4Type : 4;
2931	/** 04 - Descriptor Type. System(=0) or code/data selector */
2932	unsigned u1DescType : 1;
2933	/** 05 - Descriptor Privilege level. */
2934	unsigned u2Dpl : 2;
2935	/** 07 - Flags selector present(=1) or not. */
2936	unsigned u1Present : 1;
2937	/** 08 - Segment limit 16-19. */
2938	unsigned u4LimitHigh : 4;
2939	/** 0c - Available for system software. */
2940	unsigned u1Available : 1;
2941	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2942	unsigned u1Long : 1;
2943	/** 0e - This flags meaning depends on the segment type. Try make sense out
2944	* of the intel manual yourself. */
2945	unsigned u1DefBig : 1;
2946	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2947	* clear byte. */
2948	unsigned u1Granularity : 1;
2949	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
2950	unsigned u1Unusable : 1;
2951	} X86DESCATTRBITS;
2952	#endif /* !VBOX_FOR_DTRACE_LIB */
2953
2954	/** @name X86DESCATTR masks
2955	* @{ */
2956	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
2957	#define X86DESCATTR_DT UINT32_C(0x00000010)
2958	#define X86DESCATTR_DPL UINT32_C(0x00000060)
2959	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
2960	#define X86DESCATTR_P UINT32_C(0x00000080)
2961	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
2962	#define X86DESCATTR_AVL UINT32_C(0x00001000)
2963	#define X86DESCATTR_L UINT32_C(0x00002000)
2964	#define X86DESCATTR_D UINT32_C(0x00004000)
2965	#define X86DESCATTR_G UINT32_C(0x00008000)
2966	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
2967	/** @} */
2968
2969	#pragma pack(1)
2970	typedef union X86DESCATTR
2971	{
2972	/** Unsigned integer view. */
2973	uint32_t u;
2974	#ifndef VBOX_FOR_DTRACE_LIB
2975	/** Normal view. */
2976	X86DESCATTRBITS n;
2977	#endif
2978	} X86DESCATTR;
2979	#pragma pack()
2980	/** Pointer to descriptor attributes. */
2981	typedef X86DESCATTR *PX86DESCATTR;
2982	/** Pointer to const descriptor attributes. */
2983	typedef const X86DESCATTR *PCX86DESCATTR;
2984
2985	#ifndef VBOX_FOR_DTRACE_LIB
2986
2987	/**
2988	* Generic descriptor table entry
2989	*/
2990	#pragma pack(1)
2991	typedef struct X86DESCGENERIC
2992	{
2993	/** 00 - Limit - Low word. */
2994	unsigned u16LimitLow : 16;
2995	/** 10 - Base address - lowe word.
2996	* Don't try set this to 24 because MSC is doing stupid things then. */
2997	unsigned u16BaseLow : 16;
2998	/** 20 - Base address - first 8 bits of high word. */
2999	unsigned u8BaseHigh1 : 8;
3000	/** 28 - Segment Type. */
3001	unsigned u4Type : 4;
3002	/** 2c - Descriptor Type. System(=0) or code/data selector */
3003	unsigned u1DescType : 1;
3004	/** 2d - Descriptor Privilege level. */
3005	unsigned u2Dpl : 2;
3006	/** 2f - Flags selector present(=1) or not. */
3007	unsigned u1Present : 1;
3008	/** 30 - Segment limit 16-19. */
3009	unsigned u4LimitHigh : 4;
3010	/** 34 - Available for system software. */
3011	unsigned u1Available : 1;
3012	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3013	unsigned u1Long : 1;
3014	/** 36 - This flags meaning depends on the segment type. Try make sense out
3015	* of the intel manual yourself. */
3016	unsigned u1DefBig : 1;
3017	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
3018	* clear byte. */
3019	unsigned u1Granularity : 1;
3020	/** 38 - Base address - highest 8 bits. */
3021	unsigned u8BaseHigh2 : 8;
3022	} X86DESCGENERIC;
3023	#pragma pack()
3024	/** Pointer to a generic descriptor entry. */
3025	typedef X86DESCGENERIC *PX86DESCGENERIC;
3026	/** Pointer to a const generic descriptor entry. */
3027	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3028
3029	/** @name Bit offsets of X86DESCGENERIC members.
3030	* @{*/
3031	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
3032	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
3033	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
3034	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
3035	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
3036	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
3037	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
3038	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
3039	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
3040	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
3041	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
3042	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
3043	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
3044	/** @} */
3045
3046	/**
3047	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3048	*/
3049	typedef struct X86DESCGATE
3050	{
3051	/** 00 - Target code segment offset - Low word.
3052	* Ignored if task-gate. */
3053	unsigned u16OffsetLow : 16;
3054	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3055	* TSS selector if task-gate. */
3056	unsigned u16Sel : 16;
3057	/** 20 - Number of parameters for a call-gate.
3058	* Ignored if interrupt-, trap- or task-gate. */
3059	unsigned u4ParmCount : 4;
3060	/** 24 - Reserved / ignored. */
3061	unsigned u4Reserved : 4;
3062	/** 28 - Segment Type. */
3063	unsigned u4Type : 4;
3064	/** 2c - Descriptor Type (0 = system). */
3065	unsigned u1DescType : 1;
3066	/** 2d - Descriptor Privilege level. */
3067	unsigned u2Dpl : 2;
3068	/** 2f - Flags selector present(=1) or not. */
3069	unsigned u1Present : 1;
3070	/** 30 - Target code segment offset - High word.
3071	* Ignored if task-gate. */
3072	unsigned u16OffsetHigh : 16;
3073	} X86DESCGATE;
3074	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3075	typedef X86DESCGATE *PX86DESCGATE;
3076	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3077	typedef const X86DESCGATE *PCX86DESCGATE;
3078
3079	#endif /* VBOX_FOR_DTRACE_LIB */
3080
3081	/**
3082	* Descriptor table entry.
3083	*/
3084	#pragma pack(1)
3085	typedef union X86DESC
3086	{
3087	#ifndef VBOX_FOR_DTRACE_LIB
3088	/** Generic descriptor view. */
3089	X86DESCGENERIC Gen;
3090	/** Gate descriptor view. */
3091	X86DESCGATE Gate;
3092	#endif
3093
3094	/** 8 bit unsigned integer view. */
3095	uint8_t au8[8];
3096	/** 16 bit unsigned integer view. */
3097	uint16_t au16[4];
3098	/** 32 bit unsigned integer view. */
3099	uint32_t au32[2];
3100	/** 64 bit unsigned integer view. */
3101	uint64_t au64[1];
3102	/** Unsigned integer view. */
3103	uint64_t u;
3104	} X86DESC;
3105	#ifndef VBOX_FOR_DTRACE_LIB
3106	AssertCompileSize(X86DESC, 8);
3107	#endif
3108	#pragma pack()
3109	/** Pointer to descriptor table entry. */
3110	typedef X86DESC *PX86DESC;
3111	/** Pointer to const descriptor table entry. */
3112	typedef const X86DESC *PCX86DESC;
3113
3114	/** @def X86DESC_BASE
3115	* Return the base address of a descriptor.
3116	*/
3117	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
3118	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3119	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3120	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3121
3122	/** @def X86DESC_LIMIT
3123	* Return the limit of a descriptor.
3124	*/
3125	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
3126	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3127	\| ( (a_pDesc)->Gen.u16LimitLow ) )
3128
3129	/** @def X86DESC_LIMIT_G
3130	* Return the limit of a descriptor with the granularity bit taken into account.
3131	* @returns Selector limit (uint32_t).
3132	* @param a_pDesc Pointer to the descriptor.
3133	*/
3134	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
3135	( (a_pDesc)->Gen.u1Granularity \
3136	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
3137	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
3138	)
3139
3140	/** @def X86DESC_GET_HID_ATTR
3141	* Get the descriptor attributes for the hidden register.
3142	*/
3143	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
3144	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3145
3146	#ifndef VBOX_FOR_DTRACE_LIB
3147
3148	/**
3149	* 64 bits generic descriptor table entry
3150	* Note: most of these bits have no meaning in long mode.
3151	*/
3152	#pragma pack(1)
3153	typedef struct X86DESC64GENERIC
3154	{
3155	/** Limit - Low word - IGNORED. */
3156	uint32_t u16LimitLow : 16;
3157	/** Base address - low word. - IGNORED
3158	* Don't try set this to 24 because MSC is doing stupid things then. */
3159	uint32_t u16BaseLow : 16;
3160	/** Base address - first 8 bits of high word. - IGNORED */
3161	uint32_t u8BaseHigh1 : 8;
3162	/** Segment Type. */
3163	uint32_t u4Type : 4;
3164	/** Descriptor Type. System(=0) or code/data selector */
3165	uint32_t u1DescType : 1;
3166	/** Descriptor Privilege level. */
3167	uint32_t u2Dpl : 2;
3168	/** Flags selector present(=1) or not. */
3169	uint32_t u1Present : 1;
3170	/** Segment limit 16-19. - IGNORED */
3171	uint32_t u4LimitHigh : 4;
3172	/** Available for system software. - IGNORED */
3173	uint32_t u1Available : 1;
3174	/** Long mode flag. */
3175	uint32_t u1Long : 1;
3176	/** This flags meaning depends on the segment type. Try make sense out
3177	* of the intel manual yourself. */
3178	uint32_t u1DefBig : 1;
3179	/** Granularity of the limit. If set 4KB granularity is used, if
3180	* clear byte. - IGNORED */
3181	uint32_t u1Granularity : 1;
3182	/** Base address - highest 8 bits. - IGNORED */
3183	uint32_t u8BaseHigh2 : 8;
3184	/** Base address - bits 63-32. */
3185	uint32_t u32BaseHigh3 : 32;
3186	uint32_t u8Reserved : 8;
3187	uint32_t u5Zeros : 5;
3188	uint32_t u19Reserved : 19;
3189	} X86DESC64GENERIC;
3190	#pragma pack()
3191	/** Pointer to a generic descriptor entry. */
3192	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3193	/** Pointer to a const generic descriptor entry. */
3194	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3195
3196	/**
3197	* System descriptor table entry (64 bits)
3198	*
3199	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3200	*/
3201	#pragma pack(1)
3202	typedef struct X86DESC64SYSTEM
3203	{
3204	/** Limit - Low word. */
3205	uint32_t u16LimitLow : 16;
3206	/** Base address - lowe word.
3207	* Don't try set this to 24 because MSC is doing stupid things then. */
3208	uint32_t u16BaseLow : 16;
3209	/** Base address - first 8 bits of high word. */
3210	uint32_t u8BaseHigh1 : 8;
3211	/** Segment Type. */
3212	uint32_t u4Type : 4;
3213	/** Descriptor Type. System(=0) or code/data selector */
3214	uint32_t u1DescType : 1;
3215	/** Descriptor Privilege level. */
3216	uint32_t u2Dpl : 2;
3217	/** Flags selector present(=1) or not. */
3218	uint32_t u1Present : 1;
3219	/** Segment limit 16-19. */
3220	uint32_t u4LimitHigh : 4;
3221	/** Available for system software. */
3222	uint32_t u1Available : 1;
3223	/** Reserved - 0. */
3224	uint32_t u1Reserved : 1;
3225	/** This flags meaning depends on the segment type. Try make sense out
3226	* of the intel manual yourself. */
3227	uint32_t u1DefBig : 1;
3228	/** Granularity of the limit. If set 4KB granularity is used, if
3229	* clear byte. */
3230	uint32_t u1Granularity : 1;
3231	/** Base address - bits 31-24. */
3232	uint32_t u8BaseHigh2 : 8;
3233	/** Base address - bits 63-32. */
3234	uint32_t u32BaseHigh3 : 32;
3235	uint32_t u8Reserved : 8;
3236	uint32_t u5Zeros : 5;
3237	uint32_t u19Reserved : 19;
3238	} X86DESC64SYSTEM;
3239	#pragma pack()
3240	/** Pointer to a system descriptor entry. */
3241	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3242	/** Pointer to a const system descriptor entry. */
3243	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3244
3245	/**
3246	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3247	*/
3248	typedef struct X86DESC64GATE
3249	{
3250	/** Target code segment offset - Low word. */
3251	uint32_t u16OffsetLow : 16;
3252	/** Target code segment selector. */
3253	uint32_t u16Sel : 16;
3254	/** Interrupt stack table for interrupt- and trap-gates.
3255	* Ignored by call-gates. */
3256	uint32_t u3IST : 3;
3257	/** Reserved / ignored. */
3258	uint32_t u5Reserved : 5;
3259	/** Segment Type. */
3260	uint32_t u4Type : 4;
3261	/** Descriptor Type (0 = system). */
3262	uint32_t u1DescType : 1;
3263	/** Descriptor Privilege level. */
3264	uint32_t u2Dpl : 2;
3265	/** Flags selector present(=1) or not. */
3266	uint32_t u1Present : 1;
3267	/** Target code segment offset - High word.
3268	* Ignored if task-gate. */
3269	uint32_t u16OffsetHigh : 16;
3270	/** Target code segment offset - Top dword.
3271	* Ignored if task-gate. */
3272	uint32_t u32OffsetTop : 32;
3273	/** Reserved / ignored / must be zero.
3274	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3275	uint32_t u32Reserved : 32;
3276	} X86DESC64GATE;
3277	AssertCompileSize(X86DESC64GATE, 16);
3278	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3279	typedef X86DESC64GATE *PX86DESC64GATE;
3280	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3281	typedef const X86DESC64GATE *PCX86DESC64GATE;
3282
3283	#endif /* VBOX_FOR_DTRACE_LIB */
3284
3285	/**
3286	* Descriptor table entry.
3287	*/
3288	#pragma pack(1)
3289	typedef union X86DESC64
3290	{
3291	#ifndef VBOX_FOR_DTRACE_LIB
3292	/** Generic descriptor view. */
3293	X86DESC64GENERIC Gen;
3294	/** System descriptor view. */
3295	X86DESC64SYSTEM System;
3296	/** Gate descriptor view. */
3297	X86DESC64GATE Gate;
3298	#endif
3299
3300	/** 8 bit unsigned integer view. */
3301	uint8_t au8[16];
3302	/** 16 bit unsigned integer view. */
3303	uint16_t au16[8];
3304	/** 32 bit unsigned integer view. */
3305	uint32_t au32[4];
3306	/** 64 bit unsigned integer view. */
3307	uint64_t au64[2];
3308	} X86DESC64;
3309	#ifndef VBOX_FOR_DTRACE_LIB
3310	AssertCompileSize(X86DESC64, 16);
3311	#endif
3312	#pragma pack()
3313	/** Pointer to descriptor table entry. */
3314	typedef X86DESC64 *PX86DESC64;
3315	/** Pointer to const descriptor table entry. */
3316	typedef const X86DESC64 *PCX86DESC64;
3317
3318	/** @def X86DESC64_BASE
3319	* Return the base of a 64-bit descriptor.
3320	*/
3321	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
3322	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3323	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3324	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3325	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3326
3327
3328
3329	/** @name Host system descriptor table entry - Use with care!
3330	* @{ */
3331	/** Host system descriptor table entry. */
3332	#if HC_ARCH_BITS == 64
3333	typedef X86DESC64 X86DESCHC;
3334	#else
3335	typedef X86DESC X86DESCHC;
3336	#endif
3337	/** Pointer to a host system descriptor table entry. */
3338	#if HC_ARCH_BITS == 64
3339	typedef PX86DESC64 PX86DESCHC;
3340	#else
3341	typedef PX86DESC PX86DESCHC;
3342	#endif
3343	/** Pointer to a const host system descriptor table entry. */
3344	#if HC_ARCH_BITS == 64
3345	typedef PCX86DESC64 PCX86DESCHC;
3346	#else
3347	typedef PCX86DESC PCX86DESCHC;
3348	#endif
3349	/** @} */
3350
3351
3352	/** @name Selector Descriptor Types.
3353	* @{
3354	*/
3355
3356	/** @name Non-System Selector Types.
3357	* @{ */
3358	/** Code(=set)/Data(=clear) bit. */
3359	#define X86_SEL_TYPE_CODE 8
3360	/** Memory(=set)/System(=clear) bit. */
3361	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
3362	/** Accessed bit. */
3363	#define X86_SEL_TYPE_ACCESSED 1
3364	/** Expand down bit (for data selectors only). */
3365	#define X86_SEL_TYPE_DOWN 4
3366	/** Conforming bit (for code selectors only). */
3367	#define X86_SEL_TYPE_CONF 4
3368	/** Write bit (for data selectors only). */
3369	#define X86_SEL_TYPE_WRITE 2
3370	/** Read bit (for code selectors only). */
3371	#define X86_SEL_TYPE_READ 2
3372	/** The bit number of the code segment read bit (relative to u4Type). */
3373	#define X86_SEL_TYPE_READ_BIT 1
3374
3375	/** Read only selector type. */
3376	#define X86_SEL_TYPE_RO 0
3377	/** Accessed read only selector type. */
3378	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
3379	/** Read write selector type. */
3380	#define X86_SEL_TYPE_RW 2
3381	/** Accessed read write selector type. */
3382	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
3383	/** Expand down read only selector type. */
3384	#define X86_SEL_TYPE_RO_DOWN 4
3385	/** Accessed expand down read only selector type. */
3386	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
3387	/** Expand down read write selector type. */
3388	#define X86_SEL_TYPE_RW_DOWN 6
3389	/** Accessed expand down read write selector type. */
3390	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
3391	/** Execute only selector type. */
3392	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
3393	/** Accessed execute only selector type. */
3394	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3395	/** Execute and read selector type. */
3396	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
3397	/** Accessed execute and read selector type. */
3398	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3399	/** Conforming execute only selector type. */
3400	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
3401	/** Accessed Conforming execute only selector type. */
3402	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3403	/** Conforming execute and write selector type. */
3404	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
3405	/** Accessed Conforming execute and write selector type. */
3406	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
3407	/** @} */
3408
3409
3410	/** @name System Selector Types.
3411	* @{ */
3412	/** The TSS busy bit mask. */
3413	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3414
3415	/** Undefined system selector type. */
3416	#define X86_SEL_TYPE_SYS_UNDEFINED 0
3417	/** 286 TSS selector. */
3418	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3419	/** LDT selector. */
3420	#define X86_SEL_TYPE_SYS_LDT 2
3421	/** 286 TSS selector - Busy. */
3422	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3423	/** 286 Callgate selector. */
3424	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3425	/** Taskgate selector. */
3426	#define X86_SEL_TYPE_SYS_TASK_GATE 5
3427	/** 286 Interrupt gate selector. */
3428	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3429	/** 286 Trapgate selector. */
3430	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3431	/** Undefined system selector. */
3432	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3433	/** 386 TSS selector. */
3434	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3435	/** Undefined system selector. */
3436	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3437	/** 386 TSS selector - Busy. */
3438	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3439	/** 386 Callgate selector. */
3440	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3441	/** Undefined system selector. */
3442	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3443	/** 386 Interruptgate selector. */
3444	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3445	/** 386 Trapgate selector. */
3446	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3447	/** @} */
3448
3449	/** @name AMD64 System Selector Types.
3450	* @{ */
3451	/** LDT selector. */
3452	#define AMD64_SEL_TYPE_SYS_LDT 2
3453	/** TSS selector - Busy. */
3454	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3455	/** TSS selector - Busy. */
3456	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3457	/** Callgate selector. */
3458	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3459	/** Interruptgate selector. */
3460	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3461	/** Trapgate selector. */
3462	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3463	/** @} */
3464
3465	/** @} */
3466
3467
3468	/** @name Descriptor Table Entry Flag Masks.
3469	* These are for the 2nd 32-bit word of a descriptor.
3470	* @{ */
3471	/** Bits 8-11 - TYPE - Descriptor type mask. */
3472	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
3473	/** Bit 12 - S - System (=0) or Code/Data (=1). */
3474	#define X86_DESC_S RT_BIT(12)
3475	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3476	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
3477	/** Bit 15 - P - Present. */
3478	#define X86_DESC_P RT_BIT(15)
3479	/** Bit 20 - AVL - Available for system software. */
3480	#define X86_DESC_AVL RT_BIT(20)
3481	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3482	#define X86_DESC_DB RT_BIT(22)
3483	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3484	* used, if clear byte. */
3485	#define X86_DESC_G RT_BIT(23)
3486	/** @} */
3487
3488	/** @} */
3489
3490
3491	/** @name Task Segments.
3492	* @{
3493	*/
3494
3495	/**
3496	* The minimum TSS descriptor limit for 286 tasks.
3497	*/
3498	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3499
3500	/**
3501	* The minimum TSS descriptor segment limit for 386 tasks.
3502	*/
3503	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3504
3505	/**
3506	* 16-bit Task Segment (TSS).
3507	*/
3508	#pragma pack(1)
3509	typedef struct X86TSS16
3510	{
3511	/** Back link to previous task. (static) */
3512	RTSEL selPrev;
3513	/** Ring-0 stack pointer. (static) */
3514	uint16_t sp0;
3515	/** Ring-0 stack segment. (static) */
3516	RTSEL ss0;
3517	/** Ring-1 stack pointer. (static) */
3518	uint16_t sp1;
3519	/** Ring-1 stack segment. (static) */
3520	RTSEL ss1;
3521	/** Ring-2 stack pointer. (static) */
3522	uint16_t sp2;
3523	/** Ring-2 stack segment. (static) */
3524	RTSEL ss2;
3525	/** IP before task switch. */
3526	uint16_t ip;
3527	/** FLAGS before task switch. */
3528	uint16_t flags;
3529	/** AX before task switch. */
3530	uint16_t ax;
3531	/** CX before task switch. */
3532	uint16_t cx;
3533	/** DX before task switch. */
3534	uint16_t dx;
3535	/** BX before task switch. */
3536	uint16_t bx;
3537	/** SP before task switch. */
3538	uint16_t sp;
3539	/** BP before task switch. */
3540	uint16_t bp;
3541	/** SI before task switch. */
3542	uint16_t si;
3543	/** DI before task switch. */
3544	uint16_t di;
3545	/** ES before task switch. */
3546	RTSEL es;
3547	/** CS before task switch. */
3548	RTSEL cs;
3549	/** SS before task switch. */
3550	RTSEL ss;
3551	/** DS before task switch. */
3552	RTSEL ds;
3553	/** LDTR before task switch. */
3554	RTSEL selLdt;
3555	} X86TSS16;
3556	#ifndef VBOX_FOR_DTRACE_LIB
3557	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
3558	#endif
3559	#pragma pack()
3560	/** Pointer to a 16-bit task segment. */
3561	typedef X86TSS16 *PX86TSS16;
3562	/** Pointer to a const 16-bit task segment. */
3563	typedef const X86TSS16 *PCX86TSS16;
3564
3565
3566	/**
3567	* 32-bit Task Segment (TSS).
3568	*/
3569	#pragma pack(1)
3570	typedef struct X86TSS32
3571	{
3572	/** Back link to previous task. (static) */
3573	RTSEL selPrev;
3574	uint16_t padding1;
3575	/** Ring-0 stack pointer. (static) */
3576	uint32_t esp0;
3577	/** Ring-0 stack segment. (static) */
3578	RTSEL ss0;
3579	uint16_t padding_ss0;
3580	/** Ring-1 stack pointer. (static) */
3581	uint32_t esp1;
3582	/** Ring-1 stack segment. (static) */
3583	RTSEL ss1;
3584	uint16_t padding_ss1;
3585	/** Ring-2 stack pointer. (static) */
3586	uint32_t esp2;
3587	/** Ring-2 stack segment. (static) */
3588	RTSEL ss2;
3589	uint16_t padding_ss2;
3590	/** Page directory for the task. (static) */
3591	uint32_t cr3;
3592	/** EIP before task switch. */
3593	uint32_t eip;
3594	/** EFLAGS before task switch. */
3595	uint32_t eflags;
3596	/** EAX before task switch. */
3597	uint32_t eax;
3598	/** ECX before task switch. */
3599	uint32_t ecx;
3600	/** EDX before task switch. */
3601	uint32_t edx;
3602	/** EBX before task switch. */
3603	uint32_t ebx;
3604	/** ESP before task switch. */
3605	uint32_t esp;
3606	/** EBP before task switch. */
3607	uint32_t ebp;
3608	/** ESI before task switch. */
3609	uint32_t esi;
3610	/** EDI before task switch. */
3611	uint32_t edi;
3612	/** ES before task switch. */
3613	RTSEL es;
3614	uint16_t padding_es;
3615	/** CS before task switch. */
3616	RTSEL cs;
3617	uint16_t padding_cs;
3618	/** SS before task switch. */
3619	RTSEL ss;
3620	uint16_t padding_ss;
3621	/** DS before task switch. */
3622	RTSEL ds;
3623	uint16_t padding_ds;
3624	/** FS before task switch. */
3625	RTSEL fs;
3626	uint16_t padding_fs;
3627	/** GS before task switch. */
3628	RTSEL gs;
3629	uint16_t padding_gs;
3630	/** LDTR before task switch. */
3631	RTSEL selLdt;
3632	uint16_t padding_ldt;
3633	/** Debug trap flag */
3634	uint16_t fDebugTrap;
3635	/** Offset relative to the TSS of the start of the I/O Bitmap
3636	* and the end of the interrupt redirection bitmap. */
3637	uint16_t offIoBitmap;
3638	} X86TSS32;
3639	#pragma pack()
3640	/** Pointer to task segment. */
3641	typedef X86TSS32 *PX86TSS32;
3642	/** Pointer to const task segment. */
3643	typedef const X86TSS32 *PCX86TSS32;
3644	#ifndef VBOX_FOR_DTRACE_LIB
3645	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
3646	AssertCompileMemberOffset(X86TSS32, cr3, 28);
3647	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
3648	#endif
3649
3650	/**
3651	* 64-bit Task segment.
3652	*/
3653	#pragma pack(1)
3654	typedef struct X86TSS64
3655	{
3656	/** Reserved. */
3657	uint32_t u32Reserved;
3658	/** Ring-0 stack pointer. (static) */
3659	uint64_t rsp0;
3660	/** Ring-1 stack pointer. (static) */
3661	uint64_t rsp1;
3662	/** Ring-2 stack pointer. (static) */
3663	uint64_t rsp2;
3664	/** Reserved. */
3665	uint32_t u32Reserved2[2];
3666	/* IST */
3667	uint64_t ist1;
3668	uint64_t ist2;
3669	uint64_t ist3;
3670	uint64_t ist4;
3671	uint64_t ist5;
3672	uint64_t ist6;
3673	uint64_t ist7;
3674	/* Reserved. */
3675	uint16_t u16Reserved[5];
3676	/** Offset relative to the TSS of the start of the I/O Bitmap
3677	* and the end of the interrupt redirection bitmap. */
3678	uint16_t offIoBitmap;
3679	} X86TSS64;
3680	#pragma pack()
3681	/** Pointer to a 64-bit task segment. */
3682	typedef X86TSS64 *PX86TSS64;
3683	/** Pointer to a const 64-bit task segment. */
3684	typedef const X86TSS64 *PCX86TSS64;
3685	#ifndef VBOX_FOR_DTRACE_LIB
3686	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
3687	#endif
3688
3689	/** @} */
3690
3691
3692	/** @name Selectors.
3693	* @{
3694	*/
3695
3696	/**
3697	* The shift used to convert a selector from and to index an index (C).
3698	*/
3699	#define X86_SEL_SHIFT 3
3700
3701	/**
3702	* The mask used to mask off the table indicator and RPL of an selector.
3703	*/
3704	#define X86_SEL_MASK 0xfff8U
3705
3706	/**
3707	* The mask used to mask off the RPL of an selector.
3708	* This is suitable for checking for NULL selectors.
3709	*/
3710	#define X86_SEL_MASK_OFF_RPL 0xfffcU
3711
3712	/**
3713	* The bit indicating that a selector is in the LDT and not in the GDT.
3714	*/
3715	#define X86_SEL_LDT 0x0004U
3716
3717	/**
3718	* The bit mask for getting the RPL of a selector.
3719	*/
3720	#define X86_SEL_RPL 0x0003U
3721
3722	/**
3723	* The mask covering both RPL and LDT.
3724	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
3725	* checks.
3726	*/
3727	#define X86_SEL_RPL_LDT 0x0007U
3728
3729	/** @} */
3730
3731
3732	/**
3733	* x86 Exceptions/Faults/Traps.
3734	*/
3735	typedef enum X86XCPT
3736	{
3737	/** \#DE - Divide error. */
3738	X86_XCPT_DE = 0x00,
3739	/** \#DB - Debug event (single step, DRx, ..) */
3740	X86_XCPT_DB = 0x01,
3741	/** NMI - Non-Maskable Interrupt */
3742	X86_XCPT_NMI = 0x02,
3743	/** \#BP - Breakpoint (INT3). */
3744	X86_XCPT_BP = 0x03,
3745	/** \#OF - Overflow (INTO). */
3746	X86_XCPT_OF = 0x04,
3747	/** \#BR - Bound range exceeded (BOUND). */
3748	X86_XCPT_BR = 0x05,
3749	/** \#UD - Undefined opcode. */
3750	X86_XCPT_UD = 0x06,
3751	/** \#NM - Device not available (math coprocessor device). */
3752	X86_XCPT_NM = 0x07,
3753	/** \#DF - Double fault. */
3754	X86_XCPT_DF = 0x08,
3755	/** ??? - Coprocessor segment overrun (obsolete). */
3756	X86_XCPT_CO_SEG_OVERRUN = 0x09,
3757	/** \#TS - Taskswitch (TSS). */
3758	X86_XCPT_TS = 0x0a,
3759	/** \#NP - Segment no present. */
3760	X86_XCPT_NP = 0x0b,
3761	/** \#SS - Stack segment fault. */
3762	X86_XCPT_SS = 0x0c,
3763	/** \#GP - General protection fault. */
3764	X86_XCPT_GP = 0x0d,
3765	/** \#PF - Page fault. */
3766	X86_XCPT_PF = 0x0e,
3767	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
3768	/** \#MF - Math fault (FPU). */
3769	X86_XCPT_MF = 0x10,
3770	/** \#AC - Alignment check. */
3771	X86_XCPT_AC = 0x11,
3772	/** \#MC - Machine check. */
3773	X86_XCPT_MC = 0x12,
3774	/** \#XF - SIMD Floating-Pointer Exception. */
3775	X86_XCPT_XF = 0x13,
3776	/** \#VE - Virtualization Exception. */
3777	X86_XCPT_VE = 0x14,
3778	/** \#SX - Security Exception. */
3779	X86_XCPT_SX = 0x1f
3780	} X86XCPT;
3781	/** Pointer to a x86 exception code. */
3782	typedef X86XCPT *PX86XCPT;
3783	/** Pointer to a const x86 exception code. */
3784	typedef const X86XCPT *PCX86XCPT;
3785	/** The maximum exception value. */
3786	#define X86_XCPT_MAX (X86_XCPT_SX)
3787
3788
3789	/** @name Trap Error Codes
3790	* @{
3791	*/
3792	/** External indicator. */
3793	#define X86_TRAP_ERR_EXTERNAL 1
3794	/** IDT indicator. */
3795	#define X86_TRAP_ERR_IDT 2
3796	/** Descriptor table indicator - If set LDT, if clear GDT. */
3797	#define X86_TRAP_ERR_TI 4
3798	/** Mask for getting the selector. */
3799	#define X86_TRAP_ERR_SEL_MASK 0xfff8
3800	/** Shift for getting the selector table index (C type index). */
3801	#define X86_TRAP_ERR_SEL_SHIFT 3
3802	/** @} */
3803
3804
3805	/** @name \#PF Trap Error Codes
3806	* @{
3807	*/
3808	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3809	#define X86_TRAP_PF_P RT_BIT(0)
3810	/** Bit 1 - R/W - Read (clear) or write (set) access. */
3811	#define X86_TRAP_PF_RW RT_BIT(1)
3812	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3813	#define X86_TRAP_PF_US RT_BIT(2)
3814	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3815	#define X86_TRAP_PF_RSVD RT_BIT(3)
3816	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3817	#define X86_TRAP_PF_ID RT_BIT(4)
3818	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
3819	#define X86_TRAP_PF_PK RT_BIT(5)
3820	/** @} */
3821
3822	#pragma pack(1)
3823	/**
3824	* 16-bit IDTR.
3825	*/
3826	typedef struct X86IDTR16
3827	{
3828	/** Offset. */
3829	uint16_t offSel;
3830	/** Selector. */
3831	uint16_t uSel;
3832	} X86IDTR16, *PX86IDTR16;
3833	#pragma pack()
3834
3835	#pragma pack(1)
3836	/**
3837	* 32-bit IDTR/GDTR.
3838	*/
3839	typedef struct X86XDTR32
3840	{
3841	/** Size of the descriptor table. */
3842	uint16_t cb;
3843	/** Address of the descriptor table. */
3844	#ifndef VBOX_FOR_DTRACE_LIB
3845	uint32_t uAddr;
3846	#else
3847	uint16_t au16Addr[2];
3848	#endif
3849	} X86XDTR32, *PX86XDTR32;
3850	#pragma pack()
3851
3852	#pragma pack(1)
3853	/**
3854	* 64-bit IDTR/GDTR.
3855	*/
3856	typedef struct X86XDTR64
3857	{
3858	/** Size of the descriptor table. */
3859	uint16_t cb;
3860	/** Address of the descriptor table. */
3861	#ifndef VBOX_FOR_DTRACE_LIB
3862	uint64_t uAddr;
3863	#else
3864	uint16_t au16Addr[4];
3865	#endif
3866	} X86XDTR64, *PX86XDTR64;
3867	#pragma pack()
3868
3869
3870	/** @name ModR/M
3871	* @{ */
3872	#define X86_MODRM_RM_MASK UINT8_C(0x07)
3873	#define X86_MODRM_REG_MASK UINT8_C(0x38)
3874	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3875	#define X86_MODRM_REG_SHIFT 3
3876	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3877	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3878	#define X86_MODRM_MOD_SHIFT 6
3879	#ifndef VBOX_FOR_DTRACE_LIB
3880	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
3881	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3882	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3883	#endif
3884	/** @} */
3885
3886	/** @name SIB
3887	* @{ */
3888	#define X86_SIB_BASE_MASK UINT8_C(0x07)
3889	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3890	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3891	#define X86_SIB_INDEX_SHIFT 3
3892	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3893	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3894	#define X86_SIB_SCALE_SHIFT 6
3895	#ifndef VBOX_FOR_DTRACE_LIB
3896	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
3897	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3898	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3899	#endif
3900	/** @} */
3901
3902	/** @name General register indexes
3903	* @{ */
3904	#define X86_GREG_xAX 0
3905	#define X86_GREG_xCX 1
3906	#define X86_GREG_xDX 2
3907	#define X86_GREG_xBX 3
3908	#define X86_GREG_xSP 4
3909	#define X86_GREG_xBP 5
3910	#define X86_GREG_xSI 6
3911	#define X86_GREG_xDI 7
3912	#define X86_GREG_x8 8
3913	#define X86_GREG_x9 9
3914	#define X86_GREG_x10 10
3915	#define X86_GREG_x11 11
3916	#define X86_GREG_x12 12
3917	#define X86_GREG_x13 13
3918	#define X86_GREG_x14 14
3919	#define X86_GREG_x15 15
3920	/** @} */
3921
3922	/** @name X86_SREG_XXX - Segment register indexes.
3923	* @{ */
3924	#define X86_SREG_ES 0
3925	#define X86_SREG_CS 1
3926	#define X86_SREG_SS 2
3927	#define X86_SREG_DS 3
3928	#define X86_SREG_FS 4
3929	#define X86_SREG_GS 5
3930	/** @} */
3931	/** Segment register count. */
3932	#define X86_SREG_COUNT 6
3933
3934
3935	/** @name X86_OP_XXX - Prefixes
3936	* @{ */
3937	#define X86_OP_PRF_CS UINT8_C(0x2e)
3938	#define X86_OP_PRF_SS UINT8_C(0x36)
3939	#define X86_OP_PRF_DS UINT8_C(0x3e)
3940	#define X86_OP_PRF_ES UINT8_C(0x26)
3941	#define X86_OP_PRF_FS UINT8_C(0x64)
3942	#define X86_OP_PRF_GS UINT8_C(0x65)
3943	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
3944	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
3945	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
3946	#define X86_OP_PRF_REPZ UINT8_C(0xf2)
3947	#define X86_OP_PRF_REPNZ UINT8_C(0xf3)
3948	#define X86_OP_REX_B UINT8_C(0x41)
3949	#define X86_OP_REX_X UINT8_C(0x42)
3950	#define X86_OP_REX_R UINT8_C(0x44)
3951	#define X86_OP_REX_W UINT8_C(0x48)
3952	/** @} */
3953
3954
3955	/** @} */
3956
3957	#endif
3958

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source: vbox/trunk/include/iprt/x86.h@ 59285

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