x86.h@ 47356

Last change on this file since 47356 was 47328, checked in by vboxsync, 11 years ago
CPUM,++: Fix DR6 and DR7 read-as-1 (RA1) and read-as-zero (RAZ) values on load since REM didn't set them right for years. Introduced constants for these values.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 116.0 KB

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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2012 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#ifndef VBOX_FOR_DTRACE_LIB
32	# include <iprt/types.h>
33	# include <iprt/assert.h>
34	#else
35	# pragma D depends_on library vbox-types.d
36	#endif
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_rt_x86 x86 Types and Definitions
45	* @ingroup grp_rt
46	* @{
47	*/
48
49	#ifndef VBOX_FOR_DTRACE_LIB
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104	#endif /* !VBOX_FOR_DTRACE_LIB */
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	#ifndef VBOX_FOR_DTRACE_LIB
114	/** The bitfield view. */
115	X86EFLAGSBITS Bits;
116	#endif
117	/** The 8-bit view. */
118	uint8_t au8[4];
119	/** The 16-bit view. */
120	uint16_t au16[2];
121	/** The 32-bit view. */
122	uint32_t au32[1];
123	/** The 32-bit view. */
124	uint32_t u32;
125	} X86EFLAGS;
126	/** Pointer to EFLAGS. */
127	typedef X86EFLAGS *PX86EFLAGS;
128	/** Pointer to const EFLAGS. */
129	typedef const X86EFLAGS *PCX86EFLAGS;
130
131	/**
132	* RFLAGS (32 upper bits are reserved).
133	*/
134	typedef union X86RFLAGS
135	{
136	/** The plain unsigned view. */
137	uint64_t u;
138	#ifndef VBOX_FOR_DTRACE_LIB
139	/** The bitfield view. */
140	X86EFLAGSBITS Bits;
141	#endif
142	/** The 8-bit view. */
143	uint8_t au8[8];
144	/** The 16-bit view. */
145	uint16_t au16[4];
146	/** The 32-bit view. */
147	uint32_t au32[2];
148	/** The 64-bit view. */
149	uint64_t au64[1];
150	/** The 64-bit view. */
151	uint64_t u64;
152	} X86RFLAGS;
153	/** Pointer to RFLAGS. */
154	typedef X86RFLAGS *PX86RFLAGS;
155	/** Pointer to const RFLAGS. */
156	typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159	/** @name EFLAGS
160	* @{
161	*/
162	/** Bit 0 - CF - Carry flag - Status flag. */
163	#define X86_EFL_CF RT_BIT(0)
164	/** Bit 1 - Reserved, reads as 1. */
165	#define X86_EFL_1 RT_BIT(1)
166	/** Bit 2 - PF - Parity flag - Status flag. */
167	#define X86_EFL_PF RT_BIT(2)
168	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
169	#define X86_EFL_AF RT_BIT(4)
170	/** Bit 6 - ZF - Zero flag - Status flag. */
171	#define X86_EFL_ZF RT_BIT(6)
172	/** Bit 7 - SF - Signed flag - Status flag. */
173	#define X86_EFL_SF RT_BIT(7)
174	/** Bit 8 - TF - Trap flag - System flag. */
175	#define X86_EFL_TF RT_BIT(8)
176	/** Bit 9 - IF - Interrupt flag - System flag. */
177	#define X86_EFL_IF RT_BIT(9)
178	/** Bit 10 - DF - Direction flag - Control flag. */
179	#define X86_EFL_DF RT_BIT(10)
180	/** Bit 11 - OF - Overflow flag - Status flag. */
181	#define X86_EFL_OF RT_BIT(11)
182	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
183	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
184	/** Bit 14 - NT - Nested task flag - System flag. */
185	#define X86_EFL_NT RT_BIT(14)
186	/** Bit 16 - RF - Resume flag - System flag. */
187	#define X86_EFL_RF RT_BIT(16)
188	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
189	#define X86_EFL_VM RT_BIT(17)
190	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
191	#define X86_EFL_AC RT_BIT(18)
192	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
193	#define X86_EFL_VIF RT_BIT(19)
194	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
195	#define X86_EFL_VIP RT_BIT(20)
196	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
197	#define X86_EFL_ID RT_BIT(21)
198	/** IOPL shift. */
199	#define X86_EFL_IOPL_SHIFT 12
200	/** The the IOPL level from the flags. */
201	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
202	/** Bits restored by popf */
203	#define X86_EFL_POPF_BITS (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID)
204	/** @} */
205
206
207	/** CPUID Feature information - ECX.
208	* CPUID query with EAX=1.
209	*/
210	#ifndef VBOX_FOR_DTRACE_LIB
211	typedef struct X86CPUIDFEATECX
212	{
213	/** Bit 0 - SSE3 - Supports SSE3 or not. */
214	unsigned u1SSE3 : 1;
215	/** Bit 1 - PCLMULQDQ. */
216	unsigned u1PCLMULQDQ : 1;
217	/** Bit 2 - DS Area 64-bit layout. */
218	unsigned u1DTE64 : 1;
219	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
220	unsigned u1Monitor : 1;
221	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
222	unsigned u1CPLDS : 1;
223	/** Bit 5 - VMX - Virtual Machine Technology. */
224	unsigned u1VMX : 1;
225	/** Bit 6 - SMX: Safer Mode Extensions. */
226	unsigned u1SMX : 1;
227	/** Bit 7 - EST - Enh. SpeedStep Tech. */
228	unsigned u1EST : 1;
229	/** Bit 8 - TM2 - Terminal Monitor 2. */
230	unsigned u1TM2 : 1;
231	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
232	unsigned u1SSSE3 : 1;
233	/** Bit 10 - CNTX-ID - L1 Context ID. */
234	unsigned u1CNTXID : 1;
235	/** Bit 11 - Reserved. */
236	unsigned u1Reserved1 : 1;
237	/** Bit 12 - FMA. */
238	unsigned u1FMA : 1;
239	/** Bit 13 - CX16 - CMPXCHG16B. */
240	unsigned u1CX16 : 1;
241	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
242	unsigned u1TPRUpdate : 1;
243	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
244	unsigned u1PDCM : 1;
245	/** Bit 16 - Reserved. */
246	unsigned u1Reserved2 : 1;
247	/** Bit 17 - PCID - Process-context identifiers. */
248	unsigned u1PCID : 1;
249	/** Bit 18 - Direct Cache Access. */
250	unsigned u1DCA : 1;
251	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
252	unsigned u1SSE4_1 : 1;
253	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
254	unsigned u1SSE4_2 : 1;
255	/** Bit 21 - x2APIC. */
256	unsigned u1x2APIC : 1;
257	/** Bit 22 - MOVBE - Supports MOVBE. */
258	unsigned u1MOVBE : 1;
259	/** Bit 23 - POPCNT - Supports POPCNT. */
260	unsigned u1POPCNT : 1;
261	/** Bit 24 - TSC-Deadline. */
262	unsigned u1TSCDEADLINE : 1;
263	/** Bit 25 - AES. */
264	unsigned u1AES : 1;
265	/** Bit 26 - XSAVE - Supports XSAVE. */
266	unsigned u1XSAVE : 1;
267	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
268	unsigned u1OSXSAVE : 1;
269	/** Bit 28 - AVX - Supports AVX instruction extensions. */
270	unsigned u1AVX : 1;
271	/** Bit 29 - 30 - Reserved */
272	unsigned u2Reserved3 : 2;
273	/** Bit 31 - Hypervisor present (we're a guest). */
274	unsigned u1HVP : 1;
275	} X86CPUIDFEATECX;
276	#else /* VBOX_FOR_DTRACE_LIB */
277	typedef uint32_t X86CPUIDFEATECX;
278	#endif /* VBOX_FOR_DTRACE_LIB */
279	/** Pointer to CPUID Feature Information - ECX. */
280	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
281	/** Pointer to const CPUID Feature Information - ECX. */
282	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
283
284
285	/** CPUID Feature Information - EDX.
286	* CPUID query with EAX=1.
287	*/
288	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
289	typedef struct X86CPUIDFEATEDX
290	{
291	/** Bit 0 - FPU - x87 FPU on Chip. */
292	unsigned u1FPU : 1;
293	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
294	unsigned u1VME : 1;
295	/** Bit 2 - DE - Debugging extensions. */
296	unsigned u1DE : 1;
297	/** Bit 3 - PSE - Page Size Extension. */
298	unsigned u1PSE : 1;
299	/** Bit 4 - TSC - Time Stamp Counter. */
300	unsigned u1TSC : 1;
301	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
302	unsigned u1MSR : 1;
303	/** Bit 6 - PAE - Physical Address Extension. */
304	unsigned u1PAE : 1;
305	/** Bit 7 - MCE - Machine Check Exception. */
306	unsigned u1MCE : 1;
307	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
308	unsigned u1CX8 : 1;
309	/** Bit 9 - APIC - APIC On-Chip. */
310	unsigned u1APIC : 1;
311	/** Bit 10 - Reserved. */
312	unsigned u1Reserved1 : 1;
313	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
314	unsigned u1SEP : 1;
315	/** Bit 12 - MTRR - Memory Type Range Registers. */
316	unsigned u1MTRR : 1;
317	/** Bit 13 - PGE - PTE Global Bit. */
318	unsigned u1PGE : 1;
319	/** Bit 14 - MCA - Machine Check Architecture. */
320	unsigned u1MCA : 1;
321	/** Bit 15 - CMOV - Conditional Move Instructions. */
322	unsigned u1CMOV : 1;
323	/** Bit 16 - PAT - Page Attribute Table. */
324	unsigned u1PAT : 1;
325	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
326	unsigned u1PSE36 : 1;
327	/** Bit 18 - PSN - Processor Serial Number. */
328	unsigned u1PSN : 1;
329	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
330	unsigned u1CLFSH : 1;
331	/** Bit 20 - Reserved. */
332	unsigned u1Reserved2 : 1;
333	/** Bit 21 - DS - Debug Store. */
334	unsigned u1DS : 1;
335	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
336	unsigned u1ACPI : 1;
337	/** Bit 23 - MMX - Intel MMX 'Technology'. */
338	unsigned u1MMX : 1;
339	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
340	unsigned u1FXSR : 1;
341	/** Bit 25 - SSE - SSE Support. */
342	unsigned u1SSE : 1;
343	/** Bit 26 - SSE2 - SSE2 Support. */
344	unsigned u1SSE2 : 1;
345	/** Bit 27 - SS - Self Snoop. */
346	unsigned u1SS : 1;
347	/** Bit 28 - HTT - Hyper-Threading Technology. */
348	unsigned u1HTT : 1;
349	/** Bit 29 - TM - Thermal Monitor. */
350	unsigned u1TM : 1;
351	/** Bit 30 - Reserved - . */
352	unsigned u1Reserved3 : 1;
353	/** Bit 31 - PBE - Pending Break Enabled. */
354	unsigned u1PBE : 1;
355	} X86CPUIDFEATEDX;
356	#else /* VBOX_FOR_DTRACE_LIB */
357	typedef uint32_t X86CPUIDFEATEDX;
358	#endif /* VBOX_FOR_DTRACE_LIB */
359	/** Pointer to CPUID Feature Information - EDX. */
360	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
361	/** Pointer to const CPUID Feature Information - EDX. */
362	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
363
364	/** @name CPUID Vendor information.
365	* CPUID query with EAX=0.
366	* @{
367	*/
368	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
369	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
370	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
371
372	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
373	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
374	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
375
376	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
377	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
378	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
379	/** @} */
380
381
382	/** @name CPUID Feature information.
383	* CPUID query with EAX=1.
384	* @{
385	*/
386	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
387	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
388	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
389	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
390	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
391	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
392	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
393	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
394	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
395	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
396	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
397	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
398	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
399	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
400	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
401	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
402	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
403	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
404	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
405	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
406	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
407	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
408	/** ECX Bit 12 - FMA. */
409	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
410	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
411	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
412	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
413	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
414	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
415	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
416	/** ECX Bit 17 - PCID - Process-context identifiers. */
417	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
418	/** ECX Bit 18 - DCA - Direct Cache Access. */
419	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
420	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
421	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
422	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
423	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
424	/** ECX Bit 21 - x2APIC support. */
425	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
426	/** ECX Bit 22 - MOVBE instruction. */
427	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
428	/** ECX Bit 23 - POPCNT instruction. */
429	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
430	/** ECX Bir 24 - TSC-Deadline. */
431	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
432	/** ECX Bit 25 - AES instructions. */
433	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
434	/** ECX Bit 26 - XSAVE instruction. */
435	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
436	/** ECX Bit 27 - OSXSAVE instruction. */
437	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
438	/** ECX Bit 28 - AVX. */
439	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
440	/** ECX Bit 31 - Hypervisor Present (software only). */
441	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
442
443
444	/** Bit 0 - FPU - x87 FPU on Chip. */
445	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
446	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
447	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
448	/** Bit 2 - DE - Debugging extensions. */
449	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
450	/** Bit 3 - PSE - Page Size Extension. */
451	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
452	/** Bit 4 - TSC - Time Stamp Counter. */
453	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
454	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
455	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
456	/** Bit 6 - PAE - Physical Address Extension. */
457	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
458	/** Bit 7 - MCE - Machine Check Exception. */
459	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
460	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
461	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
462	/** Bit 9 - APIC - APIC On-Chip. */
463	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
464	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
465	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
466	/** Bit 12 - MTRR - Memory Type Range Registers. */
467	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
468	/** Bit 13 - PGE - PTE Global Bit. */
469	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
470	/** Bit 14 - MCA - Machine Check Architecture. */
471	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
472	/** Bit 15 - CMOV - Conditional Move Instructions. */
473	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
474	/** Bit 16 - PAT - Page Attribute Table. */
475	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
476	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
477	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
478	/** Bit 18 - PSN - Processor Serial Number. */
479	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
480	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
481	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
482	/** Bit 21 - DS - Debug Store. */
483	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
484	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
485	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
486	/** Bit 23 - MMX - Intel MMX Technology. */
487	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
488	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
489	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
490	/** Bit 25 - SSE - SSE Support. */
491	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
492	/** Bit 26 - SSE2 - SSE2 Support. */
493	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
494	/** Bit 27 - SS - Self Snoop. */
495	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
496	/** Bit 28 - HTT - Hyper-Threading Technology. */
497	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
498	/** Bit 29 - TM - Therm. Monitor. */
499	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
500	/** Bit 31 - PBE - Pending Break Enabled. */
501	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
502	/** @} */
503
504	/** @name CPUID mwait/monitor information.
505	* CPUID query with EAX=5.
506	* @{
507	*/
508	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
509	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
510	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
511	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
512	/** @} */
513
514
515	/** @name CPUID Extended Feature information.
516	* CPUID query with EAX=0x80000001.
517	* @{
518	*/
519	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
520	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
521
522	/** EDX Bit 11 - SYSCALL/SYSRET. */
523	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
524	/** EDX Bit 20 - No-Execute/Execute-Disable. */
525	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
526	/** EDX Bit 26 - 1 GB large page. */
527	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
528	/** EDX Bit 27 - RDTSCP. */
529	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
530	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
531	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
532	/** @}*/
533
534	/** @name CPUID AMD Feature information.
535	* CPUID query with EAX=0x80000001.
536	* @{
537	*/
538	/** Bit 0 - FPU - x87 FPU on Chip. */
539	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
540	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
541	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
542	/** Bit 2 - DE - Debugging extensions. */
543	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
544	/** Bit 3 - PSE - Page Size Extension. */
545	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
546	/** Bit 4 - TSC - Time Stamp Counter. */
547	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
548	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
549	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
550	/** Bit 6 - PAE - Physical Address Extension. */
551	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
552	/** Bit 7 - MCE - Machine Check Exception. */
553	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
554	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
555	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
556	/** Bit 9 - APIC - APIC On-Chip. */
557	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
558	/** Bit 12 - MTRR - Memory Type Range Registers. */
559	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
560	/** Bit 13 - PGE - PTE Global Bit. */
561	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
562	/** Bit 14 - MCA - Machine Check Architecture. */
563	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
564	/** Bit 15 - CMOV - Conditional Move Instructions. */
565	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
566	/** Bit 16 - PAT - Page Attribute Table. */
567	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
568	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
569	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
570	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
571	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
572	/** Bit 23 - MMX - Intel MMX Technology. */
573	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
574	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
575	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
576	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
577	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
578	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
579	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
580	/** Bit 31 - 3DNOW - AMD 3DNow. */
581	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
582
583	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
584	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
585	/** Bit 2 - SVM - AMD VM extensions. */
586	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
587	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
588	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
589	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
590	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
591	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
592	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
593	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
594	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
595	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
596	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
597	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
598	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
599	/** Bit 9 - OSVW - AMD OS visible workaround. */
600	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
601	/** Bit 10 - IBS - Instruct based sampling. */
602	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
603	/** Bit 11 - SSE5 - SSE5 instruction support. */
604	#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
605	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
606	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
607	/** Bit 13 - WDT - AMD Watchdog timer support. */
608	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
609
610	/** @} */
611
612
613	/** @name CPUID AMD Feature information.
614	* CPUID query with EAX=0x80000007.
615	* @{
616	*/
617	/** Bit 0 - TS - Temperature Sensor. */
618	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
619	/** Bit 1 - FID - Frequency ID Control. */
620	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
621	/** Bit 2 - VID - Voltage ID Control. */
622	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
623	/** Bit 3 - TTP - THERMTRIP. */
624	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
625	/** Bit 4 - TM - Hardware Thermal Control. */
626	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
627	/** Bit 5 - STC - Software Thermal Control. */
628	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
629	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
630	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
631	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
632	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
633	/** Bit 8 - TSCINVAR - TSC Invariant. */
634	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
635	/** @} */
636
637
638	/** @name CR0
639	* @{ */
640	/** Bit 0 - PE - Protection Enabled */
641	#define X86_CR0_PE RT_BIT(0)
642	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
643	/** Bit 1 - MP - Monitor Coprocessor */
644	#define X86_CR0_MP RT_BIT(1)
645	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
646	/** Bit 2 - EM - Emulation. */
647	#define X86_CR0_EM RT_BIT(2)
648	#define X86_CR0_EMULATE_FPU RT_BIT(2)
649	/** Bit 3 - TS - Task Switch. */
650	#define X86_CR0_TS RT_BIT(3)
651	#define X86_CR0_TASK_SWITCH RT_BIT(3)
652	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
653	#define X86_CR0_ET RT_BIT(4)
654	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
655	/** Bit 5 - NE - Numeric error. */
656	#define X86_CR0_NE RT_BIT(5)
657	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
658	/** Bit 16 - WP - Write Protect. */
659	#define X86_CR0_WP RT_BIT(16)
660	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
661	/** Bit 18 - AM - Alignment Mask. */
662	#define X86_CR0_AM RT_BIT(18)
663	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
664	/** Bit 29 - NW - Not Write-though. */
665	#define X86_CR0_NW RT_BIT(29)
666	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
667	/** Bit 30 - WP - Cache Disable. */
668	#define X86_CR0_CD RT_BIT(30)
669	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
670	/** Bit 31 - PG - Paging. */
671	#define X86_CR0_PG RT_BIT(31)
672	#define X86_CR0_PAGING RT_BIT(31)
673	/** @} */
674
675
676	/** @name CR3
677	* @{ */
678	/** Bit 3 - PWT - Page-level Writes Transparent. */
679	#define X86_CR3_PWT RT_BIT(3)
680	/** Bit 4 - PCD - Page-level Cache Disable. */
681	#define X86_CR3_PCD RT_BIT(4)
682	/** Bits 12-31 - - Page directory page number. */
683	#define X86_CR3_PAGE_MASK (0xfffff000)
684	/** Bits 5-31 - - PAE Page directory page number. */
685	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
686	/** Bits 12-51 - - AMD64 Page directory page number. */
687	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
688	/** @} */
689
690
691	/** @name CR4
692	* @{ */
693	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
694	#define X86_CR4_VME RT_BIT(0)
695	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
696	#define X86_CR4_PVI RT_BIT(1)
697	/** Bit 2 - TSD - Time Stamp Disable. */
698	#define X86_CR4_TSD RT_BIT(2)
699	/** Bit 3 - DE - Debugging Extensions. */
700	#define X86_CR4_DE RT_BIT(3)
701	/** Bit 4 - PSE - Page Size Extension. */
702	#define X86_CR4_PSE RT_BIT(4)
703	/** Bit 5 - PAE - Physical Address Extension. */
704	#define X86_CR4_PAE RT_BIT(5)
705	/** Bit 6 - MCE - Machine-Check Enable. */
706	#define X86_CR4_MCE RT_BIT(6)
707	/** Bit 7 - PGE - Page Global Enable. */
708	#define X86_CR4_PGE RT_BIT(7)
709	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
710	#define X86_CR4_PCE RT_BIT(8)
711	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
712	#define X86_CR4_OSFSXR RT_BIT(9)
713	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
714	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
715	/** Bit 13 - VMXE - VMX mode is enabled. */
716	#define X86_CR4_VMXE RT_BIT(13)
717	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
718	#define X86_CR4_SMXE RT_BIT(14)
719	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
720	#define X86_CR4_PCIDE RT_BIT(17)
721	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
722	* extended states. */
723	#define X86_CR4_OSXSAVE RT_BIT(18)
724	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
725	#define X86_CR4_SMEP RT_BIT(20)
726	/** @} */
727
728
729	/** @name DR6
730	* @{ */
731	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
732	#define X86_DR6_B0 RT_BIT(0)
733	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
734	#define X86_DR6_B1 RT_BIT(1)
735	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
736	#define X86_DR6_B2 RT_BIT(2)
737	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
738	#define X86_DR6_B3 RT_BIT(3)
739	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
740	#define X86_DR6_BD RT_BIT(13)
741	/** Bit 14 - BS - Single step */
742	#define X86_DR6_BS RT_BIT(14)
743	/** Bit 15 - BT - Task switch. (TSS T bit.) */
744	#define X86_DR6_BT RT_BIT(15)
745	/** Value of DR6 after powerup/reset. */
746	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
747	/** Bits which must be 1s in DR6. */
748	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
749	/** Bits which must be 0s in DR6. */
750	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
751	/** Bits which must be 0s on writes to DR6. */
752	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
753	/** @} */
754
755
756	/** @name DR7
757	* @{ */
758	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
759	#define X86_DR7_L0 RT_BIT(0)
760	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
761	#define X86_DR7_G0 RT_BIT(1)
762	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
763	#define X86_DR7_L1 RT_BIT(2)
764	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
765	#define X86_DR7_G1 RT_BIT(3)
766	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
767	#define X86_DR7_L2 RT_BIT(4)
768	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
769	#define X86_DR7_G2 RT_BIT(5)
770	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
771	#define X86_DR7_L3 RT_BIT(6)
772	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
773	#define X86_DR7_G3 RT_BIT(7)
774	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
775	#define X86_DR7_LE RT_BIT(8)
776	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
777	#define X86_DR7_GE RT_BIT(9)
778
779	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
780	* any DR register is accessed. */
781	#define X86_DR7_GD RT_BIT(13)
782	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
783	#define X86_DR7_RW0_MASK (3 << 16)
784	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
785	#define X86_DR7_LEN0_MASK (3 << 18)
786	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
787	#define X86_DR7_RW1_MASK (3 << 20)
788	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
789	#define X86_DR7_LEN1_MASK (3 << 22)
790	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
791	#define X86_DR7_RW2_MASK (3 << 24)
792	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
793	#define X86_DR7_LEN2_MASK (3 << 26)
794	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
795	#define X86_DR7_RW3_MASK (3 << 28)
796	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
797	#define X86_DR7_LEN3_MASK (3 << 30)
798
799	/** Bits which reads as 1s. */
800	#define X86_DR7_RA1_MASK (RT_BIT(10))
801	/** Bits which reads as zeros. */
802	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
803	/** Bits which must be 0s when writing to DR7. */
804	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
805
806	/** Calcs the L bit of Nth breakpoint.
807	* @param iBp The breakpoint number [0..3].
808	*/
809	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
810
811	/** Calcs the G bit of Nth breakpoint.
812	* @param iBp The breakpoint number [0..3].
813	*/
814	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
815
816	/** @name Read/Write values.
817	* @{ */
818	/** Break on instruction fetch only. */
819	#define X86_DR7_RW_EO 0U
820	/** Break on write only. */
821	#define X86_DR7_RW_WO 1U
822	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
823	#define X86_DR7_RW_IO 2U
824	/** Break on read or write (but not instruction fetches). */
825	#define X86_DR7_RW_RW 3U
826	/** @} */
827
828	/** Shifts a X86_DR7_RW_* value to its right place.
829	* @param iBp The breakpoint number [0..3].
830	* @param fRw One of the X86_DR7_RW_* value.
831	*/
832	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
833
834	/** @name Length values.
835	* @{ */
836	#define X86_DR7_LEN_BYTE 0U
837	#define X86_DR7_LEN_WORD 1U
838	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
839	#define X86_DR7_LEN_DWORD 3U
840	/** @} */
841
842	/** Shifts a X86_DR7_LEN_* value to its right place.
843	* @param iBp The breakpoint number [0..3].
844	* @param cb One of the X86_DR7_LEN_* values.
845	*/
846	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
847
848	/** Fetch the breakpoint length bits from the DR7 value.
849	* @param uDR7 DR7 value
850	* @param iBp The breakpoint number [0..3].
851	*/
852	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
853
854	/** Mask used to check if any breakpoints are enabled. */
855	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
856
857	/** Mask used to check if any io breakpoints are set. */
858	#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) \| X86_DR7_RW(1, X86_DR7_RW_IO) \| X86_DR7_RW(2, X86_DR7_RW_IO) \| X86_DR7_RW(3, X86_DR7_RW_IO))
859
860	/** Value of DR7 after powerup/reset. */
861	#define X86_DR7_INIT_VAL 0x400
862	/** @} */
863
864
865	/** @name Machine Specific Registers
866	* @{
867	*/
868
869	/** Time Stamp Counter. */
870	#define MSR_IA32_TSC 0x10
871
872	#define MSR_IA32_PLATFORM_ID 0x17
873
874	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
875	#define MSR_IA32_APICBASE 0x1b
876	#endif
877
878	/** CPU Feature control. */
879	#define MSR_IA32_FEATURE_CONTROL 0x3A
880	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
881	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
882
883	/** BIOS update trigger (microcode update). */
884	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
885
886	/** BIOS update signature (microcode). */
887	#define MSR_IA32_BIOS_SIGN_ID 0x8B
888
889	/** General performance counter no. 0. */
890	#define MSR_IA32_PMC0 0xC1
891	/** General performance counter no. 1. */
892	#define MSR_IA32_PMC1 0xC2
893	/** General performance counter no. 2. */
894	#define MSR_IA32_PMC2 0xC3
895	/** General performance counter no. 3. */
896	#define MSR_IA32_PMC3 0xC4
897
898	/** Nehalem power control. */
899	#define MSR_IA32_PLATFORM_INFO 0xCE
900
901	/** Get FSB clock status (Intel-specific). */
902	#define MSR_IA32_FSB_CLOCK_STS 0xCD
903
904	/** MTRR Capabilities. */
905	#define MSR_IA32_MTRR_CAP 0xFE
906
907
908	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
909	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
910	* R0 SS == CS + 8
911	* R3 CS == CS + 16
912	* R3 SS == CS + 24
913	*/
914	#define MSR_IA32_SYSENTER_CS 0x174
915	/** SYSENTER_ESP - the R0 ESP. */
916	#define MSR_IA32_SYSENTER_ESP 0x175
917	/** SYSENTER_EIP - the R0 EIP. */
918	#define MSR_IA32_SYSENTER_EIP 0x176
919	#endif
920
921	/** Machine Check Global Capabilities Register. */
922	#define MSR_IA32_MCP_CAP 0x179
923	/** Machine Check Global Status Register. */
924	#define MSR_IA32_MCP_STATUS 0x17A
925	/** Machine Check Global Control Register. */
926	#define MSR_IA32_MCP_CTRL 0x17B
927
928	/** Trace/Profile Resource Control (R/W) */
929	#define MSR_IA32_DEBUGCTL 0x1D9
930
931	/** Page Attribute Table. */
932	#define MSR_IA32_CR_PAT 0x277
933
934	/** Performance counter MSRs. (Intel only) */
935	#define MSR_IA32_PERFEVTSEL0 0x186
936	#define MSR_IA32_PERFEVTSEL1 0x187
937	#define MSR_IA32_FLEX_RATIO 0x194
938	#define MSR_IA32_PERF_STATUS 0x198
939	#define MSR_IA32_PERF_CTL 0x199
940	#define MSR_IA32_THERM_STATUS 0x19c
941
942	/** Enable misc. processor features (R/W). */
943	#define MSR_IA32_MISC_ENABLE 0x1A0
944	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
945	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
946	/** Automatic Thermal Control Circuit Enable (R/W). */
947	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
948	/** Performance Monitoring Available (R). */
949	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
950	/** Branch Trace Storage Unavailable (R/O). */
951	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
952	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
953	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
954	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
955	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
956	/** If MONITOR/MWAIT is supported (R/W). */
957	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
958	/** Limit CPUID Maxval to 3 leafs (R/W). */
959	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
960	/** When set to 1, xTPR messages are disabled (R/W). */
961	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
962	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
963	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
964
965	#define IA32_MTRR_PHYSBASE0 0x200
966	#define IA32_MTRR_PHYSMASK0 0x201
967	#define IA32_MTRR_PHYSBASE1 0x202
968	#define IA32_MTRR_PHYSMASK1 0x203
969	#define IA32_MTRR_PHYSBASE2 0x204
970	#define IA32_MTRR_PHYSMASK2 0x205
971	#define IA32_MTRR_PHYSBASE3 0x206
972	#define IA32_MTRR_PHYSMASK3 0x207
973	#define IA32_MTRR_PHYSBASE4 0x208
974	#define IA32_MTRR_PHYSMASK4 0x209
975	#define IA32_MTRR_PHYSBASE5 0x20a
976	#define IA32_MTRR_PHYSMASK5 0x20b
977	#define IA32_MTRR_PHYSBASE6 0x20c
978	#define IA32_MTRR_PHYSMASK6 0x20d
979	#define IA32_MTRR_PHYSBASE7 0x20e
980	#define IA32_MTRR_PHYSMASK7 0x20f
981	#define IA32_MTRR_PHYSBASE8 0x210
982	#define IA32_MTRR_PHYSMASK8 0x211
983	#define IA32_MTRR_PHYSBASE9 0x212
984	#define IA32_MTRR_PHYSMASK9 0x213
985
986	/** Fixed range MTRRs.
987	* @{ */
988	#define IA32_MTRR_FIX64K_00000 0x250
989	#define IA32_MTRR_FIX16K_80000 0x258
990	#define IA32_MTRR_FIX16K_A0000 0x259
991	#define IA32_MTRR_FIX4K_C0000 0x268
992	#define IA32_MTRR_FIX4K_C8000 0x269
993	#define IA32_MTRR_FIX4K_D0000 0x26a
994	#define IA32_MTRR_FIX4K_D8000 0x26b
995	#define IA32_MTRR_FIX4K_E0000 0x26c
996	#define IA32_MTRR_FIX4K_E8000 0x26d
997	#define IA32_MTRR_FIX4K_F0000 0x26e
998	#define IA32_MTRR_FIX4K_F8000 0x26f
999	/** @} */
1000
1001	/** MTRR Default Range. */
1002	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1003
1004	#define MSR_IA32_MC0_CTL 0x400
1005	#define MSR_IA32_MC0_STATUS 0x401
1006
1007	/** Basic VMX information. */
1008	#define MSR_IA32_VMX_BASIC_INFO 0x480
1009	/** Allowed settings for pin-based VM execution controls */
1010	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1011	/** Allowed settings for proc-based VM execution controls */
1012	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1013	/** Allowed settings for the VMX exit controls. */
1014	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1015	/** Allowed settings for the VMX entry controls. */
1016	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1017	/** Misc VMX info. */
1018	#define MSR_IA32_VMX_MISC 0x485
1019	/** Fixed cleared bits in CR0. */
1020	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1021	/** Fixed set bits in CR0. */
1022	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1023	/** Fixed cleared bits in CR4. */
1024	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1025	/** Fixed set bits in CR4. */
1026	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1027	/** Information for enumerating fields in the VMCS. */
1028	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1029	/** Allowed settings for the VM-functions controls. */
1030	#define MSR_IA32_VMX_VMFUNC 0x491
1031	/** Allowed settings for secondary proc-based VM execution controls */
1032	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1033	/** EPT capabilities. */
1034	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1035	/** DS Save Area (R/W). */
1036	#define MSR_IA32_DS_AREA 0x600
1037	/** X2APIC MSR ranges. */
1038	#define MSR_IA32_X2APIC_START 0x800
1039	#define MSR_IA32_X2APIC_TPR 0x808
1040	#define MSR_IA32_X2APIC_END 0xBFF
1041
1042	/** K6 EFER - Extended Feature Enable Register. */
1043	#define MSR_K6_EFER 0xc0000080
1044	/** @todo document EFER */
1045	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1046	#define MSR_K6_EFER_SCE RT_BIT(0)
1047	/** Bit 8 - LME - Long mode enabled. (R/W) */
1048	#define MSR_K6_EFER_LME RT_BIT(8)
1049	/** Bit 10 - LMA - Long mode active. (R) */
1050	#define MSR_K6_EFER_LMA RT_BIT(10)
1051	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1052	#define MSR_K6_EFER_NXE RT_BIT(11)
1053	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1054	#define MSR_K6_EFER_SVME RT_BIT(12)
1055	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1056	#define MSR_K6_EFER_LMSLE RT_BIT(13)
1057	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1058	#define MSR_K6_EFER_FFXSR RT_BIT(14)
1059	/** K6 STAR - SYSCALL/RET targets. */
1060	#define MSR_K6_STAR 0xc0000081
1061	/** Shift value for getting the SYSRET CS and SS value. */
1062	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1063	/** Shift value for getting the SYSCALL CS and SS value. */
1064	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1065	/** Selector mask for use after shifting. */
1066	#define MSR_K6_STAR_SEL_MASK 0xffff
1067	/** The mask which give the SYSCALL EIP. */
1068	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
1069	/** K6 WHCR - Write Handling Control Register. */
1070	#define MSR_K6_WHCR 0xc0000082
1071	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1072	#define MSR_K6_UWCCR 0xc0000085
1073	/** K6 PSOR - Processor State Observability Register. */
1074	#define MSR_K6_PSOR 0xc0000087
1075	/** K6 PFIR - Page Flush/Invalidate Register. */
1076	#define MSR_K6_PFIR 0xc0000088
1077
1078	/** Performance counter MSRs. (AMD only) */
1079	#define MSR_K7_EVNTSEL0 0xc0010000
1080	#define MSR_K7_EVNTSEL1 0xc0010001
1081	#define MSR_K7_EVNTSEL2 0xc0010002
1082	#define MSR_K7_EVNTSEL3 0xc0010003
1083	#define MSR_K7_PERFCTR0 0xc0010004
1084	#define MSR_K7_PERFCTR1 0xc0010005
1085	#define MSR_K7_PERFCTR2 0xc0010006
1086	#define MSR_K7_PERFCTR3 0xc0010007
1087
1088	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1089	#define MSR_K8_LSTAR 0xc0000082
1090	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1091	#define MSR_K8_CSTAR 0xc0000083
1092	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1093	#define MSR_K8_SF_MASK 0xc0000084
1094	/** K8 FS.base - The 64-bit base FS register. */
1095	#define MSR_K8_FS_BASE 0xc0000100
1096	/** K8 GS.base - The 64-bit base GS register. */
1097	#define MSR_K8_GS_BASE 0xc0000101
1098	/** K8 KernelGSbase - Used with SWAPGS. */
1099	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
1100	/** K8 TSC_AUX - Used with RDTSCP. */
1101	#define MSR_K8_TSC_AUX 0xc0000103
1102	#define MSR_K8_SYSCFG 0xc0010010
1103	#define MSR_K8_HWCR 0xc0010015
1104	#define MSR_K8_IORRBASE0 0xc0010016
1105	#define MSR_K8_IORRMASK0 0xc0010017
1106	#define MSR_K8_IORRBASE1 0xc0010018
1107	#define MSR_K8_IORRMASK1 0xc0010019
1108	#define MSR_K8_TOP_MEM1 0xc001001a
1109	#define MSR_K8_TOP_MEM2 0xc001001d
1110	#define MSR_K8_VM_CR 0xc0010114
1111	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1112
1113	#define MSR_K8_IGNNE 0xc0010115
1114	#define MSR_K8_SMM_CTL 0xc0010116
1115	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1116	* host state during world switch.
1117	*/
1118	#define MSR_K8_VM_HSAVE_PA 0xc0010117
1119
1120	/** @} */
1121
1122
1123	/** @name Page Table / Directory / Directory Pointers / L4.
1124	* @{
1125	*/
1126
1127	/** Page table/directory entry as an unsigned integer. */
1128	typedef uint32_t X86PGUINT;
1129	/** Pointer to a page table/directory table entry as an unsigned integer. */
1130	typedef X86PGUINT *PX86PGUINT;
1131	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1132	typedef X86PGUINT const *PCX86PGUINT;
1133
1134	/** Number of entries in a 32-bit PT/PD. */
1135	#define X86_PG_ENTRIES 1024
1136
1137
1138	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1139	typedef uint64_t X86PGPAEUINT;
1140	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1141	typedef X86PGPAEUINT *PX86PGPAEUINT;
1142	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1143	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1144
1145	/** Number of entries in a PAE PT/PD. */
1146	#define X86_PG_PAE_ENTRIES 512
1147	/** Number of entries in a PAE PDPT. */
1148	#define X86_PG_PAE_PDPE_ENTRIES 4
1149
1150	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1151	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1152	/** Number of entries in an AMD64 PDPT.
1153	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1154	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1155
1156	/** The size of a 4KB page. */
1157	#define X86_PAGE_4K_SIZE _4K
1158	/** The page shift of a 4KB page. */
1159	#define X86_PAGE_4K_SHIFT 12
1160	/** The 4KB page offset mask. */
1161	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1162	/** The 4KB page base mask for virtual addresses. */
1163	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1164	/** The 4KB page base mask for virtual addresses - 32bit version. */
1165	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1166
1167	/** The size of a 2MB page. */
1168	#define X86_PAGE_2M_SIZE _2M
1169	/** The page shift of a 2MB page. */
1170	#define X86_PAGE_2M_SHIFT 21
1171	/** The 2MB page offset mask. */
1172	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1173	/** The 2MB page base mask for virtual addresses. */
1174	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1175	/** The 2MB page base mask for virtual addresses - 32bit version. */
1176	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1177
1178	/** The size of a 4MB page. */
1179	#define X86_PAGE_4M_SIZE _4M
1180	/** The page shift of a 4MB page. */
1181	#define X86_PAGE_4M_SHIFT 22
1182	/** The 4MB page offset mask. */
1183	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1184	/** The 4MB page base mask for virtual addresses. */
1185	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1186	/** The 4MB page base mask for virtual addresses - 32bit version. */
1187	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1188
1189
1190
1191	/** @name Page Table Entry
1192	* @{
1193	*/
1194	/** Bit 0 - P - Present bit. */
1195	#define X86_PTE_BIT_P 0
1196	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1197	#define X86_PTE_BIT_RW 1
1198	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1199	#define X86_PTE_BIT_US 2
1200	/** Bit 3 - PWT - Page level write thru bit. */
1201	#define X86_PTE_BIT_PWT 3
1202	/** Bit 4 - PCD - Page level cache disable bit. */
1203	#define X86_PTE_BIT_PCD 4
1204	/** Bit 5 - A - Access bit. */
1205	#define X86_PTE_BIT_A 5
1206	/** Bit 6 - D - Dirty bit. */
1207	#define X86_PTE_BIT_D 6
1208	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1209	#define X86_PTE_BIT_PAT 7
1210	/** Bit 8 - G - Global flag. */
1211	#define X86_PTE_BIT_G 8
1212
1213	/** Bit 0 - P - Present bit mask. */
1214	#define X86_PTE_P RT_BIT(0)
1215	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1216	#define X86_PTE_RW RT_BIT(1)
1217	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1218	#define X86_PTE_US RT_BIT(2)
1219	/** Bit 3 - PWT - Page level write thru bit mask. */
1220	#define X86_PTE_PWT RT_BIT(3)
1221	/** Bit 4 - PCD - Page level cache disable bit mask. */
1222	#define X86_PTE_PCD RT_BIT(4)
1223	/** Bit 5 - A - Access bit mask. */
1224	#define X86_PTE_A RT_BIT(5)
1225	/** Bit 6 - D - Dirty bit mask. */
1226	#define X86_PTE_D RT_BIT(6)
1227	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1228	#define X86_PTE_PAT RT_BIT(7)
1229	/** Bit 8 - G - Global bit mask. */
1230	#define X86_PTE_G RT_BIT(8)
1231
1232	/** Bits 9-11 - - Available for use to system software. */
1233	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1234	/** Bits 12-31 - - Physical Page number of the next level. */
1235	#define X86_PTE_PG_MASK ( 0xfffff000 )
1236
1237	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1238	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1239	/** Bits 63 - NX - PAE/LM - No execution flag. */
1240	#define X86_PTE_PAE_NX RT_BIT_64(63)
1241	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1242	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1243	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1244	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1245	/** No bits - - LM - MBZ bits when NX is active. */
1246	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1247	/** Bits 63 - - LM - MBZ bits when no NX. */
1248	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1249
1250	/**
1251	* Page table entry.
1252	*/
1253	typedef struct X86PTEBITS
1254	{
1255	/** Flags whether(=1) or not the page is present. */
1256	unsigned u1Present : 1;
1257	/** Read(=0) / Write(=1) flag. */
1258	unsigned u1Write : 1;
1259	/** User(=1) / Supervisor (=0) flag. */
1260	unsigned u1User : 1;
1261	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1262	unsigned u1WriteThru : 1;
1263	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1264	unsigned u1CacheDisable : 1;
1265	/** Accessed flag.
1266	* Indicates that the page have been read or written to. */
1267	unsigned u1Accessed : 1;
1268	/** Dirty flag.
1269	* Indicates that the page has been written to. */
1270	unsigned u1Dirty : 1;
1271	/** Reserved / If PAT enabled, bit 2 of the index. */
1272	unsigned u1PAT : 1;
1273	/** Global flag. (Ignored in all but final level.) */
1274	unsigned u1Global : 1;
1275	/** Available for use to system software. */
1276	unsigned u3Available : 3;
1277	/** Physical Page number of the next level. */
1278	unsigned u20PageNo : 20;
1279	} X86PTEBITS;
1280	/** Pointer to a page table entry. */
1281	typedef X86PTEBITS *PX86PTEBITS;
1282	/** Pointer to a const page table entry. */
1283	typedef const X86PTEBITS *PCX86PTEBITS;
1284
1285	/**
1286	* Page table entry.
1287	*/
1288	typedef union X86PTE
1289	{
1290	/** Unsigned integer view */
1291	X86PGUINT u;
1292	/** Bit field view. */
1293	X86PTEBITS n;
1294	/** 32-bit view. */
1295	uint32_t au32[1];
1296	/** 16-bit view. */
1297	uint16_t au16[2];
1298	/** 8-bit view. */
1299	uint8_t au8[4];
1300	} X86PTE;
1301	/** Pointer to a page table entry. */
1302	typedef X86PTE *PX86PTE;
1303	/** Pointer to a const page table entry. */
1304	typedef const X86PTE *PCX86PTE;
1305
1306
1307	/**
1308	* PAE page table entry.
1309	*/
1310	typedef struct X86PTEPAEBITS
1311	{
1312	/** Flags whether(=1) or not the page is present. */
1313	uint32_t u1Present : 1;
1314	/** Read(=0) / Write(=1) flag. */
1315	uint32_t u1Write : 1;
1316	/** User(=1) / Supervisor(=0) flag. */
1317	uint32_t u1User : 1;
1318	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1319	uint32_t u1WriteThru : 1;
1320	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1321	uint32_t u1CacheDisable : 1;
1322	/** Accessed flag.
1323	* Indicates that the page have been read or written to. */
1324	uint32_t u1Accessed : 1;
1325	/** Dirty flag.
1326	* Indicates that the page has been written to. */
1327	uint32_t u1Dirty : 1;
1328	/** Reserved / If PAT enabled, bit 2 of the index. */
1329	uint32_t u1PAT : 1;
1330	/** Global flag. (Ignored in all but final level.) */
1331	uint32_t u1Global : 1;
1332	/** Available for use to system software. */
1333	uint32_t u3Available : 3;
1334	/** Physical Page number of the next level - Low Part. Don't use this. */
1335	uint32_t u20PageNoLow : 20;
1336	/** Physical Page number of the next level - High Part. Don't use this. */
1337	uint32_t u20PageNoHigh : 20;
1338	/** MBZ bits */
1339	uint32_t u11Reserved : 11;
1340	/** No Execute flag. */
1341	uint32_t u1NoExecute : 1;
1342	} X86PTEPAEBITS;
1343	/** Pointer to a page table entry. */
1344	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1345	/** Pointer to a page table entry. */
1346	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1347
1348	/**
1349	* PAE Page table entry.
1350	*/
1351	typedef union X86PTEPAE
1352	{
1353	/** Unsigned integer view */
1354	X86PGPAEUINT u;
1355	/** Bit field view. */
1356	X86PTEPAEBITS n;
1357	/** 32-bit view. */
1358	uint32_t au32[2];
1359	/** 16-bit view. */
1360	uint16_t au16[4];
1361	/** 8-bit view. */
1362	uint8_t au8[8];
1363	} X86PTEPAE;
1364	/** Pointer to a PAE page table entry. */
1365	typedef X86PTEPAE *PX86PTEPAE;
1366	/** Pointer to a const PAE page table entry. */
1367	typedef const X86PTEPAE *PCX86PTEPAE;
1368	/** @} */
1369
1370	/**
1371	* Page table.
1372	*/
1373	typedef struct X86PT
1374	{
1375	/** PTE Array. */
1376	X86PTE a[X86_PG_ENTRIES];
1377	} X86PT;
1378	/** Pointer to a page table. */
1379	typedef X86PT *PX86PT;
1380	/** Pointer to a const page table. */
1381	typedef const X86PT *PCX86PT;
1382
1383	/** The page shift to get the PT index. */
1384	#define X86_PT_SHIFT 12
1385	/** The PT index mask (apply to a shifted page address). */
1386	#define X86_PT_MASK 0x3ff
1387
1388
1389	/**
1390	* Page directory.
1391	*/
1392	typedef struct X86PTPAE
1393	{
1394	/** PTE Array. */
1395	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1396	} X86PTPAE;
1397	/** Pointer to a page table. */
1398	typedef X86PTPAE *PX86PTPAE;
1399	/** Pointer to a const page table. */
1400	typedef const X86PTPAE *PCX86PTPAE;
1401
1402	/** The page shift to get the PA PTE index. */
1403	#define X86_PT_PAE_SHIFT 12
1404	/** The PAE PT index mask (apply to a shifted page address). */
1405	#define X86_PT_PAE_MASK 0x1ff
1406
1407
1408	/** @name 4KB Page Directory Entry
1409	* @{
1410	*/
1411	/** Bit 0 - P - Present bit. */
1412	#define X86_PDE_P RT_BIT(0)
1413	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1414	#define X86_PDE_RW RT_BIT(1)
1415	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1416	#define X86_PDE_US RT_BIT(2)
1417	/** Bit 3 - PWT - Page level write thru bit. */
1418	#define X86_PDE_PWT RT_BIT(3)
1419	/** Bit 4 - PCD - Page level cache disable bit. */
1420	#define X86_PDE_PCD RT_BIT(4)
1421	/** Bit 5 - A - Access bit. */
1422	#define X86_PDE_A RT_BIT(5)
1423	/** Bit 7 - PS - Page size attribute.
1424	* Clear mean 4KB pages, set means large pages (2/4MB). */
1425	#define X86_PDE_PS RT_BIT(7)
1426	/** Bits 9-11 - - Available for use to system software. */
1427	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1428	/** Bits 12-31 - - Physical Page number of the next level. */
1429	#define X86_PDE_PG_MASK ( 0xfffff000 )
1430
1431	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1432	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1433	/** Bits 63 - NX - PAE/LM - No execution flag. */
1434	#define X86_PDE_PAE_NX RT_BIT_64(63)
1435	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1436	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1437	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1438	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1439	/** Bit 7 - - LM - MBZ bits when NX is active. */
1440	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1441	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1442	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1443
1444	/**
1445	* Page directory entry.
1446	*/
1447	typedef struct X86PDEBITS
1448	{
1449	/** Flags whether(=1) or not the page is present. */
1450	unsigned u1Present : 1;
1451	/** Read(=0) / Write(=1) flag. */
1452	unsigned u1Write : 1;
1453	/** User(=1) / Supervisor (=0) flag. */
1454	unsigned u1User : 1;
1455	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1456	unsigned u1WriteThru : 1;
1457	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1458	unsigned u1CacheDisable : 1;
1459	/** Accessed flag.
1460	* Indicates that the page has been read or written to. */
1461	unsigned u1Accessed : 1;
1462	/** Reserved / Ignored (dirty bit). */
1463	unsigned u1Reserved0 : 1;
1464	/** Size bit if PSE is enabled - in any event it's 0. */
1465	unsigned u1Size : 1;
1466	/** Reserved / Ignored (global bit). */
1467	unsigned u1Reserved1 : 1;
1468	/** Available for use to system software. */
1469	unsigned u3Available : 3;
1470	/** Physical Page number of the next level. */
1471	unsigned u20PageNo : 20;
1472	} X86PDEBITS;
1473	/** Pointer to a page directory entry. */
1474	typedef X86PDEBITS *PX86PDEBITS;
1475	/** Pointer to a const page directory entry. */
1476	typedef const X86PDEBITS *PCX86PDEBITS;
1477
1478
1479	/**
1480	* PAE page directory entry.
1481	*/
1482	typedef struct X86PDEPAEBITS
1483	{
1484	/** Flags whether(=1) or not the page is present. */
1485	uint32_t u1Present : 1;
1486	/** Read(=0) / Write(=1) flag. */
1487	uint32_t u1Write : 1;
1488	/** User(=1) / Supervisor (=0) flag. */
1489	uint32_t u1User : 1;
1490	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1491	uint32_t u1WriteThru : 1;
1492	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1493	uint32_t u1CacheDisable : 1;
1494	/** Accessed flag.
1495	* Indicates that the page has been read or written to. */
1496	uint32_t u1Accessed : 1;
1497	/** Reserved / Ignored (dirty bit). */
1498	uint32_t u1Reserved0 : 1;
1499	/** Size bit if PSE is enabled - in any event it's 0. */
1500	uint32_t u1Size : 1;
1501	/** Reserved / Ignored (global bit). / */
1502	uint32_t u1Reserved1 : 1;
1503	/** Available for use to system software. */
1504	uint32_t u3Available : 3;
1505	/** Physical Page number of the next level - Low Part. Don't use! */
1506	uint32_t u20PageNoLow : 20;
1507	/** Physical Page number of the next level - High Part. Don't use! */
1508	uint32_t u20PageNoHigh : 20;
1509	/** MBZ bits */
1510	uint32_t u11Reserved : 11;
1511	/** No Execute flag. */
1512	uint32_t u1NoExecute : 1;
1513	} X86PDEPAEBITS;
1514	/** Pointer to a page directory entry. */
1515	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1516	/** Pointer to a const page directory entry. */
1517	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1518
1519	/** @} */
1520
1521
1522	/** @name 2/4MB Page Directory Entry
1523	* @{
1524	*/
1525	/** Bit 0 - P - Present bit. */
1526	#define X86_PDE4M_P RT_BIT(0)
1527	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1528	#define X86_PDE4M_RW RT_BIT(1)
1529	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1530	#define X86_PDE4M_US RT_BIT(2)
1531	/** Bit 3 - PWT - Page level write thru bit. */
1532	#define X86_PDE4M_PWT RT_BIT(3)
1533	/** Bit 4 - PCD - Page level cache disable bit. */
1534	#define X86_PDE4M_PCD RT_BIT(4)
1535	/** Bit 5 - A - Access bit. */
1536	#define X86_PDE4M_A RT_BIT(5)
1537	/** Bit 6 - D - Dirty bit. */
1538	#define X86_PDE4M_D RT_BIT(6)
1539	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1540	#define X86_PDE4M_PS RT_BIT(7)
1541	/** Bit 8 - G - Global flag. */
1542	#define X86_PDE4M_G RT_BIT(8)
1543	/** Bits 9-11 - AVL - Available for use to system software. */
1544	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1545	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1546	#define X86_PDE4M_PAT RT_BIT(12)
1547	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1548	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1549	/** Bits 22-31 - - Physical Page number. */
1550	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1551	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1552	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1553	/** The number of bits to the high part of the page number. */
1554	#define X86_PDE4M_PG_HIGH_SHIFT 19
1555	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1556	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1557
1558	/** Bits 21-51 - - PAE/LM - Physical Page number.
1559	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1560	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1561	/** Bits 63 - NX - PAE/LM - No execution flag. */
1562	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1563	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1564	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1565	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1566	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1567	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1568	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1569	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1570	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1571
1572	/**
1573	* 4MB page directory entry.
1574	*/
1575	typedef struct X86PDE4MBITS
1576	{
1577	/** Flags whether(=1) or not the page is present. */
1578	unsigned u1Present : 1;
1579	/** Read(=0) / Write(=1) flag. */
1580	unsigned u1Write : 1;
1581	/** User(=1) / Supervisor (=0) flag. */
1582	unsigned u1User : 1;
1583	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1584	unsigned u1WriteThru : 1;
1585	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1586	unsigned u1CacheDisable : 1;
1587	/** Accessed flag.
1588	* Indicates that the page have been read or written to. */
1589	unsigned u1Accessed : 1;
1590	/** Dirty flag.
1591	* Indicates that the page has been written to. */
1592	unsigned u1Dirty : 1;
1593	/** Page size flag - always 1 for 4MB entries. */
1594	unsigned u1Size : 1;
1595	/** Global flag. */
1596	unsigned u1Global : 1;
1597	/** Available for use to system software. */
1598	unsigned u3Available : 3;
1599	/** Reserved / If PAT enabled, bit 2 of the index. */
1600	unsigned u1PAT : 1;
1601	/** Bits 32-39 of the page number on AMD64.
1602	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1603	unsigned u8PageNoHigh : 8;
1604	/** Reserved. */
1605	unsigned u1Reserved : 1;
1606	/** Physical Page number of the page. */
1607	unsigned u10PageNo : 10;
1608	} X86PDE4MBITS;
1609	/** Pointer to a page table entry. */
1610	typedef X86PDE4MBITS *PX86PDE4MBITS;
1611	/** Pointer to a const page table entry. */
1612	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1613
1614
1615	/**
1616	* 2MB PAE page directory entry.
1617	*/
1618	typedef struct X86PDE2MPAEBITS
1619	{
1620	/** Flags whether(=1) or not the page is present. */
1621	uint32_t u1Present : 1;
1622	/** Read(=0) / Write(=1) flag. */
1623	uint32_t u1Write : 1;
1624	/** User(=1) / Supervisor(=0) flag. */
1625	uint32_t u1User : 1;
1626	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1627	uint32_t u1WriteThru : 1;
1628	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1629	uint32_t u1CacheDisable : 1;
1630	/** Accessed flag.
1631	* Indicates that the page have been read or written to. */
1632	uint32_t u1Accessed : 1;
1633	/** Dirty flag.
1634	* Indicates that the page has been written to. */
1635	uint32_t u1Dirty : 1;
1636	/** Page size flag - always 1 for 2MB entries. */
1637	uint32_t u1Size : 1;
1638	/** Global flag. */
1639	uint32_t u1Global : 1;
1640	/** Available for use to system software. */
1641	uint32_t u3Available : 3;
1642	/** Reserved / If PAT enabled, bit 2 of the index. */
1643	uint32_t u1PAT : 1;
1644	/** Reserved. */
1645	uint32_t u9Reserved : 9;
1646	/** Physical Page number of the next level - Low part. Don't use! */
1647	uint32_t u10PageNoLow : 10;
1648	/** Physical Page number of the next level - High part. Don't use! */
1649	uint32_t u20PageNoHigh : 20;
1650	/** MBZ bits */
1651	uint32_t u11Reserved : 11;
1652	/** No Execute flag. */
1653	uint32_t u1NoExecute : 1;
1654	} X86PDE2MPAEBITS;
1655	/** Pointer to a 2MB PAE page table entry. */
1656	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1657	/** Pointer to a 2MB PAE page table entry. */
1658	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1659
1660	/** @} */
1661
1662	/**
1663	* Page directory entry.
1664	*/
1665	typedef union X86PDE
1666	{
1667	/** Unsigned integer view. */
1668	X86PGUINT u;
1669	/** Normal view. */
1670	X86PDEBITS n;
1671	/** 4MB view (big). */
1672	X86PDE4MBITS b;
1673	/** 8 bit unsigned integer view. */
1674	uint8_t au8[4];
1675	/** 16 bit unsigned integer view. */
1676	uint16_t au16[2];
1677	/** 32 bit unsigned integer view. */
1678	uint32_t au32[1];
1679	} X86PDE;
1680	/** Pointer to a page directory entry. */
1681	typedef X86PDE *PX86PDE;
1682	/** Pointer to a const page directory entry. */
1683	typedef const X86PDE *PCX86PDE;
1684
1685	/**
1686	* PAE page directory entry.
1687	*/
1688	typedef union X86PDEPAE
1689	{
1690	/** Unsigned integer view. */
1691	X86PGPAEUINT u;
1692	/** Normal view. */
1693	X86PDEPAEBITS n;
1694	/** 2MB page view (big). */
1695	X86PDE2MPAEBITS b;
1696	/** 8 bit unsigned integer view. */
1697	uint8_t au8[8];
1698	/** 16 bit unsigned integer view. */
1699	uint16_t au16[4];
1700	/** 32 bit unsigned integer view. */
1701	uint32_t au32[2];
1702	} X86PDEPAE;
1703	/** Pointer to a page directory entry. */
1704	typedef X86PDEPAE *PX86PDEPAE;
1705	/** Pointer to a const page directory entry. */
1706	typedef const X86PDEPAE *PCX86PDEPAE;
1707
1708	/**
1709	* Page directory.
1710	*/
1711	typedef struct X86PD
1712	{
1713	/** PDE Array. */
1714	X86PDE a[X86_PG_ENTRIES];
1715	} X86PD;
1716	/** Pointer to a page directory. */
1717	typedef X86PD *PX86PD;
1718	/** Pointer to a const page directory. */
1719	typedef const X86PD *PCX86PD;
1720
1721	/** The page shift to get the PD index. */
1722	#define X86_PD_SHIFT 22
1723	/** The PD index mask (apply to a shifted page address). */
1724	#define X86_PD_MASK 0x3ff
1725
1726
1727	/**
1728	* PAE page directory.
1729	*/
1730	typedef struct X86PDPAE
1731	{
1732	/** PDE Array. */
1733	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1734	} X86PDPAE;
1735	/** Pointer to a PAE page directory. */
1736	typedef X86PDPAE *PX86PDPAE;
1737	/** Pointer to a const PAE page directory. */
1738	typedef const X86PDPAE *PCX86PDPAE;
1739
1740	/** The page shift to get the PAE PD index. */
1741	#define X86_PD_PAE_SHIFT 21
1742	/** The PAE PD index mask (apply to a shifted page address). */
1743	#define X86_PD_PAE_MASK 0x1ff
1744
1745
1746	/** @name Page Directory Pointer Table Entry (PAE)
1747	* @{
1748	*/
1749	/** Bit 0 - P - Present bit. */
1750	#define X86_PDPE_P RT_BIT(0)
1751	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1752	#define X86_PDPE_RW RT_BIT(1)
1753	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1754	#define X86_PDPE_US RT_BIT(2)
1755	/** Bit 3 - PWT - Page level write thru bit. */
1756	#define X86_PDPE_PWT RT_BIT(3)
1757	/** Bit 4 - PCD - Page level cache disable bit. */
1758	#define X86_PDPE_PCD RT_BIT(4)
1759	/** Bit 5 - A - Access bit. Long Mode only. */
1760	#define X86_PDPE_A RT_BIT(5)
1761	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1762	#define X86_PDPE_LM_PS RT_BIT(7)
1763	/** Bits 9-11 - - Available for use to system software. */
1764	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1765	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1766	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1767	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1768	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1769	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1770	#define X86_PDPE_LM_NX RT_BIT_64(63)
1771	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1772	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1773	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1774	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1775	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1776	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1777	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1778	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1779
1780
1781	/**
1782	* Page directory pointer table entry.
1783	*/
1784	typedef struct X86PDPEBITS
1785	{
1786	/** Flags whether(=1) or not the page is present. */
1787	uint32_t u1Present : 1;
1788	/** Chunk of reserved bits. */
1789	uint32_t u2Reserved : 2;
1790	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1791	uint32_t u1WriteThru : 1;
1792	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1793	uint32_t u1CacheDisable : 1;
1794	/** Chunk of reserved bits. */
1795	uint32_t u4Reserved : 4;
1796	/** Available for use to system software. */
1797	uint32_t u3Available : 3;
1798	/** Physical Page number of the next level - Low Part. Don't use! */
1799	uint32_t u20PageNoLow : 20;
1800	/** Physical Page number of the next level - High Part. Don't use! */
1801	uint32_t u20PageNoHigh : 20;
1802	/** MBZ bits */
1803	uint32_t u12Reserved : 12;
1804	} X86PDPEBITS;
1805	/** Pointer to a page directory pointer table entry. */
1806	typedef X86PDPEBITS *PX86PTPEBITS;
1807	/** Pointer to a const page directory pointer table entry. */
1808	typedef const X86PDPEBITS *PCX86PTPEBITS;
1809
1810	/**
1811	* Page directory pointer table entry. AMD64 version
1812	*/
1813	typedef struct X86PDPEAMD64BITS
1814	{
1815	/** Flags whether(=1) or not the page is present. */
1816	uint32_t u1Present : 1;
1817	/** Read(=0) / Write(=1) flag. */
1818	uint32_t u1Write : 1;
1819	/** User(=1) / Supervisor (=0) flag. */
1820	uint32_t u1User : 1;
1821	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1822	uint32_t u1WriteThru : 1;
1823	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1824	uint32_t u1CacheDisable : 1;
1825	/** Accessed flag.
1826	* Indicates that the page have been read or written to. */
1827	uint32_t u1Accessed : 1;
1828	/** Chunk of reserved bits. */
1829	uint32_t u3Reserved : 3;
1830	/** Available for use to system software. */
1831	uint32_t u3Available : 3;
1832	/** Physical Page number of the next level - Low Part. Don't use! */
1833	uint32_t u20PageNoLow : 20;
1834	/** Physical Page number of the next level - High Part. Don't use! */
1835	uint32_t u20PageNoHigh : 20;
1836	/** MBZ bits */
1837	uint32_t u11Reserved : 11;
1838	/** No Execute flag. */
1839	uint32_t u1NoExecute : 1;
1840	} X86PDPEAMD64BITS;
1841	/** Pointer to a page directory pointer table entry. */
1842	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1843	/** Pointer to a const page directory pointer table entry. */
1844	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
1845
1846	/**
1847	* Page directory pointer table entry.
1848	*/
1849	typedef union X86PDPE
1850	{
1851	/** Unsigned integer view. */
1852	X86PGPAEUINT u;
1853	/** Normal view. */
1854	X86PDPEBITS n;
1855	/** AMD64 view. */
1856	X86PDPEAMD64BITS lm;
1857	/** 8 bit unsigned integer view. */
1858	uint8_t au8[8];
1859	/** 16 bit unsigned integer view. */
1860	uint16_t au16[4];
1861	/** 32 bit unsigned integer view. */
1862	uint32_t au32[2];
1863	} X86PDPE;
1864	/** Pointer to a page directory pointer table entry. */
1865	typedef X86PDPE *PX86PDPE;
1866	/** Pointer to a const page directory pointer table entry. */
1867	typedef const X86PDPE *PCX86PDPE;
1868
1869
1870	/**
1871	* Page directory pointer table.
1872	*/
1873	typedef struct X86PDPT
1874	{
1875	/** PDE Array. */
1876	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1877	} X86PDPT;
1878	/** Pointer to a page directory pointer table. */
1879	typedef X86PDPT *PX86PDPT;
1880	/** Pointer to a const page directory pointer table. */
1881	typedef const X86PDPT *PCX86PDPT;
1882
1883	/** The page shift to get the PDPT index. */
1884	#define X86_PDPT_SHIFT 30
1885	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1886	#define X86_PDPT_MASK_PAE 0x3
1887	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1888	#define X86_PDPT_MASK_AMD64 0x1ff
1889
1890	/** @} */
1891
1892
1893	/** @name Page Map Level-4 Entry (Long Mode PAE)
1894	* @{
1895	*/
1896	/** Bit 0 - P - Present bit. */
1897	#define X86_PML4E_P RT_BIT(0)
1898	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1899	#define X86_PML4E_RW RT_BIT(1)
1900	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1901	#define X86_PML4E_US RT_BIT(2)
1902	/** Bit 3 - PWT - Page level write thru bit. */
1903	#define X86_PML4E_PWT RT_BIT(3)
1904	/** Bit 4 - PCD - Page level cache disable bit. */
1905	#define X86_PML4E_PCD RT_BIT(4)
1906	/** Bit 5 - A - Access bit. */
1907	#define X86_PML4E_A RT_BIT(5)
1908	/** Bits 9-11 - - Available for use to system software. */
1909	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1910	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1911	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
1912	/** Bits 8, 7 - - MBZ bits when NX is active. */
1913	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1914	/** Bits 63, 7 - - MBZ bits when no NX. */
1915	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1916	/** Bits 63 - NX - PAE - No execution flag. */
1917	#define X86_PML4E_NX RT_BIT_64(63)
1918
1919	/**
1920	* Page Map Level-4 Entry
1921	*/
1922	typedef struct X86PML4EBITS
1923	{
1924	/** Flags whether(=1) or not the page is present. */
1925	uint32_t u1Present : 1;
1926	/** Read(=0) / Write(=1) flag. */
1927	uint32_t u1Write : 1;
1928	/** User(=1) / Supervisor (=0) flag. */
1929	uint32_t u1User : 1;
1930	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1931	uint32_t u1WriteThru : 1;
1932	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1933	uint32_t u1CacheDisable : 1;
1934	/** Accessed flag.
1935	* Indicates that the page have been read or written to. */
1936	uint32_t u1Accessed : 1;
1937	/** Chunk of reserved bits. */
1938	uint32_t u3Reserved : 3;
1939	/** Available for use to system software. */
1940	uint32_t u3Available : 3;
1941	/** Physical Page number of the next level - Low Part. Don't use! */
1942	uint32_t u20PageNoLow : 20;
1943	/** Physical Page number of the next level - High Part. Don't use! */
1944	uint32_t u20PageNoHigh : 20;
1945	/** MBZ bits */
1946	uint32_t u11Reserved : 11;
1947	/** No Execute flag. */
1948	uint32_t u1NoExecute : 1;
1949	} X86PML4EBITS;
1950	/** Pointer to a page map level-4 entry. */
1951	typedef X86PML4EBITS *PX86PML4EBITS;
1952	/** Pointer to a const page map level-4 entry. */
1953	typedef const X86PML4EBITS *PCX86PML4EBITS;
1954
1955	/**
1956	* Page Map Level-4 Entry.
1957	*/
1958	typedef union X86PML4E
1959	{
1960	/** Unsigned integer view. */
1961	X86PGPAEUINT u;
1962	/** Normal view. */
1963	X86PML4EBITS n;
1964	/** 8 bit unsigned integer view. */
1965	uint8_t au8[8];
1966	/** 16 bit unsigned integer view. */
1967	uint16_t au16[4];
1968	/** 32 bit unsigned integer view. */
1969	uint32_t au32[2];
1970	} X86PML4E;
1971	/** Pointer to a page map level-4 entry. */
1972	typedef X86PML4E *PX86PML4E;
1973	/** Pointer to a const page map level-4 entry. */
1974	typedef const X86PML4E *PCX86PML4E;
1975
1976
1977	/**
1978	* Page Map Level-4.
1979	*/
1980	typedef struct X86PML4
1981	{
1982	/** PDE Array. */
1983	X86PML4E a[X86_PG_PAE_ENTRIES];
1984	} X86PML4;
1985	/** Pointer to a page map level-4. */
1986	typedef X86PML4 *PX86PML4;
1987	/** Pointer to a const page map level-4. */
1988	typedef const X86PML4 *PCX86PML4;
1989
1990	/** The page shift to get the PML4 index. */
1991	#define X86_PML4_SHIFT 39
1992	/** The PML4 index mask (apply to a shifted page address). */
1993	#define X86_PML4_MASK 0x1ff
1994
1995	/** @} */
1996
1997	/** @} */
1998
1999
2000	/**
2001	* 80-bit MMX/FPU register type.
2002	*/
2003	typedef struct X86FPUMMX
2004	{
2005	uint8_t reg[10];
2006	} X86FPUMMX;
2007	/** Pointer to a 80-bit MMX/FPU register type. */
2008	typedef X86FPUMMX *PX86FPUMMX;
2009	/** Pointer to a const 80-bit MMX/FPU register type. */
2010	typedef const X86FPUMMX *PCX86FPUMMX;
2011
2012	/**
2013	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2014	* @todo verify this...
2015	*/
2016	#pragma pack(1)
2017	typedef struct X86FPUSTATE
2018	{
2019	/** 0x00 - Control word. */
2020	uint16_t FCW;
2021	/** 0x02 - Alignment word */
2022	uint16_t Dummy1;
2023	/** 0x04 - Status word. */
2024	uint16_t FSW;
2025	/** 0x06 - Alignment word */
2026	uint16_t Dummy2;
2027	/** 0x08 - Tag word */
2028	uint16_t FTW;
2029	/** 0x0a - Alignment word */
2030	uint16_t Dummy3;
2031
2032	/** 0x0c - Instruction pointer. */
2033	uint32_t FPUIP;
2034	/** 0x10 - Code selector. */
2035	uint16_t CS;
2036	/** 0x12 - Opcode. */
2037	uint16_t FOP;
2038	/** 0x14 - FOO. */
2039	uint32_t FPUOO;
2040	/** 0x18 - FOS. */
2041	uint32_t FPUOS;
2042	/** 0x1c */
2043	union
2044	{
2045	/** MMX view. */
2046	uint64_t mmx;
2047	/** FPU view - todo. */
2048	X86FPUMMX fpu;
2049	/** Extended precision floating point view. */
2050	RTFLOAT80U r80;
2051	/** Extended precision floating point view v2. */
2052	RTFLOAT80U2 r80Ex;
2053	/** 8-bit view. */
2054	uint8_t au8[16];
2055	/** 16-bit view. */
2056	uint16_t au16[8];
2057	/** 32-bit view. */
2058	uint32_t au32[4];
2059	/** 64-bit view. */
2060	uint64_t au64[2];
2061	/** 128-bit view. (yeah, very helpful) */
2062	uint128_t au128[1];
2063	} regs[8];
2064	} X86FPUSTATE;
2065	#pragma pack()
2066	/** Pointer to a FPU state. */
2067	typedef X86FPUSTATE *PX86FPUSTATE;
2068	/** Pointer to a const FPU state. */
2069	typedef const X86FPUSTATE *PCX86FPUSTATE;
2070
2071	/**
2072	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2073	*/
2074	#pragma pack(1)
2075	typedef struct X86FXSTATE
2076	{
2077	/** 0x00 - Control word. */
2078	uint16_t FCW;
2079	/** 0x02 - Status word. */
2080	uint16_t FSW;
2081	/** 0x04 - Tag word. (The upper byte is always zero.) */
2082	uint16_t FTW;
2083	/** 0x06 - Opcode. */
2084	uint16_t FOP;
2085	/** 0x08 - Instruction pointer. */
2086	uint32_t FPUIP;
2087	/** 0x0c - Code selector. */
2088	uint16_t CS;
2089	uint16_t Rsrvd1;
2090	/** 0x10 - Data pointer. */
2091	uint32_t FPUDP;
2092	/** 0x14 - Data segment */
2093	uint16_t DS;
2094	/** 0x16 */
2095	uint16_t Rsrvd2;
2096	/** 0x18 */
2097	uint32_t MXCSR;
2098	/** 0x1c */
2099	uint32_t MXCSR_MASK;
2100	/** 0x20 */
2101	union
2102	{
2103	/** MMX view. */
2104	uint64_t mmx;
2105	/** FPU view - todo. */
2106	X86FPUMMX fpu;
2107	/** Extended precision floating point view. */
2108	RTFLOAT80U r80;
2109	/** Extended precision floating point view v2 */
2110	RTFLOAT80U2 r80Ex;
2111	/** 8-bit view. */
2112	uint8_t au8[16];
2113	/** 16-bit view. */
2114	uint16_t au16[8];
2115	/** 32-bit view. */
2116	uint32_t au32[4];
2117	/** 64-bit view. */
2118	uint64_t au64[2];
2119	/** 128-bit view. (yeah, very helpful) */
2120	uint128_t au128[1];
2121	} aRegs[8];
2122	/* - offset 160 - */
2123	union
2124	{
2125	/** XMM Register view . /
2126	uint128_t xmm;
2127	/** 8-bit view. */
2128	uint8_t au8[16];
2129	/** 16-bit view. */
2130	uint16_t au16[8];
2131	/** 32-bit view. */
2132	uint32_t au32[4];
2133	/** 64-bit view. */
2134	uint64_t au64[2];
2135	/** 128-bit view. (yeah, very helpful) */
2136	uint128_t au128[1];
2137	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2138	/* - offset 416 - */
2139	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
2140	} X86FXSTATE;
2141	#pragma pack()
2142	/** Pointer to a FPU Extended state. */
2143	typedef X86FXSTATE *PX86FXSTATE;
2144	/** Pointer to a const FPU Extended state. */
2145	typedef const X86FXSTATE *PCX86FXSTATE;
2146
2147	/** @name FPU status word flags.
2148	* @{ */
2149	/** Exception Flag: Invalid operation. */
2150	#define X86_FSW_IE RT_BIT(0)
2151	/** Exception Flag: Denormalized operand. */
2152	#define X86_FSW_DE RT_BIT(1)
2153	/** Exception Flag: Zero divide. */
2154	#define X86_FSW_ZE RT_BIT(2)
2155	/** Exception Flag: Overflow. */
2156	#define X86_FSW_OE RT_BIT(3)
2157	/** Exception Flag: Underflow. */
2158	#define X86_FSW_UE RT_BIT(4)
2159	/** Exception Flag: Precision. */
2160	#define X86_FSW_PE RT_BIT(5)
2161	/** Stack fault. */
2162	#define X86_FSW_SF RT_BIT(6)
2163	/** Error summary status. */
2164	#define X86_FSW_ES RT_BIT(7)
2165	/** Mask of exceptions flags, excluding the summary bit. */
2166	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2167	/** Mask of exceptions flags, including the summary bit. */
2168	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2169	/** Condition code 0. */
2170	#define X86_FSW_C0 RT_BIT(8)
2171	/** Condition code 1. */
2172	#define X86_FSW_C1 RT_BIT(9)
2173	/** Condition code 2. */
2174	#define X86_FSW_C2 RT_BIT(10)
2175	/** Top of the stack mask. */
2176	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2177	/** TOP shift value. */
2178	#define X86_FSW_TOP_SHIFT 11
2179	/** Mask for getting TOP value after shifting it right. */
2180	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2181	/** Get the TOP value. */
2182	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2183	/** Condition code 3. */
2184	#define X86_FSW_C3 RT_BIT(14)
2185	/** Mask of exceptions flags, including the summary bit. */
2186	#define X86_FSW_C_MASK UINT16_C(0x4700)
2187	/** FPU busy. */
2188	#define X86_FSW_B RT_BIT(15)
2189	/** @} */
2190
2191
2192	/** @name FPU control word flags.
2193	* @{ */
2194	/** Exception Mask: Invalid operation. */
2195	#define X86_FCW_IM RT_BIT(0)
2196	/** Exception Mask: Denormalized operand. */
2197	#define X86_FCW_DM RT_BIT(1)
2198	/** Exception Mask: Zero divide. */
2199	#define X86_FCW_ZM RT_BIT(2)
2200	/** Exception Mask: Overflow. */
2201	#define X86_FCW_OM RT_BIT(3)
2202	/** Exception Mask: Underflow. */
2203	#define X86_FCW_UM RT_BIT(4)
2204	/** Exception Mask: Precision. */
2205	#define X86_FCW_PM RT_BIT(5)
2206	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2207	* @remarks This includes reserved bit 6. */
2208	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2209	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2210	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2211	/** Precision control mask. */
2212	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2213	/** Precision control: 24-bit. */
2214	#define X86_FCW_PC_24 UINT16_C(0x0000)
2215	/** Precision control: Reserved. */
2216	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2217	/** Precision control: 53-bit. */
2218	#define X86_FCW_PC_53 UINT16_C(0x0200)
2219	/** Precision control: 64-bit. */
2220	#define X86_FCW_PC_64 UINT16_C(0x0300)
2221	/** Rounding control mask. */
2222	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2223	/** Rounding control: To nearest. */
2224	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2225	/** Rounding control: Down. */
2226	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2227	/** Rounding control: Up. */
2228	#define X86_FCW_RC_UP UINT16_C(0x0800)
2229	/** Rounding control: Towards zero. */
2230	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2231	/** Bits which should be zero, apparently. */
2232	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2233	/** @} */
2234
2235
2236	/** @name Selector Descriptor
2237	* @{
2238	*/
2239
2240	#ifndef VBOX_FOR_DTRACE_LIB
2241	/**
2242	* Descriptor attributes (as seen by VT-x).
2243	*/
2244	typedef struct X86DESCATTRBITS
2245	{
2246	/** 00 - Segment Type. */
2247	unsigned u4Type : 4;
2248	/** 04 - Descriptor Type. System(=0) or code/data selector */
2249	unsigned u1DescType : 1;
2250	/** 05 - Descriptor Privelege level. */
2251	unsigned u2Dpl : 2;
2252	/** 07 - Flags selector present(=1) or not. */
2253	unsigned u1Present : 1;
2254	/** 08 - Segment limit 16-19. */
2255	unsigned u4LimitHigh : 4;
2256	/** 0c - Available for system software. */
2257	unsigned u1Available : 1;
2258	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2259	unsigned u1Long : 1;
2260	/** 0e - This flags meaning depends on the segment type. Try make sense out
2261	* of the intel manual yourself. */
2262	unsigned u1DefBig : 1;
2263	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2264	* clear byte. */
2265	unsigned u1Granularity : 1;
2266	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
2267	unsigned u1Unusable : 1;
2268	} X86DESCATTRBITS;
2269	#endif /* !VBOX_FOR_DTRACE_LIB */
2270
2271	/** @name X86DESCATTR masks
2272	* @{ */
2273	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
2274	#define X86DESCATTR_DT UINT32_C(0x00000010)
2275	#define X86DESCATTR_DPL UINT32_C(0x00000060)
2276	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
2277	#define X86DESCATTR_P UINT32_C(0x00000800)
2278	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
2279	#define X86DESCATTR_AVL UINT32_C(0x00001000)
2280	#define X86DESCATTR_L UINT32_C(0x00002000)
2281	#define X86DESCATTR_D UINT32_C(0x00004000)
2282	#define X86DESCATTR_G UINT32_C(0x00008000)
2283	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
2284	/** @} */
2285
2286	#pragma pack(1)
2287	typedef union X86DESCATTR
2288	{
2289	/** Unsigned integer view. */
2290	uint32_t u;
2291	#ifndef VBOX_FOR_DTRACE_LIB
2292	/** Normal view. */
2293	X86DESCATTRBITS n;
2294	#endif
2295	} X86DESCATTR;
2296	#pragma pack()
2297	/** Pointer to descriptor attributes. */
2298	typedef X86DESCATTR *PX86DESCATTR;
2299	/** Pointer to const descriptor attributes. */
2300	typedef const X86DESCATTR *PCX86DESCATTR;
2301
2302	#ifndef VBOX_FOR_DTRACE_LIB
2303
2304	/**
2305	* Generic descriptor table entry
2306	*/
2307	#pragma pack(1)
2308	typedef struct X86DESCGENERIC
2309	{
2310	/** 00 - Limit - Low word. */
2311	unsigned u16LimitLow : 16;
2312	/** 10 - Base address - lowe word.
2313	* Don't try set this to 24 because MSC is doing stupid things then. */
2314	unsigned u16BaseLow : 16;
2315	/** 20 - Base address - first 8 bits of high word. */
2316	unsigned u8BaseHigh1 : 8;
2317	/** 28 - Segment Type. */
2318	unsigned u4Type : 4;
2319	/** 2c - Descriptor Type. System(=0) or code/data selector */
2320	unsigned u1DescType : 1;
2321	/** 2d - Descriptor Privelege level. */
2322	unsigned u2Dpl : 2;
2323	/** 2f - Flags selector present(=1) or not. */
2324	unsigned u1Present : 1;
2325	/** 30 - Segment limit 16-19. */
2326	unsigned u4LimitHigh : 4;
2327	/** 34 - Available for system software. */
2328	unsigned u1Available : 1;
2329	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2330	unsigned u1Long : 1;
2331	/** 36 - This flags meaning depends on the segment type. Try make sense out
2332	* of the intel manual yourself. */
2333	unsigned u1DefBig : 1;
2334	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
2335	* clear byte. */
2336	unsigned u1Granularity : 1;
2337	/** 38 - Base address - highest 8 bits. */
2338	unsigned u8BaseHigh2 : 8;
2339	} X86DESCGENERIC;
2340	#pragma pack()
2341	/** Pointer to a generic descriptor entry. */
2342	typedef X86DESCGENERIC *PX86DESCGENERIC;
2343	/** Pointer to a const generic descriptor entry. */
2344	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2345
2346	/** @name Bit offsets of X86DESCGENERIC members.
2347	* @{*/
2348	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
2349	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
2350	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
2351	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
2352	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
2353	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
2354	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
2355	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
2356	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
2357	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
2358	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
2359	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
2360	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
2361	/** @} */
2362
2363	/**
2364	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2365	*/
2366	typedef struct X86DESCGATE
2367	{
2368	/** 00 - Target code segment offset - Low word.
2369	* Ignored if task-gate. */
2370	unsigned u16OffsetLow : 16;
2371	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2372	* TSS selector if task-gate. */
2373	unsigned u16Sel : 16;
2374	/** 20 - Number of parameters for a call-gate.
2375	* Ignored if interrupt-, trap- or task-gate. */
2376	unsigned u4ParmCount : 4;
2377	/** 24 - Reserved / ignored. */
2378	unsigned u4Reserved : 4;
2379	/** 28 - Segment Type. */
2380	unsigned u4Type : 4;
2381	/** 2c - Descriptor Type (0 = system). */
2382	unsigned u1DescType : 1;
2383	/** 2d - Descriptor Privelege level. */
2384	unsigned u2Dpl : 2;
2385	/** 2f - Flags selector present(=1) or not. */
2386	unsigned u1Present : 1;
2387	/** 30 - Target code segment offset - High word.
2388	* Ignored if task-gate. */
2389	unsigned u16OffsetHigh : 16;
2390	} X86DESCGATE;
2391	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2392	typedef X86DESCGATE *PX86DESCGATE;
2393	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2394	typedef const X86DESCGATE *PCX86DESCGATE;
2395
2396	#endif /* VBOX_FOR_DTRACE_LIB */
2397
2398	/**
2399	* Descriptor table entry.
2400	*/
2401	#pragma pack(1)
2402	typedef union X86DESC
2403	{
2404	#ifndef VBOX_FOR_DTRACE_LIB
2405	/** Generic descriptor view. */
2406	X86DESCGENERIC Gen;
2407	/** Gate descriptor view. */
2408	X86DESCGATE Gate;
2409	#endif
2410
2411	/** 8 bit unsigned integer view. */
2412	uint8_t au8[8];
2413	/** 16 bit unsigned integer view. */
2414	uint16_t au16[4];
2415	/** 32 bit unsigned integer view. */
2416	uint32_t au32[2];
2417	/** 64 bit unsigned integer view. */
2418	uint64_t au64[1];
2419	/** Unsigned integer view. */
2420	uint64_t u;
2421	} X86DESC;
2422	#ifndef VBOX_FOR_DTRACE_LIB
2423	AssertCompileSize(X86DESC, 8);
2424	#endif
2425	#pragma pack()
2426	/** Pointer to descriptor table entry. */
2427	typedef X86DESC *PX86DESC;
2428	/** Pointer to const descriptor table entry. */
2429	typedef const X86DESC *PCX86DESC;
2430
2431	/** @def X86DESC_BASE
2432	* Return the base address of a descriptor.
2433	*/
2434	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
2435	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2436	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2437	\| ( (a_pDesc)->Gen.u16BaseLow ) )
2438
2439	/** @def X86DESC_LIMIT
2440	* Return the limit of a descriptor.
2441	*/
2442	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
2443	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
2444	\| ( (a_pDesc)->Gen.u16LimitLow ) )
2445
2446	/** @def X86DESC_LIMIT_G
2447	* Return the limit of a descriptor with the granularity bit taken into account.
2448	* @returns Selector limit (uint32_t).
2449	* @param a_pDesc Pointer to the descriptor.
2450	*/
2451	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
2452	( (a_pDesc)->Gen.u1Granularity \
2453	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
2454	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
2455	)
2456
2457	/** @def X86DESC_GET_HID_ATTR
2458	* Get the descriptor attributes for the hidden register.
2459	*/
2460	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
2461	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
2462
2463	#ifndef VBOX_FOR_DTRACE_LIB
2464
2465	/**
2466	* 64 bits generic descriptor table entry
2467	* Note: most of these bits have no meaning in long mode.
2468	*/
2469	#pragma pack(1)
2470	typedef struct X86DESC64GENERIC
2471	{
2472	/** Limit - Low word - IGNORED. */
2473	unsigned u16LimitLow : 16;
2474	/** Base address - low word. - IGNORED
2475	* Don't try set this to 24 because MSC is doing stupid things then. */
2476	unsigned u16BaseLow : 16;
2477	/** Base address - first 8 bits of high word. - IGNORED */
2478	unsigned u8BaseHigh1 : 8;
2479	/** Segment Type. */
2480	unsigned u4Type : 4;
2481	/** Descriptor Type. System(=0) or code/data selector */
2482	unsigned u1DescType : 1;
2483	/** Descriptor Privelege level. */
2484	unsigned u2Dpl : 2;
2485	/** Flags selector present(=1) or not. */
2486	unsigned u1Present : 1;
2487	/** Segment limit 16-19. - IGNORED */
2488	unsigned u4LimitHigh : 4;
2489	/** Available for system software. - IGNORED */
2490	unsigned u1Available : 1;
2491	/** Long mode flag. */
2492	unsigned u1Long : 1;
2493	/** This flags meaning depends on the segment type. Try make sense out
2494	* of the intel manual yourself. */
2495	unsigned u1DefBig : 1;
2496	/** Granularity of the limit. If set 4KB granularity is used, if
2497	* clear byte. - IGNORED */
2498	unsigned u1Granularity : 1;
2499	/** Base address - highest 8 bits. - IGNORED */
2500	unsigned u8BaseHigh2 : 8;
2501	/** Base address - bits 63-32. */
2502	unsigned u32BaseHigh3 : 32;
2503	unsigned u8Reserved : 8;
2504	unsigned u5Zeros : 5;
2505	unsigned u19Reserved : 19;
2506	} X86DESC64GENERIC;
2507	#pragma pack()
2508	/** Pointer to a generic descriptor entry. */
2509	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2510	/** Pointer to a const generic descriptor entry. */
2511	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2512
2513	/**
2514	* System descriptor table entry (64 bits)
2515	*
2516	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2517	*/
2518	#pragma pack(1)
2519	typedef struct X86DESC64SYSTEM
2520	{
2521	/** Limit - Low word. */
2522	unsigned u16LimitLow : 16;
2523	/** Base address - lowe word.
2524	* Don't try set this to 24 because MSC is doing stupid things then. */
2525	unsigned u16BaseLow : 16;
2526	/** Base address - first 8 bits of high word. */
2527	unsigned u8BaseHigh1 : 8;
2528	/** Segment Type. */
2529	unsigned u4Type : 4;
2530	/** Descriptor Type. System(=0) or code/data selector */
2531	unsigned u1DescType : 1;
2532	/** Descriptor Privelege level. */
2533	unsigned u2Dpl : 2;
2534	/** Flags selector present(=1) or not. */
2535	unsigned u1Present : 1;
2536	/** Segment limit 16-19. */
2537	unsigned u4LimitHigh : 4;
2538	/** Available for system software. */
2539	unsigned u1Available : 1;
2540	/** Reserved - 0. */
2541	unsigned u1Reserved : 1;
2542	/** This flags meaning depends on the segment type. Try make sense out
2543	* of the intel manual yourself. */
2544	unsigned u1DefBig : 1;
2545	/** Granularity of the limit. If set 4KB granularity is used, if
2546	* clear byte. */
2547	unsigned u1Granularity : 1;
2548	/** Base address - bits 31-24. */
2549	unsigned u8BaseHigh2 : 8;
2550	/** Base address - bits 63-32. */
2551	unsigned u32BaseHigh3 : 32;
2552	unsigned u8Reserved : 8;
2553	unsigned u5Zeros : 5;
2554	unsigned u19Reserved : 19;
2555	} X86DESC64SYSTEM;
2556	#pragma pack()
2557	/** Pointer to a system descriptor entry. */
2558	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2559	/** Pointer to a const system descriptor entry. */
2560	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2561
2562	/**
2563	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2564	*/
2565	typedef struct X86DESC64GATE
2566	{
2567	/** Target code segment offset - Low word. */
2568	unsigned u16OffsetLow : 16;
2569	/** Target code segment selector. */
2570	unsigned u16Sel : 16;
2571	/** Interrupt stack table for interrupt- and trap-gates.
2572	* Ignored by call-gates. */
2573	unsigned u3IST : 3;
2574	/** Reserved / ignored. */
2575	unsigned u5Reserved : 5;
2576	/** Segment Type. */
2577	unsigned u4Type : 4;
2578	/** Descriptor Type (0 = system). */
2579	unsigned u1DescType : 1;
2580	/** Descriptor Privelege level. */
2581	unsigned u2Dpl : 2;
2582	/** Flags selector present(=1) or not. */
2583	unsigned u1Present : 1;
2584	/** Target code segment offset - High word.
2585	* Ignored if task-gate. */
2586	unsigned u16OffsetHigh : 16;
2587	/** Target code segment offset - Top dword.
2588	* Ignored if task-gate. */
2589	unsigned u32OffsetTop : 32;
2590	/** Reserved / ignored / must be zero.
2591	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2592	unsigned u32Reserved : 32;
2593	} X86DESC64GATE;
2594	AssertCompileSize(X86DESC64GATE, 16);
2595	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2596	typedef X86DESC64GATE *PX86DESC64GATE;
2597	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2598	typedef const X86DESC64GATE *PCX86DESC64GATE;
2599
2600	#endif /* VBOX_FOR_DTRACE_LIB */
2601
2602	/**
2603	* Descriptor table entry.
2604	*/
2605	#pragma pack(1)
2606	typedef union X86DESC64
2607	{
2608	#ifndef VBOX_FOR_DTRACE_LIB
2609	/** Generic descriptor view. */
2610	X86DESC64GENERIC Gen;
2611	/** System descriptor view. */
2612	X86DESC64SYSTEM System;
2613	/** Gate descriptor view. */
2614	X86DESC64GATE Gate;
2615	#endif
2616
2617	/** 8 bit unsigned integer view. */
2618	uint8_t au8[16];
2619	/** 16 bit unsigned integer view. */
2620	uint16_t au16[8];
2621	/** 32 bit unsigned integer view. */
2622	uint32_t au32[4];
2623	/** 64 bit unsigned integer view. */
2624	uint64_t au64[2];
2625	} X86DESC64;
2626	#ifndef VBOX_FOR_DTRACE_LIB
2627	AssertCompileSize(X86DESC64, 16);
2628	#endif
2629	#pragma pack()
2630	/** Pointer to descriptor table entry. */
2631	typedef X86DESC64 *PX86DESC64;
2632	/** Pointer to const descriptor table entry. */
2633	typedef const X86DESC64 *PCX86DESC64;
2634
2635	/** @def X86DESC64_BASE
2636	* Return the base of a 64-bit descriptor.
2637	*/
2638	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
2639	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
2640	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2641	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2642	\| ( (a_pDesc)->Gen.u16BaseLow ) )
2643
2644
2645
2646	/** @name Host system descriptor table entry - Use with care!
2647	* @{ */
2648	/** Host system descriptor table entry. */
2649	#if HC_ARCH_BITS == 64
2650	typedef X86DESC64 X86DESCHC;
2651	#else
2652	typedef X86DESC X86DESCHC;
2653	#endif
2654	/** Pointer to a host system descriptor table entry. */
2655	#if HC_ARCH_BITS == 64
2656	typedef PX86DESC64 PX86DESCHC;
2657	#else
2658	typedef PX86DESC PX86DESCHC;
2659	#endif
2660	/** Pointer to a const host system descriptor table entry. */
2661	#if HC_ARCH_BITS == 64
2662	typedef PCX86DESC64 PCX86DESCHC;
2663	#else
2664	typedef PCX86DESC PCX86DESCHC;
2665	#endif
2666	/** @} */
2667
2668
2669	/** @name Selector Descriptor Types.
2670	* @{
2671	*/
2672
2673	/** @name Non-System Selector Types.
2674	* @{ */
2675	/** Code(=set)/Data(=clear) bit. */
2676	#define X86_SEL_TYPE_CODE 8
2677	/** Memory(=set)/System(=clear) bit. */
2678	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2679	/** Accessed bit. */
2680	#define X86_SEL_TYPE_ACCESSED 1
2681	/** Expand down bit (for data selectors only). */
2682	#define X86_SEL_TYPE_DOWN 4
2683	/** Conforming bit (for code selectors only). */
2684	#define X86_SEL_TYPE_CONF 4
2685	/** Write bit (for data selectors only). */
2686	#define X86_SEL_TYPE_WRITE 2
2687	/** Read bit (for code selectors only). */
2688	#define X86_SEL_TYPE_READ 2
2689	/** The bit number of the code segment read bit (relative to u4Type). */
2690	#define X86_SEL_TYPE_READ_BIT 1
2691
2692	/** Read only selector type. */
2693	#define X86_SEL_TYPE_RO 0
2694	/** Accessed read only selector type. */
2695	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2696	/** Read write selector type. */
2697	#define X86_SEL_TYPE_RW 2
2698	/** Accessed read write selector type. */
2699	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2700	/** Expand down read only selector type. */
2701	#define X86_SEL_TYPE_RO_DOWN 4
2702	/** Accessed expand down read only selector type. */
2703	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2704	/** Expand down read write selector type. */
2705	#define X86_SEL_TYPE_RW_DOWN 6
2706	/** Accessed expand down read write selector type. */
2707	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2708	/** Execute only selector type. */
2709	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2710	/** Accessed execute only selector type. */
2711	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2712	/** Execute and read selector type. */
2713	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2714	/** Accessed execute and read selector type. */
2715	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2716	/** Conforming execute only selector type. */
2717	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2718	/** Accessed Conforming execute only selector type. */
2719	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2720	/** Conforming execute and write selector type. */
2721	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2722	/** Accessed Conforming execute and write selector type. */
2723	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2724	/** @} */
2725
2726
2727	/** @name System Selector Types.
2728	* @{ */
2729	/** The TSS busy bit mask. */
2730	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
2731
2732	/** Undefined system selector type. */
2733	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2734	/** 286 TSS selector. */
2735	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2736	/** LDT selector. */
2737	#define X86_SEL_TYPE_SYS_LDT 2
2738	/** 286 TSS selector - Busy. */
2739	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2740	/** 286 Callgate selector. */
2741	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2742	/** Taskgate selector. */
2743	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2744	/** 286 Interrupt gate selector. */
2745	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2746	/** 286 Trapgate selector. */
2747	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2748	/** Undefined system selector. */
2749	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2750	/** 386 TSS selector. */
2751	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2752	/** Undefined system selector. */
2753	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2754	/** 386 TSS selector - Busy. */
2755	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2756	/** 386 Callgate selector. */
2757	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2758	/** Undefined system selector. */
2759	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2760	/** 386 Interruptgate selector. */
2761	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2762	/** 386 Trapgate selector. */
2763	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2764	/** @} */
2765
2766	/** @name AMD64 System Selector Types.
2767	* @{ */
2768	/** LDT selector. */
2769	#define AMD64_SEL_TYPE_SYS_LDT 2
2770	/** TSS selector - Busy. */
2771	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2772	/** TSS selector - Busy. */
2773	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2774	/** Callgate selector. */
2775	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2776	/** Interruptgate selector. */
2777	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2778	/** Trapgate selector. */
2779	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2780	/** @} */
2781
2782	/** @} */
2783
2784
2785	/** @name Descriptor Table Entry Flag Masks.
2786	* These are for the 2nd 32-bit word of a descriptor.
2787	* @{ */
2788	/** Bits 8-11 - TYPE - Descriptor type mask. */
2789	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2790	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2791	#define X86_DESC_S RT_BIT(12)
2792	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2793	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2794	/** Bit 15 - P - Present. */
2795	#define X86_DESC_P RT_BIT(15)
2796	/** Bit 20 - AVL - Available for system software. */
2797	#define X86_DESC_AVL RT_BIT(20)
2798	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2799	#define X86_DESC_DB RT_BIT(22)
2800	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2801	* used, if clear byte. */
2802	#define X86_DESC_G RT_BIT(23)
2803	/** @} */
2804
2805	/** @} */
2806
2807
2808	/** @name Task Segments.
2809	* @{
2810	*/
2811
2812	/**
2813	* 16-bit Task Segment (TSS).
2814	*/
2815	#pragma pack(1)
2816	typedef struct X86TSS16
2817	{
2818	/** Back link to previous task. (static) */
2819	RTSEL selPrev;
2820	/** Ring-0 stack pointer. (static) */
2821	uint16_t sp0;
2822	/** Ring-0 stack segment. (static) */
2823	RTSEL ss0;
2824	/** Ring-1 stack pointer. (static) */
2825	uint16_t sp1;
2826	/** Ring-1 stack segment. (static) */
2827	RTSEL ss1;
2828	/** Ring-2 stack pointer. (static) */
2829	uint16_t sp2;
2830	/** Ring-2 stack segment. (static) */
2831	RTSEL ss2;
2832	/** IP before task switch. */
2833	uint16_t ip;
2834	/** FLAGS before task switch. */
2835	uint16_t flags;
2836	/** AX before task switch. */
2837	uint16_t ax;
2838	/** CX before task switch. */
2839	uint16_t cx;
2840	/** DX before task switch. */
2841	uint16_t dx;
2842	/** BX before task switch. */
2843	uint16_t bx;
2844	/** SP before task switch. */
2845	uint16_t sp;
2846	/** BP before task switch. */
2847	uint16_t bp;
2848	/** SI before task switch. */
2849	uint16_t si;
2850	/** DI before task switch. */
2851	uint16_t di;
2852	/** ES before task switch. */
2853	RTSEL es;
2854	/** CS before task switch. */
2855	RTSEL cs;
2856	/** SS before task switch. */
2857	RTSEL ss;
2858	/** DS before task switch. */
2859	RTSEL ds;
2860	/** LDTR before task switch. */
2861	RTSEL selLdt;
2862	} X86TSS16;
2863	#ifndef VBOX_FOR_DTRACE_LIB
2864	AssertCompileSize(X86TSS16, 44);
2865	#endif
2866	#pragma pack()
2867	/** Pointer to a 16-bit task segment. */
2868	typedef X86TSS16 *PX86TSS16;
2869	/** Pointer to a const 16-bit task segment. */
2870	typedef const X86TSS16 *PCX86TSS16;
2871
2872
2873	/**
2874	* 32-bit Task Segment (TSS).
2875	*/
2876	#pragma pack(1)
2877	typedef struct X86TSS32
2878	{
2879	/** Back link to previous task. (static) */
2880	RTSEL selPrev;
2881	uint16_t padding1;
2882	/** Ring-0 stack pointer. (static) */
2883	uint32_t esp0;
2884	/** Ring-0 stack segment. (static) */
2885	RTSEL ss0;
2886	uint16_t padding_ss0;
2887	/** Ring-1 stack pointer. (static) */
2888	uint32_t esp1;
2889	/** Ring-1 stack segment. (static) */
2890	RTSEL ss1;
2891	uint16_t padding_ss1;
2892	/** Ring-2 stack pointer. (static) */
2893	uint32_t esp2;
2894	/** Ring-2 stack segment. (static) */
2895	RTSEL ss2;
2896	uint16_t padding_ss2;
2897	/** Page directory for the task. (static) */
2898	uint32_t cr3;
2899	/** EIP before task switch. */
2900	uint32_t eip;
2901	/** EFLAGS before task switch. */
2902	uint32_t eflags;
2903	/** EAX before task switch. */
2904	uint32_t eax;
2905	/** ECX before task switch. */
2906	uint32_t ecx;
2907	/** EDX before task switch. */
2908	uint32_t edx;
2909	/** EBX before task switch. */
2910	uint32_t ebx;
2911	/** ESP before task switch. */
2912	uint32_t esp;
2913	/** EBP before task switch. */
2914	uint32_t ebp;
2915	/** ESI before task switch. */
2916	uint32_t esi;
2917	/** EDI before task switch. */
2918	uint32_t edi;
2919	/** ES before task switch. */
2920	RTSEL es;
2921	uint16_t padding_es;
2922	/** CS before task switch. */
2923	RTSEL cs;
2924	uint16_t padding_cs;
2925	/** SS before task switch. */
2926	RTSEL ss;
2927	uint16_t padding_ss;
2928	/** DS before task switch. */
2929	RTSEL ds;
2930	uint16_t padding_ds;
2931	/** FS before task switch. */
2932	RTSEL fs;
2933	uint16_t padding_fs;
2934	/** GS before task switch. */
2935	RTSEL gs;
2936	uint16_t padding_gs;
2937	/** LDTR before task switch. */
2938	RTSEL selLdt;
2939	uint16_t padding_ldt;
2940	/** Debug trap flag */
2941	uint16_t fDebugTrap;
2942	/** Offset relative to the TSS of the start of the I/O Bitmap
2943	* and the end of the interrupt redirection bitmap. */
2944	uint16_t offIoBitmap;
2945	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2946	uint8_t IntRedirBitmap[32];
2947	} X86TSS32;
2948	#pragma pack()
2949	/** Pointer to task segment. */
2950	typedef X86TSS32 *PX86TSS32;
2951	/** Pointer to const task segment. */
2952	typedef const X86TSS32 *PCX86TSS32;
2953
2954
2955	/**
2956	* 64-bit Task segment.
2957	*/
2958	#pragma pack(1)
2959	typedef struct X86TSS64
2960	{
2961	/** Reserved. */
2962	uint32_t u32Reserved;
2963	/** Ring-0 stack pointer. (static) */
2964	uint64_t rsp0;
2965	/** Ring-1 stack pointer. (static) */
2966	uint64_t rsp1;
2967	/** Ring-2 stack pointer. (static) */
2968	uint64_t rsp2;
2969	/** Reserved. */
2970	uint32_t u32Reserved2[2];
2971	/* IST */
2972	uint64_t ist1;
2973	uint64_t ist2;
2974	uint64_t ist3;
2975	uint64_t ist4;
2976	uint64_t ist5;
2977	uint64_t ist6;
2978	uint64_t ist7;
2979	/* Reserved. */
2980	uint16_t u16Reserved[5];
2981	/** Offset relative to the TSS of the start of the I/O Bitmap
2982	* and the end of the interrupt redirection bitmap. */
2983	uint16_t offIoBitmap;
2984	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2985	uint8_t IntRedirBitmap[32];
2986	} X86TSS64;
2987	#pragma pack()
2988	/** Pointer to a 64-bit task segment. */
2989	typedef X86TSS64 *PX86TSS64;
2990	/** Pointer to a const 64-bit task segment. */
2991	typedef const X86TSS64 *PCX86TSS64;
2992	#ifndef VBOX_FOR_DTRACE_LIB
2993	AssertCompileSize(X86TSS64, 136);
2994	#endif
2995
2996	/** @} */
2997
2998
2999	/** @name Selectors.
3000	* @{
3001	*/
3002
3003	/**
3004	* The shift used to convert a selector from and to index an index (C).
3005	*/
3006	#define X86_SEL_SHIFT 3
3007
3008	/**
3009	* The mask used to mask off the table indicator and RPL of an selector.
3010	*/
3011	#define X86_SEL_MASK 0xfff8U
3012
3013	/**
3014	* The mask used to mask off the RPL of an selector.
3015	* This is suitable for checking for NULL selectors.
3016	*/
3017	#define X86_SEL_MASK_OFF_RPL 0xfffcU
3018
3019	/**
3020	* The bit indicating that a selector is in the LDT and not in the GDT.
3021	*/
3022	#define X86_SEL_LDT 0x0004U
3023
3024	/**
3025	* The bit mask for getting the RPL of a selector.
3026	*/
3027	#define X86_SEL_RPL 0x0003U
3028
3029	/**
3030	* The mask covering both RPL and LDT.
3031	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
3032	* checks.
3033	*/
3034	#define X86_SEL_RPL_LDT 0x0007U
3035
3036	/** @} */
3037
3038
3039	/**
3040	* x86 Exceptions/Faults/Traps.
3041	*/
3042	typedef enum X86XCPT
3043	{
3044	/** \#DE - Divide error. */
3045	X86_XCPT_DE = 0x00,
3046	/** \#DB - Debug event (single step, DRx, ..) */
3047	X86_XCPT_DB = 0x01,
3048	/** NMI - Non-Maskable Interrupt */
3049	X86_XCPT_NMI = 0x02,
3050	/** \#BP - Breakpoint (INT3). */
3051	X86_XCPT_BP = 0x03,
3052	/** \#OF - Overflow (INTO). */
3053	X86_XCPT_OF = 0x04,
3054	/** \#BR - Bound range exceeded (BOUND). */
3055	X86_XCPT_BR = 0x05,
3056	/** \#UD - Undefined opcode. */
3057	X86_XCPT_UD = 0x06,
3058	/** \#NM - Device not available (math coprocessor device). */
3059	X86_XCPT_NM = 0x07,
3060	/** \#DF - Double fault. */
3061	X86_XCPT_DF = 0x08,
3062	/** ??? - Coprocessor segment overrun (obsolete). */
3063	X86_XCPT_CO_SEG_OVERRUN = 0x09,
3064	/** \#TS - Taskswitch (TSS). */
3065	X86_XCPT_TS = 0x0a,
3066	/** \#NP - Segment no present. */
3067	X86_XCPT_NP = 0x0b,
3068	/** \#SS - Stack segment fault. */
3069	X86_XCPT_SS = 0x0c,
3070	/** \#GP - General protection fault. */
3071	X86_XCPT_GP = 0x0d,
3072	/** \#PF - Page fault. */
3073	X86_XCPT_PF = 0x0e,
3074	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
3075	/** \#MF - Math fault (FPU). */
3076	X86_XCPT_MF = 0x10,
3077	/** \#AC - Alignment check. */
3078	X86_XCPT_AC = 0x11,
3079	/** \#MC - Machine check. */
3080	X86_XCPT_MC = 0x12,
3081	/** \#XF - SIMD Floating-Pointer Exception. */
3082	X86_XCPT_XF = 0x13,
3083	/** \#VE - Virtualzation Exception. */
3084	X86_XCPT_VE = 0x14,
3085	/** \#SX - Security Exception. */
3086	X86_XCPT_SX = 0x1f
3087	} X86XCPT;
3088	/** Pointer to a x86 exception code. */
3089	typedef X86XCPT *PX86XCPT;
3090	/** Pointer to a const x86 exception code. */
3091	typedef const X86XCPT *PCX86XCPT;
3092	/** The maximum exception value. */
3093	#define X86_XCPT_MAX (X86_XCPT_SX)
3094
3095
3096	/** @name Trap Error Codes
3097	* @{
3098	*/
3099	/** External indicator. */
3100	#define X86_TRAP_ERR_EXTERNAL 1
3101	/** IDT indicator. */
3102	#define X86_TRAP_ERR_IDT 2
3103	/** Descriptor table indicator - If set LDT, if clear GDT. */
3104	#define X86_TRAP_ERR_TI 4
3105	/** Mask for getting the selector. */
3106	#define X86_TRAP_ERR_SEL_MASK 0xfff8
3107	/** Shift for getting the selector table index (C type index). */
3108	#define X86_TRAP_ERR_SEL_SHIFT 3
3109	/** @} */
3110
3111
3112	/** @name \#PF Trap Error Codes
3113	* @{
3114	*/
3115	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3116	#define X86_TRAP_PF_P RT_BIT(0)
3117	/** Bit 1 - R/W - Read (clear) or write (set) access. */
3118	#define X86_TRAP_PF_RW RT_BIT(1)
3119	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3120	#define X86_TRAP_PF_US RT_BIT(2)
3121	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3122	#define X86_TRAP_PF_RSVD RT_BIT(3)
3123	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3124	#define X86_TRAP_PF_ID RT_BIT(4)
3125	/** @} */
3126
3127	#pragma pack(1)
3128	/**
3129	* 32-bit IDTR/GDTR.
3130	*/
3131	typedef struct X86XDTR32
3132	{
3133	/** Size of the descriptor table. */
3134	uint16_t cb;
3135	/** Address of the descriptor table. */
3136	#ifndef VBOX_FOR_DTRACE_LIB
3137	uint32_t uAddr;
3138	#else
3139	uint16_t au16Addr[2];
3140	#endif
3141	} X86XDTR32, *PX86XDTR32;
3142	#pragma pack()
3143
3144	#pragma pack(1)
3145	/**
3146	* 64-bit IDTR/GDTR.
3147	*/
3148	typedef struct X86XDTR64
3149	{
3150	/** Size of the descriptor table. */
3151	uint16_t cb;
3152	/** Address of the descriptor table. */
3153	#ifndef VBOX_FOR_DTRACE_LIB
3154	uint64_t uAddr;
3155	#else
3156	uint16_t au16Addr[4];
3157	#endif
3158	} X86XDTR64, *PX86XDTR64;
3159	#pragma pack()
3160
3161
3162	/** @name ModR/M
3163	* @{ */
3164	#define X86_MODRM_RM_MASK UINT8_C(0x07)
3165	#define X86_MODRM_REG_MASK UINT8_C(0x38)
3166	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3167	#define X86_MODRM_REG_SHIFT 3
3168	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3169	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3170	#define X86_MODRM_MOD_SHIFT 6
3171	#ifndef VBOX_FOR_DTRACE_LIB
3172	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
3173	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3174	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3175	#endif
3176	/** @} */
3177
3178	/** @name SIB
3179	* @{ */
3180	#define X86_SIB_BASE_MASK UINT8_C(0x07)
3181	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3182	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3183	#define X86_SIB_INDEX_SHIFT 3
3184	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3185	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3186	#define X86_SIB_SCALE_SHIFT 6
3187	#ifndef VBOX_FOR_DTRACE_LIB
3188	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
3189	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3190	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3191	#endif
3192	/** @} */
3193
3194	/** @name General register indexes
3195	* @{ */
3196	#define X86_GREG_xAX 0
3197	#define X86_GREG_xCX 1
3198	#define X86_GREG_xDX 2
3199	#define X86_GREG_xBX 3
3200	#define X86_GREG_xSP 4
3201	#define X86_GREG_xBP 5
3202	#define X86_GREG_xSI 6
3203	#define X86_GREG_xDI 7
3204	#define X86_GREG_x8 8
3205	#define X86_GREG_x9 9
3206	#define X86_GREG_x10 10
3207	#define X86_GREG_x11 11
3208	#define X86_GREG_x12 12
3209	#define X86_GREG_x13 13
3210	#define X86_GREG_x14 14
3211	#define X86_GREG_x15 15
3212	/** @} */
3213
3214	/** @name X86_SREG_XXX - Segment register indexes.
3215	* @{ */
3216	#define X86_SREG_ES 0
3217	#define X86_SREG_CS 1
3218	#define X86_SREG_SS 2
3219	#define X86_SREG_DS 3
3220	#define X86_SREG_FS 4
3221	#define X86_SREG_GS 5
3222	/** @} */
3223	/** Segment register count. */
3224	#define X86_SREG_COUNT 6
3225
3226
3227	/** @name X86_OP_XXX - Prefixes
3228	* @{ */
3229	#define X86_OP_PRF_CS UINT8_C(0x2e)
3230	#define X86_OP_PRF_SS UINT8_C(0x36)
3231	#define X86_OP_PRF_DS UINT8_C(0x3e)
3232	#define X86_OP_PRF_ES UINT8_C(0x26)
3233	#define X86_OP_PRF_FS UINT8_C(0x64)
3234	#define X86_OP_PRF_GS UINT8_C(0x65)
3235	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
3236	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
3237	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
3238	#define X86_OP_PRF_REPZ UINT8_C(0xf2)
3239	#define X86_OP_PRF_REPNZ UINT8_C(0xf3)
3240	#define X86_OP_REX_B UINT8_C(0x41)
3241	#define X86_OP_REX_X UINT8_C(0x42)
3242	#define X86_OP_REX_R UINT8_C(0x44)
3243	#define X86_OP_REX_W UINT8_C(0x48)
3244	/** @} */
3245
3246
3247	/** @} */
3248
3249	#endif
3250

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source: vbox/trunk/include/iprt/x86.h@ 47356

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