VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 43974

Last change on this file since 43974 was 43974, checked in by vboxsync, 12 years ago

VMM: Fix MSR range values for X2APIC, add in the X2APIC TPR MSR.
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File size: 113.6 KB
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1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2012 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef ___iprt_x86_h
29#define ___iprt_x86_h
30
31#ifndef VBOX_FOR_DTRACE_LIB
32# include <iprt/types.h>
33# include <iprt/assert.h>
34#else
35# pragma D depends_on library vbox-types.d
36#endif
37
38/* Workaround for Solaris sys/regset.h defining CS, DS */
39#ifdef RT_OS_SOLARIS
40# undef CS
41# undef DS
42#endif
43
44/** @defgroup grp_rt_x86 x86 Types and Definitions
45 * @ingroup grp_rt
46 * @{
47 */
48
49#ifndef VBOX_FOR_DTRACE_LIB
50/**
51 * EFLAGS Bits.
52 */
53typedef struct X86EFLAGSBITS
54{
55 /** Bit 0 - CF - Carry flag - Status flag. */
56 unsigned u1CF : 1;
57 /** Bit 1 - 1 - Reserved flag. */
58 unsigned u1Reserved0 : 1;
59 /** Bit 2 - PF - Parity flag - Status flag. */
60 unsigned u1PF : 1;
61 /** Bit 3 - 0 - Reserved flag. */
62 unsigned u1Reserved1 : 1;
63 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64 unsigned u1AF : 1;
65 /** Bit 5 - 0 - Reserved flag. */
66 unsigned u1Reserved2 : 1;
67 /** Bit 6 - ZF - Zero flag - Status flag. */
68 unsigned u1ZF : 1;
69 /** Bit 7 - SF - Signed flag - Status flag. */
70 unsigned u1SF : 1;
71 /** Bit 8 - TF - Trap flag - System flag. */
72 unsigned u1TF : 1;
73 /** Bit 9 - IF - Interrupt flag - System flag. */
74 unsigned u1IF : 1;
75 /** Bit 10 - DF - Direction flag - Control flag. */
76 unsigned u1DF : 1;
77 /** Bit 11 - OF - Overflow flag - Status flag. */
78 unsigned u1OF : 1;
79 /** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80 unsigned u2IOPL : 2;
81 /** Bit 14 - NT - Nested task flag - System flag. */
82 unsigned u1NT : 1;
83 /** Bit 15 - 0 - Reserved flag. */
84 unsigned u1Reserved3 : 1;
85 /** Bit 16 - RF - Resume flag - System flag. */
86 unsigned u1RF : 1;
87 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
88 unsigned u1VM : 1;
89 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90 unsigned u1AC : 1;
91 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92 unsigned u1VIF : 1;
93 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94 unsigned u1VIP : 1;
95 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96 unsigned u1ID : 1;
97 /** Bit 22-31 - 0 - Reserved flag. */
98 unsigned u10Reserved4 : 10;
99} X86EFLAGSBITS;
100/** Pointer to EFLAGS bits. */
101typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102/** Pointer to const EFLAGS bits. */
103typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104#endif /* !VBOX_FOR_DTRACE_LIB */
105
106/**
107 * EFLAGS.
108 */
109typedef union X86EFLAGS
110{
111 /** The plain unsigned view. */
112 uint32_t u;
113#ifndef VBOX_FOR_DTRACE_LIB
114 /** The bitfield view. */
115 X86EFLAGSBITS Bits;
116#endif
117 /** The 8-bit view. */
118 uint8_t au8[4];
119 /** The 16-bit view. */
120 uint16_t au16[2];
121 /** The 32-bit view. */
122 uint32_t au32[1];
123 /** The 32-bit view. */
124 uint32_t u32;
125} X86EFLAGS;
126/** Pointer to EFLAGS. */
127typedef X86EFLAGS *PX86EFLAGS;
128/** Pointer to const EFLAGS. */
129typedef const X86EFLAGS *PCX86EFLAGS;
130
131/**
132 * RFLAGS (32 upper bits are reserved).
133 */
134typedef union X86RFLAGS
135{
136 /** The plain unsigned view. */
137 uint64_t u;
138#ifndef VBOX_FOR_DTRACE_LIB
139 /** The bitfield view. */
140 X86EFLAGSBITS Bits;
141#endif
142 /** The 8-bit view. */
143 uint8_t au8[8];
144 /** The 16-bit view. */
145 uint16_t au16[4];
146 /** The 32-bit view. */
147 uint32_t au32[2];
148 /** The 64-bit view. */
149 uint64_t au64[1];
150 /** The 64-bit view. */
151 uint64_t u64;
152} X86RFLAGS;
153/** Pointer to RFLAGS. */
154typedef X86RFLAGS *PX86RFLAGS;
155/** Pointer to const RFLAGS. */
156typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159/** @name EFLAGS
160 * @{
161 */
162/** Bit 0 - CF - Carry flag - Status flag. */
163#define X86_EFL_CF RT_BIT(0)
164/** Bit 1 - Reserved, reads as 1. */
165#define X86_EFL_1 RT_BIT(1)
166/** Bit 2 - PF - Parity flag - Status flag. */
167#define X86_EFL_PF RT_BIT(2)
168/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
169#define X86_EFL_AF RT_BIT(4)
170/** Bit 6 - ZF - Zero flag - Status flag. */
171#define X86_EFL_ZF RT_BIT(6)
172/** Bit 7 - SF - Signed flag - Status flag. */
173#define X86_EFL_SF RT_BIT(7)
174/** Bit 8 - TF - Trap flag - System flag. */
175#define X86_EFL_TF RT_BIT(8)
176/** Bit 9 - IF - Interrupt flag - System flag. */
177#define X86_EFL_IF RT_BIT(9)
178/** Bit 10 - DF - Direction flag - Control flag. */
179#define X86_EFL_DF RT_BIT(10)
180/** Bit 11 - OF - Overflow flag - Status flag. */
181#define X86_EFL_OF RT_BIT(11)
182/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
183#define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
184/** Bit 14 - NT - Nested task flag - System flag. */
185#define X86_EFL_NT RT_BIT(14)
186/** Bit 16 - RF - Resume flag - System flag. */
187#define X86_EFL_RF RT_BIT(16)
188/** Bit 17 - VM - Virtual 8086 mode - System flag. */
189#define X86_EFL_VM RT_BIT(17)
190/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
191#define X86_EFL_AC RT_BIT(18)
192/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
193#define X86_EFL_VIF RT_BIT(19)
194/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
195#define X86_EFL_VIP RT_BIT(20)
196/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
197#define X86_EFL_ID RT_BIT(21)
198/** IOPL shift. */
199#define X86_EFL_IOPL_SHIFT 12
200/** The the IOPL level from the flags. */
201#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
202/** Bits restored by popf */
203#define X86_EFL_POPF_BITS (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID)
204/** @} */
205
206
207/** CPUID Feature information - ECX.
208 * CPUID query with EAX=1.
209 */
210#ifndef VBOX_FOR_DTRACE_LIB
211typedef struct X86CPUIDFEATECX
212{
213 /** Bit 0 - SSE3 - Supports SSE3 or not. */
214 unsigned u1SSE3 : 1;
215 /** Bit 1 - PCLMULQDQ. */
216 unsigned u1PCLMULQDQ : 1;
217 /** Bit 2 - DS Area 64-bit layout. */
218 unsigned u1DTE64 : 1;
219 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
220 unsigned u1Monitor : 1;
221 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
222 unsigned u1CPLDS : 1;
223 /** Bit 5 - VMX - Virtual Machine Technology. */
224 unsigned u1VMX : 1;
225 /** Bit 6 - SMX: Safer Mode Extensions. */
226 unsigned u1SMX : 1;
227 /** Bit 7 - EST - Enh. SpeedStep Tech. */
228 unsigned u1EST : 1;
229 /** Bit 8 - TM2 - Terminal Monitor 2. */
230 unsigned u1TM2 : 1;
231 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
232 unsigned u1SSSE3 : 1;
233 /** Bit 10 - CNTX-ID - L1 Context ID. */
234 unsigned u1CNTXID : 1;
235 /** Bit 11 - Reserved. */
236 unsigned u1Reserved1 : 1;
237 /** Bit 12 - FMA. */
238 unsigned u1FMA : 1;
239 /** Bit 13 - CX16 - CMPXCHG16B. */
240 unsigned u1CX16 : 1;
241 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
242 unsigned u1TPRUpdate : 1;
243 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
244 unsigned u1PDCM : 1;
245 /** Bit 16 - Reserved. */
246 unsigned u1Reserved2 : 1;
247 /** Bit 17 - PCID - Process-context identifiers. */
248 unsigned u1PCID : 1;
249 /** Bit 18 - Direct Cache Access. */
250 unsigned u1DCA : 1;
251 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
252 unsigned u1SSE4_1 : 1;
253 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
254 unsigned u1SSE4_2 : 1;
255 /** Bit 21 - x2APIC. */
256 unsigned u1x2APIC : 1;
257 /** Bit 22 - MOVBE - Supports MOVBE. */
258 unsigned u1MOVBE : 1;
259 /** Bit 23 - POPCNT - Supports POPCNT. */
260 unsigned u1POPCNT : 1;
261 /** Bit 24 - TSC-Deadline. */
262 unsigned u1TSCDEADLINE : 1;
263 /** Bit 25 - AES. */
264 unsigned u1AES : 1;
265 /** Bit 26 - XSAVE - Supports XSAVE. */
266 unsigned u1XSAVE : 1;
267 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
268 unsigned u1OSXSAVE : 1;
269 /** Bit 28 - AVX - Supports AVX instruction extensions. */
270 unsigned u1AVX : 1;
271 /** Bit 29 - 30 - Reserved */
272 unsigned u2Reserved3 : 2;
273 /** Bit 31 - Hypervisor present (we're a guest). */
274 unsigned u1HVP : 1;
275} X86CPUIDFEATECX;
276#else /* VBOX_FOR_DTRACE_LIB */
277typedef uint32_t X86CPUIDFEATECX;
278#endif /* VBOX_FOR_DTRACE_LIB */
279/** Pointer to CPUID Feature Information - ECX. */
280typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
281/** Pointer to const CPUID Feature Information - ECX. */
282typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
283
284
285/** CPUID Feature Information - EDX.
286 * CPUID query with EAX=1.
287 */
288#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
289typedef struct X86CPUIDFEATEDX
290{
291 /** Bit 0 - FPU - x87 FPU on Chip. */
292 unsigned u1FPU : 1;
293 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
294 unsigned u1VME : 1;
295 /** Bit 2 - DE - Debugging extensions. */
296 unsigned u1DE : 1;
297 /** Bit 3 - PSE - Page Size Extension. */
298 unsigned u1PSE : 1;
299 /** Bit 4 - TSC - Time Stamp Counter. */
300 unsigned u1TSC : 1;
301 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
302 unsigned u1MSR : 1;
303 /** Bit 6 - PAE - Physical Address Extension. */
304 unsigned u1PAE : 1;
305 /** Bit 7 - MCE - Machine Check Exception. */
306 unsigned u1MCE : 1;
307 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
308 unsigned u1CX8 : 1;
309 /** Bit 9 - APIC - APIC On-Chip. */
310 unsigned u1APIC : 1;
311 /** Bit 10 - Reserved. */
312 unsigned u1Reserved1 : 1;
313 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
314 unsigned u1SEP : 1;
315 /** Bit 12 - MTRR - Memory Type Range Registers. */
316 unsigned u1MTRR : 1;
317 /** Bit 13 - PGE - PTE Global Bit. */
318 unsigned u1PGE : 1;
319 /** Bit 14 - MCA - Machine Check Architecture. */
320 unsigned u1MCA : 1;
321 /** Bit 15 - CMOV - Conditional Move Instructions. */
322 unsigned u1CMOV : 1;
323 /** Bit 16 - PAT - Page Attribute Table. */
324 unsigned u1PAT : 1;
325 /** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
326 unsigned u1PSE36 : 1;
327 /** Bit 18 - PSN - Processor Serial Number. */
328 unsigned u1PSN : 1;
329 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
330 unsigned u1CLFSH : 1;
331 /** Bit 20 - Reserved. */
332 unsigned u1Reserved2 : 1;
333 /** Bit 21 - DS - Debug Store. */
334 unsigned u1DS : 1;
335 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
336 unsigned u1ACPI : 1;
337 /** Bit 23 - MMX - Intel MMX 'Technology'. */
338 unsigned u1MMX : 1;
339 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
340 unsigned u1FXSR : 1;
341 /** Bit 25 - SSE - SSE Support. */
342 unsigned u1SSE : 1;
343 /** Bit 26 - SSE2 - SSE2 Support. */
344 unsigned u1SSE2 : 1;
345 /** Bit 27 - SS - Self Snoop. */
346 unsigned u1SS : 1;
347 /** Bit 28 - HTT - Hyper-Threading Technology. */
348 unsigned u1HTT : 1;
349 /** Bit 29 - TM - Thermal Monitor. */
350 unsigned u1TM : 1;
351 /** Bit 30 - Reserved - . */
352 unsigned u1Reserved3 : 1;
353 /** Bit 31 - PBE - Pending Break Enabled. */
354 unsigned u1PBE : 1;
355} X86CPUIDFEATEDX;
356#else /* VBOX_FOR_DTRACE_LIB */
357typedef uint32_t X86CPUIDFEATEDX;
358#endif /* VBOX_FOR_DTRACE_LIB */
359/** Pointer to CPUID Feature Information - EDX. */
360typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
361/** Pointer to const CPUID Feature Information - EDX. */
362typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
363
364/** @name CPUID Vendor information.
365 * CPUID query with EAX=0.
366 * @{
367 */
368#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
369#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
370#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
371
372#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
373#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
374#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
375
376#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
377#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
378#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
379/** @} */
380
381
382/** @name CPUID Feature information.
383 * CPUID query with EAX=1.
384 * @{
385 */
386/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
387#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
388/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
389#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
390/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
391#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
392/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
393#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
394/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
395#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
396/** ECX Bit 5 - VMX - Virtual Machine Technology. */
397#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
398/** ECX Bit 6 - SMX - Safer Mode Extensions. */
399#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
400/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
401#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
402/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
403#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
404/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
405#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
406/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
407#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
408/** ECX Bit 12 - FMA. */
409#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
410/** ECX Bit 13 - CX16 - CMPXCHG16B. */
411#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
412/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
413#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
414/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
415#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
416/** ECX Bit 17 - PCID - Process-context identifiers. */
417#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
418/** ECX Bit 18 - DCA - Direct Cache Access. */
419#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
420/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
421#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
422/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
423#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
424/** ECX Bit 21 - x2APIC support. */
425#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
426/** ECX Bit 22 - MOVBE instruction. */
427#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
428/** ECX Bit 23 - POPCNT instruction. */
429#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
430/** ECX Bir 24 - TSC-Deadline. */
431#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
432/** ECX Bit 25 - AES instructions. */
433#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
434/** ECX Bit 26 - XSAVE instruction. */
435#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
436/** ECX Bit 27 - OSXSAVE instruction. */
437#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
438/** ECX Bit 28 - AVX. */
439#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
440/** ECX Bit 31 - Hypervisor Present (software only). */
441#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
442
443
444/** Bit 0 - FPU - x87 FPU on Chip. */
445#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
446/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
447#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
448/** Bit 2 - DE - Debugging extensions. */
449#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
450/** Bit 3 - PSE - Page Size Extension. */
451#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
452/** Bit 4 - TSC - Time Stamp Counter. */
453#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
454/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
455#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
456/** Bit 6 - PAE - Physical Address Extension. */
457#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
458/** Bit 7 - MCE - Machine Check Exception. */
459#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
460/** Bit 8 - CX8 - CMPXCHG8B instruction. */
461#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
462/** Bit 9 - APIC - APIC On-Chip. */
463#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
464/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
465#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
466/** Bit 12 - MTRR - Memory Type Range Registers. */
467#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
468/** Bit 13 - PGE - PTE Global Bit. */
469#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
470/** Bit 14 - MCA - Machine Check Architecture. */
471#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
472/** Bit 15 - CMOV - Conditional Move Instructions. */
473#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
474/** Bit 16 - PAT - Page Attribute Table. */
475#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
476/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
477#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
478/** Bit 18 - PSN - Processor Serial Number. */
479#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
480/** Bit 19 - CLFSH - CLFLUSH Instruction. */
481#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
482/** Bit 21 - DS - Debug Store. */
483#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
484/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
485#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
486/** Bit 23 - MMX - Intel MMX Technology. */
487#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
488/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
489#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
490/** Bit 25 - SSE - SSE Support. */
491#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
492/** Bit 26 - SSE2 - SSE2 Support. */
493#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
494/** Bit 27 - SS - Self Snoop. */
495#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
496/** Bit 28 - HTT - Hyper-Threading Technology. */
497#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
498/** Bit 29 - TM - Therm. Monitor. */
499#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
500/** Bit 31 - PBE - Pending Break Enabled. */
501#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
502/** @} */
503
504/** @name CPUID mwait/monitor information.
505 * CPUID query with EAX=5.
506 * @{
507 */
508/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
509#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
510/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
511#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
512/** @} */
513
514
515/** @name CPUID Extended Feature information.
516 * CPUID query with EAX=0x80000001.
517 * @{
518 */
519/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
520#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
521
522/** EDX Bit 11 - SYSCALL/SYSRET. */
523#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
524/** EDX Bit 20 - No-Execute/Execute-Disable. */
525#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
526/** EDX Bit 26 - 1 GB large page. */
527#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
528/** EDX Bit 27 - RDTSCP. */
529#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
530/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
531#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
532/** @}*/
533
534/** @name CPUID AMD Feature information.
535 * CPUID query with EAX=0x80000001.
536 * @{
537 */
538/** Bit 0 - FPU - x87 FPU on Chip. */
539#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
540/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
541#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
542/** Bit 2 - DE - Debugging extensions. */
543#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
544/** Bit 3 - PSE - Page Size Extension. */
545#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
546/** Bit 4 - TSC - Time Stamp Counter. */
547#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
548/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
549#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
550/** Bit 6 - PAE - Physical Address Extension. */
551#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
552/** Bit 7 - MCE - Machine Check Exception. */
553#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
554/** Bit 8 - CX8 - CMPXCHG8B instruction. */
555#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
556/** Bit 9 - APIC - APIC On-Chip. */
557#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
558/** Bit 12 - MTRR - Memory Type Range Registers. */
559#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
560/** Bit 13 - PGE - PTE Global Bit. */
561#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
562/** Bit 14 - MCA - Machine Check Architecture. */
563#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
564/** Bit 15 - CMOV - Conditional Move Instructions. */
565#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
566/** Bit 16 - PAT - Page Attribute Table. */
567#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
568/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
569#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
570/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
571#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
572/** Bit 23 - MMX - Intel MMX Technology. */
573#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
574/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
575#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
576/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
577#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
578/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
579#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
580/** Bit 31 - 3DNOW - AMD 3DNow. */
581#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
582
583/** Bit 1 - CMPL - Core multi-processing legacy mode. */
584#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
585/** Bit 2 - SVM - AMD VM extensions. */
586#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
587/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
588#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
589/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
590#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
591/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
592#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
593/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
594#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
595/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
596#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
597/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
598#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
599/** Bit 9 - OSVW - AMD OS visible workaround. */
600#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
601/** Bit 10 - IBS - Instruct based sampling. */
602#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
603/** Bit 11 - SSE5 - SSE5 instruction support. */
604#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
605/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
606#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
607/** Bit 13 - WDT - AMD Watchdog timer support. */
608#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
609
610/** @} */
611
612
613/** @name CPUID AMD Feature information.
614 * CPUID query with EAX=0x80000007.
615 * @{
616 */
617/** Bit 0 - TS - Temperature Sensor. */
618#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
619/** Bit 1 - FID - Frequency ID Control. */
620#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
621/** Bit 2 - VID - Voltage ID Control. */
622#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
623/** Bit 3 - TTP - THERMTRIP. */
624#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
625/** Bit 4 - TM - Hardware Thermal Control. */
626#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
627/** Bit 5 - STC - Software Thermal Control. */
628#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
629/** Bit 6 - MC - 100 Mhz Multiplier Control. */
630#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
631/** Bit 7 - HWPSTATE - Hardware P-State Control. */
632#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
633/** Bit 8 - TSCINVAR - TSC Invariant. */
634#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
635/** @} */
636
637
638/** @name CR0
639 * @{ */
640/** Bit 0 - PE - Protection Enabled */
641#define X86_CR0_PE RT_BIT(0)
642#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
643/** Bit 1 - MP - Monitor Coprocessor */
644#define X86_CR0_MP RT_BIT(1)
645#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
646/** Bit 2 - EM - Emulation. */
647#define X86_CR0_EM RT_BIT(2)
648#define X86_CR0_EMULATE_FPU RT_BIT(2)
649/** Bit 3 - TS - Task Switch. */
650#define X86_CR0_TS RT_BIT(3)
651#define X86_CR0_TASK_SWITCH RT_BIT(3)
652/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
653#define X86_CR0_ET RT_BIT(4)
654#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
655/** Bit 5 - NE - Numeric error. */
656#define X86_CR0_NE RT_BIT(5)
657#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
658/** Bit 16 - WP - Write Protect. */
659#define X86_CR0_WP RT_BIT(16)
660#define X86_CR0_WRITE_PROTECT RT_BIT(16)
661/** Bit 18 - AM - Alignment Mask. */
662#define X86_CR0_AM RT_BIT(18)
663#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
664/** Bit 29 - NW - Not Write-though. */
665#define X86_CR0_NW RT_BIT(29)
666#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
667/** Bit 30 - WP - Cache Disable. */
668#define X86_CR0_CD RT_BIT(30)
669#define X86_CR0_CACHE_DISABLE RT_BIT(30)
670/** Bit 31 - PG - Paging. */
671#define X86_CR0_PG RT_BIT(31)
672#define X86_CR0_PAGING RT_BIT(31)
673/** @} */
674
675
676/** @name CR3
677 * @{ */
678/** Bit 3 - PWT - Page-level Writes Transparent. */
679#define X86_CR3_PWT RT_BIT(3)
680/** Bit 4 - PCD - Page-level Cache Disable. */
681#define X86_CR3_PCD RT_BIT(4)
682/** Bits 12-31 - - Page directory page number. */
683#define X86_CR3_PAGE_MASK (0xfffff000)
684/** Bits 5-31 - - PAE Page directory page number. */
685#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
686/** Bits 12-51 - - AMD64 Page directory page number. */
687#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
688/** @} */
689
690
691/** @name CR4
692 * @{ */
693/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
694#define X86_CR4_VME RT_BIT(0)
695/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
696#define X86_CR4_PVI RT_BIT(1)
697/** Bit 2 - TSD - Time Stamp Disable. */
698#define X86_CR4_TSD RT_BIT(2)
699/** Bit 3 - DE - Debugging Extensions. */
700#define X86_CR4_DE RT_BIT(3)
701/** Bit 4 - PSE - Page Size Extension. */
702#define X86_CR4_PSE RT_BIT(4)
703/** Bit 5 - PAE - Physical Address Extension. */
704#define X86_CR4_PAE RT_BIT(5)
705/** Bit 6 - MCE - Machine-Check Enable. */
706#define X86_CR4_MCE RT_BIT(6)
707/** Bit 7 - PGE - Page Global Enable. */
708#define X86_CR4_PGE RT_BIT(7)
709/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
710#define X86_CR4_PCE RT_BIT(8)
711/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
712#define X86_CR4_OSFSXR RT_BIT(9)
713/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
714#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
715/** Bit 13 - VMXE - VMX mode is enabled. */
716#define X86_CR4_VMXE RT_BIT(13)
717/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
718#define X86_CR4_SMXE RT_BIT(14)
719/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
720#define X86_CR4_PCIDE RT_BIT(17)
721/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
722 * extended states. */
723#define X86_CR4_OSXSAVE RT_BIT(18)
724/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
725#define X86_CR4_SMEP RT_BIT(20)
726/** @} */
727
728
729/** @name DR6
730 * @{ */
731/** Bit 0 - B0 - Breakpoint 0 condition detected. */
732#define X86_DR6_B0 RT_BIT(0)
733/** Bit 1 - B1 - Breakpoint 1 condition detected. */
734#define X86_DR6_B1 RT_BIT(1)
735/** Bit 2 - B2 - Breakpoint 2 condition detected. */
736#define X86_DR6_B2 RT_BIT(2)
737/** Bit 3 - B3 - Breakpoint 3 condition detected. */
738#define X86_DR6_B3 RT_BIT(3)
739/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
740#define X86_DR6_BD RT_BIT(13)
741/** Bit 14 - BS - Single step */
742#define X86_DR6_BS RT_BIT(14)
743/** Bit 15 - BT - Task switch. (TSS T bit.) */
744#define X86_DR6_BT RT_BIT(15)
745/** Value of DR6 after powerup/reset. */
746#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
747/** @} */
748
749
750/** @name DR7
751 * @{ */
752/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
753#define X86_DR7_L0 RT_BIT(0)
754/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
755#define X86_DR7_G0 RT_BIT(1)
756/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
757#define X86_DR7_L1 RT_BIT(2)
758/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
759#define X86_DR7_G1 RT_BIT(3)
760/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
761#define X86_DR7_L2 RT_BIT(4)
762/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
763#define X86_DR7_G2 RT_BIT(5)
764/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
765#define X86_DR7_L3 RT_BIT(6)
766/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
767#define X86_DR7_G3 RT_BIT(7)
768/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
769#define X86_DR7_LE RT_BIT(8)
770/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
771#define X86_DR7_GE RT_BIT(9)
772
773/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
774 * any DR register is accessed. */
775#define X86_DR7_GD RT_BIT(13)
776/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
777#define X86_DR7_RW0_MASK (3 << 16)
778/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
779#define X86_DR7_LEN0_MASK (3 << 18)
780/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
781#define X86_DR7_RW1_MASK (3 << 20)
782/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
783#define X86_DR7_LEN1_MASK (3 << 22)
784/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
785#define X86_DR7_RW2_MASK (3 << 24)
786/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
787#define X86_DR7_LEN2_MASK (3 << 26)
788/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
789#define X86_DR7_RW3_MASK (3 << 28)
790/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
791#define X86_DR7_LEN3_MASK (3 << 30)
792
793/** Bits which must be 1s. */
794#define X86_DR7_MB1_MASK (RT_BIT(10))
795
796/** Calcs the L bit of Nth breakpoint.
797 * @param iBp The breakpoint number [0..3].
798 */
799#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
800
801/** Calcs the G bit of Nth breakpoint.
802 * @param iBp The breakpoint number [0..3].
803 */
804#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
805
806/** @name Read/Write values.
807 * @{ */
808/** Break on instruction fetch only. */
809#define X86_DR7_RW_EO 0U
810/** Break on write only. */
811#define X86_DR7_RW_WO 1U
812/** Break on I/O read/write. This is only defined if CR4.DE is set. */
813#define X86_DR7_RW_IO 2U
814/** Break on read or write (but not instruction fetches). */
815#define X86_DR7_RW_RW 3U
816/** @} */
817
818/** Shifts a X86_DR7_RW_* value to its right place.
819 * @param iBp The breakpoint number [0..3].
820 * @param fRw One of the X86_DR7_RW_* value.
821 */
822#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
823
824/** @name Length values.
825 * @{ */
826#define X86_DR7_LEN_BYTE 0U
827#define X86_DR7_LEN_WORD 1U
828#define X86_DR7_LEN_QWORD 2U /**< AMD64 long mode only. */
829#define X86_DR7_LEN_DWORD 3U
830/** @} */
831
832/** Shifts a X86_DR7_LEN_* value to its right place.
833 * @param iBp The breakpoint number [0..3].
834 * @param cb One of the X86_DR7_LEN_* values.
835 */
836#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
837
838/** Fetch the breakpoint length bits from the DR7 value.
839 * @param uDR7 DR7 value
840 * @param iBp The breakpoint number [0..3].
841 */
842#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
843
844/** Mask used to check if any breakpoints are enabled. */
845#define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7))
846
847/** Mask used to check if any io breakpoints are set. */
848#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) | X86_DR7_RW(1, X86_DR7_RW_IO) | X86_DR7_RW(2, X86_DR7_RW_IO) | X86_DR7_RW(3, X86_DR7_RW_IO))
849
850/** Value of DR7 after powerup/reset. */
851#define X86_DR7_INIT_VAL 0x400
852/** @} */
853
854
855/** @name Machine Specific Registers
856 * @{
857 */
858
859/** Time Stamp Counter. */
860#define MSR_IA32_TSC 0x10
861
862#define MSR_IA32_PLATFORM_ID 0x17
863
864#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
865#define MSR_IA32_APICBASE 0x1b
866#endif
867
868/** CPU Feature control. */
869#define MSR_IA32_FEATURE_CONTROL 0x3A
870#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
871#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
872
873/** BIOS update trigger (microcode update). */
874#define MSR_IA32_BIOS_UPDT_TRIG 0x79
875
876/** BIOS update signature (microcode). */
877#define MSR_IA32_BIOS_SIGN_ID 0x8B
878
879/** General performance counter no. 0. */
880#define MSR_IA32_PMC0 0xC1
881/** General performance counter no. 1. */
882#define MSR_IA32_PMC1 0xC2
883/** General performance counter no. 2. */
884#define MSR_IA32_PMC2 0xC3
885/** General performance counter no. 3. */
886#define MSR_IA32_PMC3 0xC4
887
888/** Nehalem power control. */
889#define MSR_IA32_PLATFORM_INFO 0xCE
890
891/** Get FSB clock status (Intel-specific). */
892#define MSR_IA32_FSB_CLOCK_STS 0xCD
893
894/** MTRR Capabilities. */
895#define MSR_IA32_MTRR_CAP 0xFE
896
897
898#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
899/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
900 * R0 SS == CS + 8
901 * R3 CS == CS + 16
902 * R3 SS == CS + 24
903 */
904#define MSR_IA32_SYSENTER_CS 0x174
905/** SYSENTER_ESP - the R0 ESP. */
906#define MSR_IA32_SYSENTER_ESP 0x175
907/** SYSENTER_EIP - the R0 EIP. */
908#define MSR_IA32_SYSENTER_EIP 0x176
909#endif
910
911/** Machine Check Global Capabilities Register. */
912#define MSR_IA32_MCP_CAP 0x179
913/** Machine Check Global Status Register. */
914#define MSR_IA32_MCP_STATUS 0x17A
915/** Machine Check Global Control Register. */
916#define MSR_IA32_MCP_CTRL 0x17B
917
918/** Trace/Profile Resource Control (R/W) */
919#define MSR_IA32_DEBUGCTL 0x1D9
920
921/** Page Attribute Table. */
922#define MSR_IA32_CR_PAT 0x277
923
924/** Performance counter MSRs. (Intel only) */
925#define MSR_IA32_PERFEVTSEL0 0x186
926#define MSR_IA32_PERFEVTSEL1 0x187
927#define MSR_IA32_FLEX_RATIO 0x194
928#define MSR_IA32_PERF_STATUS 0x198
929#define MSR_IA32_PERF_CTL 0x199
930#define MSR_IA32_THERM_STATUS 0x19c
931
932/** Enable misc. processor features (R/W). */
933#define MSR_IA32_MISC_ENABLE 0x1A0
934/** Enable fast-strings feature (for REP MOVS and REP STORS). */
935#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
936/** Automatic Thermal Control Circuit Enable (R/W). */
937#define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
938/** Performance Monitoring Available (R). */
939#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
940/** Branch Trace Storage Unavailable (R/O). */
941#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
942/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
943#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
944/** Enhanced Intel SpeedStep Technology Enable (R/W). */
945#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
946/** If MONITOR/MWAIT is supported (R/W). */
947#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
948/** Limit CPUID Maxval to 3 leafs (R/W). */
949#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
950/** When set to 1, xTPR messages are disabled (R/W). */
951#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
952/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
953#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
954
955#define IA32_MTRR_PHYSBASE0 0x200
956#define IA32_MTRR_PHYSMASK0 0x201
957#define IA32_MTRR_PHYSBASE1 0x202
958#define IA32_MTRR_PHYSMASK1 0x203
959#define IA32_MTRR_PHYSBASE2 0x204
960#define IA32_MTRR_PHYSMASK2 0x205
961#define IA32_MTRR_PHYSBASE3 0x206
962#define IA32_MTRR_PHYSMASK3 0x207
963#define IA32_MTRR_PHYSBASE4 0x208
964#define IA32_MTRR_PHYSMASK4 0x209
965#define IA32_MTRR_PHYSBASE5 0x20a
966#define IA32_MTRR_PHYSMASK5 0x20b
967#define IA32_MTRR_PHYSBASE6 0x20c
968#define IA32_MTRR_PHYSMASK6 0x20d
969#define IA32_MTRR_PHYSBASE7 0x20e
970#define IA32_MTRR_PHYSMASK7 0x20f
971#define IA32_MTRR_PHYSBASE8 0x210
972#define IA32_MTRR_PHYSMASK8 0x211
973#define IA32_MTRR_PHYSBASE9 0x212
974#define IA32_MTRR_PHYSMASK9 0x213
975
976/** Fixed range MTRRs.
977 * @{ */
978#define IA32_MTRR_FIX64K_00000 0x250
979#define IA32_MTRR_FIX16K_80000 0x258
980#define IA32_MTRR_FIX16K_A0000 0x259
981#define IA32_MTRR_FIX4K_C0000 0x268
982#define IA32_MTRR_FIX4K_C8000 0x269
983#define IA32_MTRR_FIX4K_D0000 0x26a
984#define IA32_MTRR_FIX4K_D8000 0x26b
985#define IA32_MTRR_FIX4K_E0000 0x26c
986#define IA32_MTRR_FIX4K_E8000 0x26d
987#define IA32_MTRR_FIX4K_F0000 0x26e
988#define IA32_MTRR_FIX4K_F8000 0x26f
989/** @} */
990
991/** MTRR Default Range. */
992#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
993
994#define MSR_IA32_MC0_CTL 0x400
995#define MSR_IA32_MC0_STATUS 0x401
996
997/** Basic VMX information. */
998#define MSR_IA32_VMX_BASIC_INFO 0x480
999/** Allowed settings for pin-based VM execution controls */
1000#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1001/** Allowed settings for proc-based VM execution controls */
1002#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1003/** Allowed settings for the VMX exit controls. */
1004#define MSR_IA32_VMX_EXIT_CTLS 0x483
1005/** Allowed settings for the VMX entry controls. */
1006#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1007/** Misc VMX info. */
1008#define MSR_IA32_VMX_MISC 0x485
1009/** Fixed cleared bits in CR0. */
1010#define MSR_IA32_VMX_CR0_FIXED0 0x486
1011/** Fixed set bits in CR0. */
1012#define MSR_IA32_VMX_CR0_FIXED1 0x487
1013/** Fixed cleared bits in CR4. */
1014#define MSR_IA32_VMX_CR4_FIXED0 0x488
1015/** Fixed set bits in CR4. */
1016#define MSR_IA32_VMX_CR4_FIXED1 0x489
1017/** Information for enumerating fields in the VMCS. */
1018#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1019/** Allowed settings for secondary proc-based VM execution controls */
1020#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1021/** EPT capabilities. */
1022#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1023/** DS Save Area (R/W). */
1024#define MSR_IA32_DS_AREA 0x600
1025/** X2APIC MSR ranges. */
1026#define MSR_IA32_X2APIC_START 0x800
1027#define MSR_IA32_X2APIC_TPR 0x808
1028#define MSR_IA32_X2APIC_END 0xBFF
1029
1030/** K6 EFER - Extended Feature Enable Register. */
1031#define MSR_K6_EFER 0xc0000080
1032/** @todo document EFER */
1033/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1034#define MSR_K6_EFER_SCE RT_BIT(0)
1035/** Bit 8 - LME - Long mode enabled. (R/W) */
1036#define MSR_K6_EFER_LME RT_BIT(8)
1037/** Bit 10 - LMA - Long mode active. (R) */
1038#define MSR_K6_EFER_LMA RT_BIT(10)
1039/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1040#define MSR_K6_EFER_NXE RT_BIT(11)
1041/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1042#define MSR_K6_EFER_SVME RT_BIT(12)
1043/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1044#define MSR_K6_EFER_LMSLE RT_BIT(13)
1045/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1046#define MSR_K6_EFER_FFXSR RT_BIT(14)
1047/** K6 STAR - SYSCALL/RET targets. */
1048#define MSR_K6_STAR 0xc0000081
1049/** Shift value for getting the SYSRET CS and SS value. */
1050#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1051/** Shift value for getting the SYSCALL CS and SS value. */
1052#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1053/** Selector mask for use after shifting. */
1054#define MSR_K6_STAR_SEL_MASK 0xffff
1055/** The mask which give the SYSCALL EIP. */
1056#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
1057/** K6 WHCR - Write Handling Control Register. */
1058#define MSR_K6_WHCR 0xc0000082
1059/** K6 UWCCR - UC/WC Cacheability Control Register. */
1060#define MSR_K6_UWCCR 0xc0000085
1061/** K6 PSOR - Processor State Observability Register. */
1062#define MSR_K6_PSOR 0xc0000087
1063/** K6 PFIR - Page Flush/Invalidate Register. */
1064#define MSR_K6_PFIR 0xc0000088
1065
1066/** Performance counter MSRs. (AMD only) */
1067#define MSR_K7_EVNTSEL0 0xc0010000
1068#define MSR_K7_EVNTSEL1 0xc0010001
1069#define MSR_K7_EVNTSEL2 0xc0010002
1070#define MSR_K7_EVNTSEL3 0xc0010003
1071#define MSR_K7_PERFCTR0 0xc0010004
1072#define MSR_K7_PERFCTR1 0xc0010005
1073#define MSR_K7_PERFCTR2 0xc0010006
1074#define MSR_K7_PERFCTR3 0xc0010007
1075
1076/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1077#define MSR_K8_LSTAR 0xc0000082
1078/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1079#define MSR_K8_CSTAR 0xc0000083
1080/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1081#define MSR_K8_SF_MASK 0xc0000084
1082/** K8 FS.base - The 64-bit base FS register. */
1083#define MSR_K8_FS_BASE 0xc0000100
1084/** K8 GS.base - The 64-bit base GS register. */
1085#define MSR_K8_GS_BASE 0xc0000101
1086/** K8 KernelGSbase - Used with SWAPGS. */
1087#define MSR_K8_KERNEL_GS_BASE 0xc0000102
1088/** K8 TSC_AUX - Used with RDTSCP. */
1089#define MSR_K8_TSC_AUX 0xc0000103
1090#define MSR_K8_SYSCFG 0xc0010010
1091#define MSR_K8_HWCR 0xc0010015
1092#define MSR_K8_IORRBASE0 0xc0010016
1093#define MSR_K8_IORRMASK0 0xc0010017
1094#define MSR_K8_IORRBASE1 0xc0010018
1095#define MSR_K8_IORRMASK1 0xc0010019
1096#define MSR_K8_TOP_MEM1 0xc001001a
1097#define MSR_K8_TOP_MEM2 0xc001001d
1098#define MSR_K8_VM_CR 0xc0010114
1099#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1100
1101#define MSR_K8_IGNNE 0xc0010115
1102#define MSR_K8_SMM_CTL 0xc0010116
1103/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1104 * host state during world switch.
1105 */
1106#define MSR_K8_VM_HSAVE_PA 0xc0010117
1107
1108/** @} */
1109
1110
1111/** @name Page Table / Directory / Directory Pointers / L4.
1112 * @{
1113 */
1114
1115/** Page table/directory entry as an unsigned integer. */
1116typedef uint32_t X86PGUINT;
1117/** Pointer to a page table/directory table entry as an unsigned integer. */
1118typedef X86PGUINT *PX86PGUINT;
1119/** Pointer to an const page table/directory table entry as an unsigned integer. */
1120typedef X86PGUINT const *PCX86PGUINT;
1121
1122/** Number of entries in a 32-bit PT/PD. */
1123#define X86_PG_ENTRIES 1024
1124
1125
1126/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1127typedef uint64_t X86PGPAEUINT;
1128/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1129typedef X86PGPAEUINT *PX86PGPAEUINT;
1130/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1131typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1132
1133/** Number of entries in a PAE PT/PD. */
1134#define X86_PG_PAE_ENTRIES 512
1135/** Number of entries in a PAE PDPT. */
1136#define X86_PG_PAE_PDPE_ENTRIES 4
1137
1138/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1139#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1140/** Number of entries in an AMD64 PDPT.
1141 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1142#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1143
1144/** The size of a 4KB page. */
1145#define X86_PAGE_4K_SIZE _4K
1146/** The page shift of a 4KB page. */
1147#define X86_PAGE_4K_SHIFT 12
1148/** The 4KB page offset mask. */
1149#define X86_PAGE_4K_OFFSET_MASK 0xfff
1150/** The 4KB page base mask for virtual addresses. */
1151#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1152/** The 4KB page base mask for virtual addresses - 32bit version. */
1153#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1154
1155/** The size of a 2MB page. */
1156#define X86_PAGE_2M_SIZE _2M
1157/** The page shift of a 2MB page. */
1158#define X86_PAGE_2M_SHIFT 21
1159/** The 2MB page offset mask. */
1160#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1161/** The 2MB page base mask for virtual addresses. */
1162#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1163/** The 2MB page base mask for virtual addresses - 32bit version. */
1164#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1165
1166/** The size of a 4MB page. */
1167#define X86_PAGE_4M_SIZE _4M
1168/** The page shift of a 4MB page. */
1169#define X86_PAGE_4M_SHIFT 22
1170/** The 4MB page offset mask. */
1171#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1172/** The 4MB page base mask for virtual addresses. */
1173#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1174/** The 4MB page base mask for virtual addresses - 32bit version. */
1175#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1176
1177
1178
1179/** @name Page Table Entry
1180 * @{
1181 */
1182/** Bit 0 - P - Present bit. */
1183#define X86_PTE_BIT_P 0
1184/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1185#define X86_PTE_BIT_RW 1
1186/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1187#define X86_PTE_BIT_US 2
1188/** Bit 3 - PWT - Page level write thru bit. */
1189#define X86_PTE_BIT_PWT 3
1190/** Bit 4 - PCD - Page level cache disable bit. */
1191#define X86_PTE_BIT_PCD 4
1192/** Bit 5 - A - Access bit. */
1193#define X86_PTE_BIT_A 5
1194/** Bit 6 - D - Dirty bit. */
1195#define X86_PTE_BIT_D 6
1196/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1197#define X86_PTE_BIT_PAT 7
1198/** Bit 8 - G - Global flag. */
1199#define X86_PTE_BIT_G 8
1200
1201/** Bit 0 - P - Present bit mask. */
1202#define X86_PTE_P RT_BIT(0)
1203/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1204#define X86_PTE_RW RT_BIT(1)
1205/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1206#define X86_PTE_US RT_BIT(2)
1207/** Bit 3 - PWT - Page level write thru bit mask. */
1208#define X86_PTE_PWT RT_BIT(3)
1209/** Bit 4 - PCD - Page level cache disable bit mask. */
1210#define X86_PTE_PCD RT_BIT(4)
1211/** Bit 5 - A - Access bit mask. */
1212#define X86_PTE_A RT_BIT(5)
1213/** Bit 6 - D - Dirty bit mask. */
1214#define X86_PTE_D RT_BIT(6)
1215/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1216#define X86_PTE_PAT RT_BIT(7)
1217/** Bit 8 - G - Global bit mask. */
1218#define X86_PTE_G RT_BIT(8)
1219
1220/** Bits 9-11 - - Available for use to system software. */
1221#define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1222/** Bits 12-31 - - Physical Page number of the next level. */
1223#define X86_PTE_PG_MASK ( 0xfffff000 )
1224
1225/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1226#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1227/** Bits 63 - NX - PAE/LM - No execution flag. */
1228#define X86_PTE_PAE_NX RT_BIT_64(63)
1229/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1230#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1231/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1232#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1233/** No bits - - LM - MBZ bits when NX is active. */
1234#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1235/** Bits 63 - - LM - MBZ bits when no NX. */
1236#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1237
1238/**
1239 * Page table entry.
1240 */
1241typedef struct X86PTEBITS
1242{
1243 /** Flags whether(=1) or not the page is present. */
1244 unsigned u1Present : 1;
1245 /** Read(=0) / Write(=1) flag. */
1246 unsigned u1Write : 1;
1247 /** User(=1) / Supervisor (=0) flag. */
1248 unsigned u1User : 1;
1249 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1250 unsigned u1WriteThru : 1;
1251 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1252 unsigned u1CacheDisable : 1;
1253 /** Accessed flag.
1254 * Indicates that the page have been read or written to. */
1255 unsigned u1Accessed : 1;
1256 /** Dirty flag.
1257 * Indicates that the page has been written to. */
1258 unsigned u1Dirty : 1;
1259 /** Reserved / If PAT enabled, bit 2 of the index. */
1260 unsigned u1PAT : 1;
1261 /** Global flag. (Ignored in all but final level.) */
1262 unsigned u1Global : 1;
1263 /** Available for use to system software. */
1264 unsigned u3Available : 3;
1265 /** Physical Page number of the next level. */
1266 unsigned u20PageNo : 20;
1267} X86PTEBITS;
1268/** Pointer to a page table entry. */
1269typedef X86PTEBITS *PX86PTEBITS;
1270/** Pointer to a const page table entry. */
1271typedef const X86PTEBITS *PCX86PTEBITS;
1272
1273/**
1274 * Page table entry.
1275 */
1276typedef union X86PTE
1277{
1278 /** Unsigned integer view */
1279 X86PGUINT u;
1280 /** Bit field view. */
1281 X86PTEBITS n;
1282 /** 32-bit view. */
1283 uint32_t au32[1];
1284 /** 16-bit view. */
1285 uint16_t au16[2];
1286 /** 8-bit view. */
1287 uint8_t au8[4];
1288} X86PTE;
1289/** Pointer to a page table entry. */
1290typedef X86PTE *PX86PTE;
1291/** Pointer to a const page table entry. */
1292typedef const X86PTE *PCX86PTE;
1293
1294
1295/**
1296 * PAE page table entry.
1297 */
1298typedef struct X86PTEPAEBITS
1299{
1300 /** Flags whether(=1) or not the page is present. */
1301 uint32_t u1Present : 1;
1302 /** Read(=0) / Write(=1) flag. */
1303 uint32_t u1Write : 1;
1304 /** User(=1) / Supervisor(=0) flag. */
1305 uint32_t u1User : 1;
1306 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1307 uint32_t u1WriteThru : 1;
1308 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1309 uint32_t u1CacheDisable : 1;
1310 /** Accessed flag.
1311 * Indicates that the page have been read or written to. */
1312 uint32_t u1Accessed : 1;
1313 /** Dirty flag.
1314 * Indicates that the page has been written to. */
1315 uint32_t u1Dirty : 1;
1316 /** Reserved / If PAT enabled, bit 2 of the index. */
1317 uint32_t u1PAT : 1;
1318 /** Global flag. (Ignored in all but final level.) */
1319 uint32_t u1Global : 1;
1320 /** Available for use to system software. */
1321 uint32_t u3Available : 3;
1322 /** Physical Page number of the next level - Low Part. Don't use this. */
1323 uint32_t u20PageNoLow : 20;
1324 /** Physical Page number of the next level - High Part. Don't use this. */
1325 uint32_t u20PageNoHigh : 20;
1326 /** MBZ bits */
1327 uint32_t u11Reserved : 11;
1328 /** No Execute flag. */
1329 uint32_t u1NoExecute : 1;
1330} X86PTEPAEBITS;
1331/** Pointer to a page table entry. */
1332typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1333/** Pointer to a page table entry. */
1334typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1335
1336/**
1337 * PAE Page table entry.
1338 */
1339typedef union X86PTEPAE
1340{
1341 /** Unsigned integer view */
1342 X86PGPAEUINT u;
1343 /** Bit field view. */
1344 X86PTEPAEBITS n;
1345 /** 32-bit view. */
1346 uint32_t au32[2];
1347 /** 16-bit view. */
1348 uint16_t au16[4];
1349 /** 8-bit view. */
1350 uint8_t au8[8];
1351} X86PTEPAE;
1352/** Pointer to a PAE page table entry. */
1353typedef X86PTEPAE *PX86PTEPAE;
1354/** Pointer to a const PAE page table entry. */
1355typedef const X86PTEPAE *PCX86PTEPAE;
1356/** @} */
1357
1358/**
1359 * Page table.
1360 */
1361typedef struct X86PT
1362{
1363 /** PTE Array. */
1364 X86PTE a[X86_PG_ENTRIES];
1365} X86PT;
1366/** Pointer to a page table. */
1367typedef X86PT *PX86PT;
1368/** Pointer to a const page table. */
1369typedef const X86PT *PCX86PT;
1370
1371/** The page shift to get the PT index. */
1372#define X86_PT_SHIFT 12
1373/** The PT index mask (apply to a shifted page address). */
1374#define X86_PT_MASK 0x3ff
1375
1376
1377/**
1378 * Page directory.
1379 */
1380typedef struct X86PTPAE
1381{
1382 /** PTE Array. */
1383 X86PTEPAE a[X86_PG_PAE_ENTRIES];
1384} X86PTPAE;
1385/** Pointer to a page table. */
1386typedef X86PTPAE *PX86PTPAE;
1387/** Pointer to a const page table. */
1388typedef const X86PTPAE *PCX86PTPAE;
1389
1390/** The page shift to get the PA PTE index. */
1391#define X86_PT_PAE_SHIFT 12
1392/** The PAE PT index mask (apply to a shifted page address). */
1393#define X86_PT_PAE_MASK 0x1ff
1394
1395
1396/** @name 4KB Page Directory Entry
1397 * @{
1398 */
1399/** Bit 0 - P - Present bit. */
1400#define X86_PDE_P RT_BIT(0)
1401/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1402#define X86_PDE_RW RT_BIT(1)
1403/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1404#define X86_PDE_US RT_BIT(2)
1405/** Bit 3 - PWT - Page level write thru bit. */
1406#define X86_PDE_PWT RT_BIT(3)
1407/** Bit 4 - PCD - Page level cache disable bit. */
1408#define X86_PDE_PCD RT_BIT(4)
1409/** Bit 5 - A - Access bit. */
1410#define X86_PDE_A RT_BIT(5)
1411/** Bit 7 - PS - Page size attribute.
1412 * Clear mean 4KB pages, set means large pages (2/4MB). */
1413#define X86_PDE_PS RT_BIT(7)
1414/** Bits 9-11 - - Available for use to system software. */
1415#define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1416/** Bits 12-31 - - Physical Page number of the next level. */
1417#define X86_PDE_PG_MASK ( 0xfffff000 )
1418
1419/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1420#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1421/** Bits 63 - NX - PAE/LM - No execution flag. */
1422#define X86_PDE_PAE_NX RT_BIT_64(63)
1423/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1424#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1425/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1426#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1427/** Bit 7 - - LM - MBZ bits when NX is active. */
1428#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1429/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1430#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1431
1432/**
1433 * Page directory entry.
1434 */
1435typedef struct X86PDEBITS
1436{
1437 /** Flags whether(=1) or not the page is present. */
1438 unsigned u1Present : 1;
1439 /** Read(=0) / Write(=1) flag. */
1440 unsigned u1Write : 1;
1441 /** User(=1) / Supervisor (=0) flag. */
1442 unsigned u1User : 1;
1443 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1444 unsigned u1WriteThru : 1;
1445 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1446 unsigned u1CacheDisable : 1;
1447 /** Accessed flag.
1448 * Indicates that the page has been read or written to. */
1449 unsigned u1Accessed : 1;
1450 /** Reserved / Ignored (dirty bit). */
1451 unsigned u1Reserved0 : 1;
1452 /** Size bit if PSE is enabled - in any event it's 0. */
1453 unsigned u1Size : 1;
1454 /** Reserved / Ignored (global bit). */
1455 unsigned u1Reserved1 : 1;
1456 /** Available for use to system software. */
1457 unsigned u3Available : 3;
1458 /** Physical Page number of the next level. */
1459 unsigned u20PageNo : 20;
1460} X86PDEBITS;
1461/** Pointer to a page directory entry. */
1462typedef X86PDEBITS *PX86PDEBITS;
1463/** Pointer to a const page directory entry. */
1464typedef const X86PDEBITS *PCX86PDEBITS;
1465
1466
1467/**
1468 * PAE page directory entry.
1469 */
1470typedef struct X86PDEPAEBITS
1471{
1472 /** Flags whether(=1) or not the page is present. */
1473 uint32_t u1Present : 1;
1474 /** Read(=0) / Write(=1) flag. */
1475 uint32_t u1Write : 1;
1476 /** User(=1) / Supervisor (=0) flag. */
1477 uint32_t u1User : 1;
1478 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1479 uint32_t u1WriteThru : 1;
1480 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1481 uint32_t u1CacheDisable : 1;
1482 /** Accessed flag.
1483 * Indicates that the page has been read or written to. */
1484 uint32_t u1Accessed : 1;
1485 /** Reserved / Ignored (dirty bit). */
1486 uint32_t u1Reserved0 : 1;
1487 /** Size bit if PSE is enabled - in any event it's 0. */
1488 uint32_t u1Size : 1;
1489 /** Reserved / Ignored (global bit). / */
1490 uint32_t u1Reserved1 : 1;
1491 /** Available for use to system software. */
1492 uint32_t u3Available : 3;
1493 /** Physical Page number of the next level - Low Part. Don't use! */
1494 uint32_t u20PageNoLow : 20;
1495 /** Physical Page number of the next level - High Part. Don't use! */
1496 uint32_t u20PageNoHigh : 20;
1497 /** MBZ bits */
1498 uint32_t u11Reserved : 11;
1499 /** No Execute flag. */
1500 uint32_t u1NoExecute : 1;
1501} X86PDEPAEBITS;
1502/** Pointer to a page directory entry. */
1503typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1504/** Pointer to a const page directory entry. */
1505typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1506
1507/** @} */
1508
1509
1510/** @name 2/4MB Page Directory Entry
1511 * @{
1512 */
1513/** Bit 0 - P - Present bit. */
1514#define X86_PDE4M_P RT_BIT(0)
1515/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1516#define X86_PDE4M_RW RT_BIT(1)
1517/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1518#define X86_PDE4M_US RT_BIT(2)
1519/** Bit 3 - PWT - Page level write thru bit. */
1520#define X86_PDE4M_PWT RT_BIT(3)
1521/** Bit 4 - PCD - Page level cache disable bit. */
1522#define X86_PDE4M_PCD RT_BIT(4)
1523/** Bit 5 - A - Access bit. */
1524#define X86_PDE4M_A RT_BIT(5)
1525/** Bit 6 - D - Dirty bit. */
1526#define X86_PDE4M_D RT_BIT(6)
1527/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1528#define X86_PDE4M_PS RT_BIT(7)
1529/** Bit 8 - G - Global flag. */
1530#define X86_PDE4M_G RT_BIT(8)
1531/** Bits 9-11 - AVL - Available for use to system software. */
1532#define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1533/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1534#define X86_PDE4M_PAT RT_BIT(12)
1535/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1536#define X86_PDE4M_PAT_SHIFT (12 - 7)
1537/** Bits 22-31 - - Physical Page number. */
1538#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1539/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1540#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1541/** The number of bits to the high part of the page number. */
1542#define X86_PDE4M_PG_HIGH_SHIFT 19
1543/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1544#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1545
1546/** Bits 21-51 - - PAE/LM - Physical Page number.
1547 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1548#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1549/** Bits 63 - NX - PAE/LM - No execution flag. */
1550#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1551/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1552#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1553/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1554#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1555/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1556#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1557/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1558#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1559
1560/**
1561 * 4MB page directory entry.
1562 */
1563typedef struct X86PDE4MBITS
1564{
1565 /** Flags whether(=1) or not the page is present. */
1566 unsigned u1Present : 1;
1567 /** Read(=0) / Write(=1) flag. */
1568 unsigned u1Write : 1;
1569 /** User(=1) / Supervisor (=0) flag. */
1570 unsigned u1User : 1;
1571 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1572 unsigned u1WriteThru : 1;
1573 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1574 unsigned u1CacheDisable : 1;
1575 /** Accessed flag.
1576 * Indicates that the page have been read or written to. */
1577 unsigned u1Accessed : 1;
1578 /** Dirty flag.
1579 * Indicates that the page has been written to. */
1580 unsigned u1Dirty : 1;
1581 /** Page size flag - always 1 for 4MB entries. */
1582 unsigned u1Size : 1;
1583 /** Global flag. */
1584 unsigned u1Global : 1;
1585 /** Available for use to system software. */
1586 unsigned u3Available : 3;
1587 /** Reserved / If PAT enabled, bit 2 of the index. */
1588 unsigned u1PAT : 1;
1589 /** Bits 32-39 of the page number on AMD64.
1590 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1591 unsigned u8PageNoHigh : 8;
1592 /** Reserved. */
1593 unsigned u1Reserved : 1;
1594 /** Physical Page number of the page. */
1595 unsigned u10PageNo : 10;
1596} X86PDE4MBITS;
1597/** Pointer to a page table entry. */
1598typedef X86PDE4MBITS *PX86PDE4MBITS;
1599/** Pointer to a const page table entry. */
1600typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1601
1602
1603/**
1604 * 2MB PAE page directory entry.
1605 */
1606typedef struct X86PDE2MPAEBITS
1607{
1608 /** Flags whether(=1) or not the page is present. */
1609 uint32_t u1Present : 1;
1610 /** Read(=0) / Write(=1) flag. */
1611 uint32_t u1Write : 1;
1612 /** User(=1) / Supervisor(=0) flag. */
1613 uint32_t u1User : 1;
1614 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1615 uint32_t u1WriteThru : 1;
1616 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1617 uint32_t u1CacheDisable : 1;
1618 /** Accessed flag.
1619 * Indicates that the page have been read or written to. */
1620 uint32_t u1Accessed : 1;
1621 /** Dirty flag.
1622 * Indicates that the page has been written to. */
1623 uint32_t u1Dirty : 1;
1624 /** Page size flag - always 1 for 2MB entries. */
1625 uint32_t u1Size : 1;
1626 /** Global flag. */
1627 uint32_t u1Global : 1;
1628 /** Available for use to system software. */
1629 uint32_t u3Available : 3;
1630 /** Reserved / If PAT enabled, bit 2 of the index. */
1631 uint32_t u1PAT : 1;
1632 /** Reserved. */
1633 uint32_t u9Reserved : 9;
1634 /** Physical Page number of the next level - Low part. Don't use! */
1635 uint32_t u10PageNoLow : 10;
1636 /** Physical Page number of the next level - High part. Don't use! */
1637 uint32_t u20PageNoHigh : 20;
1638 /** MBZ bits */
1639 uint32_t u11Reserved : 11;
1640 /** No Execute flag. */
1641 uint32_t u1NoExecute : 1;
1642} X86PDE2MPAEBITS;
1643/** Pointer to a 2MB PAE page table entry. */
1644typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1645/** Pointer to a 2MB PAE page table entry. */
1646typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1647
1648/** @} */
1649
1650/**
1651 * Page directory entry.
1652 */
1653typedef union X86PDE
1654{
1655 /** Unsigned integer view. */
1656 X86PGUINT u;
1657 /** Normal view. */
1658 X86PDEBITS n;
1659 /** 4MB view (big). */
1660 X86PDE4MBITS b;
1661 /** 8 bit unsigned integer view. */
1662 uint8_t au8[4];
1663 /** 16 bit unsigned integer view. */
1664 uint16_t au16[2];
1665 /** 32 bit unsigned integer view. */
1666 uint32_t au32[1];
1667} X86PDE;
1668/** Pointer to a page directory entry. */
1669typedef X86PDE *PX86PDE;
1670/** Pointer to a const page directory entry. */
1671typedef const X86PDE *PCX86PDE;
1672
1673/**
1674 * PAE page directory entry.
1675 */
1676typedef union X86PDEPAE
1677{
1678 /** Unsigned integer view. */
1679 X86PGPAEUINT u;
1680 /** Normal view. */
1681 X86PDEPAEBITS n;
1682 /** 2MB page view (big). */
1683 X86PDE2MPAEBITS b;
1684 /** 8 bit unsigned integer view. */
1685 uint8_t au8[8];
1686 /** 16 bit unsigned integer view. */
1687 uint16_t au16[4];
1688 /** 32 bit unsigned integer view. */
1689 uint32_t au32[2];
1690} X86PDEPAE;
1691/** Pointer to a page directory entry. */
1692typedef X86PDEPAE *PX86PDEPAE;
1693/** Pointer to a const page directory entry. */
1694typedef const X86PDEPAE *PCX86PDEPAE;
1695
1696/**
1697 * Page directory.
1698 */
1699typedef struct X86PD
1700{
1701 /** PDE Array. */
1702 X86PDE a[X86_PG_ENTRIES];
1703} X86PD;
1704/** Pointer to a page directory. */
1705typedef X86PD *PX86PD;
1706/** Pointer to a const page directory. */
1707typedef const X86PD *PCX86PD;
1708
1709/** The page shift to get the PD index. */
1710#define X86_PD_SHIFT 22
1711/** The PD index mask (apply to a shifted page address). */
1712#define X86_PD_MASK 0x3ff
1713
1714
1715/**
1716 * PAE page directory.
1717 */
1718typedef struct X86PDPAE
1719{
1720 /** PDE Array. */
1721 X86PDEPAE a[X86_PG_PAE_ENTRIES];
1722} X86PDPAE;
1723/** Pointer to a PAE page directory. */
1724typedef X86PDPAE *PX86PDPAE;
1725/** Pointer to a const PAE page directory. */
1726typedef const X86PDPAE *PCX86PDPAE;
1727
1728/** The page shift to get the PAE PD index. */
1729#define X86_PD_PAE_SHIFT 21
1730/** The PAE PD index mask (apply to a shifted page address). */
1731#define X86_PD_PAE_MASK 0x1ff
1732
1733
1734/** @name Page Directory Pointer Table Entry (PAE)
1735 * @{
1736 */
1737/** Bit 0 - P - Present bit. */
1738#define X86_PDPE_P RT_BIT(0)
1739/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1740#define X86_PDPE_RW RT_BIT(1)
1741/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1742#define X86_PDPE_US RT_BIT(2)
1743/** Bit 3 - PWT - Page level write thru bit. */
1744#define X86_PDPE_PWT RT_BIT(3)
1745/** Bit 4 - PCD - Page level cache disable bit. */
1746#define X86_PDPE_PCD RT_BIT(4)
1747/** Bit 5 - A - Access bit. Long Mode only. */
1748#define X86_PDPE_A RT_BIT(5)
1749/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1750#define X86_PDPE_LM_PS RT_BIT(7)
1751/** Bits 9-11 - - Available for use to system software. */
1752#define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1753/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1754#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1755/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1756#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1757/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1758#define X86_PDPE_LM_NX RT_BIT_64(63)
1759/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1760#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1761/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1762#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1763/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1764#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1765/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1766#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1767
1768
1769/**
1770 * Page directory pointer table entry.
1771 */
1772typedef struct X86PDPEBITS
1773{
1774 /** Flags whether(=1) or not the page is present. */
1775 uint32_t u1Present : 1;
1776 /** Chunk of reserved bits. */
1777 uint32_t u2Reserved : 2;
1778 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1779 uint32_t u1WriteThru : 1;
1780 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1781 uint32_t u1CacheDisable : 1;
1782 /** Chunk of reserved bits. */
1783 uint32_t u4Reserved : 4;
1784 /** Available for use to system software. */
1785 uint32_t u3Available : 3;
1786 /** Physical Page number of the next level - Low Part. Don't use! */
1787 uint32_t u20PageNoLow : 20;
1788 /** Physical Page number of the next level - High Part. Don't use! */
1789 uint32_t u20PageNoHigh : 20;
1790 /** MBZ bits */
1791 uint32_t u12Reserved : 12;
1792} X86PDPEBITS;
1793/** Pointer to a page directory pointer table entry. */
1794typedef X86PDPEBITS *PX86PTPEBITS;
1795/** Pointer to a const page directory pointer table entry. */
1796typedef const X86PDPEBITS *PCX86PTPEBITS;
1797
1798/**
1799 * Page directory pointer table entry. AMD64 version
1800 */
1801typedef struct X86PDPEAMD64BITS
1802{
1803 /** Flags whether(=1) or not the page is present. */
1804 uint32_t u1Present : 1;
1805 /** Read(=0) / Write(=1) flag. */
1806 uint32_t u1Write : 1;
1807 /** User(=1) / Supervisor (=0) flag. */
1808 uint32_t u1User : 1;
1809 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1810 uint32_t u1WriteThru : 1;
1811 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1812 uint32_t u1CacheDisable : 1;
1813 /** Accessed flag.
1814 * Indicates that the page have been read or written to. */
1815 uint32_t u1Accessed : 1;
1816 /** Chunk of reserved bits. */
1817 uint32_t u3Reserved : 3;
1818 /** Available for use to system software. */
1819 uint32_t u3Available : 3;
1820 /** Physical Page number of the next level - Low Part. Don't use! */
1821 uint32_t u20PageNoLow : 20;
1822 /** Physical Page number of the next level - High Part. Don't use! */
1823 uint32_t u20PageNoHigh : 20;
1824 /** MBZ bits */
1825 uint32_t u11Reserved : 11;
1826 /** No Execute flag. */
1827 uint32_t u1NoExecute : 1;
1828} X86PDPEAMD64BITS;
1829/** Pointer to a page directory pointer table entry. */
1830typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1831/** Pointer to a const page directory pointer table entry. */
1832typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
1833
1834/**
1835 * Page directory pointer table entry.
1836 */
1837typedef union X86PDPE
1838{
1839 /** Unsigned integer view. */
1840 X86PGPAEUINT u;
1841 /** Normal view. */
1842 X86PDPEBITS n;
1843 /** AMD64 view. */
1844 X86PDPEAMD64BITS lm;
1845 /** 8 bit unsigned integer view. */
1846 uint8_t au8[8];
1847 /** 16 bit unsigned integer view. */
1848 uint16_t au16[4];
1849 /** 32 bit unsigned integer view. */
1850 uint32_t au32[2];
1851} X86PDPE;
1852/** Pointer to a page directory pointer table entry. */
1853typedef X86PDPE *PX86PDPE;
1854/** Pointer to a const page directory pointer table entry. */
1855typedef const X86PDPE *PCX86PDPE;
1856
1857
1858/**
1859 * Page directory pointer table.
1860 */
1861typedef struct X86PDPT
1862{
1863 /** PDE Array. */
1864 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1865} X86PDPT;
1866/** Pointer to a page directory pointer table. */
1867typedef X86PDPT *PX86PDPT;
1868/** Pointer to a const page directory pointer table. */
1869typedef const X86PDPT *PCX86PDPT;
1870
1871/** The page shift to get the PDPT index. */
1872#define X86_PDPT_SHIFT 30
1873/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1874#define X86_PDPT_MASK_PAE 0x3
1875/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1876#define X86_PDPT_MASK_AMD64 0x1ff
1877
1878/** @} */
1879
1880
1881/** @name Page Map Level-4 Entry (Long Mode PAE)
1882 * @{
1883 */
1884/** Bit 0 - P - Present bit. */
1885#define X86_PML4E_P RT_BIT(0)
1886/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1887#define X86_PML4E_RW RT_BIT(1)
1888/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1889#define X86_PML4E_US RT_BIT(2)
1890/** Bit 3 - PWT - Page level write thru bit. */
1891#define X86_PML4E_PWT RT_BIT(3)
1892/** Bit 4 - PCD - Page level cache disable bit. */
1893#define X86_PML4E_PCD RT_BIT(4)
1894/** Bit 5 - A - Access bit. */
1895#define X86_PML4E_A RT_BIT(5)
1896/** Bits 9-11 - - Available for use to system software. */
1897#define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1898/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1899#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
1900/** Bits 8, 7 - - MBZ bits when NX is active. */
1901#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1902/** Bits 63, 7 - - MBZ bits when no NX. */
1903#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1904/** Bits 63 - NX - PAE - No execution flag. */
1905#define X86_PML4E_NX RT_BIT_64(63)
1906
1907/**
1908 * Page Map Level-4 Entry
1909 */
1910typedef struct X86PML4EBITS
1911{
1912 /** Flags whether(=1) or not the page is present. */
1913 uint32_t u1Present : 1;
1914 /** Read(=0) / Write(=1) flag. */
1915 uint32_t u1Write : 1;
1916 /** User(=1) / Supervisor (=0) flag. */
1917 uint32_t u1User : 1;
1918 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1919 uint32_t u1WriteThru : 1;
1920 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1921 uint32_t u1CacheDisable : 1;
1922 /** Accessed flag.
1923 * Indicates that the page have been read or written to. */
1924 uint32_t u1Accessed : 1;
1925 /** Chunk of reserved bits. */
1926 uint32_t u3Reserved : 3;
1927 /** Available for use to system software. */
1928 uint32_t u3Available : 3;
1929 /** Physical Page number of the next level - Low Part. Don't use! */
1930 uint32_t u20PageNoLow : 20;
1931 /** Physical Page number of the next level - High Part. Don't use! */
1932 uint32_t u20PageNoHigh : 20;
1933 /** MBZ bits */
1934 uint32_t u11Reserved : 11;
1935 /** No Execute flag. */
1936 uint32_t u1NoExecute : 1;
1937} X86PML4EBITS;
1938/** Pointer to a page map level-4 entry. */
1939typedef X86PML4EBITS *PX86PML4EBITS;
1940/** Pointer to a const page map level-4 entry. */
1941typedef const X86PML4EBITS *PCX86PML4EBITS;
1942
1943/**
1944 * Page Map Level-4 Entry.
1945 */
1946typedef union X86PML4E
1947{
1948 /** Unsigned integer view. */
1949 X86PGPAEUINT u;
1950 /** Normal view. */
1951 X86PML4EBITS n;
1952 /** 8 bit unsigned integer view. */
1953 uint8_t au8[8];
1954 /** 16 bit unsigned integer view. */
1955 uint16_t au16[4];
1956 /** 32 bit unsigned integer view. */
1957 uint32_t au32[2];
1958} X86PML4E;
1959/** Pointer to a page map level-4 entry. */
1960typedef X86PML4E *PX86PML4E;
1961/** Pointer to a const page map level-4 entry. */
1962typedef const X86PML4E *PCX86PML4E;
1963
1964
1965/**
1966 * Page Map Level-4.
1967 */
1968typedef struct X86PML4
1969{
1970 /** PDE Array. */
1971 X86PML4E a[X86_PG_PAE_ENTRIES];
1972} X86PML4;
1973/** Pointer to a page map level-4. */
1974typedef X86PML4 *PX86PML4;
1975/** Pointer to a const page map level-4. */
1976typedef const X86PML4 *PCX86PML4;
1977
1978/** The page shift to get the PML4 index. */
1979#define X86_PML4_SHIFT 39
1980/** The PML4 index mask (apply to a shifted page address). */
1981#define X86_PML4_MASK 0x1ff
1982
1983/** @} */
1984
1985/** @} */
1986
1987
1988/**
1989 * 80-bit MMX/FPU register type.
1990 */
1991typedef struct X86FPUMMX
1992{
1993 uint8_t reg[10];
1994} X86FPUMMX;
1995/** Pointer to a 80-bit MMX/FPU register type. */
1996typedef X86FPUMMX *PX86FPUMMX;
1997/** Pointer to a const 80-bit MMX/FPU register type. */
1998typedef const X86FPUMMX *PCX86FPUMMX;
1999
2000/**
2001 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2002 * @todo verify this...
2003 */
2004#pragma pack(1)
2005typedef struct X86FPUSTATE
2006{
2007 /** 0x00 - Control word. */
2008 uint16_t FCW;
2009 /** 0x02 - Alignment word */
2010 uint16_t Dummy1;
2011 /** 0x04 - Status word. */
2012 uint16_t FSW;
2013 /** 0x06 - Alignment word */
2014 uint16_t Dummy2;
2015 /** 0x08 - Tag word */
2016 uint16_t FTW;
2017 /** 0x0a - Alignment word */
2018 uint16_t Dummy3;
2019
2020 /** 0x0c - Instruction pointer. */
2021 uint32_t FPUIP;
2022 /** 0x10 - Code selector. */
2023 uint16_t CS;
2024 /** 0x12 - Opcode. */
2025 uint16_t FOP;
2026 /** 0x14 - FOO. */
2027 uint32_t FPUOO;
2028 /** 0x18 - FOS. */
2029 uint32_t FPUOS;
2030 /** 0x1c */
2031 union
2032 {
2033 /** MMX view. */
2034 uint64_t mmx;
2035 /** FPU view - todo. */
2036 X86FPUMMX fpu;
2037 /** Extended precision floating point view. */
2038 RTFLOAT80U r80;
2039 /** Extended precision floating point view v2. */
2040 RTFLOAT80U2 r80Ex;
2041 /** 8-bit view. */
2042 uint8_t au8[16];
2043 /** 16-bit view. */
2044 uint16_t au16[8];
2045 /** 32-bit view. */
2046 uint32_t au32[4];
2047 /** 64-bit view. */
2048 uint64_t au64[2];
2049 /** 128-bit view. (yeah, very helpful) */
2050 uint128_t au128[1];
2051 } regs[8];
2052} X86FPUSTATE;
2053#pragma pack()
2054/** Pointer to a FPU state. */
2055typedef X86FPUSTATE *PX86FPUSTATE;
2056/** Pointer to a const FPU state. */
2057typedef const X86FPUSTATE *PCX86FPUSTATE;
2058
2059/**
2060 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2061 */
2062#pragma pack(1)
2063typedef struct X86FXSTATE
2064{
2065 /** 0x00 - Control word. */
2066 uint16_t FCW;
2067 /** 0x02 - Status word. */
2068 uint16_t FSW;
2069 /** 0x04 - Tag word. (The upper byte is always zero.) */
2070 uint16_t FTW;
2071 /** 0x06 - Opcode. */
2072 uint16_t FOP;
2073 /** 0x08 - Instruction pointer. */
2074 uint32_t FPUIP;
2075 /** 0x0c - Code selector. */
2076 uint16_t CS;
2077 uint16_t Rsrvd1;
2078 /** 0x10 - Data pointer. */
2079 uint32_t FPUDP;
2080 /** 0x14 - Data segment */
2081 uint16_t DS;
2082 /** 0x16 */
2083 uint16_t Rsrvd2;
2084 /** 0x18 */
2085 uint32_t MXCSR;
2086 /** 0x1c */
2087 uint32_t MXCSR_MASK;
2088 /** 0x20 */
2089 union
2090 {
2091 /** MMX view. */
2092 uint64_t mmx;
2093 /** FPU view - todo. */
2094 X86FPUMMX fpu;
2095 /** Extended precision floating point view. */
2096 RTFLOAT80U r80;
2097 /** Extended precision floating point view v2 */
2098 RTFLOAT80U2 r80Ex;
2099 /** 8-bit view. */
2100 uint8_t au8[16];
2101 /** 16-bit view. */
2102 uint16_t au16[8];
2103 /** 32-bit view. */
2104 uint32_t au32[4];
2105 /** 64-bit view. */
2106 uint64_t au64[2];
2107 /** 128-bit view. (yeah, very helpful) */
2108 uint128_t au128[1];
2109 } aRegs[8];
2110 /* - offset 160 - */
2111 union
2112 {
2113 /** XMM Register view *. */
2114 uint128_t xmm;
2115 /** 8-bit view. */
2116 uint8_t au8[16];
2117 /** 16-bit view. */
2118 uint16_t au16[8];
2119 /** 32-bit view. */
2120 uint32_t au32[4];
2121 /** 64-bit view. */
2122 uint64_t au64[2];
2123 /** 128-bit view. (yeah, very helpful) */
2124 uint128_t au128[1];
2125 } aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2126 /* - offset 416 - */
2127 uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
2128} X86FXSTATE;
2129#pragma pack()
2130/** Pointer to a FPU Extended state. */
2131typedef X86FXSTATE *PX86FXSTATE;
2132/** Pointer to a const FPU Extended state. */
2133typedef const X86FXSTATE *PCX86FXSTATE;
2134
2135/** @name FPU status word flags.
2136 * @{ */
2137/** Exception Flag: Invalid operation. */
2138#define X86_FSW_IE RT_BIT(0)
2139/** Exception Flag: Denormalized operand. */
2140#define X86_FSW_DE RT_BIT(1)
2141/** Exception Flag: Zero divide. */
2142#define X86_FSW_ZE RT_BIT(2)
2143/** Exception Flag: Overflow. */
2144#define X86_FSW_OE RT_BIT(3)
2145/** Exception Flag: Underflow. */
2146#define X86_FSW_UE RT_BIT(4)
2147/** Exception Flag: Precision. */
2148#define X86_FSW_PE RT_BIT(5)
2149/** Stack fault. */
2150#define X86_FSW_SF RT_BIT(6)
2151/** Error summary status. */
2152#define X86_FSW_ES RT_BIT(7)
2153/** Mask of exceptions flags, excluding the summary bit. */
2154#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2155/** Mask of exceptions flags, including the summary bit. */
2156#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2157/** Condition code 0. */
2158#define X86_FSW_C0 RT_BIT(8)
2159/** Condition code 1. */
2160#define X86_FSW_C1 RT_BIT(9)
2161/** Condition code 2. */
2162#define X86_FSW_C2 RT_BIT(10)
2163/** Top of the stack mask. */
2164#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2165/** TOP shift value. */
2166#define X86_FSW_TOP_SHIFT 11
2167/** Mask for getting TOP value after shifting it right. */
2168#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2169/** Get the TOP value. */
2170#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2171/** Condition code 3. */
2172#define X86_FSW_C3 RT_BIT(14)
2173/** Mask of exceptions flags, including the summary bit. */
2174#define X86_FSW_C_MASK UINT16_C(0x4700)
2175/** FPU busy. */
2176#define X86_FSW_B RT_BIT(15)
2177/** @} */
2178
2179
2180/** @name FPU control word flags.
2181 * @{ */
2182/** Exception Mask: Invalid operation. */
2183#define X86_FCW_IM RT_BIT(0)
2184/** Exception Mask: Denormalized operand. */
2185#define X86_FCW_DM RT_BIT(1)
2186/** Exception Mask: Zero divide. */
2187#define X86_FCW_ZM RT_BIT(2)
2188/** Exception Mask: Overflow. */
2189#define X86_FCW_OM RT_BIT(3)
2190/** Exception Mask: Underflow. */
2191#define X86_FCW_UM RT_BIT(4)
2192/** Exception Mask: Precision. */
2193#define X86_FCW_PM RT_BIT(5)
2194/** Mask all exceptions, the value typically loaded (by for instance fninit).
2195 * @remarks This includes reserved bit 6. */
2196#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2197/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2198#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2199/** Precision control mask. */
2200#define X86_FCW_PC_MASK UINT16_C(0x0300)
2201/** Precision control: 24-bit. */
2202#define X86_FCW_PC_24 UINT16_C(0x0000)
2203/** Precision control: Reserved. */
2204#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2205/** Precision control: 53-bit. */
2206#define X86_FCW_PC_53 UINT16_C(0x0200)
2207/** Precision control: 64-bit. */
2208#define X86_FCW_PC_64 UINT16_C(0x0300)
2209/** Rounding control mask. */
2210#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2211/** Rounding control: To nearest. */
2212#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2213/** Rounding control: Down. */
2214#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2215/** Rounding control: Up. */
2216#define X86_FCW_RC_UP UINT16_C(0x0800)
2217/** Rounding control: Towards zero. */
2218#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2219/** Bits which should be zero, apparently. */
2220#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2221/** @} */
2222
2223
2224/** @name Selector Descriptor
2225 * @{
2226 */
2227
2228#ifndef VBOX_FOR_DTRACE_LIB
2229/**
2230 * Descriptor attributes.
2231 */
2232typedef struct X86DESCATTRBITS
2233{
2234 /** 00 - Segment Type. */
2235 unsigned u4Type : 4;
2236 /** 04 - Descriptor Type. System(=0) or code/data selector */
2237 unsigned u1DescType : 1;
2238 /** 05 - Descriptor Privelege level. */
2239 unsigned u2Dpl : 2;
2240 /** 07 - Flags selector present(=1) or not. */
2241 unsigned u1Present : 1;
2242 /** 08 - Segment limit 16-19. */
2243 unsigned u4LimitHigh : 4;
2244 /** 0c - Available for system software. */
2245 unsigned u1Available : 1;
2246 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2247 unsigned u1Long : 1;
2248 /** 0e - This flags meaning depends on the segment type. Try make sense out
2249 * of the intel manual yourself. */
2250 unsigned u1DefBig : 1;
2251 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
2252 * clear byte. */
2253 unsigned u1Granularity : 1;
2254} X86DESCATTRBITS;
2255#endif /* !VBOX_FOR_DTRACE_LIB */
2256
2257#pragma pack(1)
2258typedef union X86DESCATTR
2259{
2260 /** Unsigned integer view. */
2261 uint32_t u;
2262#ifndef VBOX_FOR_DTRACE_LIB
2263 /** Normal view. */
2264 X86DESCATTRBITS n;
2265#endif
2266} X86DESCATTR;
2267#pragma pack()
2268/** Pointer to descriptor attributes. */
2269typedef X86DESCATTR *PX86DESCATTR;
2270/** Pointer to const descriptor attributes. */
2271typedef const X86DESCATTR *PCX86DESCATTR;
2272
2273#ifndef VBOX_FOR_DTRACE_LIB
2274
2275/**
2276 * Generic descriptor table entry
2277 */
2278#pragma pack(1)
2279typedef struct X86DESCGENERIC
2280{
2281 /** Limit - Low word. */
2282 unsigned u16LimitLow : 16;
2283 /** Base address - lowe word.
2284 * Don't try set this to 24 because MSC is doing stupid things then. */
2285 unsigned u16BaseLow : 16;
2286 /** Base address - first 8 bits of high word. */
2287 unsigned u8BaseHigh1 : 8;
2288 /** Segment Type. */
2289 unsigned u4Type : 4;
2290 /** Descriptor Type. System(=0) or code/data selector */
2291 unsigned u1DescType : 1;
2292 /** Descriptor Privelege level. */
2293 unsigned u2Dpl : 2;
2294 /** Flags selector present(=1) or not. */
2295 unsigned u1Present : 1;
2296 /** Segment limit 16-19. */
2297 unsigned u4LimitHigh : 4;
2298 /** Available for system software. */
2299 unsigned u1Available : 1;
2300 /** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2301 unsigned u1Long : 1;
2302 /** This flags meaning depends on the segment type. Try make sense out
2303 * of the intel manual yourself. */
2304 unsigned u1DefBig : 1;
2305 /** Granularity of the limit. If set 4KB granularity is used, if
2306 * clear byte. */
2307 unsigned u1Granularity : 1;
2308 /** Base address - highest 8 bits. */
2309 unsigned u8BaseHigh2 : 8;
2310} X86DESCGENERIC;
2311#pragma pack()
2312/** Pointer to a generic descriptor entry. */
2313typedef X86DESCGENERIC *PX86DESCGENERIC;
2314/** Pointer to a const generic descriptor entry. */
2315typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2316
2317/** @name Bit offsets of X86DESCGENERIC members.
2318 * @{*/
2319#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
2320#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
2321#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
2322#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
2323#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
2324#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
2325#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
2326#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
2327#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
2328#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
2329#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
2330#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
2331#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
2332/** @} */
2333
2334/**
2335 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2336 */
2337typedef struct X86DESCGATE
2338{
2339 /** 00 - Target code segment offset - Low word.
2340 * Ignored if task-gate. */
2341 unsigned u16OffsetLow : 16;
2342 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2343 * TSS selector if task-gate. */
2344 unsigned u16Sel : 16;
2345 /** 20 - Number of parameters for a call-gate.
2346 * Ignored if interrupt-, trap- or task-gate. */
2347 unsigned u4ParmCount : 4;
2348 /** 24 - Reserved / ignored. */
2349 unsigned u4Reserved : 4;
2350 /** 28 - Segment Type. */
2351 unsigned u4Type : 4;
2352 /** 2c - Descriptor Type (0 = system). */
2353 unsigned u1DescType : 1;
2354 /** 2d - Descriptor Privelege level. */
2355 unsigned u2Dpl : 2;
2356 /** 2f - Flags selector present(=1) or not. */
2357 unsigned u1Present : 1;
2358 /** 30 - Target code segment offset - High word.
2359 * Ignored if task-gate. */
2360 unsigned u16OffsetHigh : 16;
2361} X86DESCGATE;
2362/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2363typedef X86DESCGATE *PX86DESCGATE;
2364/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2365typedef const X86DESCGATE *PCX86DESCGATE;
2366
2367#endif /* VBOX_FOR_DTRACE_LIB */
2368
2369/**
2370 * Descriptor table entry.
2371 */
2372#pragma pack(1)
2373typedef union X86DESC
2374{
2375#ifndef VBOX_FOR_DTRACE_LIB
2376 /** Generic descriptor view. */
2377 X86DESCGENERIC Gen;
2378 /** Gate descriptor view. */
2379 X86DESCGATE Gate;
2380#endif
2381
2382 /** 8 bit unsigned integer view. */
2383 uint8_t au8[8];
2384 /** 16 bit unsigned integer view. */
2385 uint16_t au16[4];
2386 /** 32 bit unsigned integer view. */
2387 uint32_t au32[2];
2388 /** 64 bit unsigned integer view. */
2389 uint64_t au64[1];
2390 /** Unsigned integer view. */
2391 uint64_t u;
2392} X86DESC;
2393#ifndef VBOX_FOR_DTRACE_LIB
2394AssertCompileSize(X86DESC, 8);
2395#endif
2396#pragma pack()
2397/** Pointer to descriptor table entry. */
2398typedef X86DESC *PX86DESC;
2399/** Pointer to const descriptor table entry. */
2400typedef const X86DESC *PCX86DESC;
2401
2402/** @def X86DESC_BASE
2403 * Return the base address of a descriptor.
2404 */
2405#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
2406 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2407 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2408 | ( (a_pDesc)->Gen.u16BaseLow ) )
2409
2410/** @def X86DESC_LIMIT
2411 * Return the limit of a descriptor.
2412 */
2413#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
2414 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
2415 | ( (a_pDesc)->Gen.u16LimitLow ) )
2416
2417/** @def X86DESC_LIMIT_G
2418 * Return the limit of a descriptor with the granularity bit taken into account.
2419 * @returns Selector limit (uint32_t).
2420 * @param a_pDesc Pointer to the descriptor.
2421 */
2422#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
2423 ( (a_pDesc)->Gen.u1Granularity \
2424 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
2425 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
2426 )
2427
2428/** @def X86DESC_GET_HID_ATTR
2429 * Get the descriptor attributes for the hidden register.
2430 */
2431#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
2432 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
2433
2434#ifndef VBOX_FOR_DTRACE_LIB
2435
2436/**
2437 * 64 bits generic descriptor table entry
2438 * Note: most of these bits have no meaning in long mode.
2439 */
2440#pragma pack(1)
2441typedef struct X86DESC64GENERIC
2442{
2443 /** Limit - Low word - *IGNORED*. */
2444 unsigned u16LimitLow : 16;
2445 /** Base address - low word. - *IGNORED*
2446 * Don't try set this to 24 because MSC is doing stupid things then. */
2447 unsigned u16BaseLow : 16;
2448 /** Base address - first 8 bits of high word. - *IGNORED* */
2449 unsigned u8BaseHigh1 : 8;
2450 /** Segment Type. */
2451 unsigned u4Type : 4;
2452 /** Descriptor Type. System(=0) or code/data selector */
2453 unsigned u1DescType : 1;
2454 /** Descriptor Privelege level. */
2455 unsigned u2Dpl : 2;
2456 /** Flags selector present(=1) or not. */
2457 unsigned u1Present : 1;
2458 /** Segment limit 16-19. - *IGNORED* */
2459 unsigned u4LimitHigh : 4;
2460 /** Available for system software. - *IGNORED* */
2461 unsigned u1Available : 1;
2462 /** Long mode flag. */
2463 unsigned u1Long : 1;
2464 /** This flags meaning depends on the segment type. Try make sense out
2465 * of the intel manual yourself. */
2466 unsigned u1DefBig : 1;
2467 /** Granularity of the limit. If set 4KB granularity is used, if
2468 * clear byte. - *IGNORED* */
2469 unsigned u1Granularity : 1;
2470 /** Base address - highest 8 bits. - *IGNORED* */
2471 unsigned u8BaseHigh2 : 8;
2472 /** Base address - bits 63-32. */
2473 unsigned u32BaseHigh3 : 32;
2474 unsigned u8Reserved : 8;
2475 unsigned u5Zeros : 5;
2476 unsigned u19Reserved : 19;
2477} X86DESC64GENERIC;
2478#pragma pack()
2479/** Pointer to a generic descriptor entry. */
2480typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2481/** Pointer to a const generic descriptor entry. */
2482typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2483
2484/**
2485 * System descriptor table entry (64 bits)
2486 *
2487 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2488 */
2489#pragma pack(1)
2490typedef struct X86DESC64SYSTEM
2491{
2492 /** Limit - Low word. */
2493 unsigned u16LimitLow : 16;
2494 /** Base address - lowe word.
2495 * Don't try set this to 24 because MSC is doing stupid things then. */
2496 unsigned u16BaseLow : 16;
2497 /** Base address - first 8 bits of high word. */
2498 unsigned u8BaseHigh1 : 8;
2499 /** Segment Type. */
2500 unsigned u4Type : 4;
2501 /** Descriptor Type. System(=0) or code/data selector */
2502 unsigned u1DescType : 1;
2503 /** Descriptor Privelege level. */
2504 unsigned u2Dpl : 2;
2505 /** Flags selector present(=1) or not. */
2506 unsigned u1Present : 1;
2507 /** Segment limit 16-19. */
2508 unsigned u4LimitHigh : 4;
2509 /** Available for system software. */
2510 unsigned u1Available : 1;
2511 /** Reserved - 0. */
2512 unsigned u1Reserved : 1;
2513 /** This flags meaning depends on the segment type. Try make sense out
2514 * of the intel manual yourself. */
2515 unsigned u1DefBig : 1;
2516 /** Granularity of the limit. If set 4KB granularity is used, if
2517 * clear byte. */
2518 unsigned u1Granularity : 1;
2519 /** Base address - bits 31-24. */
2520 unsigned u8BaseHigh2 : 8;
2521 /** Base address - bits 63-32. */
2522 unsigned u32BaseHigh3 : 32;
2523 unsigned u8Reserved : 8;
2524 unsigned u5Zeros : 5;
2525 unsigned u19Reserved : 19;
2526} X86DESC64SYSTEM;
2527#pragma pack()
2528/** Pointer to a system descriptor entry. */
2529typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2530/** Pointer to a const system descriptor entry. */
2531typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2532
2533/**
2534 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2535 */
2536typedef struct X86DESC64GATE
2537{
2538 /** Target code segment offset - Low word. */
2539 unsigned u16OffsetLow : 16;
2540 /** Target code segment selector. */
2541 unsigned u16Sel : 16;
2542 /** Interrupt stack table for interrupt- and trap-gates.
2543 * Ignored by call-gates. */
2544 unsigned u3IST : 3;
2545 /** Reserved / ignored. */
2546 unsigned u5Reserved : 5;
2547 /** Segment Type. */
2548 unsigned u4Type : 4;
2549 /** Descriptor Type (0 = system). */
2550 unsigned u1DescType : 1;
2551 /** Descriptor Privelege level. */
2552 unsigned u2Dpl : 2;
2553 /** Flags selector present(=1) or not. */
2554 unsigned u1Present : 1;
2555 /** Target code segment offset - High word.
2556 * Ignored if task-gate. */
2557 unsigned u16OffsetHigh : 16;
2558 /** Target code segment offset - Top dword.
2559 * Ignored if task-gate. */
2560 unsigned u32OffsetTop : 32;
2561 /** Reserved / ignored / must be zero.
2562 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2563 unsigned u32Reserved : 32;
2564} X86DESC64GATE;
2565AssertCompileSize(X86DESC64GATE, 16);
2566/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2567typedef X86DESC64GATE *PX86DESC64GATE;
2568/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2569typedef const X86DESC64GATE *PCX86DESC64GATE;
2570
2571#endif /* VBOX_FOR_DTRACE_LIB */
2572
2573/**
2574 * Descriptor table entry.
2575 */
2576#pragma pack(1)
2577typedef union X86DESC64
2578{
2579#ifndef VBOX_FOR_DTRACE_LIB
2580 /** Generic descriptor view. */
2581 X86DESC64GENERIC Gen;
2582 /** System descriptor view. */
2583 X86DESC64SYSTEM System;
2584 /** Gate descriptor view. */
2585 X86DESC64GATE Gate;
2586#endif
2587
2588 /** 8 bit unsigned integer view. */
2589 uint8_t au8[16];
2590 /** 16 bit unsigned integer view. */
2591 uint16_t au16[8];
2592 /** 32 bit unsigned integer view. */
2593 uint32_t au32[4];
2594 /** 64 bit unsigned integer view. */
2595 uint64_t au64[2];
2596} X86DESC64;
2597#ifndef VBOX_FOR_DTRACE_LIB
2598AssertCompileSize(X86DESC64, 16);
2599#endif
2600#pragma pack()
2601/** Pointer to descriptor table entry. */
2602typedef X86DESC64 *PX86DESC64;
2603/** Pointer to const descriptor table entry. */
2604typedef const X86DESC64 *PCX86DESC64;
2605
2606/** @def X86DESC64_BASE
2607 * Return the base of a 64-bit descriptor.
2608 */
2609#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
2610 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
2611 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2612 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2613 | ( (a_pDesc)->Gen.u16BaseLow ) )
2614
2615
2616
2617/** @name Host system descriptor table entry - Use with care!
2618 * @{ */
2619/** Host system descriptor table entry. */
2620#if HC_ARCH_BITS == 64
2621typedef X86DESC64 X86DESCHC;
2622#else
2623typedef X86DESC X86DESCHC;
2624#endif
2625/** Pointer to a host system descriptor table entry. */
2626#if HC_ARCH_BITS == 64
2627typedef PX86DESC64 PX86DESCHC;
2628#else
2629typedef PX86DESC PX86DESCHC;
2630#endif
2631/** Pointer to a const host system descriptor table entry. */
2632#if HC_ARCH_BITS == 64
2633typedef PCX86DESC64 PCX86DESCHC;
2634#else
2635typedef PCX86DESC PCX86DESCHC;
2636#endif
2637/** @} */
2638
2639
2640/** @name Selector Descriptor Types.
2641 * @{
2642 */
2643
2644/** @name Non-System Selector Types.
2645 * @{ */
2646/** Code(=set)/Data(=clear) bit. */
2647#define X86_SEL_TYPE_CODE 8
2648/** Memory(=set)/System(=clear) bit. */
2649#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2650/** Accessed bit. */
2651#define X86_SEL_TYPE_ACCESSED 1
2652/** Expand down bit (for data selectors only). */
2653#define X86_SEL_TYPE_DOWN 4
2654/** Conforming bit (for code selectors only). */
2655#define X86_SEL_TYPE_CONF 4
2656/** Write bit (for data selectors only). */
2657#define X86_SEL_TYPE_WRITE 2
2658/** Read bit (for code selectors only). */
2659#define X86_SEL_TYPE_READ 2
2660/** The bit number of the code segment read bit (relative to u4Type). */
2661#define X86_SEL_TYPE_READ_BIT 1
2662
2663/** Read only selector type. */
2664#define X86_SEL_TYPE_RO 0
2665/** Accessed read only selector type. */
2666#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
2667/** Read write selector type. */
2668#define X86_SEL_TYPE_RW 2
2669/** Accessed read write selector type. */
2670#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
2671/** Expand down read only selector type. */
2672#define X86_SEL_TYPE_RO_DOWN 4
2673/** Accessed expand down read only selector type. */
2674#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
2675/** Expand down read write selector type. */
2676#define X86_SEL_TYPE_RW_DOWN 6
2677/** Accessed expand down read write selector type. */
2678#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
2679/** Execute only selector type. */
2680#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
2681/** Accessed execute only selector type. */
2682#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2683/** Execute and read selector type. */
2684#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
2685/** Accessed execute and read selector type. */
2686#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2687/** Conforming execute only selector type. */
2688#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
2689/** Accessed Conforming execute only selector type. */
2690#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2691/** Conforming execute and write selector type. */
2692#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
2693/** Accessed Conforming execute and write selector type. */
2694#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2695/** @} */
2696
2697
2698/** @name System Selector Types.
2699 * @{ */
2700/** The TSS busy bit mask. */
2701#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
2702
2703/** Undefined system selector type. */
2704#define X86_SEL_TYPE_SYS_UNDEFINED 0
2705/** 286 TSS selector. */
2706#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2707/** LDT selector. */
2708#define X86_SEL_TYPE_SYS_LDT 2
2709/** 286 TSS selector - Busy. */
2710#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2711/** 286 Callgate selector. */
2712#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2713/** Taskgate selector. */
2714#define X86_SEL_TYPE_SYS_TASK_GATE 5
2715/** 286 Interrupt gate selector. */
2716#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2717/** 286 Trapgate selector. */
2718#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2719/** Undefined system selector. */
2720#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2721/** 386 TSS selector. */
2722#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2723/** Undefined system selector. */
2724#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2725/** 386 TSS selector - Busy. */
2726#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2727/** 386 Callgate selector. */
2728#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2729/** Undefined system selector. */
2730#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2731/** 386 Interruptgate selector. */
2732#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2733/** 386 Trapgate selector. */
2734#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2735/** @} */
2736
2737/** @name AMD64 System Selector Types.
2738 * @{ */
2739/** LDT selector. */
2740#define AMD64_SEL_TYPE_SYS_LDT 2
2741/** TSS selector - Busy. */
2742#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2743/** TSS selector - Busy. */
2744#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2745/** Callgate selector. */
2746#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2747/** Interruptgate selector. */
2748#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2749/** Trapgate selector. */
2750#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2751/** @} */
2752
2753/** @} */
2754
2755
2756/** @name Descriptor Table Entry Flag Masks.
2757 * These are for the 2nd 32-bit word of a descriptor.
2758 * @{ */
2759/** Bits 8-11 - TYPE - Descriptor type mask. */
2760#define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
2761/** Bit 12 - S - System (=0) or Code/Data (=1). */
2762#define X86_DESC_S RT_BIT(12)
2763/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2764#define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
2765/** Bit 15 - P - Present. */
2766#define X86_DESC_P RT_BIT(15)
2767/** Bit 20 - AVL - Available for system software. */
2768#define X86_DESC_AVL RT_BIT(20)
2769/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2770#define X86_DESC_DB RT_BIT(22)
2771/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2772 * used, if clear byte. */
2773#define X86_DESC_G RT_BIT(23)
2774/** @} */
2775
2776/** @} */
2777
2778
2779/** @name Task Segments.
2780 * @{
2781 */
2782
2783/**
2784 * 16-bit Task Segment (TSS).
2785 */
2786#pragma pack(1)
2787typedef struct X86TSS16
2788{
2789 /** Back link to previous task. (static) */
2790 RTSEL selPrev;
2791 /** Ring-0 stack pointer. (static) */
2792 uint16_t sp0;
2793 /** Ring-0 stack segment. (static) */
2794 RTSEL ss0;
2795 /** Ring-1 stack pointer. (static) */
2796 uint16_t sp1;
2797 /** Ring-1 stack segment. (static) */
2798 RTSEL ss1;
2799 /** Ring-2 stack pointer. (static) */
2800 uint16_t sp2;
2801 /** Ring-2 stack segment. (static) */
2802 RTSEL ss2;
2803 /** IP before task switch. */
2804 uint16_t ip;
2805 /** FLAGS before task switch. */
2806 uint16_t flags;
2807 /** AX before task switch. */
2808 uint16_t ax;
2809 /** CX before task switch. */
2810 uint16_t cx;
2811 /** DX before task switch. */
2812 uint16_t dx;
2813 /** BX before task switch. */
2814 uint16_t bx;
2815 /** SP before task switch. */
2816 uint16_t sp;
2817 /** BP before task switch. */
2818 uint16_t bp;
2819 /** SI before task switch. */
2820 uint16_t si;
2821 /** DI before task switch. */
2822 uint16_t di;
2823 /** ES before task switch. */
2824 RTSEL es;
2825 /** CS before task switch. */
2826 RTSEL cs;
2827 /** SS before task switch. */
2828 RTSEL ss;
2829 /** DS before task switch. */
2830 RTSEL ds;
2831 /** LDTR before task switch. */
2832 RTSEL selLdt;
2833} X86TSS16;
2834#ifndef VBOX_FOR_DTRACE_LIB
2835AssertCompileSize(X86TSS16, 44);
2836#endif
2837#pragma pack()
2838/** Pointer to a 16-bit task segment. */
2839typedef X86TSS16 *PX86TSS16;
2840/** Pointer to a const 16-bit task segment. */
2841typedef const X86TSS16 *PCX86TSS16;
2842
2843
2844/**
2845 * 32-bit Task Segment (TSS).
2846 */
2847#pragma pack(1)
2848typedef struct X86TSS32
2849{
2850 /** Back link to previous task. (static) */
2851 RTSEL selPrev;
2852 uint16_t padding1;
2853 /** Ring-0 stack pointer. (static) */
2854 uint32_t esp0;
2855 /** Ring-0 stack segment. (static) */
2856 RTSEL ss0;
2857 uint16_t padding_ss0;
2858 /** Ring-1 stack pointer. (static) */
2859 uint32_t esp1;
2860 /** Ring-1 stack segment. (static) */
2861 RTSEL ss1;
2862 uint16_t padding_ss1;
2863 /** Ring-2 stack pointer. (static) */
2864 uint32_t esp2;
2865 /** Ring-2 stack segment. (static) */
2866 RTSEL ss2;
2867 uint16_t padding_ss2;
2868 /** Page directory for the task. (static) */
2869 uint32_t cr3;
2870 /** EIP before task switch. */
2871 uint32_t eip;
2872 /** EFLAGS before task switch. */
2873 uint32_t eflags;
2874 /** EAX before task switch. */
2875 uint32_t eax;
2876 /** ECX before task switch. */
2877 uint32_t ecx;
2878 /** EDX before task switch. */
2879 uint32_t edx;
2880 /** EBX before task switch. */
2881 uint32_t ebx;
2882 /** ESP before task switch. */
2883 uint32_t esp;
2884 /** EBP before task switch. */
2885 uint32_t ebp;
2886 /** ESI before task switch. */
2887 uint32_t esi;
2888 /** EDI before task switch. */
2889 uint32_t edi;
2890 /** ES before task switch. */
2891 RTSEL es;
2892 uint16_t padding_es;
2893 /** CS before task switch. */
2894 RTSEL cs;
2895 uint16_t padding_cs;
2896 /** SS before task switch. */
2897 RTSEL ss;
2898 uint16_t padding_ss;
2899 /** DS before task switch. */
2900 RTSEL ds;
2901 uint16_t padding_ds;
2902 /** FS before task switch. */
2903 RTSEL fs;
2904 uint16_t padding_fs;
2905 /** GS before task switch. */
2906 RTSEL gs;
2907 uint16_t padding_gs;
2908 /** LDTR before task switch. */
2909 RTSEL selLdt;
2910 uint16_t padding_ldt;
2911 /** Debug trap flag */
2912 uint16_t fDebugTrap;
2913 /** Offset relative to the TSS of the start of the I/O Bitmap
2914 * and the end of the interrupt redirection bitmap. */
2915 uint16_t offIoBitmap;
2916 /** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2917 uint8_t IntRedirBitmap[32];
2918} X86TSS32;
2919#pragma pack()
2920/** Pointer to task segment. */
2921typedef X86TSS32 *PX86TSS32;
2922/** Pointer to const task segment. */
2923typedef const X86TSS32 *PCX86TSS32;
2924
2925
2926/**
2927 * 64-bit Task segment.
2928 */
2929#pragma pack(1)
2930typedef struct X86TSS64
2931{
2932 /** Reserved. */
2933 uint32_t u32Reserved;
2934 /** Ring-0 stack pointer. (static) */
2935 uint64_t rsp0;
2936 /** Ring-1 stack pointer. (static) */
2937 uint64_t rsp1;
2938 /** Ring-2 stack pointer. (static) */
2939 uint64_t rsp2;
2940 /** Reserved. */
2941 uint32_t u32Reserved2[2];
2942 /* IST */
2943 uint64_t ist1;
2944 uint64_t ist2;
2945 uint64_t ist3;
2946 uint64_t ist4;
2947 uint64_t ist5;
2948 uint64_t ist6;
2949 uint64_t ist7;
2950 /* Reserved. */
2951 uint16_t u16Reserved[5];
2952 /** Offset relative to the TSS of the start of the I/O Bitmap
2953 * and the end of the interrupt redirection bitmap. */
2954 uint16_t offIoBitmap;
2955 /** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2956 uint8_t IntRedirBitmap[32];
2957} X86TSS64;
2958#pragma pack()
2959/** Pointer to a 64-bit task segment. */
2960typedef X86TSS64 *PX86TSS64;
2961/** Pointer to a const 64-bit task segment. */
2962typedef const X86TSS64 *PCX86TSS64;
2963#ifndef VBOX_FOR_DTRACE_LIB
2964AssertCompileSize(X86TSS64, 136);
2965#endif
2966
2967/** @} */
2968
2969
2970/** @name Selectors.
2971 * @{
2972 */
2973
2974/**
2975 * The shift used to convert a selector from and to index an index (C).
2976 */
2977#define X86_SEL_SHIFT 3
2978
2979/**
2980 * The mask used to mask off the table indicator and RPL of an selector.
2981 */
2982#define X86_SEL_MASK 0xfff8U
2983
2984/**
2985 * The mask used to mask off the RPL of an selector.
2986 * This is suitable for checking for NULL selectors.
2987 */
2988#define X86_SEL_MASK_OFF_RPL 0xfffcU
2989
2990/**
2991 * The bit indicating that a selector is in the LDT and not in the GDT.
2992 */
2993#define X86_SEL_LDT 0x0004U
2994
2995/**
2996 * The bit mask for getting the RPL of a selector.
2997 */
2998#define X86_SEL_RPL 0x0003U
2999
3000/**
3001 * The mask covering both RPL and LDT.
3002 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
3003 * checks.
3004 */
3005#define X86_SEL_RPL_LDT 0x0007U
3006
3007/** @} */
3008
3009
3010/**
3011 * x86 Exceptions/Faults/Traps.
3012 */
3013typedef enum X86XCPT
3014{
3015 /** \#DE - Divide error. */
3016 X86_XCPT_DE = 0x00,
3017 /** \#DB - Debug event (single step, DRx, ..) */
3018 X86_XCPT_DB = 0x01,
3019 /** NMI - Non-Maskable Interrupt */
3020 X86_XCPT_NMI = 0x02,
3021 /** \#BP - Breakpoint (INT3). */
3022 X86_XCPT_BP = 0x03,
3023 /** \#OF - Overflow (INTO). */
3024 X86_XCPT_OF = 0x04,
3025 /** \#BR - Bound range exceeded (BOUND). */
3026 X86_XCPT_BR = 0x05,
3027 /** \#UD - Undefined opcode. */
3028 X86_XCPT_UD = 0x06,
3029 /** \#NM - Device not available (math coprocessor device). */
3030 X86_XCPT_NM = 0x07,
3031 /** \#DF - Double fault. */
3032 X86_XCPT_DF = 0x08,
3033 /** ??? - Coprocessor segment overrun (obsolete). */
3034 X86_XCPT_CO_SEG_OVERRUN = 0x09,
3035 /** \#TS - Taskswitch (TSS). */
3036 X86_XCPT_TS = 0x0a,
3037 /** \#NP - Segment no present. */
3038 X86_XCPT_NP = 0x0b,
3039 /** \#SS - Stack segment fault. */
3040 X86_XCPT_SS = 0x0c,
3041 /** \#GP - General protection fault. */
3042 X86_XCPT_GP = 0x0d,
3043 /** \#PF - Page fault. */
3044 X86_XCPT_PF = 0x0e,
3045 /* 0x0f is reserved. */
3046 /** \#MF - Math fault (FPU). */
3047 X86_XCPT_MF = 0x10,
3048 /** \#AC - Alignment check. */
3049 X86_XCPT_AC = 0x11,
3050 /** \#MC - Machine check. */
3051 X86_XCPT_MC = 0x12,
3052 /** \#XF - SIMD Floating-Pointer Exception. */
3053 X86_XCPT_XF = 0x13
3054} X86XCPT;
3055/** Pointer to a x86 exception code. */
3056typedef X86XCPT *PX86XCPT;
3057/** Pointer to a const x86 exception code. */
3058typedef const X86XCPT *PCX86XCPT;
3059/** The maximum exception value. */
3060#define X86_XCPT_MAX (X86_XCPT_XF)
3061
3062
3063/** @name Trap Error Codes
3064 * @{
3065 */
3066/** External indicator. */
3067#define X86_TRAP_ERR_EXTERNAL 1
3068/** IDT indicator. */
3069#define X86_TRAP_ERR_IDT 2
3070/** Descriptor table indicator - If set LDT, if clear GDT. */
3071#define X86_TRAP_ERR_TI 4
3072/** Mask for getting the selector. */
3073#define X86_TRAP_ERR_SEL_MASK 0xfff8
3074/** Shift for getting the selector table index (C type index). */
3075#define X86_TRAP_ERR_SEL_SHIFT 3
3076/** @} */
3077
3078
3079/** @name \#PF Trap Error Codes
3080 * @{
3081 */
3082/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3083#define X86_TRAP_PF_P RT_BIT(0)
3084/** Bit 1 - R/W - Read (clear) or write (set) access. */
3085#define X86_TRAP_PF_RW RT_BIT(1)
3086/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3087#define X86_TRAP_PF_US RT_BIT(2)
3088/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3089#define X86_TRAP_PF_RSVD RT_BIT(3)
3090/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3091#define X86_TRAP_PF_ID RT_BIT(4)
3092/** @} */
3093
3094#pragma pack(1)
3095/**
3096 * 32-bit IDTR/GDTR.
3097 */
3098typedef struct X86XDTR32
3099{
3100 /** Size of the descriptor table. */
3101 uint16_t cb;
3102 /** Address of the descriptor table. */
3103#ifndef VBOX_FOR_DTRACE_LIB
3104 uint32_t uAddr;
3105#else
3106 uint16_t au16Addr[2];
3107#endif
3108} X86XDTR32, *PX86XDTR32;
3109#pragma pack()
3110
3111#pragma pack(1)
3112/**
3113 * 64-bit IDTR/GDTR.
3114 */
3115typedef struct X86XDTR64
3116{
3117 /** Size of the descriptor table. */
3118 uint16_t cb;
3119 /** Address of the descriptor table. */
3120#ifndef VBOX_FOR_DTRACE_LIB
3121 uint64_t uAddr;
3122#else
3123 uint16_t au16Addr[4];
3124#endif
3125} X86XDTR64, *PX86XDTR64;
3126#pragma pack()
3127
3128
3129/** @name ModR/M
3130 * @{ */
3131#define X86_MODRM_RM_MASK UINT8_C(0x07)
3132#define X86_MODRM_REG_MASK UINT8_C(0x38)
3133#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3134#define X86_MODRM_REG_SHIFT 3
3135#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3136#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3137#define X86_MODRM_MOD_SHIFT 6
3138#ifndef VBOX_FOR_DTRACE_LIB
3139AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
3140AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3141AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3142#endif
3143/** @} */
3144
3145/** @name SIB
3146 * @{ */
3147#define X86_SIB_BASE_MASK UINT8_C(0x07)
3148#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3149#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3150#define X86_SIB_INDEX_SHIFT 3
3151#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3152#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3153#define X86_SIB_SCALE_SHIFT 6
3154#ifndef VBOX_FOR_DTRACE_LIB
3155AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
3156AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3157AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3158#endif
3159/** @} */
3160
3161/** @name General register indexes
3162 * @{ */
3163#define X86_GREG_xAX 0
3164#define X86_GREG_xCX 1
3165#define X86_GREG_xDX 2
3166#define X86_GREG_xBX 3
3167#define X86_GREG_xSP 4
3168#define X86_GREG_xBP 5
3169#define X86_GREG_xSI 6
3170#define X86_GREG_xDI 7
3171#define X86_GREG_x8 8
3172#define X86_GREG_x9 9
3173#define X86_GREG_x10 10
3174#define X86_GREG_x11 11
3175#define X86_GREG_x12 12
3176#define X86_GREG_x13 13
3177#define X86_GREG_x14 14
3178#define X86_GREG_x15 15
3179/** @} */
3180
3181/** @name X86_SREG_XXX - Segment register indexes.
3182 * @{ */
3183#define X86_SREG_ES 0
3184#define X86_SREG_CS 1
3185#define X86_SREG_SS 2
3186#define X86_SREG_DS 3
3187#define X86_SREG_FS 4
3188#define X86_SREG_GS 5
3189/** @} */
3190/** Segment register count. */
3191#define X86_SREG_COUNT 6
3192
3193
3194/** @} */
3195
3196#endif
3197
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