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source: vbox/trunk/include/iprt/x86.h@ 43902

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1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2012 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef ___iprt_x86_h
29#define ___iprt_x86_h
30
31#ifndef VBOX_FOR_DTRACE_LIB
32# include <iprt/types.h>
33# include <iprt/assert.h>
34#else
35# pragma D depends_on library vbox-types.d
36#endif
37
38/* Workaround for Solaris sys/regset.h defining CS, DS */
39#ifdef RT_OS_SOLARIS
40# undef CS
41# undef DS
42#endif
43
44/** @defgroup grp_rt_x86 x86 Types and Definitions
45 * @ingroup grp_rt
46 * @{
47 */
48
49#ifndef VBOX_FOR_DTRACE_LIB
50/**
51 * EFLAGS Bits.
52 */
53typedef struct X86EFLAGSBITS
54{
55 /** Bit 0 - CF - Carry flag - Status flag. */
56 unsigned u1CF : 1;
57 /** Bit 1 - 1 - Reserved flag. */
58 unsigned u1Reserved0 : 1;
59 /** Bit 2 - PF - Parity flag - Status flag. */
60 unsigned u1PF : 1;
61 /** Bit 3 - 0 - Reserved flag. */
62 unsigned u1Reserved1 : 1;
63 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64 unsigned u1AF : 1;
65 /** Bit 5 - 0 - Reserved flag. */
66 unsigned u1Reserved2 : 1;
67 /** Bit 6 - ZF - Zero flag - Status flag. */
68 unsigned u1ZF : 1;
69 /** Bit 7 - SF - Signed flag - Status flag. */
70 unsigned u1SF : 1;
71 /** Bit 8 - TF - Trap flag - System flag. */
72 unsigned u1TF : 1;
73 /** Bit 9 - IF - Interrupt flag - System flag. */
74 unsigned u1IF : 1;
75 /** Bit 10 - DF - Direction flag - Control flag. */
76 unsigned u1DF : 1;
77 /** Bit 11 - OF - Overflow flag - Status flag. */
78 unsigned u1OF : 1;
79 /** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80 unsigned u2IOPL : 2;
81 /** Bit 14 - NT - Nested task flag - System flag. */
82 unsigned u1NT : 1;
83 /** Bit 15 - 0 - Reserved flag. */
84 unsigned u1Reserved3 : 1;
85 /** Bit 16 - RF - Resume flag - System flag. */
86 unsigned u1RF : 1;
87 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
88 unsigned u1VM : 1;
89 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90 unsigned u1AC : 1;
91 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92 unsigned u1VIF : 1;
93 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94 unsigned u1VIP : 1;
95 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96 unsigned u1ID : 1;
97 /** Bit 22-31 - 0 - Reserved flag. */
98 unsigned u10Reserved4 : 10;
99} X86EFLAGSBITS;
100/** Pointer to EFLAGS bits. */
101typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102/** Pointer to const EFLAGS bits. */
103typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104#endif /* !VBOX_FOR_DTRACE_LIB */
105
106/**
107 * EFLAGS.
108 */
109typedef union X86EFLAGS
110{
111 /** The plain unsigned view. */
112 uint32_t u;
113#ifndef VBOX_FOR_DTRACE_LIB
114 /** The bitfield view. */
115 X86EFLAGSBITS Bits;
116#endif
117 /** The 8-bit view. */
118 uint8_t au8[4];
119 /** The 16-bit view. */
120 uint16_t au16[2];
121 /** The 32-bit view. */
122 uint32_t au32[1];
123 /** The 32-bit view. */
124 uint32_t u32;
125} X86EFLAGS;
126/** Pointer to EFLAGS. */
127typedef X86EFLAGS *PX86EFLAGS;
128/** Pointer to const EFLAGS. */
129typedef const X86EFLAGS *PCX86EFLAGS;
130
131/**
132 * RFLAGS (32 upper bits are reserved).
133 */
134typedef union X86RFLAGS
135{
136 /** The plain unsigned view. */
137 uint64_t u;
138#ifndef VBOX_FOR_DTRACE_LIB
139 /** The bitfield view. */
140 X86EFLAGSBITS Bits;
141#endif
142 /** The 8-bit view. */
143 uint8_t au8[8];
144 /** The 16-bit view. */
145 uint16_t au16[4];
146 /** The 32-bit view. */
147 uint32_t au32[2];
148 /** The 64-bit view. */
149 uint64_t au64[1];
150 /** The 64-bit view. */
151 uint64_t u64;
152} X86RFLAGS;
153/** Pointer to RFLAGS. */
154typedef X86RFLAGS *PX86RFLAGS;
155/** Pointer to const RFLAGS. */
156typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159/** @name EFLAGS
160 * @{
161 */
162/** Bit 0 - CF - Carry flag - Status flag. */
163#define X86_EFL_CF RT_BIT(0)
164/** Bit 1 - Reserved, reads as 1. */
165#define X86_EFL_1 RT_BIT(1)
166/** Bit 2 - PF - Parity flag - Status flag. */
167#define X86_EFL_PF RT_BIT(2)
168/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
169#define X86_EFL_AF RT_BIT(4)
170/** Bit 6 - ZF - Zero flag - Status flag. */
171#define X86_EFL_ZF RT_BIT(6)
172/** Bit 7 - SF - Signed flag - Status flag. */
173#define X86_EFL_SF RT_BIT(7)
174/** Bit 8 - TF - Trap flag - System flag. */
175#define X86_EFL_TF RT_BIT(8)
176/** Bit 9 - IF - Interrupt flag - System flag. */
177#define X86_EFL_IF RT_BIT(9)
178/** Bit 10 - DF - Direction flag - Control flag. */
179#define X86_EFL_DF RT_BIT(10)
180/** Bit 11 - OF - Overflow flag - Status flag. */
181#define X86_EFL_OF RT_BIT(11)
182/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
183#define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
184/** Bit 14 - NT - Nested task flag - System flag. */
185#define X86_EFL_NT RT_BIT(14)
186/** Bit 16 - RF - Resume flag - System flag. */
187#define X86_EFL_RF RT_BIT(16)
188/** Bit 17 - VM - Virtual 8086 mode - System flag. */
189#define X86_EFL_VM RT_BIT(17)
190/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
191#define X86_EFL_AC RT_BIT(18)
192/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
193#define X86_EFL_VIF RT_BIT(19)
194/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
195#define X86_EFL_VIP RT_BIT(20)
196/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
197#define X86_EFL_ID RT_BIT(21)
198/** IOPL shift. */
199#define X86_EFL_IOPL_SHIFT 12
200/** The the IOPL level from the flags. */
201#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
202/** Bits restored by popf */
203#define X86_EFL_POPF_BITS (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID)
204/** @} */
205
206
207/** CPUID Feature information - ECX.
208 * CPUID query with EAX=1.
209 */
210#ifndef VBOX_FOR_DTRACE_LIB
211typedef struct X86CPUIDFEATECX
212{
213 /** Bit 0 - SSE3 - Supports SSE3 or not. */
214 unsigned u1SSE3 : 1;
215 /** Bit 1 - PCLMULQDQ. */
216 unsigned u1PCLMULQDQ : 1;
217 /** Bit 2 - DS Area 64-bit layout. */
218 unsigned u1DTE64 : 1;
219 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
220 unsigned u1Monitor : 1;
221 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
222 unsigned u1CPLDS : 1;
223 /** Bit 5 - VMX - Virtual Machine Technology. */
224 unsigned u1VMX : 1;
225 /** Bit 6 - SMX: Safer Mode Extensions. */
226 unsigned u1SMX : 1;
227 /** Bit 7 - EST - Enh. SpeedStep Tech. */
228 unsigned u1EST : 1;
229 /** Bit 8 - TM2 - Terminal Monitor 2. */
230 unsigned u1TM2 : 1;
231 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
232 unsigned u1SSSE3 : 1;
233 /** Bit 10 - CNTX-ID - L1 Context ID. */
234 unsigned u1CNTXID : 1;
235 /** Bit 11 - Reserved. */
236 unsigned u1Reserved1 : 1;
237 /** Bit 12 - FMA. */
238 unsigned u1FMA : 1;
239 /** Bit 13 - CX16 - CMPXCHG16B. */
240 unsigned u1CX16 : 1;
241 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
242 unsigned u1TPRUpdate : 1;
243 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
244 unsigned u1PDCM : 1;
245 /** Bit 16 - Reserved. */
246 unsigned u1Reserved2 : 1;
247 /** Bit 17 - PCID - Process-context identifiers. */
248 unsigned u1PCID : 1;
249 /** Bit 18 - Direct Cache Access. */
250 unsigned u1DCA : 1;
251 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
252 unsigned u1SSE4_1 : 1;
253 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
254 unsigned u1SSE4_2 : 1;
255 /** Bit 21 - x2APIC. */
256 unsigned u1x2APIC : 1;
257 /** Bit 22 - MOVBE - Supports MOVBE. */
258 unsigned u1MOVBE : 1;
259 /** Bit 23 - POPCNT - Supports POPCNT. */
260 unsigned u1POPCNT : 1;
261 /** Bit 24 - TSC-Deadline. */
262 unsigned u1TSCDEADLINE : 1;
263 /** Bit 25 - AES. */
264 unsigned u1AES : 1;
265 /** Bit 26 - XSAVE - Supports XSAVE. */
266 unsigned u1XSAVE : 1;
267 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
268 unsigned u1OSXSAVE : 1;
269 /** Bit 28 - AVX - Supports AVX instruction extensions. */
270 unsigned u1AVX : 1;
271 /** Bit 29 - 30 - Reserved */
272 unsigned u2Reserved3 : 2;
273 /** Bit 31 - Hypervisor present (we're a guest). */
274 unsigned u1HVP : 1;
275} X86CPUIDFEATECX;
276#else /* VBOX_FOR_DTRACE_LIB */
277typedef uint32_t X86CPUIDFEATECX;
278#endif /* VBOX_FOR_DTRACE_LIB */
279/** Pointer to CPUID Feature Information - ECX. */
280typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
281/** Pointer to const CPUID Feature Information - ECX. */
282typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
283
284
285/** CPUID Feature Information - EDX.
286 * CPUID query with EAX=1.
287 */
288#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
289typedef struct X86CPUIDFEATEDX
290{
291 /** Bit 0 - FPU - x87 FPU on Chip. */
292 unsigned u1FPU : 1;
293 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
294 unsigned u1VME : 1;
295 /** Bit 2 - DE - Debugging extensions. */
296 unsigned u1DE : 1;
297 /** Bit 3 - PSE - Page Size Extension. */
298 unsigned u1PSE : 1;
299 /** Bit 4 - TSC - Time Stamp Counter. */
300 unsigned u1TSC : 1;
301 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
302 unsigned u1MSR : 1;
303 /** Bit 6 - PAE - Physical Address Extension. */
304 unsigned u1PAE : 1;
305 /** Bit 7 - MCE - Machine Check Exception. */
306 unsigned u1MCE : 1;
307 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
308 unsigned u1CX8 : 1;
309 /** Bit 9 - APIC - APIC On-Chip. */
310 unsigned u1APIC : 1;
311 /** Bit 10 - Reserved. */
312 unsigned u1Reserved1 : 1;
313 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
314 unsigned u1SEP : 1;
315 /** Bit 12 - MTRR - Memory Type Range Registers. */
316 unsigned u1MTRR : 1;
317 /** Bit 13 - PGE - PTE Global Bit. */
318 unsigned u1PGE : 1;
319 /** Bit 14 - MCA - Machine Check Architecture. */
320 unsigned u1MCA : 1;
321 /** Bit 15 - CMOV - Conditional Move Instructions. */
322 unsigned u1CMOV : 1;
323 /** Bit 16 - PAT - Page Attribute Table. */
324 unsigned u1PAT : 1;
325 /** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
326 unsigned u1PSE36 : 1;
327 /** Bit 18 - PSN - Processor Serial Number. */
328 unsigned u1PSN : 1;
329 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
330 unsigned u1CLFSH : 1;
331 /** Bit 20 - Reserved. */
332 unsigned u1Reserved2 : 1;
333 /** Bit 21 - DS - Debug Store. */
334 unsigned u1DS : 1;
335 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
336 unsigned u1ACPI : 1;
337 /** Bit 23 - MMX - Intel MMX 'Technology'. */
338 unsigned u1MMX : 1;
339 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
340 unsigned u1FXSR : 1;
341 /** Bit 25 - SSE - SSE Support. */
342 unsigned u1SSE : 1;
343 /** Bit 26 - SSE2 - SSE2 Support. */
344 unsigned u1SSE2 : 1;
345 /** Bit 27 - SS - Self Snoop. */
346 unsigned u1SS : 1;
347 /** Bit 28 - HTT - Hyper-Threading Technology. */
348 unsigned u1HTT : 1;
349 /** Bit 29 - TM - Thermal Monitor. */
350 unsigned u1TM : 1;
351 /** Bit 30 - Reserved - . */
352 unsigned u1Reserved3 : 1;
353 /** Bit 31 - PBE - Pending Break Enabled. */
354 unsigned u1PBE : 1;
355} X86CPUIDFEATEDX;
356#else /* VBOX_FOR_DTRACE_LIB */
357typedef uint32_t X86CPUIDFEATEDX;
358#endif /* VBOX_FOR_DTRACE_LIB */
359/** Pointer to CPUID Feature Information - EDX. */
360typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
361/** Pointer to const CPUID Feature Information - EDX. */
362typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
363
364/** @name CPUID Vendor information.
365 * CPUID query with EAX=0.
366 * @{
367 */
368#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
369#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
370#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
371
372#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
373#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
374#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
375
376#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
377#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
378#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
379/** @} */
380
381
382/** @name CPUID Feature information.
383 * CPUID query with EAX=1.
384 * @{
385 */
386/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
387#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
388/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
389#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
390/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
391#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
392/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
393#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
394/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
395#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
396/** ECX Bit 5 - VMX - Virtual Machine Technology. */
397#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
398/** ECX Bit 6 - SMX - Safer Mode Extensions. */
399#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
400/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
401#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
402/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
403#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
404/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
405#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
406/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
407#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
408/** ECX Bit 12 - FMA. */
409#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
410/** ECX Bit 13 - CX16 - CMPXCHG16B. */
411#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
412/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
413#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
414/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
415#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
416/** ECX Bit 17 - PCID - Process-context identifiers. */
417#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
418/** ECX Bit 18 - DCA - Direct Cache Access. */
419#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
420/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
421#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
422/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
423#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
424/** ECX Bit 21 - x2APIC support. */
425#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
426/** ECX Bit 22 - MOVBE instruction. */
427#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
428/** ECX Bit 23 - POPCNT instruction. */
429#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
430/** ECX Bir 24 - TSC-Deadline. */
431#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
432/** ECX Bit 25 - AES instructions. */
433#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
434/** ECX Bit 26 - XSAVE instruction. */
435#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
436/** ECX Bit 27 - OSXSAVE instruction. */
437#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
438/** ECX Bit 28 - AVX. */
439#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
440/** ECX Bit 31 - Hypervisor Present (software only). */
441#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
442
443
444/** Bit 0 - FPU - x87 FPU on Chip. */
445#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
446/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
447#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
448/** Bit 2 - DE - Debugging extensions. */
449#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
450/** Bit 3 - PSE - Page Size Extension. */
451#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
452/** Bit 4 - TSC - Time Stamp Counter. */
453#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
454/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
455#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
456/** Bit 6 - PAE - Physical Address Extension. */
457#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
458/** Bit 7 - MCE - Machine Check Exception. */
459#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
460/** Bit 8 - CX8 - CMPXCHG8B instruction. */
461#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
462/** Bit 9 - APIC - APIC On-Chip. */
463#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
464/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
465#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
466/** Bit 12 - MTRR - Memory Type Range Registers. */
467#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
468/** Bit 13 - PGE - PTE Global Bit. */
469#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
470/** Bit 14 - MCA - Machine Check Architecture. */
471#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
472/** Bit 15 - CMOV - Conditional Move Instructions. */
473#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
474/** Bit 16 - PAT - Page Attribute Table. */
475#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
476/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
477#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
478/** Bit 18 - PSN - Processor Serial Number. */
479#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
480/** Bit 19 - CLFSH - CLFLUSH Instruction. */
481#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
482/** Bit 21 - DS - Debug Store. */
483#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
484/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
485#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
486/** Bit 23 - MMX - Intel MMX Technology. */
487#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
488/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
489#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
490/** Bit 25 - SSE - SSE Support. */
491#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
492/** Bit 26 - SSE2 - SSE2 Support. */
493#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
494/** Bit 27 - SS - Self Snoop. */
495#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
496/** Bit 28 - HTT - Hyper-Threading Technology. */
497#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
498/** Bit 29 - TM - Therm. Monitor. */
499#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
500/** Bit 31 - PBE - Pending Break Enabled. */
501#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
502/** @} */
503
504/** @name CPUID mwait/monitor information.
505 * CPUID query with EAX=5.
506 * @{
507 */
508/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
509#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
510/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
511#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
512/** @} */
513
514
515/** @name CPUID Extended Feature information.
516 * CPUID query with EAX=0x80000001.
517 * @{
518 */
519/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
520#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
521
522/** EDX Bit 11 - SYSCALL/SYSRET. */
523#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
524/** EDX Bit 20 - No-Execute/Execute-Disable. */
525#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
526/** EDX Bit 26 - 1 GB large page. */
527#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
528/** EDX Bit 27 - RDTSCP. */
529#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
530/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
531#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
532/** @}*/
533
534/** @name CPUID AMD Feature information.
535 * CPUID query with EAX=0x80000001.
536 * @{
537 */
538/** Bit 0 - FPU - x87 FPU on Chip. */
539#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
540/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
541#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
542/** Bit 2 - DE - Debugging extensions. */
543#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
544/** Bit 3 - PSE - Page Size Extension. */
545#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
546/** Bit 4 - TSC - Time Stamp Counter. */
547#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
548/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
549#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
550/** Bit 6 - PAE - Physical Address Extension. */
551#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
552/** Bit 7 - MCE - Machine Check Exception. */
553#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
554/** Bit 8 - CX8 - CMPXCHG8B instruction. */
555#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
556/** Bit 9 - APIC - APIC On-Chip. */
557#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
558/** Bit 12 - MTRR - Memory Type Range Registers. */
559#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
560/** Bit 13 - PGE - PTE Global Bit. */
561#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
562/** Bit 14 - MCA - Machine Check Architecture. */
563#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
564/** Bit 15 - CMOV - Conditional Move Instructions. */
565#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
566/** Bit 16 - PAT - Page Attribute Table. */
567#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
568/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
569#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
570/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
571#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
572/** Bit 23 - MMX - Intel MMX Technology. */
573#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
574/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
575#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
576/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
577#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
578/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
579#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
580/** Bit 31 - 3DNOW - AMD 3DNow. */
581#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
582
583/** Bit 1 - CMPL - Core multi-processing legacy mode. */
584#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
585/** Bit 2 - SVM - AMD VM extensions. */
586#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
587/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
588#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
589/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
590#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
591/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
592#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
593/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
594#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
595/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
596#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
597/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
598#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
599/** Bit 9 - OSVW - AMD OS visible workaround. */
600#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
601/** Bit 10 - IBS - Instruct based sampling. */
602#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
603/** Bit 11 - SSE5 - SSE5 instruction support. */
604#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
605/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
606#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
607/** Bit 13 - WDT - AMD Watchdog timer support. */
608#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
609
610/** @} */
611
612
613/** @name CPUID AMD Feature information.
614 * CPUID query with EAX=0x80000007.
615 * @{
616 */
617/** Bit 0 - TS - Temperature Sensor. */
618#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
619/** Bit 1 - FID - Frequency ID Control. */
620#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
621/** Bit 2 - VID - Voltage ID Control. */
622#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
623/** Bit 3 - TTP - THERMTRIP. */
624#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
625/** Bit 4 - TM - Hardware Thermal Control. */
626#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
627/** Bit 5 - STC - Software Thermal Control. */
628#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
629/** Bit 6 - MC - 100 Mhz Multiplier Control. */
630#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
631/** Bit 7 - HWPSTATE - Hardware P-State Control. */
632#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
633/** Bit 8 - TSCINVAR - TSC Invariant. */
634#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
635/** @} */
636
637
638/** @name CR0
639 * @{ */
640/** Bit 0 - PE - Protection Enabled */
641#define X86_CR0_PE RT_BIT(0)
642#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
643/** Bit 1 - MP - Monitor Coprocessor */
644#define X86_CR0_MP RT_BIT(1)
645#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
646/** Bit 2 - EM - Emulation. */
647#define X86_CR0_EM RT_BIT(2)
648#define X86_CR0_EMULATE_FPU RT_BIT(2)
649/** Bit 3 - TS - Task Switch. */
650#define X86_CR0_TS RT_BIT(3)
651#define X86_CR0_TASK_SWITCH RT_BIT(3)
652/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
653#define X86_CR0_ET RT_BIT(4)
654#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
655/** Bit 5 - NE - Numeric error. */
656#define X86_CR0_NE RT_BIT(5)
657#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
658/** Bit 16 - WP - Write Protect. */
659#define X86_CR0_WP RT_BIT(16)
660#define X86_CR0_WRITE_PROTECT RT_BIT(16)
661/** Bit 18 - AM - Alignment Mask. */
662#define X86_CR0_AM RT_BIT(18)
663#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
664/** Bit 29 - NW - Not Write-though. */
665#define X86_CR0_NW RT_BIT(29)
666#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
667/** Bit 30 - WP - Cache Disable. */
668#define X86_CR0_CD RT_BIT(30)
669#define X86_CR0_CACHE_DISABLE RT_BIT(30)
670/** Bit 31 - PG - Paging. */
671#define X86_CR0_PG RT_BIT(31)
672#define X86_CR0_PAGING RT_BIT(31)
673/** @} */
674
675
676/** @name CR3
677 * @{ */
678/** Bit 3 - PWT - Page-level Writes Transparent. */
679#define X86_CR3_PWT RT_BIT(3)
680/** Bit 4 - PCD - Page-level Cache Disable. */
681#define X86_CR3_PCD RT_BIT(4)
682/** Bits 12-31 - - Page directory page number. */
683#define X86_CR3_PAGE_MASK (0xfffff000)
684/** Bits 5-31 - - PAE Page directory page number. */
685#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
686/** Bits 12-51 - - AMD64 Page directory page number. */
687#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
688/** @} */
689
690
691/** @name CR4
692 * @{ */
693/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
694#define X86_CR4_VME RT_BIT(0)
695/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
696#define X86_CR4_PVI RT_BIT(1)
697/** Bit 2 - TSD - Time Stamp Disable. */
698#define X86_CR4_TSD RT_BIT(2)
699/** Bit 3 - DE - Debugging Extensions. */
700#define X86_CR4_DE RT_BIT(3)
701/** Bit 4 - PSE - Page Size Extension. */
702#define X86_CR4_PSE RT_BIT(4)
703/** Bit 5 - PAE - Physical Address Extension. */
704#define X86_CR4_PAE RT_BIT(5)
705/** Bit 6 - MCE - Machine-Check Enable. */
706#define X86_CR4_MCE RT_BIT(6)
707/** Bit 7 - PGE - Page Global Enable. */
708#define X86_CR4_PGE RT_BIT(7)
709/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
710#define X86_CR4_PCE RT_BIT(8)
711/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
712#define X86_CR4_OSFSXR RT_BIT(9)
713/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
714#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
715/** Bit 13 - VMXE - VMX mode is enabled. */
716#define X86_CR4_VMXE RT_BIT(13)
717/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
718#define X86_CR4_SMXE RT_BIT(14)
719/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
720#define X86_CR4_PCIDE RT_BIT(17)
721/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
722 * extended states. */
723#define X86_CR4_OSXSAVE RT_BIT(18)
724/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
725#define X86_CR4_SMEP RT_BIT(20)
726/** @} */
727
728
729/** @name DR6
730 * @{ */
731/** Bit 0 - B0 - Breakpoint 0 condition detected. */
732#define X86_DR6_B0 RT_BIT(0)
733/** Bit 1 - B1 - Breakpoint 1 condition detected. */
734#define X86_DR6_B1 RT_BIT(1)
735/** Bit 2 - B2 - Breakpoint 2 condition detected. */
736#define X86_DR6_B2 RT_BIT(2)
737/** Bit 3 - B3 - Breakpoint 3 condition detected. */
738#define X86_DR6_B3 RT_BIT(3)
739/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
740#define X86_DR6_BD RT_BIT(13)
741/** Bit 14 - BS - Single step */
742#define X86_DR6_BS RT_BIT(14)
743/** Bit 15 - BT - Task switch. (TSS T bit.) */
744#define X86_DR6_BT RT_BIT(15)
745/** Value of DR6 after powerup/reset. */
746#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
747/** @} */
748
749
750/** @name DR7
751 * @{ */
752/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
753#define X86_DR7_L0 RT_BIT(0)
754/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
755#define X86_DR7_G0 RT_BIT(1)
756/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
757#define X86_DR7_L1 RT_BIT(2)
758/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
759#define X86_DR7_G1 RT_BIT(3)
760/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
761#define X86_DR7_L2 RT_BIT(4)
762/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
763#define X86_DR7_G2 RT_BIT(5)
764/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
765#define X86_DR7_L3 RT_BIT(6)
766/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
767#define X86_DR7_G3 RT_BIT(7)
768/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
769#define X86_DR7_LE RT_BIT(8)
770/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
771#define X86_DR7_GE RT_BIT(9)
772
773/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
774 * any DR register is accessed. */
775#define X86_DR7_GD RT_BIT(13)
776/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
777#define X86_DR7_RW0_MASK (3 << 16)
778/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
779#define X86_DR7_LEN0_MASK (3 << 18)
780/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
781#define X86_DR7_RW1_MASK (3 << 20)
782/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
783#define X86_DR7_LEN1_MASK (3 << 22)
784/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
785#define X86_DR7_RW2_MASK (3 << 24)
786/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
787#define X86_DR7_LEN2_MASK (3 << 26)
788/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
789#define X86_DR7_RW3_MASK (3 << 28)
790/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
791#define X86_DR7_LEN3_MASK (3 << 30)
792
793/** Bits which must be 1s. */
794#define X86_DR7_MB1_MASK (RT_BIT(10))
795
796/** Calcs the L bit of Nth breakpoint.
797 * @param iBp The breakpoint number [0..3].
798 */
799#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
800
801/** Calcs the G bit of Nth breakpoint.
802 * @param iBp The breakpoint number [0..3].
803 */
804#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
805
806/** @name Read/Write values.
807 * @{ */
808/** Break on instruction fetch only. */
809#define X86_DR7_RW_EO 0U
810/** Break on write only. */
811#define X86_DR7_RW_WO 1U
812/** Break on I/O read/write. This is only defined if CR4.DE is set. */
813#define X86_DR7_RW_IO 2U
814/** Break on read or write (but not instruction fetches). */
815#define X86_DR7_RW_RW 3U
816/** @} */
817
818/** Shifts a X86_DR7_RW_* value to its right place.
819 * @param iBp The breakpoint number [0..3].
820 * @param fRw One of the X86_DR7_RW_* value.
821 */
822#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
823
824/** @name Length values.
825 * @{ */
826#define X86_DR7_LEN_BYTE 0U
827#define X86_DR7_LEN_WORD 1U
828#define X86_DR7_LEN_QWORD 2U /**< AMD64 long mode only. */
829#define X86_DR7_LEN_DWORD 3U
830/** @} */
831
832/** Shifts a X86_DR7_LEN_* value to its right place.
833 * @param iBp The breakpoint number [0..3].
834 * @param cb One of the X86_DR7_LEN_* values.
835 */
836#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
837
838/** Fetch the breakpoint length bits from the DR7 value.
839 * @param uDR7 DR7 value
840 * @param iBp The breakpoint number [0..3].
841 */
842#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
843
844/** Mask used to check if any breakpoints are enabled. */
845#define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7))
846
847/** Mask used to check if any io breakpoints are set. */
848#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) | X86_DR7_RW(1, X86_DR7_RW_IO) | X86_DR7_RW(2, X86_DR7_RW_IO) | X86_DR7_RW(3, X86_DR7_RW_IO))
849
850/** Value of DR7 after powerup/reset. */
851#define X86_DR7_INIT_VAL 0x400
852/** @} */
853
854
855/** @name Machine Specific Registers
856 * @{
857 */
858
859/** Time Stamp Counter. */
860#define MSR_IA32_TSC 0x10
861
862#define MSR_IA32_PLATFORM_ID 0x17
863
864#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
865#define MSR_IA32_APICBASE 0x1b
866#endif
867
868/** CPU Feature control. */
869#define MSR_IA32_FEATURE_CONTROL 0x3A
870#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
871#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
872
873/** BIOS update trigger (microcode update). */
874#define MSR_IA32_BIOS_UPDT_TRIG 0x79
875
876/** BIOS update signature (microcode). */
877#define MSR_IA32_BIOS_SIGN_ID 0x8B
878
879/** General performance counter no. 0. */
880#define MSR_IA32_PMC0 0xC1
881/** General performance counter no. 1. */
882#define MSR_IA32_PMC1 0xC2
883/** General performance counter no. 2. */
884#define MSR_IA32_PMC2 0xC3
885/** General performance counter no. 3. */
886#define MSR_IA32_PMC3 0xC4
887
888/** Nehalem power control. */
889#define MSR_IA32_PLATFORM_INFO 0xCE
890
891/** Get FSB clock status (Intel-specific). */
892#define MSR_IA32_FSB_CLOCK_STS 0xCD
893
894/** MTRR Capabilities. */
895#define MSR_IA32_MTRR_CAP 0xFE
896
897
898#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
899/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
900 * R0 SS == CS + 8
901 * R3 CS == CS + 16
902 * R3 SS == CS + 24
903 */
904#define MSR_IA32_SYSENTER_CS 0x174
905/** SYSENTER_ESP - the R0 ESP. */
906#define MSR_IA32_SYSENTER_ESP 0x175
907/** SYSENTER_EIP - the R0 EIP. */
908#define MSR_IA32_SYSENTER_EIP 0x176
909#endif
910
911/** Machine Check Global Capabilities Register. */
912#define MSR_IA32_MCP_CAP 0x179
913/** Machine Check Global Status Register. */
914#define MSR_IA32_MCP_STATUS 0x17A
915/** Machine Check Global Control Register. */
916#define MSR_IA32_MCP_CTRL 0x17B
917
918/** Trace/Profile Resource Control (R/W) */
919#define MSR_IA32_DEBUGCTL 0x1D9
920
921/** Page Attribute Table. */
922#define MSR_IA32_CR_PAT 0x277
923
924/** Performance counter MSRs. (Intel only) */
925#define MSR_IA32_PERFEVTSEL0 0x186
926#define MSR_IA32_PERFEVTSEL1 0x187
927#define MSR_IA32_FLEX_RATIO 0x194
928#define MSR_IA32_PERF_STATUS 0x198
929#define MSR_IA32_PERF_CTL 0x199
930#define MSR_IA32_THERM_STATUS 0x19c
931
932/** Enable misc. processor features (R/W). */
933#define MSR_IA32_MISC_ENABLE 0x1A0
934/** Enable fast-strings feature (for REP MOVS and REP STORS). */
935#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
936/** Automatic Thermal Control Circuit Enable (R/W). */
937#define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
938/** Performance Monitoring Available (R). */
939#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
940/** Branch Trace Storage Unavailable (R/O). */
941#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
942/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
943#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
944/** Enhanced Intel SpeedStep Technology Enable (R/W). */
945#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
946/** If MONITOR/MWAIT is supported (R/W). */
947#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
948/** Limit CPUID Maxval to 3 leafs (R/W). */
949#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
950/** When set to 1, xTPR messages are disabled (R/W). */
951#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
952/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
953#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
954
955#define IA32_MTRR_PHYSBASE0 0x200
956#define IA32_MTRR_PHYSMASK0 0x201
957#define IA32_MTRR_PHYSBASE1 0x202
958#define IA32_MTRR_PHYSMASK1 0x203
959#define IA32_MTRR_PHYSBASE2 0x204
960#define IA32_MTRR_PHYSMASK2 0x205
961#define IA32_MTRR_PHYSBASE3 0x206
962#define IA32_MTRR_PHYSMASK3 0x207
963#define IA32_MTRR_PHYSBASE4 0x208
964#define IA32_MTRR_PHYSMASK4 0x209
965#define IA32_MTRR_PHYSBASE5 0x20a
966#define IA32_MTRR_PHYSMASK5 0x20b
967#define IA32_MTRR_PHYSBASE6 0x20c
968#define IA32_MTRR_PHYSMASK6 0x20d
969#define IA32_MTRR_PHYSBASE7 0x20e
970#define IA32_MTRR_PHYSMASK7 0x20f
971#define IA32_MTRR_PHYSBASE8 0x210
972#define IA32_MTRR_PHYSMASK8 0x211
973#define IA32_MTRR_PHYSBASE9 0x212
974#define IA32_MTRR_PHYSMASK9 0x213
975
976/** Fixed range MTRRs.
977 * @{ */
978#define IA32_MTRR_FIX64K_00000 0x250
979#define IA32_MTRR_FIX16K_80000 0x258
980#define IA32_MTRR_FIX16K_A0000 0x259
981#define IA32_MTRR_FIX4K_C0000 0x268
982#define IA32_MTRR_FIX4K_C8000 0x269
983#define IA32_MTRR_FIX4K_D0000 0x26a
984#define IA32_MTRR_FIX4K_D8000 0x26b
985#define IA32_MTRR_FIX4K_E0000 0x26c
986#define IA32_MTRR_FIX4K_E8000 0x26d
987#define IA32_MTRR_FIX4K_F0000 0x26e
988#define IA32_MTRR_FIX4K_F8000 0x26f
989/** @} */
990
991/** MTRR Default Range. */
992#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
993
994#define MSR_IA32_MC0_CTL 0x400
995#define MSR_IA32_MC0_STATUS 0x401
996
997/** Basic VMX information. */
998#define MSR_IA32_VMX_BASIC_INFO 0x480
999/** Allowed settings for pin-based VM execution controls */
1000#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1001/** Allowed settings for proc-based VM execution controls */
1002#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1003/** Allowed settings for the VMX exit controls. */
1004#define MSR_IA32_VMX_EXIT_CTLS 0x483
1005/** Allowed settings for the VMX entry controls. */
1006#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1007/** Misc VMX info. */
1008#define MSR_IA32_VMX_MISC 0x485
1009/** Fixed cleared bits in CR0. */
1010#define MSR_IA32_VMX_CR0_FIXED0 0x486
1011/** Fixed set bits in CR0. */
1012#define MSR_IA32_VMX_CR0_FIXED1 0x487
1013/** Fixed cleared bits in CR4. */
1014#define MSR_IA32_VMX_CR4_FIXED0 0x488
1015/** Fixed set bits in CR4. */
1016#define MSR_IA32_VMX_CR4_FIXED1 0x489
1017/** Information for enumerating fields in the VMCS. */
1018#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1019/** Allowed settings for secondary proc-based VM execution controls */
1020#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1021/** EPT capabilities. */
1022#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1023/** DS Save Area (R/W). */
1024#define MSR_IA32_DS_AREA 0x600
1025/** X2APIC MSR ranges. */
1026#define MSR_IA32_APIC_START 0x800
1027#define MSR_IA32_APIC_END 0x900
1028
1029/** K6 EFER - Extended Feature Enable Register. */
1030#define MSR_K6_EFER 0xc0000080
1031/** @todo document EFER */
1032/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1033#define MSR_K6_EFER_SCE RT_BIT(0)
1034/** Bit 8 - LME - Long mode enabled. (R/W) */
1035#define MSR_K6_EFER_LME RT_BIT(8)
1036/** Bit 10 - LMA - Long mode active. (R) */
1037#define MSR_K6_EFER_LMA RT_BIT(10)
1038/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1039#define MSR_K6_EFER_NXE RT_BIT(11)
1040/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1041#define MSR_K6_EFER_SVME RT_BIT(12)
1042/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1043#define MSR_K6_EFER_LMSLE RT_BIT(13)
1044/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1045#define MSR_K6_EFER_FFXSR RT_BIT(14)
1046/** K6 STAR - SYSCALL/RET targets. */
1047#define MSR_K6_STAR 0xc0000081
1048/** Shift value for getting the SYSRET CS and SS value. */
1049#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1050/** Shift value for getting the SYSCALL CS and SS value. */
1051#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1052/** Selector mask for use after shifting. */
1053#define MSR_K6_STAR_SEL_MASK 0xffff
1054/** The mask which give the SYSCALL EIP. */
1055#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
1056/** K6 WHCR - Write Handling Control Register. */
1057#define MSR_K6_WHCR 0xc0000082
1058/** K6 UWCCR - UC/WC Cacheability Control Register. */
1059#define MSR_K6_UWCCR 0xc0000085
1060/** K6 PSOR - Processor State Observability Register. */
1061#define MSR_K6_PSOR 0xc0000087
1062/** K6 PFIR - Page Flush/Invalidate Register. */
1063#define MSR_K6_PFIR 0xc0000088
1064
1065/** Performance counter MSRs. (AMD only) */
1066#define MSR_K7_EVNTSEL0 0xc0010000
1067#define MSR_K7_EVNTSEL1 0xc0010001
1068#define MSR_K7_EVNTSEL2 0xc0010002
1069#define MSR_K7_EVNTSEL3 0xc0010003
1070#define MSR_K7_PERFCTR0 0xc0010004
1071#define MSR_K7_PERFCTR1 0xc0010005
1072#define MSR_K7_PERFCTR2 0xc0010006
1073#define MSR_K7_PERFCTR3 0xc0010007
1074
1075/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1076#define MSR_K8_LSTAR 0xc0000082
1077/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1078#define MSR_K8_CSTAR 0xc0000083
1079/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1080#define MSR_K8_SF_MASK 0xc0000084
1081/** K8 FS.base - The 64-bit base FS register. */
1082#define MSR_K8_FS_BASE 0xc0000100
1083/** K8 GS.base - The 64-bit base GS register. */
1084#define MSR_K8_GS_BASE 0xc0000101
1085/** K8 KernelGSbase - Used with SWAPGS. */
1086#define MSR_K8_KERNEL_GS_BASE 0xc0000102
1087/** K8 TSC_AUX - Used with RDTSCP. */
1088#define MSR_K8_TSC_AUX 0xc0000103
1089#define MSR_K8_SYSCFG 0xc0010010
1090#define MSR_K8_HWCR 0xc0010015
1091#define MSR_K8_IORRBASE0 0xc0010016
1092#define MSR_K8_IORRMASK0 0xc0010017
1093#define MSR_K8_IORRBASE1 0xc0010018
1094#define MSR_K8_IORRMASK1 0xc0010019
1095#define MSR_K8_TOP_MEM1 0xc001001a
1096#define MSR_K8_TOP_MEM2 0xc001001d
1097#define MSR_K8_VM_CR 0xc0010114
1098#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1099
1100#define MSR_K8_IGNNE 0xc0010115
1101#define MSR_K8_SMM_CTL 0xc0010116
1102/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1103 * host state during world switch.
1104 */
1105#define MSR_K8_VM_HSAVE_PA 0xc0010117
1106
1107/** @} */
1108
1109
1110/** @name Page Table / Directory / Directory Pointers / L4.
1111 * @{
1112 */
1113
1114/** Page table/directory entry as an unsigned integer. */
1115typedef uint32_t X86PGUINT;
1116/** Pointer to a page table/directory table entry as an unsigned integer. */
1117typedef X86PGUINT *PX86PGUINT;
1118/** Pointer to an const page table/directory table entry as an unsigned integer. */
1119typedef X86PGUINT const *PCX86PGUINT;
1120
1121/** Number of entries in a 32-bit PT/PD. */
1122#define X86_PG_ENTRIES 1024
1123
1124
1125/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1126typedef uint64_t X86PGPAEUINT;
1127/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1128typedef X86PGPAEUINT *PX86PGPAEUINT;
1129/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1130typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1131
1132/** Number of entries in a PAE PT/PD. */
1133#define X86_PG_PAE_ENTRIES 512
1134/** Number of entries in a PAE PDPT. */
1135#define X86_PG_PAE_PDPE_ENTRIES 4
1136
1137/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1138#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1139/** Number of entries in an AMD64 PDPT.
1140 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1141#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1142
1143/** The size of a 4KB page. */
1144#define X86_PAGE_4K_SIZE _4K
1145/** The page shift of a 4KB page. */
1146#define X86_PAGE_4K_SHIFT 12
1147/** The 4KB page offset mask. */
1148#define X86_PAGE_4K_OFFSET_MASK 0xfff
1149/** The 4KB page base mask for virtual addresses. */
1150#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1151/** The 4KB page base mask for virtual addresses - 32bit version. */
1152#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1153
1154/** The size of a 2MB page. */
1155#define X86_PAGE_2M_SIZE _2M
1156/** The page shift of a 2MB page. */
1157#define X86_PAGE_2M_SHIFT 21
1158/** The 2MB page offset mask. */
1159#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1160/** The 2MB page base mask for virtual addresses. */
1161#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1162/** The 2MB page base mask for virtual addresses - 32bit version. */
1163#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1164
1165/** The size of a 4MB page. */
1166#define X86_PAGE_4M_SIZE _4M
1167/** The page shift of a 4MB page. */
1168#define X86_PAGE_4M_SHIFT 22
1169/** The 4MB page offset mask. */
1170#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1171/** The 4MB page base mask for virtual addresses. */
1172#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1173/** The 4MB page base mask for virtual addresses - 32bit version. */
1174#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1175
1176
1177
1178/** @name Page Table Entry
1179 * @{
1180 */
1181/** Bit 0 - P - Present bit. */
1182#define X86_PTE_BIT_P 0
1183/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1184#define X86_PTE_BIT_RW 1
1185/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1186#define X86_PTE_BIT_US 2
1187/** Bit 3 - PWT - Page level write thru bit. */
1188#define X86_PTE_BIT_PWT 3
1189/** Bit 4 - PCD - Page level cache disable bit. */
1190#define X86_PTE_BIT_PCD 4
1191/** Bit 5 - A - Access bit. */
1192#define X86_PTE_BIT_A 5
1193/** Bit 6 - D - Dirty bit. */
1194#define X86_PTE_BIT_D 6
1195/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1196#define X86_PTE_BIT_PAT 7
1197/** Bit 8 - G - Global flag. */
1198#define X86_PTE_BIT_G 8
1199
1200/** Bit 0 - P - Present bit mask. */
1201#define X86_PTE_P RT_BIT(0)
1202/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1203#define X86_PTE_RW RT_BIT(1)
1204/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1205#define X86_PTE_US RT_BIT(2)
1206/** Bit 3 - PWT - Page level write thru bit mask. */
1207#define X86_PTE_PWT RT_BIT(3)
1208/** Bit 4 - PCD - Page level cache disable bit mask. */
1209#define X86_PTE_PCD RT_BIT(4)
1210/** Bit 5 - A - Access bit mask. */
1211#define X86_PTE_A RT_BIT(5)
1212/** Bit 6 - D - Dirty bit mask. */
1213#define X86_PTE_D RT_BIT(6)
1214/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1215#define X86_PTE_PAT RT_BIT(7)
1216/** Bit 8 - G - Global bit mask. */
1217#define X86_PTE_G RT_BIT(8)
1218
1219/** Bits 9-11 - - Available for use to system software. */
1220#define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1221/** Bits 12-31 - - Physical Page number of the next level. */
1222#define X86_PTE_PG_MASK ( 0xfffff000 )
1223
1224/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1225#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1226/** Bits 63 - NX - PAE/LM - No execution flag. */
1227#define X86_PTE_PAE_NX RT_BIT_64(63)
1228/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1229#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1230/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1231#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1232/** No bits - - LM - MBZ bits when NX is active. */
1233#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1234/** Bits 63 - - LM - MBZ bits when no NX. */
1235#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1236
1237/**
1238 * Page table entry.
1239 */
1240typedef struct X86PTEBITS
1241{
1242 /** Flags whether(=1) or not the page is present. */
1243 unsigned u1Present : 1;
1244 /** Read(=0) / Write(=1) flag. */
1245 unsigned u1Write : 1;
1246 /** User(=1) / Supervisor (=0) flag. */
1247 unsigned u1User : 1;
1248 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1249 unsigned u1WriteThru : 1;
1250 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1251 unsigned u1CacheDisable : 1;
1252 /** Accessed flag.
1253 * Indicates that the page have been read or written to. */
1254 unsigned u1Accessed : 1;
1255 /** Dirty flag.
1256 * Indicates that the page has been written to. */
1257 unsigned u1Dirty : 1;
1258 /** Reserved / If PAT enabled, bit 2 of the index. */
1259 unsigned u1PAT : 1;
1260 /** Global flag. (Ignored in all but final level.) */
1261 unsigned u1Global : 1;
1262 /** Available for use to system software. */
1263 unsigned u3Available : 3;
1264 /** Physical Page number of the next level. */
1265 unsigned u20PageNo : 20;
1266} X86PTEBITS;
1267/** Pointer to a page table entry. */
1268typedef X86PTEBITS *PX86PTEBITS;
1269/** Pointer to a const page table entry. */
1270typedef const X86PTEBITS *PCX86PTEBITS;
1271
1272/**
1273 * Page table entry.
1274 */
1275typedef union X86PTE
1276{
1277 /** Unsigned integer view */
1278 X86PGUINT u;
1279 /** Bit field view. */
1280 X86PTEBITS n;
1281 /** 32-bit view. */
1282 uint32_t au32[1];
1283 /** 16-bit view. */
1284 uint16_t au16[2];
1285 /** 8-bit view. */
1286 uint8_t au8[4];
1287} X86PTE;
1288/** Pointer to a page table entry. */
1289typedef X86PTE *PX86PTE;
1290/** Pointer to a const page table entry. */
1291typedef const X86PTE *PCX86PTE;
1292
1293
1294/**
1295 * PAE page table entry.
1296 */
1297typedef struct X86PTEPAEBITS
1298{
1299 /** Flags whether(=1) or not the page is present. */
1300 uint32_t u1Present : 1;
1301 /** Read(=0) / Write(=1) flag. */
1302 uint32_t u1Write : 1;
1303 /** User(=1) / Supervisor(=0) flag. */
1304 uint32_t u1User : 1;
1305 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1306 uint32_t u1WriteThru : 1;
1307 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1308 uint32_t u1CacheDisable : 1;
1309 /** Accessed flag.
1310 * Indicates that the page have been read or written to. */
1311 uint32_t u1Accessed : 1;
1312 /** Dirty flag.
1313 * Indicates that the page has been written to. */
1314 uint32_t u1Dirty : 1;
1315 /** Reserved / If PAT enabled, bit 2 of the index. */
1316 uint32_t u1PAT : 1;
1317 /** Global flag. (Ignored in all but final level.) */
1318 uint32_t u1Global : 1;
1319 /** Available for use to system software. */
1320 uint32_t u3Available : 3;
1321 /** Physical Page number of the next level - Low Part. Don't use this. */
1322 uint32_t u20PageNoLow : 20;
1323 /** Physical Page number of the next level - High Part. Don't use this. */
1324 uint32_t u20PageNoHigh : 20;
1325 /** MBZ bits */
1326 uint32_t u11Reserved : 11;
1327 /** No Execute flag. */
1328 uint32_t u1NoExecute : 1;
1329} X86PTEPAEBITS;
1330/** Pointer to a page table entry. */
1331typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1332/** Pointer to a page table entry. */
1333typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1334
1335/**
1336 * PAE Page table entry.
1337 */
1338typedef union X86PTEPAE
1339{
1340 /** Unsigned integer view */
1341 X86PGPAEUINT u;
1342 /** Bit field view. */
1343 X86PTEPAEBITS n;
1344 /** 32-bit view. */
1345 uint32_t au32[2];
1346 /** 16-bit view. */
1347 uint16_t au16[4];
1348 /** 8-bit view. */
1349 uint8_t au8[8];
1350} X86PTEPAE;
1351/** Pointer to a PAE page table entry. */
1352typedef X86PTEPAE *PX86PTEPAE;
1353/** Pointer to a const PAE page table entry. */
1354typedef const X86PTEPAE *PCX86PTEPAE;
1355/** @} */
1356
1357/**
1358 * Page table.
1359 */
1360typedef struct X86PT
1361{
1362 /** PTE Array. */
1363 X86PTE a[X86_PG_ENTRIES];
1364} X86PT;
1365/** Pointer to a page table. */
1366typedef X86PT *PX86PT;
1367/** Pointer to a const page table. */
1368typedef const X86PT *PCX86PT;
1369
1370/** The page shift to get the PT index. */
1371#define X86_PT_SHIFT 12
1372/** The PT index mask (apply to a shifted page address). */
1373#define X86_PT_MASK 0x3ff
1374
1375
1376/**
1377 * Page directory.
1378 */
1379typedef struct X86PTPAE
1380{
1381 /** PTE Array. */
1382 X86PTEPAE a[X86_PG_PAE_ENTRIES];
1383} X86PTPAE;
1384/** Pointer to a page table. */
1385typedef X86PTPAE *PX86PTPAE;
1386/** Pointer to a const page table. */
1387typedef const X86PTPAE *PCX86PTPAE;
1388
1389/** The page shift to get the PA PTE index. */
1390#define X86_PT_PAE_SHIFT 12
1391/** The PAE PT index mask (apply to a shifted page address). */
1392#define X86_PT_PAE_MASK 0x1ff
1393
1394
1395/** @name 4KB Page Directory Entry
1396 * @{
1397 */
1398/** Bit 0 - P - Present bit. */
1399#define X86_PDE_P RT_BIT(0)
1400/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1401#define X86_PDE_RW RT_BIT(1)
1402/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1403#define X86_PDE_US RT_BIT(2)
1404/** Bit 3 - PWT - Page level write thru bit. */
1405#define X86_PDE_PWT RT_BIT(3)
1406/** Bit 4 - PCD - Page level cache disable bit. */
1407#define X86_PDE_PCD RT_BIT(4)
1408/** Bit 5 - A - Access bit. */
1409#define X86_PDE_A RT_BIT(5)
1410/** Bit 7 - PS - Page size attribute.
1411 * Clear mean 4KB pages, set means large pages (2/4MB). */
1412#define X86_PDE_PS RT_BIT(7)
1413/** Bits 9-11 - - Available for use to system software. */
1414#define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1415/** Bits 12-31 - - Physical Page number of the next level. */
1416#define X86_PDE_PG_MASK ( 0xfffff000 )
1417
1418/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1419#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1420/** Bits 63 - NX - PAE/LM - No execution flag. */
1421#define X86_PDE_PAE_NX RT_BIT_64(63)
1422/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1423#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1424/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1425#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1426/** Bit 7 - - LM - MBZ bits when NX is active. */
1427#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1428/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1429#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1430
1431/**
1432 * Page directory entry.
1433 */
1434typedef struct X86PDEBITS
1435{
1436 /** Flags whether(=1) or not the page is present. */
1437 unsigned u1Present : 1;
1438 /** Read(=0) / Write(=1) flag. */
1439 unsigned u1Write : 1;
1440 /** User(=1) / Supervisor (=0) flag. */
1441 unsigned u1User : 1;
1442 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1443 unsigned u1WriteThru : 1;
1444 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1445 unsigned u1CacheDisable : 1;
1446 /** Accessed flag.
1447 * Indicates that the page has been read or written to. */
1448 unsigned u1Accessed : 1;
1449 /** Reserved / Ignored (dirty bit). */
1450 unsigned u1Reserved0 : 1;
1451 /** Size bit if PSE is enabled - in any event it's 0. */
1452 unsigned u1Size : 1;
1453 /** Reserved / Ignored (global bit). */
1454 unsigned u1Reserved1 : 1;
1455 /** Available for use to system software. */
1456 unsigned u3Available : 3;
1457 /** Physical Page number of the next level. */
1458 unsigned u20PageNo : 20;
1459} X86PDEBITS;
1460/** Pointer to a page directory entry. */
1461typedef X86PDEBITS *PX86PDEBITS;
1462/** Pointer to a const page directory entry. */
1463typedef const X86PDEBITS *PCX86PDEBITS;
1464
1465
1466/**
1467 * PAE page directory entry.
1468 */
1469typedef struct X86PDEPAEBITS
1470{
1471 /** Flags whether(=1) or not the page is present. */
1472 uint32_t u1Present : 1;
1473 /** Read(=0) / Write(=1) flag. */
1474 uint32_t u1Write : 1;
1475 /** User(=1) / Supervisor (=0) flag. */
1476 uint32_t u1User : 1;
1477 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1478 uint32_t u1WriteThru : 1;
1479 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1480 uint32_t u1CacheDisable : 1;
1481 /** Accessed flag.
1482 * Indicates that the page has been read or written to. */
1483 uint32_t u1Accessed : 1;
1484 /** Reserved / Ignored (dirty bit). */
1485 uint32_t u1Reserved0 : 1;
1486 /** Size bit if PSE is enabled - in any event it's 0. */
1487 uint32_t u1Size : 1;
1488 /** Reserved / Ignored (global bit). / */
1489 uint32_t u1Reserved1 : 1;
1490 /** Available for use to system software. */
1491 uint32_t u3Available : 3;
1492 /** Physical Page number of the next level - Low Part. Don't use! */
1493 uint32_t u20PageNoLow : 20;
1494 /** Physical Page number of the next level - High Part. Don't use! */
1495 uint32_t u20PageNoHigh : 20;
1496 /** MBZ bits */
1497 uint32_t u11Reserved : 11;
1498 /** No Execute flag. */
1499 uint32_t u1NoExecute : 1;
1500} X86PDEPAEBITS;
1501/** Pointer to a page directory entry. */
1502typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1503/** Pointer to a const page directory entry. */
1504typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1505
1506/** @} */
1507
1508
1509/** @name 2/4MB Page Directory Entry
1510 * @{
1511 */
1512/** Bit 0 - P - Present bit. */
1513#define X86_PDE4M_P RT_BIT(0)
1514/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1515#define X86_PDE4M_RW RT_BIT(1)
1516/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1517#define X86_PDE4M_US RT_BIT(2)
1518/** Bit 3 - PWT - Page level write thru bit. */
1519#define X86_PDE4M_PWT RT_BIT(3)
1520/** Bit 4 - PCD - Page level cache disable bit. */
1521#define X86_PDE4M_PCD RT_BIT(4)
1522/** Bit 5 - A - Access bit. */
1523#define X86_PDE4M_A RT_BIT(5)
1524/** Bit 6 - D - Dirty bit. */
1525#define X86_PDE4M_D RT_BIT(6)
1526/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1527#define X86_PDE4M_PS RT_BIT(7)
1528/** Bit 8 - G - Global flag. */
1529#define X86_PDE4M_G RT_BIT(8)
1530/** Bits 9-11 - AVL - Available for use to system software. */
1531#define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1532/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1533#define X86_PDE4M_PAT RT_BIT(12)
1534/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1535#define X86_PDE4M_PAT_SHIFT (12 - 7)
1536/** Bits 22-31 - - Physical Page number. */
1537#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1538/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1539#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1540/** The number of bits to the high part of the page number. */
1541#define X86_PDE4M_PG_HIGH_SHIFT 19
1542/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1543#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1544
1545/** Bits 21-51 - - PAE/LM - Physical Page number.
1546 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1547#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1548/** Bits 63 - NX - PAE/LM - No execution flag. */
1549#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1550/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1551#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1552/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1553#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1554/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1555#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1556/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1557#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1558
1559/**
1560 * 4MB page directory entry.
1561 */
1562typedef struct X86PDE4MBITS
1563{
1564 /** Flags whether(=1) or not the page is present. */
1565 unsigned u1Present : 1;
1566 /** Read(=0) / Write(=1) flag. */
1567 unsigned u1Write : 1;
1568 /** User(=1) / Supervisor (=0) flag. */
1569 unsigned u1User : 1;
1570 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1571 unsigned u1WriteThru : 1;
1572 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1573 unsigned u1CacheDisable : 1;
1574 /** Accessed flag.
1575 * Indicates that the page have been read or written to. */
1576 unsigned u1Accessed : 1;
1577 /** Dirty flag.
1578 * Indicates that the page has been written to. */
1579 unsigned u1Dirty : 1;
1580 /** Page size flag - always 1 for 4MB entries. */
1581 unsigned u1Size : 1;
1582 /** Global flag. */
1583 unsigned u1Global : 1;
1584 /** Available for use to system software. */
1585 unsigned u3Available : 3;
1586 /** Reserved / If PAT enabled, bit 2 of the index. */
1587 unsigned u1PAT : 1;
1588 /** Bits 32-39 of the page number on AMD64.
1589 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1590 unsigned u8PageNoHigh : 8;
1591 /** Reserved. */
1592 unsigned u1Reserved : 1;
1593 /** Physical Page number of the page. */
1594 unsigned u10PageNo : 10;
1595} X86PDE4MBITS;
1596/** Pointer to a page table entry. */
1597typedef X86PDE4MBITS *PX86PDE4MBITS;
1598/** Pointer to a const page table entry. */
1599typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1600
1601
1602/**
1603 * 2MB PAE page directory entry.
1604 */
1605typedef struct X86PDE2MPAEBITS
1606{
1607 /** Flags whether(=1) or not the page is present. */
1608 uint32_t u1Present : 1;
1609 /** Read(=0) / Write(=1) flag. */
1610 uint32_t u1Write : 1;
1611 /** User(=1) / Supervisor(=0) flag. */
1612 uint32_t u1User : 1;
1613 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1614 uint32_t u1WriteThru : 1;
1615 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1616 uint32_t u1CacheDisable : 1;
1617 /** Accessed flag.
1618 * Indicates that the page have been read or written to. */
1619 uint32_t u1Accessed : 1;
1620 /** Dirty flag.
1621 * Indicates that the page has been written to. */
1622 uint32_t u1Dirty : 1;
1623 /** Page size flag - always 1 for 2MB entries. */
1624 uint32_t u1Size : 1;
1625 /** Global flag. */
1626 uint32_t u1Global : 1;
1627 /** Available for use to system software. */
1628 uint32_t u3Available : 3;
1629 /** Reserved / If PAT enabled, bit 2 of the index. */
1630 uint32_t u1PAT : 1;
1631 /** Reserved. */
1632 uint32_t u9Reserved : 9;
1633 /** Physical Page number of the next level - Low part. Don't use! */
1634 uint32_t u10PageNoLow : 10;
1635 /** Physical Page number of the next level - High part. Don't use! */
1636 uint32_t u20PageNoHigh : 20;
1637 /** MBZ bits */
1638 uint32_t u11Reserved : 11;
1639 /** No Execute flag. */
1640 uint32_t u1NoExecute : 1;
1641} X86PDE2MPAEBITS;
1642/** Pointer to a 2MB PAE page table entry. */
1643typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1644/** Pointer to a 2MB PAE page table entry. */
1645typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1646
1647/** @} */
1648
1649/**
1650 * Page directory entry.
1651 */
1652typedef union X86PDE
1653{
1654 /** Unsigned integer view. */
1655 X86PGUINT u;
1656 /** Normal view. */
1657 X86PDEBITS n;
1658 /** 4MB view (big). */
1659 X86PDE4MBITS b;
1660 /** 8 bit unsigned integer view. */
1661 uint8_t au8[4];
1662 /** 16 bit unsigned integer view. */
1663 uint16_t au16[2];
1664 /** 32 bit unsigned integer view. */
1665 uint32_t au32[1];
1666} X86PDE;
1667/** Pointer to a page directory entry. */
1668typedef X86PDE *PX86PDE;
1669/** Pointer to a const page directory entry. */
1670typedef const X86PDE *PCX86PDE;
1671
1672/**
1673 * PAE page directory entry.
1674 */
1675typedef union X86PDEPAE
1676{
1677 /** Unsigned integer view. */
1678 X86PGPAEUINT u;
1679 /** Normal view. */
1680 X86PDEPAEBITS n;
1681 /** 2MB page view (big). */
1682 X86PDE2MPAEBITS b;
1683 /** 8 bit unsigned integer view. */
1684 uint8_t au8[8];
1685 /** 16 bit unsigned integer view. */
1686 uint16_t au16[4];
1687 /** 32 bit unsigned integer view. */
1688 uint32_t au32[2];
1689} X86PDEPAE;
1690/** Pointer to a page directory entry. */
1691typedef X86PDEPAE *PX86PDEPAE;
1692/** Pointer to a const page directory entry. */
1693typedef const X86PDEPAE *PCX86PDEPAE;
1694
1695/**
1696 * Page directory.
1697 */
1698typedef struct X86PD
1699{
1700 /** PDE Array. */
1701 X86PDE a[X86_PG_ENTRIES];
1702} X86PD;
1703/** Pointer to a page directory. */
1704typedef X86PD *PX86PD;
1705/** Pointer to a const page directory. */
1706typedef const X86PD *PCX86PD;
1707
1708/** The page shift to get the PD index. */
1709#define X86_PD_SHIFT 22
1710/** The PD index mask (apply to a shifted page address). */
1711#define X86_PD_MASK 0x3ff
1712
1713
1714/**
1715 * PAE page directory.
1716 */
1717typedef struct X86PDPAE
1718{
1719 /** PDE Array. */
1720 X86PDEPAE a[X86_PG_PAE_ENTRIES];
1721} X86PDPAE;
1722/** Pointer to a PAE page directory. */
1723typedef X86PDPAE *PX86PDPAE;
1724/** Pointer to a const PAE page directory. */
1725typedef const X86PDPAE *PCX86PDPAE;
1726
1727/** The page shift to get the PAE PD index. */
1728#define X86_PD_PAE_SHIFT 21
1729/** The PAE PD index mask (apply to a shifted page address). */
1730#define X86_PD_PAE_MASK 0x1ff
1731
1732
1733/** @name Page Directory Pointer Table Entry (PAE)
1734 * @{
1735 */
1736/** Bit 0 - P - Present bit. */
1737#define X86_PDPE_P RT_BIT(0)
1738/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1739#define X86_PDPE_RW RT_BIT(1)
1740/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1741#define X86_PDPE_US RT_BIT(2)
1742/** Bit 3 - PWT - Page level write thru bit. */
1743#define X86_PDPE_PWT RT_BIT(3)
1744/** Bit 4 - PCD - Page level cache disable bit. */
1745#define X86_PDPE_PCD RT_BIT(4)
1746/** Bit 5 - A - Access bit. Long Mode only. */
1747#define X86_PDPE_A RT_BIT(5)
1748/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1749#define X86_PDPE_LM_PS RT_BIT(7)
1750/** Bits 9-11 - - Available for use to system software. */
1751#define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1752/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1753#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1754/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1755#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1756/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1757#define X86_PDPE_LM_NX RT_BIT_64(63)
1758/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1759#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1760/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1761#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1762/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1763#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1764/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1765#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1766
1767
1768/**
1769 * Page directory pointer table entry.
1770 */
1771typedef struct X86PDPEBITS
1772{
1773 /** Flags whether(=1) or not the page is present. */
1774 uint32_t u1Present : 1;
1775 /** Chunk of reserved bits. */
1776 uint32_t u2Reserved : 2;
1777 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1778 uint32_t u1WriteThru : 1;
1779 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1780 uint32_t u1CacheDisable : 1;
1781 /** Chunk of reserved bits. */
1782 uint32_t u4Reserved : 4;
1783 /** Available for use to system software. */
1784 uint32_t u3Available : 3;
1785 /** Physical Page number of the next level - Low Part. Don't use! */
1786 uint32_t u20PageNoLow : 20;
1787 /** Physical Page number of the next level - High Part. Don't use! */
1788 uint32_t u20PageNoHigh : 20;
1789 /** MBZ bits */
1790 uint32_t u12Reserved : 12;
1791} X86PDPEBITS;
1792/** Pointer to a page directory pointer table entry. */
1793typedef X86PDPEBITS *PX86PTPEBITS;
1794/** Pointer to a const page directory pointer table entry. */
1795typedef const X86PDPEBITS *PCX86PTPEBITS;
1796
1797/**
1798 * Page directory pointer table entry. AMD64 version
1799 */
1800typedef struct X86PDPEAMD64BITS
1801{
1802 /** Flags whether(=1) or not the page is present. */
1803 uint32_t u1Present : 1;
1804 /** Read(=0) / Write(=1) flag. */
1805 uint32_t u1Write : 1;
1806 /** User(=1) / Supervisor (=0) flag. */
1807 uint32_t u1User : 1;
1808 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1809 uint32_t u1WriteThru : 1;
1810 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1811 uint32_t u1CacheDisable : 1;
1812 /** Accessed flag.
1813 * Indicates that the page have been read or written to. */
1814 uint32_t u1Accessed : 1;
1815 /** Chunk of reserved bits. */
1816 uint32_t u3Reserved : 3;
1817 /** Available for use to system software. */
1818 uint32_t u3Available : 3;
1819 /** Physical Page number of the next level - Low Part. Don't use! */
1820 uint32_t u20PageNoLow : 20;
1821 /** Physical Page number of the next level - High Part. Don't use! */
1822 uint32_t u20PageNoHigh : 20;
1823 /** MBZ bits */
1824 uint32_t u11Reserved : 11;
1825 /** No Execute flag. */
1826 uint32_t u1NoExecute : 1;
1827} X86PDPEAMD64BITS;
1828/** Pointer to a page directory pointer table entry. */
1829typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1830/** Pointer to a const page directory pointer table entry. */
1831typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
1832
1833/**
1834 * Page directory pointer table entry.
1835 */
1836typedef union X86PDPE
1837{
1838 /** Unsigned integer view. */
1839 X86PGPAEUINT u;
1840 /** Normal view. */
1841 X86PDPEBITS n;
1842 /** AMD64 view. */
1843 X86PDPEAMD64BITS lm;
1844 /** 8 bit unsigned integer view. */
1845 uint8_t au8[8];
1846 /** 16 bit unsigned integer view. */
1847 uint16_t au16[4];
1848 /** 32 bit unsigned integer view. */
1849 uint32_t au32[2];
1850} X86PDPE;
1851/** Pointer to a page directory pointer table entry. */
1852typedef X86PDPE *PX86PDPE;
1853/** Pointer to a const page directory pointer table entry. */
1854typedef const X86PDPE *PCX86PDPE;
1855
1856
1857/**
1858 * Page directory pointer table.
1859 */
1860typedef struct X86PDPT
1861{
1862 /** PDE Array. */
1863 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1864} X86PDPT;
1865/** Pointer to a page directory pointer table. */
1866typedef X86PDPT *PX86PDPT;
1867/** Pointer to a const page directory pointer table. */
1868typedef const X86PDPT *PCX86PDPT;
1869
1870/** The page shift to get the PDPT index. */
1871#define X86_PDPT_SHIFT 30
1872/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1873#define X86_PDPT_MASK_PAE 0x3
1874/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1875#define X86_PDPT_MASK_AMD64 0x1ff
1876
1877/** @} */
1878
1879
1880/** @name Page Map Level-4 Entry (Long Mode PAE)
1881 * @{
1882 */
1883/** Bit 0 - P - Present bit. */
1884#define X86_PML4E_P RT_BIT(0)
1885/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1886#define X86_PML4E_RW RT_BIT(1)
1887/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1888#define X86_PML4E_US RT_BIT(2)
1889/** Bit 3 - PWT - Page level write thru bit. */
1890#define X86_PML4E_PWT RT_BIT(3)
1891/** Bit 4 - PCD - Page level cache disable bit. */
1892#define X86_PML4E_PCD RT_BIT(4)
1893/** Bit 5 - A - Access bit. */
1894#define X86_PML4E_A RT_BIT(5)
1895/** Bits 9-11 - - Available for use to system software. */
1896#define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1897/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1898#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
1899/** Bits 8, 7 - - MBZ bits when NX is active. */
1900#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1901/** Bits 63, 7 - - MBZ bits when no NX. */
1902#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1903/** Bits 63 - NX - PAE - No execution flag. */
1904#define X86_PML4E_NX RT_BIT_64(63)
1905
1906/**
1907 * Page Map Level-4 Entry
1908 */
1909typedef struct X86PML4EBITS
1910{
1911 /** Flags whether(=1) or not the page is present. */
1912 uint32_t u1Present : 1;
1913 /** Read(=0) / Write(=1) flag. */
1914 uint32_t u1Write : 1;
1915 /** User(=1) / Supervisor (=0) flag. */
1916 uint32_t u1User : 1;
1917 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1918 uint32_t u1WriteThru : 1;
1919 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1920 uint32_t u1CacheDisable : 1;
1921 /** Accessed flag.
1922 * Indicates that the page have been read or written to. */
1923 uint32_t u1Accessed : 1;
1924 /** Chunk of reserved bits. */
1925 uint32_t u3Reserved : 3;
1926 /** Available for use to system software. */
1927 uint32_t u3Available : 3;
1928 /** Physical Page number of the next level - Low Part. Don't use! */
1929 uint32_t u20PageNoLow : 20;
1930 /** Physical Page number of the next level - High Part. Don't use! */
1931 uint32_t u20PageNoHigh : 20;
1932 /** MBZ bits */
1933 uint32_t u11Reserved : 11;
1934 /** No Execute flag. */
1935 uint32_t u1NoExecute : 1;
1936} X86PML4EBITS;
1937/** Pointer to a page map level-4 entry. */
1938typedef X86PML4EBITS *PX86PML4EBITS;
1939/** Pointer to a const page map level-4 entry. */
1940typedef const X86PML4EBITS *PCX86PML4EBITS;
1941
1942/**
1943 * Page Map Level-4 Entry.
1944 */
1945typedef union X86PML4E
1946{
1947 /** Unsigned integer view. */
1948 X86PGPAEUINT u;
1949 /** Normal view. */
1950 X86PML4EBITS n;
1951 /** 8 bit unsigned integer view. */
1952 uint8_t au8[8];
1953 /** 16 bit unsigned integer view. */
1954 uint16_t au16[4];
1955 /** 32 bit unsigned integer view. */
1956 uint32_t au32[2];
1957} X86PML4E;
1958/** Pointer to a page map level-4 entry. */
1959typedef X86PML4E *PX86PML4E;
1960/** Pointer to a const page map level-4 entry. */
1961typedef const X86PML4E *PCX86PML4E;
1962
1963
1964/**
1965 * Page Map Level-4.
1966 */
1967typedef struct X86PML4
1968{
1969 /** PDE Array. */
1970 X86PML4E a[X86_PG_PAE_ENTRIES];
1971} X86PML4;
1972/** Pointer to a page map level-4. */
1973typedef X86PML4 *PX86PML4;
1974/** Pointer to a const page map level-4. */
1975typedef const X86PML4 *PCX86PML4;
1976
1977/** The page shift to get the PML4 index. */
1978#define X86_PML4_SHIFT 39
1979/** The PML4 index mask (apply to a shifted page address). */
1980#define X86_PML4_MASK 0x1ff
1981
1982/** @} */
1983
1984/** @} */
1985
1986
1987/**
1988 * 80-bit MMX/FPU register type.
1989 */
1990typedef struct X86FPUMMX
1991{
1992 uint8_t reg[10];
1993} X86FPUMMX;
1994/** Pointer to a 80-bit MMX/FPU register type. */
1995typedef X86FPUMMX *PX86FPUMMX;
1996/** Pointer to a const 80-bit MMX/FPU register type. */
1997typedef const X86FPUMMX *PCX86FPUMMX;
1998
1999/**
2000 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2001 * @todo verify this...
2002 */
2003#pragma pack(1)
2004typedef struct X86FPUSTATE
2005{
2006 /** 0x00 - Control word. */
2007 uint16_t FCW;
2008 /** 0x02 - Alignment word */
2009 uint16_t Dummy1;
2010 /** 0x04 - Status word. */
2011 uint16_t FSW;
2012 /** 0x06 - Alignment word */
2013 uint16_t Dummy2;
2014 /** 0x08 - Tag word */
2015 uint16_t FTW;
2016 /** 0x0a - Alignment word */
2017 uint16_t Dummy3;
2018
2019 /** 0x0c - Instruction pointer. */
2020 uint32_t FPUIP;
2021 /** 0x10 - Code selector. */
2022 uint16_t CS;
2023 /** 0x12 - Opcode. */
2024 uint16_t FOP;
2025 /** 0x14 - FOO. */
2026 uint32_t FPUOO;
2027 /** 0x18 - FOS. */
2028 uint32_t FPUOS;
2029 /** 0x1c */
2030 union
2031 {
2032 /** MMX view. */
2033 uint64_t mmx;
2034 /** FPU view - todo. */
2035 X86FPUMMX fpu;
2036 /** Extended precision floating point view. */
2037 RTFLOAT80U r80;
2038 /** Extended precision floating point view v2. */
2039 RTFLOAT80U2 r80Ex;
2040 /** 8-bit view. */
2041 uint8_t au8[16];
2042 /** 16-bit view. */
2043 uint16_t au16[8];
2044 /** 32-bit view. */
2045 uint32_t au32[4];
2046 /** 64-bit view. */
2047 uint64_t au64[2];
2048 /** 128-bit view. (yeah, very helpful) */
2049 uint128_t au128[1];
2050 } regs[8];
2051} X86FPUSTATE;
2052#pragma pack()
2053/** Pointer to a FPU state. */
2054typedef X86FPUSTATE *PX86FPUSTATE;
2055/** Pointer to a const FPU state. */
2056typedef const X86FPUSTATE *PCX86FPUSTATE;
2057
2058/**
2059 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2060 */
2061#pragma pack(1)
2062typedef struct X86FXSTATE
2063{
2064 /** 0x00 - Control word. */
2065 uint16_t FCW;
2066 /** 0x02 - Status word. */
2067 uint16_t FSW;
2068 /** 0x04 - Tag word. (The upper byte is always zero.) */
2069 uint16_t FTW;
2070 /** 0x06 - Opcode. */
2071 uint16_t FOP;
2072 /** 0x08 - Instruction pointer. */
2073 uint32_t FPUIP;
2074 /** 0x0c - Code selector. */
2075 uint16_t CS;
2076 uint16_t Rsrvd1;
2077 /** 0x10 - Data pointer. */
2078 uint32_t FPUDP;
2079 /** 0x14 - Data segment */
2080 uint16_t DS;
2081 /** 0x16 */
2082 uint16_t Rsrvd2;
2083 /** 0x18 */
2084 uint32_t MXCSR;
2085 /** 0x1c */
2086 uint32_t MXCSR_MASK;
2087 /** 0x20 */
2088 union
2089 {
2090 /** MMX view. */
2091 uint64_t mmx;
2092 /** FPU view - todo. */
2093 X86FPUMMX fpu;
2094 /** Extended precision floating point view. */
2095 RTFLOAT80U r80;
2096 /** Extended precision floating point view v2 */
2097 RTFLOAT80U2 r80Ex;
2098 /** 8-bit view. */
2099 uint8_t au8[16];
2100 /** 16-bit view. */
2101 uint16_t au16[8];
2102 /** 32-bit view. */
2103 uint32_t au32[4];
2104 /** 64-bit view. */
2105 uint64_t au64[2];
2106 /** 128-bit view. (yeah, very helpful) */
2107 uint128_t au128[1];
2108 } aRegs[8];
2109 /* - offset 160 - */
2110 union
2111 {
2112 /** XMM Register view *. */
2113 uint128_t xmm;
2114 /** 8-bit view. */
2115 uint8_t au8[16];
2116 /** 16-bit view. */
2117 uint16_t au16[8];
2118 /** 32-bit view. */
2119 uint32_t au32[4];
2120 /** 64-bit view. */
2121 uint64_t au64[2];
2122 /** 128-bit view. (yeah, very helpful) */
2123 uint128_t au128[1];
2124 } aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2125 /* - offset 416 - */
2126 uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
2127} X86FXSTATE;
2128#pragma pack()
2129/** Pointer to a FPU Extended state. */
2130typedef X86FXSTATE *PX86FXSTATE;
2131/** Pointer to a const FPU Extended state. */
2132typedef const X86FXSTATE *PCX86FXSTATE;
2133
2134/** @name FPU status word flags.
2135 * @{ */
2136/** Exception Flag: Invalid operation. */
2137#define X86_FSW_IE RT_BIT(0)
2138/** Exception Flag: Denormalized operand. */
2139#define X86_FSW_DE RT_BIT(1)
2140/** Exception Flag: Zero divide. */
2141#define X86_FSW_ZE RT_BIT(2)
2142/** Exception Flag: Overflow. */
2143#define X86_FSW_OE RT_BIT(3)
2144/** Exception Flag: Underflow. */
2145#define X86_FSW_UE RT_BIT(4)
2146/** Exception Flag: Precision. */
2147#define X86_FSW_PE RT_BIT(5)
2148/** Stack fault. */
2149#define X86_FSW_SF RT_BIT(6)
2150/** Error summary status. */
2151#define X86_FSW_ES RT_BIT(7)
2152/** Mask of exceptions flags, excluding the summary bit. */
2153#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2154/** Mask of exceptions flags, including the summary bit. */
2155#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2156/** Condition code 0. */
2157#define X86_FSW_C0 RT_BIT(8)
2158/** Condition code 1. */
2159#define X86_FSW_C1 RT_BIT(9)
2160/** Condition code 2. */
2161#define X86_FSW_C2 RT_BIT(10)
2162/** Top of the stack mask. */
2163#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2164/** TOP shift value. */
2165#define X86_FSW_TOP_SHIFT 11
2166/** Mask for getting TOP value after shifting it right. */
2167#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2168/** Get the TOP value. */
2169#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2170/** Condition code 3. */
2171#define X86_FSW_C3 RT_BIT(14)
2172/** Mask of exceptions flags, including the summary bit. */
2173#define X86_FSW_C_MASK UINT16_C(0x4700)
2174/** FPU busy. */
2175#define X86_FSW_B RT_BIT(15)
2176/** @} */
2177
2178
2179/** @name FPU control word flags.
2180 * @{ */
2181/** Exception Mask: Invalid operation. */
2182#define X86_FCW_IM RT_BIT(0)
2183/** Exception Mask: Denormalized operand. */
2184#define X86_FCW_DM RT_BIT(1)
2185/** Exception Mask: Zero divide. */
2186#define X86_FCW_ZM RT_BIT(2)
2187/** Exception Mask: Overflow. */
2188#define X86_FCW_OM RT_BIT(3)
2189/** Exception Mask: Underflow. */
2190#define X86_FCW_UM RT_BIT(4)
2191/** Exception Mask: Precision. */
2192#define X86_FCW_PM RT_BIT(5)
2193/** Mask all exceptions, the value typically loaded (by for instance fninit).
2194 * @remarks This includes reserved bit 6. */
2195#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2196/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2197#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2198/** Precision control mask. */
2199#define X86_FCW_PC_MASK UINT16_C(0x0300)
2200/** Precision control: 24-bit. */
2201#define X86_FCW_PC_24 UINT16_C(0x0000)
2202/** Precision control: Reserved. */
2203#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2204/** Precision control: 53-bit. */
2205#define X86_FCW_PC_53 UINT16_C(0x0200)
2206/** Precision control: 64-bit. */
2207#define X86_FCW_PC_64 UINT16_C(0x0300)
2208/** Rounding control mask. */
2209#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2210/** Rounding control: To nearest. */
2211#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2212/** Rounding control: Down. */
2213#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2214/** Rounding control: Up. */
2215#define X86_FCW_RC_UP UINT16_C(0x0800)
2216/** Rounding control: Towards zero. */
2217#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2218/** Bits which should be zero, apparently. */
2219#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2220/** @} */
2221
2222
2223/** @name Selector Descriptor
2224 * @{
2225 */
2226
2227#ifndef VBOX_FOR_DTRACE_LIB
2228/**
2229 * Descriptor attributes.
2230 */
2231typedef struct X86DESCATTRBITS
2232{
2233 /** 00 - Segment Type. */
2234 unsigned u4Type : 4;
2235 /** 04 - Descriptor Type. System(=0) or code/data selector */
2236 unsigned u1DescType : 1;
2237 /** 05 - Descriptor Privelege level. */
2238 unsigned u2Dpl : 2;
2239 /** 07 - Flags selector present(=1) or not. */
2240 unsigned u1Present : 1;
2241 /** 08 - Segment limit 16-19. */
2242 unsigned u4LimitHigh : 4;
2243 /** 0c - Available for system software. */
2244 unsigned u1Available : 1;
2245 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2246 unsigned u1Long : 1;
2247 /** 0e - This flags meaning depends on the segment type. Try make sense out
2248 * of the intel manual yourself. */
2249 unsigned u1DefBig : 1;
2250 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
2251 * clear byte. */
2252 unsigned u1Granularity : 1;
2253} X86DESCATTRBITS;
2254#endif /* !VBOX_FOR_DTRACE_LIB */
2255
2256#pragma pack(1)
2257typedef union X86DESCATTR
2258{
2259 /** Unsigned integer view. */
2260 uint32_t u;
2261#ifndef VBOX_FOR_DTRACE_LIB
2262 /** Normal view. */
2263 X86DESCATTRBITS n;
2264#endif
2265} X86DESCATTR;
2266#pragma pack()
2267/** Pointer to descriptor attributes. */
2268typedef X86DESCATTR *PX86DESCATTR;
2269/** Pointer to const descriptor attributes. */
2270typedef const X86DESCATTR *PCX86DESCATTR;
2271
2272#ifndef VBOX_FOR_DTRACE_LIB
2273
2274/**
2275 * Generic descriptor table entry
2276 */
2277#pragma pack(1)
2278typedef struct X86DESCGENERIC
2279{
2280 /** Limit - Low word. */
2281 unsigned u16LimitLow : 16;
2282 /** Base address - lowe word.
2283 * Don't try set this to 24 because MSC is doing stupid things then. */
2284 unsigned u16BaseLow : 16;
2285 /** Base address - first 8 bits of high word. */
2286 unsigned u8BaseHigh1 : 8;
2287 /** Segment Type. */
2288 unsigned u4Type : 4;
2289 /** Descriptor Type. System(=0) or code/data selector */
2290 unsigned u1DescType : 1;
2291 /** Descriptor Privelege level. */
2292 unsigned u2Dpl : 2;
2293 /** Flags selector present(=1) or not. */
2294 unsigned u1Present : 1;
2295 /** Segment limit 16-19. */
2296 unsigned u4LimitHigh : 4;
2297 /** Available for system software. */
2298 unsigned u1Available : 1;
2299 /** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2300 unsigned u1Long : 1;
2301 /** This flags meaning depends on the segment type. Try make sense out
2302 * of the intel manual yourself. */
2303 unsigned u1DefBig : 1;
2304 /** Granularity of the limit. If set 4KB granularity is used, if
2305 * clear byte. */
2306 unsigned u1Granularity : 1;
2307 /** Base address - highest 8 bits. */
2308 unsigned u8BaseHigh2 : 8;
2309} X86DESCGENERIC;
2310#pragma pack()
2311/** Pointer to a generic descriptor entry. */
2312typedef X86DESCGENERIC *PX86DESCGENERIC;
2313/** Pointer to a const generic descriptor entry. */
2314typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2315
2316/** @name Bit offsets of X86DESCGENERIC members.
2317 * @{*/
2318#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
2319#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
2320#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
2321#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
2322#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
2323#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
2324#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
2325#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
2326#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
2327#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
2328#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
2329#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
2330#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
2331/** @} */
2332
2333/**
2334 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2335 */
2336typedef struct X86DESCGATE
2337{
2338 /** 00 - Target code segment offset - Low word.
2339 * Ignored if task-gate. */
2340 unsigned u16OffsetLow : 16;
2341 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2342 * TSS selector if task-gate. */
2343 unsigned u16Sel : 16;
2344 /** 20 - Number of parameters for a call-gate.
2345 * Ignored if interrupt-, trap- or task-gate. */
2346 unsigned u4ParmCount : 4;
2347 /** 24 - Reserved / ignored. */
2348 unsigned u4Reserved : 4;
2349 /** 28 - Segment Type. */
2350 unsigned u4Type : 4;
2351 /** 2c - Descriptor Type (0 = system). */
2352 unsigned u1DescType : 1;
2353 /** 2d - Descriptor Privelege level. */
2354 unsigned u2Dpl : 2;
2355 /** 2f - Flags selector present(=1) or not. */
2356 unsigned u1Present : 1;
2357 /** 30 - Target code segment offset - High word.
2358 * Ignored if task-gate. */
2359 unsigned u16OffsetHigh : 16;
2360} X86DESCGATE;
2361/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2362typedef X86DESCGATE *PX86DESCGATE;
2363/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2364typedef const X86DESCGATE *PCX86DESCGATE;
2365
2366#endif /* VBOX_FOR_DTRACE_LIB */
2367
2368/**
2369 * Descriptor table entry.
2370 */
2371#pragma pack(1)
2372typedef union X86DESC
2373{
2374#ifndef VBOX_FOR_DTRACE_LIB
2375 /** Generic descriptor view. */
2376 X86DESCGENERIC Gen;
2377 /** Gate descriptor view. */
2378 X86DESCGATE Gate;
2379#endif
2380
2381 /** 8 bit unsigned integer view. */
2382 uint8_t au8[8];
2383 /** 16 bit unsigned integer view. */
2384 uint16_t au16[4];
2385 /** 32 bit unsigned integer view. */
2386 uint32_t au32[2];
2387 /** 64 bit unsigned integer view. */
2388 uint64_t au64[1];
2389 /** Unsigned integer view. */
2390 uint64_t u;
2391} X86DESC;
2392#ifndef VBOX_FOR_DTRACE_LIB
2393AssertCompileSize(X86DESC, 8);
2394#endif
2395#pragma pack()
2396/** Pointer to descriptor table entry. */
2397typedef X86DESC *PX86DESC;
2398/** Pointer to const descriptor table entry. */
2399typedef const X86DESC *PCX86DESC;
2400
2401/** @def X86DESC_BASE
2402 * Return the base address of a descriptor.
2403 */
2404#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
2405 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2406 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2407 | ( (a_pDesc)->Gen.u16BaseLow ) )
2408
2409/** @def X86DESC_LIMIT
2410 * Return the limit of a descriptor.
2411 */
2412#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
2413 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
2414 | ( (a_pDesc)->Gen.u16LimitLow ) )
2415
2416/** @def X86DESC_LIMIT_G
2417 * Return the limit of a descriptor with the granularity bit taken into account.
2418 * @returns Selector limit (uint32_t).
2419 * @param a_pDesc Pointer to the descriptor.
2420 */
2421#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
2422 ( (a_pDesc)->Gen.u1Granularity \
2423 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
2424 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
2425 )
2426
2427/** @def X86DESC_GET_HID_ATTR
2428 * Get the descriptor attributes for the hidden register.
2429 */
2430#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
2431 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
2432
2433#ifndef VBOX_FOR_DTRACE_LIB
2434
2435/**
2436 * 64 bits generic descriptor table entry
2437 * Note: most of these bits have no meaning in long mode.
2438 */
2439#pragma pack(1)
2440typedef struct X86DESC64GENERIC
2441{
2442 /** Limit - Low word - *IGNORED*. */
2443 unsigned u16LimitLow : 16;
2444 /** Base address - low word. - *IGNORED*
2445 * Don't try set this to 24 because MSC is doing stupid things then. */
2446 unsigned u16BaseLow : 16;
2447 /** Base address - first 8 bits of high word. - *IGNORED* */
2448 unsigned u8BaseHigh1 : 8;
2449 /** Segment Type. */
2450 unsigned u4Type : 4;
2451 /** Descriptor Type. System(=0) or code/data selector */
2452 unsigned u1DescType : 1;
2453 /** Descriptor Privelege level. */
2454 unsigned u2Dpl : 2;
2455 /** Flags selector present(=1) or not. */
2456 unsigned u1Present : 1;
2457 /** Segment limit 16-19. - *IGNORED* */
2458 unsigned u4LimitHigh : 4;
2459 /** Available for system software. - *IGNORED* */
2460 unsigned u1Available : 1;
2461 /** Long mode flag. */
2462 unsigned u1Long : 1;
2463 /** This flags meaning depends on the segment type. Try make sense out
2464 * of the intel manual yourself. */
2465 unsigned u1DefBig : 1;
2466 /** Granularity of the limit. If set 4KB granularity is used, if
2467 * clear byte. - *IGNORED* */
2468 unsigned u1Granularity : 1;
2469 /** Base address - highest 8 bits. - *IGNORED* */
2470 unsigned u8BaseHigh2 : 8;
2471 /** Base address - bits 63-32. */
2472 unsigned u32BaseHigh3 : 32;
2473 unsigned u8Reserved : 8;
2474 unsigned u5Zeros : 5;
2475 unsigned u19Reserved : 19;
2476} X86DESC64GENERIC;
2477#pragma pack()
2478/** Pointer to a generic descriptor entry. */
2479typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2480/** Pointer to a const generic descriptor entry. */
2481typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2482
2483/**
2484 * System descriptor table entry (64 bits)
2485 *
2486 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2487 */
2488#pragma pack(1)
2489typedef struct X86DESC64SYSTEM
2490{
2491 /** Limit - Low word. */
2492 unsigned u16LimitLow : 16;
2493 /** Base address - lowe word.
2494 * Don't try set this to 24 because MSC is doing stupid things then. */
2495 unsigned u16BaseLow : 16;
2496 /** Base address - first 8 bits of high word. */
2497 unsigned u8BaseHigh1 : 8;
2498 /** Segment Type. */
2499 unsigned u4Type : 4;
2500 /** Descriptor Type. System(=0) or code/data selector */
2501 unsigned u1DescType : 1;
2502 /** Descriptor Privelege level. */
2503 unsigned u2Dpl : 2;
2504 /** Flags selector present(=1) or not. */
2505 unsigned u1Present : 1;
2506 /** Segment limit 16-19. */
2507 unsigned u4LimitHigh : 4;
2508 /** Available for system software. */
2509 unsigned u1Available : 1;
2510 /** Reserved - 0. */
2511 unsigned u1Reserved : 1;
2512 /** This flags meaning depends on the segment type. Try make sense out
2513 * of the intel manual yourself. */
2514 unsigned u1DefBig : 1;
2515 /** Granularity of the limit. If set 4KB granularity is used, if
2516 * clear byte. */
2517 unsigned u1Granularity : 1;
2518 /** Base address - bits 31-24. */
2519 unsigned u8BaseHigh2 : 8;
2520 /** Base address - bits 63-32. */
2521 unsigned u32BaseHigh3 : 32;
2522 unsigned u8Reserved : 8;
2523 unsigned u5Zeros : 5;
2524 unsigned u19Reserved : 19;
2525} X86DESC64SYSTEM;
2526#pragma pack()
2527/** Pointer to a system descriptor entry. */
2528typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2529/** Pointer to a const system descriptor entry. */
2530typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2531
2532/**
2533 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2534 */
2535typedef struct X86DESC64GATE
2536{
2537 /** Target code segment offset - Low word. */
2538 unsigned u16OffsetLow : 16;
2539 /** Target code segment selector. */
2540 unsigned u16Sel : 16;
2541 /** Interrupt stack table for interrupt- and trap-gates.
2542 * Ignored by call-gates. */
2543 unsigned u3IST : 3;
2544 /** Reserved / ignored. */
2545 unsigned u5Reserved : 5;
2546 /** Segment Type. */
2547 unsigned u4Type : 4;
2548 /** Descriptor Type (0 = system). */
2549 unsigned u1DescType : 1;
2550 /** Descriptor Privelege level. */
2551 unsigned u2Dpl : 2;
2552 /** Flags selector present(=1) or not. */
2553 unsigned u1Present : 1;
2554 /** Target code segment offset - High word.
2555 * Ignored if task-gate. */
2556 unsigned u16OffsetHigh : 16;
2557 /** Target code segment offset - Top dword.
2558 * Ignored if task-gate. */
2559 unsigned u32OffsetTop : 32;
2560 /** Reserved / ignored / must be zero.
2561 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2562 unsigned u32Reserved : 32;
2563} X86DESC64GATE;
2564AssertCompileSize(X86DESC64GATE, 16);
2565/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2566typedef X86DESC64GATE *PX86DESC64GATE;
2567/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2568typedef const X86DESC64GATE *PCX86DESC64GATE;
2569
2570#endif /* VBOX_FOR_DTRACE_LIB */
2571
2572/**
2573 * Descriptor table entry.
2574 */
2575#pragma pack(1)
2576typedef union X86DESC64
2577{
2578#ifndef VBOX_FOR_DTRACE_LIB
2579 /** Generic descriptor view. */
2580 X86DESC64GENERIC Gen;
2581 /** System descriptor view. */
2582 X86DESC64SYSTEM System;
2583 /** Gate descriptor view. */
2584 X86DESC64GATE Gate;
2585#endif
2586
2587 /** 8 bit unsigned integer view. */
2588 uint8_t au8[16];
2589 /** 16 bit unsigned integer view. */
2590 uint16_t au16[8];
2591 /** 32 bit unsigned integer view. */
2592 uint32_t au32[4];
2593 /** 64 bit unsigned integer view. */
2594 uint64_t au64[2];
2595} X86DESC64;
2596#ifndef VBOX_FOR_DTRACE_LIB
2597AssertCompileSize(X86DESC64, 16);
2598#endif
2599#pragma pack()
2600/** Pointer to descriptor table entry. */
2601typedef X86DESC64 *PX86DESC64;
2602/** Pointer to const descriptor table entry. */
2603typedef const X86DESC64 *PCX86DESC64;
2604
2605/** @def X86DESC64_BASE
2606 * Return the base of a 64-bit descriptor.
2607 */
2608#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
2609 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
2610 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
2611 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
2612 | ( (a_pDesc)->Gen.u16BaseLow ) )
2613
2614
2615
2616/** @name Host system descriptor table entry - Use with care!
2617 * @{ */
2618/** Host system descriptor table entry. */
2619#if HC_ARCH_BITS == 64
2620typedef X86DESC64 X86DESCHC;
2621#else
2622typedef X86DESC X86DESCHC;
2623#endif
2624/** Pointer to a host system descriptor table entry. */
2625#if HC_ARCH_BITS == 64
2626typedef PX86DESC64 PX86DESCHC;
2627#else
2628typedef PX86DESC PX86DESCHC;
2629#endif
2630/** Pointer to a const host system descriptor table entry. */
2631#if HC_ARCH_BITS == 64
2632typedef PCX86DESC64 PCX86DESCHC;
2633#else
2634typedef PCX86DESC PCX86DESCHC;
2635#endif
2636/** @} */
2637
2638
2639/** @name Selector Descriptor Types.
2640 * @{
2641 */
2642
2643/** @name Non-System Selector Types.
2644 * @{ */
2645/** Code(=set)/Data(=clear) bit. */
2646#define X86_SEL_TYPE_CODE 8
2647/** Memory(=set)/System(=clear) bit. */
2648#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2649/** Accessed bit. */
2650#define X86_SEL_TYPE_ACCESSED 1
2651/** Expand down bit (for data selectors only). */
2652#define X86_SEL_TYPE_DOWN 4
2653/** Conforming bit (for code selectors only). */
2654#define X86_SEL_TYPE_CONF 4
2655/** Write bit (for data selectors only). */
2656#define X86_SEL_TYPE_WRITE 2
2657/** Read bit (for code selectors only). */
2658#define X86_SEL_TYPE_READ 2
2659/** The bit number of the code segment read bit (relative to u4Type). */
2660#define X86_SEL_TYPE_READ_BIT 1
2661
2662/** Read only selector type. */
2663#define X86_SEL_TYPE_RO 0
2664/** Accessed read only selector type. */
2665#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
2666/** Read write selector type. */
2667#define X86_SEL_TYPE_RW 2
2668/** Accessed read write selector type. */
2669#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
2670/** Expand down read only selector type. */
2671#define X86_SEL_TYPE_RO_DOWN 4
2672/** Accessed expand down read only selector type. */
2673#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
2674/** Expand down read write selector type. */
2675#define X86_SEL_TYPE_RW_DOWN 6
2676/** Accessed expand down read write selector type. */
2677#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
2678/** Execute only selector type. */
2679#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
2680/** Accessed execute only selector type. */
2681#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2682/** Execute and read selector type. */
2683#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
2684/** Accessed execute and read selector type. */
2685#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2686/** Conforming execute only selector type. */
2687#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
2688/** Accessed Conforming execute only selector type. */
2689#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2690/** Conforming execute and write selector type. */
2691#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
2692/** Accessed Conforming execute and write selector type. */
2693#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2694/** @} */
2695
2696
2697/** @name System Selector Types.
2698 * @{ */
2699/** The TSS busy bit mask. */
2700#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
2701
2702/** Undefined system selector type. */
2703#define X86_SEL_TYPE_SYS_UNDEFINED 0
2704/** 286 TSS selector. */
2705#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2706/** LDT selector. */
2707#define X86_SEL_TYPE_SYS_LDT 2
2708/** 286 TSS selector - Busy. */
2709#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2710/** 286 Callgate selector. */
2711#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2712/** Taskgate selector. */
2713#define X86_SEL_TYPE_SYS_TASK_GATE 5
2714/** 286 Interrupt gate selector. */
2715#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2716/** 286 Trapgate selector. */
2717#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2718/** Undefined system selector. */
2719#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2720/** 386 TSS selector. */
2721#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2722/** Undefined system selector. */
2723#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2724/** 386 TSS selector - Busy. */
2725#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2726/** 386 Callgate selector. */
2727#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2728/** Undefined system selector. */
2729#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2730/** 386 Interruptgate selector. */
2731#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2732/** 386 Trapgate selector. */
2733#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2734/** @} */
2735
2736/** @name AMD64 System Selector Types.
2737 * @{ */
2738/** LDT selector. */
2739#define AMD64_SEL_TYPE_SYS_LDT 2
2740/** TSS selector - Busy. */
2741#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2742/** TSS selector - Busy. */
2743#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2744/** Callgate selector. */
2745#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2746/** Interruptgate selector. */
2747#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2748/** Trapgate selector. */
2749#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2750/** @} */
2751
2752/** @} */
2753
2754
2755/** @name Descriptor Table Entry Flag Masks.
2756 * These are for the 2nd 32-bit word of a descriptor.
2757 * @{ */
2758/** Bits 8-11 - TYPE - Descriptor type mask. */
2759#define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
2760/** Bit 12 - S - System (=0) or Code/Data (=1). */
2761#define X86_DESC_S RT_BIT(12)
2762/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2763#define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
2764/** Bit 15 - P - Present. */
2765#define X86_DESC_P RT_BIT(15)
2766/** Bit 20 - AVL - Available for system software. */
2767#define X86_DESC_AVL RT_BIT(20)
2768/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2769#define X86_DESC_DB RT_BIT(22)
2770/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2771 * used, if clear byte. */
2772#define X86_DESC_G RT_BIT(23)
2773/** @} */
2774
2775/** @} */
2776
2777
2778/** @name Task Segments.
2779 * @{
2780 */
2781
2782/**
2783 * 16-bit Task Segment (TSS).
2784 */
2785#pragma pack(1)
2786typedef struct X86TSS16
2787{
2788 /** Back link to previous task. (static) */
2789 RTSEL selPrev;
2790 /** Ring-0 stack pointer. (static) */
2791 uint16_t sp0;
2792 /** Ring-0 stack segment. (static) */
2793 RTSEL ss0;
2794 /** Ring-1 stack pointer. (static) */
2795 uint16_t sp1;
2796 /** Ring-1 stack segment. (static) */
2797 RTSEL ss1;
2798 /** Ring-2 stack pointer. (static) */
2799 uint16_t sp2;
2800 /** Ring-2 stack segment. (static) */
2801 RTSEL ss2;
2802 /** IP before task switch. */
2803 uint16_t ip;
2804 /** FLAGS before task switch. */
2805 uint16_t flags;
2806 /** AX before task switch. */
2807 uint16_t ax;
2808 /** CX before task switch. */
2809 uint16_t cx;
2810 /** DX before task switch. */
2811 uint16_t dx;
2812 /** BX before task switch. */
2813 uint16_t bx;
2814 /** SP before task switch. */
2815 uint16_t sp;
2816 /** BP before task switch. */
2817 uint16_t bp;
2818 /** SI before task switch. */
2819 uint16_t si;
2820 /** DI before task switch. */
2821 uint16_t di;
2822 /** ES before task switch. */
2823 RTSEL es;
2824 /** CS before task switch. */
2825 RTSEL cs;
2826 /** SS before task switch. */
2827 RTSEL ss;
2828 /** DS before task switch. */
2829 RTSEL ds;
2830 /** LDTR before task switch. */
2831 RTSEL selLdt;
2832} X86TSS16;
2833#ifndef VBOX_FOR_DTRACE_LIB
2834AssertCompileSize(X86TSS16, 44);
2835#endif
2836#pragma pack()
2837/** Pointer to a 16-bit task segment. */
2838typedef X86TSS16 *PX86TSS16;
2839/** Pointer to a const 16-bit task segment. */
2840typedef const X86TSS16 *PCX86TSS16;
2841
2842
2843/**
2844 * 32-bit Task Segment (TSS).
2845 */
2846#pragma pack(1)
2847typedef struct X86TSS32
2848{
2849 /** Back link to previous task. (static) */
2850 RTSEL selPrev;
2851 uint16_t padding1;
2852 /** Ring-0 stack pointer. (static) */
2853 uint32_t esp0;
2854 /** Ring-0 stack segment. (static) */
2855 RTSEL ss0;
2856 uint16_t padding_ss0;
2857 /** Ring-1 stack pointer. (static) */
2858 uint32_t esp1;
2859 /** Ring-1 stack segment. (static) */
2860 RTSEL ss1;
2861 uint16_t padding_ss1;
2862 /** Ring-2 stack pointer. (static) */
2863 uint32_t esp2;
2864 /** Ring-2 stack segment. (static) */
2865 RTSEL ss2;
2866 uint16_t padding_ss2;
2867 /** Page directory for the task. (static) */
2868 uint32_t cr3;
2869 /** EIP before task switch. */
2870 uint32_t eip;
2871 /** EFLAGS before task switch. */
2872 uint32_t eflags;
2873 /** EAX before task switch. */
2874 uint32_t eax;
2875 /** ECX before task switch. */
2876 uint32_t ecx;
2877 /** EDX before task switch. */
2878 uint32_t edx;
2879 /** EBX before task switch. */
2880 uint32_t ebx;
2881 /** ESP before task switch. */
2882 uint32_t esp;
2883 /** EBP before task switch. */
2884 uint32_t ebp;
2885 /** ESI before task switch. */
2886 uint32_t esi;
2887 /** EDI before task switch. */
2888 uint32_t edi;
2889 /** ES before task switch. */
2890 RTSEL es;
2891 uint16_t padding_es;
2892 /** CS before task switch. */
2893 RTSEL cs;
2894 uint16_t padding_cs;
2895 /** SS before task switch. */
2896 RTSEL ss;
2897 uint16_t padding_ss;
2898 /** DS before task switch. */
2899 RTSEL ds;
2900 uint16_t padding_ds;
2901 /** FS before task switch. */
2902 RTSEL fs;
2903 uint16_t padding_fs;
2904 /** GS before task switch. */
2905 RTSEL gs;
2906 uint16_t padding_gs;
2907 /** LDTR before task switch. */
2908 RTSEL selLdt;
2909 uint16_t padding_ldt;
2910 /** Debug trap flag */
2911 uint16_t fDebugTrap;
2912 /** Offset relative to the TSS of the start of the I/O Bitmap
2913 * and the end of the interrupt redirection bitmap. */
2914 uint16_t offIoBitmap;
2915 /** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2916 uint8_t IntRedirBitmap[32];
2917} X86TSS32;
2918#pragma pack()
2919/** Pointer to task segment. */
2920typedef X86TSS32 *PX86TSS32;
2921/** Pointer to const task segment. */
2922typedef const X86TSS32 *PCX86TSS32;
2923
2924
2925/**
2926 * 64-bit Task segment.
2927 */
2928#pragma pack(1)
2929typedef struct X86TSS64
2930{
2931 /** Reserved. */
2932 uint32_t u32Reserved;
2933 /** Ring-0 stack pointer. (static) */
2934 uint64_t rsp0;
2935 /** Ring-1 stack pointer. (static) */
2936 uint64_t rsp1;
2937 /** Ring-2 stack pointer. (static) */
2938 uint64_t rsp2;
2939 /** Reserved. */
2940 uint32_t u32Reserved2[2];
2941 /* IST */
2942 uint64_t ist1;
2943 uint64_t ist2;
2944 uint64_t ist3;
2945 uint64_t ist4;
2946 uint64_t ist5;
2947 uint64_t ist6;
2948 uint64_t ist7;
2949 /* Reserved. */
2950 uint16_t u16Reserved[5];
2951 /** Offset relative to the TSS of the start of the I/O Bitmap
2952 * and the end of the interrupt redirection bitmap. */
2953 uint16_t offIoBitmap;
2954 /** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2955 uint8_t IntRedirBitmap[32];
2956} X86TSS64;
2957#pragma pack()
2958/** Pointer to a 64-bit task segment. */
2959typedef X86TSS64 *PX86TSS64;
2960/** Pointer to a const 64-bit task segment. */
2961typedef const X86TSS64 *PCX86TSS64;
2962#ifndef VBOX_FOR_DTRACE_LIB
2963AssertCompileSize(X86TSS64, 136);
2964#endif
2965
2966/** @} */
2967
2968
2969/** @name Selectors.
2970 * @{
2971 */
2972
2973/**
2974 * The shift used to convert a selector from and to index an index (C).
2975 */
2976#define X86_SEL_SHIFT 3
2977
2978/**
2979 * The mask used to mask off the table indicator and RPL of an selector.
2980 */
2981#define X86_SEL_MASK 0xfff8U
2982
2983/**
2984 * The mask used to mask off the RPL of an selector.
2985 * This is suitable for checking for NULL selectors.
2986 */
2987#define X86_SEL_MASK_OFF_RPL 0xfffcU
2988
2989/**
2990 * The bit indicating that a selector is in the LDT and not in the GDT.
2991 */
2992#define X86_SEL_LDT 0x0004U
2993
2994/**
2995 * The bit mask for getting the RPL of a selector.
2996 */
2997#define X86_SEL_RPL 0x0003U
2998
2999/**
3000 * The mask covering both RPL and LDT.
3001 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
3002 * checks.
3003 */
3004#define X86_SEL_RPL_LDT 0x0007U
3005
3006/** @} */
3007
3008
3009/**
3010 * x86 Exceptions/Faults/Traps.
3011 */
3012typedef enum X86XCPT
3013{
3014 /** \#DE - Divide error. */
3015 X86_XCPT_DE = 0x00,
3016 /** \#DB - Debug event (single step, DRx, ..) */
3017 X86_XCPT_DB = 0x01,
3018 /** NMI - Non-Maskable Interrupt */
3019 X86_XCPT_NMI = 0x02,
3020 /** \#BP - Breakpoint (INT3). */
3021 X86_XCPT_BP = 0x03,
3022 /** \#OF - Overflow (INTO). */
3023 X86_XCPT_OF = 0x04,
3024 /** \#BR - Bound range exceeded (BOUND). */
3025 X86_XCPT_BR = 0x05,
3026 /** \#UD - Undefined opcode. */
3027 X86_XCPT_UD = 0x06,
3028 /** \#NM - Device not available (math coprocessor device). */
3029 X86_XCPT_NM = 0x07,
3030 /** \#DF - Double fault. */
3031 X86_XCPT_DF = 0x08,
3032 /** ??? - Coprocessor segment overrun (obsolete). */
3033 X86_XCPT_CO_SEG_OVERRUN = 0x09,
3034 /** \#TS - Taskswitch (TSS). */
3035 X86_XCPT_TS = 0x0a,
3036 /** \#NP - Segment no present. */
3037 X86_XCPT_NP = 0x0b,
3038 /** \#SS - Stack segment fault. */
3039 X86_XCPT_SS = 0x0c,
3040 /** \#GP - General protection fault. */
3041 X86_XCPT_GP = 0x0d,
3042 /** \#PF - Page fault. */
3043 X86_XCPT_PF = 0x0e,
3044 /* 0x0f is reserved. */
3045 /** \#MF - Math fault (FPU). */
3046 X86_XCPT_MF = 0x10,
3047 /** \#AC - Alignment check. */
3048 X86_XCPT_AC = 0x11,
3049 /** \#MC - Machine check. */
3050 X86_XCPT_MC = 0x12,
3051 /** \#XF - SIMD Floating-Pointer Exception. */
3052 X86_XCPT_XF = 0x13
3053} X86XCPT;
3054/** Pointer to a x86 exception code. */
3055typedef X86XCPT *PX86XCPT;
3056/** Pointer to a const x86 exception code. */
3057typedef const X86XCPT *PCX86XCPT;
3058/** The maximum exception value. */
3059#define X86_XCPT_MAX (X86_XCPT_XF)
3060
3061
3062/** @name Trap Error Codes
3063 * @{
3064 */
3065/** External indicator. */
3066#define X86_TRAP_ERR_EXTERNAL 1
3067/** IDT indicator. */
3068#define X86_TRAP_ERR_IDT 2
3069/** Descriptor table indicator - If set LDT, if clear GDT. */
3070#define X86_TRAP_ERR_TI 4
3071/** Mask for getting the selector. */
3072#define X86_TRAP_ERR_SEL_MASK 0xfff8
3073/** Shift for getting the selector table index (C type index). */
3074#define X86_TRAP_ERR_SEL_SHIFT 3
3075/** @} */
3076
3077
3078/** @name \#PF Trap Error Codes
3079 * @{
3080 */
3081/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
3082#define X86_TRAP_PF_P RT_BIT(0)
3083/** Bit 1 - R/W - Read (clear) or write (set) access. */
3084#define X86_TRAP_PF_RW RT_BIT(1)
3085/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
3086#define X86_TRAP_PF_US RT_BIT(2)
3087/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
3088#define X86_TRAP_PF_RSVD RT_BIT(3)
3089/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
3090#define X86_TRAP_PF_ID RT_BIT(4)
3091/** @} */
3092
3093#pragma pack(1)
3094/**
3095 * 32-bit IDTR/GDTR.
3096 */
3097typedef struct X86XDTR32
3098{
3099 /** Size of the descriptor table. */
3100 uint16_t cb;
3101 /** Address of the descriptor table. */
3102#ifndef VBOX_FOR_DTRACE_LIB
3103 uint32_t uAddr;
3104#else
3105 uint16_t au16Addr[2];
3106#endif
3107} X86XDTR32, *PX86XDTR32;
3108#pragma pack()
3109
3110#pragma pack(1)
3111/**
3112 * 64-bit IDTR/GDTR.
3113 */
3114typedef struct X86XDTR64
3115{
3116 /** Size of the descriptor table. */
3117 uint16_t cb;
3118 /** Address of the descriptor table. */
3119#ifndef VBOX_FOR_DTRACE_LIB
3120 uint64_t uAddr;
3121#else
3122 uint16_t au16Addr[4];
3123#endif
3124} X86XDTR64, *PX86XDTR64;
3125#pragma pack()
3126
3127
3128/** @name ModR/M
3129 * @{ */
3130#define X86_MODRM_RM_MASK UINT8_C(0x07)
3131#define X86_MODRM_REG_MASK UINT8_C(0x38)
3132#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3133#define X86_MODRM_REG_SHIFT 3
3134#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3135#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3136#define X86_MODRM_MOD_SHIFT 6
3137#ifndef VBOX_FOR_DTRACE_LIB
3138AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
3139AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3140AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3141#endif
3142/** @} */
3143
3144/** @name SIB
3145 * @{ */
3146#define X86_SIB_BASE_MASK UINT8_C(0x07)
3147#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3148#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3149#define X86_SIB_INDEX_SHIFT 3
3150#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3151#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3152#define X86_SIB_SCALE_SHIFT 6
3153#ifndef VBOX_FOR_DTRACE_LIB
3154AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
3155AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3156AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3157#endif
3158/** @} */
3159
3160/** @name General register indexes
3161 * @{ */
3162#define X86_GREG_xAX 0
3163#define X86_GREG_xCX 1
3164#define X86_GREG_xDX 2
3165#define X86_GREG_xBX 3
3166#define X86_GREG_xSP 4
3167#define X86_GREG_xBP 5
3168#define X86_GREG_xSI 6
3169#define X86_GREG_xDI 7
3170#define X86_GREG_x8 8
3171#define X86_GREG_x9 9
3172#define X86_GREG_x10 10
3173#define X86_GREG_x11 11
3174#define X86_GREG_x12 12
3175#define X86_GREG_x13 13
3176#define X86_GREG_x14 14
3177#define X86_GREG_x15 15
3178/** @} */
3179
3180/** @name X86_SREG_XXX - Segment register indexes.
3181 * @{ */
3182#define X86_SREG_ES 0
3183#define X86_SREG_CS 1
3184#define X86_SREG_SS 2
3185#define X86_SREG_DS 3
3186#define X86_SREG_FS 4
3187#define X86_SREG_GS 5
3188/** @} */
3189/** Segment register count. */
3190#define X86_SREG_COUNT 6
3191
3192
3193/** @} */
3194
3195#endif
3196
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