x86.h@ 40282

Last change on this file since 40282 was 40222, checked in by vboxsync, 13 years ago
IEM: Implemented fldcw, fldenv fnstcw and fnstenv.
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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2012 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___iprt_x86_h
29	#define ___iprt_x86_h
30
31	#include <iprt/types.h>
32	#include <iprt/assert.h>
33
34	/* Workaround for Solaris sys/regset.h defining CS, DS */
35	#ifdef RT_OS_SOLARIS
36	# undef CS
37	# undef DS
38	#endif
39
40	/** @defgroup grp_rt_x86 x86 Types and Definitions
41	* @ingroup grp_rt
42	* @{
43	*/
44
45	/**
46	* EFLAGS Bits.
47	*/
48	typedef struct X86EFLAGSBITS
49	{
50	/** Bit 0 - CF - Carry flag - Status flag. */
51	unsigned u1CF : 1;
52	/** Bit 1 - 1 - Reserved flag. */
53	unsigned u1Reserved0 : 1;
54	/** Bit 2 - PF - Parity flag - Status flag. */
55	unsigned u1PF : 1;
56	/** Bit 3 - 0 - Reserved flag. */
57	unsigned u1Reserved1 : 1;
58	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
59	unsigned u1AF : 1;
60	/** Bit 5 - 0 - Reserved flag. */
61	unsigned u1Reserved2 : 1;
62	/** Bit 6 - ZF - Zero flag - Status flag. */
63	unsigned u1ZF : 1;
64	/** Bit 7 - SF - Signed flag - Status flag. */
65	unsigned u1SF : 1;
66	/** Bit 8 - TF - Trap flag - System flag. */
67	unsigned u1TF : 1;
68	/** Bit 9 - IF - Interrupt flag - System flag. */
69	unsigned u1IF : 1;
70	/** Bit 10 - DF - Direction flag - Control flag. */
71	unsigned u1DF : 1;
72	/** Bit 11 - OF - Overflow flag - Status flag. */
73	unsigned u1OF : 1;
74	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
75	unsigned u2IOPL : 2;
76	/** Bit 14 - NT - Nested task flag - System flag. */
77	unsigned u1NT : 1;
78	/** Bit 15 - 0 - Reserved flag. */
79	unsigned u1Reserved3 : 1;
80	/** Bit 16 - RF - Resume flag - System flag. */
81	unsigned u1RF : 1;
82	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
83	unsigned u1VM : 1;
84	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
85	unsigned u1AC : 1;
86	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
87	unsigned u1VIF : 1;
88	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
89	unsigned u1VIP : 1;
90	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
91	unsigned u1ID : 1;
92	/** Bit 22-31 - 0 - Reserved flag. */
93	unsigned u10Reserved4 : 10;
94	} X86EFLAGSBITS;
95	/** Pointer to EFLAGS bits. */
96	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
97	/** Pointer to const EFLAGS bits. */
98	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
99
100	/**
101	* EFLAGS.
102	*/
103	typedef union X86EFLAGS
104	{
105	/** The plain unsigned view. */
106	uint32_t u;
107	/** The bitfield view. */
108	X86EFLAGSBITS Bits;
109	/** The 8-bit view. */
110	uint8_t au8[4];
111	/** The 16-bit view. */
112	uint16_t au16[2];
113	/** The 32-bit view. */
114	uint32_t au32[1];
115	/** The 32-bit view. */
116	uint32_t u32;
117	} X86EFLAGS;
118	/** Pointer to EFLAGS. */
119	typedef X86EFLAGS *PX86EFLAGS;
120	/** Pointer to const EFLAGS. */
121	typedef const X86EFLAGS *PCX86EFLAGS;
122
123	/**
124	* RFLAGS (32 upper bits are reserved).
125	*/
126	typedef union X86RFLAGS
127	{
128	/** The plain unsigned view. */
129	uint64_t u;
130	/** The bitfield view. */
131	X86EFLAGSBITS Bits;
132	/** The 8-bit view. */
133	uint8_t au8[8];
134	/** The 16-bit view. */
135	uint16_t au16[4];
136	/** The 32-bit view. */
137	uint32_t au32[2];
138	/** The 64-bit view. */
139	uint64_t au64[1];
140	/** The 64-bit view. */
141	uint64_t u64;
142	} X86RFLAGS;
143	/** Pointer to RFLAGS. */
144	typedef X86RFLAGS *PX86RFLAGS;
145	/** Pointer to const RFLAGS. */
146	typedef const X86RFLAGS *PCX86RFLAGS;
147
148
149	/** @name EFLAGS
150	* @{
151	*/
152	/** Bit 0 - CF - Carry flag - Status flag. */
153	#define X86_EFL_CF RT_BIT(0)
154	/** Bit 1 - Reserved, reads as 1. */
155	#define X86_EFL_1 RT_BIT(1)
156	/** Bit 2 - PF - Parity flag - Status flag. */
157	#define X86_EFL_PF RT_BIT(2)
158	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
159	#define X86_EFL_AF RT_BIT(4)
160	/** Bit 6 - ZF - Zero flag - Status flag. */
161	#define X86_EFL_ZF RT_BIT(6)
162	/** Bit 7 - SF - Signed flag - Status flag. */
163	#define X86_EFL_SF RT_BIT(7)
164	/** Bit 8 - TF - Trap flag - System flag. */
165	#define X86_EFL_TF RT_BIT(8)
166	/** Bit 9 - IF - Interrupt flag - System flag. */
167	#define X86_EFL_IF RT_BIT(9)
168	/** Bit 10 - DF - Direction flag - Control flag. */
169	#define X86_EFL_DF RT_BIT(10)
170	/** Bit 11 - OF - Overflow flag - Status flag. */
171	#define X86_EFL_OF RT_BIT(11)
172	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
173	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
174	/** Bit 14 - NT - Nested task flag - System flag. */
175	#define X86_EFL_NT RT_BIT(14)
176	/** Bit 16 - RF - Resume flag - System flag. */
177	#define X86_EFL_RF RT_BIT(16)
178	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
179	#define X86_EFL_VM RT_BIT(17)
180	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
181	#define X86_EFL_AC RT_BIT(18)
182	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
183	#define X86_EFL_VIF RT_BIT(19)
184	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
185	#define X86_EFL_VIP RT_BIT(20)
186	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
187	#define X86_EFL_ID RT_BIT(21)
188	/** IOPL shift. */
189	#define X86_EFL_IOPL_SHIFT 12
190	/** The the IOPL level from the flags. */
191	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
192	/** Bits restored by popf */
193	#define X86_EFL_POPF_BITS (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID)
194	/** @} */
195
196
197	/** CPUID Feature information - ECX.
198	* CPUID query with EAX=1.
199	*/
200	typedef struct X86CPUIDFEATECX
201	{
202	/** Bit 0 - SSE3 - Supports SSE3 or not. */
203	unsigned u1SSE3 : 1;
204	/** Bit 1 - PCLMULQDQ. */
205	unsigned u1PCLMULQDQ : 1;
206	/** Bit 2 - DS Area 64-bit layout. */
207	unsigned u1DTE64 : 1;
208	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
209	unsigned u1Monitor : 1;
210	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
211	unsigned u1CPLDS : 1;
212	/** Bit 5 - VMX - Virtual Machine Technology. */
213	unsigned u1VMX : 1;
214	/** Bit 6 - SMX: Safer Mode Extensions. */
215	unsigned u1SMX : 1;
216	/** Bit 7 - EST - Enh. SpeedStep Tech. */
217	unsigned u1EST : 1;
218	/** Bit 8 - TM2 - Terminal Monitor 2. */
219	unsigned u1TM2 : 1;
220	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
221	unsigned u1SSSE3 : 1;
222	/** Bit 10 - CNTX-ID - L1 Context ID. */
223	unsigned u1CNTXID : 1;
224	/** Bit 11 - Reserved. */
225	unsigned u1Reserved1 : 1;
226	/** Bit 12 - FMA. */
227	unsigned u1FMA : 1;
228	/** Bit 13 - CX16 - CMPXCHG16B. */
229	unsigned u1CX16 : 1;
230	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
231	unsigned u1TPRUpdate : 1;
232	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
233	unsigned u1PDCM : 1;
234	/** Bit 16 - Reserved. */
235	unsigned u1Reserved2 : 1;
236	/** Bit 17 - PCID - Process-context identifiers. */
237	unsigned u1PCID : 1;
238	/** Bit 18 - Direct Cache Access. */
239	unsigned u1DCA : 1;
240	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
241	unsigned u1SSE4_1 : 1;
242	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
243	unsigned u1SSE4_2 : 1;
244	/** Bit 21 - x2APIC. */
245	unsigned u1x2APIC : 1;
246	/** Bit 22 - MOVBE - Supports MOVBE. */
247	unsigned u1MOVBE : 1;
248	/** Bit 23 - POPCNT - Supports POPCNT. */
249	unsigned u1POPCNT : 1;
250	/** Bit 24 - TSC-Deadline. */
251	unsigned u1TSCDEADLINE : 1;
252	/** Bit 25 - AES. */
253	unsigned u1AES : 1;
254	/** Bit 26 - XSAVE - Supports XSAVE. */
255	unsigned u1XSAVE : 1;
256	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
257	unsigned u1OSXSAVE : 1;
258	/** Bit 28 - AVX - Supports AVX instruction extensions. */
259	unsigned u1AVX : 1;
260	/** Bit 29 - 30 - Reserved */
261	unsigned u2Reserved3 : 2;
262	/** Bit 31 - Hypervisor present (we're a guest). */
263	unsigned u1HVP : 1;
264	} X86CPUIDFEATECX;
265	/** Pointer to CPUID Feature Information - ECX. */
266	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
267	/** Pointer to const CPUID Feature Information - ECX. */
268	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
269
270
271	/** CPUID Feature Information - EDX.
272	* CPUID query with EAX=1.
273	*/
274	typedef struct X86CPUIDFEATEDX
275	{
276	/** Bit 0 - FPU - x87 FPU on Chip. */
277	unsigned u1FPU : 1;
278	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
279	unsigned u1VME : 1;
280	/** Bit 2 - DE - Debugging extensions. */
281	unsigned u1DE : 1;
282	/** Bit 3 - PSE - Page Size Extension. */
283	unsigned u1PSE : 1;
284	/** Bit 4 - TSC - Time Stamp Counter. */
285	unsigned u1TSC : 1;
286	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
287	unsigned u1MSR : 1;
288	/** Bit 6 - PAE - Physical Address Extension. */
289	unsigned u1PAE : 1;
290	/** Bit 7 - MCE - Machine Check Exception. */
291	unsigned u1MCE : 1;
292	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
293	unsigned u1CX8 : 1;
294	/** Bit 9 - APIC - APIC On-Chip. */
295	unsigned u1APIC : 1;
296	/** Bit 10 - Reserved. */
297	unsigned u1Reserved1 : 1;
298	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
299	unsigned u1SEP : 1;
300	/** Bit 12 - MTRR - Memory Type Range Registers. */
301	unsigned u1MTRR : 1;
302	/** Bit 13 - PGE - PTE Global Bit. */
303	unsigned u1PGE : 1;
304	/** Bit 14 - MCA - Machine Check Architecture. */
305	unsigned u1MCA : 1;
306	/** Bit 15 - CMOV - Conditional Move Instructions. */
307	unsigned u1CMOV : 1;
308	/** Bit 16 - PAT - Page Attribute Table. */
309	unsigned u1PAT : 1;
310	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
311	unsigned u1PSE36 : 1;
312	/** Bit 18 - PSN - Processor Serial Number. */
313	unsigned u1PSN : 1;
314	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
315	unsigned u1CLFSH : 1;
316	/** Bit 20 - Reserved. */
317	unsigned u1Reserved2 : 1;
318	/** Bit 21 - DS - Debug Store. */
319	unsigned u1DS : 1;
320	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
321	unsigned u1ACPI : 1;
322	/** Bit 23 - MMX - Intel MMX 'Technology'. */
323	unsigned u1MMX : 1;
324	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
325	unsigned u1FXSR : 1;
326	/** Bit 25 - SSE - SSE Support. */
327	unsigned u1SSE : 1;
328	/** Bit 26 - SSE2 - SSE2 Support. */
329	unsigned u1SSE2 : 1;
330	/** Bit 27 - SS - Self Snoop. */
331	unsigned u1SS : 1;
332	/** Bit 28 - HTT - Hyper-Threading Technology. */
333	unsigned u1HTT : 1;
334	/** Bit 29 - TM - Thermal Monitor. */
335	unsigned u1TM : 1;
336	/** Bit 30 - Reserved - . */
337	unsigned u1Reserved3 : 1;
338	/** Bit 31 - PBE - Pending Break Enabled. */
339	unsigned u1PBE : 1;
340	} X86CPUIDFEATEDX;
341	/** Pointer to CPUID Feature Information - EDX. */
342	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
343	/** Pointer to const CPUID Feature Information - EDX. */
344	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
345
346	/** @name CPUID Vendor information.
347	* CPUID query with EAX=0.
348	* @{
349	*/
350	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
351	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
352	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
353
354	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
355	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
356	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
357	/** @} */
358
359
360	/** @name CPUID Feature information.
361	* CPUID query with EAX=1.
362	* @{
363	*/
364	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
365	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
366	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
367	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
368	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
369	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
370	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
371	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
372	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
373	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
374	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
375	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
376	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
377	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
378	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
379	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
380	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
381	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
382	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
383	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
384	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
385	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
386	/** ECX Bit 12 - FMA. */
387	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
388	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
389	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
390	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
391	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
392	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
393	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
394	/** ECX Bit 17 - PCID - Process-context identifiers. */
395	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
396	/** ECX Bit 18 - DCA - Direct Cache Access. */
397	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
398	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
399	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
400	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
401	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
402	/** ECX Bit 21 - x2APIC support. */
403	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
404	/** ECX Bit 22 - MOVBE instruction. */
405	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
406	/** ECX Bit 23 - POPCNT instruction. */
407	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
408	/** ECX Bir 24 - TSC-Deadline. */
409	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
410	/** ECX Bit 25 - AES instructions. */
411	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
412	/** ECX Bit 26 - XSAVE instruction. */
413	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
414	/** ECX Bit 27 - OSXSAVE instruction. */
415	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
416	/** ECX Bit 28 - AVX. */
417	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
418	/** ECX Bit 31 - Hypervisor Present (software only). */
419	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
420
421
422	/** Bit 0 - FPU - x87 FPU on Chip. */
423	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
424	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
425	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
426	/** Bit 2 - DE - Debugging extensions. */
427	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
428	/** Bit 3 - PSE - Page Size Extension. */
429	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
430	/** Bit 4 - TSC - Time Stamp Counter. */
431	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
432	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
433	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
434	/** Bit 6 - PAE - Physical Address Extension. */
435	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
436	/** Bit 7 - MCE - Machine Check Exception. */
437	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
438	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
439	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
440	/** Bit 9 - APIC - APIC On-Chip. */
441	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
442	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
443	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
444	/** Bit 12 - MTRR - Memory Type Range Registers. */
445	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
446	/** Bit 13 - PGE - PTE Global Bit. */
447	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
448	/** Bit 14 - MCA - Machine Check Architecture. */
449	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
450	/** Bit 15 - CMOV - Conditional Move Instructions. */
451	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
452	/** Bit 16 - PAT - Page Attribute Table. */
453	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
454	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
455	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
456	/** Bit 18 - PSN - Processor Serial Number. */
457	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
458	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
459	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
460	/** Bit 21 - DS - Debug Store. */
461	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
462	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
463	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
464	/** Bit 23 - MMX - Intel MMX Technology. */
465	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
466	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
467	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
468	/** Bit 25 - SSE - SSE Support. */
469	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
470	/** Bit 26 - SSE2 - SSE2 Support. */
471	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
472	/** Bit 27 - SS - Self Snoop. */
473	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
474	/** Bit 28 - HTT - Hyper-Threading Technology. */
475	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
476	/** Bit 29 - TM - Therm. Monitor. */
477	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
478	/** Bit 31 - PBE - Pending Break Enabled. */
479	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
480	/** @} */
481
482	/** @name CPUID mwait/monitor information.
483	* CPUID query with EAX=5.
484	* @{
485	*/
486	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
487	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
488	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
489	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
490	/** @} */
491
492
493	/** @name CPUID AMD Feature information.
494	* CPUID query with EAX=0x80000001.
495	* @{
496	*/
497	/** Bit 0 - FPU - x87 FPU on Chip. */
498	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
499	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
500	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
501	/** Bit 2 - DE - Debugging extensions. */
502	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
503	/** Bit 3 - PSE - Page Size Extension. */
504	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
505	/** Bit 4 - TSC - Time Stamp Counter. */
506	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
507	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
508	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
509	/** Bit 6 - PAE - Physical Address Extension. */
510	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
511	/** Bit 7 - MCE - Machine Check Exception. */
512	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
513	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
514	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
515	/** Bit 9 - APIC - APIC On-Chip. */
516	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
517	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
518	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
519	/** Bit 12 - MTRR - Memory Type Range Registers. */
520	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
521	/** Bit 13 - PGE - PTE Global Bit. */
522	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
523	/** Bit 14 - MCA - Machine Check Architecture. */
524	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
525	/** Bit 15 - CMOV - Conditional Move Instructions. */
526	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
527	/** Bit 16 - PAT - Page Attribute Table. */
528	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
529	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
530	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
531	/** Bit 20 - NX - AMD No-Execute Page Protection. */
532	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
533	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
534	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
535	/** Bit 23 - MMX - Intel MMX Technology. */
536	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
537	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
538	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
539	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
540	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
541	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
542	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
543	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
544	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
545	/** Bit 29 - LM - AMD Long Mode. */
546	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
547	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
548	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
549	/** Bit 31 - 3DNOW - AMD 3DNow. */
550	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
551
552	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
553	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
554	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
555	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
556	/** Bit 2 - SVM - AMD VM extensions. */
557	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
558	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
559	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
560	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
561	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
562	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
563	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
564	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
565	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
566	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
567	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
568	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
569	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
570	/** Bit 9 - OSVW - AMD OS visible workaround. */
571	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
572	/** Bit 10 - IBS - Instruct based sampling. */
573	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
574	/** Bit 11 - SSE5 - SSE5 instruction support. */
575	#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
576	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
577	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
578	/** Bit 13 - WDT - AMD Watchdog timer support. */
579	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
580
581	/** @} */
582
583
584	/** @name CPUID AMD Feature information.
585	* CPUID query with EAX=0x80000007.
586	* @{
587	*/
588	/** Bit 0 - TS - Temperature Sensor. */
589	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
590	/** Bit 1 - FID - Frequency ID Control. */
591	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
592	/** Bit 2 - VID - Voltage ID Control. */
593	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
594	/** Bit 3 - TTP - THERMTRIP. */
595	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
596	/** Bit 4 - TM - Hardware Thermal Control. */
597	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
598	/** Bit 5 - STC - Software Thermal Control. */
599	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
600	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
601	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
602	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
603	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
604	/** Bit 8 - TSCINVAR - TSC Invariant. */
605	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
606	/** @} */
607
608
609	/** @name CR0
610	* @{ */
611	/** Bit 0 - PE - Protection Enabled */
612	#define X86_CR0_PE RT_BIT(0)
613	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
614	/** Bit 1 - MP - Monitor Coprocessor */
615	#define X86_CR0_MP RT_BIT(1)
616	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
617	/** Bit 2 - EM - Emulation. */
618	#define X86_CR0_EM RT_BIT(2)
619	#define X86_CR0_EMULATE_FPU RT_BIT(2)
620	/** Bit 3 - TS - Task Switch. */
621	#define X86_CR0_TS RT_BIT(3)
622	#define X86_CR0_TASK_SWITCH RT_BIT(3)
623	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
624	#define X86_CR0_ET RT_BIT(4)
625	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
626	/** Bit 5 - NE - Numeric error. */
627	#define X86_CR0_NE RT_BIT(5)
628	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
629	/** Bit 16 - WP - Write Protect. */
630	#define X86_CR0_WP RT_BIT(16)
631	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
632	/** Bit 18 - AM - Alignment Mask. */
633	#define X86_CR0_AM RT_BIT(18)
634	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
635	/** Bit 29 - NW - Not Write-though. */
636	#define X86_CR0_NW RT_BIT(29)
637	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
638	/** Bit 30 - WP - Cache Disable. */
639	#define X86_CR0_CD RT_BIT(30)
640	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
641	/** Bit 31 - PG - Paging. */
642	#define X86_CR0_PG RT_BIT(31)
643	#define X86_CR0_PAGING RT_BIT(31)
644	/** @} */
645
646
647	/** @name CR3
648	* @{ */
649	/** Bit 3 - PWT - Page-level Writes Transparent. */
650	#define X86_CR3_PWT RT_BIT(3)
651	/** Bit 4 - PCD - Page-level Cache Disable. */
652	#define X86_CR3_PCD RT_BIT(4)
653	/** Bits 12-31 - - Page directory page number. */
654	#define X86_CR3_PAGE_MASK (0xfffff000)
655	/** Bits 5-31 - - PAE Page directory page number. */
656	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
657	/** Bits 12-51 - - AMD64 Page directory page number. */
658	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
659	/** @} */
660
661
662	/** @name CR4
663	* @{ */
664	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
665	#define X86_CR4_VME RT_BIT(0)
666	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
667	#define X86_CR4_PVI RT_BIT(1)
668	/** Bit 2 - TSD - Time Stamp Disable. */
669	#define X86_CR4_TSD RT_BIT(2)
670	/** Bit 3 - DE - Debugging Extensions. */
671	#define X86_CR4_DE RT_BIT(3)
672	/** Bit 4 - PSE - Page Size Extension. */
673	#define X86_CR4_PSE RT_BIT(4)
674	/** Bit 5 - PAE - Physical Address Extension. */
675	#define X86_CR4_PAE RT_BIT(5)
676	/** Bit 6 - MCE - Machine-Check Enable. */
677	#define X86_CR4_MCE RT_BIT(6)
678	/** Bit 7 - PGE - Page Global Enable. */
679	#define X86_CR4_PGE RT_BIT(7)
680	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
681	#define X86_CR4_PCE RT_BIT(8)
682	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
683	#define X86_CR4_OSFSXR RT_BIT(9)
684	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
685	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
686	/** Bit 13 - VMXE - VMX mode is enabled. */
687	#define X86_CR4_VMXE RT_BIT(13)
688	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
689	#define X86_CR4_SMXE RT_BIT(14)
690	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
691	#define X86_CR4_PCIDE RT_BIT(17)
692	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
693	* extended states. */
694	#define X86_CR4_OSXSAVE RT_BIT(18)
695	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
696	#define X86_CR4_SMEP RT_BIT(20)
697	/** @} */
698
699
700	/** @name DR6
701	* @{ */
702	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
703	#define X86_DR6_B0 RT_BIT(0)
704	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
705	#define X86_DR6_B1 RT_BIT(1)
706	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
707	#define X86_DR6_B2 RT_BIT(2)
708	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
709	#define X86_DR6_B3 RT_BIT(3)
710	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
711	#define X86_DR6_BD RT_BIT(13)
712	/** Bit 14 - BS - Single step */
713	#define X86_DR6_BS RT_BIT(14)
714	/** Bit 15 - BT - Task switch. (TSS T bit.) */
715	#define X86_DR6_BT RT_BIT(15)
716	/** Value of DR6 after powerup/reset. */
717	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
718	/** @} */
719
720
721	/** @name DR7
722	* @{ */
723	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
724	#define X86_DR7_L0 RT_BIT(0)
725	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
726	#define X86_DR7_G0 RT_BIT(1)
727	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
728	#define X86_DR7_L1 RT_BIT(2)
729	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
730	#define X86_DR7_G1 RT_BIT(3)
731	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
732	#define X86_DR7_L2 RT_BIT(4)
733	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
734	#define X86_DR7_G2 RT_BIT(5)
735	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
736	#define X86_DR7_L3 RT_BIT(6)
737	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
738	#define X86_DR7_G3 RT_BIT(7)
739	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
740	#define X86_DR7_LE RT_BIT(8)
741	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
742	#define X86_DR7_GE RT_BIT(9)
743
744	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
745	* any DR register is accessed. */
746	#define X86_DR7_GD RT_BIT(13)
747	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
748	#define X86_DR7_RW0_MASK (3 << 16)
749	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
750	#define X86_DR7_LEN0_MASK (3 << 18)
751	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
752	#define X86_DR7_RW1_MASK (3 << 20)
753	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
754	#define X86_DR7_LEN1_MASK (3 << 22)
755	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
756	#define X86_DR7_RW2_MASK (3 << 24)
757	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
758	#define X86_DR7_LEN2_MASK (3 << 26)
759	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
760	#define X86_DR7_RW3_MASK (3 << 28)
761	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
762	#define X86_DR7_LEN3_MASK (3 << 30)
763
764	/** Bits which must be 1s. */
765	#define X86_DR7_MB1_MASK (RT_BIT(10))
766
767	/** Calcs the L bit of Nth breakpoint.
768	* @param iBp The breakpoint number [0..3].
769	*/
770	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
771
772	/** Calcs the G bit of Nth breakpoint.
773	* @param iBp The breakpoint number [0..3].
774	*/
775	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
776
777	/** @name Read/Write values.
778	* @{ */
779	/** Break on instruction fetch only. */
780	#define X86_DR7_RW_EO 0U
781	/** Break on write only. */
782	#define X86_DR7_RW_WO 1U
783	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
784	#define X86_DR7_RW_IO 2U
785	/** Break on read or write (but not instruction fetches). */
786	#define X86_DR7_RW_RW 3U
787	/** @} */
788
789	/** Shifts a X86_DR7_RW_* value to its right place.
790	* @param iBp The breakpoint number [0..3].
791	* @param fRw One of the X86_DR7_RW_* value.
792	*/
793	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
794
795	/** @name Length values.
796	* @{ */
797	#define X86_DR7_LEN_BYTE 0U
798	#define X86_DR7_LEN_WORD 1U
799	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
800	#define X86_DR7_LEN_DWORD 3U
801	/** @} */
802
803	/** Shifts a X86_DR7_LEN_* value to its right place.
804	* @param iBp The breakpoint number [0..3].
805	* @param cb One of the X86_DR7_LEN_* values.
806	*/
807	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
808
809	/** Fetch the breakpoint length bits from the DR7 value.
810	* @param uDR7 DR7 value
811	* @param iBp The breakpoint number [0..3].
812	*/
813	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
814
815	/** Mask used to check if any breakpoints are enabled. */
816	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
817
818	/** Mask used to check if any io breakpoints are set. */
819	#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) \| X86_DR7_RW(1, X86_DR7_RW_IO) \| X86_DR7_RW(2, X86_DR7_RW_IO) \| X86_DR7_RW(3, X86_DR7_RW_IO))
820
821	/** Value of DR7 after powerup/reset. */
822	#define X86_DR7_INIT_VAL 0x400
823	/** @} */
824
825
826	/** @name Machine Specific Registers
827	* @{
828	*/
829
830	/** Time Stamp Counter. */
831	#define MSR_IA32_TSC 0x10
832
833	#define MSR_IA32_PLATFORM_ID 0x17
834
835	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
836	#define MSR_IA32_APICBASE 0x1b
837	#endif
838
839	/** CPU Feature control. */
840	#define MSR_IA32_FEATURE_CONTROL 0x3A
841	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
842	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
843
844	/** BIOS update trigger (microcode update). */
845	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
846
847	/** BIOS update signature (microcode). */
848	#define MSR_IA32_BIOS_SIGN_ID 0x8B
849
850	/** General performance counter no. 0. */
851	#define MSR_IA32_PMC0 0xC1
852	/** General performance counter no. 1. */
853	#define MSR_IA32_PMC1 0xC2
854	/** General performance counter no. 2. */
855	#define MSR_IA32_PMC2 0xC3
856	/** General performance counter no. 3. */
857	#define MSR_IA32_PMC3 0xC4
858
859	/** Nehalem power control. */
860	#define MSR_IA32_PLATFORM_INFO 0xCE
861
862	/** Get FSB clock status (Intel-specific). */
863	#define MSR_IA32_FSB_CLOCK_STS 0xCD
864
865	/** MTRR Capabilities. */
866	#define MSR_IA32_MTRR_CAP 0xFE
867
868
869	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
870	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
871	* R0 SS == CS + 8
872	* R3 CS == CS + 16
873	* R3 SS == CS + 24
874	*/
875	#define MSR_IA32_SYSENTER_CS 0x174
876	/** SYSENTER_ESP - the R0 ESP. */
877	#define MSR_IA32_SYSENTER_ESP 0x175
878	/** SYSENTER_EIP - the R0 EIP. */
879	#define MSR_IA32_SYSENTER_EIP 0x176
880	#endif
881
882	/** Machine Check Global Capabilities Register. */
883	#define MSR_IA32_MCP_CAP 0x179
884	/** Machine Check Global Status Register. */
885	#define MSR_IA32_MCP_STATUS 0x17A
886	/** Machine Check Global Control Register. */
887	#define MSR_IA32_MCP_CTRL 0x17B
888
889	/** Trace/Profile Resource Control (R/W) */
890	#define MSR_IA32_DEBUGCTL 0x1D9
891
892	/** Page Attribute Table. */
893	#define MSR_IA32_CR_PAT 0x277
894
895	/** Performance counter MSRs. (Intel only) */
896	#define MSR_IA32_PERFEVTSEL0 0x186
897	#define MSR_IA32_PERFEVTSEL1 0x187
898	#define MSR_IA32_FLEX_RATIO 0x194
899	#define MSR_IA32_PERF_STATUS 0x198
900	#define MSR_IA32_PERF_CTL 0x199
901	#define MSR_IA32_THERM_STATUS 0x19c
902
903	/** Enable misc. processor features (R/W). */
904	#define MSR_IA32_MISC_ENABLE 0x1A0
905	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
906	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
907	/** Automatic Thermal Control Circuit Enable (R/W). */
908	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
909	/** Performance Monitoring Available (R). */
910	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
911	/** Branch Trace Storage Unavailable (R/O). */
912	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
913	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
914	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
915	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
916	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
917	/** If MONITOR/MWAIT is supported (R/W). */
918	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
919	/** Limit CPUID Maxval to 3 leafs (R/W). */
920	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
921	/** When set to 1, xTPR messages are disabled (R/W). */
922	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
923	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
924	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
925
926	#define IA32_MTRR_PHYSBASE0 0x200
927	#define IA32_MTRR_PHYSMASK0 0x201
928	#define IA32_MTRR_PHYSBASE1 0x202
929	#define IA32_MTRR_PHYSMASK1 0x203
930	#define IA32_MTRR_PHYSBASE2 0x204
931	#define IA32_MTRR_PHYSMASK2 0x205
932	#define IA32_MTRR_PHYSBASE3 0x206
933	#define IA32_MTRR_PHYSMASK3 0x207
934	#define IA32_MTRR_PHYSBASE4 0x208
935	#define IA32_MTRR_PHYSMASK4 0x209
936	#define IA32_MTRR_PHYSBASE5 0x20a
937	#define IA32_MTRR_PHYSMASK5 0x20b
938	#define IA32_MTRR_PHYSBASE6 0x20c
939	#define IA32_MTRR_PHYSMASK6 0x20d
940	#define IA32_MTRR_PHYSBASE7 0x20e
941	#define IA32_MTRR_PHYSMASK7 0x20f
942	#define IA32_MTRR_PHYSBASE8 0x210
943	#define IA32_MTRR_PHYSMASK8 0x211
944	#define IA32_MTRR_PHYSBASE9 0x212
945	#define IA32_MTRR_PHYSMASK9 0x213
946
947	/** Fixed range MTRRs.
948	* @{ */
949	#define IA32_MTRR_FIX64K_00000 0x250
950	#define IA32_MTRR_FIX16K_80000 0x258
951	#define IA32_MTRR_FIX16K_A0000 0x259
952	#define IA32_MTRR_FIX4K_C0000 0x268
953	#define IA32_MTRR_FIX4K_C8000 0x269
954	#define IA32_MTRR_FIX4K_D0000 0x26a
955	#define IA32_MTRR_FIX4K_D8000 0x26b
956	#define IA32_MTRR_FIX4K_E0000 0x26c
957	#define IA32_MTRR_FIX4K_E8000 0x26d
958	#define IA32_MTRR_FIX4K_F0000 0x26e
959	#define IA32_MTRR_FIX4K_F8000 0x26f
960	/** @} */
961
962	/** MTRR Default Range. */
963	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
964
965	#define MSR_IA32_MC0_CTL 0x400
966	#define MSR_IA32_MC0_STATUS 0x401
967
968	/** Basic VMX information. */
969	#define MSR_IA32_VMX_BASIC_INFO 0x480
970	/** Allowed settings for pin-based VM execution controls */
971	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
972	/** Allowed settings for proc-based VM execution controls */
973	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
974	/** Allowed settings for the VMX exit controls. */
975	#define MSR_IA32_VMX_EXIT_CTLS 0x483
976	/** Allowed settings for the VMX entry controls. */
977	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
978	/** Misc VMX info. */
979	#define MSR_IA32_VMX_MISC 0x485
980	/** Fixed cleared bits in CR0. */
981	#define MSR_IA32_VMX_CR0_FIXED0 0x486
982	/** Fixed set bits in CR0. */
983	#define MSR_IA32_VMX_CR0_FIXED1 0x487
984	/** Fixed cleared bits in CR4. */
985	#define MSR_IA32_VMX_CR4_FIXED0 0x488
986	/** Fixed set bits in CR4. */
987	#define MSR_IA32_VMX_CR4_FIXED1 0x489
988	/** Information for enumerating fields in the VMCS. */
989	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
990	/** Allowed settings for secondary proc-based VM execution controls */
991	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
992	/** EPT capabilities. */
993	#define MSR_IA32_VMX_EPT_CAPS 0x48C
994	/** DS Save Area (R/W). */
995	#define MSR_IA32_DS_AREA 0x600
996	/** X2APIC MSR ranges. */
997	#define MSR_IA32_APIC_START 0x800
998	#define MSR_IA32_APIC_END 0x900
999
1000	/** K6 EFER - Extended Feature Enable Register. */
1001	#define MSR_K6_EFER 0xc0000080
1002	/** @todo document EFER */
1003	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1004	#define MSR_K6_EFER_SCE RT_BIT(0)
1005	/** Bit 8 - LME - Long mode enabled. (R/W) */
1006	#define MSR_K6_EFER_LME RT_BIT(8)
1007	/** Bit 10 - LMA - Long mode active. (R) */
1008	#define MSR_K6_EFER_LMA RT_BIT(10)
1009	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1010	#define MSR_K6_EFER_NXE RT_BIT(11)
1011	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1012	#define MSR_K6_EFER_SVME RT_BIT(12)
1013	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1014	#define MSR_K6_EFER_LMSLE RT_BIT(13)
1015	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1016	#define MSR_K6_EFER_FFXSR RT_BIT(14)
1017	/** K6 STAR - SYSCALL/RET targets. */
1018	#define MSR_K6_STAR 0xc0000081
1019	/** Shift value for getting the SYSRET CS and SS value. */
1020	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1021	/** Shift value for getting the SYSCALL CS and SS value. */
1022	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1023	/** Selector mask for use after shifting. */
1024	#define MSR_K6_STAR_SEL_MASK 0xffff
1025	/** The mask which give the SYSCALL EIP. */
1026	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
1027	/** K6 WHCR - Write Handling Control Register. */
1028	#define MSR_K6_WHCR 0xc0000082
1029	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1030	#define MSR_K6_UWCCR 0xc0000085
1031	/** K6 PSOR - Processor State Observability Register. */
1032	#define MSR_K6_PSOR 0xc0000087
1033	/** K6 PFIR - Page Flush/Invalidate Register. */
1034	#define MSR_K6_PFIR 0xc0000088
1035
1036	/** Performance counter MSRs. (AMD only) */
1037	#define MSR_K7_EVNTSEL0 0xc0010000
1038	#define MSR_K7_EVNTSEL1 0xc0010001
1039	#define MSR_K7_EVNTSEL2 0xc0010002
1040	#define MSR_K7_EVNTSEL3 0xc0010003
1041	#define MSR_K7_PERFCTR0 0xc0010004
1042	#define MSR_K7_PERFCTR1 0xc0010005
1043	#define MSR_K7_PERFCTR2 0xc0010006
1044	#define MSR_K7_PERFCTR3 0xc0010007
1045
1046	#define MSR_K8_HWCR 0xc0010015
1047
1048	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1049	#define MSR_K8_LSTAR 0xc0000082
1050	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1051	#define MSR_K8_CSTAR 0xc0000083
1052	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1053	#define MSR_K8_SF_MASK 0xc0000084
1054	/** K8 FS.base - The 64-bit base FS register. */
1055	#define MSR_K8_FS_BASE 0xc0000100
1056	/** K8 GS.base - The 64-bit base GS register. */
1057	#define MSR_K8_GS_BASE 0xc0000101
1058	/** K8 KernelGSbase - Used with SWAPGS. */
1059	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
1060	#define MSR_K8_TSC_AUX 0xc0000103
1061	#define MSR_K8_SYSCFG 0xc0010010
1062	#define MSR_K8_HWCR 0xc0010015
1063	#define MSR_K8_IORRBASE0 0xc0010016
1064	#define MSR_K8_IORRMASK0 0xc0010017
1065	#define MSR_K8_IORRBASE1 0xc0010018
1066	#define MSR_K8_IORRMASK1 0xc0010019
1067	#define MSR_K8_TOP_MEM1 0xc001001a
1068	#define MSR_K8_TOP_MEM2 0xc001001d
1069	#define MSR_K8_VM_CR 0xc0010114
1070	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
1071
1072	#define MSR_K8_IGNNE 0xc0010115
1073	#define MSR_K8_SMM_CTL 0xc0010116
1074	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1075	* host state during world switch.
1076	*/
1077	#define MSR_K8_VM_HSAVE_PA 0xc0010117
1078
1079	/** @} */
1080
1081
1082	/** @name Page Table / Directory / Directory Pointers / L4.
1083	* @{
1084	*/
1085
1086	/** Page table/directory entry as an unsigned integer. */
1087	typedef uint32_t X86PGUINT;
1088	/** Pointer to a page table/directory table entry as an unsigned integer. */
1089	typedef X86PGUINT *PX86PGUINT;
1090	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1091	typedef X86PGUINT const *PCX86PGUINT;
1092
1093	/** Number of entries in a 32-bit PT/PD. */
1094	#define X86_PG_ENTRIES 1024
1095
1096
1097	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1098	typedef uint64_t X86PGPAEUINT;
1099	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1100	typedef X86PGPAEUINT *PX86PGPAEUINT;
1101	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1102	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1103
1104	/** Number of entries in a PAE PT/PD. */
1105	#define X86_PG_PAE_ENTRIES 512
1106	/** Number of entries in a PAE PDPT. */
1107	#define X86_PG_PAE_PDPE_ENTRIES 4
1108
1109	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1110	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1111	/** Number of entries in an AMD64 PDPT.
1112	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1113	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1114
1115	/** The size of a 4KB page. */
1116	#define X86_PAGE_4K_SIZE _4K
1117	/** The page shift of a 4KB page. */
1118	#define X86_PAGE_4K_SHIFT 12
1119	/** The 4KB page offset mask. */
1120	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1121	/** The 4KB page base mask for virtual addresses. */
1122	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1123	/** The 4KB page base mask for virtual addresses - 32bit version. */
1124	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1125
1126	/** The size of a 2MB page. */
1127	#define X86_PAGE_2M_SIZE _2M
1128	/** The page shift of a 2MB page. */
1129	#define X86_PAGE_2M_SHIFT 21
1130	/** The 2MB page offset mask. */
1131	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1132	/** The 2MB page base mask for virtual addresses. */
1133	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1134	/** The 2MB page base mask for virtual addresses - 32bit version. */
1135	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1136
1137	/** The size of a 4MB page. */
1138	#define X86_PAGE_4M_SIZE _4M
1139	/** The page shift of a 4MB page. */
1140	#define X86_PAGE_4M_SHIFT 22
1141	/** The 4MB page offset mask. */
1142	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1143	/** The 4MB page base mask for virtual addresses. */
1144	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1145	/** The 4MB page base mask for virtual addresses - 32bit version. */
1146	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1147
1148
1149
1150	/** @name Page Table Entry
1151	* @{
1152	*/
1153	/** Bit 0 - P - Present bit. */
1154	#define X86_PTE_BIT_P 0
1155	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1156	#define X86_PTE_BIT_RW 1
1157	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1158	#define X86_PTE_BIT_US 2
1159	/** Bit 3 - PWT - Page level write thru bit. */
1160	#define X86_PTE_BIT_PWT 3
1161	/** Bit 4 - PCD - Page level cache disable bit. */
1162	#define X86_PTE_BIT_PCD 4
1163	/** Bit 5 - A - Access bit. */
1164	#define X86_PTE_BIT_A 5
1165	/** Bit 6 - D - Dirty bit. */
1166	#define X86_PTE_BIT_D 6
1167	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1168	#define X86_PTE_BIT_PAT 7
1169	/** Bit 8 - G - Global flag. */
1170	#define X86_PTE_BIT_G 8
1171
1172	/** Bit 0 - P - Present bit mask. */
1173	#define X86_PTE_P RT_BIT(0)
1174	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1175	#define X86_PTE_RW RT_BIT(1)
1176	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1177	#define X86_PTE_US RT_BIT(2)
1178	/** Bit 3 - PWT - Page level write thru bit mask. */
1179	#define X86_PTE_PWT RT_BIT(3)
1180	/** Bit 4 - PCD - Page level cache disable bit mask. */
1181	#define X86_PTE_PCD RT_BIT(4)
1182	/** Bit 5 - A - Access bit mask. */
1183	#define X86_PTE_A RT_BIT(5)
1184	/** Bit 6 - D - Dirty bit mask. */
1185	#define X86_PTE_D RT_BIT(6)
1186	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1187	#define X86_PTE_PAT RT_BIT(7)
1188	/** Bit 8 - G - Global bit mask. */
1189	#define X86_PTE_G RT_BIT(8)
1190
1191	/** Bits 9-11 - - Available for use to system software. */
1192	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1193	/** Bits 12-31 - - Physical Page number of the next level. */
1194	#define X86_PTE_PG_MASK ( 0xfffff000 )
1195
1196	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1197	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1198	/** Bits 63 - NX - PAE/LM - No execution flag. */
1199	#define X86_PTE_PAE_NX RT_BIT_64(63)
1200	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1201	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1202	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1203	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1204	/** No bits - - LM - MBZ bits when NX is active. */
1205	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1206	/** Bits 63 - - LM - MBZ bits when no NX. */
1207	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1208
1209	/**
1210	* Page table entry.
1211	*/
1212	typedef struct X86PTEBITS
1213	{
1214	/** Flags whether(=1) or not the page is present. */
1215	unsigned u1Present : 1;
1216	/** Read(=0) / Write(=1) flag. */
1217	unsigned u1Write : 1;
1218	/** User(=1) / Supervisor (=0) flag. */
1219	unsigned u1User : 1;
1220	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1221	unsigned u1WriteThru : 1;
1222	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1223	unsigned u1CacheDisable : 1;
1224	/** Accessed flag.
1225	* Indicates that the page have been read or written to. */
1226	unsigned u1Accessed : 1;
1227	/** Dirty flag.
1228	* Indicates that the page has been written to. */
1229	unsigned u1Dirty : 1;
1230	/** Reserved / If PAT enabled, bit 2 of the index. */
1231	unsigned u1PAT : 1;
1232	/** Global flag. (Ignored in all but final level.) */
1233	unsigned u1Global : 1;
1234	/** Available for use to system software. */
1235	unsigned u3Available : 3;
1236	/** Physical Page number of the next level. */
1237	unsigned u20PageNo : 20;
1238	} X86PTEBITS;
1239	/** Pointer to a page table entry. */
1240	typedef X86PTEBITS *PX86PTEBITS;
1241	/** Pointer to a const page table entry. */
1242	typedef const X86PTEBITS *PCX86PTEBITS;
1243
1244	/**
1245	* Page table entry.
1246	*/
1247	typedef union X86PTE
1248	{
1249	/** Unsigned integer view */
1250	X86PGUINT u;
1251	/** Bit field view. */
1252	X86PTEBITS n;
1253	/** 32-bit view. */
1254	uint32_t au32[1];
1255	/** 16-bit view. */
1256	uint16_t au16[2];
1257	/** 8-bit view. */
1258	uint8_t au8[4];
1259	} X86PTE;
1260	/** Pointer to a page table entry. */
1261	typedef X86PTE *PX86PTE;
1262	/** Pointer to a const page table entry. */
1263	typedef const X86PTE *PCX86PTE;
1264
1265
1266	/**
1267	* PAE page table entry.
1268	*/
1269	typedef struct X86PTEPAEBITS
1270	{
1271	/** Flags whether(=1) or not the page is present. */
1272	uint32_t u1Present : 1;
1273	/** Read(=0) / Write(=1) flag. */
1274	uint32_t u1Write : 1;
1275	/** User(=1) / Supervisor(=0) flag. */
1276	uint32_t u1User : 1;
1277	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1278	uint32_t u1WriteThru : 1;
1279	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1280	uint32_t u1CacheDisable : 1;
1281	/** Accessed flag.
1282	* Indicates that the page have been read or written to. */
1283	uint32_t u1Accessed : 1;
1284	/** Dirty flag.
1285	* Indicates that the page has been written to. */
1286	uint32_t u1Dirty : 1;
1287	/** Reserved / If PAT enabled, bit 2 of the index. */
1288	uint32_t u1PAT : 1;
1289	/** Global flag. (Ignored in all but final level.) */
1290	uint32_t u1Global : 1;
1291	/** Available for use to system software. */
1292	uint32_t u3Available : 3;
1293	/** Physical Page number of the next level - Low Part. Don't use this. */
1294	uint32_t u20PageNoLow : 20;
1295	/** Physical Page number of the next level - High Part. Don't use this. */
1296	uint32_t u20PageNoHigh : 20;
1297	/** MBZ bits */
1298	uint32_t u11Reserved : 11;
1299	/** No Execute flag. */
1300	uint32_t u1NoExecute : 1;
1301	} X86PTEPAEBITS;
1302	/** Pointer to a page table entry. */
1303	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1304	/** Pointer to a page table entry. */
1305	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1306
1307	/**
1308	* PAE Page table entry.
1309	*/
1310	typedef union X86PTEPAE
1311	{
1312	/** Unsigned integer view */
1313	X86PGPAEUINT u;
1314	/** Bit field view. */
1315	X86PTEPAEBITS n;
1316	/** 32-bit view. */
1317	uint32_t au32[2];
1318	/** 16-bit view. */
1319	uint16_t au16[4];
1320	/** 8-bit view. */
1321	uint8_t au8[8];
1322	} X86PTEPAE;
1323	/** Pointer to a PAE page table entry. */
1324	typedef X86PTEPAE *PX86PTEPAE;
1325	/** Pointer to a const PAE page table entry. */
1326	typedef const X86PTEPAE *PCX86PTEPAE;
1327	/** @} */
1328
1329	/**
1330	* Page table.
1331	*/
1332	typedef struct X86PT
1333	{
1334	/** PTE Array. */
1335	X86PTE a[X86_PG_ENTRIES];
1336	} X86PT;
1337	/** Pointer to a page table. */
1338	typedef X86PT *PX86PT;
1339	/** Pointer to a const page table. */
1340	typedef const X86PT *PCX86PT;
1341
1342	/** The page shift to get the PT index. */
1343	#define X86_PT_SHIFT 12
1344	/** The PT index mask (apply to a shifted page address). */
1345	#define X86_PT_MASK 0x3ff
1346
1347
1348	/**
1349	* Page directory.
1350	*/
1351	typedef struct X86PTPAE
1352	{
1353	/** PTE Array. */
1354	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1355	} X86PTPAE;
1356	/** Pointer to a page table. */
1357	typedef X86PTPAE *PX86PTPAE;
1358	/** Pointer to a const page table. */
1359	typedef const X86PTPAE *PCX86PTPAE;
1360
1361	/** The page shift to get the PA PTE index. */
1362	#define X86_PT_PAE_SHIFT 12
1363	/** The PAE PT index mask (apply to a shifted page address). */
1364	#define X86_PT_PAE_MASK 0x1ff
1365
1366
1367	/** @name 4KB Page Directory Entry
1368	* @{
1369	*/
1370	/** Bit 0 - P - Present bit. */
1371	#define X86_PDE_P RT_BIT(0)
1372	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1373	#define X86_PDE_RW RT_BIT(1)
1374	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1375	#define X86_PDE_US RT_BIT(2)
1376	/** Bit 3 - PWT - Page level write thru bit. */
1377	#define X86_PDE_PWT RT_BIT(3)
1378	/** Bit 4 - PCD - Page level cache disable bit. */
1379	#define X86_PDE_PCD RT_BIT(4)
1380	/** Bit 5 - A - Access bit. */
1381	#define X86_PDE_A RT_BIT(5)
1382	/** Bit 7 - PS - Page size attribute.
1383	* Clear mean 4KB pages, set means large pages (2/4MB). */
1384	#define X86_PDE_PS RT_BIT(7)
1385	/** Bits 9-11 - - Available for use to system software. */
1386	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1387	/** Bits 12-31 - - Physical Page number of the next level. */
1388	#define X86_PDE_PG_MASK ( 0xfffff000 )
1389
1390	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1391	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1392	/** Bits 63 - NX - PAE/LM - No execution flag. */
1393	#define X86_PDE_PAE_NX RT_BIT_64(63)
1394	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
1395	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
1396	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
1397	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
1398	/** Bit 7 - - LM - MBZ bits when NX is active. */
1399	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1400	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
1401	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1402
1403	/**
1404	* Page directory entry.
1405	*/
1406	typedef struct X86PDEBITS
1407	{
1408	/** Flags whether(=1) or not the page is present. */
1409	unsigned u1Present : 1;
1410	/** Read(=0) / Write(=1) flag. */
1411	unsigned u1Write : 1;
1412	/** User(=1) / Supervisor (=0) flag. */
1413	unsigned u1User : 1;
1414	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1415	unsigned u1WriteThru : 1;
1416	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1417	unsigned u1CacheDisable : 1;
1418	/** Accessed flag.
1419	* Indicates that the page has been read or written to. */
1420	unsigned u1Accessed : 1;
1421	/** Reserved / Ignored (dirty bit). */
1422	unsigned u1Reserved0 : 1;
1423	/** Size bit if PSE is enabled - in any event it's 0. */
1424	unsigned u1Size : 1;
1425	/** Reserved / Ignored (global bit). */
1426	unsigned u1Reserved1 : 1;
1427	/** Available for use to system software. */
1428	unsigned u3Available : 3;
1429	/** Physical Page number of the next level. */
1430	unsigned u20PageNo : 20;
1431	} X86PDEBITS;
1432	/** Pointer to a page directory entry. */
1433	typedef X86PDEBITS *PX86PDEBITS;
1434	/** Pointer to a const page directory entry. */
1435	typedef const X86PDEBITS *PCX86PDEBITS;
1436
1437
1438	/**
1439	* PAE page directory entry.
1440	*/
1441	typedef struct X86PDEPAEBITS
1442	{
1443	/** Flags whether(=1) or not the page is present. */
1444	uint32_t u1Present : 1;
1445	/** Read(=0) / Write(=1) flag. */
1446	uint32_t u1Write : 1;
1447	/** User(=1) / Supervisor (=0) flag. */
1448	uint32_t u1User : 1;
1449	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1450	uint32_t u1WriteThru : 1;
1451	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1452	uint32_t u1CacheDisable : 1;
1453	/** Accessed flag.
1454	* Indicates that the page has been read or written to. */
1455	uint32_t u1Accessed : 1;
1456	/** Reserved / Ignored (dirty bit). */
1457	uint32_t u1Reserved0 : 1;
1458	/** Size bit if PSE is enabled - in any event it's 0. */
1459	uint32_t u1Size : 1;
1460	/** Reserved / Ignored (global bit). / */
1461	uint32_t u1Reserved1 : 1;
1462	/** Available for use to system software. */
1463	uint32_t u3Available : 3;
1464	/** Physical Page number of the next level - Low Part. Don't use! */
1465	uint32_t u20PageNoLow : 20;
1466	/** Physical Page number of the next level - High Part. Don't use! */
1467	uint32_t u20PageNoHigh : 20;
1468	/** MBZ bits */
1469	uint32_t u11Reserved : 11;
1470	/** No Execute flag. */
1471	uint32_t u1NoExecute : 1;
1472	} X86PDEPAEBITS;
1473	/** Pointer to a page directory entry. */
1474	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1475	/** Pointer to a const page directory entry. */
1476	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1477
1478	/** @} */
1479
1480
1481	/** @name 2/4MB Page Directory Entry
1482	* @{
1483	*/
1484	/** Bit 0 - P - Present bit. */
1485	#define X86_PDE4M_P RT_BIT(0)
1486	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1487	#define X86_PDE4M_RW RT_BIT(1)
1488	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1489	#define X86_PDE4M_US RT_BIT(2)
1490	/** Bit 3 - PWT - Page level write thru bit. */
1491	#define X86_PDE4M_PWT RT_BIT(3)
1492	/** Bit 4 - PCD - Page level cache disable bit. */
1493	#define X86_PDE4M_PCD RT_BIT(4)
1494	/** Bit 5 - A - Access bit. */
1495	#define X86_PDE4M_A RT_BIT(5)
1496	/** Bit 6 - D - Dirty bit. */
1497	#define X86_PDE4M_D RT_BIT(6)
1498	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1499	#define X86_PDE4M_PS RT_BIT(7)
1500	/** Bit 8 - G - Global flag. */
1501	#define X86_PDE4M_G RT_BIT(8)
1502	/** Bits 9-11 - AVL - Available for use to system software. */
1503	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1504	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1505	#define X86_PDE4M_PAT RT_BIT(12)
1506	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1507	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1508	/** Bits 22-31 - - Physical Page number. */
1509	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1510	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1511	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1512	/** The number of bits to the high part of the page number. */
1513	#define X86_PDE4M_PG_HIGH_SHIFT 19
1514	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
1515	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1516
1517	/** Bits 21-51 - - PAE/LM - Physical Page number.
1518	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1519	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
1520	/** Bits 63 - NX - PAE/LM - No execution flag. */
1521	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
1522	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
1523	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
1524	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
1525	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
1526	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
1527	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
1528	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
1529	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
1530
1531	/**
1532	* 4MB page directory entry.
1533	*/
1534	typedef struct X86PDE4MBITS
1535	{
1536	/** Flags whether(=1) or not the page is present. */
1537	unsigned u1Present : 1;
1538	/** Read(=0) / Write(=1) flag. */
1539	unsigned u1Write : 1;
1540	/** User(=1) / Supervisor (=0) flag. */
1541	unsigned u1User : 1;
1542	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1543	unsigned u1WriteThru : 1;
1544	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1545	unsigned u1CacheDisable : 1;
1546	/** Accessed flag.
1547	* Indicates that the page have been read or written to. */
1548	unsigned u1Accessed : 1;
1549	/** Dirty flag.
1550	* Indicates that the page has been written to. */
1551	unsigned u1Dirty : 1;
1552	/** Page size flag - always 1 for 4MB entries. */
1553	unsigned u1Size : 1;
1554	/** Global flag. */
1555	unsigned u1Global : 1;
1556	/** Available for use to system software. */
1557	unsigned u3Available : 3;
1558	/** Reserved / If PAT enabled, bit 2 of the index. */
1559	unsigned u1PAT : 1;
1560	/** Bits 32-39 of the page number on AMD64.
1561	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1562	unsigned u8PageNoHigh : 8;
1563	/** Reserved. */
1564	unsigned u1Reserved : 1;
1565	/** Physical Page number of the page. */
1566	unsigned u10PageNo : 10;
1567	} X86PDE4MBITS;
1568	/** Pointer to a page table entry. */
1569	typedef X86PDE4MBITS *PX86PDE4MBITS;
1570	/** Pointer to a const page table entry. */
1571	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1572
1573
1574	/**
1575	* 2MB PAE page directory entry.
1576	*/
1577	typedef struct X86PDE2MPAEBITS
1578	{
1579	/** Flags whether(=1) or not the page is present. */
1580	uint32_t u1Present : 1;
1581	/** Read(=0) / Write(=1) flag. */
1582	uint32_t u1Write : 1;
1583	/** User(=1) / Supervisor(=0) flag. */
1584	uint32_t u1User : 1;
1585	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1586	uint32_t u1WriteThru : 1;
1587	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1588	uint32_t u1CacheDisable : 1;
1589	/** Accessed flag.
1590	* Indicates that the page have been read or written to. */
1591	uint32_t u1Accessed : 1;
1592	/** Dirty flag.
1593	* Indicates that the page has been written to. */
1594	uint32_t u1Dirty : 1;
1595	/** Page size flag - always 1 for 2MB entries. */
1596	uint32_t u1Size : 1;
1597	/** Global flag. */
1598	uint32_t u1Global : 1;
1599	/** Available for use to system software. */
1600	uint32_t u3Available : 3;
1601	/** Reserved / If PAT enabled, bit 2 of the index. */
1602	uint32_t u1PAT : 1;
1603	/** Reserved. */
1604	uint32_t u9Reserved : 9;
1605	/** Physical Page number of the next level - Low part. Don't use! */
1606	uint32_t u10PageNoLow : 10;
1607	/** Physical Page number of the next level - High part. Don't use! */
1608	uint32_t u20PageNoHigh : 20;
1609	/** MBZ bits */
1610	uint32_t u11Reserved : 11;
1611	/** No Execute flag. */
1612	uint32_t u1NoExecute : 1;
1613	} X86PDE2MPAEBITS;
1614	/** Pointer to a 2MB PAE page table entry. */
1615	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1616	/** Pointer to a 2MB PAE page table entry. */
1617	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1618
1619	/** @} */
1620
1621	/**
1622	* Page directory entry.
1623	*/
1624	typedef union X86PDE
1625	{
1626	/** Unsigned integer view. */
1627	X86PGUINT u;
1628	/** Normal view. */
1629	X86PDEBITS n;
1630	/** 4MB view (big). */
1631	X86PDE4MBITS b;
1632	/** 8 bit unsigned integer view. */
1633	uint8_t au8[4];
1634	/** 16 bit unsigned integer view. */
1635	uint16_t au16[2];
1636	/** 32 bit unsigned integer view. */
1637	uint32_t au32[1];
1638	} X86PDE;
1639	/** Pointer to a page directory entry. */
1640	typedef X86PDE *PX86PDE;
1641	/** Pointer to a const page directory entry. */
1642	typedef const X86PDE *PCX86PDE;
1643
1644	/**
1645	* PAE page directory entry.
1646	*/
1647	typedef union X86PDEPAE
1648	{
1649	/** Unsigned integer view. */
1650	X86PGPAEUINT u;
1651	/** Normal view. */
1652	X86PDEPAEBITS n;
1653	/** 2MB page view (big). */
1654	X86PDE2MPAEBITS b;
1655	/** 8 bit unsigned integer view. */
1656	uint8_t au8[8];
1657	/** 16 bit unsigned integer view. */
1658	uint16_t au16[4];
1659	/** 32 bit unsigned integer view. */
1660	uint32_t au32[2];
1661	} X86PDEPAE;
1662	/** Pointer to a page directory entry. */
1663	typedef X86PDEPAE *PX86PDEPAE;
1664	/** Pointer to a const page directory entry. */
1665	typedef const X86PDEPAE *PCX86PDEPAE;
1666
1667	/**
1668	* Page directory.
1669	*/
1670	typedef struct X86PD
1671	{
1672	/** PDE Array. */
1673	X86PDE a[X86_PG_ENTRIES];
1674	} X86PD;
1675	/** Pointer to a page directory. */
1676	typedef X86PD *PX86PD;
1677	/** Pointer to a const page directory. */
1678	typedef const X86PD *PCX86PD;
1679
1680	/** The page shift to get the PD index. */
1681	#define X86_PD_SHIFT 22
1682	/** The PD index mask (apply to a shifted page address). */
1683	#define X86_PD_MASK 0x3ff
1684
1685
1686	/**
1687	* PAE page directory.
1688	*/
1689	typedef struct X86PDPAE
1690	{
1691	/** PDE Array. */
1692	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1693	} X86PDPAE;
1694	/** Pointer to a PAE page directory. */
1695	typedef X86PDPAE *PX86PDPAE;
1696	/** Pointer to a const PAE page directory. */
1697	typedef const X86PDPAE *PCX86PDPAE;
1698
1699	/** The page shift to get the PAE PD index. */
1700	#define X86_PD_PAE_SHIFT 21
1701	/** The PAE PD index mask (apply to a shifted page address). */
1702	#define X86_PD_PAE_MASK 0x1ff
1703
1704
1705	/** @name Page Directory Pointer Table Entry (PAE)
1706	* @{
1707	*/
1708	/** Bit 0 - P - Present bit. */
1709	#define X86_PDPE_P RT_BIT(0)
1710	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1711	#define X86_PDPE_RW RT_BIT(1)
1712	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1713	#define X86_PDPE_US RT_BIT(2)
1714	/** Bit 3 - PWT - Page level write thru bit. */
1715	#define X86_PDPE_PWT RT_BIT(3)
1716	/** Bit 4 - PCD - Page level cache disable bit. */
1717	#define X86_PDPE_PCD RT_BIT(4)
1718	/** Bit 5 - A - Access bit. Long Mode only. */
1719	#define X86_PDPE_A RT_BIT(5)
1720	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
1721	#define X86_PDPE_LM_PS RT_BIT(7)
1722	/** Bits 9-11 - - Available for use to system software. */
1723	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1724	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1725	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
1726	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
1727	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
1728	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
1729	#define X86_PDPE_LM_NX RT_BIT_64(63)
1730	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
1731	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
1732	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
1733	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
1734	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
1735	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
1736	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
1737	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
1738
1739
1740	/**
1741	* Page directory pointer table entry.
1742	*/
1743	typedef struct X86PDPEBITS
1744	{
1745	/** Flags whether(=1) or not the page is present. */
1746	uint32_t u1Present : 1;
1747	/** Chunk of reserved bits. */
1748	uint32_t u2Reserved : 2;
1749	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1750	uint32_t u1WriteThru : 1;
1751	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1752	uint32_t u1CacheDisable : 1;
1753	/** Chunk of reserved bits. */
1754	uint32_t u4Reserved : 4;
1755	/** Available for use to system software. */
1756	uint32_t u3Available : 3;
1757	/** Physical Page number of the next level - Low Part. Don't use! */
1758	uint32_t u20PageNoLow : 20;
1759	/** Physical Page number of the next level - High Part. Don't use! */
1760	uint32_t u20PageNoHigh : 20;
1761	/** MBZ bits */
1762	uint32_t u12Reserved : 12;
1763	} X86PDPEBITS;
1764	/** Pointer to a page directory pointer table entry. */
1765	typedef X86PDPEBITS *PX86PTPEBITS;
1766	/** Pointer to a const page directory pointer table entry. */
1767	typedef const X86PDPEBITS *PCX86PTPEBITS;
1768
1769	/**
1770	* Page directory pointer table entry. AMD64 version
1771	*/
1772	typedef struct X86PDPEAMD64BITS
1773	{
1774	/** Flags whether(=1) or not the page is present. */
1775	uint32_t u1Present : 1;
1776	/** Read(=0) / Write(=1) flag. */
1777	uint32_t u1Write : 1;
1778	/** User(=1) / Supervisor (=0) flag. */
1779	uint32_t u1User : 1;
1780	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1781	uint32_t u1WriteThru : 1;
1782	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1783	uint32_t u1CacheDisable : 1;
1784	/** Accessed flag.
1785	* Indicates that the page have been read or written to. */
1786	uint32_t u1Accessed : 1;
1787	/** Chunk of reserved bits. */
1788	uint32_t u3Reserved : 3;
1789	/** Available for use to system software. */
1790	uint32_t u3Available : 3;
1791	/** Physical Page number of the next level - Low Part. Don't use! */
1792	uint32_t u20PageNoLow : 20;
1793	/** Physical Page number of the next level - High Part. Don't use! */
1794	uint32_t u20PageNoHigh : 20;
1795	/** MBZ bits */
1796	uint32_t u11Reserved : 11;
1797	/** No Execute flag. */
1798	uint32_t u1NoExecute : 1;
1799	} X86PDPEAMD64BITS;
1800	/** Pointer to a page directory pointer table entry. */
1801	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1802	/** Pointer to a const page directory pointer table entry. */
1803	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
1804
1805	/**
1806	* Page directory pointer table entry.
1807	*/
1808	typedef union X86PDPE
1809	{
1810	/** Unsigned integer view. */
1811	X86PGPAEUINT u;
1812	/** Normal view. */
1813	X86PDPEBITS n;
1814	/** AMD64 view. */
1815	X86PDPEAMD64BITS lm;
1816	/** 8 bit unsigned integer view. */
1817	uint8_t au8[8];
1818	/** 16 bit unsigned integer view. */
1819	uint16_t au16[4];
1820	/** 32 bit unsigned integer view. */
1821	uint32_t au32[2];
1822	} X86PDPE;
1823	/** Pointer to a page directory pointer table entry. */
1824	typedef X86PDPE *PX86PDPE;
1825	/** Pointer to a const page directory pointer table entry. */
1826	typedef const X86PDPE *PCX86PDPE;
1827
1828
1829	/**
1830	* Page directory pointer table.
1831	*/
1832	typedef struct X86PDPT
1833	{
1834	/** PDE Array. */
1835	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1836	} X86PDPT;
1837	/** Pointer to a page directory pointer table. */
1838	typedef X86PDPT *PX86PDPT;
1839	/** Pointer to a const page directory pointer table. */
1840	typedef const X86PDPT *PCX86PDPT;
1841
1842	/** The page shift to get the PDPT index. */
1843	#define X86_PDPT_SHIFT 30
1844	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1845	#define X86_PDPT_MASK_PAE 0x3
1846	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1847	#define X86_PDPT_MASK_AMD64 0x1ff
1848
1849	/** @} */
1850
1851
1852	/** @name Page Map Level-4 Entry (Long Mode PAE)
1853	* @{
1854	*/
1855	/** Bit 0 - P - Present bit. */
1856	#define X86_PML4E_P RT_BIT(0)
1857	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1858	#define X86_PML4E_RW RT_BIT(1)
1859	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1860	#define X86_PML4E_US RT_BIT(2)
1861	/** Bit 3 - PWT - Page level write thru bit. */
1862	#define X86_PML4E_PWT RT_BIT(3)
1863	/** Bit 4 - PCD - Page level cache disable bit. */
1864	#define X86_PML4E_PCD RT_BIT(4)
1865	/** Bit 5 - A - Access bit. */
1866	#define X86_PML4E_A RT_BIT(5)
1867	/** Bits 9-11 - - Available for use to system software. */
1868	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1869	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1870	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
1871	/** Bits 8, 7 - - MBZ bits when NX is active. */
1872	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
1873	/** Bits 63, 7 - - MBZ bits when no NX. */
1874	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
1875	/** Bits 63 - NX - PAE - No execution flag. */
1876	#define X86_PML4E_NX RT_BIT_64(63)
1877
1878	/**
1879	* Page Map Level-4 Entry
1880	*/
1881	typedef struct X86PML4EBITS
1882	{
1883	/** Flags whether(=1) or not the page is present. */
1884	uint32_t u1Present : 1;
1885	/** Read(=0) / Write(=1) flag. */
1886	uint32_t u1Write : 1;
1887	/** User(=1) / Supervisor (=0) flag. */
1888	uint32_t u1User : 1;
1889	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1890	uint32_t u1WriteThru : 1;
1891	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1892	uint32_t u1CacheDisable : 1;
1893	/** Accessed flag.
1894	* Indicates that the page have been read or written to. */
1895	uint32_t u1Accessed : 1;
1896	/** Chunk of reserved bits. */
1897	uint32_t u3Reserved : 3;
1898	/** Available for use to system software. */
1899	uint32_t u3Available : 3;
1900	/** Physical Page number of the next level - Low Part. Don't use! */
1901	uint32_t u20PageNoLow : 20;
1902	/** Physical Page number of the next level - High Part. Don't use! */
1903	uint32_t u20PageNoHigh : 20;
1904	/** MBZ bits */
1905	uint32_t u11Reserved : 11;
1906	/** No Execute flag. */
1907	uint32_t u1NoExecute : 1;
1908	} X86PML4EBITS;
1909	/** Pointer to a page map level-4 entry. */
1910	typedef X86PML4EBITS *PX86PML4EBITS;
1911	/** Pointer to a const page map level-4 entry. */
1912	typedef const X86PML4EBITS *PCX86PML4EBITS;
1913
1914	/**
1915	* Page Map Level-4 Entry.
1916	*/
1917	typedef union X86PML4E
1918	{
1919	/** Unsigned integer view. */
1920	X86PGPAEUINT u;
1921	/** Normal view. */
1922	X86PML4EBITS n;
1923	/** 8 bit unsigned integer view. */
1924	uint8_t au8[8];
1925	/** 16 bit unsigned integer view. */
1926	uint16_t au16[4];
1927	/** 32 bit unsigned integer view. */
1928	uint32_t au32[2];
1929	} X86PML4E;
1930	/** Pointer to a page map level-4 entry. */
1931	typedef X86PML4E *PX86PML4E;
1932	/** Pointer to a const page map level-4 entry. */
1933	typedef const X86PML4E *PCX86PML4E;
1934
1935
1936	/**
1937	* Page Map Level-4.
1938	*/
1939	typedef struct X86PML4
1940	{
1941	/** PDE Array. */
1942	X86PML4E a[X86_PG_PAE_ENTRIES];
1943	} X86PML4;
1944	/** Pointer to a page map level-4. */
1945	typedef X86PML4 *PX86PML4;
1946	/** Pointer to a const page map level-4. */
1947	typedef const X86PML4 *PCX86PML4;
1948
1949	/** The page shift to get the PML4 index. */
1950	#define X86_PML4_SHIFT 39
1951	/** The PML4 index mask (apply to a shifted page address). */
1952	#define X86_PML4_MASK 0x1ff
1953
1954	/** @} */
1955
1956	/** @} */
1957
1958
1959	/**
1960	* 80-bit MMX/FPU register type.
1961	*/
1962	typedef struct X86FPUMMX
1963	{
1964	uint8_t reg[10];
1965	} X86FPUMMX;
1966	/** Pointer to a 80-bit MMX/FPU register type. */
1967	typedef X86FPUMMX *PX86FPUMMX;
1968	/** Pointer to a const 80-bit MMX/FPU register type. */
1969	typedef const X86FPUMMX *PCX86FPUMMX;
1970
1971	/**
1972	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
1973	* @todo verify this...
1974	*/
1975	#pragma pack(1)
1976	typedef struct X86FPUSTATE
1977	{
1978	/** 0x00 - Control word. */
1979	uint16_t FCW;
1980	/** 0x02 - Alignment word */
1981	uint16_t Dummy1;
1982	/** 0x04 - Status word. */
1983	uint16_t FSW;
1984	/** 0x06 - Alignment word */
1985	uint16_t Dummy2;
1986	/** 0x08 - Tag word */
1987	uint16_t FTW;
1988	/** 0x0a - Alignment word */
1989	uint16_t Dummy3;
1990
1991	/** 0x0c - Instruction pointer. */
1992	uint32_t FPUIP;
1993	/** 0x10 - Code selector. */
1994	uint16_t CS;
1995	/** 0x12 - Opcode. */
1996	uint16_t FOP;
1997	/** 0x14 - FOO. */
1998	uint32_t FPUOO;
1999	/** 0x18 - FOS. */
2000	uint32_t FPUOS;
2001	/** 0x1c */
2002	union
2003	{
2004	/** MMX view. */
2005	uint64_t mmx;
2006	/** FPU view - todo. */
2007	X86FPUMMX fpu;
2008	/** Extended precision floating point view. */
2009	RTFLOAT80U r80;
2010	/** Extended precision floating point view v2. */
2011	RTFLOAT80U2 r80Ex;
2012	/** 8-bit view. */
2013	uint8_t au8[16];
2014	/** 16-bit view. */
2015	uint16_t au16[8];
2016	/** 32-bit view. */
2017	uint32_t au32[4];
2018	/** 64-bit view. */
2019	uint64_t au64[2];
2020	/** 128-bit view. (yeah, very helpful) */
2021	uint128_t au128[1];
2022	} regs[8];
2023	} X86FPUSTATE;
2024	#pragma pack()
2025	/** Pointer to a FPU state. */
2026	typedef X86FPUSTATE *PX86FPUSTATE;
2027	/** Pointer to a const FPU state. */
2028	typedef const X86FPUSTATE *PCX86FPUSTATE;
2029
2030	/**
2031	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2032	*/
2033	#pragma pack(1)
2034	typedef struct X86FXSTATE
2035	{
2036	/** 0x00 - Control word. */
2037	uint16_t FCW;
2038	/** 0x02 - Status word. */
2039	uint16_t FSW;
2040	/** 0x04 - Tag word. (The upper byte is always zero.) */
2041	uint16_t FTW;
2042	/** 0x06 - Opcode. */
2043	uint16_t FOP;
2044	/** 0x08 - Instruction pointer. */
2045	uint32_t FPUIP;
2046	/** 0x0c - Code selector. */
2047	uint16_t CS;
2048	uint16_t Rsrvd1;
2049	/** 0x10 - Data pointer. */
2050	uint32_t FPUDP;
2051	/** 0x14 - Data segment */
2052	uint16_t DS;
2053	/** 0x16 */
2054	uint16_t Rsrvd2;
2055	/** 0x18 */
2056	uint32_t MXCSR;
2057	/** 0x1c */
2058	uint32_t MXCSR_MASK;
2059	/** 0x20 */
2060	union
2061	{
2062	/** MMX view. */
2063	uint64_t mmx;
2064	/** FPU view - todo. */
2065	X86FPUMMX fpu;
2066	/** Extended precision floating point view. */
2067	RTFLOAT80U r80;
2068	/** Extended precision floating point view v2 */
2069	RTFLOAT80U2 r80Ex;
2070	/** 8-bit view. */
2071	uint8_t au8[16];
2072	/** 16-bit view. */
2073	uint16_t au16[8];
2074	/** 32-bit view. */
2075	uint32_t au32[4];
2076	/** 64-bit view. */
2077	uint64_t au64[2];
2078	/** 128-bit view. (yeah, very helpful) */
2079	uint128_t au128[1];
2080	} aRegs[8];
2081	/* - offset 160 - */
2082	union
2083	{
2084	/** XMM Register view . /
2085	uint128_t xmm;
2086	/** 8-bit view. */
2087	uint8_t au8[16];
2088	/** 16-bit view. */
2089	uint16_t au16[8];
2090	/** 32-bit view. */
2091	uint32_t au32[4];
2092	/** 64-bit view. */
2093	uint64_t au64[2];
2094	/** 128-bit view. (yeah, very helpful) */
2095	uint128_t au128[1];
2096	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
2097	/* - offset 416 - */
2098	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
2099	} X86FXSTATE;
2100	#pragma pack()
2101	/** Pointer to a FPU Extended state. */
2102	typedef X86FXSTATE *PX86FXSTATE;
2103	/** Pointer to a const FPU Extended state. */
2104	typedef const X86FXSTATE *PCX86FXSTATE;
2105
2106	/** @name FPU status word flags.
2107	* @{ */
2108	/** Exception Flag: Invalid operation. */
2109	#define X86_FSW_IE RT_BIT(0)
2110	/** Exception Flag: Denormalized operand. */
2111	#define X86_FSW_DE RT_BIT(1)
2112	/** Exception Flag: Zero divide. */
2113	#define X86_FSW_ZE RT_BIT(2)
2114	/** Exception Flag: Overflow. */
2115	#define X86_FSW_OE RT_BIT(3)
2116	/** Exception Flag: Underflow. */
2117	#define X86_FSW_UE RT_BIT(4)
2118	/** Exception Flag: Precision. */
2119	#define X86_FSW_PE RT_BIT(5)
2120	/** Stack fault. */
2121	#define X86_FSW_SF RT_BIT(6)
2122	/** Error summary status. */
2123	#define X86_FSW_ES RT_BIT(7)
2124	/** Mask of exceptions flags, excluding the summary bit. */
2125	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2126	/** Mask of exceptions flags, including the summary bit. */
2127	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2128	/** Condition code 0. */
2129	#define X86_FSW_C0 RT_BIT(8)
2130	/** Condition code 1. */
2131	#define X86_FSW_C1 RT_BIT(9)
2132	/** Condition code 2. */
2133	#define X86_FSW_C2 RT_BIT(10)
2134	/** Top of the stack mask. */
2135	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2136	/** TOP shift value. */
2137	#define X86_FSW_TOP_SHIFT 11
2138	/** Mask for getting TOP value after shifting it right. */
2139	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2140	/** Get the TOP value. */
2141	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2142	/** Condition code 3. */
2143	#define X86_FSW_C3 RT_BIT(14)
2144	/** Mask of exceptions flags, including the summary bit. */
2145	#define X86_FSW_C_MASK UINT16_C(0x4700)
2146	/** FPU busy. */
2147	#define X86_FSW_B RT_BIT(15)
2148	/** @} */
2149
2150
2151	/** @name FPU control word flags.
2152	* @{ */
2153	/** Exception Mask: Invalid operation. */
2154	#define X86_FCW_IM RT_BIT(0)
2155	/** Exception Mask: Denormalized operand. */
2156	#define X86_FCW_DM RT_BIT(1)
2157	/** Exception Mask: Zero divide. */
2158	#define X86_FCW_ZM RT_BIT(2)
2159	/** Exception Mask: Overflow. */
2160	#define X86_FCW_OM RT_BIT(3)
2161	/** Exception Mask: Underflow. */
2162	#define X86_FCW_UM RT_BIT(4)
2163	/** Exception Mask: Precision. */
2164	#define X86_FCW_PM RT_BIT(5)
2165	/** Mask all exceptions, the value typically loaded (by for instance fninit).
2166	* @remarks This includes reserved bit 6. */
2167	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2168	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2169	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2170	/** Precision control mask. */
2171	#define X86_FCW_PC_MASK UINT16_C(0x0300)
2172	/** Precision control: 24-bit. */
2173	#define X86_FCW_PC_24 UINT16_C(0x0000)
2174	/** Precision control: Reserved. */
2175	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2176	/** Precision control: 53-bit. */
2177	#define X86_FCW_PC_53 UINT16_C(0x0200)
2178	/** Precision control: 64-bit. */
2179	#define X86_FCW_PC_64 UINT16_C(0x0300)
2180	/** Rounding control mask. */
2181	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
2182	/** Rounding control: To nearest. */
2183	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
2184	/** Rounding control: Down. */
2185	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
2186	/** Rounding control: Up. */
2187	#define X86_FCW_RC_UP UINT16_C(0x0800)
2188	/** Rounding control: Towards zero. */
2189	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
2190	/** Bits which should be zero, apparently. */
2191	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
2192	/** @} */
2193
2194
2195	/** @name Selector Descriptor
2196	* @{
2197	*/
2198
2199	/**
2200	* Descriptor attributes.
2201	*/
2202	typedef struct X86DESCATTRBITS
2203	{
2204	/** 00 - Segment Type. */
2205	unsigned u4Type : 4;
2206	/** 04 - Descriptor Type. System(=0) or code/data selector */
2207	unsigned u1DescType : 1;
2208	/** 05 - Descriptor Privelege level. */
2209	unsigned u2Dpl : 2;
2210	/** 07 - Flags selector present(=1) or not. */
2211	unsigned u1Present : 1;
2212	/** 08 - Segment limit 16-19. */
2213	unsigned u4LimitHigh : 4;
2214	/** 0c - Available for system software. */
2215	unsigned u1Available : 1;
2216	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2217	unsigned u1Long : 1;
2218	/** 0e - This flags meaning depends on the segment type. Try make sense out
2219	* of the intel manual yourself. */
2220	unsigned u1DefBig : 1;
2221	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2222	* clear byte. */
2223	unsigned u1Granularity : 1;
2224	} X86DESCATTRBITS;
2225
2226
2227	#pragma pack(1)
2228	typedef union X86DESCATTR
2229	{
2230	/** Unsigned integer view. */
2231	uint32_t u;
2232	/** Normal view. */
2233	X86DESCATTRBITS n;
2234	} X86DESCATTR;
2235	#pragma pack()
2236	/** Pointer to descriptor attributes. */
2237	typedef X86DESCATTR *PX86DESCATTR;
2238	/** Pointer to const descriptor attributes. */
2239	typedef const X86DESCATTR *PCX86DESCATTR;
2240
2241
2242	/**
2243	* Generic descriptor table entry
2244	*/
2245	#pragma pack(1)
2246	typedef struct X86DESCGENERIC
2247	{
2248	/** Limit - Low word. */
2249	unsigned u16LimitLow : 16;
2250	/** Base address - lowe word.
2251	* Don't try set this to 24 because MSC is doing stupid things then. */
2252	unsigned u16BaseLow : 16;
2253	/** Base address - first 8 bits of high word. */
2254	unsigned u8BaseHigh1 : 8;
2255	/** Segment Type. */
2256	unsigned u4Type : 4;
2257	/** Descriptor Type. System(=0) or code/data selector */
2258	unsigned u1DescType : 1;
2259	/** Descriptor Privelege level. */
2260	unsigned u2Dpl : 2;
2261	/** Flags selector present(=1) or not. */
2262	unsigned u1Present : 1;
2263	/** Segment limit 16-19. */
2264	unsigned u4LimitHigh : 4;
2265	/** Available for system software. */
2266	unsigned u1Available : 1;
2267	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2268	unsigned u1Long : 1;
2269	/** This flags meaning depends on the segment type. Try make sense out
2270	* of the intel manual yourself. */
2271	unsigned u1DefBig : 1;
2272	/** Granularity of the limit. If set 4KB granularity is used, if
2273	* clear byte. */
2274	unsigned u1Granularity : 1;
2275	/** Base address - highest 8 bits. */
2276	unsigned u8BaseHigh2 : 8;
2277	} X86DESCGENERIC;
2278	#pragma pack()
2279	/** Pointer to a generic descriptor entry. */
2280	typedef X86DESCGENERIC *PX86DESCGENERIC;
2281	/** Pointer to a const generic descriptor entry. */
2282	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2283
2284	/**
2285	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2286	*/
2287	typedef struct X86DESCGATE
2288	{
2289	/** 00 - Target code segment offset - Low word.
2290	* Ignored if task-gate. */
2291	unsigned u16OffsetLow : 16;
2292	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
2293	* TSS selector if task-gate. */
2294	unsigned u16Sel : 16;
2295	/** 20 - Number of parameters for a call-gate.
2296	* Ignored if interrupt-, trap- or task-gate. */
2297	unsigned u4ParmCount : 4;
2298	/** 24 - Reserved / ignored. */
2299	unsigned u4Reserved : 4;
2300	/** 28 - Segment Type. */
2301	unsigned u4Type : 4;
2302	/** 2c - Descriptor Type (0 = system). */
2303	unsigned u1DescType : 1;
2304	/** 2d - Descriptor Privelege level. */
2305	unsigned u2Dpl : 2;
2306	/** 2f - Flags selector present(=1) or not. */
2307	unsigned u1Present : 1;
2308	/** 30 - Target code segment offset - High word.
2309	* Ignored if task-gate. */
2310	unsigned u16OffsetHigh : 16;
2311	} X86DESCGATE;
2312	AssertCompileSize(X86DESCGATE, 8);
2313	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2314	typedef X86DESCGATE *PX86DESCGATE;
2315	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2316	typedef const X86DESCGATE *PCX86DESCGATE;
2317
2318	/**
2319	* Descriptor table entry.
2320	*/
2321	#pragma pack(1)
2322	typedef union X86DESC
2323	{
2324	/** Generic descriptor view. */
2325	X86DESCGENERIC Gen;
2326	/** Gate descriptor view. */
2327	X86DESCGATE Gate;
2328
2329	/** 8 bit unsigned integer view. */
2330	uint8_t au8[8];
2331	/** 16 bit unsigned integer view. */
2332	uint16_t au16[4];
2333	/** 32 bit unsigned integer view. */
2334	uint32_t au32[2];
2335	/** 64 bit unsigned integer view. */
2336	uint64_t au64[1];
2337	/** Unsigned integer view. */
2338	uint64_t u;
2339	} X86DESC;
2340	AssertCompileSize(X86DESC, 8);
2341	#pragma pack()
2342	/** Pointer to descriptor table entry. */
2343	typedef X86DESC *PX86DESC;
2344	/** Pointer to const descriptor table entry. */
2345	typedef const X86DESC *PCX86DESC;
2346
2347	/** @def X86DESC_BASE
2348	* Return the base address of a descriptor.
2349	*/
2350	#define X86DESC_BASE(desc) /ASM-NOINC/ \
2351	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2352	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2353	\| ( (desc).Gen.u16BaseLow ) )
2354
2355	/** @def X86DESC_LIMIT
2356	* Return the limit of a descriptor.
2357	*/
2358	#define X86DESC_LIMIT(desc) /ASM-NOINC/ \
2359	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
2360	\| ( (desc).Gen.u16LimitLow ) )
2361
2362	/** @def X86DESC_GET_HID_ATTR
2363	* Get the descriptor attributes for the hidden register.
2364	*/
2365	#define X86DESC_GET_HID_ATTR(desc) /ASM-NOINC/ \
2366	( (desc.u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
2367
2368
2369	/**
2370	* 64 bits generic descriptor table entry
2371	* Note: most of these bits have no meaning in long mode.
2372	*/
2373	#pragma pack(1)
2374	typedef struct X86DESC64GENERIC
2375	{
2376	/** Limit - Low word - IGNORED. */
2377	unsigned u16LimitLow : 16;
2378	/** Base address - low word. - IGNORED
2379	* Don't try set this to 24 because MSC is doing stupid things then. */
2380	unsigned u16BaseLow : 16;
2381	/** Base address - first 8 bits of high word. - IGNORED */
2382	unsigned u8BaseHigh1 : 8;
2383	/** Segment Type. */
2384	unsigned u4Type : 4;
2385	/** Descriptor Type. System(=0) or code/data selector */
2386	unsigned u1DescType : 1;
2387	/** Descriptor Privelege level. */
2388	unsigned u2Dpl : 2;
2389	/** Flags selector present(=1) or not. */
2390	unsigned u1Present : 1;
2391	/** Segment limit 16-19. - IGNORED */
2392	unsigned u4LimitHigh : 4;
2393	/** Available for system software. - IGNORED */
2394	unsigned u1Available : 1;
2395	/** Long mode flag. */
2396	unsigned u1Long : 1;
2397	/** This flags meaning depends on the segment type. Try make sense out
2398	* of the intel manual yourself. */
2399	unsigned u1DefBig : 1;
2400	/** Granularity of the limit. If set 4KB granularity is used, if
2401	* clear byte. - IGNORED */
2402	unsigned u1Granularity : 1;
2403	/** Base address - highest 8 bits. - IGNORED */
2404	unsigned u8BaseHigh2 : 8;
2405	/** Base address - bits 63-32. */
2406	unsigned u32BaseHigh3 : 32;
2407	unsigned u8Reserved : 8;
2408	unsigned u5Zeros : 5;
2409	unsigned u19Reserved : 19;
2410	} X86DESC64GENERIC;
2411	#pragma pack()
2412	/** Pointer to a generic descriptor entry. */
2413	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2414	/** Pointer to a const generic descriptor entry. */
2415	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2416
2417	/**
2418	* System descriptor table entry (64 bits)
2419	*
2420	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2421	*/
2422	#pragma pack(1)
2423	typedef struct X86DESC64SYSTEM
2424	{
2425	/** Limit - Low word. */
2426	unsigned u16LimitLow : 16;
2427	/** Base address - lowe word.
2428	* Don't try set this to 24 because MSC is doing stupid things then. */
2429	unsigned u16BaseLow : 16;
2430	/** Base address - first 8 bits of high word. */
2431	unsigned u8BaseHigh1 : 8;
2432	/** Segment Type. */
2433	unsigned u4Type : 4;
2434	/** Descriptor Type. System(=0) or code/data selector */
2435	unsigned u1DescType : 1;
2436	/** Descriptor Privelege level. */
2437	unsigned u2Dpl : 2;
2438	/** Flags selector present(=1) or not. */
2439	unsigned u1Present : 1;
2440	/** Segment limit 16-19. */
2441	unsigned u4LimitHigh : 4;
2442	/** Available for system software. */
2443	unsigned u1Available : 1;
2444	/** Reserved - 0. */
2445	unsigned u1Reserved : 1;
2446	/** This flags meaning depends on the segment type. Try make sense out
2447	* of the intel manual yourself. */
2448	unsigned u1DefBig : 1;
2449	/** Granularity of the limit. If set 4KB granularity is used, if
2450	* clear byte. */
2451	unsigned u1Granularity : 1;
2452	/** Base address - bits 31-24. */
2453	unsigned u8BaseHigh2 : 8;
2454	/** Base address - bits 63-32. */
2455	unsigned u32BaseHigh3 : 32;
2456	unsigned u8Reserved : 8;
2457	unsigned u5Zeros : 5;
2458	unsigned u19Reserved : 19;
2459	} X86DESC64SYSTEM;
2460	#pragma pack()
2461	/** Pointer to a system descriptor entry. */
2462	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2463	/** Pointer to a const system descriptor entry. */
2464	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2465
2466	/**
2467	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2468	*/
2469	typedef struct X86DESC64GATE
2470	{
2471	/** Target code segment offset - Low word. */
2472	unsigned u16OffsetLow : 16;
2473	/** Target code segment selector. */
2474	unsigned u16Sel : 16;
2475	/** Interrupt stack table for interrupt- and trap-gates.
2476	* Ignored by call-gates. */
2477	unsigned u3IST : 3;
2478	/** Reserved / ignored. */
2479	unsigned u5Reserved : 5;
2480	/** Segment Type. */
2481	unsigned u4Type : 4;
2482	/** Descriptor Type (0 = system). */
2483	unsigned u1DescType : 1;
2484	/** Descriptor Privelege level. */
2485	unsigned u2Dpl : 2;
2486	/** Flags selector present(=1) or not. */
2487	unsigned u1Present : 1;
2488	/** Target code segment offset - High word.
2489	* Ignored if task-gate. */
2490	unsigned u16OffsetHigh : 16;
2491	/** Target code segment offset - Top dword.
2492	* Ignored if task-gate. */
2493	unsigned u32OffsetTop : 32;
2494	/** Reserved / ignored / must be zero.
2495	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2496	unsigned u32Reserved : 32;
2497	} X86DESC64GATE;
2498	AssertCompileSize(X86DESC64GATE, 16);
2499	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2500	typedef X86DESC64GATE *PX86DESC64GATE;
2501	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2502	typedef const X86DESC64GATE *PCX86DESC64GATE;
2503
2504
2505	/**
2506	* Descriptor table entry.
2507	*/
2508	#pragma pack(1)
2509	typedef union X86DESC64
2510	{
2511	/** Generic descriptor view. */
2512	X86DESC64GENERIC Gen;
2513	/** System descriptor view. */
2514	X86DESC64SYSTEM System;
2515	/** Gate descriptor view. */
2516	X86DESC64GATE Gate;
2517
2518	/** 8 bit unsigned integer view. */
2519	uint8_t au8[16];
2520	/** 16 bit unsigned integer view. */
2521	uint16_t au16[8];
2522	/** 32 bit unsigned integer view. */
2523	uint32_t au32[4];
2524	/** 64 bit unsigned integer view. */
2525	uint64_t au64[2];
2526	} X86DESC64;
2527	AssertCompileSize(X86DESC64, 16);
2528	#pragma pack()
2529	/** Pointer to descriptor table entry. */
2530	typedef X86DESC64 *PX86DESC64;
2531	/** Pointer to const descriptor table entry. */
2532	typedef const X86DESC64 *PCX86DESC64;
2533
2534	/** @def X86DESC64_BASE
2535	* Return the base of a 64-bit descriptor.
2536	*/
2537	#define X86DESC64_BASE(desc) /ASM-NOINC/ \
2538	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2539	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2540	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2541	\| ( (desc).Gen.u16BaseLow ) )
2542
2543
2544
2545	/** @name Host system descriptor table entry - Use with care!
2546	* @{ */
2547	/** Host system descriptor table entry. */
2548	#if HC_ARCH_BITS == 64
2549	typedef X86DESC64 X86DESCHC;
2550	#else
2551	typedef X86DESC X86DESCHC;
2552	#endif
2553	/** Pointer to a host system descriptor table entry. */
2554	#if HC_ARCH_BITS == 64
2555	typedef PX86DESC64 PX86DESCHC;
2556	#else
2557	typedef PX86DESC PX86DESCHC;
2558	#endif
2559	/** Pointer to a const host system descriptor table entry. */
2560	#if HC_ARCH_BITS == 64
2561	typedef PCX86DESC64 PCX86DESCHC;
2562	#else
2563	typedef PCX86DESC PCX86DESCHC;
2564	#endif
2565	/** @} */
2566
2567
2568	/** @name Selector Descriptor Types.
2569	* @{
2570	*/
2571
2572	/** @name Non-System Selector Types.
2573	* @{ */
2574	/** Code(=set)/Data(=clear) bit. */
2575	#define X86_SEL_TYPE_CODE 8
2576	/** Memory(=set)/System(=clear) bit. */
2577	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2578	/** Accessed bit. */
2579	#define X86_SEL_TYPE_ACCESSED 1
2580	/** Expand down bit (for data selectors only). */
2581	#define X86_SEL_TYPE_DOWN 4
2582	/** Conforming bit (for code selectors only). */
2583	#define X86_SEL_TYPE_CONF 4
2584	/** Write bit (for data selectors only). */
2585	#define X86_SEL_TYPE_WRITE 2
2586	/** Read bit (for code selectors only). */
2587	#define X86_SEL_TYPE_READ 2
2588
2589	/** Read only selector type. */
2590	#define X86_SEL_TYPE_RO 0
2591	/** Accessed read only selector type. */
2592	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2593	/** Read write selector type. */
2594	#define X86_SEL_TYPE_RW 2
2595	/** Accessed read write selector type. */
2596	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2597	/** Expand down read only selector type. */
2598	#define X86_SEL_TYPE_RO_DOWN 4
2599	/** Accessed expand down read only selector type. */
2600	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2601	/** Expand down read write selector type. */
2602	#define X86_SEL_TYPE_RW_DOWN 6
2603	/** Accessed expand down read write selector type. */
2604	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2605	/** Execute only selector type. */
2606	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2607	/** Accessed execute only selector type. */
2608	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2609	/** Execute and read selector type. */
2610	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2611	/** Accessed execute and read selector type. */
2612	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2613	/** Conforming execute only selector type. */
2614	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2615	/** Accessed Conforming execute only selector type. */
2616	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2617	/** Conforming execute and write selector type. */
2618	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2619	/** Accessed Conforming execute and write selector type. */
2620	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2621	/** @} */
2622
2623
2624	/** @name System Selector Types.
2625	* @{ */
2626	/** The TSS busy bit mask. */
2627	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
2628
2629	/** Undefined system selector type. */
2630	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2631	/** 286 TSS selector. */
2632	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2633	/** LDT selector. */
2634	#define X86_SEL_TYPE_SYS_LDT 2
2635	/** 286 TSS selector - Busy. */
2636	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2637	/** 286 Callgate selector. */
2638	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2639	/** Taskgate selector. */
2640	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2641	/** 286 Interrupt gate selector. */
2642	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2643	/** 286 Trapgate selector. */
2644	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2645	/** Undefined system selector. */
2646	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2647	/** 386 TSS selector. */
2648	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2649	/** Undefined system selector. */
2650	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2651	/** 386 TSS selector - Busy. */
2652	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2653	/** 386 Callgate selector. */
2654	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2655	/** Undefined system selector. */
2656	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2657	/** 386 Interruptgate selector. */
2658	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2659	/** 386 Trapgate selector. */
2660	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2661	/** @} */
2662
2663	/** @name AMD64 System Selector Types.
2664	* @{ */
2665	/** LDT selector. */
2666	#define AMD64_SEL_TYPE_SYS_LDT 2
2667	/** TSS selector - Busy. */
2668	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2669	/** TSS selector - Busy. */
2670	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2671	/** Callgate selector. */
2672	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2673	/** Interruptgate selector. */
2674	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2675	/** Trapgate selector. */
2676	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2677	/** @} */
2678
2679	/** @} */
2680
2681
2682	/** @name Descriptor Table Entry Flag Masks.
2683	* These are for the 2nd 32-bit word of a descriptor.
2684	* @{ */
2685	/** Bits 8-11 - TYPE - Descriptor type mask. */
2686	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2687	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2688	#define X86_DESC_S RT_BIT(12)
2689	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2690	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2691	/** Bit 15 - P - Present. */
2692	#define X86_DESC_P RT_BIT(15)
2693	/** Bit 20 - AVL - Available for system software. */
2694	#define X86_DESC_AVL RT_BIT(20)
2695	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2696	#define X86_DESC_DB RT_BIT(22)
2697	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2698	* used, if clear byte. */
2699	#define X86_DESC_G RT_BIT(23)
2700	/** @} */
2701
2702	/** @} */
2703
2704
2705	/** @name Task Segments.
2706	* @{
2707	*/
2708
2709	/**
2710	* 16-bit Task Segment (TSS).
2711	*/
2712	#pragma pack(1)
2713	typedef struct X86TSS16
2714	{
2715	/** Back link to previous task. (static) */
2716	RTSEL selPrev;
2717	/** Ring-0 stack pointer. (static) */
2718	uint16_t sp0;
2719	/** Ring-0 stack segment. (static) */
2720	RTSEL ss0;
2721	/** Ring-1 stack pointer. (static) */
2722	uint16_t sp1;
2723	/** Ring-1 stack segment. (static) */
2724	RTSEL ss1;
2725	/** Ring-2 stack pointer. (static) */
2726	uint16_t sp2;
2727	/** Ring-2 stack segment. (static) */
2728	RTSEL ss2;
2729	/** IP before task switch. */
2730	uint16_t ip;
2731	/** FLAGS before task switch. */
2732	uint16_t flags;
2733	/** AX before task switch. */
2734	uint16_t ax;
2735	/** CX before task switch. */
2736	uint16_t cx;
2737	/** DX before task switch. */
2738	uint16_t dx;
2739	/** BX before task switch. */
2740	uint16_t bx;
2741	/** SP before task switch. */
2742	uint16_t sp;
2743	/** BP before task switch. */
2744	uint16_t bp;
2745	/** SI before task switch. */
2746	uint16_t si;
2747	/** DI before task switch. */
2748	uint16_t di;
2749	/** ES before task switch. */
2750	RTSEL es;
2751	/** CS before task switch. */
2752	RTSEL cs;
2753	/** SS before task switch. */
2754	RTSEL ss;
2755	/** DS before task switch. */
2756	RTSEL ds;
2757	/** LDTR before task switch. */
2758	RTSEL selLdt;
2759	} X86TSS16;
2760	AssertCompileSize(X86TSS16, 44);
2761	#pragma pack()
2762	/** Pointer to a 16-bit task segment. */
2763	typedef X86TSS16 *PX86TSS16;
2764	/** Pointer to a const 16-bit task segment. */
2765	typedef const X86TSS16 *PCX86TSS16;
2766
2767
2768	/**
2769	* 32-bit Task Segment (TSS).
2770	*/
2771	#pragma pack(1)
2772	typedef struct X86TSS32
2773	{
2774	/** Back link to previous task. (static) */
2775	RTSEL selPrev;
2776	uint16_t padding1;
2777	/** Ring-0 stack pointer. (static) */
2778	uint32_t esp0;
2779	/** Ring-0 stack segment. (static) */
2780	RTSEL ss0;
2781	uint16_t padding_ss0;
2782	/** Ring-1 stack pointer. (static) */
2783	uint32_t esp1;
2784	/** Ring-1 stack segment. (static) */
2785	RTSEL ss1;
2786	uint16_t padding_ss1;
2787	/** Ring-2 stack pointer. (static) */
2788	uint32_t esp2;
2789	/** Ring-2 stack segment. (static) */
2790	RTSEL ss2;
2791	uint16_t padding_ss2;
2792	/** Page directory for the task. (static) */
2793	uint32_t cr3;
2794	/** EIP before task switch. */
2795	uint32_t eip;
2796	/** EFLAGS before task switch. */
2797	uint32_t eflags;
2798	/** EAX before task switch. */
2799	uint32_t eax;
2800	/** ECX before task switch. */
2801	uint32_t ecx;
2802	/** EDX before task switch. */
2803	uint32_t edx;
2804	/** EBX before task switch. */
2805	uint32_t ebx;
2806	/** ESP before task switch. */
2807	uint32_t esp;
2808	/** EBP before task switch. */
2809	uint32_t ebp;
2810	/** ESI before task switch. */
2811	uint32_t esi;
2812	/** EDI before task switch. */
2813	uint32_t edi;
2814	/** ES before task switch. */
2815	RTSEL es;
2816	uint16_t padding_es;
2817	/** CS before task switch. */
2818	RTSEL cs;
2819	uint16_t padding_cs;
2820	/** SS before task switch. */
2821	RTSEL ss;
2822	uint16_t padding_ss;
2823	/** DS before task switch. */
2824	RTSEL ds;
2825	uint16_t padding_ds;
2826	/** FS before task switch. */
2827	RTSEL fs;
2828	uint16_t padding_fs;
2829	/** GS before task switch. */
2830	RTSEL gs;
2831	uint16_t padding_gs;
2832	/** LDTR before task switch. */
2833	RTSEL selLdt;
2834	uint16_t padding_ldt;
2835	/** Debug trap flag */
2836	uint16_t fDebugTrap;
2837	/** Offset relative to the TSS of the start of the I/O Bitmap
2838	* and the end of the interrupt redirection bitmap. */
2839	uint16_t offIoBitmap;
2840	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2841	uint8_t IntRedirBitmap[32];
2842	} X86TSS32;
2843	#pragma pack()
2844	/** Pointer to task segment. */
2845	typedef X86TSS32 *PX86TSS32;
2846	/** Pointer to const task segment. */
2847	typedef const X86TSS32 *PCX86TSS32;
2848
2849
2850	/**
2851	* 64-bit Task segment.
2852	*/
2853	#pragma pack(1)
2854	typedef struct X86TSS64
2855	{
2856	/** Reserved. */
2857	uint32_t u32Reserved;
2858	/** Ring-0 stack pointer. (static) */
2859	uint64_t rsp0;
2860	/** Ring-1 stack pointer. (static) */
2861	uint64_t rsp1;
2862	/** Ring-2 stack pointer. (static) */
2863	uint64_t rsp2;
2864	/** Reserved. */
2865	uint32_t u32Reserved2[2];
2866	/* IST */
2867	uint64_t ist1;
2868	uint64_t ist2;
2869	uint64_t ist3;
2870	uint64_t ist4;
2871	uint64_t ist5;
2872	uint64_t ist6;
2873	uint64_t ist7;
2874	/* Reserved. */
2875	uint16_t u16Reserved[5];
2876	/** Offset relative to the TSS of the start of the I/O Bitmap
2877	* and the end of the interrupt redirection bitmap. */
2878	uint16_t offIoBitmap;
2879	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2880	uint8_t IntRedirBitmap[32];
2881	} X86TSS64;
2882	#pragma pack()
2883	/** Pointer to a 64-bit task segment. */
2884	typedef X86TSS64 *PX86TSS64;
2885	/** Pointer to a const 64-bit task segment. */
2886	typedef const X86TSS64 *PCX86TSS64;
2887	AssertCompileSize(X86TSS64, 136);
2888
2889	/** @} */
2890
2891
2892	/** @name Selectors.
2893	* @{
2894	*/
2895
2896	/**
2897	* The shift used to convert a selector from and to index an index (C).
2898	*/
2899	#define X86_SEL_SHIFT 3
2900
2901	/**
2902	* The mask used to mask off the table indicator and CPL of an selector.
2903	*/
2904	#define X86_SEL_MASK 0xfff8U
2905
2906	/**
2907	* The bit indicating that a selector is in the LDT and not in the GDT.
2908	*/
2909	#define X86_SEL_LDT 0x0004U
2910	/**
2911	* The bit mask for getting the RPL of a selector.
2912	*/
2913	#define X86_SEL_RPL 0x0003U
2914
2915	/** @} */
2916
2917
2918	/**
2919	* x86 Exceptions/Faults/Traps.
2920	*/
2921	typedef enum X86XCPT
2922	{
2923	/** \#DE - Divide error. */
2924	X86_XCPT_DE = 0x00,
2925	/** \#DB - Debug event (single step, DRx, ..) */
2926	X86_XCPT_DB = 0x01,
2927	/** NMI - Non-Maskable Interrupt */
2928	X86_XCPT_NMI = 0x02,
2929	/** \#BP - Breakpoint (INT3). */
2930	X86_XCPT_BP = 0x03,
2931	/** \#OF - Overflow (INTO). */
2932	X86_XCPT_OF = 0x04,
2933	/** \#BR - Bound range exceeded (BOUND). */
2934	X86_XCPT_BR = 0x05,
2935	/** \#UD - Undefined opcode. */
2936	X86_XCPT_UD = 0x06,
2937	/** \#NM - Device not available (math coprocessor device). */
2938	X86_XCPT_NM = 0x07,
2939	/** \#DF - Double fault. */
2940	X86_XCPT_DF = 0x08,
2941	/** ??? - Coprocessor segment overrun (obsolete). */
2942	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2943	/** \#TS - Taskswitch (TSS). */
2944	X86_XCPT_TS = 0x0a,
2945	/** \#NP - Segment no present. */
2946	X86_XCPT_NP = 0x0b,
2947	/** \#SS - Stack segment fault. */
2948	X86_XCPT_SS = 0x0c,
2949	/** \#GP - General protection fault. */
2950	X86_XCPT_GP = 0x0d,
2951	/** \#PF - Page fault. */
2952	X86_XCPT_PF = 0x0e,
2953	/* 0x0f is reserved. */
2954	/** \#MF - Math fault (FPU). */
2955	X86_XCPT_MF = 0x10,
2956	/** \#AC - Alignment check. */
2957	X86_XCPT_AC = 0x11,
2958	/** \#MC - Machine check. */
2959	X86_XCPT_MC = 0x12,
2960	/** \#XF - SIMD Floating-Pointer Exception. */
2961	X86_XCPT_XF = 0x13
2962	} X86XCPT;
2963	/** Pointer to a x86 exception code. */
2964	typedef X86XCPT *PX86XCPT;
2965	/** Pointer to a const x86 exception code. */
2966	typedef const X86XCPT *PCX86XCPT;
2967
2968
2969	/** @name Trap Error Codes
2970	* @{
2971	*/
2972	/** External indicator. */
2973	#define X86_TRAP_ERR_EXTERNAL 1
2974	/** IDT indicator. */
2975	#define X86_TRAP_ERR_IDT 2
2976	/** Descriptor table indicator - If set LDT, if clear GDT. */
2977	#define X86_TRAP_ERR_TI 4
2978	/** Mask for getting the selector. */
2979	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2980	/** Shift for getting the selector table index (C type index). */
2981	#define X86_TRAP_ERR_SEL_SHIFT 3
2982	/** @} */
2983
2984
2985	/** @name \#PF Trap Error Codes
2986	* @{
2987	*/
2988	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2989	#define X86_TRAP_PF_P RT_BIT(0)
2990	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2991	#define X86_TRAP_PF_RW RT_BIT(1)
2992	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2993	#define X86_TRAP_PF_US RT_BIT(2)
2994	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2995	#define X86_TRAP_PF_RSVD RT_BIT(3)
2996	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2997	#define X86_TRAP_PF_ID RT_BIT(4)
2998	/** @} */
2999
3000	#pragma pack(1)
3001	/**
3002	* 32-bit IDTR/GDTR.
3003	*/
3004	typedef struct X86XDTR32
3005	{
3006	/** Size of the descriptor table. */
3007	uint16_t cb;
3008	/** Address of the descriptor table. */
3009	uint32_t uAddr;
3010	} X86XDTR32, *PX86XDTR32;
3011	#pragma pack()
3012
3013	#pragma pack(1)
3014	/**
3015	* 64-bit IDTR/GDTR.
3016	*/
3017	typedef struct X86XDTR64
3018	{
3019	/** Size of the descriptor table. */
3020	uint16_t cb;
3021	/** Address of the descriptor table. */
3022	uint64_t uAddr;
3023	} X86XDTR64, *PX86XDTR64;
3024	#pragma pack()
3025
3026
3027	/** @name ModR/M
3028	* @{ */
3029	#define X86_MODRM_RM_MASK UINT8_C(0x07)
3030	#define X86_MODRM_REG_MASK UINT8_C(0x38)
3031	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
3032	#define X86_MODRM_REG_SHIFT 3
3033	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
3034	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
3035	#define X86_MODRM_MOD_SHIFT 6
3036	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
3037	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
3038	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
3039	/** @} */
3040
3041	/** @name SIB
3042	* @{ */
3043	#define X86_SIB_BASE_MASK UINT8_C(0x07)
3044	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
3045	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
3046	#define X86_SIB_INDEX_SHIFT 3
3047	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
3048	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
3049	#define X86_SIB_SCALE_SHIFT 6
3050	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
3051	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
3052	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
3053	/** @} */
3054
3055	/** @name General register indexes
3056	* @{ */
3057	#define X86_GREG_xAX 0
3058	#define X86_GREG_xCX 1
3059	#define X86_GREG_xDX 2
3060	#define X86_GREG_xBX 3
3061	#define X86_GREG_xSP 4
3062	#define X86_GREG_xBP 5
3063	#define X86_GREG_xSI 6
3064	#define X86_GREG_xDI 7
3065	#define X86_GREG_x8 8
3066	#define X86_GREG_x9 9
3067	#define X86_GREG_x10 10
3068	#define X86_GREG_x11 11
3069	#define X86_GREG_x12 12
3070	#define X86_GREG_x13 13
3071	#define X86_GREG_x14 14
3072	#define X86_GREG_x15 15
3073	/** @} */
3074
3075	/** @name X86_SREG_XXX - Segment register indexes.
3076	* @{ */
3077	#define X86_SREG_ES 0
3078	#define X86_SREG_CS 1
3079	#define X86_SREG_SS 2
3080	#define X86_SREG_DS 3
3081	#define X86_SREG_FS 4
3082	#define X86_SREG_GS 5
3083	/** @} */
3084
3085
3086	/** @} */
3087
3088	#endif
3089

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source: vbox/trunk/include/iprt/x86.h@ 40282

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