x86.h@ 105688

Last change on this file since 105688 was 105459, checked in by vboxsync, 4 months ago
VMM/IEM: Need to clear PE if either OE/UE is set and not masked by the guest's MXCSR, bugref:10652 [typo]
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 205.3 KB

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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
9	*
10	* This file is part of VirtualBox base platform packages, as
11	* available from https://www.virtualbox.org.
12	*
13	* This program is free software; you can redistribute it and/or
14	* modify it under the terms of the GNU General Public License
15	* as published by the Free Software Foundation, in version 3 of the
16	* License.
17	*
18	* This program is distributed in the hope that it will be useful, but
19	* WITHOUT ANY WARRANTY; without even the implied warranty of
20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21	* General Public License for more details.
22	*
23	* You should have received a copy of the GNU General Public License
24	* along with this program; if not, see <https://www.gnu.org/licenses>.
25	*
26	* The contents of this file may alternatively be used under the terms
27	* of the Common Development and Distribution License Version 1.0
28	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
29	* in the VirtualBox distribution, in which case the provisions of the
30	* CDDL are applicable instead of those of the GPL.
31	*
32	* You may elect to license modified versions of this file under the
33	* terms and conditions of either the GPL or the CDDL or both.
34	*
35	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
36	*/
37
38	#ifndef IPRT_INCLUDED_x86_h
39	#define IPRT_INCLUDED_x86_h
40	#ifndef RT_WITHOUT_PRAGMA_ONCE
41	# pragma once
42	#endif
43
44	#ifndef VBOX_FOR_DTRACE_LIB
45	# ifndef __ASSEMBLER__
46	# include <iprt/types.h>
47	# include <iprt/assert.h>
48	# else
49	# include <iprt/stdint.h>
50	# include <iprt/assertcompile.h>
51	# endif
52	#else
53	# pragma D depends_on library vbox-types.d
54	#endif
55
56	/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
57	* defining MSR_IA32_FLUSH_CMD and MSR_AMD_VIRT_SPEC_CTL */
58	#ifdef RT_OS_SOLARIS
59	# undef CS
60	# undef DS
61	# undef MSR_IA32_FLUSH_CMD
62	# undef MSR_AMD_VIRT_SPEC_CTL
63	#endif
64
65	/** @defgroup grp_rt_x86 x86 Types and Definitions
66	* @ingroup grp_rt
67	* @{
68	*/
69
70	#ifndef __ASSEMBLER__
71
72	# ifndef VBOX_FOR_DTRACE_LIB
73	/**
74	* EFLAGS Bits.
75	*/
76	typedef struct X86EFLAGSBITS
77	{
78	/** Bit 0 - CF - Carry flag - Status flag. */
79	unsigned u1CF : 1;
80	/** Bit 1 - 1 - Reserved flag. */
81	unsigned u1Reserved0 : 1;
82	/** Bit 2 - PF - Parity flag - Status flag. */
83	unsigned u1PF : 1;
84	/** Bit 3 - 0 - Reserved flag. */
85	unsigned u1Reserved1 : 1;
86	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
87	unsigned u1AF : 1;
88	/** Bit 5 - 0 - Reserved flag. */
89	unsigned u1Reserved2 : 1;
90	/** Bit 6 - ZF - Zero flag - Status flag. */
91	unsigned u1ZF : 1;
92	/** Bit 7 - SF - Signed flag - Status flag. */
93	unsigned u1SF : 1;
94	/** Bit 8 - TF - Trap flag - System flag. */
95	unsigned u1TF : 1;
96	/** Bit 9 - IF - Interrupt flag - System flag. */
97	unsigned u1IF : 1;
98	/** Bit 10 - DF - Direction flag - Control flag. */
99	unsigned u1DF : 1;
100	/** Bit 11 - OF - Overflow flag - Status flag. */
101	unsigned u1OF : 1;
102	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
103	unsigned u2IOPL : 2;
104	/** Bit 14 - NT - Nested task flag - System flag. */
105	unsigned u1NT : 1;
106	/** Bit 15 - 0 - Reserved flag. */
107	unsigned u1Reserved3 : 1;
108	/** Bit 16 - RF - Resume flag - System flag. */
109	unsigned u1RF : 1;
110	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
111	unsigned u1VM : 1;
112	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
113	unsigned u1AC : 1;
114	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
115	unsigned u1VIF : 1;
116	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
117	unsigned u1VIP : 1;
118	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
119	unsigned u1ID : 1;
120	/** Bit 22-31 - 0 - Reserved flag. */
121	unsigned u10Reserved4 : 10;
122	} X86EFLAGSBITS;
123	/** Pointer to EFLAGS bits. */
124	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
125	/** Pointer to const EFLAGS bits. */
126	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
127	# endif /* !VBOX_FOR_DTRACE_LIB */
128
129	/**
130	* EFLAGS.
131	*/
132	typedef union X86EFLAGS
133	{
134	/** The plain unsigned view. */
135	uint32_t u;
136	# ifndef VBOX_FOR_DTRACE_LIB
137	/** The bitfield view. */
138	X86EFLAGSBITS Bits;
139	# endif
140	/** The 8-bit view. */
141	uint8_t au8[4];
142	/** The 16-bit view. */
143	uint16_t au16[2];
144	/** The 32-bit view. */
145	uint32_t au32[1];
146	/** The 32-bit view. */
147	uint32_t u32;
148	} X86EFLAGS;
149	/** Pointer to EFLAGS. */
150	typedef X86EFLAGS *PX86EFLAGS;
151	/** Pointer to const EFLAGS. */
152	typedef const X86EFLAGS *PCX86EFLAGS;
153
154	/**
155	* RFLAGS (32 upper bits are reserved).
156	*/
157	typedef union X86RFLAGS
158	{
159	/** The plain unsigned view. */
160	uint64_t u;
161	# ifndef VBOX_FOR_DTRACE_LIB
162	/** The bitfield view. */
163	X86EFLAGSBITS Bits;
164	# endif
165	/** The 8-bit view. */
166	uint8_t au8[8];
167	/** The 16-bit view. */
168	uint16_t au16[4];
169	/** The 32-bit view. */
170	uint32_t au32[2];
171	/** The 64-bit view. */
172	uint64_t au64[1];
173	/** The 64-bit view. */
174	uint64_t u64;
175	} X86RFLAGS;
176	/** Pointer to RFLAGS. */
177	typedef X86RFLAGS *PX86RFLAGS;
178	/** Pointer to const RFLAGS. */
179	typedef const X86RFLAGS *PCX86RFLAGS;
180
181	#endif /* !__ASSEMBLER__ */
182
183
184	/** @name EFLAGS
185	* @{
186	*/
187	/** Bit 0 - CF - Carry flag - Status flag. */
188	#define X86_EFL_CF RT_BIT_32(0)
189	#define X86_EFL_CF_BIT 0
190	/** Bit 1 - Reserved, reads as 1. */
191	#define X86_EFL_1 RT_BIT_32(1)
192	/** Bit 2 - PF - Parity flag - Status flag. */
193	#define X86_EFL_PF RT_BIT_32(2)
194	#define X86_EFL_PF_BIT 2
195	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
196	#define X86_EFL_AF RT_BIT_32(4)
197	#define X86_EFL_AF_BIT 4
198	/** Bit 6 - ZF - Zero flag - Status flag. */
199	#define X86_EFL_ZF RT_BIT_32(6)
200	#define X86_EFL_ZF_BIT 6
201	/** Bit 7 - SF - Signed flag - Status flag. */
202	#define X86_EFL_SF RT_BIT_32(7)
203	#define X86_EFL_SF_BIT 7
204	/** Bit 8 - TF - Trap flag - System flag. */
205	#define X86_EFL_TF RT_BIT_32(8)
206	#define X86_EFL_TF_BIT 8
207	/** Bit 9 - IF - Interrupt flag - System flag. */
208	#define X86_EFL_IF RT_BIT_32(9)
209	#define X86_EFL_IF_BIT 9
210	/** Bit 10 - DF - Direction flag - Control flag. */
211	#define X86_EFL_DF RT_BIT_32(10)
212	#define X86_EFL_DF_BIT 10
213	/** Bit 11 - OF - Overflow flag - Status flag. */
214	#define X86_EFL_OF RT_BIT_32(11)
215	#define X86_EFL_OF_BIT 11
216	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
217	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
218	/** Bit 14 - NT - Nested task flag - System flag. */
219	#define X86_EFL_NT RT_BIT_32(14)
220	#define X86_EFL_NT_BIT 14
221	/** Bit 16 - RF - Resume flag - System flag. */
222	#define X86_EFL_RF RT_BIT_32(16)
223	#define X86_EFL_RF_BIT 16
224	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
225	#define X86_EFL_VM RT_BIT_32(17)
226	#define X86_EFL_VM_BIT 17
227	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
228	#define X86_EFL_AC RT_BIT_32(18)
229	#define X86_EFL_AC_BIT 18
230	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
231	#define X86_EFL_VIF RT_BIT_32(19)
232	#define X86_EFL_VIF_BIT 19
233	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
234	#define X86_EFL_VIP RT_BIT_32(20)
235	#define X86_EFL_VIP_BIT 20
236	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
237	#define X86_EFL_ID RT_BIT_32(21)
238	#define X86_EFL_ID_BIT 21
239	/** All live bits. */
240	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
241	/** Read as 1 bits. */
242	#define X86_EFL_RA1_MASK RT_BIT_32(1)
243	/** Read as 0 bits, excluding bits 31:22.
244	* Bits 3, 5, 15, and 22 thru 31. */
245	#define X86_EFL_RAZ_MASK UINT32_C(0xffc08028)
246	/** Read as 0 bits, excluding bits 31:22.
247	* Bits 3, 5 and 15. */
248	#define X86_EFL_RAZ_LO_MASK UINT32_C(0x00008028)
249	/** IOPL shift. */
250	#define X86_EFL_IOPL_SHIFT 12
251	/** The IOPL level from the flags. */
252	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
253	/** Bits restored by popf */
254	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
255	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
256	/** Bits restored by popf */
257	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
258	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
259	/** The status bits commonly updated by arithmetic instructions. */
260	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
261	/** @} */
262
263
264	#ifndef __ASSEMBLER__
265
266	/** CPUID Feature information - ECX.
267	* CPUID query with EAX=1.
268	*/
269	# ifndef VBOX_FOR_DTRACE_LIB
270	typedef struct X86CPUIDFEATECX
271	{
272	/** Bit 0 - SSE3 - Supports SSE3 or not. */
273	unsigned u1SSE3 : 1;
274	/** Bit 1 - PCLMULQDQ. */
275	unsigned u1PCLMULQDQ : 1;
276	/** Bit 2 - DS Area 64-bit layout. */
277	unsigned u1DTE64 : 1;
278	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
279	unsigned u1Monitor : 1;
280	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
281	unsigned u1CPLDS : 1;
282	/** Bit 5 - VMX - Virtual Machine Technology. */
283	unsigned u1VMX : 1;
284	/** Bit 6 - SMX: Safer Mode Extensions. */
285	unsigned u1SMX : 1;
286	/** Bit 7 - EST - Enh. SpeedStep Tech. */
287	unsigned u1EST : 1;
288	/** Bit 8 - TM2 - Terminal Monitor 2. */
289	unsigned u1TM2 : 1;
290	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
291	unsigned u1SSSE3 : 1;
292	/** Bit 10 - CNTX-ID - L1 Context ID. */
293	unsigned u1CNTXID : 1;
294	/** Bit 11 - Reserved. */
295	unsigned u1Reserved1 : 1;
296	/** Bit 12 - FMA. */
297	unsigned u1FMA : 1;
298	/** Bit 13 - CX16 - CMPXCHG16B. */
299	unsigned u1CX16 : 1;
300	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
301	unsigned u1TPRUpdate : 1;
302	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
303	unsigned u1PDCM : 1;
304	/** Bit 16 - Reserved. */
305	unsigned u1Reserved2 : 1;
306	/** Bit 17 - PCID - Process-context identifiers. */
307	unsigned u1PCID : 1;
308	/** Bit 18 - Direct Cache Access. */
309	unsigned u1DCA : 1;
310	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
311	unsigned u1SSE4_1 : 1;
312	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
313	unsigned u1SSE4_2 : 1;
314	/** Bit 21 - x2APIC. */
315	unsigned u1x2APIC : 1;
316	/** Bit 22 - MOVBE - Supports MOVBE. */
317	unsigned u1MOVBE : 1;
318	/** Bit 23 - POPCNT - Supports POPCNT. */
319	unsigned u1POPCNT : 1;
320	/** Bit 24 - TSC-Deadline. */
321	unsigned u1TSCDEADLINE : 1;
322	/** Bit 25 - AES. */
323	unsigned u1AES : 1;
324	/** Bit 26 - XSAVE - Supports XSAVE. */
325	unsigned u1XSAVE : 1;
326	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
327	unsigned u1OSXSAVE : 1;
328	/** Bit 28 - AVX - Supports AVX instruction extensions. */
329	unsigned u1AVX : 1;
330	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
331	unsigned u1F16C : 1;
332	/** Bit 30 - RDRAND - Supports RDRAND. */
333	unsigned u1RDRAND : 1;
334	/** Bit 31 - Hypervisor present (we're a guest). */
335	unsigned u1HVP : 1;
336	} X86CPUIDFEATECX;
337	# else /* VBOX_FOR_DTRACE_LIB */
338	typedef uint32_t X86CPUIDFEATECX;
339	# endif /* VBOX_FOR_DTRACE_LIB */
340	/** Pointer to CPUID Feature Information - ECX. */
341	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
342	/** Pointer to const CPUID Feature Information - ECX. */
343	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
344
345
346	/** CPUID Feature Information - EDX.
347	* CPUID query with EAX=1.
348	*/
349	# ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
350	typedef struct X86CPUIDFEATEDX
351	{
352	/** Bit 0 - FPU - x87 FPU on Chip. */
353	unsigned u1FPU : 1;
354	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
355	unsigned u1VME : 1;
356	/** Bit 2 - DE - Debugging extensions. */
357	unsigned u1DE : 1;
358	/** Bit 3 - PSE - Page Size Extension. */
359	unsigned u1PSE : 1;
360	/** Bit 4 - TSC - Time Stamp Counter. */
361	unsigned u1TSC : 1;
362	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
363	unsigned u1MSR : 1;
364	/** Bit 6 - PAE - Physical Address Extension. */
365	unsigned u1PAE : 1;
366	/** Bit 7 - MCE - Machine Check Exception. */
367	unsigned u1MCE : 1;
368	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
369	unsigned u1CX8 : 1;
370	/** Bit 9 - APIC - APIC On-Chip. */
371	unsigned u1APIC : 1;
372	/** Bit 10 - Reserved. */
373	unsigned u1Reserved1 : 1;
374	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
375	unsigned u1SEP : 1;
376	/** Bit 12 - MTRR - Memory Type Range Registers. */
377	unsigned u1MTRR : 1;
378	/** Bit 13 - PGE - PTE Global Bit. */
379	unsigned u1PGE : 1;
380	/** Bit 14 - MCA - Machine Check Architecture. */
381	unsigned u1MCA : 1;
382	/** Bit 15 - CMOV - Conditional Move Instructions. */
383	unsigned u1CMOV : 1;
384	/** Bit 16 - PAT - Page Attribute Table. */
385	unsigned u1PAT : 1;
386	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
387	unsigned u1PSE36 : 1;
388	/** Bit 18 - PSN - Processor Serial Number. */
389	unsigned u1PSN : 1;
390	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
391	unsigned u1CLFSH : 1;
392	/** Bit 20 - Reserved. */
393	unsigned u1Reserved2 : 1;
394	/** Bit 21 - DS - Debug Store. */
395	unsigned u1DS : 1;
396	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
397	unsigned u1ACPI : 1;
398	/** Bit 23 - MMX - Intel MMX 'Technology'. */
399	unsigned u1MMX : 1;
400	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
401	unsigned u1FXSR : 1;
402	/** Bit 25 - SSE - SSE Support. */
403	unsigned u1SSE : 1;
404	/** Bit 26 - SSE2 - SSE2 Support. */
405	unsigned u1SSE2 : 1;
406	/** Bit 27 - SS - Self Snoop. */
407	unsigned u1SS : 1;
408	/** Bit 28 - HTT - Hyper-Threading Technology. */
409	unsigned u1HTT : 1;
410	/** Bit 29 - TM - Thermal Monitor. */
411	unsigned u1TM : 1;
412	/** Bit 30 - Reserved - . */
413	unsigned u1Reserved3 : 1;
414	/** Bit 31 - PBE - Pending Break Enabled. */
415	unsigned u1PBE : 1;
416	} X86CPUIDFEATEDX;
417	# else /* VBOX_FOR_DTRACE_LIB */
418	typedef uint32_t X86CPUIDFEATEDX;
419	# endif /* VBOX_FOR_DTRACE_LIB */
420	/** Pointer to CPUID Feature Information - EDX. */
421	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
422	/** Pointer to const CPUID Feature Information - EDX. */
423	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
424
425	#endif /* !__ASSEMBLER__ */
426
427
428	/** @name CPUID Vendor information.
429	* CPUID query with EAX=0.
430	* @{
431	*/
432	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
433	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
434	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
435
436	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
437	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
438	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
439
440	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
441	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
442	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
443
444	#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
445	#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
446	#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
447
448	#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
449	#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
450	#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
451	/** @} */
452
453
454	/** @name CPUID Feature information.
455	* CPUID query with EAX=1.
456	* @{
457	*/
458	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
459	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
460	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
461	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
462	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
463	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
464	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
465	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
466	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
467	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
468	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
469	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
470	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
471	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
472	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
473	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
474	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
475	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
476	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
477	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
478	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
479	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
480	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
481	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
482	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
483	/** ECX Bit 12 - FMA. */
484	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
485	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
486	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
487	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
488	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
489	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
490	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
491	/** ECX Bit 17 - PCID - Process-context identifiers. */
492	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
493	/** ECX Bit 18 - DCA - Direct Cache Access. */
494	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
495	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
496	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
497	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
498	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
499	/** ECX Bit 21 - x2APIC support. */
500	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
501	/** ECX Bit 22 - MOVBE instruction. */
502	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
503	/** ECX Bit 23 - POPCNT instruction. */
504	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
505	/** ECX Bir 24 - TSC-Deadline. */
506	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
507	/** ECX Bit 25 - AES instructions. */
508	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
509	/** ECX Bit 26 - XSAVE instruction. */
510	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
511	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
512	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
513	/** ECX Bit 28 - AVX. */
514	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
515	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
516	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
517	/** ECX Bit 30 - RDRAND instruction. */
518	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
519	/** ECX Bit 31 - Hypervisor Present (software only). */
520	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
521
522
523	/** Bit 0 - FPU - x87 FPU on Chip. */
524	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
525	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
526	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
527	/** Bit 2 - DE - Debugging extensions. */
528	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
529	/** Bit 3 - PSE - Page Size Extension. */
530	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
531	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
532	/** Bit 4 - TSC - Time Stamp Counter. */
533	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
534	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
535	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
536	/** Bit 6 - PAE - Physical Address Extension. */
537	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
538	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
539	/** Bit 7 - MCE - Machine Check Exception. */
540	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
541	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
542	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
543	/** Bit 9 - APIC - APIC On-Chip. */
544	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
545	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
546	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
547	/** Bit 12 - MTRR - Memory Type Range Registers. */
548	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
549	/** Bit 13 - PGE - PTE Global Bit. */
550	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
551	/** Bit 14 - MCA - Machine Check Architecture. */
552	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
553	/** Bit 15 - CMOV - Conditional Move Instructions. */
554	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
555	/** Bit 16 - PAT - Page Attribute Table. */
556	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
557	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
558	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
559	/** Bit 18 - PSN - Processor Serial Number. */
560	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
561	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
562	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
563	/** Bit 21 - DS - Debug Store. */
564	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
565	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
566	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
567	/** Bit 23 - MMX - Intel MMX Technology. */
568	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
569	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
570	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
571	/** Bit 25 - SSE - SSE Support. */
572	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
573	/** Bit 26 - SSE2 - SSE2 Support. */
574	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
575	/** Bit 27 - SS - Self Snoop. */
576	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
577	/** Bit 28 - HTT - Hyper-Threading Technology. */
578	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
579	/** Bit 29 - TM - Therm. Monitor. */
580	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
581	/** Bit 31 - PBE - Pending Break Enabled. */
582	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
583	/** @} */
584
585	/** @name CPUID mwait/monitor information.
586	* CPUID query with EAX=5.
587	* @{
588	*/
589	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
590	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
591	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
592	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
593	/** @} */
594
595
596	/** @name CPUID Thermal and Power Management information.
597	* Generally Intel only unless noted otherwise.
598	* CPUID query with EAX=5. @{
599	*/
600	/** EAX Bit 0 - DTS - Supports Digital Temperature Sensor. */
601	#define X86_CPUID_POWER_EAX_DTS RT_BIT_32(0)
602	/** EAX Bit 1 - TURBOBOOST - Intel Turbo Boost available. */
603	#define X86_CPUID_POWER_EAX_TURBOBOOST RT_BIT_32(1)
604	/** EAX Bit 2 - ARAT - Always Running APIC Timer. Intel and AMD. */
605	#define X86_CPUID_POWER_EAX_ARAT RT_BIT_32(2)
606	/** EAX Bit 4 - PLN - Power Limit Notifications supported. */
607	#define X86_CPUID_POWER_EAX_PLN RT_BIT_32(4)
608	/** EAX Bit 5 - ECMD - Clock modulation duty cycle extension supported. */
609	#define X86_CPUID_POWER_EAX_ECMD RT_BIT_32(5)
610	/** EAX Bit 6 - PTM - Package Thermal Management supported. */
611	#define X86_CPUID_POWER_EAX_PTM RT_BIT_32(6)
612	/** EAX Bit 7 - HWP - HWP base MSRs supported. */
613	#define X86_CPUID_POWER_EAX_HWP RT_BIT_32(7)
614	/** EAX Bit 8 - HWP_NOTIFY - HWP notification MSR supported. */
615	#define X86_CPUID_POWER_EAX_HWP_NOTIFY RT_BIT_32(8)
616	/** EAX Bit 9 - HWP_ACT_WIN - HWP activity window MSR bits supported. */
617	#define X86_CPUID_POWER_EAX_HWP_ACT_WIN RT_BIT_32(9)
618	/** EAX Bit 10 - HWP_NRG_PP - HWP energy performae preference MSR bits supported. */
619	#define X86_CPUID_POWER_EAX_HWP_NRG_PP RT_BIT_32(10)
620	/** EAX Bit 11 - HWP_PLR - HWP package level request MSR supported. */
621	#define X86_CPUID_POWER_EAX_HWP_PLR RT_BIT_32(11)
622	/** EAX Bit 13 - HDC - HDC base MSRs supported. */
623	#define X86_CPUID_POWER_EAX_HDC RT_BIT_32(13)
624	/** EAX Bit 14 - TBM30 - Turbo Boost Max Technology 3.0 supported. */
625	#define X86_CPUID_POWER_EAX_TBM30 RT_BIT_32(14)
626	/** EAX Bit 15 - HWP_HPC - HWP Highest Performance change supported. */
627	#define X86_CPUID_POWER_EAX_HWP_HPC RT_BIT_32(15)
628	/** EAX Bit 16 - HWP_PECI - HWP PECI override supported. */
629	#define X86_CPUID_POWER_EAX_HWP_PECI RT_BIT_32(16)
630	/** EAX Bit 17 - HWP_FLEX - Flexible HWP supported. */
631	#define X86_CPUID_POWER_EAX_HWP_FLEX RT_BIT_32(17)
632
633	/** ECX Bit 1 - HCFC - Hardware Coordintion Feedback Capability supported. Intel and AMD. */
634	#define X86_CPUID_POWER_ECX_HCFC RT_BIT_32(0)
635	/** @} */
636
637
638	/** @name CPUID Structured Extended Feature information.
639	* CPUID query with EAX=7.
640	* @{
641	*/
642	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
643	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
644	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
645	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
646	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
647	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
648	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
649	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
650	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
651	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
652	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
653	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
654	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
655	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
656	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
657	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
658	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
659	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
660	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
661	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
662	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
663	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
664	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
665	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
666	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
667	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
668	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
669	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
670	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
671	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
672	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
673	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
674	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
675	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
676	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
677	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
678	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
679	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
680	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
681	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
682	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
683	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
684	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
685	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
686	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
687	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
688	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
689	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
690	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
691	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
692	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
693	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
694
695	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
696	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
697	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
698	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
699	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
700	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
701	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
702	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
703	/** ECX Bit 7 - CET_SS - Supports CET shadow stack features. */
704	#define X86_CPUID_STEXT_FEATURE_ECX_CET_SS RT_BIT_32(7)
705	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
706	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
707	/** ECX Bit 22 - RDPID - Support pread process ID. */
708	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
709	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
710	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
711
712	/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
713	#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
714	/** EDX Bit 20 - CET_IBT - Supports CET indirect branch tracking features. */
715	#define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT_32(20)
716	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
717	* IBPB command in IA32_PRED_CMD. */
718	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
719	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
720	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
721	/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
722	#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
723	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
724	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
725	/** EDX Bit 30 - CORECAP - Supports the IA32_CORE_CAPABILITIES MSR. */
726	#define X86_CPUID_STEXT_FEATURE_EDX_CORECAP RT_BIT_32(30)
727	/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
728	#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
729
730	/** @} */
731
732
733	/** @name CPUID Extended Feature information.
734	* CPUID query with EAX=0x80000001.
735	* @{
736	*/
737	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
738	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
739
740	/** EDX Bit 11 - SYSCALL/SYSRET. */
741	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
742	/** EDX Bit 20 - No-Execute/Execute-Disable. */
743	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
744	/** EDX Bit 26 - 1 GB large page. */
745	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
746	/** EDX Bit 27 - RDTSCP. */
747	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
748	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
749	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
750	/** @}*/
751
752	/** @name CPUID AMD Feature information.
753	* CPUID query with EAX=0x80000001.
754	* @{
755	*/
756	/** Bit 0 - FPU - x87 FPU on Chip. */
757	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
758	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
759	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
760	/** Bit 2 - DE - Debugging extensions. */
761	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
762	/** Bit 3 - PSE - Page Size Extension. */
763	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
764	/** Bit 4 - TSC - Time Stamp Counter. */
765	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
766	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
767	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
768	/** Bit 6 - PAE - Physical Address Extension. */
769	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
770	/** Bit 7 - MCE - Machine Check Exception. */
771	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
772	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
773	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
774	/** Bit 9 - APIC - APIC On-Chip. */
775	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
776	/** Bit 12 - MTRR - Memory Type Range Registers. */
777	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
778	/** Bit 13 - PGE - PTE Global Bit. */
779	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
780	/** Bit 14 - MCA - Machine Check Architecture. */
781	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
782	/** Bit 15 - CMOV - Conditional Move Instructions. */
783	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
784	/** Bit 16 - PAT - Page Attribute Table. */
785	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
786	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
787	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
788	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
789	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
790	/** Bit 23 - MMX - Intel MMX Technology. */
791	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
792	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
793	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
794	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
795	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
796	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
797	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
798	/** Bit 31 - 3DNOW - AMD 3DNow. */
799	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
800
801	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
802	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
803	/** Bit 2 - SVM - AMD VM extensions. */
804	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
805	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
806	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
807	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
808	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
809	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
810	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
811	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
812	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
813	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
814	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
815	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
816	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
817	/** Bit 9 - OSVW - AMD OS visible workaround. */
818	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
819	/** Bit 10 - IBS - Instruct based sampling. */
820	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
821	/** Bit 11 - XOP - Extended operation support (see APM6). */
822	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
823	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
824	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
825	/** Bit 13 - WDT - AMD Watchdog timer support. */
826	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
827	/** Bit 15 - LWP - Lightweight profiling support. */
828	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
829	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
830	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
831	/** Bit 19 - NodeId - Indicates support for
832	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
833	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
834	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
835	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
836	/** Bit 22 - TopologyExtensions - . */
837	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
838	/** @} */
839
840
841	/** @name CPUID AMD Feature information.
842	* CPUID query with EAX=0x80000007.
843	* @{
844	*/
845	/** Bit 0 - TS - Temperature Sensor. */
846	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
847	/** Bit 1 - FID - Frequency ID Control. */
848	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
849	/** Bit 2 - VID - Voltage ID Control. */
850	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
851	/** Bit 3 - TTP - THERMTRIP. */
852	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
853	/** Bit 4 - TM - Hardware Thermal Control. */
854	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
855	/** Bit 5 - STC - Software Thermal Control. */
856	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
857	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
858	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
859	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
860	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
861	/** Bit 8 - TSCINVAR - TSC Invariant. */
862	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
863	/** Bit 9 - CPB - TSC Invariant. */
864	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
865	/** Bit 10 - EffFreqRO - MPERF/APERF. */
866	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
867	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
868	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
869	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
870	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
871	/** @} */
872
873
874	/** @name CPUID AMD extended feature extensions ID (EBX).
875	* CPUID query with EAX=0x80000008.
876	* @{
877	*/
878	/** Bit 0 - CLZERO - Clear zero instruction. */
879	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
880	/** Bit 1 - IRPerf - Instructions retired count support. */
881	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
882	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
883	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
884	/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
885	#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
886	/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
887	#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
888	/* AMD pipeline length: 9 feature bits ;-) */
889	/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
890	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
891	/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
892	#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
893	/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
894	#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
895	/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
896	#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
897	/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
898	#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
899	/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
900	#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
901	/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
902	#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
903	/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
904	#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
905	/** Bit 26 - Speculative Store Bypass Disable not required. */
906	#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
907	/** @} */
908
909
910	/** @name CPUID AMD SVM Feature information.
911	* CPUID query with EAX=0x8000000a.
912	* @{
913	*/
914	/** Bit 0 - NP - Nested Paging supported. */
915	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
916	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
917	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
918	/** Bit 2 - SVML - SVM locking bit supported. */
919	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
920	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
921	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
922	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
923	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
924	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
925	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
926	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
927	* VMCB.TLB_Control is supported. */
928	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
929	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
930	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
931	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
932	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
933	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
934	* intercept filter cycle count threshold. */
935	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
936	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
937	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
938	/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
939	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
940	/** Bit 16 - VGIF - Supports virtualized GIF. */
941	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
942	/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
943	#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
944	/** Bit 18 - X2AVIC - Supports Advanced Virtual Interrupt Controller in x2APIC
945	* mode. */
946	#define X86_CPUID_SVM_FEATURE_EDX_X2AVIC RT_BIT(18)
947	/** Bit 19 - SSSCheck - SVM supervisor shadow stack restrictions. */
948	#define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
949	/** Bit 20 - SpecCtrl - Supports SPEC_CTRL Virtualization. */
950	#define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
951	/** Bit 21 - ROGPT - Read-Only Guest Page Table. */
952	#define X86_CPUID_SVM_FEATURE_EDX_ROGPT RT_BIT(21)
953	/** Bit 23 - HOST_MCE_OVERRIDE - Supports host \#MC exception override. */
954	#define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
955	/** Bit 24 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
956	#define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
957	/** Bit 25 - TlbiCtl - Supports virtual NMIs. */
958	#define X86_CPUID_SVM_FEATURE_EDX_VNMI RT_BIT(25)
959	/** Bit 26 - TlbiCtl - Supports IBS virtualization. */
960	#define X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT RT_BIT(26)
961	/** Bit 27 - TlbiCtl - Supports extended LVT AVIC access changes. */
962	#define X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG RT_BIT(27)
963	/** Bit 28 - TlbiCtl - Supports guest VMCB address check. */
964	#define X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK RT_BIT(28)
965	/** Bit 29 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
966	#define X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD RT_BIT(29)
967
968	/** @} */
969
970
971	/** @name CR0
972	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
973	* reserved flags.
974	* @{ */
975	/** Bit 0 - PE - Protection Enabled */
976	#define X86_CR0_PE RT_BIT_32(0)
977	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
978	#define X86_CR0_PE_BIT 0
979	/** Bit 1 - MP - Monitor Coprocessor */
980	#define X86_CR0_MP RT_BIT_32(1)
981	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
982	#define X86_CR0_MP_BIT 1
983	/** Bit 2 - EM - Emulation. */
984	#define X86_CR0_EM RT_BIT_32(2)
985	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
986	#define X86_CR0_EM_BIT 2
987	/** Bit 3 - TS - Task Switch. */
988	#define X86_CR0_TS RT_BIT_32(3)
989	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
990	#define X86_CR0_TS_BIT 3
991	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
992	#define X86_CR0_ET RT_BIT_32(4)
993	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
994	#define X86_CR0_ET_BIT 4
995	/** Bit 5 - NE - Numeric error (486+). */
996	#define X86_CR0_NE RT_BIT_32(5)
997	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
998	#define X86_CR0_NE_BIT 5
999	/** Bit 16 - WP - Write Protect (486+). */
1000	#define X86_CR0_WP RT_BIT_32(16)
1001	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
1002	#define X86_CR0_WP_BIT 16
1003	/** Bit 18 - AM - Alignment Mask (486+). */
1004	#define X86_CR0_AM RT_BIT_32(18)
1005	#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
1006	#define X86_CR0_AM_BIT 18
1007	/** Bit 29 - NW - Not Write-though (486+). */
1008	#define X86_CR0_NW RT_BIT_32(29)
1009	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
1010	#define X86_CR0_NW_BIT 29
1011	/** Bit 30 - WP - Cache Disable (486+). */
1012	#define X86_CR0_CD RT_BIT_32(30)
1013	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
1014	#define X86_CR0_CD_BIT 30
1015	/** Bit 31 - PG - Paging. */
1016	#define X86_CR0_PG RT_BIT_32(31)
1017	#define X86_CR0_PAGING RT_BIT_32(31)
1018	#define X86_CR0_BIT_PG 31 /*< Bit number of X86_CR0_PG /
1019	/** @} */
1020
1021
1022	/** @name CR3
1023	* @{ */
1024	/** Bit 3 - PWT - Page-level Writes Transparent. */
1025	#define X86_CR3_PWT RT_BIT_32(3)
1026	#define X86_CR3_PWT_BIT 3
1027	/** Bit 4 - PCD - Page-level Cache Disable. */
1028	#define X86_CR3_PCD RT_BIT_32(4)
1029	#define X86_CR3_PCD_BIT 4
1030	/** Bits 12-31 - - Page directory page number. */
1031	#define X86_CR3_PAGE_MASK (0xfffff000)
1032	/** Bits 5-31 - - PAE Page directory page number. */
1033	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
1034	/** Bits 12-51 - - AMD64 PML4 page number.
1035	* @note This is a maxed out mask, the actual acceptable CR3 value can
1036	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1037	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
1038	/** Bits 12-51 - - Intel EPT PML4 page number (EPTP).
1039	* @note This is a maxed out mask, the actual acceptable CR3/EPTP value can
1040	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1041	#define X86_CR3_EPT_PAGE_MASK UINT64_C(0x000ffffffffff000)
1042	/** @} */
1043
1044
1045	/** @name CR4
1046	* @{ */
1047	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
1048	#define X86_CR4_VME RT_BIT_32(0)
1049	#define X86_CR4_VME_BIT 0
1050	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
1051	#define X86_CR4_PVI RT_BIT_32(1)
1052	#define X86_CR4_PVI_BIT 1
1053	/** Bit 2 - TSD - Time Stamp Disable. */
1054	#define X86_CR4_TSD RT_BIT_32(2)
1055	#define X86_CR4_TSD_BIT 2
1056	/** Bit 3 - DE - Debugging Extensions. */
1057	#define X86_CR4_DE RT_BIT_32(3)
1058	#define X86_CR4_DE_BIT 3
1059	/** Bit 4 - PSE - Page Size Extension. */
1060	#define X86_CR4_PSE RT_BIT_32(4)
1061	#define X86_CR4_PSE_BIT 4
1062	/** Bit 5 - PAE - Physical Address Extension. */
1063	#define X86_CR4_PAE RT_BIT_32(5)
1064	#define X86_CR4_PAE_BIT 5
1065	/** Bit 6 - MCE - Machine-Check Enable. */
1066	#define X86_CR4_MCE RT_BIT_32(6)
1067	#define X86_CR4_MCE_BIT 6
1068	/** Bit 7 - PGE - Page Global Enable. */
1069	#define X86_CR4_PGE RT_BIT_32(7)
1070	#define X86_CR4_PGE_BIT 7
1071	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
1072	#define X86_CR4_PCE RT_BIT_32(8)
1073	#define X86_CR4_PCE_BIT 8
1074	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
1075	#define X86_CR4_OSFXSR RT_BIT_32(9)
1076	#define X86_CR4_OSFXSR_BIT 9
1077	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
1078	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
1079	#define X86_CR4_OSXMMEEXCPT_BIT 10
1080	/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
1081	#define X86_CR4_UMIP RT_BIT_32(11)
1082	#define X86_CR4_UMIP_BIT 11
1083	/** Bit 13 - VMXE - VMX mode is enabled. */
1084	#define X86_CR4_VMXE RT_BIT_32(13)
1085	#define X86_CR4_VMXE_BIT 13
1086	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
1087	#define X86_CR4_SMXE RT_BIT_32(14)
1088	#define X86_CR4_SMXE_BIT 14
1089	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
1090	#define X86_CR4_FSGSBASE RT_BIT_32(16)
1091	#define X86_CR4_FSGSBASE_BIT 16
1092	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
1093	#define X86_CR4_PCIDE RT_BIT_32(17)
1094	#define X86_CR4_PCIDE_BIT 17
1095	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
1096	* extended states. */
1097	#define X86_CR4_OSXSAVE RT_BIT_32(18)
1098	#define X86_CR4_OSXSAVE_BIT 18
1099	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
1100	#define X86_CR4_SMEP RT_BIT_32(20)
1101	#define X86_CR4_SMEP_BIt 20
1102	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
1103	#define X86_CR4_SMAP RT_BIT_32(21)
1104	#define X86_CR4_SMAP_BIT 21
1105	/** Bit 22 - PKE - Protection Key Enable. */
1106	#define X86_CR4_PKE RT_BIT_32(22)
1107	#define X86_CR4_PKE_BIT 22
1108	/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
1109	#define X86_CR4_CET RT_BIT_32(23)
1110	#define X86_CR4_CET_BIT 23
1111	/** @} */
1112
1113
1114	/** @name DR6
1115	* @{ */
1116	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
1117	#define X86_DR6_B0 RT_BIT_32(0)
1118	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
1119	#define X86_DR6_B1 RT_BIT_32(1)
1120	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
1121	#define X86_DR6_B2 RT_BIT_32(2)
1122	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
1123	#define X86_DR6_B3 RT_BIT_32(3)
1124	/** Mask of all the Bx bits. */
1125	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
1126	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
1127	#define X86_DR6_BD RT_BIT_32(13)
1128	/** Bit 14 - BS - Single step */
1129	#define X86_DR6_BS RT_BIT_32(14)
1130	/** Bit 15 - BT - Task switch. (TSS T bit.) */
1131	#define X86_DR6_BT RT_BIT_32(15)
1132	/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
1133	#define X86_DR6_RTM RT_BIT_32(16)
1134	/** Value of DR6 after powerup/reset. */
1135	#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
1136	/** Bits which must be 1s in DR6. */
1137	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
1138	/** Bits which must be 1s in DR6, when RTM is supported. */
1139	#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
1140	/** Bits which must be 0s in DR6. */
1141	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
1142	/** Bits which must be 0s on writes to DR6. */
1143	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
1144	/** @} */
1145
1146	/** Get the DR6.Bx bit for a the given breakpoint. */
1147	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
1148
1149
1150	/** @name DR7
1151	* @{ */
1152	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1153	#define X86_DR7_L0 RT_BIT_32(0)
1154	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1155	#define X86_DR7_G0 RT_BIT_32(1)
1156	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1157	#define X86_DR7_L1 RT_BIT_32(2)
1158	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1159	#define X86_DR7_G1 RT_BIT_32(3)
1160	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1161	#define X86_DR7_L2 RT_BIT_32(4)
1162	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1163	#define X86_DR7_G2 RT_BIT_32(5)
1164	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1165	#define X86_DR7_L3 RT_BIT_32(6)
1166	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1167	#define X86_DR7_G3 RT_BIT_32(7)
1168	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1169	#define X86_DR7_LE RT_BIT_32(8)
1170	/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1171	#define X86_DR7_GE RT_BIT_32(9)
1172
1173	/** L0, L1, L2, and L3. */
1174	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1175	/** L0, L1, L2, and L3. */
1176	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1177
1178	/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1179	* Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1180	#define X86_DR7_RTM RT_BIT_32(11)
1181	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1182	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1183	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1184	* instruction is executed.
1185	* @see http://www.rcollins.org/secrets/DR7.html */
1186	#define X86_DR7_ICE_IR RT_BIT_32(12)
1187	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1188	* any DR register is accessed. */
1189	#define X86_DR7_GD RT_BIT_32(13)
1190	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1191	* Pentium. */
1192	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1193	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1194	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1195	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
1196	#define X86_DR7_RW0_MASK (3 << 16)
1197	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
1198	#define X86_DR7_LEN0_MASK (3 << 18)
1199	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
1200	#define X86_DR7_RW1_MASK (3 << 20)
1201	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
1202	#define X86_DR7_LEN1_MASK (3 << 22)
1203	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
1204	#define X86_DR7_RW2_MASK (3 << 24)
1205	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1206	#define X86_DR7_LEN2_MASK (3 << 26)
1207	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1208	#define X86_DR7_RW3_MASK (3 << 28)
1209	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1210	#define X86_DR7_LEN3_MASK (3 << 30)
1211
1212	/** Bits which reads as 1s. */
1213	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1214	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1215	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1216	/** Bits which must be 0s when writing to DR7. */
1217	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1218
1219	/** Calcs the L bit of Nth breakpoint.
1220	* @param iBp The breakpoint number [0..3].
1221	*/
1222	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1223
1224	/** Calcs the G bit of Nth breakpoint.
1225	* @param iBp The breakpoint number [0..3].
1226	*/
1227	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1228
1229	/** Calcs the L and G bits of Nth breakpoint.
1230	* @param iBp The breakpoint number [0..3].
1231	*/
1232	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1233
1234	/** @name Read/Write values.
1235	* @{ */
1236	/** Break on instruction fetch only. */
1237	#define X86_DR7_RW_EO UINT32_C(0)
1238	/** Break on write only. */
1239	#define X86_DR7_RW_WO UINT32_C(1)
1240	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1241	#define X86_DR7_RW_IO UINT32_C(2)
1242	/** Break on read or write (but not instruction fetches). */
1243	#define X86_DR7_RW_RW UINT32_C(3)
1244	/** @} */
1245
1246	/** Shifts a X86_DR7_RW_* value to its right place.
1247	* @param iBp The breakpoint number [0..3].
1248	* @param fRw One of the X86_DR7_RW_* value.
1249	*/
1250	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1251
1252	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1253	* one of the X86_DR7_RW_XXX constants).
1254	*
1255	* @returns X86_DR7_RW_XXX
1256	* @param uDR7 DR7 value
1257	* @param iBp The breakpoint number [0..3].
1258	*/
1259	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1260
1261	/** R/W0, R/W1, R/W2, and R/W3. */
1262	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1263
1264	#ifndef VBOX_FOR_DTRACE_LIB
1265	/** Checks if the RW and LEN fields are set up for an instruction breakpoint.
1266	* @note This does not check if it's enabled. */
1267	# define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x000f0000) << ((a_iBp) * 4))) == 0 )
1268	/** Checks if an instruction breakpoint is enabled and configured correctly.
1269	* @sa X86_DR7_IS_EO_CFG, X86_DR7_ANY_EO_ENABLED */
1270	# define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
1271	( ((a_uDR7) & (UINT32_C(0x03) << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
1272	/** Checks if there are any instruction fetch breakpoint types configured in
1273	* the RW and LEN registers and enabled in the Lx/Gx bits.
1274	* @sa X86_DR7_IS_EO_CFG, X86_DR7_IS_EO_ENABLED */
1275	# define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
1276	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \
1277	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \
1278	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
1279	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
1280
1281	/** Checks if the RW field is set up for a read-write data breakpoint.
1282	* @note This does not check if it's enabled. */
1283	# define X86_DR7_IS_RW_CFG(a_uDR7, a_iBp) ( ~((a_uDR7) & (UINT32_C(0x00030000) << ((a_iBp) * 4))) == 0)
1284
1285	/** Checks if there are any read-write data breakpoint types configured in the
1286	* RW registers and enabled in the Lx/Gx bits.
1287	*
1288	* @note We don't consider the LEN registers here, even if qword isn't
1289	* techincally valid for older processors - see
1290	* @sdmv3{082,645,18.2.4,Debug Control Register (DR7)} for details.
1291	*/
1292	# define X86_DR7_ANY_RW_ENABLED(a_uDR7) \
1293	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x00030000)) == UINT32_C(0x00030000)) \
1294	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00300000)) == UINT32_C(0x00300000)) \
1295	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x03000000)) == UINT32_C(0x03000000)) \
1296	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0x30000000)) == UINT32_C(0x30000000)) )
1297
1298	/** Checks if the RW field is set up for a write-only or read-write data
1299	* breakpoint.
1300	* @note This does not check if it's enabled. */
1301	# define X86_DR7_IS_W_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x00010000) << ((a_iBp) * 4))) != 0)
1302
1303	/** Checks if there are any read-write or write-only data breakpoint types
1304	* configured in the the RW registers and enabled in the Lx/Gx bits.
1305	*
1306	* @note We don't consider the LEN registers here, even if qword isn't
1307	* techincally valid for older processors - see
1308	* @sdmv3{082,645,18.2.4,Debug Control Register (DR7)} for details.
1309	*/
1310	# define X86_DR7_ANY_W_ENABLED(a_uDR7) \
1311	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x00010000)) != 0) \
1312	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00100000)) != 0) \
1313	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x01000000)) != 0) \
1314	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0x10000000)) != 0) )
1315
1316	/** Checks if there are any I/O breakpoint types configured in the RW
1317	* registers. Does NOT check if these are enabled, sorry. */
1318	# define X86_DR7_ANY_RW_IO(uDR7) \
1319	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1320	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1321	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1322	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1323	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1324	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1325	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1326	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1327	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1328	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1329	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1330
1331	#endif /* !VBOX_FOR_DTRACE_LIB */
1332
1333	/** @name Length values.
1334	* @{ */
1335	#define X86_DR7_LEN_BYTE UINT32_C(0)
1336	#define X86_DR7_LEN_WORD UINT32_C(1)
1337	#define X86_DR7_LEN_QWORD UINT32_C(2) /*< AMD64 long mode only. /
1338	#define X86_DR7_LEN_DWORD UINT32_C(3)
1339	/** @} */
1340
1341	/** Shifts a X86_DR7_LEN_* value to its right place.
1342	* @param iBp The breakpoint number [0..3].
1343	* @param cb One of the X86_DR7_LEN_* values.
1344	*/
1345	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1346
1347	/** Fetch the breakpoint length bits from the DR7 value.
1348	* @param uDR7 DR7 value
1349	* @param iBp The breakpoint number [0..3].
1350	*/
1351	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1352
1353	/** Mask used to check if any breakpoints are enabled. */
1354	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1355
1356	/** LEN0, LEN1, LEN2, and LEN3. */
1357	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1358	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1359	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1360
1361	/** Value of DR7 after powerup/reset. */
1362	#define X86_DR7_INIT_VAL 0x400
1363	/** @} */
1364
1365
1366	/** @name Machine Specific Registers
1367	* @{
1368	*/
1369	/** Machine check address register (P5). */
1370	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1371	/** Machine check type register (P5). */
1372	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1373	/** Time Stamp Counter. */
1374	#define MSR_IA32_TSC 0x10
1375	#define MSR_IA32_CESR UINT32_C(0x00000011)
1376	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1377	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1378
1379	#define MSR_IA32_PLATFORM_ID 0x17
1380
1381	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1382	# define MSR_IA32_APICBASE 0x1b
1383	/** Local APIC enabled. */
1384	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1385	/** X2APIC enabled (requires the EN bit to be set). */
1386	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1387	/** The processor is the boot strap processor (BSP). */
1388	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1389	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1390	* width. */
1391	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1392	/** The default physical base address of the APIC. */
1393	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1394	/** Gets the physical base address from the MSR. */
1395	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1396	#endif
1397
1398	/** Memory Control (Intel-specific). */
1399	#define MSR_MEMORY_CTRL 0x33
1400	/** Memory Control - UC-store throttle. */
1401	#define MSR_MEMORY_CTRL_UC_STORE_THROTTLE RT_BIT_64(27)
1402	/** Memory Control - UC-lock disable. */
1403	#define MSR_MEMORY_CTRL_UC_LOCK_DISABLE RT_BIT_64(28)
1404	/** Memory Control - Split-lock disable. */
1405	#define MSR_MEMORY_CTRL_SPLIT_LOCK_DISABLE RT_BIT_64(29)
1406
1407	/** Undocumented intel MSR for reporting thread and core counts.
1408	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1409	* first 16 bits is the thread count. The next 16 bits the core count, except
1410	* on Westmere where it seems it's only the next 4 bits for some reason. */
1411	#define MSR_CORE_THREAD_COUNT 0x35
1412
1413	/** CPU Feature control. */
1414	#define MSR_IA32_FEATURE_CONTROL 0x3A
1415	/** Feature control - Lock MSR from writes (R/W0). */
1416	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1417	/** Feature control - Enable VMX inside SMX operation (R/WL). */
1418	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1419	/** Feature control - Enable VMX outside SMX operation (R/WL). */
1420	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1421	/** Feature control - SENTER local functions enable (R/WL). */
1422	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1423	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1424	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1425	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1426	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1427	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1428	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1429	/** Feature control - SENTER global enable (R/WL). */
1430	#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1431	/** Feature control - SGX launch control enable (R/WL). */
1432	#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1433	/** Feature control - SGX global enable (R/WL). */
1434	#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1435	/** Feature control - LMCE on (R/WL). */
1436	#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1437
1438	/** Per-processor TSC adjust MSR. */
1439	#define MSR_IA32_TSC_ADJUST 0x3B
1440
1441	/** Spectre control register.
1442	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1443	#define MSR_IA32_SPEC_CTRL 0x48
1444	/** IBRS - Indirect branch restricted speculation. */
1445	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1446	/** STIBP - Single thread indirect branch predictors. */
1447	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1448	/** SSBD - Speculative Store Bypass Disable. */
1449	#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
1450
1451	/** Prediction command register.
1452	* Write only, logical processor scope, no state since write only. */
1453	#define MSR_IA32_PRED_CMD 0x49
1454	/** IBPB - Indirect branch prediction barrie when written as 1. */
1455	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1456
1457	/** BIOS update trigger (microcode update). */
1458	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1459
1460	/** BIOS update signature (microcode). */
1461	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1462
1463	/** SMM monitor control. */
1464	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1465	/** SMM control - Valid. */
1466	#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1467	/** SMM control - VMXOFF unblocks SMI. */
1468	#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1469	/** SMM control - MSEG base physical address. */
1470	#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1471
1472	/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1473	#define MSR_IA32_SMBASE 0x9E
1474
1475	/** General performance counter no. 0. */
1476	#define MSR_IA32_PMC0 0xC1
1477	/** General performance counter no. 1. */
1478	#define MSR_IA32_PMC1 0xC2
1479	/** General performance counter no. 2. */
1480	#define MSR_IA32_PMC2 0xC3
1481	/** General performance counter no. 3. */
1482	#define MSR_IA32_PMC3 0xC4
1483	/** General performance counter no. 4. */
1484	#define MSR_IA32_PMC4 0xC5
1485	/** General performance counter no. 5. */
1486	#define MSR_IA32_PMC5 0xC6
1487	/** General performance counter no. 6. */
1488	#define MSR_IA32_PMC6 0xC7
1489	/** General performance counter no. 7. */
1490	#define MSR_IA32_PMC7 0xC8
1491
1492	/** Nehalem power control. */
1493	#define MSR_IA32_PLATFORM_INFO 0xCE
1494
1495	/** Core Capabilities (Intel-specific). */
1496	#define MSR_IA32_CORE_CAPABILITIES 0xCF
1497	/** STLB QoS feature supported. */
1498	#define MSR_IA32_CORE_CAP_STLB_QOS RT_BIT_64(0)
1499	/** FUSA feature supported. */
1500	#define MSR_IA32_CORE_CAP_FUSA RT_BIT_64(2)
1501	/** RSM instruction only allowed in CPL 0. */
1502	#define MSR_IA32_CORE_CAP_RSM_CPL0 RT_BIT_64(3)
1503	/** UC lock disable supported. */
1504	#define MSR_IA32_CORE_CAP_UC_LOCK_DISABLE RT_BIT_64(4)
1505	/** Split-lock disable supported. */
1506	#define MSR_IA32_CORE_CAP_SPLIT_LOCK_DISABLE RT_BIT_64(5)
1507	/** Snoop filter QoS Mask MSRs supported. */
1508	#define MSR_IA32_CORE_CAP_SNOOP_FILTER_QOS RT_BIT_64(6)
1509	/** UC store throttling supported. */
1510	#define MSR_IA32_CORE_CAP_UC_STORE_THROTTLE RT_BIT_64(7)
1511
1512	/** Get FSB clock status (Intel-specific). */
1513	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1514
1515	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1516	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1517
1518	/** C0 Maximum Frequency Clock Count */
1519	#define MSR_IA32_MPERF 0xE7
1520	/** C0 Actual Frequency Clock Count */
1521	#define MSR_IA32_APERF 0xE8
1522
1523	/** MTRR Capabilities. */
1524	#define MSR_IA32_MTRR_CAP 0xFE
1525	/** Bits 0-7 - VCNT - Variable range registers count. */
1526	#define MSR_IA32_MTRR_CAP_VCNT_MASK UINT64_C(0x00000000000000ff)
1527	/** Bit 8 - FIX - Fixed range registers supported. */
1528	#define MSR_IA32_MTRR_CAP_FIX RT_BIT_64(8)
1529	/** Bit 10 - WC - Write-Combining memory type supported. */
1530	#define MSR_IA32_MTRR_CAP_WC RT_BIT_64(10)
1531	/** Bit 11 - SMRR - System Management Range Register supported. */
1532	#define MSR_IA32_MTRR_CAP_SMRR RT_BIT_64(11)
1533	/** Bit 12 - PRMRR - Processor Reserved Memory Range Register supported. */
1534	#define MSR_IA32_MTRR_CAP_PRMRR RT_BIT_64(12)
1535
1536
1537	#ifndef __ASSEMBLER__
1538	/**
1539	* Variable-range MTRR MSR pair.
1540	*/
1541	typedef struct X86MTRRVAR
1542	{
1543	uint64_t MtrrPhysBase; /*< IA32_MTRR_PHYSBASEn /
1544	uint64_t MtrrPhysMask; /*< IA32_MTRR_PHYSMASKn /
1545	} X86MTRRVAR;
1546	# ifndef VBOX_FOR_DTRACE_LIB
1547	AssertCompileSize(X86MTRRVAR, 16);
1548	# endif
1549	/** Pointer to a variable-range MTRR MSR pair. */
1550	typedef X86MTRRVAR *PX86MTRRVAR;
1551	/** Pointer to a const variable-range MTRR MSR pair. */
1552	typedef const X86MTRRVAR *PCX86MTRRVAR;
1553	#endif /* __ASSEMBLER__ */
1554
1555
1556	/** Memory types that can be encoded in MTRRs.
1557	* @{ */
1558	/** Uncacheable. */
1559	#define X86_MTRR_MT_UC 0
1560	/** Write Combining. */
1561	#define X86_MTRR_MT_WC 1
1562	/** Write-through. */
1563	#define X86_MTRR_MT_WT 4
1564	/** Write-protected. */
1565	#define X86_MTRR_MT_WP 5
1566	/** Writeback. */
1567	#define X86_MTRR_MT_WB 6
1568	/** @}*/
1569
1570	/** Architecture capabilities (bugfixes). */
1571	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1572	/** CPU is no subject to meltdown problems. */
1573	#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1574	/** CPU has better IBRS and you can leave it on all the time. */
1575	#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1576	/** CPU has return stack buffer (RSB) override. */
1577	#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1578	/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1579	* This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1580	#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1581	/** CPU does not suffer from speculative store bypass (SSB) issues. */
1582	#define MSR_IA32_ARCH_CAP_F_SSB_NO RT_BIT_32(4)
1583	/** CPU does not suffer from microarchitectural data sampling (MDS) issues. */
1584	#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(5)
1585	/** CPU does not suffer MCE after change code page size w/o invlpg issues. */
1586	#define MSR_IA32_ARCH_CAP_F_IF_PSCHANGE_MC_NO RT_BIT_32(6)
1587	/** CPU has RTM_DISABLE and TXS_CPUID_CLEAR support. */
1588	#define MSR_IA32_ARCH_CAP_F_TSX_CTRL RT_BIT_32(7)
1589	/** CPU does not suffer from transaction synchronization extensions (TSX)
1590	* asyncrhonous abort (TAA) issues. */
1591	#define MSR_IA32_ARCH_CAP_F_TAA_NO RT_BIT_32(8)
1592	/* 9 is 'reserved' */
1593	#define MSR_IA32_ARCH_CAP_F_MISC_PACKAGE_CTRLS RT_BIT_32(10)
1594	#define MSR_IA32_ARCH_CAP_F_ENERGY_FILTERING_CTL RT_BIT_32(11)
1595	#define MSR_IA32_ARCH_CAP_F_DOITM RT_BIT_32(12)
1596	#define MSR_IA32_ARCH_CAP_F_SBDR_SSDP_NO RT_BIT_32(13)
1597	#define MSR_IA32_ARCH_CAP_F_FBSDP_NO RT_BIT_32(14)
1598	#define MSR_IA32_ARCH_CAP_F_PSDP_NO RT_BIT_32(15)
1599	/* 16 is 'reserved' */
1600	#define MSR_IA32_ARCH_CAP_F_FB_CLEAR RT_BIT_32(17)
1601	#define MSR_IA32_ARCH_CAP_F_FB_CLEAR_CTRL RT_BIT_32(18)
1602	#define MSR_IA32_ARCH_CAP_F_RRSBA RT_BIT_32(19)
1603	#define MSR_IA32_ARCH_CAP_F_BHI_NO RT_BIT_32(20)
1604	#define MSR_IA32_ARCH_CAP_F_XAPIC_DISABLE_STATUS RT_BIT_32(21)
1605	/* 22 is 'reserved' */
1606	#define MSR_IA32_ARCH_CAP_F_OVERCLOCKING_STATUS RT_BIT_32(22)
1607	#define MSR_IA32_ARCH_CAP_F_PBRSB_NO RT_BIT_32(23)
1608	#define MSR_IA32_ARCH_CAP_F_GDS_CTRL RT_BIT_32(24)
1609	#define MSR_IA32_ARCH_CAP_F_GDS_NO RT_BIT_32(25)
1610	#define MSR_IA32_ARCH_CAP_F_RFDS_NO RT_BIT_32(26)
1611	#define MSR_IA32_ARCH_CAP_F_RFDS_CLEAR RT_BIT_32(27)
1612
1613	/** Flush command register. */
1614	#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1615	/** Flush the level 1 data cache when this bit is written. */
1616	#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1617
1618	/** Cache control/info. */
1619	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1620
1621	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1622	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1623	* R0 SS == CS + 8
1624	* R3 CS == CS + 16
1625	* R3 SS == CS + 24
1626	*/
1627	#define MSR_IA32_SYSENTER_CS 0x174
1628	/** SYSENTER_ESP - the R0 ESP. */
1629	#define MSR_IA32_SYSENTER_ESP 0x175
1630	/** SYSENTER_EIP - the R0 EIP. */
1631	#define MSR_IA32_SYSENTER_EIP 0x176
1632	#endif
1633
1634	/** Machine Check Global Capabilities Register. */
1635	#define MSR_IA32_MCG_CAP 0x179
1636	/** Machine Check Global Status Register. */
1637	#define MSR_IA32_MCG_STATUS 0x17A
1638	/** Machine Check Global Control Register. */
1639	#define MSR_IA32_MCG_CTRL 0x17B
1640
1641	/** Page Attribute Table. */
1642	#define MSR_IA32_CR_PAT 0x277
1643	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1644	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1645	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1646
1647	/** Memory types that can be encoded in the IA32_PAT MSR.
1648	* @{ */
1649	/** Uncacheable. */
1650	#define MSR_IA32_PAT_MT_UC 0
1651	/** Write Combining. */
1652	#define MSR_IA32_PAT_MT_WC 1
1653	/** Reserved value 2. */
1654	#define MSR_IA32_PAT_MT_RSVD_2 2
1655	/** Reserved value 3. */
1656	#define MSR_IA32_PAT_MT_RSVD_3 3
1657	/** Write-through. */
1658	#define MSR_IA32_PAT_MT_WT 4
1659	/** Write-protected. */
1660	#define MSR_IA32_PAT_MT_WP 5
1661	/** Writeback. */
1662	#define MSR_IA32_PAT_MT_WB 6
1663	/** Uncached (UC-). */
1664	#define MSR_IA32_PAT_MT_UCD 7
1665	/** @}*/
1666
1667
1668	/** Performance event select MSRs. (Intel only) */
1669	#define MSR_IA32_PERFEVTSEL0 0x186
1670	#define MSR_IA32_PERFEVTSEL1 0x187
1671	#define MSR_IA32_PERFEVTSEL2 0x188
1672	#define MSR_IA32_PERFEVTSEL3 0x189
1673
1674	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1675	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1676	* holds a ratio that Apple takes for TSC granularity.
1677	*
1678	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1679	#define MSR_FLEX_RATIO 0x194
1680	/** Performance state value and starting with Intel core more.
1681	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1682	#define MSR_IA32_PERF_STATUS 0x198
1683	#define MSR_IA32_PERF_CTL 0x199
1684	#define MSR_IA32_THERM_STATUS 0x19c
1685
1686	/** Offcore response event select registers. */
1687	#define MSR_OFFCORE_RSP_0 0x1a6
1688	#define MSR_OFFCORE_RSP_1 0x1a7
1689
1690	/** Enable misc. processor features (R/W). */
1691	#define MSR_IA32_MISC_ENABLE 0x1A0
1692	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1693	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1694	/** Automatic Thermal Control Circuit Enable (R/W). */
1695	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1696	/** Performance Monitoring Available (R). */
1697	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1698	/** Branch Trace Storage Unavailable (R/O). */
1699	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1700	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1701	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1702	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1703	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1704	/** If MONITOR/MWAIT is supported (R/W). */
1705	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1706	/** Limit CPUID Maxval to 3 leafs (R/W). */
1707	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1708	/** When set to 1, xTPR messages are disabled (R/W). */
1709	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1710	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1711	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1712
1713	/** Trace/Profile Resource Control (R/W) */
1714	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1715	/** Last branch record. */
1716	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1717	/** Branch trace flag (single step on branches). */
1718	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1719	/** Performance monitoring pin control (AMD only). */
1720	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1721	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1722	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1723	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1724	/** Trace message enable (Intel only). */
1725	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1726	/** Branch trace store (Intel only). */
1727	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1728	/** Branch trace interrupt (Intel only). */
1729	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1730	/** Branch trace off in privileged code (Intel only). */
1731	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1732	/** Branch trace off in user code (Intel only). */
1733	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1734	/** Freeze LBR on PMI flag (Intel only). */
1735	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1736	/** Freeze PERFMON on PMI flag (Intel only). */
1737	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1738	/** Freeze while SMM enabled (Intel only). */
1739	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1740	/** Advanced debugging of RTM regions (Intel only). */
1741	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1742	/** Debug control MSR valid bits (Intel only). */
1743	#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR \| MSR_IA32_DEBUGCTL_BTF \| MSR_IA32_DEBUGCTL_TR \
1744	\| MSR_IA32_DEBUGCTL_BTS \| MSR_IA32_DEBUGCTL_BTINT \| MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1745	\| MSR_IA32_DEBUGCTL_BTS_OFF_USER \| MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1746	\| MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI \| MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1747	\| MSR_IA32_DEBUGCTL_RTM)
1748
1749	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1750	* @{ */
1751	#define MSR_P4_LASTBRANCH_0 0x1db
1752	#define MSR_P4_LASTBRANCH_1 0x1dc
1753	#define MSR_P4_LASTBRANCH_2 0x1dd
1754	#define MSR_P4_LASTBRANCH_3 0x1de
1755
1756	/** LBR Top-of-stack MSR (index to most recent record). */
1757	#define MSR_P4_LASTBRANCH_TOS 0x1da
1758	/** @} */
1759
1760	/** @name Last branch registers for Core 2 and related Xeons.
1761	* @{ */
1762	#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1763	#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1764	#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1765	#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1766
1767	#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1768	#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1769	#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1770	#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1771
1772	/** LBR Top-of-stack MSR (index to most recent record). */
1773	#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1774	/** @} */
1775
1776	/** @name Last branch registers.
1777	* @{ */
1778	#define MSR_LASTBRANCH_0_FROM_IP 0x680
1779	#define MSR_LASTBRANCH_1_FROM_IP 0x681
1780	#define MSR_LASTBRANCH_2_FROM_IP 0x682
1781	#define MSR_LASTBRANCH_3_FROM_IP 0x683
1782	#define MSR_LASTBRANCH_4_FROM_IP 0x684
1783	#define MSR_LASTBRANCH_5_FROM_IP 0x685
1784	#define MSR_LASTBRANCH_6_FROM_IP 0x686
1785	#define MSR_LASTBRANCH_7_FROM_IP 0x687
1786	#define MSR_LASTBRANCH_8_FROM_IP 0x688
1787	#define MSR_LASTBRANCH_9_FROM_IP 0x689
1788	#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1789	#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1790	#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1791	#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1792	#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1793	#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1794	#define MSR_LASTBRANCH_16_FROM_IP 0x690
1795	#define MSR_LASTBRANCH_17_FROM_IP 0x691
1796	#define MSR_LASTBRANCH_18_FROM_IP 0x692
1797	#define MSR_LASTBRANCH_19_FROM_IP 0x693
1798	#define MSR_LASTBRANCH_20_FROM_IP 0x694
1799	#define MSR_LASTBRANCH_21_FROM_IP 0x695
1800	#define MSR_LASTBRANCH_22_FROM_IP 0x696
1801	#define MSR_LASTBRANCH_23_FROM_IP 0x697
1802	#define MSR_LASTBRANCH_24_FROM_IP 0x698
1803	#define MSR_LASTBRANCH_25_FROM_IP 0x699
1804	#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1805	#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1806	#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1807	#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1808	#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1809	#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1810
1811	#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1812	#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1813	#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1814	#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1815	#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1816	#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1817	#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1818	#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1819	#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1820	#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1821	#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1822	#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1823	#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1824	#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1825	#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1826	#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1827	#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1828	#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1829	#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1830	#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1831	#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1832	#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1833	#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1834	#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1835	#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1836	#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1837	#define MSR_LASTBRANCH_26_TO_IP 0x6da
1838	#define MSR_LASTBRANCH_27_TO_IP 0x6db
1839	#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1840	#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1841	#define MSR_LASTBRANCH_30_TO_IP 0x6de
1842	#define MSR_LASTBRANCH_31_TO_IP 0x6df
1843
1844	#define MSR_LASTBRANCH_0_INFO 0xdc0
1845	#define MSR_LASTBRANCH_1_INFO 0xdc1
1846	#define MSR_LASTBRANCH_2_INFO 0xdc2
1847	#define MSR_LASTBRANCH_3_INFO 0xdc3
1848	#define MSR_LASTBRANCH_4_INFO 0xdc4
1849	#define MSR_LASTBRANCH_5_INFO 0xdc5
1850	#define MSR_LASTBRANCH_6_INFO 0xdc6
1851	#define MSR_LASTBRANCH_7_INFO 0xdc7
1852	#define MSR_LASTBRANCH_8_INFO 0xdc8
1853	#define MSR_LASTBRANCH_9_INFO 0xdc9
1854	#define MSR_LASTBRANCH_10_INFO 0xdca
1855	#define MSR_LASTBRANCH_11_INFO 0xdcb
1856	#define MSR_LASTBRANCH_12_INFO 0xdcc
1857	#define MSR_LASTBRANCH_13_INFO 0xdcd
1858	#define MSR_LASTBRANCH_14_INFO 0xdce
1859	#define MSR_LASTBRANCH_15_INFO 0xdcf
1860	#define MSR_LASTBRANCH_16_INFO 0xdd0
1861	#define MSR_LASTBRANCH_17_INFO 0xdd1
1862	#define MSR_LASTBRANCH_18_INFO 0xdd2
1863	#define MSR_LASTBRANCH_19_INFO 0xdd3
1864	#define MSR_LASTBRANCH_20_INFO 0xdd4
1865	#define MSR_LASTBRANCH_21_INFO 0xdd5
1866	#define MSR_LASTBRANCH_22_INFO 0xdd6
1867	#define MSR_LASTBRANCH_23_INFO 0xdd7
1868	#define MSR_LASTBRANCH_24_INFO 0xdd8
1869	#define MSR_LASTBRANCH_25_INFO 0xdd9
1870	#define MSR_LASTBRANCH_26_INFO 0xdda
1871	#define MSR_LASTBRANCH_27_INFO 0xddb
1872	#define MSR_LASTBRANCH_28_INFO 0xddc
1873	#define MSR_LASTBRANCH_29_INFO 0xddd
1874	#define MSR_LASTBRANCH_30_INFO 0xdde
1875	#define MSR_LASTBRANCH_31_INFO 0xddf
1876
1877	/** LBR branch tracking selection MSR. */
1878	#define MSR_LASTBRANCH_SELECT 0x1c8
1879	/** LBR Top-of-stack MSR (index to most recent record). */
1880	#define MSR_LASTBRANCH_TOS 0x1c9
1881	/** @} */
1882
1883	/** @name Last event record registers.
1884	* @{ */
1885	/** Last event record source IP register. */
1886	#define MSR_LER_FROM_IP 0x1dd
1887	/** Last event record destination IP register. */
1888	#define MSR_LER_TO_IP 0x1de
1889	/** @} */
1890
1891	/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1892	#define MSR_IA32_TSX_CTRL 0x122
1893
1894	/** Variable range MTRRs.
1895	* @{ */
1896	#define MSR_IA32_MTRR_PHYSBASE0 0x200
1897	#define MSR_IA32_MTRR_PHYSMASK0 0x201
1898	#define MSR_IA32_MTRR_PHYSBASE1 0x202
1899	#define MSR_IA32_MTRR_PHYSMASK1 0x203
1900	#define MSR_IA32_MTRR_PHYSBASE2 0x204
1901	#define MSR_IA32_MTRR_PHYSMASK2 0x205
1902	#define MSR_IA32_MTRR_PHYSBASE3 0x206
1903	#define MSR_IA32_MTRR_PHYSMASK3 0x207
1904	#define MSR_IA32_MTRR_PHYSBASE4 0x208
1905	#define MSR_IA32_MTRR_PHYSMASK4 0x209
1906	#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1907	#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1908	#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1909	#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1910	#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1911	#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1912	#define MSR_IA32_MTRR_PHYSBASE8 0x210
1913	#define MSR_IA32_MTRR_PHYSMASK8 0x211
1914	#define MSR_IA32_MTRR_PHYSBASE9 0x212
1915	#define MSR_IA32_MTRR_PHYSMASK9 0x213
1916	/** @} */
1917
1918	/** Fixed range MTRRs.
1919	* @{ */
1920	#define MSR_IA32_MTRR_FIX64K_00000 0x250
1921	#define MSR_IA32_MTRR_FIX16K_80000 0x258
1922	#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1923	#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1924	#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1925	#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1926	#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1927	#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1928	#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1929	#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1930	#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1931	/** @} */
1932
1933	/** MTRR Default Type.
1934	* @{ */
1935	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1936	#define MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK 0xFF
1937	#define MSR_IA32_MTRR_DEF_TYPE_FIXED_EN RT_BIT_64(10)
1938	#define MSR_IA32_MTRR_DEF_TYPE_MTRR_EN RT_BIT_64(11)
1939	#define MSR_IA32_MTRR_DEF_TYPE_VALID_MASK ( MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK \
1940	\| MSR_IA32_MTRR_DEF_TYPE_FIXED_EN \
1941	\| MSR_IA32_MTRR_DEF_TYPE_MTRR_EN)
1942	/** @} */
1943
1944	/** Variable-range MTRR physical mask valid. */
1945	#define MSR_IA32_MTRR_PHYSMASK_VALID RT_BIT_64(11)
1946
1947	/** Variable-range MTRR memory type mask. */
1948	#define MSR_IA32_MTRR_PHYSBASE_MT_MASK UINT64_C(0xff)
1949
1950	/** Global performance counter control facilities (Intel only). */
1951	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1952	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1953	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1954
1955	/** Precise Event Based sampling (Intel only). */
1956	#define MSR_IA32_PEBS_ENABLE 0x3F1
1957
1958	#define MSR_IA32_MC0_CTL 0x400
1959	#define MSR_IA32_MC0_STATUS 0x401
1960
1961	/** Basic VMX information. */
1962	#define MSR_IA32_VMX_BASIC 0x480
1963	/** Allowed settings for pin-based VM execution controls. */
1964	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1965	/** Allowed settings for proc-based VM execution controls. */
1966	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1967	/** Allowed settings for the VM-exit controls. */
1968	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1969	/** Allowed settings for the VM-entry controls. */
1970	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1971	/** Misc VMX info. */
1972	#define MSR_IA32_VMX_MISC 0x485
1973	/** Fixed cleared bits in CR0. */
1974	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1975	/** Fixed set bits in CR0. */
1976	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1977	/** Fixed cleared bits in CR4. */
1978	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1979	/** Fixed set bits in CR4. */
1980	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1981	/** Information for enumerating fields in the VMCS. */
1982	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1983	/** Allowed settings for secondary processor-based VM-execution controls. */
1984	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1985	/** EPT capabilities. */
1986	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1987	/** Allowed settings of all pin-based VM execution controls. */
1988	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1989	/** Allowed settings of all proc-based VM execution controls. */
1990	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1991	/** Allowed settings of all VMX exit controls. */
1992	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1993	/** Allowed settings of all VMX entry controls. */
1994	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1995	/** Allowed settings for the VM-function controls. */
1996	#define MSR_IA32_VMX_VMFUNC 0x491
1997	/** Tertiary processor-based VM execution controls. */
1998	#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
1999	/** Secondary VM-exit controls. */
2000	#define MSR_IA32_VMX_EXIT_CTLS2 0x493
2001
2002	/** Intel PT - Enable and control for trace packet generation. */
2003	#define MSR_IA32_RTIT_CTL 0x570
2004
2005	/** DS Save Area (R/W). */
2006	#define MSR_IA32_DS_AREA 0x600
2007	/** Running Average Power Limit (RAPL) power units. */
2008	#define MSR_RAPL_POWER_UNIT 0x606
2009	/** Package C3 Interrupt Response Limit. */
2010	#define MSR_PKGC3_IRTL 0x60a
2011	/** Package C6/C7S Interrupt Response Limit 1. */
2012	#define MSR_PKGC_IRTL1 0x60b
2013	/** Package C6/C7S Interrupt Response Limit 2. */
2014	#define MSR_PKGC_IRTL2 0x60c
2015	/** Package C2 Residency Counter. */
2016	#define MSR_PKG_C2_RESIDENCY 0x60d
2017	/** PKG RAPL Power Limit Control. */
2018	#define MSR_PKG_POWER_LIMIT 0x610
2019	/** PKG Energy Status. */
2020	#define MSR_PKG_ENERGY_STATUS 0x611
2021	/** PKG Perf Status. */
2022	#define MSR_PKG_PERF_STATUS 0x613
2023	/** PKG RAPL Parameters. */
2024	#define MSR_PKG_POWER_INFO 0x614
2025	/** DRAM RAPL Power Limit Control. */
2026	#define MSR_DRAM_POWER_LIMIT 0x618
2027	/** DRAM Energy Status. */
2028	#define MSR_DRAM_ENERGY_STATUS 0x619
2029	/** DRAM Performance Throttling Status. */
2030	#define MSR_DRAM_PERF_STATUS 0x61b
2031	/** DRAM RAPL Parameters. */
2032	#define MSR_DRAM_POWER_INFO 0x61c
2033	/** Package C10 Residency Counter. */
2034	#define MSR_PKG_C10_RESIDENCY 0x632
2035	/** PP0 Energy Status. */
2036	#define MSR_PP0_ENERGY_STATUS 0x639
2037	/** PP1 Energy Status. */
2038	#define MSR_PP1_ENERGY_STATUS 0x641
2039	/** Turbo Activation Ratio. */
2040	#define MSR_TURBO_ACTIVATION_RATIO 0x64c
2041	/** Core Performance Limit Reasons. */
2042	#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
2043
2044	/** Userspace Control flow Enforcement Technology setting. */
2045	#define MSR_IA32_U_CET 0x6a0
2046	/** Supervisor space Control flow Enforcement Technology setting. */
2047	#define MSR_IA32_S_CET 0x6a2
2048	/** @name Bit fields for both MSR_IA32_U_CET and MSR_IA32_S_CET
2049	* @{ */
2050	/** Enables the Shadow stack. */
2051	# define MSR_IA32_CET_SH_STK_EN RT_BIT_64(0)
2052	/** Enables WRSS{D,Q}W instructions. */
2053	# define MSR_IA32_CET_WR_SHSTK_EN RT_BIT_64(1)
2054	/** Enables indirect branch tracking. */
2055	# define MSR_IA32_CET_ENDBR_EN RT_BIT_64(2)
2056	/** Enable legacy compatibility treatment for indirect branch tracking. */
2057	# define MSR_IA32_CET_LEG_IW_EN RT_BIT_64(3)
2058	/** Enables the use of no-track prefix for indirect branch tracking. */
2059	# define MSR_IA32_CET_NO_TRACK_EN RT_BIT_64(4)
2060	/** Disables suppression of CET indirect branch tracking on legacy compatibility. */
2061	# define MSR_IA32_CET_SUPPRESS_DIS RT_BIT_64(5)
2062	/** Suppresses indirect branch tracking. */
2063	# define MSR_IA32_CET_SUPPRESS RT_BIT_64(10)
2064	/** Returns the value of the indirect branch tracking state machine: IDLE(0), WAIT_FOR_ENDBRANCH(1). */
2065	# define MSR_IA32_CET_TRACKER RT_BIT_64(11)
2066	/** Linear address of memory containing a bitmap indicating valid pages as CALL/JMP targets not landing
2067	* on a ENDBRANCH instruction. */
2068	# define MSR_IA32_CET_EB_LEG_BITMAP_BASE UINT64_C(0xfffffffffffff000)
2069	/** @} */
2070
2071	/** X2APIC MSR range start. */
2072	#define MSR_IA32_X2APIC_START 0x800
2073	/** X2APIC MSR - APIC ID Register. */
2074	#define MSR_IA32_X2APIC_ID 0x802
2075	/** X2APIC MSR - APIC Version Register. */
2076	#define MSR_IA32_X2APIC_VERSION 0x803
2077	/** X2APIC MSR - Task Priority Register. */
2078	#define MSR_IA32_X2APIC_TPR 0x808
2079	/** X2APIC MSR - Processor Priority register. */
2080	#define MSR_IA32_X2APIC_PPR 0x80A
2081	/** X2APIC MSR - End Of Interrupt register. */
2082	#define MSR_IA32_X2APIC_EOI 0x80B
2083	/** X2APIC MSR - Logical Destination Register. */
2084	#define MSR_IA32_X2APIC_LDR 0x80D
2085	/** X2APIC MSR - Spurious Interrupt Vector Register. */
2086	#define MSR_IA32_X2APIC_SVR 0x80F
2087	/** X2APIC MSR - In-service Register (bits 31:0). */
2088	#define MSR_IA32_X2APIC_ISR0 0x810
2089	/** X2APIC MSR - In-service Register (bits 63:32). */
2090	#define MSR_IA32_X2APIC_ISR1 0x811
2091	/** X2APIC MSR - In-service Register (bits 95:64). */
2092	#define MSR_IA32_X2APIC_ISR2 0x812
2093	/** X2APIC MSR - In-service Register (bits 127:96). */
2094	#define MSR_IA32_X2APIC_ISR3 0x813
2095	/** X2APIC MSR - In-service Register (bits 159:128). */
2096	#define MSR_IA32_X2APIC_ISR4 0x814
2097	/** X2APIC MSR - In-service Register (bits 191:160). */
2098	#define MSR_IA32_X2APIC_ISR5 0x815
2099	/** X2APIC MSR - In-service Register (bits 223:192). */
2100	#define MSR_IA32_X2APIC_ISR6 0x816
2101	/** X2APIC MSR - In-service Register (bits 255:224). */
2102	#define MSR_IA32_X2APIC_ISR7 0x817
2103	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
2104	#define MSR_IA32_X2APIC_TMR0 0x818
2105	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
2106	#define MSR_IA32_X2APIC_TMR1 0x819
2107	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
2108	#define MSR_IA32_X2APIC_TMR2 0x81A
2109	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
2110	#define MSR_IA32_X2APIC_TMR3 0x81B
2111	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
2112	#define MSR_IA32_X2APIC_TMR4 0x81C
2113	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
2114	#define MSR_IA32_X2APIC_TMR5 0x81D
2115	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
2116	#define MSR_IA32_X2APIC_TMR6 0x81E
2117	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
2118	#define MSR_IA32_X2APIC_TMR7 0x81F
2119	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
2120	#define MSR_IA32_X2APIC_IRR0 0x820
2121	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
2122	#define MSR_IA32_X2APIC_IRR1 0x821
2123	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
2124	#define MSR_IA32_X2APIC_IRR2 0x822
2125	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
2126	#define MSR_IA32_X2APIC_IRR3 0x823
2127	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
2128	#define MSR_IA32_X2APIC_IRR4 0x824
2129	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
2130	#define MSR_IA32_X2APIC_IRR5 0x825
2131	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
2132	#define MSR_IA32_X2APIC_IRR6 0x826
2133	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
2134	#define MSR_IA32_X2APIC_IRR7 0x827
2135	/** X2APIC MSR - Error Status Register. */
2136	#define MSR_IA32_X2APIC_ESR 0x828
2137	/** X2APIC MSR - LVT CMCI Register. */
2138	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
2139	/** X2APIC MSR - Interrupt Command Register. */
2140	#define MSR_IA32_X2APIC_ICR 0x830
2141	/** X2APIC MSR - LVT Timer Register. */
2142	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
2143	/** X2APIC MSR - LVT Thermal Sensor Register. */
2144	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
2145	/** X2APIC MSR - LVT Performance Counter Register. */
2146	#define MSR_IA32_X2APIC_LVT_PERF 0x834
2147	/** X2APIC MSR - LVT LINT0 Register. */
2148	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
2149	/** X2APIC MSR - LVT LINT1 Register. */
2150	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
2151	/** X2APIC MSR - LVT Error Register . */
2152	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
2153	/** X2APIC MSR - Timer Initial Count Register. */
2154	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
2155	/** X2APIC MSR - Timer Current Count Register. */
2156	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
2157	/** X2APIC MSR - Timer Divide Configuration Register. */
2158	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
2159	/** X2APIC MSR - Self IPI. */
2160	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
2161	/** X2APIC MSR range end. */
2162	#define MSR_IA32_X2APIC_END 0x8FF
2163	/** X2APIC MSR - LVT start range. */
2164	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
2165	/** X2APIC MSR - LVT end range (inclusive). */
2166	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
2167
2168	/** K6 EFER - Extended Feature Enable Register. */
2169	#define MSR_K6_EFER UINT32_C(0xc0000080)
2170	/** @todo document EFER */
2171	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
2172	#define MSR_K6_EFER_SCE RT_BIT_32(0)
2173	/** Bit 8 - LME - Long mode enabled. (R/W) */
2174	#define MSR_K6_EFER_LME RT_BIT_32(8)
2175	#define MSR_K6_EFER_BIT_LME 8 /*< Bit number of MSR_K6_EFER_LME /
2176	/** Bit 10 - LMA - Long mode active. (R) */
2177	#define MSR_K6_EFER_LMA RT_BIT_32(10)
2178	#define MSR_K6_EFER_BIT_LMA 10 /*< Bit number of MSR_K6_EFER_LMA /
2179	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
2180	#define MSR_K6_EFER_NXE RT_BIT_32(11)
2181	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
2182	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
2183	#define MSR_K6_EFER_SVME RT_BIT_32(12)
2184	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
2185	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
2186	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
2187	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
2188	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
2189	#define MSR_K6_EFER_TCE RT_BIT_32(15)
2190	/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
2191	#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
2192
2193	/** K6 STAR - SYSCALL/RET targets. */
2194	#define MSR_K6_STAR UINT32_C(0xc0000081)
2195	/** Shift value for getting the SYSRET CS and SS value. */
2196	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
2197	/** Shift value for getting the SYSCALL CS and SS value. */
2198	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
2199	/** Selector mask for use after shifting. */
2200	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
2201	/** The mask which give the SYSCALL EIP. */
2202	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
2203	/** K6 WHCR - Write Handling Control Register. */
2204	#define MSR_K6_WHCR UINT32_C(0xc0000082)
2205	/** K6 UWCCR - UC/WC Cacheability Control Register. */
2206	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
2207	/** K6 PSOR - Processor State Observability Register. */
2208	#define MSR_K6_PSOR UINT32_C(0xc0000087)
2209	/** K6 PFIR - Page Flush/Invalidate Register. */
2210	#define MSR_K6_PFIR UINT32_C(0xc0000088)
2211
2212	/** Performance counter MSRs. (AMD only) */
2213	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
2214	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
2215	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
2216	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
2217	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
2218	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
2219	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
2220	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
2221
2222	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
2223	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
2224	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
2225	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
2226	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
2227	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
2228	/** K8 FS.base - The 64-bit base FS register. */
2229	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
2230	/** K8 GS.base - The 64-bit base GS register. */
2231	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
2232	/** K8 KernelGSbase - Used with SWAPGS. */
2233	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
2234	/** K8 TSC_AUX - Used with RDTSCP. */
2235	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
2236	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
2237	#define MSR_K8_HWCR UINT32_C(0xc0010015)
2238	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
2239	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
2240	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
2241	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
2242	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
2243	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
2244
2245	/** SMM MSRs. */
2246	#define MSR_K7_SMBASE UINT32_C(0xc0010111)
2247	#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
2248	#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
2249
2250	/** North bridge config? See BIOS & Kernel dev guides for
2251	* details. */
2252	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
2253
2254	/** Hypertransport interrupt pending register.
2255	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
2256	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
2257
2258	/** SVM Control. */
2259	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
2260	/** Disables HDT (Hardware Debug Tool) and certain internal debug
2261	* features. */
2262	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
2263	/** If set, non-intercepted INIT signals are converted to \#SX
2264	* exceptions. */
2265	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
2266	/** Disables A20 masking. */
2267	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
2268	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
2269	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
2270	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
2271	* clear, EFER.SVME can be written normally. */
2272	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
2273
2274	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
2275	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
2276	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
2277	* host state during world switch. */
2278	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
2279
2280	/** Virtualized speculation control for AMD processors.
2281	*
2282	* Unified interface among different CPU generations.
2283	* The VMM will set any architectural MSRs based on the CPU.
2284	* See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
2285	* (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
2286	#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
2287	/** Speculative Store Bypass Disable. */
2288	# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
2289
2290	/** @} */
2291
2292
2293	/** @name Page Table / Directory / Directory Pointers / L4.
2294	* @{
2295	*/
2296
2297	#ifndef __ASSEMBLER__
2298	/** Page table/directory entry as an unsigned integer. */
2299	typedef uint32_t X86PGUINT;
2300	/** Pointer to a page table/directory table entry as an unsigned integer. */
2301	typedef X86PGUINT *PX86PGUINT;
2302	/** Pointer to an const page table/directory table entry as an unsigned integer. */
2303	typedef X86PGUINT const *PCX86PGUINT;
2304	#endif
2305
2306	/** Number of entries in a 32-bit PT/PD. */
2307	#define X86_PG_ENTRIES 1024
2308
2309
2310	#ifndef __ASSEMBLER__
2311	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2312	typedef uint64_t X86PGPAEUINT;
2313	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2314	typedef X86PGPAEUINT *PX86PGPAEUINT;
2315	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2316	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
2317	#endif
2318
2319	/** Number of entries in a PAE PT/PD. */
2320	#define X86_PG_PAE_ENTRIES 512
2321	/** Number of entries in a PAE PDPT. */
2322	#define X86_PG_PAE_PDPE_ENTRIES 4
2323
2324	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
2325	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
2326	/** Number of entries in an AMD64 PDPT.
2327	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
2328	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
2329
2330	/** The size of a default page. */
2331	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
2332	/** The page shift of a default page. */
2333	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
2334	/** The default page offset mask. */
2335	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
2336	/** The default page base mask for virtual addresses. */
2337	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
2338	/** The default page base mask for virtual addresses - 32bit version. */
2339	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
2340
2341	/** The size of a 4KB page. */
2342	#define X86_PAGE_4K_SIZE _4K
2343	/** The page shift of a 4KB page. */
2344	#define X86_PAGE_4K_SHIFT 12
2345	/** The 4KB page offset mask. */
2346	#define X86_PAGE_4K_OFFSET_MASK 0xfff
2347	/** The 4KB page base mask for virtual addresses. */
2348	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
2349	/** The 4KB page base mask for virtual addresses - 32bit version. */
2350	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
2351
2352	/** The size of a 2MB page. */
2353	#define X86_PAGE_2M_SIZE _2M
2354	/** The page shift of a 2MB page. */
2355	#define X86_PAGE_2M_SHIFT 21
2356	/** The 2MB page offset mask. */
2357	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
2358	/** The 2MB page base mask for virtual addresses. */
2359	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
2360	/** The 2MB page base mask for virtual addresses - 32bit version. */
2361	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
2362
2363	/** The size of a 4MB page. */
2364	#define X86_PAGE_4M_SIZE _4M
2365	/** The page shift of a 4MB page. */
2366	#define X86_PAGE_4M_SHIFT 22
2367	/** The 4MB page offset mask. */
2368	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
2369	/** The 4MB page base mask for virtual addresses. */
2370	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
2371	/** The 4MB page base mask for virtual addresses - 32bit version. */
2372	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
2373
2374	/** The size of a 1GB page. */
2375	#define X86_PAGE_1G_SIZE _1G
2376	/** The page shift of a 1GB page. */
2377	#define X86_PAGE_1G_SHIFT 30
2378	/** The 1GB page offset mask. */
2379	#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
2380	/** The 1GB page base mask for virtual addresses. */
2381	#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
2382
2383	/**
2384	* Check if the given address is canonical.
2385	*/
2386	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
2387
2388	/**
2389	* Gets the page base mask given the page shift.
2390	*/
2391	#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
2392
2393	/**
2394	* Gets the page offset mask given the page shift.
2395	*/
2396	#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
2397
2398
2399	/** @name Page Table Entry
2400	* @{
2401	*/
2402	/** Bit 0 - P - Present bit. */
2403	#define X86_PTE_BIT_P 0
2404	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2405	#define X86_PTE_BIT_RW 1
2406	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2407	#define X86_PTE_BIT_US 2
2408	/** Bit 3 - PWT - Page level write thru bit. */
2409	#define X86_PTE_BIT_PWT 3
2410	/** Bit 4 - PCD - Page level cache disable bit. */
2411	#define X86_PTE_BIT_PCD 4
2412	/** Bit 5 - A - Access bit. */
2413	#define X86_PTE_BIT_A 5
2414	/** Bit 6 - D - Dirty bit. */
2415	#define X86_PTE_BIT_D 6
2416	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2417	#define X86_PTE_BIT_PAT 7
2418	/** Bit 8 - G - Global flag. */
2419	#define X86_PTE_BIT_G 8
2420	/** Bits 63 - NX - PAE/LM - No execution flag. */
2421	#define X86_PTE_PAE_BIT_NX 63
2422
2423	/** Bit 0 - P - Present bit mask. */
2424	#define X86_PTE_P RT_BIT_32(0)
2425	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2426	#define X86_PTE_RW RT_BIT_32(1)
2427	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2428	#define X86_PTE_US RT_BIT_32(2)
2429	/** Bit 3 - PWT - Page level write thru bit mask. */
2430	#define X86_PTE_PWT RT_BIT_32(3)
2431	/** Bit 4 - PCD - Page level cache disable bit mask. */
2432	#define X86_PTE_PCD RT_BIT_32(4)
2433	/** Bit 5 - A - Access bit mask. */
2434	#define X86_PTE_A RT_BIT_32(5)
2435	/** Bit 6 - D - Dirty bit mask. */
2436	#define X86_PTE_D RT_BIT_32(6)
2437	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2438	#define X86_PTE_PAT RT_BIT_32(7)
2439	/** Bit 8 - G - Global bit mask. */
2440	#define X86_PTE_G RT_BIT_32(8)
2441
2442	/** Bits 9-11 - - Available for use to system software. */
2443	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2444	/** Bits 12-31 - - Physical Page number of the next level. */
2445	#define X86_PTE_PG_MASK ( 0xfffff000 )
2446
2447	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2448	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2449	/** Bits 63 - NX - PAE/LM - No execution flag. */
2450	#define X86_PTE_PAE_NX RT_BIT_64(63)
2451	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2452	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2453	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2454	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2455	/** No bits - - LM - MBZ bits when NX is active. */
2456	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2457	/** Bits 63 - - LM - MBZ bits when no NX. */
2458	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2459
2460	#ifndef __ASSEMBLER__
2461
2462	/**
2463	* Page table entry.
2464	*/
2465	typedef struct X86PTEBITS
2466	{
2467	/** Flags whether(=1) or not the page is present. */
2468	uint32_t u1Present : 1;
2469	/** Read(=0) / Write(=1) flag. */
2470	uint32_t u1Write : 1;
2471	/** User(=1) / Supervisor (=0) flag. */
2472	uint32_t u1User : 1;
2473	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2474	uint32_t u1WriteThru : 1;
2475	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2476	uint32_t u1CacheDisable : 1;
2477	/** Accessed flag.
2478	* Indicates that the page have been read or written to. */
2479	uint32_t u1Accessed : 1;
2480	/** Dirty flag.
2481	* Indicates that the page has been written to. */
2482	uint32_t u1Dirty : 1;
2483	/** Reserved / If PAT enabled, bit 2 of the index. */
2484	uint32_t u1PAT : 1;
2485	/** Global flag. (Ignored in all but final level.) */
2486	uint32_t u1Global : 1;
2487	/** Available for use to system software. */
2488	uint32_t u3Available : 3;
2489	/** Physical Page number of the next level. */
2490	uint32_t u20PageNo : 20;
2491	} X86PTEBITS;
2492	# ifndef VBOX_FOR_DTRACE_LIB
2493	AssertCompileSize(X86PTEBITS, 4);
2494	# endif
2495	/** Pointer to a page table entry. */
2496	typedef X86PTEBITS *PX86PTEBITS;
2497	/** Pointer to a const page table entry. */
2498	typedef const X86PTEBITS *PCX86PTEBITS;
2499
2500	/**
2501	* Page table entry.
2502	*/
2503	typedef union X86PTE
2504	{
2505	/** Unsigned integer view */
2506	X86PGUINT u;
2507	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2508	/** Bit field view. */
2509	X86PTEBITS n;
2510	# endif
2511	/** 32-bit view. */
2512	uint32_t au32[1];
2513	/** 16-bit view. */
2514	uint16_t au16[2];
2515	/** 8-bit view. */
2516	uint8_t au8[4];
2517	} X86PTE;
2518	# ifndef VBOX_FOR_DTRACE_LIB
2519	AssertCompileSize(X86PTE, 4);
2520	# endif
2521	/** Pointer to a page table entry. */
2522	typedef X86PTE *PX86PTE;
2523	/** Pointer to a const page table entry. */
2524	typedef const X86PTE *PCX86PTE;
2525
2526
2527	/**
2528	* PAE page table entry.
2529	*/
2530	typedef struct X86PTEPAEBITS
2531	{
2532	/** Flags whether(=1) or not the page is present. */
2533	uint32_t u1Present : 1;
2534	/** Read(=0) / Write(=1) flag. */
2535	uint32_t u1Write : 1;
2536	/** User(=1) / Supervisor(=0) flag. */
2537	uint32_t u1User : 1;
2538	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2539	uint32_t u1WriteThru : 1;
2540	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2541	uint32_t u1CacheDisable : 1;
2542	/** Accessed flag.
2543	* Indicates that the page have been read or written to. */
2544	uint32_t u1Accessed : 1;
2545	/** Dirty flag.
2546	* Indicates that the page has been written to. */
2547	uint32_t u1Dirty : 1;
2548	/** Reserved / If PAT enabled, bit 2 of the index. */
2549	uint32_t u1PAT : 1;
2550	/** Global flag. (Ignored in all but final level.) */
2551	uint32_t u1Global : 1;
2552	/** Available for use to system software. */
2553	uint32_t u3Available : 3;
2554	/** Physical Page number of the next level - Low Part. Don't use this. */
2555	uint32_t u20PageNoLow : 20;
2556	/** Physical Page number of the next level - High Part. Don't use this. */
2557	uint32_t u20PageNoHigh : 20;
2558	/** MBZ bits */
2559	uint32_t u11Reserved : 11;
2560	/** No Execute flag. */
2561	uint32_t u1NoExecute : 1;
2562	} X86PTEPAEBITS;
2563	# ifndef VBOX_FOR_DTRACE_LIB
2564	AssertCompileSize(X86PTEPAEBITS, 8);
2565	# endif
2566	/** Pointer to a page table entry. */
2567	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2568	/** Pointer to a page table entry. */
2569	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2570
2571	/**
2572	* PAE Page table entry.
2573	*/
2574	typedef union X86PTEPAE
2575	{
2576	/** Unsigned integer view */
2577	X86PGPAEUINT u;
2578	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2579	/** Bit field view. */
2580	X86PTEPAEBITS n;
2581	# endif
2582	/** 32-bit view. */
2583	uint32_t au32[2];
2584	/** 16-bit view. */
2585	uint16_t au16[4];
2586	/** 8-bit view. */
2587	uint8_t au8[8];
2588	} X86PTEPAE;
2589	# ifndef VBOX_FOR_DTRACE_LIB
2590	AssertCompileSize(X86PTEPAE, 8);
2591	# endif
2592	/** Pointer to a PAE page table entry. */
2593	typedef X86PTEPAE *PX86PTEPAE;
2594	/** Pointer to a const PAE page table entry. */
2595	typedef const X86PTEPAE *PCX86PTEPAE;
2596	/** @} */
2597
2598	/**
2599	* Page table.
2600	*/
2601	typedef struct X86PT
2602	{
2603	/** PTE Array. */
2604	X86PTE a[X86_PG_ENTRIES];
2605	} X86PT;
2606	# ifndef VBOX_FOR_DTRACE_LIB
2607	AssertCompileSize(X86PT, 4096);
2608	# endif
2609	/** Pointer to a page table. */
2610	typedef X86PT *PX86PT;
2611	/** Pointer to a const page table. */
2612	typedef const X86PT *PCX86PT;
2613
2614	#endif /* !__ASSEMBLER__ */
2615
2616	/** The page shift to get the PT index. */
2617	#define X86_PT_SHIFT 12
2618	/** The PT index mask (apply to a shifted page address). */
2619	#define X86_PT_MASK 0x3ff
2620
2621
2622	#ifndef __ASSEMBLER__
2623	/**
2624	* Page directory.
2625	*/
2626	typedef struct X86PTPAE
2627	{
2628	/** PTE Array. */
2629	X86PTEPAE a[X86_PG_PAE_ENTRIES];
2630	} X86PTPAE;
2631	# ifndef VBOX_FOR_DTRACE_LIB
2632	AssertCompileSize(X86PTPAE, 4096);
2633	# endif
2634	/** Pointer to a page table. */
2635	typedef X86PTPAE *PX86PTPAE;
2636	/** Pointer to a const page table. */
2637	typedef const X86PTPAE *PCX86PTPAE;
2638	#endif /* !__ASSEMBLY__ */
2639
2640	/** The page shift to get the PA PTE index. */
2641	#define X86_PT_PAE_SHIFT 12
2642	/** The PAE PT index mask (apply to a shifted page address). */
2643	#define X86_PT_PAE_MASK 0x1ff
2644
2645
2646	/** @name 4KB Page Directory Entry
2647	* @{
2648	*/
2649	/** Bit 0 - P - Present bit. */
2650	#define X86_PDE_P RT_BIT_32(0)
2651	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2652	#define X86_PDE_RW RT_BIT_32(1)
2653	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2654	#define X86_PDE_US RT_BIT_32(2)
2655	/** Bit 3 - PWT - Page level write thru bit. */
2656	#define X86_PDE_PWT RT_BIT_32(3)
2657	/** Bit 4 - PCD - Page level cache disable bit. */
2658	#define X86_PDE_PCD RT_BIT_32(4)
2659	/** Bit 5 - A - Access bit. */
2660	#define X86_PDE_A RT_BIT_32(5)
2661	/** Bit 7 - PS - Page size attribute.
2662	* Clear mean 4KB pages, set means large pages (2/4MB). */
2663	#define X86_PDE_PS RT_BIT_32(7)
2664	/** Bits 9-11 - - Available for use to system software. */
2665	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2666	/** Bits 12-31 - - Physical Page number of the next level. */
2667	#define X86_PDE_PG_MASK ( 0xfffff000 )
2668
2669	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2670	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2671	/** Bits 63 - NX - PAE/LM - No execution flag. */
2672	#define X86_PDE_PAE_NX RT_BIT_64(63)
2673	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2674	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2675	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2676	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2677	/** Bit 7 - - LM - MBZ bits when NX is active. */
2678	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2679	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2680	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2681
2682	#ifndef __ASSEMBLER__
2683
2684	/**
2685	* Page directory entry.
2686	*/
2687	typedef struct X86PDEBITS
2688	{
2689	/** Flags whether(=1) or not the page is present. */
2690	uint32_t u1Present : 1;
2691	/** Read(=0) / Write(=1) flag. */
2692	uint32_t u1Write : 1;
2693	/** User(=1) / Supervisor (=0) flag. */
2694	uint32_t u1User : 1;
2695	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2696	uint32_t u1WriteThru : 1;
2697	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2698	uint32_t u1CacheDisable : 1;
2699	/** Accessed flag.
2700	* Indicates that the page has been read or written to. */
2701	uint32_t u1Accessed : 1;
2702	/** Reserved / Ignored (dirty bit). */
2703	uint32_t u1Reserved0 : 1;
2704	/** Size bit if PSE is enabled - in any event it's 0. */
2705	uint32_t u1Size : 1;
2706	/** Reserved / Ignored (global bit). */
2707	uint32_t u1Reserved1 : 1;
2708	/** Available for use to system software. */
2709	uint32_t u3Available : 3;
2710	/** Physical Page number of the next level. */
2711	uint32_t u20PageNo : 20;
2712	} X86PDEBITS;
2713	# ifndef VBOX_FOR_DTRACE_LIB
2714	AssertCompileSize(X86PDEBITS, 4);
2715	# endif
2716	/** Pointer to a page directory entry. */
2717	typedef X86PDEBITS *PX86PDEBITS;
2718	/** Pointer to a const page directory entry. */
2719	typedef const X86PDEBITS *PCX86PDEBITS;
2720
2721
2722	/**
2723	* PAE page directory entry.
2724	*/
2725	typedef struct X86PDEPAEBITS
2726	{
2727	/** Flags whether(=1) or not the page is present. */
2728	uint32_t u1Present : 1;
2729	/** Read(=0) / Write(=1) flag. */
2730	uint32_t u1Write : 1;
2731	/** User(=1) / Supervisor (=0) flag. */
2732	uint32_t u1User : 1;
2733	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2734	uint32_t u1WriteThru : 1;
2735	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2736	uint32_t u1CacheDisable : 1;
2737	/** Accessed flag.
2738	* Indicates that the page has been read or written to. */
2739	uint32_t u1Accessed : 1;
2740	/** Reserved / Ignored (dirty bit). */
2741	uint32_t u1Reserved0 : 1;
2742	/** Size bit if PSE is enabled - in any event it's 0. */
2743	uint32_t u1Size : 1;
2744	/** Reserved / Ignored (global bit). / */
2745	uint32_t u1Reserved1 : 1;
2746	/** Available for use to system software. */
2747	uint32_t u3Available : 3;
2748	/** Physical Page number of the next level - Low Part. Don't use! */
2749	uint32_t u20PageNoLow : 20;
2750	/** Physical Page number of the next level - High Part. Don't use! */
2751	uint32_t u20PageNoHigh : 20;
2752	/** MBZ bits */
2753	uint32_t u11Reserved : 11;
2754	/** No Execute flag. */
2755	uint32_t u1NoExecute : 1;
2756	} X86PDEPAEBITS;
2757	# ifndef VBOX_FOR_DTRACE_LIB
2758	AssertCompileSize(X86PDEPAEBITS, 8);
2759	# endif
2760	/** Pointer to a page directory entry. */
2761	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2762	/** Pointer to a const page directory entry. */
2763	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2764
2765	#endif /* !__ASSEMBLER__ */
2766
2767	/** @} */
2768
2769
2770	/** @name 2/4MB Page Directory Entry
2771	* @{
2772	*/
2773	/** Bit 0 - P - Present bit. */
2774	#define X86_PDE4M_P RT_BIT_32(0)
2775	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2776	#define X86_PDE4M_RW RT_BIT_32(1)
2777	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2778	#define X86_PDE4M_US RT_BIT_32(2)
2779	/** Bit 3 - PWT - Page level write thru bit. */
2780	#define X86_PDE4M_PWT RT_BIT_32(3)
2781	/** Bit 4 - PCD - Page level cache disable bit. */
2782	#define X86_PDE4M_PCD RT_BIT_32(4)
2783	/** Bit 5 - A - Access bit. */
2784	#define X86_PDE4M_A RT_BIT_32(5)
2785	/** Bit 6 - D - Dirty bit. */
2786	#define X86_PDE4M_D RT_BIT_32(6)
2787	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2788	#define X86_PDE4M_PS RT_BIT_32(7)
2789	/** Bit 8 - G - Global flag. */
2790	#define X86_PDE4M_G RT_BIT_32(8)
2791	/** Bits 9-11 - AVL - Available for use to system software. */
2792	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2793	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2794	#define X86_PDE4M_PAT RT_BIT_32(12)
2795	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2796	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2797	/** Bits 22-31 - - Physical Page number. */
2798	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2799	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2800	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2801	/** The number of bits to the high part of the page number. */
2802	#define X86_PDE4M_PG_HIGH_SHIFT 19
2803	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2804	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2805
2806	/** Bits 21-51 - - PAE/LM - Physical Page number.
2807	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2808	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2809	/** Bits 63 - NX - PAE/LM - No execution flag. */
2810	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2811	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2812	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2813	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2814	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2815	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2816	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2817	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2818	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2819
2820	#ifndef __ASSEMBLER__
2821
2822	/**
2823	* 4MB page directory entry.
2824	*/
2825	typedef struct X86PDE4MBITS
2826	{
2827	/** Flags whether(=1) or not the page is present. */
2828	uint32_t u1Present : 1;
2829	/** Read(=0) / Write(=1) flag. */
2830	uint32_t u1Write : 1;
2831	/** User(=1) / Supervisor (=0) flag. */
2832	uint32_t u1User : 1;
2833	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2834	uint32_t u1WriteThru : 1;
2835	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2836	uint32_t u1CacheDisable : 1;
2837	/** Accessed flag.
2838	* Indicates that the page have been read or written to. */
2839	uint32_t u1Accessed : 1;
2840	/** Dirty flag.
2841	* Indicates that the page has been written to. */
2842	uint32_t u1Dirty : 1;
2843	/** Page size flag - always 1 for 4MB entries. */
2844	uint32_t u1Size : 1;
2845	/** Global flag. */
2846	uint32_t u1Global : 1;
2847	/** Available for use to system software. */
2848	uint32_t u3Available : 3;
2849	/** Reserved / If PAT enabled, bit 2 of the index. */
2850	uint32_t u1PAT : 1;
2851	/** Bits 32-39 of the page number on AMD64.
2852	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2853	uint32_t u8PageNoHigh : 8;
2854	/** Reserved. */
2855	uint32_t u1Reserved : 1;
2856	/** Physical Page number of the page. */
2857	uint32_t u10PageNo : 10;
2858	} X86PDE4MBITS;
2859	# ifndef VBOX_FOR_DTRACE_LIB
2860	AssertCompileSize(X86PDE4MBITS, 4);
2861	# endif
2862	/** Pointer to a page table entry. */
2863	typedef X86PDE4MBITS *PX86PDE4MBITS;
2864	/** Pointer to a const page table entry. */
2865	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2866
2867
2868	/**
2869	* 2MB PAE page directory entry.
2870	*/
2871	typedef struct X86PDE2MPAEBITS
2872	{
2873	/** Flags whether(=1) or not the page is present. */
2874	uint32_t u1Present : 1;
2875	/** Read(=0) / Write(=1) flag. */
2876	uint32_t u1Write : 1;
2877	/** User(=1) / Supervisor(=0) flag. */
2878	uint32_t u1User : 1;
2879	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2880	uint32_t u1WriteThru : 1;
2881	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2882	uint32_t u1CacheDisable : 1;
2883	/** Accessed flag.
2884	* Indicates that the page have been read or written to. */
2885	uint32_t u1Accessed : 1;
2886	/** Dirty flag.
2887	* Indicates that the page has been written to. */
2888	uint32_t u1Dirty : 1;
2889	/** Page size flag - always 1 for 2MB entries. */
2890	uint32_t u1Size : 1;
2891	/** Global flag. */
2892	uint32_t u1Global : 1;
2893	/** Available for use to system software. */
2894	uint32_t u3Available : 3;
2895	/** Reserved / If PAT enabled, bit 2 of the index. */
2896	uint32_t u1PAT : 1;
2897	/** Reserved. */
2898	uint32_t u9Reserved : 9;
2899	/** Physical Page number of the next level - Low part. Don't use! */
2900	uint32_t u10PageNoLow : 10;
2901	/** Physical Page number of the next level - High part. Don't use! */
2902	uint32_t u20PageNoHigh : 20;
2903	/** MBZ bits */
2904	uint32_t u11Reserved : 11;
2905	/** No Execute flag. */
2906	uint32_t u1NoExecute : 1;
2907	} X86PDE2MPAEBITS;
2908	# ifndef VBOX_FOR_DTRACE_LIB
2909	AssertCompileSize(X86PDE2MPAEBITS, 8);
2910	# endif
2911	/** Pointer to a 2MB PAE page table entry. */
2912	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2913	/** Pointer to a 2MB PAE page table entry. */
2914	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2915
2916	#endif /* !__ASSEMBLER__ */
2917
2918	/** @} */
2919
2920	#ifndef __ASSEMBLER__
2921
2922	/**
2923	* Page directory entry.
2924	*/
2925	typedef union X86PDE
2926	{
2927	/** Unsigned integer view. */
2928	X86PGUINT u;
2929	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2930	/** Normal view. */
2931	X86PDEBITS n;
2932	/** 4MB view (big). */
2933	X86PDE4MBITS b;
2934	# endif
2935	/** 8 bit unsigned integer view. */
2936	uint8_t au8[4];
2937	/** 16 bit unsigned integer view. */
2938	uint16_t au16[2];
2939	/** 32 bit unsigned integer view. */
2940	uint32_t au32[1];
2941	} X86PDE;
2942	# ifndef VBOX_FOR_DTRACE_LIB
2943	AssertCompileSize(X86PDE, 4);
2944	# endif
2945	/** Pointer to a page directory entry. */
2946	typedef X86PDE *PX86PDE;
2947	/** Pointer to a const page directory entry. */
2948	typedef const X86PDE *PCX86PDE;
2949
2950	/**
2951	* PAE page directory entry.
2952	*/
2953	typedef union X86PDEPAE
2954	{
2955	/** Unsigned integer view. */
2956	X86PGPAEUINT u;
2957	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2958	/** Normal view. */
2959	X86PDEPAEBITS n;
2960	/** 2MB page view (big). */
2961	X86PDE2MPAEBITS b;
2962	# endif
2963	/** 8 bit unsigned integer view. */
2964	uint8_t au8[8];
2965	/** 16 bit unsigned integer view. */
2966	uint16_t au16[4];
2967	/** 32 bit unsigned integer view. */
2968	uint32_t au32[2];
2969	} X86PDEPAE;
2970	# ifndef VBOX_FOR_DTRACE_LIB
2971	AssertCompileSize(X86PDEPAE, 8);
2972	# endif
2973	/** Pointer to a page directory entry. */
2974	typedef X86PDEPAE *PX86PDEPAE;
2975	/** Pointer to a const page directory entry. */
2976	typedef const X86PDEPAE *PCX86PDEPAE;
2977
2978	/**
2979	* Page directory.
2980	*/
2981	typedef struct X86PD
2982	{
2983	/** PDE Array. */
2984	X86PDE a[X86_PG_ENTRIES];
2985	} X86PD;
2986	# ifndef VBOX_FOR_DTRACE_LIB
2987	AssertCompileSize(X86PD, 4096);
2988	# endif
2989	/** Pointer to a page directory. */
2990	typedef X86PD *PX86PD;
2991	/** Pointer to a const page directory. */
2992	typedef const X86PD *PCX86PD;
2993
2994	#endif /* !__ASSEMBLER__ */
2995
2996	/** The page shift to get the PD index. */
2997	#define X86_PD_SHIFT 22
2998	/** The PD index mask (apply to a shifted page address). */
2999	#define X86_PD_MASK 0x3ff
3000
3001
3002	#ifndef __ASSEMBLER__
3003	/**
3004	* PAE page directory.
3005	*/
3006	typedef struct X86PDPAE
3007	{
3008	/** PDE Array. */
3009	X86PDEPAE a[X86_PG_PAE_ENTRIES];
3010	} X86PDPAE;
3011	# ifndef VBOX_FOR_DTRACE_LIB
3012	AssertCompileSize(X86PDPAE, 4096);
3013	# endif
3014	/** Pointer to a PAE page directory. */
3015	typedef X86PDPAE *PX86PDPAE;
3016	/** Pointer to a const PAE page directory. */
3017	typedef const X86PDPAE *PCX86PDPAE;
3018	#endif /* !__ASSEMBLER__ */
3019
3020	/** The page shift to get the PAE PD index. */
3021	#define X86_PD_PAE_SHIFT 21
3022	/** The PAE PD index mask (apply to a shifted page address). */
3023	#define X86_PD_PAE_MASK 0x1ff
3024
3025
3026	/** @name Page Directory Pointer Table Entry (PAE)
3027	* @{
3028	*/
3029	/** Bit 0 - P - Present bit. */
3030	#define X86_PDPE_P RT_BIT_32(0)
3031	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
3032	#define X86_PDPE_RW RT_BIT_32(1)
3033	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
3034	#define X86_PDPE_US RT_BIT_32(2)
3035	/** Bit 3 - PWT - Page level write thru bit. */
3036	#define X86_PDPE_PWT RT_BIT_32(3)
3037	/** Bit 4 - PCD - Page level cache disable bit. */
3038	#define X86_PDPE_PCD RT_BIT_32(4)
3039	/** Bit 5 - A - Access bit. Long Mode only. */
3040	#define X86_PDPE_A RT_BIT_32(5)
3041	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
3042	#define X86_PDPE_LM_PS RT_BIT_32(7)
3043	/** Bits 9-11 - - Available for use to system software. */
3044	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3045	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
3046	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
3047	/** Bits 30-51 - - PG - Physical address of the 1GB page referenced by this entry. */
3048	#define X86_PDPE1G_PG_MASK UINT64_C(0x000fffffc0000000)
3049	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
3050	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
3051	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
3052	#define X86_PDPE_LM_NX RT_BIT_64(63)
3053	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
3054	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
3055	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
3056	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
3057	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
3058	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
3059	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
3060	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
3061
3062	#ifndef __ASSEMBLER__
3063
3064	/**
3065	* Page directory pointer table entry.
3066	*/
3067	typedef struct X86PDPEBITS
3068	{
3069	/** Flags whether(=1) or not the page is present. */
3070	uint32_t u1Present : 1;
3071	/** Chunk of reserved bits. */
3072	uint32_t u2Reserved : 2;
3073	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3074	uint32_t u1WriteThru : 1;
3075	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3076	uint32_t u1CacheDisable : 1;
3077	/** Chunk of reserved bits. */
3078	uint32_t u4Reserved : 4;
3079	/** Available for use to system software. */
3080	uint32_t u3Available : 3;
3081	/** Physical Page number of the next level - Low Part. Don't use! */
3082	uint32_t u20PageNoLow : 20;
3083	/** Physical Page number of the next level - High Part. Don't use! */
3084	uint32_t u20PageNoHigh : 20;
3085	/** MBZ bits */
3086	uint32_t u12Reserved : 12;
3087	} X86PDPEBITS;
3088	# ifndef VBOX_FOR_DTRACE_LIB
3089	AssertCompileSize(X86PDPEBITS, 8);
3090	# endif
3091	/** Pointer to a page directory pointer table entry. */
3092	typedef X86PDPEBITS *PX86PTPEBITS;
3093	/** Pointer to a const page directory pointer table entry. */
3094	typedef const X86PDPEBITS *PCX86PTPEBITS;
3095
3096	/**
3097	* Page directory pointer table entry. AMD64 version
3098	*/
3099	typedef struct X86PDPEAMD64BITS
3100	{
3101	/** Flags whether(=1) or not the page is present. */
3102	uint32_t u1Present : 1;
3103	/** Read(=0) / Write(=1) flag. */
3104	uint32_t u1Write : 1;
3105	/** User(=1) / Supervisor (=0) flag. */
3106	uint32_t u1User : 1;
3107	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3108	uint32_t u1WriteThru : 1;
3109	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3110	uint32_t u1CacheDisable : 1;
3111	/** Accessed flag.
3112	* Indicates that the page have been read or written to. */
3113	uint32_t u1Accessed : 1;
3114	/** Chunk of reserved bits. */
3115	uint32_t u3Reserved : 3;
3116	/** Available for use to system software. */
3117	uint32_t u3Available : 3;
3118	/** Physical Page number of the next level - Low Part. Don't use! */
3119	uint32_t u20PageNoLow : 20;
3120	/** Physical Page number of the next level - High Part. Don't use! */
3121	uint32_t u20PageNoHigh : 20;
3122	/** MBZ bits */
3123	uint32_t u11Reserved : 11;
3124	/** No Execute flag. */
3125	uint32_t u1NoExecute : 1;
3126	} X86PDPEAMD64BITS;
3127	# ifndef VBOX_FOR_DTRACE_LIB
3128	AssertCompileSize(X86PDPEAMD64BITS, 8);
3129	# endif
3130	/** Pointer to a page directory pointer table entry. */
3131	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
3132	/** Pointer to a const page directory pointer table entry. */
3133	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
3134
3135	/**
3136	* Page directory pointer table entry for 1GB page. (AMD64 only)
3137	*/
3138	typedef struct X86PDPE1GB
3139	{
3140	/** 0: Flags whether(=1) or not the page is present. */
3141	uint32_t u1Present : 1;
3142	/** 1: Read(=0) / Write(=1) flag. */
3143	uint32_t u1Write : 1;
3144	/** 2: User(=1) / Supervisor (=0) flag. */
3145	uint32_t u1User : 1;
3146	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
3147	uint32_t u1WriteThru : 1;
3148	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
3149	uint32_t u1CacheDisable : 1;
3150	/** 5: Accessed flag.
3151	* Indicates that the page have been read or written to. */
3152	uint32_t u1Accessed : 1;
3153	/** 6: Dirty flag for 1GB pages. */
3154	uint32_t u1Dirty : 1;
3155	/** 7: Indicates 1GB page if set. */
3156	uint32_t u1Size : 1;
3157	/** 8: Global 1GB page. */
3158	uint32_t u1Global: 1;
3159	/** 9-11: Available for use to system software. */
3160	uint32_t u3Available : 3;
3161	/** 12: PAT bit for 1GB page. */
3162	uint32_t u1PAT : 1;
3163	/** 13-29: MBZ bits. */
3164	uint32_t u17Reserved : 17;
3165	/** 30-31: Physical page number - Low Part. Don't use! */
3166	uint32_t u2PageNoLow : 2;
3167	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
3168	uint32_t u20PageNoHigh : 20;
3169	/** 52-62: MBZ bits */
3170	uint32_t u11Reserved : 11;
3171	/** 63: No Execute flag. */
3172	uint32_t u1NoExecute : 1;
3173	} X86PDPE1GB;
3174	# ifndef VBOX_FOR_DTRACE_LIB
3175	AssertCompileSize(X86PDPE1GB, 8);
3176	# endif
3177	/** Pointer to a page directory pointer table entry for a 1GB page. */
3178	typedef X86PDPE1GB *PX86PDPE1GB;
3179	/** Pointer to a const page directory pointer table entry for a 1GB page. */
3180	typedef const X86PDPE1GB *PCX86PDPE1GB;
3181
3182	/**
3183	* Page directory pointer table entry.
3184	*/
3185	typedef union X86PDPE
3186	{
3187	/** Unsigned integer view. */
3188	X86PGPAEUINT u;
3189	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3190	/** Normal view. */
3191	X86PDPEBITS n;
3192	/** AMD64 view. */
3193	X86PDPEAMD64BITS lm;
3194	/** AMD64 big view. */
3195	X86PDPE1GB b;
3196	# endif
3197	/** 8 bit unsigned integer view. */
3198	uint8_t au8[8];
3199	/** 16 bit unsigned integer view. */
3200	uint16_t au16[4];
3201	/** 32 bit unsigned integer view. */
3202	uint32_t au32[2];
3203	} X86PDPE;
3204	# ifndef VBOX_FOR_DTRACE_LIB
3205	AssertCompileSize(X86PDPE, 8);
3206	# endif
3207	/** Pointer to a page directory pointer table entry. */
3208	typedef X86PDPE *PX86PDPE;
3209	/** Pointer to a const page directory pointer table entry. */
3210	typedef const X86PDPE *PCX86PDPE;
3211
3212
3213	/**
3214	* Page directory pointer table.
3215	*/
3216	typedef struct X86PDPT
3217	{
3218	/** PDE Array. */
3219	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
3220	} X86PDPT;
3221	# ifndef VBOX_FOR_DTRACE_LIB
3222	AssertCompileSize(X86PDPT, 4096);
3223	# endif
3224	/** Pointer to a page directory pointer table. */
3225	typedef X86PDPT *PX86PDPT;
3226	/** Pointer to a const page directory pointer table. */
3227	typedef const X86PDPT *PCX86PDPT;
3228
3229	#endif /* !__ASSEMBLER__ */
3230
3231	/** The page shift to get the PDPT index. */
3232	#define X86_PDPT_SHIFT 30
3233	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
3234	#define X86_PDPT_MASK_PAE 0x3
3235	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
3236	#define X86_PDPT_MASK_AMD64 0x1ff
3237
3238	/** @} */
3239
3240
3241	/** @name Page Map Level-4 Entry (Long Mode PAE)
3242	* @{
3243	*/
3244	/** Bit 0 - P - Present bit. */
3245	#define X86_PML4E_P RT_BIT_32(0)
3246	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
3247	#define X86_PML4E_RW RT_BIT_32(1)
3248	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
3249	#define X86_PML4E_US RT_BIT_32(2)
3250	/** Bit 3 - PWT - Page level write thru bit. */
3251	#define X86_PML4E_PWT RT_BIT_32(3)
3252	/** Bit 4 - PCD - Page level cache disable bit. */
3253	#define X86_PML4E_PCD RT_BIT_32(4)
3254	/** Bit 5 - A - Access bit. */
3255	#define X86_PML4E_A RT_BIT_32(5)
3256	/** Bits 9-11 - - Available for use to system software. */
3257	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3258	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
3259	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
3260	/** Bits 8, 7 - - MBZ bits when NX is active. */
3261	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
3262	/** Bits 63, 7 - - MBZ bits when no NX. */
3263	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
3264	/** Bits 63 - NX - PAE - No execution flag. */
3265	#define X86_PML4E_NX RT_BIT_64(63)
3266
3267	#ifndef __ASSEMBLER__
3268
3269	/**
3270	* Page Map Level-4 Entry
3271	*/
3272	typedef struct X86PML4EBITS
3273	{
3274	/** Flags whether(=1) or not the page is present. */
3275	uint32_t u1Present : 1;
3276	/** Read(=0) / Write(=1) flag. */
3277	uint32_t u1Write : 1;
3278	/** User(=1) / Supervisor (=0) flag. */
3279	uint32_t u1User : 1;
3280	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3281	uint32_t u1WriteThru : 1;
3282	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3283	uint32_t u1CacheDisable : 1;
3284	/** Accessed flag.
3285	* Indicates that the page have been read or written to. */
3286	uint32_t u1Accessed : 1;
3287	/** Chunk of reserved bits. */
3288	uint32_t u3Reserved : 3;
3289	/** Available for use to system software. */
3290	uint32_t u3Available : 3;
3291	/** Physical Page number of the next level - Low Part. Don't use! */
3292	uint32_t u20PageNoLow : 20;
3293	/** Physical Page number of the next level - High Part. Don't use! */
3294	uint32_t u20PageNoHigh : 20;
3295	/** MBZ bits */
3296	uint32_t u11Reserved : 11;
3297	/** No Execute flag. */
3298	uint32_t u1NoExecute : 1;
3299	} X86PML4EBITS;
3300	# ifndef VBOX_FOR_DTRACE_LIB
3301	AssertCompileSize(X86PML4EBITS, 8);
3302	# endif
3303	/** Pointer to a page map level-4 entry. */
3304	typedef X86PML4EBITS *PX86PML4EBITS;
3305	/** Pointer to a const page map level-4 entry. */
3306	typedef const X86PML4EBITS *PCX86PML4EBITS;
3307
3308	/**
3309	* Page Map Level-4 Entry.
3310	*/
3311	typedef union X86PML4E
3312	{
3313	/** Unsigned integer view. */
3314	X86PGPAEUINT u;
3315	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3316	/** Normal view. */
3317	X86PML4EBITS n;
3318	# endif
3319	/** 8 bit unsigned integer view. */
3320	uint8_t au8[8];
3321	/** 16 bit unsigned integer view. */
3322	uint16_t au16[4];
3323	/** 32 bit unsigned integer view. */
3324	uint32_t au32[2];
3325	} X86PML4E;
3326	# ifndef VBOX_FOR_DTRACE_LIB
3327	AssertCompileSize(X86PML4E, 8);
3328	# endif
3329	/** Pointer to a page map level-4 entry. */
3330	typedef X86PML4E *PX86PML4E;
3331	/** Pointer to a const page map level-4 entry. */
3332	typedef const X86PML4E *PCX86PML4E;
3333
3334
3335	/**
3336	* Page Map Level-4.
3337	*/
3338	typedef struct X86PML4
3339	{
3340	/** PDE Array. */
3341	X86PML4E a[X86_PG_PAE_ENTRIES];
3342	} X86PML4;
3343	# ifndef VBOX_FOR_DTRACE_LIB
3344	AssertCompileSize(X86PML4, 4096);
3345	# endif
3346	/** Pointer to a page map level-4. */
3347	typedef X86PML4 *PX86PML4;
3348	/** Pointer to a const page map level-4. */
3349	typedef const X86PML4 *PCX86PML4;
3350
3351	#endif /* !__ASSEMBLER__ */
3352
3353	/** The page shift to get the PML4 index. */
3354	#define X86_PML4_SHIFT 39
3355	/** The PML4 index mask (apply to a shifted page address). */
3356	#define X86_PML4_MASK 0x1ff
3357
3358	/** @} */
3359
3360	/** @} */
3361
3362	/**
3363	* Intel PCID invalidation types.
3364	*/
3365	/** Individual address invalidation. */
3366	#define X86_INVPCID_TYPE_INDV_ADDR 0
3367	/** Single-context invalidation. */
3368	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
3369	/** All-context including globals invalidation. */
3370	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
3371	/** All-context excluding globals invalidation. */
3372	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
3373	/** The maximum valid invalidation type value. */
3374	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
3375
3376
3377	/** @name Special FPU integer values.
3378	* @{ */
3379	#define X86_FPU_INT64_INDEFINITE INT64_MIN
3380	#define X86_FPU_INT32_INDEFINITE INT32_MIN
3381	#define X86_FPU_INT16_INDEFINITE INT16_MIN
3382	/** @} */
3383
3384	#ifndef __ASSEMBLER__
3385
3386	/**
3387	* 32-bit protected mode FSTENV image.
3388	*/
3389	typedef struct X86FSTENV32P
3390	{
3391	uint16_t FCW; /*< 0x00 /
3392	uint16_t padding1; /*< 0x02 /
3393	uint16_t FSW; /*< 0x04 /
3394	uint16_t padding2; /*< 0x06 /
3395	uint16_t FTW; /*< 0x08 /
3396	uint16_t padding3; /*< 0x0a /
3397	uint32_t FPUIP; /*< 0x0c /
3398	uint16_t FPUCS; /*< 0x10 /
3399	uint16_t FOP; /*< 0x12 /
3400	uint32_t FPUDP; /*< 0x14 /
3401	uint16_t FPUDS; /*< 0x18 /
3402	uint16_t padding4; /*< 0x1a /
3403	} X86FSTENV32P;
3404	# ifndef VBOX_FOR_DTRACE_LIB
3405	AssertCompileSize(X86FSTENV32P, 0x1c);
3406	# endif
3407	/** Pointer to a 32-bit protected mode FSTENV image. */
3408	typedef X86FSTENV32P *PX86FSTENV32P;
3409	/** Pointer to a const 32-bit protected mode FSTENV image. */
3410	typedef X86FSTENV32P const *PCX86FSTENV32P;
3411
3412
3413	/**
3414	* 80-bit MMX/FPU register type.
3415	*/
3416	typedef struct X86FPUMMX
3417	{
3418	uint8_t reg[10];
3419	} X86FPUMMX;
3420	# ifndef VBOX_FOR_DTRACE_LIB
3421	AssertCompileSize(X86FPUMMX, 10);
3422	# endif
3423	/** Pointer to a 80-bit MMX/FPU register type. */
3424	typedef X86FPUMMX *PX86FPUMMX;
3425	/** Pointer to a const 80-bit MMX/FPU register type. */
3426	typedef const X86FPUMMX *PCX86FPUMMX;
3427
3428	/** FPU (x87) register. */
3429	typedef union X86FPUREG
3430	{
3431	/** MMX view. */
3432	uint64_t mmx;
3433	/** FPU view - todo. */
3434	X86FPUMMX fpu;
3435	/** Extended precision floating point view. */
3436	RTFLOAT80U r80;
3437	/** Extended precision floating point view v2 */
3438	RTFLOAT80U2 r80Ex;
3439	/** 8-bit view. */
3440	uint8_t au8[16];
3441	/** 16-bit view. */
3442	uint16_t au16[8];
3443	/** 32-bit view. */
3444	uint32_t au32[4];
3445	/** 64-bit view. */
3446	uint64_t au64[2];
3447	/** 128-bit view. (yeah, very helpful) */
3448	uint128_t au128[1];
3449	} X86FPUREG;
3450	# ifndef VBOX_FOR_DTRACE_LIB
3451	AssertCompileSize(X86FPUREG, 16);
3452	# endif
3453	/** Pointer to a FPU register. */
3454	typedef X86FPUREG *PX86FPUREG;
3455	/** Pointer to a const FPU register. */
3456	typedef X86FPUREG const *PCX86FPUREG;
3457
3458	/** FPU (x87) register - v2 with correct size. */
3459	# pragma pack(1)
3460	typedef union X86FPUREG2
3461	{
3462	/** MMX view. */
3463	uint64_t mmx;
3464	/** FPU view - todo. */
3465	X86FPUMMX fpu;
3466	/** Extended precision floating point view. */
3467	RTFLOAT80U r80;
3468	/** 8-bit view. */
3469	uint8_t au8[10];
3470	/** 16-bit view. */
3471	uint16_t au16[5];
3472	/** 32-bit view. */
3473	uint32_t au32[2];
3474	/** 64-bit view. */
3475	uint64_t au64[1];
3476	} X86FPUREG2;
3477	# pragma pack()
3478	# ifndef VBOX_FOR_DTRACE_LIB
3479	AssertCompileSize(X86FPUREG2, 10);
3480	# endif
3481	/** Pointer to a FPU register - v2. */
3482	typedef X86FPUREG2 *PX86FPUREG2;
3483	/** Pointer to a const FPU register - v2. */
3484	typedef X86FPUREG2 const *PCX86FPUREG2;
3485
3486	/**
3487	* XMM register union.
3488	*/
3489	typedef union X86XMMREG
3490	{
3491	/** XMM Register view. */
3492	uint128_t xmm;
3493	/** 8-bit view. */
3494	uint8_t au8[16];
3495	/** 16-bit view. */
3496	uint16_t au16[8];
3497	/** 32-bit view. */
3498	uint32_t au32[4];
3499	/** 64-bit view. */
3500	uint64_t au64[2];
3501	/** Signed 8-bit view. */
3502	int8_t ai8[16];
3503	/** Signed 16-bit view. */
3504	int16_t ai16[8];
3505	/** Signed 32-bit view. */
3506	int32_t ai32[4];
3507	/** Signed 64-bit view. */
3508	int64_t ai64[2];
3509	/** 128-bit view. (yeah, very helpful) */
3510	uint128_t au128[1];
3511	/** Single precision floating point view. */
3512	RTFLOAT32U ar32[4];
3513	/** Double precision floating point view. */
3514	RTFLOAT64U ar64[2];
3515	# ifndef VBOX_FOR_DTRACE_LIB
3516	/** Confusing nested 128-bit union view (this is what xmm should've been). */
3517	RTUINT128U uXmm;
3518	# endif
3519	} X86XMMREG;
3520	# ifndef VBOX_FOR_DTRACE_LIB
3521	AssertCompileSize(X86XMMREG, 16);
3522	# endif
3523	/** Pointer to an XMM register state. */
3524	typedef X86XMMREG *PX86XMMREG;
3525	/** Pointer to a const XMM register state. */
3526	typedef X86XMMREG const *PCX86XMMREG;
3527
3528	/**
3529	* YMM register union.
3530	*/
3531	typedef union X86YMMREG
3532	{
3533	/** YMM register view. */
3534	RTUINT256U ymm;
3535	/** 8-bit view. */
3536	uint8_t au8[32];
3537	/** 16-bit view. */
3538	uint16_t au16[16];
3539	/** 32-bit view. */
3540	uint32_t au32[8];
3541	/** 64-bit view. */
3542	uint64_t au64[4];
3543	/** Signed 8-bit view. */
3544	int8_t ai8[32];
3545	/** Signed 16-bit view. */
3546	int16_t ai16[16];
3547	/** Signed 32-bit view. */
3548	int32_t ai32[8];
3549	/** Signed 64-bit view. */
3550	int64_t ai64[4];
3551	/** 128-bit view. (yeah, very helpful) */
3552	uint128_t au128[2];
3553	/** Single precision floating point view. */
3554	RTFLOAT32U ar32[8];
3555	/** Double precision floating point view. */
3556	RTFLOAT64U ar64[4];
3557	/** XMM sub register view. */
3558	X86XMMREG aXmm[2];
3559	} X86YMMREG;
3560	# ifndef VBOX_FOR_DTRACE_LIB
3561	AssertCompileSize(X86YMMREG, 32);
3562	# endif
3563	/** Pointer to an YMM register state. */
3564	typedef X86YMMREG *PX86YMMREG;
3565	/** Pointer to a const YMM register state. */
3566	typedef X86YMMREG const *PCX86YMMREG;
3567
3568	/**
3569	* ZMM register union.
3570	*/
3571	typedef union X86ZMMREG
3572	{
3573	/** 8-bit view. */
3574	uint8_t au8[64];
3575	/** 16-bit view. */
3576	uint16_t au16[32];
3577	/** 32-bit view. */
3578	uint32_t au32[16];
3579	/** 64-bit view. */
3580	uint64_t au64[8];
3581	/** Signed 8-bit view. */
3582	int8_t ai8[64];
3583	/** Signed 16-bit view. */
3584	int16_t ai16[32];
3585	/** Signed 32-bit view. */
3586	int32_t ai32[16];
3587	/** Signed 64-bit view. */
3588	int64_t ai64[8];
3589	/** 128-bit view. (yeah, very helpful) */
3590	uint128_t au128[4];
3591	/** Single precision floating point view. */
3592	RTFLOAT32U ar32[16];
3593	/** Double precision floating point view. */
3594	RTFLOAT64U ar64[8];
3595	/** XMM sub register view. */
3596	X86XMMREG aXmm[4];
3597	/** YMM sub register view. */
3598	X86YMMREG aYmm[2];
3599	} X86ZMMREG;
3600	# ifndef VBOX_FOR_DTRACE_LIB
3601	AssertCompileSize(X86ZMMREG, 64);
3602	# endif
3603	/** Pointer to an ZMM register state. */
3604	typedef X86ZMMREG *PX86ZMMREG;
3605	/** Pointer to a const ZMM register state. */
3606	typedef X86ZMMREG const *PCX86ZMMREG;
3607
3608
3609	/**
3610	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3611	*/
3612	# pragma pack(1)
3613	typedef struct X86FPUSTATE
3614	{
3615	/** 0x00 - Control word. */
3616	uint16_t FCW;
3617	/** 0x02 - Alignment word */
3618	uint16_t Dummy1;
3619	/** 0x04 - Status word. */
3620	uint16_t FSW;
3621	/** 0x06 - Alignment word */
3622	uint16_t Dummy2;
3623	/** 0x08 - Tag word */
3624	uint16_t FTW;
3625	/** 0x0a - Alignment word */
3626	uint16_t Dummy3;
3627
3628	/** 0x0c - Instruction pointer. */
3629	uint32_t FPUIP;
3630	/** 0x10 - Code selector. */
3631	uint16_t CS;
3632	/** 0x12 - Opcode. */
3633	uint16_t FOP;
3634	/** 0x14 - Data pointer. */
3635	uint32_t FPUOO;
3636	/** 0x18 - FOS. */
3637	uint16_t FPUOS;
3638	/** 0x0a - Alignment word */
3639	uint16_t Dummy4;
3640	/** 0x1c - FPU register. */
3641	X86FPUREG2 regs[8];
3642	} X86FPUSTATE;
3643	# pragma pack()
3644	AssertCompileSize(X86FPUSTATE, 108);
3645	/** Pointer to a FPU state. */
3646	typedef X86FPUSTATE *PX86FPUSTATE;
3647	/** Pointer to a const FPU state. */
3648	typedef const X86FPUSTATE *PCX86FPUSTATE;
3649
3650	/**
3651	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3652	*/
3653	# pragma pack(1)
3654	typedef struct X86FXSTATE
3655	{
3656	/** 0x00 - Control word. */
3657	uint16_t FCW;
3658	/** 0x02 - Status word. */
3659	uint16_t FSW;
3660	/** 0x04 - Tag word. (The upper byte is always zero.) */
3661	uint16_t FTW;
3662	/** 0x06 - Opcode. */
3663	uint16_t FOP;
3664	/** 0x08 - Instruction pointer. */
3665	uint32_t FPUIP;
3666	/** 0x0c - Code selector. */
3667	uint16_t CS;
3668	uint16_t Rsrvd1;
3669	/** 0x10 - Data pointer. */
3670	uint32_t FPUDP;
3671	/** 0x14 - Data segment */
3672	uint16_t DS;
3673	/** 0x16 */
3674	uint16_t Rsrvd2;
3675	/** 0x18 */
3676	uint32_t MXCSR;
3677	/** 0x1c */
3678	uint32_t MXCSR_MASK;
3679	/** 0x20 - FPU registers. */
3680	X86FPUREG aRegs[8];
3681	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3682	X86XMMREG aXMM[16];
3683	/* - offset 416 - */
3684	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3685	/* - offset 464 - Software usable reserved bits. */
3686	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3687	} X86FXSTATE;
3688	# pragma pack()
3689	/** Pointer to a FPU Extended state. */
3690	typedef X86FXSTATE *PX86FXSTATE;
3691	/** Pointer to a const FPU Extended state. */
3692	typedef const X86FXSTATE *PCX86FXSTATE;
3693
3694	#endif /* !__ASSEMBLER__ */
3695
3696
3697	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3698	* magic. Don't forget to update x86.mac if you change this! */
3699	#define X86_OFF_FXSTATE_RSVD 0x1d0
3700	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3701	* forget to update x86.mac if you change this!
3702	* @todo r=bird: This has nothing what-so-ever to do here.... */
3703	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3704	#ifndef VBOX_FOR_DTRACE_LIB
3705	AssertCompileSize(X86FXSTATE, 512);
3706	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3707	#endif
3708
3709	/** @name FPU status word flags.
3710	* @{ */
3711	/** Exception Flag: Invalid operation. */
3712	#define X86_FSW_IE RT_BIT_32(0)
3713	#define X86_FSW_IE_BIT 0
3714	/** Exception Flag: Denormalized operand. */
3715	#define X86_FSW_DE RT_BIT_32(1)
3716	#define X86_FSW_DE_BIT 1
3717	/** Exception Flag: Zero divide. */
3718	#define X86_FSW_ZE RT_BIT_32(2)
3719	#define X86_FSW_ZE_BIT 2
3720	/** Exception Flag: Overflow. */
3721	#define X86_FSW_OE RT_BIT_32(3)
3722	#define X86_FSW_OE_BIT 3
3723	/** Exception Flag: Underflow. */
3724	#define X86_FSW_UE RT_BIT_32(4)
3725	#define X86_FSW_UE_BIT 4
3726	/** Exception Flag: Precision. */
3727	#define X86_FSW_PE RT_BIT_32(5)
3728	#define X86_FSW_PE_BIT 5
3729	/** Stack fault. */
3730	#define X86_FSW_SF RT_BIT_32(6)
3731	#define X86_FSW_SF_BIT 6
3732	/** Error summary status. */
3733	#define X86_FSW_ES RT_BIT_32(7)
3734	#define X86_FSW_ES_BIT 7
3735	/** Mask of exceptions flags, excluding the summary bit. */
3736	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3737	/** Mask of exceptions flags, including the summary bit. */
3738	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3739	/** Condition code 0. */
3740	#define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
3741	#define X86_FSW_C0_BIT 8
3742	/** Condition code 1. */
3743	#define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
3744	#define X86_FSW_C1_BIT 9
3745	/** Condition code 2. */
3746	#define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
3747	#define X86_FSW_C2_BIT 10
3748	/** Top of the stack mask. */
3749	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3750	/** TOP shift value. */
3751	#define X86_FSW_TOP_SHIFT 11
3752	/** Mask for getting TOP value after shifting it right. */
3753	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3754	/** Get the TOP value. */
3755	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3756	/** Get the TOP value offsetted by a_iSt (0-7). */
3757	#define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
3758	/** Condition code 3. */
3759	#define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
3760	#define X86_FSW_C3_BIT 14
3761	/** Mask of exceptions flags, including the summary bit. */
3762	#define X86_FSW_C_MASK UINT16_C(0x4700)
3763	/** FPU busy. */
3764	#define X86_FSW_B RT_BIT_32(15)
3765	/** For use with FPREM and FPREM1. */
3766	#define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
3767	( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
3768	\| (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
3769	\| (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
3770	/** For use with FPREM and FPREM1. */
3771	#define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
3772	( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
3773	\| ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
3774	\| ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
3775	/** @} */
3776
3777
3778	/** @name FPU control word flags.
3779	* @{ */
3780	/** Exception Mask: Invalid operation. */
3781	#define X86_FCW_IM RT_BIT_32(0)
3782	#define X86_FCW_IM_BIT 0
3783	/** Exception Mask: Denormalized operand. */
3784	#define X86_FCW_DM RT_BIT_32(1)
3785	#define X86_FCW_DM_BIT 1
3786	/** Exception Mask: Zero divide. */
3787	#define X86_FCW_ZM RT_BIT_32(2)
3788	#define X86_FCW_ZM_BIT 2
3789	/** Exception Mask: Overflow. */
3790	#define X86_FCW_OM RT_BIT_32(3)
3791	#define X86_FCW_OM_BIT 3
3792	/** Exception Mask: Underflow. */
3793	#define X86_FCW_UM RT_BIT_32(4)
3794	#define X86_FCW_UM_BIT 4
3795	/** Exception Mask: Precision. */
3796	#define X86_FCW_PM RT_BIT_32(5)
3797	#define X86_FCW_PM_BIT 5
3798	/** Mask all exceptions, the value typically loaded (by for instance fninit).
3799	* @remarks This includes reserved bit 6. */
3800	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3801	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3802	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3803	/** Precision control mask. */
3804	#define X86_FCW_PC_MASK UINT16_C(0x0300)
3805	/** Precision control shift. */
3806	#define X86_FCW_PC_SHIFT 8
3807	/** Precision control: 24-bit. */
3808	#define X86_FCW_PC_24 UINT16_C(0x0000)
3809	/** Precision control: Reserved. */
3810	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3811	/** Precision control: 53-bit. */
3812	#define X86_FCW_PC_53 UINT16_C(0x0200)
3813	/** Precision control: 64-bit. */
3814	#define X86_FCW_PC_64 UINT16_C(0x0300)
3815	/** Rounding control mask. */
3816	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3817	/** Rounding control shift. */
3818	#define X86_FCW_RC_SHIFT 10
3819	/** Rounding control: To nearest. */
3820	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3821	/** Rounding control: Down. */
3822	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3823	/** Rounding control: Up. */
3824	#define X86_FCW_RC_UP UINT16_C(0x0800)
3825	/** Rounding control: Towards zero. */
3826	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3827	/** Infinity control mask - obsolete, 8087 & 287 only. */
3828	#define X86_FCW_IC_MASK UINT16_C(0x1000)
3829	/** Infinity control: Affine - positive infinity is distictly different from
3830	* negative infinity.
3831	* @note 8087, 287 only */
3832	#define X86_FCW_IC_AFFINE UINT16_C(0x1000)
3833	/** Infinity control: Projective - positive and negative infinity are the
3834	* same (sign ignored).
3835	* @note 8087, 287 only */
3836	#define X86_FCW_IC_PROJECTIVE UINT16_C(0x0000)
3837	/** Bits which should be zero, apparently. */
3838	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3839	/** @} */
3840
3841	/** @name SSE MXCSR
3842	* @{ */
3843	/** Exception Flag: Invalid operation. */
3844	#define X86_MXCSR_IE RT_BIT_32(0)
3845	#define X86_MXCSR_IE_BIT 0
3846	/** Exception Flag: Denormalized operand. */
3847	#define X86_MXCSR_DE RT_BIT_32(1)
3848	#define X86_MXCSR_DE_BIT 1
3849	/** Exception Flag: Zero divide. */
3850	#define X86_MXCSR_ZE RT_BIT_32(2)
3851	#define X86_MXCSR_ZE_BIT 2
3852	/** Exception Flag: Overflow. */
3853	#define X86_MXCSR_OE RT_BIT_32(3)
3854	#define X86_MXCSR_OE_BIT 3
3855	/** Exception Flag: Underflow. */
3856	#define X86_MXCSR_UE RT_BIT_32(4)
3857	#define X86_MXCSR_UE_BIT 4
3858	/** Exception Flag: Precision. */
3859	#define X86_MXCSR_PE RT_BIT_32(5)
3860	#define X86_MXCSR_PE_BIT 5
3861	/** Exception Flags: mask */
3862	#define X86_MXCSR_XCPT_FLAGS UINT32_C(0x003f)
3863
3864	/** Denormals are zero. */
3865	#define X86_MXCSR_DAZ RT_BIT_32(6)
3866	#define X86_MXCSR_DAZ_BIT 6
3867
3868	/** Exception Mask: Invalid operation. */
3869	#define X86_MXCSR_IM RT_BIT_32(7)
3870	#define X86_MXCSR_IM_BIT 7
3871	/** Exception Mask: Denormalized operand. */
3872	#define X86_MXCSR_DM RT_BIT_32(8)
3873	#define X86_MXCSR_DM_BIT 8
3874	/** Exception Mask: Zero divide. */
3875	#define X86_MXCSR_ZM RT_BIT_32(9)
3876	#define X86_MXCSR_ZM_BIT 9
3877	/** Exception Mask: Overflow. */
3878	#define X86_MXCSR_OM RT_BIT_32(10)
3879	#define X86_MXCSR_OM_BIT 10
3880	/** Exception Mask: Underflow. */
3881	#define X86_MXCSR_UM RT_BIT_32(11)
3882	#define X86_MXCSR_UM_BIT 11
3883	/** Exception Mask: Precision. */
3884	#define X86_MXCSR_PM RT_BIT_32(12)
3885	#define X86_MXCSR_PM_BIT 12
3886	/** Exception Mask: mask. */
3887	#define X86_MXCSR_XCPT_MASK UINT32_C(0x1f80)
3888	/** Exception Mask: shift. */
3889	#define X86_MXCSR_XCPT_MASK_SHIFT 7
3890
3891	/** Rounding control mask. */
3892	#define X86_MXCSR_RC_MASK UINT32_C(0x6000)
3893	/** Rounding control shift. */
3894	#define X86_MXCSR_RC_SHIFT 13
3895	/** Rounding control: To nearest. */
3896	#define X86_MXCSR_RC_NEAREST UINT32_C(0x0000)
3897	/** Rounding control: Down. */
3898	#define X86_MXCSR_RC_DOWN UINT32_C(0x2000)
3899	/** Rounding control: Up. */
3900	#define X86_MXCSR_RC_UP UINT32_C(0x4000)
3901	/** Rounding control: Towards zero. */
3902	#define X86_MXCSR_RC_ZERO UINT32_C(0x6000)
3903
3904	/** Flush-to-zero for masked underflow. */
3905	#define X86_MXCSR_FZ RT_BIT_32(15)
3906	#define X86_MXCSR_FZ_BIT 15
3907
3908	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3909	#define X86_MXCSR_MM RT_BIT_32(17)
3910	#define X86_MXCSR_MM_BIT 17
3911	/** Bits which should be zero, apparently. */
3912	#define X86_MXCSR_ZERO_MASK UINT32_C(0xfffd0000)
3913	/** @} */
3914
3915	#ifndef __ASSEMBLER__
3916
3917	/**
3918	* XSAVE header.
3919	*/
3920	typedef struct X86XSAVEHDR
3921	{
3922	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
3923	uint64_t bmXState;
3924	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3925	uint64_t bmXComp;
3926	/** Reserved for furture extensions, probably MBZ. */
3927	uint64_t au64Reserved[6];
3928	} X86XSAVEHDR;
3929	# ifndef VBOX_FOR_DTRACE_LIB
3930	AssertCompileSize(X86XSAVEHDR, 64);
3931	# endif
3932	/** Pointer to an XSAVE header. */
3933	typedef X86XSAVEHDR *PX86XSAVEHDR;
3934	/** Pointer to a const XSAVE header. */
3935	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3936
3937
3938	/**
3939	* The high 128-bit YMM register state (XSAVE_C_YMM).
3940	* (The lower 128-bits being in X86FXSTATE.)
3941	*/
3942	typedef struct X86XSAVEYMMHI
3943	{
3944	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3945	X86XMMREG aYmmHi[16];
3946	} X86XSAVEYMMHI;
3947	# ifndef VBOX_FOR_DTRACE_LIB
3948	AssertCompileSize(X86XSAVEYMMHI, 256);
3949	# endif
3950	/** Pointer to a high 128-bit YMM register state. */
3951	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3952	/** Pointer to a const high 128-bit YMM register state. */
3953	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3954
3955	/**
3956	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
3957	*/
3958	typedef struct X86XSAVEBNDREGS
3959	{
3960	/** Array of registers (BND0...BND3). */
3961	struct
3962	{
3963	/** Lower bound. */
3964	uint64_t uLowerBound;
3965	/** Upper bound. */
3966	uint64_t uUpperBound;
3967	} aRegs[4];
3968	} X86XSAVEBNDREGS;
3969	# ifndef VBOX_FOR_DTRACE_LIB
3970	AssertCompileSize(X86XSAVEBNDREGS, 64);
3971	# endif
3972	/** Pointer to a MPX bound register state. */
3973	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3974	/** Pointer to a const MPX bound register state. */
3975	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3976
3977	/**
3978	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3979	*/
3980	typedef struct X86XSAVEBNDCFG
3981	{
3982	uint64_t fConfig;
3983	uint64_t fStatus;
3984	} X86XSAVEBNDCFG;
3985	# ifndef VBOX_FOR_DTRACE_LIB
3986	AssertCompileSize(X86XSAVEBNDCFG, 16);
3987	# endif
3988	/** Pointer to a MPX bound config and status register state. */
3989	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3990	/** Pointer to a const MPX bound config and status register state. */
3991	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3992
3993	/**
3994	* AVX-512 opmask state (XSAVE_C_OPMASK).
3995	*/
3996	typedef struct X86XSAVEOPMASK
3997	{
3998	/** The K0..K7 values. */
3999	uint64_t aKRegs[8];
4000	} X86XSAVEOPMASK;
4001	# ifndef VBOX_FOR_DTRACE_LIB
4002	AssertCompileSize(X86XSAVEOPMASK, 64);
4003	# endif
4004	/** Pointer to a AVX-512 opmask state. */
4005	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
4006	/** Pointer to a const AVX-512 opmask state. */
4007	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
4008
4009	/**
4010	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
4011	*/
4012	typedef struct X86XSAVEZMMHI256
4013	{
4014	/** Upper 256-bits of ZMM0-15. */
4015	X86YMMREG aHi256Regs[16];
4016	} X86XSAVEZMMHI256;
4017	# ifndef VBOX_FOR_DTRACE_LIB
4018	AssertCompileSize(X86XSAVEZMMHI256, 512);
4019	# endif
4020	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
4021	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
4022	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
4023	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
4024
4025	/**
4026	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
4027	*/
4028	typedef struct X86XSAVEZMM16HI
4029	{
4030	/** ZMM16 thru ZMM31. */
4031	X86ZMMREG aRegs[16];
4032	} X86XSAVEZMM16HI;
4033	# ifndef VBOX_FOR_DTRACE_LIB
4034	AssertCompileSize(X86XSAVEZMM16HI, 1024);
4035	# endif
4036	/** Pointer to a state comprising ZMM16-32. */
4037	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
4038	/** Pointer to a const state comprising ZMM16-32. */
4039	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
4040
4041	/**
4042	* AMD Light weight profiling state (XSAVE_C_LWP).
4043	*
4044	* We probably won't play with this as AMD seems to be dropping from their "zen"
4045	* processor micro architecture.
4046	*/
4047	typedef struct X86XSAVELWP
4048	{
4049	/** Details when needed. */
4050	uint64_t auLater[128/8];
4051	} X86XSAVELWP;
4052	# ifndef VBOX_FOR_DTRACE_LIB
4053	AssertCompileSize(X86XSAVELWP, 128);
4054	# endif
4055
4056
4057	/**
4058	* x86 FPU/SSE/AVX/XXXX state.
4059	*
4060	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
4061	* changes to this structure.
4062	*/
4063	typedef struct X86XSAVEAREA
4064	{
4065	/** The x87 and SSE region (or legacy region if you like). */
4066	X86FXSTATE x87;
4067	/** The XSAVE header. */
4068	X86XSAVEHDR Hdr;
4069	/** Beyond the header, there isn't really a fixed layout, but we can
4070	generally assume the YMM (AVX) register extensions are present and
4071	follows immediately. */
4072	union
4073	{
4074	/** The high 128-bit AVX registers for easy access by IEM.
4075	* @note This ASSUMES they will always be here... */
4076	X86XSAVEYMMHI YmmHi;
4077
4078	/** This is a typical layout on intel CPUs (good for debuggers). */
4079	struct
4080	{
4081	X86XSAVEYMMHI YmmHi;
4082	X86XSAVEBNDREGS BndRegs;
4083	X86XSAVEBNDCFG BndCfg;
4084	uint8_t abFudgeToMatchDocs[0xB0];
4085	X86XSAVEOPMASK Opmask;
4086	X86XSAVEZMMHI256 ZmmHi256;
4087	X86XSAVEZMM16HI Zmm16Hi;
4088	} Intel;
4089
4090	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
4091	struct
4092	{
4093	X86XSAVEYMMHI YmmHi;
4094	X86XSAVELWP Lwp;
4095	} AmdBd;
4096
4097	/** To enbling static deployments that have a reasonable chance of working for
4098	* the next 3-6 CPU generations without running short on space, we allocate a
4099	* lot of extra space here, making the structure a round 8KB in size. This
4100	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
4101	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
4102	uint8_t ab[8192 - 512 - 64];
4103	} u;
4104	} X86XSAVEAREA;
4105	# ifndef VBOX_FOR_DTRACE_LIB
4106	AssertCompileSize(X86XSAVEAREA, 8192);
4107	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
4108	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
4109	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
4110	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
4111	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
4112	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
4113	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
4114	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
4115	# endif
4116	/** Pointer to a XSAVE area. */
4117	typedef X86XSAVEAREA *PX86XSAVEAREA;
4118	/** Pointer to a const XSAVE area. */
4119	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
4120
4121	#endif /* __ASSEMBLER__ */
4122
4123
4124	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
4125	* @{ */
4126	/** Bit 0 - x87 - Legacy FPU state (bit number) */
4127	#define XSAVE_C_X87_BIT 0
4128	/** Bit 0 - x87 - Legacy FPU state. */
4129	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
4130	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
4131	#define XSAVE_C_SSE_BIT 1
4132	/** Bit 1 - SSE - 128-bit SSE state. */
4133	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
4134	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
4135	#define XSAVE_C_YMM_BIT 2
4136	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
4137	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
4138	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
4139	#define XSAVE_C_BNDREGS_BIT 3
4140	/** Bit 3 - BNDREGS - MPX bound register state. */
4141	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
4142	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
4143	#define XSAVE_C_BNDCSR_BIT 4
4144	/** Bit 4 - BNDCSR - MPX bound config and status state. */
4145	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
4146	/** Bit 5 - Opmask - opmask state (bit number). */
4147	#define XSAVE_C_OPMASK_BIT 5
4148	/** Bit 5 - Opmask - opmask state. */
4149	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
4150	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
4151	#define XSAVE_C_ZMM_HI256_BIT 6
4152	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
4153	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
4154	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
4155	#define XSAVE_C_ZMM_16HI_BIT 7
4156	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
4157	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
4158	/** Bit 9 - PKRU - Protection-key state (bit number). */
4159	#define XSAVE_C_PKRU_BIT 9
4160	/** Bit 9 - PKRU - Protection-key state. */
4161	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
4162	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
4163	#define XSAVE_C_LWP_BIT 62
4164	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
4165	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
4166	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
4167	#define XSAVE_C_X_BIT 63
4168	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
4169	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
4170	/** @} */
4171
4172
4173
4174	/** @name Selector Descriptor
4175	* @{
4176	*/
4177
4178	#ifndef __ASSEMBLER__
4179	# ifndef VBOX_FOR_DTRACE_LIB
4180	/**
4181	* Descriptor attributes (as seen by VT-x).
4182	*/
4183	typedef struct X86DESCATTRBITS
4184	{
4185	/** 00 - Segment Type. */
4186	unsigned u4Type : 4;
4187	/** 04 - Descriptor Type. System(=0) or code/data selector */
4188	unsigned u1DescType : 1;
4189	/** 05 - Descriptor Privilege level. */
4190	unsigned u2Dpl : 2;
4191	/** 07 - Flags selector present(=1) or not. */
4192	unsigned u1Present : 1;
4193	/** 08 - Segment limit 16-19. */
4194	unsigned u4LimitHigh : 4;
4195	/** 0c - Available for system software. */
4196	unsigned u1Available : 1;
4197	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
4198	unsigned u1Long : 1;
4199	/** 0e - This flags meaning depends on the segment type. Try make sense out
4200	* of the intel manual yourself. */
4201	unsigned u1DefBig : 1;
4202	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
4203	* clear byte. */
4204	unsigned u1Granularity : 1;
4205	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
4206	unsigned u1Unusable : 1;
4207	} X86DESCATTRBITS;
4208	# endif /* !VBOX_FOR_DTRACE_LIB */
4209	#endif /* !__ASSEMBLER__ */
4210
4211	/** @name X86DESCATTR masks
4212	* Fields X86DESCGENERIC::u4Type thru X86DESCGENERIC::u1Granularity (or
4213	* bits[55:40] if you like). The X86DESCATTR_UNUSABLE bit is an Intel addition.
4214	* @{ */
4215	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
4216	#define X86DESCATTR_DT UINT32_C(0x00000010) /*< Descriptor type: 0=system, 1=code/data /
4217	#define X86DESCATTR_DPL UINT32_C(0x00000060)
4218	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL bitfield. /
4219	#define X86DESCATTR_P UINT32_C(0x00000080)
4220	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
4221	#define X86DESCATTR_AVL UINT32_C(0x00001000)
4222	#define X86DESCATTR_L UINT32_C(0x00002000)
4223	#define X86DESCATTR_D UINT32_C(0x00004000)
4224	#define X86DESCATTR_G UINT32_C(0x00008000)
4225	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
4226	/** @} */
4227
4228
4229	#ifndef __ASSEMBLER__
4230	# pragma pack(1)
4231	typedef union X86DESCATTR
4232	{
4233	/** Unsigned integer view. */
4234	uint32_t u;
4235	# ifndef VBOX_FOR_DTRACE_LIB
4236	/** Normal view. */
4237	X86DESCATTRBITS n;
4238	# endif
4239	} X86DESCATTR;
4240	# pragma pack()
4241	/** Pointer to descriptor attributes. */
4242	typedef X86DESCATTR *PX86DESCATTR;
4243	/** Pointer to const descriptor attributes. */
4244	typedef const X86DESCATTR *PCX86DESCATTR;
4245	#endif /* !__ASSEMBLER__ */
4246
4247	#ifndef VBOX_FOR_DTRACE_LIB
4248
4249	#ifndef __ASSEMBLER__
4250	/**
4251	* Generic descriptor table entry
4252	*/
4253	# pragma pack(1)
4254	typedef struct X86DESCGENERIC
4255	{
4256	/** 00 - Limit - Low word. */
4257	unsigned u16LimitLow : 16;
4258	/** 10 - Base address - low word.
4259	* Don't try set this to 24 because MSC is doing stupid things then. */
4260	unsigned u16BaseLow : 16;
4261	/** 20 - Base address - first 8 bits of high word. */
4262	unsigned u8BaseHigh1 : 8;
4263	/** 28 - Segment Type. */
4264	unsigned u4Type : 4;
4265	/** 2c - Descriptor Type. System(=0) or code/data selector */
4266	unsigned u1DescType : 1;
4267	/** 2d - Descriptor Privilege level. */
4268	unsigned u2Dpl : 2;
4269	/** 2f - Flags selector present(=1) or not. */
4270	unsigned u1Present : 1;
4271	/** 30 - Segment limit 16-19. */
4272	unsigned u4LimitHigh : 4;
4273	/** 34 - Available for system software. */
4274	unsigned u1Available : 1;
4275	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
4276	unsigned u1Long : 1;
4277	/** 36 - This flags meaning depends on the segment type. Try make sense out
4278	* of the intel manual yourself. */
4279	unsigned u1DefBig : 1;
4280	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
4281	* clear byte. */
4282	unsigned u1Granularity : 1;
4283	/** 38 - Base address - highest 8 bits. */
4284	unsigned u8BaseHigh2 : 8;
4285	} X86DESCGENERIC;
4286	# pragma pack()
4287	/** Pointer to a generic descriptor entry. */
4288	typedef X86DESCGENERIC *PX86DESCGENERIC;
4289	/** Pointer to a const generic descriptor entry. */
4290	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
4291	# endif /* !__ASSEMBLER__ */
4292
4293
4294	/** @name Bit offsets of X86DESCGENERIC members.
4295	* @{*/
4296	# define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
4297	# define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
4298	# define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
4299	# define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
4300	# define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
4301	# define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
4302	# define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
4303	# define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
4304	# define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
4305	# define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
4306	# define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
4307	# define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
4308	# define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
4309	/** @} */
4310
4311
4312	/** @name LAR mask
4313	* @{ */
4314	# define X86LAR_F_TYPE UINT16_C( 0x0f00)
4315	# define X86LAR_F_DT UINT16_C( 0x1000)
4316	# define X86LAR_F_DPL UINT16_C( 0x6000)
4317	# define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
4318	# define X86LAR_F_P UINT16_C( 0x8000)
4319	# define X86LAR_F_AVL UINT32_C(0x00100000)
4320	# define X86LAR_F_L UINT32_C(0x00200000)
4321	# define X86LAR_F_D UINT32_C(0x00400000)
4322	# define X86LAR_F_G UINT32_C(0x00800000)
4323	/** @} */
4324
4325
4326	# ifndef __ASSEMBLER__
4327	/**
4328	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
4329	*/
4330	typedef struct X86DESCGATE
4331	{
4332	/** 00 - Target code segment offset - Low word.
4333	* Ignored if task-gate. */
4334	unsigned u16OffsetLow : 16;
4335	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
4336	* TSS selector if task-gate. */
4337	unsigned u16Sel : 16;
4338	/** 20 - Number of parameters for a call-gate.
4339	* Ignored if interrupt-, trap- or task-gate. */
4340	unsigned u5ParmCount : 5;
4341	/** 25 - Reserved / ignored. */
4342	unsigned u3Reserved : 3;
4343	/** 28 - Segment Type. */
4344	unsigned u4Type : 4;
4345	/** 2c - Descriptor Type (0 = system). */
4346	unsigned u1DescType : 1;
4347	/** 2d - Descriptor Privilege level. */
4348	unsigned u2Dpl : 2;
4349	/** 2f - Flags selector present(=1) or not. */
4350	unsigned u1Present : 1;
4351	/** 30 - Target code segment offset - High word.
4352	* Ignored if task-gate. */
4353	unsigned u16OffsetHigh : 16;
4354	} X86DESCGATE;
4355	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4356	typedef X86DESCGATE *PX86DESCGATE;
4357	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4358	typedef const X86DESCGATE *PCX86DESCGATE;
4359	# endif /* !__ASSEMBLER__ */
4360
4361	#endif /* VBOX_FOR_DTRACE_LIB */
4362
4363	#ifndef __ASSEMBLER__
4364	/**
4365	* Descriptor table entry.
4366	*/
4367	# pragma pack(1)
4368	typedef union X86DESC
4369	{
4370	# ifndef VBOX_FOR_DTRACE_LIB
4371	/** Generic descriptor view. */
4372	X86DESCGENERIC Gen;
4373	/** Gate descriptor view. */
4374	X86DESCGATE Gate;
4375	# endif
4376	/** 8 bit unsigned integer view. */
4377	uint8_t au8[8];
4378	/** 16 bit unsigned integer view. */
4379	uint16_t au16[4];
4380	/** 32 bit unsigned integer view. */
4381	uint32_t au32[2];
4382	/** 64 bit unsigned integer view. */
4383	uint64_t au64[1];
4384	/** Unsigned integer view. */
4385	uint64_t u;
4386	} X86DESC;
4387	# ifndef VBOX_FOR_DTRACE_LIB
4388	AssertCompileSize(X86DESC, 8);
4389	# endif
4390	# pragma pack()
4391	/** Pointer to descriptor table entry. */
4392	typedef X86DESC *PX86DESC;
4393	/** Pointer to const descriptor table entry. */
4394	typedef const X86DESC *PCX86DESC;
4395	#endif /* !__ASSEMBLER__ */
4396
4397	/** @def X86DESC_BASE
4398	* Return the base address of a descriptor.
4399	*/
4400	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
4401	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4402	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4403	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4404
4405	/** @def X86DESC_LIMIT
4406	* Return the limit of a descriptor.
4407	*/
4408	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
4409	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
4410	\| ( (a_pDesc)->Gen.u16LimitLow ) )
4411
4412	/** @def X86DESC_LIMIT_G
4413	* Return the limit of a descriptor with the granularity bit taken into account.
4414	* @returns Selector limit (uint32_t).
4415	* @param a_pDesc Pointer to the descriptor.
4416	*/
4417	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
4418	( (a_pDesc)->Gen.u1Granularity \
4419	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
4420	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
4421	)
4422
4423	/** @def X86DESC_GET_HID_ATTR
4424	* Get the descriptor attributes for the hidden register.
4425	*/
4426	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
4427	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
4428
4429	#ifndef __ASSEMBLER__
4430	# ifndef VBOX_FOR_DTRACE_LIB
4431
4432	/**
4433	* 64 bits generic descriptor table entry
4434	* Note: most of these bits have no meaning in long mode.
4435	*/
4436	# pragma pack(1)
4437	typedef struct X86DESC64GENERIC
4438	{
4439	/** Limit - Low word - IGNORED. */
4440	uint32_t u16LimitLow : 16;
4441	/** Base address - low word. - IGNORED
4442	* Don't try set this to 24 because MSC is doing stupid things then. */
4443	uint32_t u16BaseLow : 16;
4444	/** Base address - first 8 bits of high word. - IGNORED */
4445	uint32_t u8BaseHigh1 : 8;
4446	/** Segment Type. */
4447	uint32_t u4Type : 4;
4448	/** Descriptor Type. System(=0) or code/data selector */
4449	uint32_t u1DescType : 1;
4450	/** Descriptor Privilege level. */
4451	uint32_t u2Dpl : 2;
4452	/** Flags selector present(=1) or not. */
4453	uint32_t u1Present : 1;
4454	/** Segment limit 16-19. - IGNORED */
4455	uint32_t u4LimitHigh : 4;
4456	/** Available for system software. - IGNORED */
4457	uint32_t u1Available : 1;
4458	/** Long mode flag. */
4459	uint32_t u1Long : 1;
4460	/** This flags meaning depends on the segment type. Try make sense out
4461	* of the intel manual yourself. */
4462	uint32_t u1DefBig : 1;
4463	/** Granularity of the limit. If set 4KB granularity is used, if
4464	* clear byte. - IGNORED */
4465	uint32_t u1Granularity : 1;
4466	/** Base address - highest 8 bits. - IGNORED */
4467	uint32_t u8BaseHigh2 : 8;
4468	/** Base address - bits 63-32. */
4469	uint32_t u32BaseHigh3 : 32;
4470	uint32_t u8Reserved : 8;
4471	uint32_t u5Zeros : 5;
4472	uint32_t u19Reserved : 19;
4473	} X86DESC64GENERIC;
4474	# pragma pack()
4475	/** Pointer to a generic descriptor entry. */
4476	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
4477	/** Pointer to a const generic descriptor entry. */
4478	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
4479
4480	/**
4481	* System descriptor table entry (64 bits)
4482	*
4483	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
4484	*/
4485	# pragma pack(1)
4486	typedef struct X86DESC64SYSTEM
4487	{
4488	/** Limit - Low word. */
4489	uint32_t u16LimitLow : 16;
4490	/** Base address - low word.
4491	* Don't try set this to 24 because MSC is doing stupid things then. */
4492	uint32_t u16BaseLow : 16;
4493	/** Base address - first 8 bits of high word. */
4494	uint32_t u8BaseHigh1 : 8;
4495	/** Segment Type. */
4496	uint32_t u4Type : 4;
4497	/** Descriptor Type. System(=0) or code/data selector */
4498	uint32_t u1DescType : 1;
4499	/** Descriptor Privilege level. */
4500	uint32_t u2Dpl : 2;
4501	/** Flags selector present(=1) or not. */
4502	uint32_t u1Present : 1;
4503	/** Segment limit 16-19. */
4504	uint32_t u4LimitHigh : 4;
4505	/** Available for system software. */
4506	uint32_t u1Available : 1;
4507	/** Reserved - 0. */
4508	uint32_t u1Reserved : 1;
4509	/** This flags meaning depends on the segment type. Try make sense out
4510	* of the intel manual yourself. */
4511	uint32_t u1DefBig : 1;
4512	/** Granularity of the limit. If set 4KB granularity is used, if
4513	* clear byte. */
4514	uint32_t u1Granularity : 1;
4515	/** Base address - bits 31-24. */
4516	uint32_t u8BaseHigh2 : 8;
4517	/** Base address - bits 63-32. */
4518	uint32_t u32BaseHigh3 : 32;
4519	uint32_t u8Reserved : 8;
4520	uint32_t u5Zeros : 5;
4521	uint32_t u19Reserved : 19;
4522	} X86DESC64SYSTEM;
4523	# pragma pack()
4524	/** Pointer to a system descriptor entry. */
4525	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
4526	/** Pointer to a const system descriptor entry. */
4527	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
4528
4529	/**
4530	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
4531	*/
4532	typedef struct X86DESC64GATE
4533	{
4534	/** Target code segment offset - Low word. */
4535	uint32_t u16OffsetLow : 16;
4536	/** Target code segment selector. */
4537	uint32_t u16Sel : 16;
4538	/** Interrupt stack table for interrupt- and trap-gates.
4539	* Ignored by call-gates. */
4540	uint32_t u3IST : 3;
4541	/** Reserved / ignored. */
4542	uint32_t u5Reserved : 5;
4543	/** Segment Type. */
4544	uint32_t u4Type : 4;
4545	/** Descriptor Type (0 = system). */
4546	uint32_t u1DescType : 1;
4547	/** Descriptor Privilege level. */
4548	uint32_t u2Dpl : 2;
4549	/** Flags selector present(=1) or not. */
4550	uint32_t u1Present : 1;
4551	/** Target code segment offset - High word.
4552	* Ignored if task-gate. */
4553	uint32_t u16OffsetHigh : 16;
4554	/** Target code segment offset - Top dword.
4555	* Ignored if task-gate. */
4556	uint32_t u32OffsetTop : 32;
4557	/** Reserved / ignored / must be zero.
4558	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
4559	uint32_t u32Reserved : 32;
4560	} X86DESC64GATE;
4561	AssertCompileSize(X86DESC64GATE, 16);
4562	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4563	typedef X86DESC64GATE *PX86DESC64GATE;
4564	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4565	typedef const X86DESC64GATE *PCX86DESC64GATE;
4566
4567	# endif /* VBOX_FOR_DTRACE_LIB */
4568
4569	/**
4570	* Descriptor table entry.
4571	*/
4572	# pragma pack(1)
4573	typedef union X86DESC64
4574	{
4575	# ifndef VBOX_FOR_DTRACE_LIB
4576	/** Generic descriptor view. */
4577	X86DESC64GENERIC Gen;
4578	/** System descriptor view. */
4579	X86DESC64SYSTEM System;
4580	/** Gate descriptor view. */
4581	X86DESC64GATE Gate;
4582	# endif
4583
4584	/** 8 bit unsigned integer view. */
4585	uint8_t au8[16];
4586	/** 16 bit unsigned integer view. */
4587	uint16_t au16[8];
4588	/** 32 bit unsigned integer view. */
4589	uint32_t au32[4];
4590	/** 64 bit unsigned integer view. */
4591	uint64_t au64[2];
4592	} X86DESC64;
4593	# ifndef VBOX_FOR_DTRACE_LIB
4594	AssertCompileSize(X86DESC64, 16);
4595	# endif
4596	# pragma pack()
4597	/** Pointer to descriptor table entry. */
4598	typedef X86DESC64 *PX86DESC64;
4599	/** Pointer to const descriptor table entry. */
4600	typedef const X86DESC64 *PCX86DESC64;
4601
4602	/** @def X86DESC64_BASE
4603	* Return the base of a 64-bit descriptor.
4604	*/
4605	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
4606	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
4607	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4608	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4609	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4610
4611
4612
4613	/** @name Host system descriptor table entry - Use with care!
4614	* @{ */
4615	/** Host system descriptor table entry. */
4616	#if HC_ARCH_BITS == 64
4617	typedef X86DESC64 X86DESCHC;
4618	#else
4619	typedef X86DESC X86DESCHC;
4620	#endif
4621	/** Pointer to a host system descriptor table entry. */
4622	#if HC_ARCH_BITS == 64
4623	typedef PX86DESC64 PX86DESCHC;
4624	#else
4625	typedef PX86DESC PX86DESCHC;
4626	#endif
4627	/** Pointer to a const host system descriptor table entry. */
4628	#if HC_ARCH_BITS == 64
4629	typedef PCX86DESC64 PCX86DESCHC;
4630	#else
4631	typedef PCX86DESC PCX86DESCHC;
4632	#endif
4633	/** @} */
4634
4635	#endif /* !__ASSEMBLER__ */
4636
4637
4638	/** @name Selector Descriptor Types.
4639	* @{
4640	*/
4641
4642	/** @name Non-System Selector Types.
4643	* @{ */
4644	/** Code(=set)/Data(=clear) bit. */
4645	#define X86_SEL_TYPE_CODE 8
4646	/** Memory(=set)/System(=clear) bit. */
4647	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4648	/** Accessed bit. */
4649	#define X86_SEL_TYPE_ACCESSED 1
4650	/** Expand down bit (for data selectors only). */
4651	#define X86_SEL_TYPE_DOWN 4
4652	/** Conforming bit (for code selectors only). */
4653	#define X86_SEL_TYPE_CONF 4
4654	/** Write bit (for data selectors only). */
4655	#define X86_SEL_TYPE_WRITE 2
4656	/** Read bit (for code selectors only). */
4657	#define X86_SEL_TYPE_READ 2
4658	/** The bit number of the code segment read bit (relative to u4Type). */
4659	#define X86_SEL_TYPE_READ_BIT 1
4660
4661	/** Read only selector type. */
4662	#define X86_SEL_TYPE_RO 0
4663	/** Accessed read only selector type. */
4664	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
4665	/** Read write selector type. */
4666	#define X86_SEL_TYPE_RW 2
4667	/** Accessed read write selector type. */
4668	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
4669	/** Expand down read only selector type. */
4670	#define X86_SEL_TYPE_RO_DOWN 4
4671	/** Accessed expand down read only selector type. */
4672	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
4673	/** Expand down read write selector type. */
4674	#define X86_SEL_TYPE_RW_DOWN 6
4675	/** Accessed expand down read write selector type. */
4676	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
4677	/** Execute only selector type. */
4678	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
4679	/** Accessed execute only selector type. */
4680	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4681	/** Execute and read selector type. */
4682	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
4683	/** Accessed execute and read selector type. */
4684	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4685	/** Conforming execute only selector type. */
4686	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
4687	/** Accessed Conforming execute only selector type. */
4688	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4689	/** Conforming execute and write selector type. */
4690	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
4691	/** Accessed Conforming execute and write selector type. */
4692	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4693	/** @} */
4694
4695
4696	/** @name System Selector Types.
4697	* @{ */
4698	/** The TSS busy bit mask. */
4699	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4700
4701	/** Undefined system selector type. */
4702	#define X86_SEL_TYPE_SYS_UNDEFINED 0
4703	/** 286 TSS selector. */
4704	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4705	/** LDT selector. */
4706	#define X86_SEL_TYPE_SYS_LDT 2
4707	/** 286 TSS selector - Busy. */
4708	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4709	/** 286 Callgate selector. */
4710	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4711	/** Taskgate selector. */
4712	#define X86_SEL_TYPE_SYS_TASK_GATE 5
4713	/** 286 Interrupt gate selector. */
4714	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4715	/** 286 Trapgate selector. */
4716	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4717	/** Undefined system selector. */
4718	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4719	/** 386 TSS selector. */
4720	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4721	/** Undefined system selector. */
4722	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4723	/** 386 TSS selector - Busy. */
4724	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4725	/** 386 Callgate selector. */
4726	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4727	/** Undefined system selector. */
4728	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4729	/** 386 Interruptgate selector. */
4730	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4731	/** 386 Trapgate selector. */
4732	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4733	/** @} */
4734
4735	/** @name AMD64 System Selector Types.
4736	* @{ */
4737	/** LDT selector. */
4738	#define AMD64_SEL_TYPE_SYS_LDT 2
4739	/** TSS selector - Busy. */
4740	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4741	/** TSS selector - Busy. */
4742	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4743	/** Callgate selector. */
4744	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4745	/** Interruptgate selector. */
4746	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4747	/** Trapgate selector. */
4748	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4749	/** @} */
4750
4751	/** @} */
4752
4753
4754	/** @name Descriptor Table Entry Flag Masks.
4755	* These are for the 2nd 32-bit word of a descriptor.
4756	* @{ */
4757	/** Bits 8-11 - TYPE - Descriptor type mask. */
4758	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
4759	/** Bit 12 - S - System (=0) or Code/Data (=1). */
4760	#define X86_DESC_S RT_BIT_32(12)
4761	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4762	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
4763	/** Bit 15 - P - Present. */
4764	#define X86_DESC_P RT_BIT_32(15)
4765	/** Bit 20 - AVL - Available for system software. */
4766	#define X86_DESC_AVL RT_BIT_32(20)
4767	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4768	#define X86_DESC_DB RT_BIT_32(22)
4769	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4770	* used, if clear byte. */
4771	#define X86_DESC_G RT_BIT_32(23)
4772	/** @} */
4773
4774	/** @} */
4775
4776
4777	/** @name Task Segments.
4778	* @{
4779	*/
4780
4781	/**
4782	* The minimum TSS descriptor limit for 286 tasks.
4783	*/
4784	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4785
4786	/**
4787	* The minimum TSS descriptor segment limit for 386 tasks.
4788	*/
4789	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4790
4791	#ifndef __ASSEMBLER__
4792
4793	/**
4794	* 16-bit Task Segment (TSS).
4795	*/
4796	# pragma pack(1)
4797	typedef struct X86TSS16
4798	{
4799	/** Back link to previous task. (static) */
4800	RTSEL selPrev;
4801	/** Ring-0 stack pointer. (static) */
4802	uint16_t sp0;
4803	/** Ring-0 stack segment. (static) */
4804	RTSEL ss0;
4805	/** Ring-1 stack pointer. (static) */
4806	uint16_t sp1;
4807	/** Ring-1 stack segment. (static) */
4808	RTSEL ss1;
4809	/** Ring-2 stack pointer. (static) */
4810	uint16_t sp2;
4811	/** Ring-2 stack segment. (static) */
4812	RTSEL ss2;
4813	/** IP before task switch. */
4814	uint16_t ip;
4815	/** FLAGS before task switch. */
4816	uint16_t flags;
4817	/** AX before task switch. */
4818	uint16_t ax;
4819	/** CX before task switch. */
4820	uint16_t cx;
4821	/** DX before task switch. */
4822	uint16_t dx;
4823	/** BX before task switch. */
4824	uint16_t bx;
4825	/** SP before task switch. */
4826	uint16_t sp;
4827	/** BP before task switch. */
4828	uint16_t bp;
4829	/** SI before task switch. */
4830	uint16_t si;
4831	/** DI before task switch. */
4832	uint16_t di;
4833	/** ES before task switch. */
4834	RTSEL es;
4835	/** CS before task switch. */
4836	RTSEL cs;
4837	/** SS before task switch. */
4838	RTSEL ss;
4839	/** DS before task switch. */
4840	RTSEL ds;
4841	/** LDTR before task switch. */
4842	RTSEL selLdt;
4843	} X86TSS16;
4844	# ifndef VBOX_FOR_DTRACE_LIB
4845	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4846	# endif
4847	# pragma pack()
4848	/** Pointer to a 16-bit task segment. */
4849	typedef X86TSS16 *PX86TSS16;
4850	/** Pointer to a const 16-bit task segment. */
4851	typedef const X86TSS16 *PCX86TSS16;
4852
4853
4854	/**
4855	* 32-bit Task Segment (TSS).
4856	*/
4857	# pragma pack(1)
4858	typedef struct X86TSS32
4859	{
4860	/** Back link to previous task. (static) */
4861	RTSEL selPrev;
4862	uint16_t padding1;
4863	/** Ring-0 stack pointer. (static) */
4864	uint32_t esp0;
4865	/** Ring-0 stack segment. (static) */
4866	RTSEL ss0;
4867	uint16_t padding_ss0;
4868	/** Ring-1 stack pointer. (static) */
4869	uint32_t esp1;
4870	/** Ring-1 stack segment. (static) */
4871	RTSEL ss1;
4872	uint16_t padding_ss1;
4873	/** Ring-2 stack pointer. (static) */
4874	uint32_t esp2;
4875	/** Ring-2 stack segment. (static) */
4876	RTSEL ss2;
4877	uint16_t padding_ss2;
4878	/** Page directory for the task. (static) */
4879	uint32_t cr3;
4880	/** EIP before task switch. */
4881	uint32_t eip;
4882	/** EFLAGS before task switch. */
4883	uint32_t eflags;
4884	/** EAX before task switch. */
4885	uint32_t eax;
4886	/** ECX before task switch. */
4887	uint32_t ecx;
4888	/** EDX before task switch. */
4889	uint32_t edx;
4890	/** EBX before task switch. */
4891	uint32_t ebx;
4892	/** ESP before task switch. */
4893	uint32_t esp;
4894	/** EBP before task switch. */
4895	uint32_t ebp;
4896	/** ESI before task switch. */
4897	uint32_t esi;
4898	/** EDI before task switch. */
4899	uint32_t edi;
4900	/** ES before task switch. */
4901	RTSEL es;
4902	uint16_t padding_es;
4903	/** CS before task switch. */
4904	RTSEL cs;
4905	uint16_t padding_cs;
4906	/** SS before task switch. */
4907	RTSEL ss;
4908	uint16_t padding_ss;
4909	/** DS before task switch. */
4910	RTSEL ds;
4911	uint16_t padding_ds;
4912	/** FS before task switch. */
4913	RTSEL fs;
4914	uint16_t padding_fs;
4915	/** GS before task switch. */
4916	RTSEL gs;
4917	uint16_t padding_gs;
4918	/** LDTR before task switch. */
4919	RTSEL selLdt;
4920	uint16_t padding_ldt;
4921	/** Debug trap flag */
4922	uint16_t fDebugTrap;
4923	/** Offset relative to the TSS of the start of the I/O Bitmap
4924	* and the end of the interrupt redirection bitmap. */
4925	uint16_t offIoBitmap;
4926	} X86TSS32;
4927	# pragma pack()
4928	/** Pointer to task segment. */
4929	typedef X86TSS32 *PX86TSS32;
4930	/** Pointer to const task segment. */
4931	typedef const X86TSS32 *PCX86TSS32;
4932	# ifndef VBOX_FOR_DTRACE_LIB
4933	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4934	AssertCompileMemberOffset(X86TSS32, cr3, 28);
4935	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4936	# endif
4937
4938	/**
4939	* 64-bit Task segment.
4940	*/
4941	# pragma pack(1)
4942	typedef struct X86TSS64
4943	{
4944	/** Reserved. */
4945	uint32_t u32Reserved;
4946	/** Ring-0 stack pointer. (static) */
4947	uint64_t rsp0;
4948	/** Ring-1 stack pointer. (static) */
4949	uint64_t rsp1;
4950	/** Ring-2 stack pointer. (static) */
4951	uint64_t rsp2;
4952	/** Reserved. */
4953	uint32_t u32Reserved2[2];
4954	/* IST */
4955	uint64_t ist1;
4956	uint64_t ist2;
4957	uint64_t ist3;
4958	uint64_t ist4;
4959	uint64_t ist5;
4960	uint64_t ist6;
4961	uint64_t ist7;
4962	/* Reserved. */
4963	uint16_t u16Reserved[5];
4964	/** Offset relative to the TSS of the start of the I/O Bitmap
4965	* and the end of the interrupt redirection bitmap. */
4966	uint16_t offIoBitmap;
4967	} X86TSS64;
4968	# pragma pack()
4969	/** Pointer to a 64-bit task segment. */
4970	typedef X86TSS64 *PX86TSS64;
4971	/** Pointer to a const 64-bit task segment. */
4972	typedef const X86TSS64 *PCX86TSS64;
4973	# ifndef VBOX_FOR_DTRACE_LIB
4974	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4975	# endif
4976
4977	#endif /* !__ASSEMBLER__ */
4978
4979	/** @} */
4980
4981
4982	/** @name Selectors.
4983	* @{
4984	*/
4985
4986	/**
4987	* The shift used to convert a selector from and to index an index (C).
4988	*/
4989	#define X86_SEL_SHIFT 3
4990
4991	/**
4992	* The mask used to mask off the table indicator and RPL of an selector.
4993	*/
4994	#define X86_SEL_MASK 0xfff8U
4995
4996	/**
4997	* The mask used to mask off the RPL of an selector.
4998	* This is suitable for checking for NULL selectors.
4999	*/
5000	#define X86_SEL_MASK_OFF_RPL 0xfffcU
5001
5002	/**
5003	* The bit indicating that a selector is in the LDT and not in the GDT.
5004	*/
5005	#define X86_SEL_LDT 0x0004U
5006
5007	/**
5008	* The bit mask for getting the RPL of a selector.
5009	*/
5010	#define X86_SEL_RPL 0x0003U
5011
5012	/**
5013	* The mask covering both RPL and LDT.
5014	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
5015	* checks.
5016	*/
5017	#define X86_SEL_RPL_LDT 0x0007U
5018
5019	/** @} */
5020
5021
5022	#ifndef __ASSEMBLER__
5023	/**
5024	* x86 Exceptions/Faults/Traps.
5025	*/
5026	typedef enum X86XCPT
5027	{
5028	/** \#DE - Divide error. */
5029	X86_XCPT_DE = 0x00,
5030	/** \#DB - Debug event (single step, DRx, ..) */
5031	X86_XCPT_DB = 0x01,
5032	/** NMI - Non-Maskable Interrupt */
5033	X86_XCPT_NMI = 0x02,
5034	/** \#BP - Breakpoint (INT3). */
5035	X86_XCPT_BP = 0x03,
5036	/** \#OF - Overflow (INTO). */
5037	X86_XCPT_OF = 0x04,
5038	/** \#BR - Bound range exceeded (BOUND). */
5039	X86_XCPT_BR = 0x05,
5040	/** \#UD - Undefined opcode. */
5041	X86_XCPT_UD = 0x06,
5042	/** \#NM - Device not available (math coprocessor device). */
5043	X86_XCPT_NM = 0x07,
5044	/** \#DF - Double fault. */
5045	X86_XCPT_DF = 0x08,
5046	/** ??? - Coprocessor segment overrun (obsolete). */
5047	X86_XCPT_CO_SEG_OVERRUN = 0x09,
5048	/** \#TS - Taskswitch (TSS). */
5049	X86_XCPT_TS = 0x0a,
5050	/** \#NP - Segment no present. */
5051	X86_XCPT_NP = 0x0b,
5052	/** \#SS - Stack segment fault. */
5053	X86_XCPT_SS = 0x0c,
5054	/** \#GP - General protection fault. */
5055	X86_XCPT_GP = 0x0d,
5056	/** \#PF - Page fault. */
5057	X86_XCPT_PF = 0x0e,
5058	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
5059	/** \#MF - Math fault (FPU). */
5060	X86_XCPT_MF = 0x10,
5061	/** \#AC - Alignment check. */
5062	X86_XCPT_AC = 0x11,
5063	/** \#MC - Machine check. */
5064	X86_XCPT_MC = 0x12,
5065	/** \#XF - SIMD Floating-Point Exception. */
5066	X86_XCPT_XF = 0x13,
5067	/** \#VE - Virtualization Exception (Intel only). */
5068	X86_XCPT_VE = 0x14,
5069	/** \#CP - Control Protection Exception. */
5070	X86_XCPT_CP = 0x15,
5071	/** \#VC - VMM Communication Exception (AMD only). */
5072	X86_XCPT_VC = 0x1d,
5073	/** \#SX - Security Exception (AMD only). */
5074	X86_XCPT_SX = 0x1e
5075	} X86XCPT;
5076	/** Pointer to a x86 exception code. */
5077	typedef X86XCPT *PX86XCPT;
5078	/** Pointer to a const x86 exception code. */
5079	typedef const X86XCPT *PCX86XCPT;
5080	#endif /* !__ASSEMBLER__ */
5081	/** The last valid (currently reserved) exception value. */
5082	#define X86_XCPT_LAST 0x1f
5083
5084
5085	/** @name Trap Error Codes
5086	* @{
5087	*/
5088	/** External indicator. */
5089	#define X86_TRAP_ERR_EXTERNAL 1
5090	/** IDT indicator. */
5091	#define X86_TRAP_ERR_IDT 2
5092	/** Descriptor table indicator - If set LDT, if clear GDT. */
5093	#define X86_TRAP_ERR_TI 4
5094	/** Mask for getting the selector. */
5095	#define X86_TRAP_ERR_SEL_MASK 0xfff8
5096	/** Shift for getting the selector table index (C type index). */
5097	#define X86_TRAP_ERR_SEL_SHIFT 3
5098	/** @} */
5099
5100
5101	/** @name \#PF Trap Error Codes
5102	* @{
5103	*/
5104	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
5105	#define X86_TRAP_PF_P RT_BIT_32(0)
5106	/** Bit 1 - R/W - Read (clear) or write (set) access. */
5107	#define X86_TRAP_PF_RW RT_BIT_32(1)
5108	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
5109	#define X86_TRAP_PF_US RT_BIT_32(2)
5110	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
5111	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
5112	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
5113	#define X86_TRAP_PF_ID RT_BIT_32(4)
5114	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
5115	#define X86_TRAP_PF_PK RT_BIT_32(5)
5116	/** @} */
5117
5118	#ifndef __ASSEMBLER__
5119
5120	# pragma pack(1)
5121	/**
5122	* 16-bit IDTR.
5123	*/
5124	typedef struct X86IDTR16
5125	{
5126	/** Offset. */
5127	uint16_t offSel;
5128	/** Selector. */
5129	uint16_t uSel;
5130	} X86IDTR16, *PX86IDTR16;
5131	# pragma pack()
5132
5133	# pragma pack(1)
5134	/**
5135	* 32-bit IDTR/GDTR.
5136	*/
5137	typedef struct X86XDTR32
5138	{
5139	/** Size of the descriptor table. */
5140	uint16_t cb;
5141	/** Address of the descriptor table. */
5142	# ifndef VBOX_FOR_DTRACE_LIB
5143	uint32_t uAddr;
5144	# else
5145	uint16_t au16Addr[2];
5146	# endif
5147	} X86XDTR32, *PX86XDTR32;
5148	# pragma pack()
5149
5150	# pragma pack(1)
5151	/**
5152	* 64-bit IDTR/GDTR.
5153	*/
5154	typedef struct X86XDTR64
5155	{
5156	/** Size of the descriptor table. */
5157	uint16_t cb;
5158	/** Address of the descriptor table. */
5159	# ifndef VBOX_FOR_DTRACE_LIB
5160	uint64_t uAddr;
5161	# else
5162	uint16_t au16Addr[4];
5163	# endif
5164	} X86XDTR64, *PX86XDTR64;
5165	# pragma pack()
5166
5167	#endif /* !__ASSEMBLER__ */
5168
5169
5170	/** @name ModR/M
5171	* @{ */
5172	#define X86_MODRM_RM_MASK UINT8_C(0x07)
5173	#define X86_MODRM_REG_MASK UINT8_C(0x38)
5174	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
5175	#define X86_MODRM_REG_SHIFT 3
5176	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
5177	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
5178	#define X86_MODRM_MOD_SHIFT 6
5179
5180	#define X86_MOD_MEM0 0 /*< Indirect addressing without displacement (except RM=4 (SIB) and RM=5 (disp32)). /
5181	#define X86_MOD_MEM1 1 /*< Indirect addressing with 8-bit displacement. /
5182	#define X86_MOD_MEM4 2 /*< Indirect addressing with 32-bit displacement. /
5183	#define X86_MOD_REG 3 /*< Registers. /
5184
5185	#ifndef VBOX_FOR_DTRACE_LIB
5186	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
5187	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
5188	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
5189	/** @def X86_MODRM_MAKE
5190	* @param a_Mod The mod value (0..3) - X86_MOD_XXX.
5191	* @param a_Reg The register value (0..7).
5192	* @param a_RegMem The register or memory value (0..7). */
5193	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
5194	#endif
5195
5196	/** @} */
5197
5198	/** @name SIB
5199	* @{ */
5200	#define X86_SIB_BASE_MASK UINT8_C(0x07)
5201	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
5202	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
5203	#define X86_SIB_INDEX_SHIFT 3
5204	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
5205	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
5206	#define X86_SIB_SCALE_SHIFT 6
5207	#ifndef VBOX_FOR_DTRACE_LIB
5208	/** @def X86_SIB_MAKE
5209	* @param a_BaseReg The base register value (0..7).
5210	* @param a_IndexReg The index register value (0..7).
5211	* @param a_Scale The left shift (0..3) to be applied to the index
5212	* register (0 = none, 1 = x2, 2 = x4, 3 = x8).
5213	* */
5214	# define X86_SIB_MAKE(a_BaseReg, a_IndexReg, a_Scale) \
5215	(((a_Scale) << X86_SIB_SCALE_SHIFT) \| ((a_IndexReg) << X86_SIB_INDEX_SHIFT) \| (a_BaseReg))
5216
5217	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
5218	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
5219	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
5220	#endif
5221	/** @} */
5222
5223	/** @name General register indexes.
5224	* @{ */
5225	#define X86_GREG_xAX 0
5226	#define X86_GREG_xCX 1
5227	#define X86_GREG_xDX 2
5228	#define X86_GREG_xBX 3
5229	#define X86_GREG_xSP 4
5230	#define X86_GREG_xBP 5
5231	#define X86_GREG_xSI 6
5232	#define X86_GREG_xDI 7
5233	#define X86_GREG_x8 8
5234	#define X86_GREG_x9 9
5235	#define X86_GREG_x10 10
5236	#define X86_GREG_x11 11
5237	#define X86_GREG_x12 12
5238	#define X86_GREG_x13 13
5239	#define X86_GREG_x14 14
5240	#define X86_GREG_x15 15
5241	/** @} */
5242	/** General register count. */
5243	#define X86_GREG_COUNT 16
5244
5245	/** @name X86_SREG_XXX - Segment register indexes.
5246	* @{ */
5247	#define X86_SREG_ES 0
5248	#define X86_SREG_CS 1
5249	#define X86_SREG_SS 2
5250	#define X86_SREG_DS 3
5251	#define X86_SREG_FS 4
5252	#define X86_SREG_GS 5
5253	/** @} */
5254	/** Segment register count. */
5255	#define X86_SREG_COUNT 6
5256
5257
5258	/** @name X86_OP_XXX - Prefixes
5259	* @{ */
5260	#define X86_OP_PRF_CS UINT8_C(0x2e)
5261	#define X86_OP_PRF_SS UINT8_C(0x36)
5262	#define X86_OP_PRF_DS UINT8_C(0x3e)
5263	#define X86_OP_PRF_ES UINT8_C(0x26)
5264	#define X86_OP_PRF_FS UINT8_C(0x64)
5265	#define X86_OP_PRF_GS UINT8_C(0x65)
5266	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
5267	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
5268	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
5269	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
5270	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
5271	#define X86_OP_REX UINT8_C(0x40)
5272	#define X86_OP_REX_B UINT8_C(0x41)
5273	#define X86_OP_REX_X UINT8_C(0x42)
5274	#define X86_OP_REX_R UINT8_C(0x44)
5275	#define X86_OP_REX_W UINT8_C(0x48)
5276	#define X86_OP_VEX3 UINT8_C(0xc4)
5277	#define X86_OP_VEX2 UINT8_C(0xc5)
5278	/** @} */
5279
5280	/** @name X86_OP_VEX2_XXX - 2-byte VEX prefix helpers.
5281	* @{ */
5282	#define X86_OP_VEX2_BYTE1_P_MASK 0x3
5283	# define X86_OP_VEX2_BYTE1_P_NO_PRF 0
5284	# define X86_OP_VEX2_BYTE1_P_066H 1
5285	# define X86_OP_VEX2_BYTE1_P_0F3H 2
5286	# define X86_OP_VEX2_BYTE1_P_0F2H 3
5287	#define X86_OP_VEX2_BYTE1_L RT_BIT(2)
5288	#define X86_OP_VEX2_BYTE1_VVVV_MASK 0x78
5289	#define X86_OP_VEX2_BYTE1_VVVV_SHIFT 3
5290	#define X86_OP_VEX2_BYTE1_VVVV_NONE 15
5291	#define X86_OP_VEX2_BYTE1_R RT_BIT(7)
5292
5293	#define X86_OP_VEX2_BYTE1_MAKE(a_fRegW, a_iSrcReg, a_f256BitAvx, a_fPrf) \
5294	( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \
5295	\| (~((uint8_t)(a_iSrcReg) & 0xf) << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \
5296	\| ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \
5297	\| ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK))
5298
5299	#define X86_OP_VEX2_BYTE1_MAKE_NO_VVVV(a_fRegW, a_f256BitAvx, a_fPrf) \
5300	( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \
5301	\| (X86_OP_VEX2_BYTE1_VVVV_NONE << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \
5302	\| ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \
5303	\| ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK))
5304	/** @} */
5305
5306	/** @name X86_OP_VEX3_XXX - 3-byte VEX prefix helpers.
5307	* @{ */
5308	#define X86_OP_VEX3_BYTE1_MAP_MASK 0x1f
5309	#define X86_OP_VEX3_BYTE1_B RT_BIT(5)
5310	#define X86_OP_VEX3_BYTE1_X RT_BIT(6)
5311	#define X86_OP_VEX3_BYTE1_R RT_BIT(7)
5312	#define X86_OP_VEX3_BYTE1_MAKE(a_idxMap, a_B, a_X, a_R) \
5313	( (uint8_t)(a_idxMap) \
5314	\| ((a_B) ? 0 : X86_OP_VEX3_BYTE1_B) \
5315	\| ((a_X) ? 0 : X86_OP_VEX3_BYTE1_X) \
5316	\| ((a_R) ? 0 : X86_OP_VEX3_BYTE1_R))
5317
5318	#define X86_OP_VEX3_BYTE2_P_MASK 0x3
5319	# define X86_OP_VEX3_BYTE2_P_NO_PRF 0
5320	# define X86_OP_VEX3_BYTE2_P_066H 1
5321	# define X86_OP_VEX3_BYTE2_P_0F3H 2
5322	# define X86_OP_VEX3_BYTE2_P_0F2H 3
5323	#define X86_OP_VEX3_BYTE2_L RT_BIT(2)
5324	#define X86_OP_VEX3_BYTE2_VVVV_MASK 0x78
5325	#define X86_OP_VEX3_BYTE2_VVVV_SHIFT 3
5326	#define X86_OP_VEX3_BYTE2_VVVV_NONE 15
5327	#define X86_OP_VEX3_BYTE2_W RT_BIT(7)
5328
5329	/** @todo r=bird: Is the '& UINT8_C(0xf)' bit needed? You mask it again after
5330	* shifting. */
5331	#define X86_OP_VEX3_BYTE2_MAKE(a_f64BitOpSize, a_iSrcReg, a_f256BitAvx, a_fPrf) \
5332	( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \
5333	\| ((~((uint8_t)(a_iSrcReg) & UINT8_C(0xf)) << X86_OP_VEX3_BYTE2_VVVV_SHIFT) & X86_OP_VEX3_BYTE2_VVVV_MASK) \
5334	\| ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
5335	\| ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
5336
5337	#define X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(a_f64BitOpSize, a_f256BitAvx, a_fPrf) \
5338	( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \
5339	\| (X86_OP_VEX3_BYTE2_VVVV_NONE << X86_OP_VEX3_BYTE2_VVVV_SHIFT) \
5340	\| ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
5341	\| ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
5342	/** @} */
5343
5344	/** @} */
5345
5346	#endif /* !IPRT_INCLUDED_x86_h */
5347

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source: vbox/trunk/include/iprt/x86.h@ 105688

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