VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 75704

Last change on this file since 75704 was 74648, checked in by vboxsync, 6 years ago

VMM/IEM, CPUM: Nested VMX: bugref:9180 VM-exit bits; Add TPR virtualization for WRMSR.
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1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2017 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef ___iprt_x86_h
29#define ___iprt_x86_h
30
31#ifndef VBOX_FOR_DTRACE_LIB
32# include <iprt/types.h>
33# include <iprt/assert.h>
34#else
35# pragma D depends_on library vbox-types.d
36#endif
37
38/* Workaround for Solaris sys/regset.h defining CS, DS */
39#ifdef RT_OS_SOLARIS
40# undef CS
41# undef DS
42#endif
43
44/** @defgroup grp_rt_x86 x86 Types and Definitions
45 * @ingroup grp_rt
46 * @{
47 */
48
49#ifndef VBOX_FOR_DTRACE_LIB
50/**
51 * EFLAGS Bits.
52 */
53typedef struct X86EFLAGSBITS
54{
55 /** Bit 0 - CF - Carry flag - Status flag. */
56 unsigned u1CF : 1;
57 /** Bit 1 - 1 - Reserved flag. */
58 unsigned u1Reserved0 : 1;
59 /** Bit 2 - PF - Parity flag - Status flag. */
60 unsigned u1PF : 1;
61 /** Bit 3 - 0 - Reserved flag. */
62 unsigned u1Reserved1 : 1;
63 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64 unsigned u1AF : 1;
65 /** Bit 5 - 0 - Reserved flag. */
66 unsigned u1Reserved2 : 1;
67 /** Bit 6 - ZF - Zero flag - Status flag. */
68 unsigned u1ZF : 1;
69 /** Bit 7 - SF - Signed flag - Status flag. */
70 unsigned u1SF : 1;
71 /** Bit 8 - TF - Trap flag - System flag. */
72 unsigned u1TF : 1;
73 /** Bit 9 - IF - Interrupt flag - System flag. */
74 unsigned u1IF : 1;
75 /** Bit 10 - DF - Direction flag - Control flag. */
76 unsigned u1DF : 1;
77 /** Bit 11 - OF - Overflow flag - Status flag. */
78 unsigned u1OF : 1;
79 /** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
80 unsigned u2IOPL : 2;
81 /** Bit 14 - NT - Nested task flag - System flag. */
82 unsigned u1NT : 1;
83 /** Bit 15 - 0 - Reserved flag. */
84 unsigned u1Reserved3 : 1;
85 /** Bit 16 - RF - Resume flag - System flag. */
86 unsigned u1RF : 1;
87 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
88 unsigned u1VM : 1;
89 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90 unsigned u1AC : 1;
91 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92 unsigned u1VIF : 1;
93 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94 unsigned u1VIP : 1;
95 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96 unsigned u1ID : 1;
97 /** Bit 22-31 - 0 - Reserved flag. */
98 unsigned u10Reserved4 : 10;
99} X86EFLAGSBITS;
100/** Pointer to EFLAGS bits. */
101typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102/** Pointer to const EFLAGS bits. */
103typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104#endif /* !VBOX_FOR_DTRACE_LIB */
105
106/**
107 * EFLAGS.
108 */
109typedef union X86EFLAGS
110{
111 /** The plain unsigned view. */
112 uint32_t u;
113#ifndef VBOX_FOR_DTRACE_LIB
114 /** The bitfield view. */
115 X86EFLAGSBITS Bits;
116#endif
117 /** The 8-bit view. */
118 uint8_t au8[4];
119 /** The 16-bit view. */
120 uint16_t au16[2];
121 /** The 32-bit view. */
122 uint32_t au32[1];
123 /** The 32-bit view. */
124 uint32_t u32;
125} X86EFLAGS;
126/** Pointer to EFLAGS. */
127typedef X86EFLAGS *PX86EFLAGS;
128/** Pointer to const EFLAGS. */
129typedef const X86EFLAGS *PCX86EFLAGS;
130
131/**
132 * RFLAGS (32 upper bits are reserved).
133 */
134typedef union X86RFLAGS
135{
136 /** The plain unsigned view. */
137 uint64_t u;
138#ifndef VBOX_FOR_DTRACE_LIB
139 /** The bitfield view. */
140 X86EFLAGSBITS Bits;
141#endif
142 /** The 8-bit view. */
143 uint8_t au8[8];
144 /** The 16-bit view. */
145 uint16_t au16[4];
146 /** The 32-bit view. */
147 uint32_t au32[2];
148 /** The 64-bit view. */
149 uint64_t au64[1];
150 /** The 64-bit view. */
151 uint64_t u64;
152} X86RFLAGS;
153/** Pointer to RFLAGS. */
154typedef X86RFLAGS *PX86RFLAGS;
155/** Pointer to const RFLAGS. */
156typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159/** @name EFLAGS
160 * @{
161 */
162/** Bit 0 - CF - Carry flag - Status flag. */
163#define X86_EFL_CF RT_BIT_32(0)
164#define X86_EFL_CF_BIT 0
165/** Bit 1 - Reserved, reads as 1. */
166#define X86_EFL_1 RT_BIT_32(1)
167/** Bit 2 - PF - Parity flag - Status flag. */
168#define X86_EFL_PF RT_BIT_32(2)
169/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
170#define X86_EFL_AF RT_BIT_32(4)
171#define X86_EFL_AF_BIT 4
172/** Bit 6 - ZF - Zero flag - Status flag. */
173#define X86_EFL_ZF RT_BIT_32(6)
174#define X86_EFL_ZF_BIT 6
175/** Bit 7 - SF - Signed flag - Status flag. */
176#define X86_EFL_SF RT_BIT_32(7)
177#define X86_EFL_SF_BIT 7
178/** Bit 8 - TF - Trap flag - System flag. */
179#define X86_EFL_TF RT_BIT_32(8)
180/** Bit 9 - IF - Interrupt flag - System flag. */
181#define X86_EFL_IF RT_BIT_32(9)
182/** Bit 10 - DF - Direction flag - Control flag. */
183#define X86_EFL_DF RT_BIT_32(10)
184/** Bit 11 - OF - Overflow flag - Status flag. */
185#define X86_EFL_OF RT_BIT_32(11)
186#define X86_EFL_OF_BIT 11
187/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
188#define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
189/** Bit 14 - NT - Nested task flag - System flag. */
190#define X86_EFL_NT RT_BIT_32(14)
191/** Bit 16 - RF - Resume flag - System flag. */
192#define X86_EFL_RF RT_BIT_32(16)
193/** Bit 17 - VM - Virtual 8086 mode - System flag. */
194#define X86_EFL_VM RT_BIT_32(17)
195/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
196#define X86_EFL_AC RT_BIT_32(18)
197/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
198#define X86_EFL_VIF RT_BIT_32(19)
199/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
200#define X86_EFL_VIP RT_BIT_32(20)
201/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
202#define X86_EFL_ID RT_BIT_32(21)
203/** All live bits. */
204#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
205/** Read as 1 bits. */
206#define X86_EFL_RA1_MASK RT_BIT_32(1)
207/** IOPL shift. */
208#define X86_EFL_IOPL_SHIFT 12
209/** The IOPL level from the flags. */
210#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
211/** Bits restored by popf */
212#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
213 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
214/** Bits restored by popf */
215#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
216 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
217/** The status bits commonly updated by arithmetic instructions. */
218#define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
219/** @} */
220
221
222/** CPUID Feature information - ECX.
223 * CPUID query with EAX=1.
224 */
225#ifndef VBOX_FOR_DTRACE_LIB
226typedef struct X86CPUIDFEATECX
227{
228 /** Bit 0 - SSE3 - Supports SSE3 or not. */
229 unsigned u1SSE3 : 1;
230 /** Bit 1 - PCLMULQDQ. */
231 unsigned u1PCLMULQDQ : 1;
232 /** Bit 2 - DS Area 64-bit layout. */
233 unsigned u1DTE64 : 1;
234 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
235 unsigned u1Monitor : 1;
236 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
237 unsigned u1CPLDS : 1;
238 /** Bit 5 - VMX - Virtual Machine Technology. */
239 unsigned u1VMX : 1;
240 /** Bit 6 - SMX: Safer Mode Extensions. */
241 unsigned u1SMX : 1;
242 /** Bit 7 - EST - Enh. SpeedStep Tech. */
243 unsigned u1EST : 1;
244 /** Bit 8 - TM2 - Terminal Monitor 2. */
245 unsigned u1TM2 : 1;
246 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
247 unsigned u1SSSE3 : 1;
248 /** Bit 10 - CNTX-ID - L1 Context ID. */
249 unsigned u1CNTXID : 1;
250 /** Bit 11 - Reserved. */
251 unsigned u1Reserved1 : 1;
252 /** Bit 12 - FMA. */
253 unsigned u1FMA : 1;
254 /** Bit 13 - CX16 - CMPXCHG16B. */
255 unsigned u1CX16 : 1;
256 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
257 unsigned u1TPRUpdate : 1;
258 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
259 unsigned u1PDCM : 1;
260 /** Bit 16 - Reserved. */
261 unsigned u1Reserved2 : 1;
262 /** Bit 17 - PCID - Process-context identifiers. */
263 unsigned u1PCID : 1;
264 /** Bit 18 - Direct Cache Access. */
265 unsigned u1DCA : 1;
266 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
267 unsigned u1SSE4_1 : 1;
268 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
269 unsigned u1SSE4_2 : 1;
270 /** Bit 21 - x2APIC. */
271 unsigned u1x2APIC : 1;
272 /** Bit 22 - MOVBE - Supports MOVBE. */
273 unsigned u1MOVBE : 1;
274 /** Bit 23 - POPCNT - Supports POPCNT. */
275 unsigned u1POPCNT : 1;
276 /** Bit 24 - TSC-Deadline. */
277 unsigned u1TSCDEADLINE : 1;
278 /** Bit 25 - AES. */
279 unsigned u1AES : 1;
280 /** Bit 26 - XSAVE - Supports XSAVE. */
281 unsigned u1XSAVE : 1;
282 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
283 unsigned u1OSXSAVE : 1;
284 /** Bit 28 - AVX - Supports AVX instruction extensions. */
285 unsigned u1AVX : 1;
286 /** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
287 unsigned u1F16C : 1;
288 /** Bit 30 - RDRAND - Supports RDRAND. */
289 unsigned u1RDRAND : 1;
290 /** Bit 31 - Hypervisor present (we're a guest). */
291 unsigned u1HVP : 1;
292} X86CPUIDFEATECX;
293#else /* VBOX_FOR_DTRACE_LIB */
294typedef uint32_t X86CPUIDFEATECX;
295#endif /* VBOX_FOR_DTRACE_LIB */
296/** Pointer to CPUID Feature Information - ECX. */
297typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
298/** Pointer to const CPUID Feature Information - ECX. */
299typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
300
301
302/** CPUID Feature Information - EDX.
303 * CPUID query with EAX=1.
304 */
305#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
306typedef struct X86CPUIDFEATEDX
307{
308 /** Bit 0 - FPU - x87 FPU on Chip. */
309 unsigned u1FPU : 1;
310 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
311 unsigned u1VME : 1;
312 /** Bit 2 - DE - Debugging extensions. */
313 unsigned u1DE : 1;
314 /** Bit 3 - PSE - Page Size Extension. */
315 unsigned u1PSE : 1;
316 /** Bit 4 - TSC - Time Stamp Counter. */
317 unsigned u1TSC : 1;
318 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
319 unsigned u1MSR : 1;
320 /** Bit 6 - PAE - Physical Address Extension. */
321 unsigned u1PAE : 1;
322 /** Bit 7 - MCE - Machine Check Exception. */
323 unsigned u1MCE : 1;
324 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
325 unsigned u1CX8 : 1;
326 /** Bit 9 - APIC - APIC On-Chip. */
327 unsigned u1APIC : 1;
328 /** Bit 10 - Reserved. */
329 unsigned u1Reserved1 : 1;
330 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
331 unsigned u1SEP : 1;
332 /** Bit 12 - MTRR - Memory Type Range Registers. */
333 unsigned u1MTRR : 1;
334 /** Bit 13 - PGE - PTE Global Bit. */
335 unsigned u1PGE : 1;
336 /** Bit 14 - MCA - Machine Check Architecture. */
337 unsigned u1MCA : 1;
338 /** Bit 15 - CMOV - Conditional Move Instructions. */
339 unsigned u1CMOV : 1;
340 /** Bit 16 - PAT - Page Attribute Table. */
341 unsigned u1PAT : 1;
342 /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
343 unsigned u1PSE36 : 1;
344 /** Bit 18 - PSN - Processor Serial Number. */
345 unsigned u1PSN : 1;
346 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
347 unsigned u1CLFSH : 1;
348 /** Bit 20 - Reserved. */
349 unsigned u1Reserved2 : 1;
350 /** Bit 21 - DS - Debug Store. */
351 unsigned u1DS : 1;
352 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
353 unsigned u1ACPI : 1;
354 /** Bit 23 - MMX - Intel MMX 'Technology'. */
355 unsigned u1MMX : 1;
356 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
357 unsigned u1FXSR : 1;
358 /** Bit 25 - SSE - SSE Support. */
359 unsigned u1SSE : 1;
360 /** Bit 26 - SSE2 - SSE2 Support. */
361 unsigned u1SSE2 : 1;
362 /** Bit 27 - SS - Self Snoop. */
363 unsigned u1SS : 1;
364 /** Bit 28 - HTT - Hyper-Threading Technology. */
365 unsigned u1HTT : 1;
366 /** Bit 29 - TM - Thermal Monitor. */
367 unsigned u1TM : 1;
368 /** Bit 30 - Reserved - . */
369 unsigned u1Reserved3 : 1;
370 /** Bit 31 - PBE - Pending Break Enabled. */
371 unsigned u1PBE : 1;
372} X86CPUIDFEATEDX;
373#else /* VBOX_FOR_DTRACE_LIB */
374typedef uint32_t X86CPUIDFEATEDX;
375#endif /* VBOX_FOR_DTRACE_LIB */
376/** Pointer to CPUID Feature Information - EDX. */
377typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
378/** Pointer to const CPUID Feature Information - EDX. */
379typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
380
381/** @name CPUID Vendor information.
382 * CPUID query with EAX=0.
383 * @{
384 */
385#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
386#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
387#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
388
389#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
390#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
391#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
392
393#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
394#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
395#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
396/** @} */
397
398
399/** @name CPUID Feature information.
400 * CPUID query with EAX=1.
401 * @{
402 */
403/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
404#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
405/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
406#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
407/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
408#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
409/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
410#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
411/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
412#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
413/** ECX Bit 5 - VMX - Virtual Machine Technology. */
414#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
415/** ECX Bit 6 - SMX - Safer Mode Extensions. */
416#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
417/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
418#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
419/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
420#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
421/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
422#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
423/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
424#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
425/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
426 * See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
427#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
428/** ECX Bit 12 - FMA. */
429#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
430/** ECX Bit 13 - CX16 - CMPXCHG16B. */
431#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
432/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
433#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
434/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
435#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
436/** ECX Bit 17 - PCID - Process-context identifiers. */
437#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
438/** ECX Bit 18 - DCA - Direct Cache Access. */
439#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
440/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
441#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
442/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
443#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
444/** ECX Bit 21 - x2APIC support. */
445#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
446/** ECX Bit 22 - MOVBE instruction. */
447#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
448/** ECX Bit 23 - POPCNT instruction. */
449#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
450/** ECX Bir 24 - TSC-Deadline. */
451#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
452/** ECX Bit 25 - AES instructions. */
453#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
454/** ECX Bit 26 - XSAVE instruction. */
455#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
456/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
457#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
458/** ECX Bit 28 - AVX. */
459#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
460/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
461#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
462/** ECX Bit 30 - RDRAND instruction. */
463#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
464/** ECX Bit 31 - Hypervisor Present (software only). */
465#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
466
467
468/** Bit 0 - FPU - x87 FPU on Chip. */
469#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
470/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
471#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
472/** Bit 2 - DE - Debugging extensions. */
473#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
474/** Bit 3 - PSE - Page Size Extension. */
475#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
476#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /**< Bit number for X86_CPUID_FEATURE_EDX_PSE. */
477/** Bit 4 - TSC - Time Stamp Counter. */
478#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
479/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
480#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
481/** Bit 6 - PAE - Physical Address Extension. */
482#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
483#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /**< Bit number for X86_CPUID_FEATURE_EDX_PAE. */
484/** Bit 7 - MCE - Machine Check Exception. */
485#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
486/** Bit 8 - CX8 - CMPXCHG8B instruction. */
487#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
488/** Bit 9 - APIC - APIC On-Chip. */
489#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
490/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
491#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
492/** Bit 12 - MTRR - Memory Type Range Registers. */
493#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
494/** Bit 13 - PGE - PTE Global Bit. */
495#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
496/** Bit 14 - MCA - Machine Check Architecture. */
497#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
498/** Bit 15 - CMOV - Conditional Move Instructions. */
499#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
500/** Bit 16 - PAT - Page Attribute Table. */
501#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
502/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
503#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
504/** Bit 18 - PSN - Processor Serial Number. */
505#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
506/** Bit 19 - CLFSH - CLFLUSH Instruction. */
507#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
508/** Bit 21 - DS - Debug Store. */
509#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
510/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
511#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
512/** Bit 23 - MMX - Intel MMX Technology. */
513#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
514/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
515#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
516/** Bit 25 - SSE - SSE Support. */
517#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
518/** Bit 26 - SSE2 - SSE2 Support. */
519#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
520/** Bit 27 - SS - Self Snoop. */
521#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
522/** Bit 28 - HTT - Hyper-Threading Technology. */
523#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
524/** Bit 29 - TM - Therm. Monitor. */
525#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
526/** Bit 31 - PBE - Pending Break Enabled. */
527#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
528/** @} */
529
530/** @name CPUID mwait/monitor information.
531 * CPUID query with EAX=5.
532 * @{
533 */
534/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
535#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
536/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
537#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
538/** @} */
539
540
541/** @name CPUID Structured Extended Feature information.
542 * CPUID query with EAX=7.
543 * @{
544 */
545/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
546#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
547/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
548#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
549/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
550#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
551/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
552#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
553/** EBX Bit 4 - HLE - Hardware Lock Elision. */
554#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
555/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
556#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
557/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
558#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
559/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
560#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
561/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
562#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
563/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
564#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
565/** EBX Bit 10 - INVPCID - Supports INVPCID. */
566#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
567/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
568#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
569/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
570#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
571/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
572#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
573/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
574#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
575/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
576#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
577/** EBX Bit 16 - AVX512F - Supports AVX512F. */
578#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
579/** EBX Bit 18 - RDSEED - Supports RDSEED. */
580#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
581/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
582#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
583/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
584#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
585/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
586#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
587/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
588#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
589/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
590#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
591/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
592#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
593/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
594#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
595/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
596#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
597
598/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
599#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
600/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
601#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
602/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
603#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
604/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
605#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
606/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
607#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
608/** ECX Bit 22 - RDPID - Support pread process ID. */
609#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
610/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
611#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
612
613/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
614 * IBPB command in IA32_PRED_CMD. */
615#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
616/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
617#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
618
619/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
620#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
621
622/** @} */
623
624
625/** @name CPUID Extended Feature information.
626 * CPUID query with EAX=0x80000001.
627 * @{
628 */
629/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
630#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
631
632/** EDX Bit 11 - SYSCALL/SYSRET. */
633#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
634/** EDX Bit 20 - No-Execute/Execute-Disable. */
635#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
636/** EDX Bit 26 - 1 GB large page. */
637#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
638/** EDX Bit 27 - RDTSCP. */
639#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
640/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
641#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
642/** @}*/
643
644/** @name CPUID AMD Feature information.
645 * CPUID query with EAX=0x80000001.
646 * @{
647 */
648/** Bit 0 - FPU - x87 FPU on Chip. */
649#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
650/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
651#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
652/** Bit 2 - DE - Debugging extensions. */
653#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
654/** Bit 3 - PSE - Page Size Extension. */
655#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
656/** Bit 4 - TSC - Time Stamp Counter. */
657#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
658/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
659#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
660/** Bit 6 - PAE - Physical Address Extension. */
661#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
662/** Bit 7 - MCE - Machine Check Exception. */
663#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
664/** Bit 8 - CX8 - CMPXCHG8B instruction. */
665#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
666/** Bit 9 - APIC - APIC On-Chip. */
667#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
668/** Bit 12 - MTRR - Memory Type Range Registers. */
669#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
670/** Bit 13 - PGE - PTE Global Bit. */
671#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
672/** Bit 14 - MCA - Machine Check Architecture. */
673#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
674/** Bit 15 - CMOV - Conditional Move Instructions. */
675#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
676/** Bit 16 - PAT - Page Attribute Table. */
677#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
678/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
679#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
680/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
681#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
682/** Bit 23 - MMX - Intel MMX Technology. */
683#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
684/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
685#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
686/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
687#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
688/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
689#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
690/** Bit 31 - 3DNOW - AMD 3DNow. */
691#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
692
693/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
694#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
695/** Bit 2 - SVM - AMD VM extensions. */
696#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
697/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
698#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
699/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
700#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
701/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
702#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
703/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
704#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
705/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
706#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
707/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
708#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
709/** Bit 9 - OSVW - AMD OS visible workaround. */
710#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
711/** Bit 10 - IBS - Instruct based sampling. */
712#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
713/** Bit 11 - XOP - Extended operation support (see APM6). */
714#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
715/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
716#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
717/** Bit 13 - WDT - AMD Watchdog timer support. */
718#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
719/** Bit 15 - LWP - Lightweight profiling support. */
720#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
721/** Bit 16 - FMA4 - Four operand FMA instruction support. */
722#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
723/** Bit 19 - NodeId - Indicates support for
724 * MSR_C001_100C[NodeId,NodesPerProcessr]. */
725#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
726/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
727#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
728/** Bit 22 - TopologyExtensions - . */
729#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
730/** @} */
731
732
733/** @name CPUID AMD Feature information.
734 * CPUID query with EAX=0x80000007.
735 * @{
736 */
737/** Bit 0 - TS - Temperature Sensor. */
738#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
739/** Bit 1 - FID - Frequency ID Control. */
740#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
741/** Bit 2 - VID - Voltage ID Control. */
742#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
743/** Bit 3 - TTP - THERMTRIP. */
744#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
745/** Bit 4 - TM - Hardware Thermal Control. */
746#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
747/** Bit 5 - STC - Software Thermal Control. */
748#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
749/** Bit 6 - MC - 100 Mhz Multiplier Control. */
750#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
751/** Bit 7 - HWPSTATE - Hardware P-State Control. */
752#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
753/** Bit 8 - TSCINVAR - TSC Invariant. */
754#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
755/** Bit 9 - CPB - TSC Invariant. */
756#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
757/** Bit 10 - EffFreqRO - MPERF/APERF. */
758#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
759/** Bit 11 - PFI - Processor feedback interface (see EAX). */
760#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
761/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
762#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
763/** @} */
764
765
766/** @name CPUID AMD extended feature extensions ID (EBX).
767 * CPUID query with EAX=0x80000008.
768 * @{
769 */
770/** Bit 0 - CLZERO - Clear zero instruction. */
771#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
772/** Bit 1 - IRPerf - Instructions retired count support. */
773#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
774/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
775#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
776/* AMD pipeline length: 9 feature bits ;-) */
777/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
778#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
779/** @} */
780
781
782/** @name CPUID AMD SVM Feature information.
783 * CPUID query with EAX=0x8000000a.
784 * @{
785 */
786/** Bit 0 - NP - Nested Paging supported. */
787#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
788/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
789#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
790/** Bit 2 - SVML - SVM locking bit supported. */
791#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
792/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
793#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
794/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
795#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
796/** Bit 5 - VmcbClean - Support VMCB clean bits. */
797#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
798/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
799 * VMCB.TLB_Control is supported. */
800#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
801/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
802#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
803/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
804#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
805/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
806 * intercept filter cycle count threshold. */
807#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
808/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
809#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
810/** Bit 15 - V_VMSAVE_VMLOAD - Supports virtualized VMSAVE/VMLOAD. */
811#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
812/** Bit 16 - V_VMSAVE_VMLOAD - Supports virtualized GIF. */
813#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
814/** @} */
815
816
817/** @name CR0
818 * @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
819 * reserved flags.
820 * @{ */
821/** Bit 0 - PE - Protection Enabled */
822#define X86_CR0_PE RT_BIT_32(0)
823#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
824/** Bit 1 - MP - Monitor Coprocessor */
825#define X86_CR0_MP RT_BIT_32(1)
826#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
827/** Bit 2 - EM - Emulation. */
828#define X86_CR0_EM RT_BIT_32(2)
829#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
830/** Bit 3 - TS - Task Switch. */
831#define X86_CR0_TS RT_BIT_32(3)
832#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
833/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
834#define X86_CR0_ET RT_BIT_32(4)
835#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
836/** Bit 5 - NE - Numeric error (486+). */
837#define X86_CR0_NE RT_BIT_32(5)
838#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
839/** Bit 16 - WP - Write Protect (486+). */
840#define X86_CR0_WP RT_BIT_32(16)
841#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
842/** Bit 18 - AM - Alignment Mask (486+). */
843#define X86_CR0_AM RT_BIT_32(18)
844#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
845/** Bit 29 - NW - Not Write-though (486+). */
846#define X86_CR0_NW RT_BIT_32(29)
847#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
848/** Bit 30 - WP - Cache Disable (486+). */
849#define X86_CR0_CD RT_BIT_32(30)
850#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
851/** Bit 31 - PG - Paging. */
852#define X86_CR0_PG RT_BIT_32(31)
853#define X86_CR0_PAGING RT_BIT_32(31)
854#define X86_CR0_BIT_PG 31 /**< Bit number of X86_CR0_PG */
855/** @} */
856
857
858/** @name CR3
859 * @{ */
860/** Bit 3 - PWT - Page-level Writes Transparent. */
861#define X86_CR3_PWT RT_BIT_32(3)
862/** Bit 4 - PCD - Page-level Cache Disable. */
863#define X86_CR3_PCD RT_BIT_32(4)
864/** Bits 12-31 - - Page directory page number. */
865#define X86_CR3_PAGE_MASK (0xfffff000)
866/** Bits 5-31 - - PAE Page directory page number. */
867#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
868/** Bits 12-51 - - AMD64 Page directory page number. */
869#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
870/** @} */
871
872
873/** @name CR4
874 * @{ */
875/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
876#define X86_CR4_VME RT_BIT_32(0)
877/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
878#define X86_CR4_PVI RT_BIT_32(1)
879/** Bit 2 - TSD - Time Stamp Disable. */
880#define X86_CR4_TSD RT_BIT_32(2)
881/** Bit 3 - DE - Debugging Extensions. */
882#define X86_CR4_DE RT_BIT_32(3)
883/** Bit 4 - PSE - Page Size Extension. */
884#define X86_CR4_PSE RT_BIT_32(4)
885/** Bit 5 - PAE - Physical Address Extension. */
886#define X86_CR4_PAE RT_BIT_32(5)
887/** Bit 6 - MCE - Machine-Check Enable. */
888#define X86_CR4_MCE RT_BIT_32(6)
889/** Bit 7 - PGE - Page Global Enable. */
890#define X86_CR4_PGE RT_BIT_32(7)
891/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
892#define X86_CR4_PCE RT_BIT_32(8)
893/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
894#define X86_CR4_OSFXSR RT_BIT_32(9)
895/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
896#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
897/** Bit 13 - VMXE - VMX mode is enabled. */
898#define X86_CR4_VMXE RT_BIT_32(13)
899/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
900#define X86_CR4_SMXE RT_BIT_32(14)
901/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
902#define X86_CR4_FSGSBASE RT_BIT_32(16)
903/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
904#define X86_CR4_PCIDE RT_BIT_32(17)
905/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
906 * extended states. */
907#define X86_CR4_OSXSAVE RT_BIT_32(18)
908/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
909#define X86_CR4_SMEP RT_BIT_32(20)
910/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
911#define X86_CR4_SMAP RT_BIT_32(21)
912/** Bit 22 - PKE - Protection Key Enable. */
913#define X86_CR4_PKE RT_BIT_32(22)
914/** @} */
915
916
917/** @name DR6
918 * @{ */
919/** Bit 0 - B0 - Breakpoint 0 condition detected. */
920#define X86_DR6_B0 RT_BIT_32(0)
921/** Bit 1 - B1 - Breakpoint 1 condition detected. */
922#define X86_DR6_B1 RT_BIT_32(1)
923/** Bit 2 - B2 - Breakpoint 2 condition detected. */
924#define X86_DR6_B2 RT_BIT_32(2)
925/** Bit 3 - B3 - Breakpoint 3 condition detected. */
926#define X86_DR6_B3 RT_BIT_32(3)
927/** Mask of all the Bx bits. */
928#define X86_DR6_B_MASK UINT64_C(0x0000000f)
929/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
930#define X86_DR6_BD RT_BIT_32(13)
931/** Bit 14 - BS - Single step */
932#define X86_DR6_BS RT_BIT_32(14)
933/** Bit 15 - BT - Task switch. (TSS T bit.) */
934#define X86_DR6_BT RT_BIT_32(15)
935/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
936#define X86_DR6_RTM RT_BIT_32(16)
937/** Value of DR6 after powerup/reset. */
938#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
939/** Bits which must be 1s in DR6. */
940#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
941/** Bits which must be 1s in DR6, when RTM is supported. */
942#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
943/** Bits which must be 0s in DR6. */
944#define X86_DR6_RAZ_MASK RT_BIT_64(12)
945/** Bits which must be 0s on writes to DR6. */
946#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
947/** @} */
948
949/** Get the DR6.Bx bit for a the given breakpoint. */
950#define X86_DR6_B(iBp) RT_BIT_64(iBp)
951
952
953/** @name DR7
954 * @{ */
955/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
956#define X86_DR7_L0 RT_BIT_32(0)
957/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
958#define X86_DR7_G0 RT_BIT_32(1)
959/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
960#define X86_DR7_L1 RT_BIT_32(2)
961/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
962#define X86_DR7_G1 RT_BIT_32(3)
963/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
964#define X86_DR7_L2 RT_BIT_32(4)
965/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
966#define X86_DR7_G2 RT_BIT_32(5)
967/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
968#define X86_DR7_L3 RT_BIT_32(6)
969/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
970#define X86_DR7_G3 RT_BIT_32(7)
971/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
972#define X86_DR7_LE RT_BIT_32(8)
973/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
974#define X86_DR7_GE RT_BIT_32(9)
975
976/** L0, L1, L2, and L3. */
977#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
978/** L0, L1, L2, and L3. */
979#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
980
981/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
982 * Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
983#define X86_DR7_RTM RT_BIT_32(11)
984/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
985 * Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
986 * May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
987 * instruction is executed.
988 * @see http://www.rcollins.org/secrets/DR7.html */
989#define X86_DR7_ICE_IR RT_BIT_32(12)
990/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
991 * any DR register is accessed. */
992#define X86_DR7_GD RT_BIT_32(13)
993/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
994 * Pentium. */
995#define X86_DR7_ICE_TR1 RT_BIT_32(14)
996/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
997#define X86_DR7_ICE_TR2 RT_BIT_32(15)
998/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
999#define X86_DR7_RW0_MASK (3 << 16)
1000/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
1001#define X86_DR7_LEN0_MASK (3 << 18)
1002/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
1003#define X86_DR7_RW1_MASK (3 << 20)
1004/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
1005#define X86_DR7_LEN1_MASK (3 << 22)
1006/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
1007#define X86_DR7_RW2_MASK (3 << 24)
1008/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
1009#define X86_DR7_LEN2_MASK (3 << 26)
1010/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
1011#define X86_DR7_RW3_MASK (3 << 28)
1012/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
1013#define X86_DR7_LEN3_MASK (3 << 30)
1014
1015/** Bits which reads as 1s. */
1016#define X86_DR7_RA1_MASK RT_BIT_32(10)
1017/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1018#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1019/** Bits which must be 0s when writing to DR7. */
1020#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1021
1022/** Calcs the L bit of Nth breakpoint.
1023 * @param iBp The breakpoint number [0..3].
1024 */
1025#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1026
1027/** Calcs the G bit of Nth breakpoint.
1028 * @param iBp The breakpoint number [0..3].
1029 */
1030#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1031
1032/** Calcs the L and G bits of Nth breakpoint.
1033 * @param iBp The breakpoint number [0..3].
1034 */
1035#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1036
1037/** @name Read/Write values.
1038 * @{ */
1039/** Break on instruction fetch only. */
1040#define X86_DR7_RW_EO UINT32_C(0)
1041/** Break on write only. */
1042#define X86_DR7_RW_WO UINT32_C(1)
1043/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1044#define X86_DR7_RW_IO UINT32_C(2)
1045/** Break on read or write (but not instruction fetches). */
1046#define X86_DR7_RW_RW UINT32_C(3)
1047/** @} */
1048
1049/** Shifts a X86_DR7_RW_* value to its right place.
1050 * @param iBp The breakpoint number [0..3].
1051 * @param fRw One of the X86_DR7_RW_* value.
1052 */
1053#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1054
1055/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1056 * one of the X86_DR7_RW_XXX constants).
1057 *
1058 * @returns X86_DR7_RW_XXX
1059 * @param uDR7 DR7 value
1060 * @param iBp The breakpoint number [0..3].
1061 */
1062#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1063
1064/** R/W0, R/W1, R/W2, and R/W3. */
1065#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1066
1067#ifndef VBOX_FOR_DTRACE_LIB
1068/** Checks if there are any I/O breakpoint types configured in the RW
1069 * registers. Does NOT check if these are enabled, sorry. */
1070# define X86_DR7_ANY_RW_IO(uDR7) \
1071 ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1072 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1073AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1074AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1075AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1076AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1077AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1078AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1079AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1080AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1081AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1082#endif /* !VBOX_FOR_DTRACE_LIB */
1083
1084/** @name Length values.
1085 * @{ */
1086#define X86_DR7_LEN_BYTE UINT32_C(0)
1087#define X86_DR7_LEN_WORD UINT32_C(1)
1088#define X86_DR7_LEN_QWORD UINT32_C(2) /**< AMD64 long mode only. */
1089#define X86_DR7_LEN_DWORD UINT32_C(3)
1090/** @} */
1091
1092/** Shifts a X86_DR7_LEN_* value to its right place.
1093 * @param iBp The breakpoint number [0..3].
1094 * @param cb One of the X86_DR7_LEN_* values.
1095 */
1096#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1097
1098/** Fetch the breakpoint length bits from the DR7 value.
1099 * @param uDR7 DR7 value
1100 * @param iBp The breakpoint number [0..3].
1101 */
1102#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1103
1104/** Mask used to check if any breakpoints are enabled. */
1105#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1106
1107/** LEN0, LEN1, LEN2, and LEN3. */
1108#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1109/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1110#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1111
1112/** Value of DR7 after powerup/reset. */
1113#define X86_DR7_INIT_VAL 0x400
1114/** @} */
1115
1116
1117/** @name Machine Specific Registers
1118 * @{
1119 */
1120/** Machine check address register (P5). */
1121#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1122/** Machine check type register (P5). */
1123#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1124/** Time Stamp Counter. */
1125#define MSR_IA32_TSC 0x10
1126#define MSR_IA32_CESR UINT32_C(0x00000011)
1127#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1128#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1129
1130#define MSR_IA32_PLATFORM_ID 0x17
1131
1132#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1133# define MSR_IA32_APICBASE 0x1b
1134/** Local APIC enabled. */
1135# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1136/** X2APIC enabled (requires the EN bit to be set). */
1137# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1138/** The processor is the boot strap processor (BSP). */
1139# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1140/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1141 * width. */
1142# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1143/** The default physical base address of the APIC. */
1144# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1145/** Gets the physical base address from the MSR. */
1146# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1147#endif
1148
1149/** Undocumented intel MSR for reporting thread and core counts.
1150 * Judging from the XNU sources, it seems to be introduced in Nehalem. The
1151 * first 16 bits is the thread count. The next 16 bits the core count, except
1152 * on Westmere where it seems it's only the next 4 bits for some reason. */
1153#define MSR_CORE_THREAD_COUNT 0x35
1154
1155/** CPU Feature control. */
1156#define MSR_IA32_FEATURE_CONTROL 0x3A
1157/** Feature control - Lock MSR from writes (R/W0). */
1158#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1159/** Feature control - Enable VMX inside SMX operation (R/WL). */
1160#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1161/** Feature control - Enable VMX outside SMX operation (R/WL). */
1162#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1163/** Feature control - SENTER local functions enable (R/WL). */
1164#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1165#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1166#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1167#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1168#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1169#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1170#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1171/** Feature control - SENTER global enable (R/WL). */
1172#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1173/** Feature control - SGX launch control enable (R/WL). */
1174#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1175/** Feature control - SGX global enable (R/WL). */
1176#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1177/** Feature control - LMCE on (R/WL). */
1178#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1179
1180/** Per-processor TSC adjust MSR. */
1181#define MSR_IA32_TSC_ADJUST 0x3B
1182
1183/** Spectre control register.
1184 * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1185#define MSR_IA32_SPEC_CTRL 0x48
1186/** IBRS - Indirect branch restricted speculation. */
1187#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1188/** STIBP - Single thread indirect branch predictors. */
1189#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1190
1191/** Prediction command register.
1192 * Write only, logical processor scope, no state since write only. */
1193#define MSR_IA32_PRED_CMD 0x49
1194/** IBPB - Indirect branch prediction barrie when written as 1. */
1195#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1196
1197/** BIOS update trigger (microcode update). */
1198#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1199
1200/** BIOS update signature (microcode). */
1201#define MSR_IA32_BIOS_SIGN_ID 0x8B
1202
1203/** SMM monitor control. */
1204#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1205/** SMM control - Valid. */
1206#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1207/** SMM control - VMXOFF unblocks SMI. */
1208#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1209/** SMM control - MSEG base physical address. */
1210#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1211
1212/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1213#define MSR_IA32_SMBASE 0x9E
1214
1215/** General performance counter no. 0. */
1216#define MSR_IA32_PMC0 0xC1
1217/** General performance counter no. 1. */
1218#define MSR_IA32_PMC1 0xC2
1219/** General performance counter no. 2. */
1220#define MSR_IA32_PMC2 0xC3
1221/** General performance counter no. 3. */
1222#define MSR_IA32_PMC3 0xC4
1223
1224/** Nehalem power control. */
1225#define MSR_IA32_PLATFORM_INFO 0xCE
1226
1227/** Get FSB clock status (Intel-specific). */
1228#define MSR_IA32_FSB_CLOCK_STS 0xCD
1229
1230/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1231#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1232
1233/** C0 Maximum Frequency Clock Count */
1234#define MSR_IA32_MPERF 0xE7
1235/** C0 Actual Frequency Clock Count */
1236#define MSR_IA32_APERF 0xE8
1237
1238/** MTRR Capabilities. */
1239#define MSR_IA32_MTRR_CAP 0xFE
1240
1241/** Architecture capabilities (bugfixes).
1242 * @note May move */
1243#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1244/** CPU is no subject to spectre problems. */
1245#define MSR_IA32_ARCH_CAP_F_SPECTRE_FIX RT_BIT_32(0)
1246/** CPU has better IBRS and you can leave it on all the time. */
1247#define MSR_IA32_ARCH_CAP_F_BETTER_IBRS RT_BIT_32(1)
1248
1249/** Cache control/info. */
1250#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1251
1252#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1253/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1254 * R0 SS == CS + 8
1255 * R3 CS == CS + 16
1256 * R3 SS == CS + 24
1257 */
1258#define MSR_IA32_SYSENTER_CS 0x174
1259/** SYSENTER_ESP - the R0 ESP. */
1260#define MSR_IA32_SYSENTER_ESP 0x175
1261/** SYSENTER_EIP - the R0 EIP. */
1262#define MSR_IA32_SYSENTER_EIP 0x176
1263#endif
1264
1265/** Machine Check Global Capabilities Register. */
1266#define MSR_IA32_MCG_CAP 0x179
1267/** Machine Check Global Status Register. */
1268#define MSR_IA32_MCG_STATUS 0x17A
1269/** Machine Check Global Control Register. */
1270#define MSR_IA32_MCG_CTRL 0x17B
1271
1272/** Page Attribute Table. */
1273#define MSR_IA32_CR_PAT 0x277
1274/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1275 * "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1276#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1277
1278/** Performance counter MSRs. (Intel only) */
1279#define MSR_IA32_PERFEVTSEL0 0x186
1280#define MSR_IA32_PERFEVTSEL1 0x187
1281/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1282 * The 16th bit whether flex ratio is being used, in which case bits 15:8
1283 * holds a ratio that Apple takes for TSC granularity.
1284 *
1285 * @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1286#define MSR_FLEX_RATIO 0x194
1287/** Performance state value and starting with Intel core more.
1288 * Apple uses the >=core features to determine TSC granularity on older CPUs. */
1289#define MSR_IA32_PERF_STATUS 0x198
1290#define MSR_IA32_PERF_CTL 0x199
1291#define MSR_IA32_THERM_STATUS 0x19c
1292
1293/** Enable misc. processor features (R/W). */
1294#define MSR_IA32_MISC_ENABLE 0x1A0
1295/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1296#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1297/** Automatic Thermal Control Circuit Enable (R/W). */
1298#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1299/** Performance Monitoring Available (R). */
1300#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1301/** Branch Trace Storage Unavailable (R/O). */
1302#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1303/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1304#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1305/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1306#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1307/** If MONITOR/MWAIT is supported (R/W). */
1308#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1309/** Limit CPUID Maxval to 3 leafs (R/W). */
1310#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1311/** When set to 1, xTPR messages are disabled (R/W). */
1312#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1313/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1314#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1315
1316/** Trace/Profile Resource Control (R/W) */
1317#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1318/** Last branch record. */
1319#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1320/** Branch trace flag (single step on branches). */
1321#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1322/** Performance monitoring pin control (AMD only). */
1323#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1324#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1325#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1326#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1327/** Trace message enable (Intel only). */
1328#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1329/** Branch trace store (Intel only). */
1330#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1331/** Branch trace interrupt (Intel only). */
1332#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1333/** Branch trace off in privileged code (Intel only). */
1334#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1335/** Branch trace off in user code (Intel only). */
1336#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1337/** Freeze LBR on PMI flag (Intel only). */
1338#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1339/** Freeze PERFMON on PMI flag (Intel only). */
1340#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1341/** Freeze while SMM enabled (Intel only). */
1342#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1343/** Advanced debugging of RTM regions (Intel only). */
1344#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1345/** Debug control MSR valid bits (Intel only). */
1346#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \
1347 | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1348 | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1349 | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1350 | MSR_IA32_DEBUGCTL_RTM)
1351
1352/** The number (0..3 or 0..15) of the last branch record register on P4 and
1353 * related Xeons. */
1354#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1355/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1356 * @{ */
1357#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1358#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1359#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1360#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1361/** @} */
1362
1363
1364#define IA32_MTRR_PHYSBASE0 0x200
1365#define IA32_MTRR_PHYSMASK0 0x201
1366#define IA32_MTRR_PHYSBASE1 0x202
1367#define IA32_MTRR_PHYSMASK1 0x203
1368#define IA32_MTRR_PHYSBASE2 0x204
1369#define IA32_MTRR_PHYSMASK2 0x205
1370#define IA32_MTRR_PHYSBASE3 0x206
1371#define IA32_MTRR_PHYSMASK3 0x207
1372#define IA32_MTRR_PHYSBASE4 0x208
1373#define IA32_MTRR_PHYSMASK4 0x209
1374#define IA32_MTRR_PHYSBASE5 0x20a
1375#define IA32_MTRR_PHYSMASK5 0x20b
1376#define IA32_MTRR_PHYSBASE6 0x20c
1377#define IA32_MTRR_PHYSMASK6 0x20d
1378#define IA32_MTRR_PHYSBASE7 0x20e
1379#define IA32_MTRR_PHYSMASK7 0x20f
1380#define IA32_MTRR_PHYSBASE8 0x210
1381#define IA32_MTRR_PHYSMASK8 0x211
1382#define IA32_MTRR_PHYSBASE9 0x212
1383#define IA32_MTRR_PHYSMASK9 0x213
1384
1385/** Fixed range MTRRs.
1386 * @{ */
1387#define IA32_MTRR_FIX64K_00000 0x250
1388#define IA32_MTRR_FIX16K_80000 0x258
1389#define IA32_MTRR_FIX16K_A0000 0x259
1390#define IA32_MTRR_FIX4K_C0000 0x268
1391#define IA32_MTRR_FIX4K_C8000 0x269
1392#define IA32_MTRR_FIX4K_D0000 0x26a
1393#define IA32_MTRR_FIX4K_D8000 0x26b
1394#define IA32_MTRR_FIX4K_E0000 0x26c
1395#define IA32_MTRR_FIX4K_E8000 0x26d
1396#define IA32_MTRR_FIX4K_F0000 0x26e
1397#define IA32_MTRR_FIX4K_F8000 0x26f
1398/** @} */
1399
1400/** MTRR Default Range. */
1401#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1402
1403/** Global performance counter control facilities (Intel only). */
1404#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1405#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1406#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1407
1408/** Precise Event Based sampling (Intel only). */
1409#define MSR_IA32_PEBS_ENABLE 0x3F1
1410
1411#define MSR_IA32_MC0_CTL 0x400
1412#define MSR_IA32_MC0_STATUS 0x401
1413
1414/** Basic VMX information. */
1415#define MSR_IA32_VMX_BASIC 0x480
1416/** Allowed settings for pin-based VM execution controls. */
1417#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1418/** Allowed settings for proc-based VM execution controls. */
1419#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1420/** Allowed settings for the VM-exit controls. */
1421#define MSR_IA32_VMX_EXIT_CTLS 0x483
1422/** Allowed settings for the VM-entry controls. */
1423#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1424/** Misc VMX info. */
1425#define MSR_IA32_VMX_MISC 0x485
1426/** Fixed cleared bits in CR0. */
1427#define MSR_IA32_VMX_CR0_FIXED0 0x486
1428/** Fixed set bits in CR0. */
1429#define MSR_IA32_VMX_CR0_FIXED1 0x487
1430/** Fixed cleared bits in CR4. */
1431#define MSR_IA32_VMX_CR4_FIXED0 0x488
1432/** Fixed set bits in CR4. */
1433#define MSR_IA32_VMX_CR4_FIXED1 0x489
1434/** Information for enumerating fields in the VMCS. */
1435#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1436/** Allowed settings for secondary proc-based VM execution controls */
1437#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1438/** EPT capabilities. */
1439#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1440/** Allowed settings of all pin-based VM execution controls. */
1441#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1442/** Allowed settings of all proc-based VM execution controls. */
1443#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1444/** Allowed settings of all VMX exit controls. */
1445#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1446/** Allowed settings of all VMX entry controls. */
1447#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1448/** Allowed settings for the VM-function controls. */
1449#define MSR_IA32_VMX_VMFUNC 0x491
1450
1451/** Intel PT - Enable and control for trace packet generation. */
1452#define MSR_IA32_RTIT_CTL 0x570
1453
1454/** DS Save Area (R/W). */
1455#define MSR_IA32_DS_AREA 0x600
1456/** Running Average Power Limit (RAPL) power units. */
1457#define MSR_RAPL_POWER_UNIT 0x606
1458
1459/** X2APIC MSR range start. */
1460#define MSR_IA32_X2APIC_START 0x800
1461/** X2APIC MSR - APIC ID Register. */
1462#define MSR_IA32_X2APIC_ID 0x802
1463/** X2APIC MSR - APIC Version Register. */
1464#define MSR_IA32_X2APIC_VERSION 0x803
1465/** X2APIC MSR - Task Priority Register. */
1466#define MSR_IA32_X2APIC_TPR 0x808
1467/** X2APIC MSR - Processor Priority register. */
1468#define MSR_IA32_X2APIC_PPR 0x80A
1469/** X2APIC MSR - End Of Interrupt register. */
1470#define MSR_IA32_X2APIC_EOI 0x80B
1471/** X2APIC MSR - Logical Destination Register. */
1472#define MSR_IA32_X2APIC_LDR 0x80D
1473/** X2APIC MSR - Spurious Interrupt Vector Register. */
1474#define MSR_IA32_X2APIC_SVR 0x80F
1475/** X2APIC MSR - In-service Register (bits 31:0). */
1476#define MSR_IA32_X2APIC_ISR0 0x810
1477/** X2APIC MSR - In-service Register (bits 63:32). */
1478#define MSR_IA32_X2APIC_ISR1 0x811
1479/** X2APIC MSR - In-service Register (bits 95:64). */
1480#define MSR_IA32_X2APIC_ISR2 0x812
1481/** X2APIC MSR - In-service Register (bits 127:96). */
1482#define MSR_IA32_X2APIC_ISR3 0x813
1483/** X2APIC MSR - In-service Register (bits 159:128). */
1484#define MSR_IA32_X2APIC_ISR4 0x814
1485/** X2APIC MSR - In-service Register (bits 191:160). */
1486#define MSR_IA32_X2APIC_ISR5 0x815
1487/** X2APIC MSR - In-service Register (bits 223:192). */
1488#define MSR_IA32_X2APIC_ISR6 0x816
1489/** X2APIC MSR - In-service Register (bits 255:224). */
1490#define MSR_IA32_X2APIC_ISR7 0x817
1491/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1492#define MSR_IA32_X2APIC_TMR0 0x818
1493/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1494#define MSR_IA32_X2APIC_TMR1 0x819
1495/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1496#define MSR_IA32_X2APIC_TMR2 0x81A
1497/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1498#define MSR_IA32_X2APIC_TMR3 0x81B
1499/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1500#define MSR_IA32_X2APIC_TMR4 0x81C
1501/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1502#define MSR_IA32_X2APIC_TMR5 0x81D
1503/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1504#define MSR_IA32_X2APIC_TMR6 0x81E
1505/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1506#define MSR_IA32_X2APIC_TMR7 0x81F
1507/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1508#define MSR_IA32_X2APIC_IRR0 0x820
1509/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1510#define MSR_IA32_X2APIC_IRR1 0x821
1511/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1512#define MSR_IA32_X2APIC_IRR2 0x822
1513/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1514#define MSR_IA32_X2APIC_IRR3 0x823
1515/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1516#define MSR_IA32_X2APIC_IRR4 0x824
1517/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1518#define MSR_IA32_X2APIC_IRR5 0x825
1519/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1520#define MSR_IA32_X2APIC_IRR6 0x826
1521/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1522#define MSR_IA32_X2APIC_IRR7 0x827
1523/** X2APIC MSR - Error Status Register. */
1524#define MSR_IA32_X2APIC_ESR 0x828
1525/** X2APIC MSR - LVT CMCI Register. */
1526#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1527/** X2APIC MSR - Interrupt Command Register. */
1528#define MSR_IA32_X2APIC_ICR 0x830
1529/** X2APIC MSR - LVT Timer Register. */
1530#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1531/** X2APIC MSR - LVT Thermal Sensor Register. */
1532#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1533/** X2APIC MSR - LVT Performance Counter Register. */
1534#define MSR_IA32_X2APIC_LVT_PERF 0x834
1535/** X2APIC MSR - LVT LINT0 Register. */
1536#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1537/** X2APIC MSR - LVT LINT1 Register. */
1538#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1539/** X2APIC MSR - LVT Error Register . */
1540#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1541/** X2APIC MSR - Timer Initial Count Register. */
1542#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1543/** X2APIC MSR - Timer Current Count Register. */
1544#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1545/** X2APIC MSR - Timer Divide Configuration Register. */
1546#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1547/** X2APIC MSR - Self IPI. */
1548#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1549/** X2APIC MSR range end. */
1550#define MSR_IA32_X2APIC_END 0xBFF
1551/** X2APIC MSR - LVT start range. */
1552#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1553/** X2APIC MSR - LVT end range (inclusive). */
1554#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1555
1556/** K6 EFER - Extended Feature Enable Register. */
1557#define MSR_K6_EFER UINT32_C(0xc0000080)
1558/** @todo document EFER */
1559/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1560#define MSR_K6_EFER_SCE RT_BIT_32(0)
1561/** Bit 8 - LME - Long mode enabled. (R/W) */
1562#define MSR_K6_EFER_LME RT_BIT_32(8)
1563#define MSR_K6_EFER_BIT_LME 8 /**< Bit number of MSR_K6_EFER_LME */
1564/** Bit 10 - LMA - Long mode active. (R) */
1565#define MSR_K6_EFER_LMA RT_BIT_32(10)
1566#define MSR_K6_EFER_BIT_LMA 10 /**< Bit number of MSR_K6_EFER_LMA */
1567/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1568#define MSR_K6_EFER_NXE RT_BIT_32(11)
1569#define MSR_K6_EFER_BIT_NXE 11 /**< Bit number of MSR_K6_EFER_NXE */
1570/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1571#define MSR_K6_EFER_SVME RT_BIT_32(12)
1572/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1573#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1574/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1575#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1576/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1577#define MSR_K6_EFER_TCE RT_BIT_32(15)
1578/** K6 STAR - SYSCALL/RET targets. */
1579#define MSR_K6_STAR UINT32_C(0xc0000081)
1580/** Shift value for getting the SYSRET CS and SS value. */
1581#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1582/** Shift value for getting the SYSCALL CS and SS value. */
1583#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1584/** Selector mask for use after shifting. */
1585#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1586/** The mask which give the SYSCALL EIP. */
1587#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1588/** K6 WHCR - Write Handling Control Register. */
1589#define MSR_K6_WHCR UINT32_C(0xc0000082)
1590/** K6 UWCCR - UC/WC Cacheability Control Register. */
1591#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1592/** K6 PSOR - Processor State Observability Register. */
1593#define MSR_K6_PSOR UINT32_C(0xc0000087)
1594/** K6 PFIR - Page Flush/Invalidate Register. */
1595#define MSR_K6_PFIR UINT32_C(0xc0000088)
1596
1597/** Performance counter MSRs. (AMD only) */
1598#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1599#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1600#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1601#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1602#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1603#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1604#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1605#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1606
1607/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1608#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1609/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1610#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1611/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1612#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1613/** K8 FS.base - The 64-bit base FS register. */
1614#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1615/** K8 GS.base - The 64-bit base GS register. */
1616#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1617/** K8 KernelGSbase - Used with SWAPGS. */
1618#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1619/** K8 TSC_AUX - Used with RDTSCP. */
1620#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1621#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1622#define MSR_K8_HWCR UINT32_C(0xc0010015)
1623#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1624#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1625#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1626#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1627#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1628#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1629/** North bridge config? See BIOS & Kernel dev guides for
1630 * details. */
1631#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1632
1633/** Hypertransport interrupt pending register.
1634 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1635#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1636
1637/** SVM Control. */
1638#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1639/** Disables HDT (Hardware Debug Tool) and certain internal debug
1640 * features. */
1641#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1642/** If set, non-intercepted INIT signals are converted to \#SX
1643 * exceptions. */
1644#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1645/** Disables A20 masking. */
1646#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1647/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1648#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1649/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1650 * clear, EFER.SVME can be written normally. */
1651#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1652
1653#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1654#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1655/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1656 * host state during world switch. */
1657#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1658
1659/** @} */
1660
1661
1662/** @name Page Table / Directory / Directory Pointers / L4.
1663 * @{
1664 */
1665
1666/** Page table/directory entry as an unsigned integer. */
1667typedef uint32_t X86PGUINT;
1668/** Pointer to a page table/directory table entry as an unsigned integer. */
1669typedef X86PGUINT *PX86PGUINT;
1670/** Pointer to an const page table/directory table entry as an unsigned integer. */
1671typedef X86PGUINT const *PCX86PGUINT;
1672
1673/** Number of entries in a 32-bit PT/PD. */
1674#define X86_PG_ENTRIES 1024
1675
1676
1677/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1678typedef uint64_t X86PGPAEUINT;
1679/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1680typedef X86PGPAEUINT *PX86PGPAEUINT;
1681/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1682typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1683
1684/** Number of entries in a PAE PT/PD. */
1685#define X86_PG_PAE_ENTRIES 512
1686/** Number of entries in a PAE PDPT. */
1687#define X86_PG_PAE_PDPE_ENTRIES 4
1688
1689/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1690#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1691/** Number of entries in an AMD64 PDPT.
1692 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1693#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1694
1695/** The size of a default page. */
1696#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1697/** The page shift of a default page. */
1698#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1699/** The default page offset mask. */
1700#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1701/** The default page base mask for virtual addresses. */
1702#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1703/** The default page base mask for virtual addresses - 32bit version. */
1704#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1705
1706/** The size of a 4KB page. */
1707#define X86_PAGE_4K_SIZE _4K
1708/** The page shift of a 4KB page. */
1709#define X86_PAGE_4K_SHIFT 12
1710/** The 4KB page offset mask. */
1711#define X86_PAGE_4K_OFFSET_MASK 0xfff
1712/** The 4KB page base mask for virtual addresses. */
1713#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1714/** The 4KB page base mask for virtual addresses - 32bit version. */
1715#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1716
1717/** The size of a 2MB page. */
1718#define X86_PAGE_2M_SIZE _2M
1719/** The page shift of a 2MB page. */
1720#define X86_PAGE_2M_SHIFT 21
1721/** The 2MB page offset mask. */
1722#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1723/** The 2MB page base mask for virtual addresses. */
1724#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1725/** The 2MB page base mask for virtual addresses - 32bit version. */
1726#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1727
1728/** The size of a 4MB page. */
1729#define X86_PAGE_4M_SIZE _4M
1730/** The page shift of a 4MB page. */
1731#define X86_PAGE_4M_SHIFT 22
1732/** The 4MB page offset mask. */
1733#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1734/** The 4MB page base mask for virtual addresses. */
1735#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1736/** The 4MB page base mask for virtual addresses - 32bit version. */
1737#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1738
1739/** The size of a 1GB page. */
1740#define X86_PAGE_1G_SIZE _1G
1741/** The page shift of a 1GB page. */
1742#define X86_PAGE_1G_SHIFT 30
1743/** The 1GB page offset mask. */
1744#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
1745/** The 1GB page base mask for virtual addresses. */
1746#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
1747
1748/**
1749 * Check if the given address is canonical.
1750 */
1751#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1752
1753
1754/** @name Page Table Entry
1755 * @{
1756 */
1757/** Bit 0 - P - Present bit. */
1758#define X86_PTE_BIT_P 0
1759/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1760#define X86_PTE_BIT_RW 1
1761/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1762#define X86_PTE_BIT_US 2
1763/** Bit 3 - PWT - Page level write thru bit. */
1764#define X86_PTE_BIT_PWT 3
1765/** Bit 4 - PCD - Page level cache disable bit. */
1766#define X86_PTE_BIT_PCD 4
1767/** Bit 5 - A - Access bit. */
1768#define X86_PTE_BIT_A 5
1769/** Bit 6 - D - Dirty bit. */
1770#define X86_PTE_BIT_D 6
1771/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1772#define X86_PTE_BIT_PAT 7
1773/** Bit 8 - G - Global flag. */
1774#define X86_PTE_BIT_G 8
1775/** Bits 63 - NX - PAE/LM - No execution flag. */
1776#define X86_PTE_PAE_BIT_NX 63
1777
1778/** Bit 0 - P - Present bit mask. */
1779#define X86_PTE_P RT_BIT_32(0)
1780/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1781#define X86_PTE_RW RT_BIT_32(1)
1782/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1783#define X86_PTE_US RT_BIT_32(2)
1784/** Bit 3 - PWT - Page level write thru bit mask. */
1785#define X86_PTE_PWT RT_BIT_32(3)
1786/** Bit 4 - PCD - Page level cache disable bit mask. */
1787#define X86_PTE_PCD RT_BIT_32(4)
1788/** Bit 5 - A - Access bit mask. */
1789#define X86_PTE_A RT_BIT_32(5)
1790/** Bit 6 - D - Dirty bit mask. */
1791#define X86_PTE_D RT_BIT_32(6)
1792/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1793#define X86_PTE_PAT RT_BIT_32(7)
1794/** Bit 8 - G - Global bit mask. */
1795#define X86_PTE_G RT_BIT_32(8)
1796
1797/** Bits 9-11 - - Available for use to system software. */
1798#define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1799/** Bits 12-31 - - Physical Page number of the next level. */
1800#define X86_PTE_PG_MASK ( 0xfffff000 )
1801
1802/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1803#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1804/** Bits 63 - NX - PAE/LM - No execution flag. */
1805#define X86_PTE_PAE_NX RT_BIT_64(63)
1806/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1807#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1808/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1809#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1810/** No bits - - LM - MBZ bits when NX is active. */
1811#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1812/** Bits 63 - - LM - MBZ bits when no NX. */
1813#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1814
1815/**
1816 * Page table entry.
1817 */
1818typedef struct X86PTEBITS
1819{
1820 /** Flags whether(=1) or not the page is present. */
1821 uint32_t u1Present : 1;
1822 /** Read(=0) / Write(=1) flag. */
1823 uint32_t u1Write : 1;
1824 /** User(=1) / Supervisor (=0) flag. */
1825 uint32_t u1User : 1;
1826 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1827 uint32_t u1WriteThru : 1;
1828 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1829 uint32_t u1CacheDisable : 1;
1830 /** Accessed flag.
1831 * Indicates that the page have been read or written to. */
1832 uint32_t u1Accessed : 1;
1833 /** Dirty flag.
1834 * Indicates that the page has been written to. */
1835 uint32_t u1Dirty : 1;
1836 /** Reserved / If PAT enabled, bit 2 of the index. */
1837 uint32_t u1PAT : 1;
1838 /** Global flag. (Ignored in all but final level.) */
1839 uint32_t u1Global : 1;
1840 /** Available for use to system software. */
1841 uint32_t u3Available : 3;
1842 /** Physical Page number of the next level. */
1843 uint32_t u20PageNo : 20;
1844} X86PTEBITS;
1845#ifndef VBOX_FOR_DTRACE_LIB
1846AssertCompileSize(X86PTEBITS, 4);
1847#endif
1848/** Pointer to a page table entry. */
1849typedef X86PTEBITS *PX86PTEBITS;
1850/** Pointer to a const page table entry. */
1851typedef const X86PTEBITS *PCX86PTEBITS;
1852
1853/**
1854 * Page table entry.
1855 */
1856typedef union X86PTE
1857{
1858 /** Unsigned integer view */
1859 X86PGUINT u;
1860 /** Bit field view. */
1861 X86PTEBITS n;
1862 /** 32-bit view. */
1863 uint32_t au32[1];
1864 /** 16-bit view. */
1865 uint16_t au16[2];
1866 /** 8-bit view. */
1867 uint8_t au8[4];
1868} X86PTE;
1869#ifndef VBOX_FOR_DTRACE_LIB
1870AssertCompileSize(X86PTE, 4);
1871#endif
1872/** Pointer to a page table entry. */
1873typedef X86PTE *PX86PTE;
1874/** Pointer to a const page table entry. */
1875typedef const X86PTE *PCX86PTE;
1876
1877
1878/**
1879 * PAE page table entry.
1880 */
1881typedef struct X86PTEPAEBITS
1882{
1883 /** Flags whether(=1) or not the page is present. */
1884 uint32_t u1Present : 1;
1885 /** Read(=0) / Write(=1) flag. */
1886 uint32_t u1Write : 1;
1887 /** User(=1) / Supervisor(=0) flag. */
1888 uint32_t u1User : 1;
1889 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1890 uint32_t u1WriteThru : 1;
1891 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1892 uint32_t u1CacheDisable : 1;
1893 /** Accessed flag.
1894 * Indicates that the page have been read or written to. */
1895 uint32_t u1Accessed : 1;
1896 /** Dirty flag.
1897 * Indicates that the page has been written to. */
1898 uint32_t u1Dirty : 1;
1899 /** Reserved / If PAT enabled, bit 2 of the index. */
1900 uint32_t u1PAT : 1;
1901 /** Global flag. (Ignored in all but final level.) */
1902 uint32_t u1Global : 1;
1903 /** Available for use to system software. */
1904 uint32_t u3Available : 3;
1905 /** Physical Page number of the next level - Low Part. Don't use this. */
1906 uint32_t u20PageNoLow : 20;
1907 /** Physical Page number of the next level - High Part. Don't use this. */
1908 uint32_t u20PageNoHigh : 20;
1909 /** MBZ bits */
1910 uint32_t u11Reserved : 11;
1911 /** No Execute flag. */
1912 uint32_t u1NoExecute : 1;
1913} X86PTEPAEBITS;
1914#ifndef VBOX_FOR_DTRACE_LIB
1915AssertCompileSize(X86PTEPAEBITS, 8);
1916#endif
1917/** Pointer to a page table entry. */
1918typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1919/** Pointer to a page table entry. */
1920typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1921
1922/**
1923 * PAE Page table entry.
1924 */
1925typedef union X86PTEPAE
1926{
1927 /** Unsigned integer view */
1928 X86PGPAEUINT u;
1929 /** Bit field view. */
1930 X86PTEPAEBITS n;
1931 /** 32-bit view. */
1932 uint32_t au32[2];
1933 /** 16-bit view. */
1934 uint16_t au16[4];
1935 /** 8-bit view. */
1936 uint8_t au8[8];
1937} X86PTEPAE;
1938#ifndef VBOX_FOR_DTRACE_LIB
1939AssertCompileSize(X86PTEPAE, 8);
1940#endif
1941/** Pointer to a PAE page table entry. */
1942typedef X86PTEPAE *PX86PTEPAE;
1943/** Pointer to a const PAE page table entry. */
1944typedef const X86PTEPAE *PCX86PTEPAE;
1945/** @} */
1946
1947/**
1948 * Page table.
1949 */
1950typedef struct X86PT
1951{
1952 /** PTE Array. */
1953 X86PTE a[X86_PG_ENTRIES];
1954} X86PT;
1955#ifndef VBOX_FOR_DTRACE_LIB
1956AssertCompileSize(X86PT, 4096);
1957#endif
1958/** Pointer to a page table. */
1959typedef X86PT *PX86PT;
1960/** Pointer to a const page table. */
1961typedef const X86PT *PCX86PT;
1962
1963/** The page shift to get the PT index. */
1964#define X86_PT_SHIFT 12
1965/** The PT index mask (apply to a shifted page address). */
1966#define X86_PT_MASK 0x3ff
1967
1968
1969/**
1970 * Page directory.
1971 */
1972typedef struct X86PTPAE
1973{
1974 /** PTE Array. */
1975 X86PTEPAE a[X86_PG_PAE_ENTRIES];
1976} X86PTPAE;
1977#ifndef VBOX_FOR_DTRACE_LIB
1978AssertCompileSize(X86PTPAE, 4096);
1979#endif
1980/** Pointer to a page table. */
1981typedef X86PTPAE *PX86PTPAE;
1982/** Pointer to a const page table. */
1983typedef const X86PTPAE *PCX86PTPAE;
1984
1985/** The page shift to get the PA PTE index. */
1986#define X86_PT_PAE_SHIFT 12
1987/** The PAE PT index mask (apply to a shifted page address). */
1988#define X86_PT_PAE_MASK 0x1ff
1989
1990
1991/** @name 4KB Page Directory Entry
1992 * @{
1993 */
1994/** Bit 0 - P - Present bit. */
1995#define X86_PDE_P RT_BIT_32(0)
1996/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1997#define X86_PDE_RW RT_BIT_32(1)
1998/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1999#define X86_PDE_US RT_BIT_32(2)
2000/** Bit 3 - PWT - Page level write thru bit. */
2001#define X86_PDE_PWT RT_BIT_32(3)
2002/** Bit 4 - PCD - Page level cache disable bit. */
2003#define X86_PDE_PCD RT_BIT_32(4)
2004/** Bit 5 - A - Access bit. */
2005#define X86_PDE_A RT_BIT_32(5)
2006/** Bit 7 - PS - Page size attribute.
2007 * Clear mean 4KB pages, set means large pages (2/4MB). */
2008#define X86_PDE_PS RT_BIT_32(7)
2009/** Bits 9-11 - - Available for use to system software. */
2010#define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2011/** Bits 12-31 - - Physical Page number of the next level. */
2012#define X86_PDE_PG_MASK ( 0xfffff000 )
2013
2014/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2015#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2016/** Bits 63 - NX - PAE/LM - No execution flag. */
2017#define X86_PDE_PAE_NX RT_BIT_64(63)
2018/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2019#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2020/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2021#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2022/** Bit 7 - - LM - MBZ bits when NX is active. */
2023#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2024/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2025#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2026
2027/**
2028 * Page directory entry.
2029 */
2030typedef struct X86PDEBITS
2031{
2032 /** Flags whether(=1) or not the page is present. */
2033 uint32_t u1Present : 1;
2034 /** Read(=0) / Write(=1) flag. */
2035 uint32_t u1Write : 1;
2036 /** User(=1) / Supervisor (=0) flag. */
2037 uint32_t u1User : 1;
2038 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2039 uint32_t u1WriteThru : 1;
2040 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2041 uint32_t u1CacheDisable : 1;
2042 /** Accessed flag.
2043 * Indicates that the page has been read or written to. */
2044 uint32_t u1Accessed : 1;
2045 /** Reserved / Ignored (dirty bit). */
2046 uint32_t u1Reserved0 : 1;
2047 /** Size bit if PSE is enabled - in any event it's 0. */
2048 uint32_t u1Size : 1;
2049 /** Reserved / Ignored (global bit). */
2050 uint32_t u1Reserved1 : 1;
2051 /** Available for use to system software. */
2052 uint32_t u3Available : 3;
2053 /** Physical Page number of the next level. */
2054 uint32_t u20PageNo : 20;
2055} X86PDEBITS;
2056#ifndef VBOX_FOR_DTRACE_LIB
2057AssertCompileSize(X86PDEBITS, 4);
2058#endif
2059/** Pointer to a page directory entry. */
2060typedef X86PDEBITS *PX86PDEBITS;
2061/** Pointer to a const page directory entry. */
2062typedef const X86PDEBITS *PCX86PDEBITS;
2063
2064
2065/**
2066 * PAE page directory entry.
2067 */
2068typedef struct X86PDEPAEBITS
2069{
2070 /** Flags whether(=1) or not the page is present. */
2071 uint32_t u1Present : 1;
2072 /** Read(=0) / Write(=1) flag. */
2073 uint32_t u1Write : 1;
2074 /** User(=1) / Supervisor (=0) flag. */
2075 uint32_t u1User : 1;
2076 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2077 uint32_t u1WriteThru : 1;
2078 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2079 uint32_t u1CacheDisable : 1;
2080 /** Accessed flag.
2081 * Indicates that the page has been read or written to. */
2082 uint32_t u1Accessed : 1;
2083 /** Reserved / Ignored (dirty bit). */
2084 uint32_t u1Reserved0 : 1;
2085 /** Size bit if PSE is enabled - in any event it's 0. */
2086 uint32_t u1Size : 1;
2087 /** Reserved / Ignored (global bit). / */
2088 uint32_t u1Reserved1 : 1;
2089 /** Available for use to system software. */
2090 uint32_t u3Available : 3;
2091 /** Physical Page number of the next level - Low Part. Don't use! */
2092 uint32_t u20PageNoLow : 20;
2093 /** Physical Page number of the next level - High Part. Don't use! */
2094 uint32_t u20PageNoHigh : 20;
2095 /** MBZ bits */
2096 uint32_t u11Reserved : 11;
2097 /** No Execute flag. */
2098 uint32_t u1NoExecute : 1;
2099} X86PDEPAEBITS;
2100#ifndef VBOX_FOR_DTRACE_LIB
2101AssertCompileSize(X86PDEPAEBITS, 8);
2102#endif
2103/** Pointer to a page directory entry. */
2104typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2105/** Pointer to a const page directory entry. */
2106typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2107
2108/** @} */
2109
2110
2111/** @name 2/4MB Page Directory Entry
2112 * @{
2113 */
2114/** Bit 0 - P - Present bit. */
2115#define X86_PDE4M_P RT_BIT_32(0)
2116/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2117#define X86_PDE4M_RW RT_BIT_32(1)
2118/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2119#define X86_PDE4M_US RT_BIT_32(2)
2120/** Bit 3 - PWT - Page level write thru bit. */
2121#define X86_PDE4M_PWT RT_BIT_32(3)
2122/** Bit 4 - PCD - Page level cache disable bit. */
2123#define X86_PDE4M_PCD RT_BIT_32(4)
2124/** Bit 5 - A - Access bit. */
2125#define X86_PDE4M_A RT_BIT_32(5)
2126/** Bit 6 - D - Dirty bit. */
2127#define X86_PDE4M_D RT_BIT_32(6)
2128/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2129#define X86_PDE4M_PS RT_BIT_32(7)
2130/** Bit 8 - G - Global flag. */
2131#define X86_PDE4M_G RT_BIT_32(8)
2132/** Bits 9-11 - AVL - Available for use to system software. */
2133#define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2134/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2135#define X86_PDE4M_PAT RT_BIT_32(12)
2136/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2137#define X86_PDE4M_PAT_SHIFT (12 - 7)
2138/** Bits 22-31 - - Physical Page number. */
2139#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2140/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2141#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2142/** The number of bits to the high part of the page number. */
2143#define X86_PDE4M_PG_HIGH_SHIFT 19
2144/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2145#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2146
2147/** Bits 21-51 - - PAE/LM - Physical Page number.
2148 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2149#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2150/** Bits 63 - NX - PAE/LM - No execution flag. */
2151#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2152/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2153#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2154/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2155#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2156/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2157#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2158/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2159#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2160
2161/**
2162 * 4MB page directory entry.
2163 */
2164typedef struct X86PDE4MBITS
2165{
2166 /** Flags whether(=1) or not the page is present. */
2167 uint32_t u1Present : 1;
2168 /** Read(=0) / Write(=1) flag. */
2169 uint32_t u1Write : 1;
2170 /** User(=1) / Supervisor (=0) flag. */
2171 uint32_t u1User : 1;
2172 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2173 uint32_t u1WriteThru : 1;
2174 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2175 uint32_t u1CacheDisable : 1;
2176 /** Accessed flag.
2177 * Indicates that the page have been read or written to. */
2178 uint32_t u1Accessed : 1;
2179 /** Dirty flag.
2180 * Indicates that the page has been written to. */
2181 uint32_t u1Dirty : 1;
2182 /** Page size flag - always 1 for 4MB entries. */
2183 uint32_t u1Size : 1;
2184 /** Global flag. */
2185 uint32_t u1Global : 1;
2186 /** Available for use to system software. */
2187 uint32_t u3Available : 3;
2188 /** Reserved / If PAT enabled, bit 2 of the index. */
2189 uint32_t u1PAT : 1;
2190 /** Bits 32-39 of the page number on AMD64.
2191 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2192 uint32_t u8PageNoHigh : 8;
2193 /** Reserved. */
2194 uint32_t u1Reserved : 1;
2195 /** Physical Page number of the page. */
2196 uint32_t u10PageNo : 10;
2197} X86PDE4MBITS;
2198#ifndef VBOX_FOR_DTRACE_LIB
2199AssertCompileSize(X86PDE4MBITS, 4);
2200#endif
2201/** Pointer to a page table entry. */
2202typedef X86PDE4MBITS *PX86PDE4MBITS;
2203/** Pointer to a const page table entry. */
2204typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2205
2206
2207/**
2208 * 2MB PAE page directory entry.
2209 */
2210typedef struct X86PDE2MPAEBITS
2211{
2212 /** Flags whether(=1) or not the page is present. */
2213 uint32_t u1Present : 1;
2214 /** Read(=0) / Write(=1) flag. */
2215 uint32_t u1Write : 1;
2216 /** User(=1) / Supervisor(=0) flag. */
2217 uint32_t u1User : 1;
2218 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2219 uint32_t u1WriteThru : 1;
2220 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2221 uint32_t u1CacheDisable : 1;
2222 /** Accessed flag.
2223 * Indicates that the page have been read or written to. */
2224 uint32_t u1Accessed : 1;
2225 /** Dirty flag.
2226 * Indicates that the page has been written to. */
2227 uint32_t u1Dirty : 1;
2228 /** Page size flag - always 1 for 2MB entries. */
2229 uint32_t u1Size : 1;
2230 /** Global flag. */
2231 uint32_t u1Global : 1;
2232 /** Available for use to system software. */
2233 uint32_t u3Available : 3;
2234 /** Reserved / If PAT enabled, bit 2 of the index. */
2235 uint32_t u1PAT : 1;
2236 /** Reserved. */
2237 uint32_t u9Reserved : 9;
2238 /** Physical Page number of the next level - Low part. Don't use! */
2239 uint32_t u10PageNoLow : 10;
2240 /** Physical Page number of the next level - High part. Don't use! */
2241 uint32_t u20PageNoHigh : 20;
2242 /** MBZ bits */
2243 uint32_t u11Reserved : 11;
2244 /** No Execute flag. */
2245 uint32_t u1NoExecute : 1;
2246} X86PDE2MPAEBITS;
2247#ifndef VBOX_FOR_DTRACE_LIB
2248AssertCompileSize(X86PDE2MPAEBITS, 8);
2249#endif
2250/** Pointer to a 2MB PAE page table entry. */
2251typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2252/** Pointer to a 2MB PAE page table entry. */
2253typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2254
2255/** @} */
2256
2257/**
2258 * Page directory entry.
2259 */
2260typedef union X86PDE
2261{
2262 /** Unsigned integer view. */
2263 X86PGUINT u;
2264 /** Normal view. */
2265 X86PDEBITS n;
2266 /** 4MB view (big). */
2267 X86PDE4MBITS b;
2268 /** 8 bit unsigned integer view. */
2269 uint8_t au8[4];
2270 /** 16 bit unsigned integer view. */
2271 uint16_t au16[2];
2272 /** 32 bit unsigned integer view. */
2273 uint32_t au32[1];
2274} X86PDE;
2275#ifndef VBOX_FOR_DTRACE_LIB
2276AssertCompileSize(X86PDE, 4);
2277#endif
2278/** Pointer to a page directory entry. */
2279typedef X86PDE *PX86PDE;
2280/** Pointer to a const page directory entry. */
2281typedef const X86PDE *PCX86PDE;
2282
2283/**
2284 * PAE page directory entry.
2285 */
2286typedef union X86PDEPAE
2287{
2288 /** Unsigned integer view. */
2289 X86PGPAEUINT u;
2290 /** Normal view. */
2291 X86PDEPAEBITS n;
2292 /** 2MB page view (big). */
2293 X86PDE2MPAEBITS b;
2294 /** 8 bit unsigned integer view. */
2295 uint8_t au8[8];
2296 /** 16 bit unsigned integer view. */
2297 uint16_t au16[4];
2298 /** 32 bit unsigned integer view. */
2299 uint32_t au32[2];
2300} X86PDEPAE;
2301#ifndef VBOX_FOR_DTRACE_LIB
2302AssertCompileSize(X86PDEPAE, 8);
2303#endif
2304/** Pointer to a page directory entry. */
2305typedef X86PDEPAE *PX86PDEPAE;
2306/** Pointer to a const page directory entry. */
2307typedef const X86PDEPAE *PCX86PDEPAE;
2308
2309/**
2310 * Page directory.
2311 */
2312typedef struct X86PD
2313{
2314 /** PDE Array. */
2315 X86PDE a[X86_PG_ENTRIES];
2316} X86PD;
2317#ifndef VBOX_FOR_DTRACE_LIB
2318AssertCompileSize(X86PD, 4096);
2319#endif
2320/** Pointer to a page directory. */
2321typedef X86PD *PX86PD;
2322/** Pointer to a const page directory. */
2323typedef const X86PD *PCX86PD;
2324
2325/** The page shift to get the PD index. */
2326#define X86_PD_SHIFT 22
2327/** The PD index mask (apply to a shifted page address). */
2328#define X86_PD_MASK 0x3ff
2329
2330
2331/**
2332 * PAE page directory.
2333 */
2334typedef struct X86PDPAE
2335{
2336 /** PDE Array. */
2337 X86PDEPAE a[X86_PG_PAE_ENTRIES];
2338} X86PDPAE;
2339#ifndef VBOX_FOR_DTRACE_LIB
2340AssertCompileSize(X86PDPAE, 4096);
2341#endif
2342/** Pointer to a PAE page directory. */
2343typedef X86PDPAE *PX86PDPAE;
2344/** Pointer to a const PAE page directory. */
2345typedef const X86PDPAE *PCX86PDPAE;
2346
2347/** The page shift to get the PAE PD index. */
2348#define X86_PD_PAE_SHIFT 21
2349/** The PAE PD index mask (apply to a shifted page address). */
2350#define X86_PD_PAE_MASK 0x1ff
2351
2352
2353/** @name Page Directory Pointer Table Entry (PAE)
2354 * @{
2355 */
2356/** Bit 0 - P - Present bit. */
2357#define X86_PDPE_P RT_BIT_32(0)
2358/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2359#define X86_PDPE_RW RT_BIT_32(1)
2360/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2361#define X86_PDPE_US RT_BIT_32(2)
2362/** Bit 3 - PWT - Page level write thru bit. */
2363#define X86_PDPE_PWT RT_BIT_32(3)
2364/** Bit 4 - PCD - Page level cache disable bit. */
2365#define X86_PDPE_PCD RT_BIT_32(4)
2366/** Bit 5 - A - Access bit. Long Mode only. */
2367#define X86_PDPE_A RT_BIT_32(5)
2368/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2369#define X86_PDPE_LM_PS RT_BIT_32(7)
2370/** Bits 9-11 - - Available for use to system software. */
2371#define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2372/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2373#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2374/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2375#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2376/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2377#define X86_PDPE_LM_NX RT_BIT_64(63)
2378/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2379#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2380/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2381#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2382/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2383#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2384/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2385#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2386
2387
2388/**
2389 * Page directory pointer table entry.
2390 */
2391typedef struct X86PDPEBITS
2392{
2393 /** Flags whether(=1) or not the page is present. */
2394 uint32_t u1Present : 1;
2395 /** Chunk of reserved bits. */
2396 uint32_t u2Reserved : 2;
2397 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2398 uint32_t u1WriteThru : 1;
2399 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2400 uint32_t u1CacheDisable : 1;
2401 /** Chunk of reserved bits. */
2402 uint32_t u4Reserved : 4;
2403 /** Available for use to system software. */
2404 uint32_t u3Available : 3;
2405 /** Physical Page number of the next level - Low Part. Don't use! */
2406 uint32_t u20PageNoLow : 20;
2407 /** Physical Page number of the next level - High Part. Don't use! */
2408 uint32_t u20PageNoHigh : 20;
2409 /** MBZ bits */
2410 uint32_t u12Reserved : 12;
2411} X86PDPEBITS;
2412#ifndef VBOX_FOR_DTRACE_LIB
2413AssertCompileSize(X86PDPEBITS, 8);
2414#endif
2415/** Pointer to a page directory pointer table entry. */
2416typedef X86PDPEBITS *PX86PTPEBITS;
2417/** Pointer to a const page directory pointer table entry. */
2418typedef const X86PDPEBITS *PCX86PTPEBITS;
2419
2420/**
2421 * Page directory pointer table entry. AMD64 version
2422 */
2423typedef struct X86PDPEAMD64BITS
2424{
2425 /** Flags whether(=1) or not the page is present. */
2426 uint32_t u1Present : 1;
2427 /** Read(=0) / Write(=1) flag. */
2428 uint32_t u1Write : 1;
2429 /** User(=1) / Supervisor (=0) flag. */
2430 uint32_t u1User : 1;
2431 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2432 uint32_t u1WriteThru : 1;
2433 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2434 uint32_t u1CacheDisable : 1;
2435 /** Accessed flag.
2436 * Indicates that the page have been read or written to. */
2437 uint32_t u1Accessed : 1;
2438 /** Chunk of reserved bits. */
2439 uint32_t u3Reserved : 3;
2440 /** Available for use to system software. */
2441 uint32_t u3Available : 3;
2442 /** Physical Page number of the next level - Low Part. Don't use! */
2443 uint32_t u20PageNoLow : 20;
2444 /** Physical Page number of the next level - High Part. Don't use! */
2445 uint32_t u20PageNoHigh : 20;
2446 /** MBZ bits */
2447 uint32_t u11Reserved : 11;
2448 /** No Execute flag. */
2449 uint32_t u1NoExecute : 1;
2450} X86PDPEAMD64BITS;
2451#ifndef VBOX_FOR_DTRACE_LIB
2452AssertCompileSize(X86PDPEAMD64BITS, 8);
2453#endif
2454/** Pointer to a page directory pointer table entry. */
2455typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2456/** Pointer to a const page directory pointer table entry. */
2457typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2458
2459/**
2460 * Page directory pointer table entry for 1GB page. (AMD64 only)
2461 */
2462typedef struct X86PDPE1GB
2463{
2464 /** 0: Flags whether(=1) or not the page is present. */
2465 uint32_t u1Present : 1;
2466 /** 1: Read(=0) / Write(=1) flag. */
2467 uint32_t u1Write : 1;
2468 /** 2: User(=1) / Supervisor (=0) flag. */
2469 uint32_t u1User : 1;
2470 /** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2471 uint32_t u1WriteThru : 1;
2472 /** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2473 uint32_t u1CacheDisable : 1;
2474 /** 5: Accessed flag.
2475 * Indicates that the page have been read or written to. */
2476 uint32_t u1Accessed : 1;
2477 /** 6: Dirty flag for 1GB pages. */
2478 uint32_t u1Dirty : 1;
2479 /** 7: Indicates 1GB page if set. */
2480 uint32_t u1Size : 1;
2481 /** 8: Global 1GB page. */
2482 uint32_t u1Global: 1;
2483 /** 9-11: Available for use to system software. */
2484 uint32_t u3Available : 3;
2485 /** 12: PAT bit for 1GB page. */
2486 uint32_t u1PAT : 1;
2487 /** 13-29: MBZ bits. */
2488 uint32_t u17Reserved : 17;
2489 /** 30-31: Physical page number - Low Part. Don't use! */
2490 uint32_t u2PageNoLow : 2;
2491 /** 32-51: Physical Page number of the next level - High Part. Don't use! */
2492 uint32_t u20PageNoHigh : 20;
2493 /** 52-62: MBZ bits */
2494 uint32_t u11Reserved : 11;
2495 /** 63: No Execute flag. */
2496 uint32_t u1NoExecute : 1;
2497} X86PDPE1GB;
2498#ifndef VBOX_FOR_DTRACE_LIB
2499AssertCompileSize(X86PDPE1GB, 8);
2500#endif
2501/** Pointer to a page directory pointer table entry for a 1GB page. */
2502typedef X86PDPE1GB *PX86PDPE1GB;
2503/** Pointer to a const page directory pointer table entry for a 1GB page. */
2504typedef const X86PDPE1GB *PCX86PDPE1GB;
2505
2506/**
2507 * Page directory pointer table entry.
2508 */
2509typedef union X86PDPE
2510{
2511 /** Unsigned integer view. */
2512 X86PGPAEUINT u;
2513 /** Normal view. */
2514 X86PDPEBITS n;
2515 /** AMD64 view. */
2516 X86PDPEAMD64BITS lm;
2517 /** AMD64 big view. */
2518 X86PDPE1GB b;
2519 /** 8 bit unsigned integer view. */
2520 uint8_t au8[8];
2521 /** 16 bit unsigned integer view. */
2522 uint16_t au16[4];
2523 /** 32 bit unsigned integer view. */
2524 uint32_t au32[2];
2525} X86PDPE;
2526#ifndef VBOX_FOR_DTRACE_LIB
2527AssertCompileSize(X86PDPE, 8);
2528#endif
2529/** Pointer to a page directory pointer table entry. */
2530typedef X86PDPE *PX86PDPE;
2531/** Pointer to a const page directory pointer table entry. */
2532typedef const X86PDPE *PCX86PDPE;
2533
2534
2535/**
2536 * Page directory pointer table.
2537 */
2538typedef struct X86PDPT
2539{
2540 /** PDE Array. */
2541 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2542} X86PDPT;
2543#ifndef VBOX_FOR_DTRACE_LIB
2544AssertCompileSize(X86PDPT, 4096);
2545#endif
2546/** Pointer to a page directory pointer table. */
2547typedef X86PDPT *PX86PDPT;
2548/** Pointer to a const page directory pointer table. */
2549typedef const X86PDPT *PCX86PDPT;
2550
2551/** The page shift to get the PDPT index. */
2552#define X86_PDPT_SHIFT 30
2553/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2554#define X86_PDPT_MASK_PAE 0x3
2555/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2556#define X86_PDPT_MASK_AMD64 0x1ff
2557
2558/** @} */
2559
2560
2561/** @name Page Map Level-4 Entry (Long Mode PAE)
2562 * @{
2563 */
2564/** Bit 0 - P - Present bit. */
2565#define X86_PML4E_P RT_BIT_32(0)
2566/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2567#define X86_PML4E_RW RT_BIT_32(1)
2568/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2569#define X86_PML4E_US RT_BIT_32(2)
2570/** Bit 3 - PWT - Page level write thru bit. */
2571#define X86_PML4E_PWT RT_BIT_32(3)
2572/** Bit 4 - PCD - Page level cache disable bit. */
2573#define X86_PML4E_PCD RT_BIT_32(4)
2574/** Bit 5 - A - Access bit. */
2575#define X86_PML4E_A RT_BIT_32(5)
2576/** Bits 9-11 - - Available for use to system software. */
2577#define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2578/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2579#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2580/** Bits 8, 7 - - MBZ bits when NX is active. */
2581#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2582/** Bits 63, 7 - - MBZ bits when no NX. */
2583#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2584/** Bits 63 - NX - PAE - No execution flag. */
2585#define X86_PML4E_NX RT_BIT_64(63)
2586
2587/**
2588 * Page Map Level-4 Entry
2589 */
2590typedef struct X86PML4EBITS
2591{
2592 /** Flags whether(=1) or not the page is present. */
2593 uint32_t u1Present : 1;
2594 /** Read(=0) / Write(=1) flag. */
2595 uint32_t u1Write : 1;
2596 /** User(=1) / Supervisor (=0) flag. */
2597 uint32_t u1User : 1;
2598 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2599 uint32_t u1WriteThru : 1;
2600 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2601 uint32_t u1CacheDisable : 1;
2602 /** Accessed flag.
2603 * Indicates that the page have been read or written to. */
2604 uint32_t u1Accessed : 1;
2605 /** Chunk of reserved bits. */
2606 uint32_t u3Reserved : 3;
2607 /** Available for use to system software. */
2608 uint32_t u3Available : 3;
2609 /** Physical Page number of the next level - Low Part. Don't use! */
2610 uint32_t u20PageNoLow : 20;
2611 /** Physical Page number of the next level - High Part. Don't use! */
2612 uint32_t u20PageNoHigh : 20;
2613 /** MBZ bits */
2614 uint32_t u11Reserved : 11;
2615 /** No Execute flag. */
2616 uint32_t u1NoExecute : 1;
2617} X86PML4EBITS;
2618#ifndef VBOX_FOR_DTRACE_LIB
2619AssertCompileSize(X86PML4EBITS, 8);
2620#endif
2621/** Pointer to a page map level-4 entry. */
2622typedef X86PML4EBITS *PX86PML4EBITS;
2623/** Pointer to a const page map level-4 entry. */
2624typedef const X86PML4EBITS *PCX86PML4EBITS;
2625
2626/**
2627 * Page Map Level-4 Entry.
2628 */
2629typedef union X86PML4E
2630{
2631 /** Unsigned integer view. */
2632 X86PGPAEUINT u;
2633 /** Normal view. */
2634 X86PML4EBITS n;
2635 /** 8 bit unsigned integer view. */
2636 uint8_t au8[8];
2637 /** 16 bit unsigned integer view. */
2638 uint16_t au16[4];
2639 /** 32 bit unsigned integer view. */
2640 uint32_t au32[2];
2641} X86PML4E;
2642#ifndef VBOX_FOR_DTRACE_LIB
2643AssertCompileSize(X86PML4E, 8);
2644#endif
2645/** Pointer to a page map level-4 entry. */
2646typedef X86PML4E *PX86PML4E;
2647/** Pointer to a const page map level-4 entry. */
2648typedef const X86PML4E *PCX86PML4E;
2649
2650
2651/**
2652 * Page Map Level-4.
2653 */
2654typedef struct X86PML4
2655{
2656 /** PDE Array. */
2657 X86PML4E a[X86_PG_PAE_ENTRIES];
2658} X86PML4;
2659#ifndef VBOX_FOR_DTRACE_LIB
2660AssertCompileSize(X86PML4, 4096);
2661#endif
2662/** Pointer to a page map level-4. */
2663typedef X86PML4 *PX86PML4;
2664/** Pointer to a const page map level-4. */
2665typedef const X86PML4 *PCX86PML4;
2666
2667/** The page shift to get the PML4 index. */
2668#define X86_PML4_SHIFT 39
2669/** The PML4 index mask (apply to a shifted page address). */
2670#define X86_PML4_MASK 0x1ff
2671
2672/** @} */
2673
2674/** @} */
2675
2676/**
2677 * Intel PCID invalidation types.
2678 */
2679/** Individual address invalidation. */
2680#define X86_INVPCID_TYPE_INDV_ADDR 0
2681/** Single-context invalidation. */
2682#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2683/** All-context including globals invalidation. */
2684#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2685/** All-context excluding globals invalidation. */
2686#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2687/** The maximum valid invalidation type value. */
2688#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2689
2690/**
2691 * 32-bit protected mode FSTENV image.
2692 */
2693typedef struct X86FSTENV32P
2694{
2695 uint16_t FCW;
2696 uint16_t padding1;
2697 uint16_t FSW;
2698 uint16_t padding2;
2699 uint16_t FTW;
2700 uint16_t padding3;
2701 uint32_t FPUIP;
2702 uint16_t FPUCS;
2703 uint16_t FOP;
2704 uint32_t FPUDP;
2705 uint16_t FPUDS;
2706 uint16_t padding4;
2707} X86FSTENV32P;
2708/** Pointer to a 32-bit protected mode FSTENV image. */
2709typedef X86FSTENV32P *PX86FSTENV32P;
2710/** Pointer to a const 32-bit protected mode FSTENV image. */
2711typedef X86FSTENV32P const *PCX86FSTENV32P;
2712
2713
2714/**
2715 * 80-bit MMX/FPU register type.
2716 */
2717typedef struct X86FPUMMX
2718{
2719 uint8_t reg[10];
2720} X86FPUMMX;
2721#ifndef VBOX_FOR_DTRACE_LIB
2722AssertCompileSize(X86FPUMMX, 10);
2723#endif
2724/** Pointer to a 80-bit MMX/FPU register type. */
2725typedef X86FPUMMX *PX86FPUMMX;
2726/** Pointer to a const 80-bit MMX/FPU register type. */
2727typedef const X86FPUMMX *PCX86FPUMMX;
2728
2729/** FPU (x87) register. */
2730typedef union X86FPUREG
2731{
2732 /** MMX view. */
2733 uint64_t mmx;
2734 /** FPU view - todo. */
2735 X86FPUMMX fpu;
2736 /** Extended precision floating point view. */
2737 RTFLOAT80U r80;
2738 /** Extended precision floating point view v2 */
2739 RTFLOAT80U2 r80Ex;
2740 /** 8-bit view. */
2741 uint8_t au8[16];
2742 /** 16-bit view. */
2743 uint16_t au16[8];
2744 /** 32-bit view. */
2745 uint32_t au32[4];
2746 /** 64-bit view. */
2747 uint64_t au64[2];
2748 /** 128-bit view. (yeah, very helpful) */
2749 uint128_t au128[1];
2750} X86FPUREG;
2751#ifndef VBOX_FOR_DTRACE_LIB
2752AssertCompileSize(X86FPUREG, 16);
2753#endif
2754/** Pointer to a FPU register. */
2755typedef X86FPUREG *PX86FPUREG;
2756/** Pointer to a const FPU register. */
2757typedef X86FPUREG const *PCX86FPUREG;
2758
2759/**
2760 * XMM register union.
2761 */
2762typedef union X86XMMREG
2763{
2764 /** XMM Register view. */
2765 uint128_t xmm;
2766 /** 8-bit view. */
2767 uint8_t au8[16];
2768 /** 16-bit view. */
2769 uint16_t au16[8];
2770 /** 32-bit view. */
2771 uint32_t au32[4];
2772 /** 64-bit view. */
2773 uint64_t au64[2];
2774 /** 128-bit view. (yeah, very helpful) */
2775 uint128_t au128[1];
2776#ifndef VBOX_FOR_DTRACE_LIB
2777 /** Confusing nested 128-bit union view (this is what xmm should've been). */
2778 RTUINT128U uXmm;
2779#endif
2780} X86XMMREG;
2781#ifndef VBOX_FOR_DTRACE_LIB
2782AssertCompileSize(X86XMMREG, 16);
2783#endif
2784/** Pointer to an XMM register state. */
2785typedef X86XMMREG *PX86XMMREG;
2786/** Pointer to a const XMM register state. */
2787typedef X86XMMREG const *PCX86XMMREG;
2788
2789/**
2790 * YMM register union.
2791 */
2792typedef union X86YMMREG
2793{
2794 /** 8-bit view. */
2795 uint8_t au8[32];
2796 /** 16-bit view. */
2797 uint16_t au16[16];
2798 /** 32-bit view. */
2799 uint32_t au32[8];
2800 /** 64-bit view. */
2801 uint64_t au64[4];
2802 /** 128-bit view. (yeah, very helpful) */
2803 uint128_t au128[2];
2804 /** XMM sub register view. */
2805 X86XMMREG aXmm[2];
2806} X86YMMREG;
2807#ifndef VBOX_FOR_DTRACE_LIB
2808AssertCompileSize(X86YMMREG, 32);
2809#endif
2810/** Pointer to an YMM register state. */
2811typedef X86YMMREG *PX86YMMREG;
2812/** Pointer to a const YMM register state. */
2813typedef X86YMMREG const *PCX86YMMREG;
2814
2815/**
2816 * ZMM register union.
2817 */
2818typedef union X86ZMMREG
2819{
2820 /** 8-bit view. */
2821 uint8_t au8[64];
2822 /** 16-bit view. */
2823 uint16_t au16[32];
2824 /** 32-bit view. */
2825 uint32_t au32[16];
2826 /** 64-bit view. */
2827 uint64_t au64[8];
2828 /** 128-bit view. (yeah, very helpful) */
2829 uint128_t au128[4];
2830 /** XMM sub register view. */
2831 X86XMMREG aXmm[4];
2832 /** YMM sub register view. */
2833 X86YMMREG aYmm[2];
2834} X86ZMMREG;
2835#ifndef VBOX_FOR_DTRACE_LIB
2836AssertCompileSize(X86ZMMREG, 64);
2837#endif
2838/** Pointer to an ZMM register state. */
2839typedef X86ZMMREG *PX86ZMMREG;
2840/** Pointer to a const ZMM register state. */
2841typedef X86ZMMREG const *PCX86ZMMREG;
2842
2843
2844/**
2845 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2846 * @todo verify this...
2847 */
2848#pragma pack(1)
2849typedef struct X86FPUSTATE
2850{
2851 /** 0x00 - Control word. */
2852 uint16_t FCW;
2853 /** 0x02 - Alignment word */
2854 uint16_t Dummy1;
2855 /** 0x04 - Status word. */
2856 uint16_t FSW;
2857 /** 0x06 - Alignment word */
2858 uint16_t Dummy2;
2859 /** 0x08 - Tag word */
2860 uint16_t FTW;
2861 /** 0x0a - Alignment word */
2862 uint16_t Dummy3;
2863
2864 /** 0x0c - Instruction pointer. */
2865 uint32_t FPUIP;
2866 /** 0x10 - Code selector. */
2867 uint16_t CS;
2868 /** 0x12 - Opcode. */
2869 uint16_t FOP;
2870 /** 0x14 - FOO. */
2871 uint32_t FPUOO;
2872 /** 0x18 - FOS. */
2873 uint32_t FPUOS;
2874 /** 0x1c - FPU register. */
2875 X86FPUREG regs[8];
2876} X86FPUSTATE;
2877#pragma pack()
2878/** Pointer to a FPU state. */
2879typedef X86FPUSTATE *PX86FPUSTATE;
2880/** Pointer to a const FPU state. */
2881typedef const X86FPUSTATE *PCX86FPUSTATE;
2882
2883/**
2884 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2885 */
2886#pragma pack(1)
2887typedef struct X86FXSTATE
2888{
2889 /** 0x00 - Control word. */
2890 uint16_t FCW;
2891 /** 0x02 - Status word. */
2892 uint16_t FSW;
2893 /** 0x04 - Tag word. (The upper byte is always zero.) */
2894 uint16_t FTW;
2895 /** 0x06 - Opcode. */
2896 uint16_t FOP;
2897 /** 0x08 - Instruction pointer. */
2898 uint32_t FPUIP;
2899 /** 0x0c - Code selector. */
2900 uint16_t CS;
2901 uint16_t Rsrvd1;
2902 /** 0x10 - Data pointer. */
2903 uint32_t FPUDP;
2904 /** 0x14 - Data segment */
2905 uint16_t DS;
2906 /** 0x16 */
2907 uint16_t Rsrvd2;
2908 /** 0x18 */
2909 uint32_t MXCSR;
2910 /** 0x1c */
2911 uint32_t MXCSR_MASK;
2912 /** 0x20 - FPU registers. */
2913 X86FPUREG aRegs[8];
2914 /** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
2915 X86XMMREG aXMM[16];
2916 /* - offset 416 - */
2917 uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2918 /* - offset 464 - Software usable reserved bits. */
2919 uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2920} X86FXSTATE;
2921#pragma pack()
2922/** Pointer to a FPU Extended state. */
2923typedef X86FXSTATE *PX86FXSTATE;
2924/** Pointer to a const FPU Extended state. */
2925typedef const X86FXSTATE *PCX86FXSTATE;
2926
2927/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2928 * magic. Don't forget to update x86.mac if you change this! */
2929#define X86_OFF_FXSTATE_RSVD 0x1d0
2930/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2931 * forget to update x86.mac if you change this!
2932 * @todo r=bird: This has nothing what-so-ever to do here.... */
2933#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2934#ifndef VBOX_FOR_DTRACE_LIB
2935AssertCompileSize(X86FXSTATE, 512);
2936AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2937#endif
2938
2939/** @name FPU status word flags.
2940 * @{ */
2941/** Exception Flag: Invalid operation. */
2942#define X86_FSW_IE RT_BIT_32(0)
2943/** Exception Flag: Denormalized operand. */
2944#define X86_FSW_DE RT_BIT_32(1)
2945/** Exception Flag: Zero divide. */
2946#define X86_FSW_ZE RT_BIT_32(2)
2947/** Exception Flag: Overflow. */
2948#define X86_FSW_OE RT_BIT_32(3)
2949/** Exception Flag: Underflow. */
2950#define X86_FSW_UE RT_BIT_32(4)
2951/** Exception Flag: Precision. */
2952#define X86_FSW_PE RT_BIT_32(5)
2953/** Stack fault. */
2954#define X86_FSW_SF RT_BIT_32(6)
2955/** Error summary status. */
2956#define X86_FSW_ES RT_BIT_32(7)
2957/** Mask of exceptions flags, excluding the summary bit. */
2958#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2959/** Mask of exceptions flags, including the summary bit. */
2960#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2961/** Condition code 0. */
2962#define X86_FSW_C0 RT_BIT_32(8)
2963/** Condition code 1. */
2964#define X86_FSW_C1 RT_BIT_32(9)
2965/** Condition code 2. */
2966#define X86_FSW_C2 RT_BIT_32(10)
2967/** Top of the stack mask. */
2968#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2969/** TOP shift value. */
2970#define X86_FSW_TOP_SHIFT 11
2971/** Mask for getting TOP value after shifting it right. */
2972#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2973/** Get the TOP value. */
2974#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2975/** Condition code 3. */
2976#define X86_FSW_C3 RT_BIT_32(14)
2977/** Mask of exceptions flags, including the summary bit. */
2978#define X86_FSW_C_MASK UINT16_C(0x4700)
2979/** FPU busy. */
2980#define X86_FSW_B RT_BIT_32(15)
2981/** @} */
2982
2983
2984/** @name FPU control word flags.
2985 * @{ */
2986/** Exception Mask: Invalid operation. */
2987#define X86_FCW_IM RT_BIT_32(0)
2988/** Exception Mask: Denormalized operand. */
2989#define X86_FCW_DM RT_BIT_32(1)
2990/** Exception Mask: Zero divide. */
2991#define X86_FCW_ZM RT_BIT_32(2)
2992/** Exception Mask: Overflow. */
2993#define X86_FCW_OM RT_BIT_32(3)
2994/** Exception Mask: Underflow. */
2995#define X86_FCW_UM RT_BIT_32(4)
2996/** Exception Mask: Precision. */
2997#define X86_FCW_PM RT_BIT_32(5)
2998/** Mask all exceptions, the value typically loaded (by for instance fninit).
2999 * @remarks This includes reserved bit 6. */
3000#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3001/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3002#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3003/** Precision control mask. */
3004#define X86_FCW_PC_MASK UINT16_C(0x0300)
3005/** Precision control: 24-bit. */
3006#define X86_FCW_PC_24 UINT16_C(0x0000)
3007/** Precision control: Reserved. */
3008#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3009/** Precision control: 53-bit. */
3010#define X86_FCW_PC_53 UINT16_C(0x0200)
3011/** Precision control: 64-bit. */
3012#define X86_FCW_PC_64 UINT16_C(0x0300)
3013/** Rounding control mask. */
3014#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3015/** Rounding control: To nearest. */
3016#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3017/** Rounding control: Down. */
3018#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3019/** Rounding control: Up. */
3020#define X86_FCW_RC_UP UINT16_C(0x0800)
3021/** Rounding control: Towards zero. */
3022#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3023/** Bits which should be zero, apparently. */
3024#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3025/** @} */
3026
3027/** @name SSE MXCSR
3028 * @{ */
3029/** Exception Flag: Invalid operation. */
3030#define X86_MXCSR_IE RT_BIT_32(0)
3031/** Exception Flag: Denormalized operand. */
3032#define X86_MXCSR_DE RT_BIT_32(1)
3033/** Exception Flag: Zero divide. */
3034#define X86_MXCSR_ZE RT_BIT_32(2)
3035/** Exception Flag: Overflow. */
3036#define X86_MXCSR_OE RT_BIT_32(3)
3037/** Exception Flag: Underflow. */
3038#define X86_MXCSR_UE RT_BIT_32(4)
3039/** Exception Flag: Precision. */
3040#define X86_MXCSR_PE RT_BIT_32(5)
3041
3042/** Denormals are zero. */
3043#define X86_MXCSR_DAZ RT_BIT_32(6)
3044
3045/** Exception Mask: Invalid operation. */
3046#define X86_MXCSR_IM RT_BIT_32(7)
3047/** Exception Mask: Denormalized operand. */
3048#define X86_MXCSR_DM RT_BIT_32(8)
3049/** Exception Mask: Zero divide. */
3050#define X86_MXCSR_ZM RT_BIT_32(9)
3051/** Exception Mask: Overflow. */
3052#define X86_MXCSR_OM RT_BIT_32(10)
3053/** Exception Mask: Underflow. */
3054#define X86_MXCSR_UM RT_BIT_32(11)
3055/** Exception Mask: Precision. */
3056#define X86_MXCSR_PM RT_BIT_32(12)
3057
3058/** Rounding control mask. */
3059#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
3060/** Rounding control: To nearest. */
3061#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3062/** Rounding control: Down. */
3063#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3064/** Rounding control: Up. */
3065#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3066/** Rounding control: Towards zero. */
3067#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3068
3069/** Flush-to-zero for masked underflow. */
3070#define X86_MXCSR_FZ RT_BIT_32(15)
3071
3072/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3073#define X86_MXCSR_MM RT_BIT_32(17)
3074/** @} */
3075
3076/**
3077 * XSAVE header.
3078 */
3079typedef struct X86XSAVEHDR
3080{
3081 /** XTATE_BV - Bitmap indicating whether a component is in the state. */
3082 uint64_t bmXState;
3083 /** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3084 uint64_t bmXComp;
3085 /** Reserved for furture extensions, probably MBZ. */
3086 uint64_t au64Reserved[6];
3087} X86XSAVEHDR;
3088#ifndef VBOX_FOR_DTRACE_LIB
3089AssertCompileSize(X86XSAVEHDR, 64);
3090#endif
3091/** Pointer to an XSAVE header. */
3092typedef X86XSAVEHDR *PX86XSAVEHDR;
3093/** Pointer to a const XSAVE header. */
3094typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3095
3096
3097/**
3098 * The high 128-bit YMM register state (XSAVE_C_YMM).
3099 * (The lower 128-bits being in X86FXSTATE.)
3100 */
3101typedef struct X86XSAVEYMMHI
3102{
3103 /** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3104 X86XMMREG aYmmHi[16];
3105} X86XSAVEYMMHI;
3106#ifndef VBOX_FOR_DTRACE_LIB
3107AssertCompileSize(X86XSAVEYMMHI, 256);
3108#endif
3109/** Pointer to a high 128-bit YMM register state. */
3110typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3111/** Pointer to a const high 128-bit YMM register state. */
3112typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3113
3114/**
3115 * Intel MPX bound registers state (XSAVE_C_BNDREGS).
3116 */
3117typedef struct X86XSAVEBNDREGS
3118{
3119 /** Array of registers (BND0...BND3). */
3120 struct
3121 {
3122 /** Lower bound. */
3123 uint64_t uLowerBound;
3124 /** Upper bound. */
3125 uint64_t uUpperBound;
3126 } aRegs[4];
3127} X86XSAVEBNDREGS;
3128#ifndef VBOX_FOR_DTRACE_LIB
3129AssertCompileSize(X86XSAVEBNDREGS, 64);
3130#endif
3131/** Pointer to a MPX bound register state. */
3132typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3133/** Pointer to a const MPX bound register state. */
3134typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3135
3136/**
3137 * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3138 */
3139typedef struct X86XSAVEBNDCFG
3140{
3141 uint64_t fConfig;
3142 uint64_t fStatus;
3143} X86XSAVEBNDCFG;
3144#ifndef VBOX_FOR_DTRACE_LIB
3145AssertCompileSize(X86XSAVEBNDCFG, 16);
3146#endif
3147/** Pointer to a MPX bound config and status register state. */
3148typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3149/** Pointer to a const MPX bound config and status register state. */
3150typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3151
3152/**
3153 * AVX-512 opmask state (XSAVE_C_OPMASK).
3154 */
3155typedef struct X86XSAVEOPMASK
3156{
3157 /** The K0..K7 values. */
3158 uint64_t aKRegs[8];
3159} X86XSAVEOPMASK;
3160#ifndef VBOX_FOR_DTRACE_LIB
3161AssertCompileSize(X86XSAVEOPMASK, 64);
3162#endif
3163/** Pointer to a AVX-512 opmask state. */
3164typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3165/** Pointer to a const AVX-512 opmask state. */
3166typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3167
3168/**
3169 * ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3170 */
3171typedef struct X86XSAVEZMMHI256
3172{
3173 /** Upper 256-bits of ZMM0-15. */
3174 X86YMMREG aHi256Regs[16];
3175} X86XSAVEZMMHI256;
3176#ifndef VBOX_FOR_DTRACE_LIB
3177AssertCompileSize(X86XSAVEZMMHI256, 512);
3178#endif
3179/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3180typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3181/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3182typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3183
3184/**
3185 * ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3186 */
3187typedef struct X86XSAVEZMM16HI
3188{
3189 /** ZMM16 thru ZMM31. */
3190 X86ZMMREG aRegs[16];
3191} X86XSAVEZMM16HI;
3192#ifndef VBOX_FOR_DTRACE_LIB
3193AssertCompileSize(X86XSAVEZMM16HI, 1024);
3194#endif
3195/** Pointer to a state comprising ZMM16-32. */
3196typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3197/** Pointer to a const state comprising ZMM16-32. */
3198typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3199
3200/**
3201 * AMD Light weight profiling state (XSAVE_C_LWP).
3202 *
3203 * We probably won't play with this as AMD seems to be dropping from their "zen"
3204 * processor micro architecture.
3205 */
3206typedef struct X86XSAVELWP
3207{
3208 /** Details when needed. */
3209 uint64_t auLater[128/8];
3210} X86XSAVELWP;
3211#ifndef VBOX_FOR_DTRACE_LIB
3212AssertCompileSize(X86XSAVELWP, 128);
3213#endif
3214
3215
3216/**
3217 * x86 FPU/SSE/AVX/XXXX state.
3218 *
3219 * Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3220 * changes to this structure.
3221 */
3222typedef struct X86XSAVEAREA
3223{
3224 /** The x87 and SSE region (or legacy region if you like). */
3225 X86FXSTATE x87;
3226 /** The XSAVE header. */
3227 X86XSAVEHDR Hdr;
3228 /** Beyond the header, there isn't really a fixed layout, but we can
3229 generally assume the YMM (AVX) register extensions are present and
3230 follows immediately. */
3231 union
3232 {
3233 /** The high 128-bit AVX registers for easy access by IEM.
3234 * @note This ASSUMES they will always be here... */
3235 X86XSAVEYMMHI YmmHi;
3236
3237 /** This is a typical layout on intel CPUs (good for debuggers). */
3238 struct
3239 {
3240 X86XSAVEYMMHI YmmHi;
3241 X86XSAVEBNDREGS BndRegs;
3242 X86XSAVEBNDCFG BndCfg;
3243 uint8_t abFudgeToMatchDocs[0xB0];
3244 X86XSAVEOPMASK Opmask;
3245 X86XSAVEZMMHI256 ZmmHi256;
3246 X86XSAVEZMM16HI Zmm16Hi;
3247 } Intel;
3248
3249 /** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3250 struct
3251 {
3252 X86XSAVEYMMHI YmmHi;
3253 X86XSAVELWP Lwp;
3254 } AmdBd;
3255
3256 /** To enbling static deployments that have a reasonable chance of working for
3257 * the next 3-6 CPU generations without running short on space, we allocate a
3258 * lot of extra space here, making the structure a round 8KB in size. This
3259 * leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3260 * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3261 uint8_t ab[8192 - 512 - 64];
3262 } u;
3263} X86XSAVEAREA;
3264#ifndef VBOX_FOR_DTRACE_LIB
3265AssertCompileSize(X86XSAVEAREA, 8192);
3266AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
3267AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3268AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3269AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3270AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3271AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3272AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3273AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3274#endif
3275/** Pointer to a XSAVE area. */
3276typedef X86XSAVEAREA *PX86XSAVEAREA;
3277/** Pointer to a const XSAVE area. */
3278typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3279
3280
3281/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3282 * @{ */
3283/** Bit 0 - x87 - Legacy FPU state (bit number) */
3284#define XSAVE_C_X87_BIT 0
3285/** Bit 0 - x87 - Legacy FPU state. */
3286#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3287/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3288#define XSAVE_C_SSE_BIT 1
3289/** Bit 1 - SSE - 128-bit SSE state. */
3290#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3291/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3292#define XSAVE_C_YMM_BIT 2
3293/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3294#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3295/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3296#define XSAVE_C_BNDREGS_BIT 3
3297/** Bit 3 - BNDREGS - MPX bound register state. */
3298#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3299/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3300#define XSAVE_C_BNDCSR_BIT 4
3301/** Bit 4 - BNDCSR - MPX bound config and status state. */
3302#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3303/** Bit 5 - Opmask - opmask state (bit number). */
3304#define XSAVE_C_OPMASK_BIT 5
3305/** Bit 5 - Opmask - opmask state. */
3306#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3307/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3308#define XSAVE_C_ZMM_HI256_BIT 6
3309/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3310#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3311/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3312#define XSAVE_C_ZMM_16HI_BIT 7
3313/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3314#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3315/** Bit 9 - PKRU - Protection-key state (bit number). */
3316#define XSAVE_C_PKRU_BIT 9
3317/** Bit 9 - PKRU - Protection-key state. */
3318#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3319/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3320#define XSAVE_C_LWP_BIT 62
3321/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3322#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3323/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3324#define XSAVE_C_X_BIT 63
3325/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3326#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3327/** @} */
3328
3329
3330
3331/** @name Selector Descriptor
3332 * @{
3333 */
3334
3335#ifndef VBOX_FOR_DTRACE_LIB
3336/**
3337 * Descriptor attributes (as seen by VT-x).
3338 */
3339typedef struct X86DESCATTRBITS
3340{
3341 /** 00 - Segment Type. */
3342 unsigned u4Type : 4;
3343 /** 04 - Descriptor Type. System(=0) or code/data selector */
3344 unsigned u1DescType : 1;
3345 /** 05 - Descriptor Privilege level. */
3346 unsigned u2Dpl : 2;
3347 /** 07 - Flags selector present(=1) or not. */
3348 unsigned u1Present : 1;
3349 /** 08 - Segment limit 16-19. */
3350 unsigned u4LimitHigh : 4;
3351 /** 0c - Available for system software. */
3352 unsigned u1Available : 1;
3353 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3354 unsigned u1Long : 1;
3355 /** 0e - This flags meaning depends on the segment type. Try make sense out
3356 * of the intel manual yourself. */
3357 unsigned u1DefBig : 1;
3358 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
3359 * clear byte. */
3360 unsigned u1Granularity : 1;
3361 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3362 unsigned u1Unusable : 1;
3363} X86DESCATTRBITS;
3364#endif /* !VBOX_FOR_DTRACE_LIB */
3365
3366/** @name X86DESCATTR masks
3367 * @{ */
3368#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3369#define X86DESCATTR_DT UINT32_C(0x00000010)
3370#define X86DESCATTR_DPL UINT32_C(0x00000060)
3371#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
3372#define X86DESCATTR_P UINT32_C(0x00000080)
3373#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3374#define X86DESCATTR_AVL UINT32_C(0x00001000)
3375#define X86DESCATTR_L UINT32_C(0x00002000)
3376#define X86DESCATTR_D UINT32_C(0x00004000)
3377#define X86DESCATTR_G UINT32_C(0x00008000)
3378#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3379/** @} */
3380
3381#pragma pack(1)
3382typedef union X86DESCATTR
3383{
3384 /** Unsigned integer view. */
3385 uint32_t u;
3386#ifndef VBOX_FOR_DTRACE_LIB
3387 /** Normal view. */
3388 X86DESCATTRBITS n;
3389#endif
3390} X86DESCATTR;
3391#pragma pack()
3392/** Pointer to descriptor attributes. */
3393typedef X86DESCATTR *PX86DESCATTR;
3394/** Pointer to const descriptor attributes. */
3395typedef const X86DESCATTR *PCX86DESCATTR;
3396
3397#ifndef VBOX_FOR_DTRACE_LIB
3398
3399/**
3400 * Generic descriptor table entry
3401 */
3402#pragma pack(1)
3403typedef struct X86DESCGENERIC
3404{
3405 /** 00 - Limit - Low word. */
3406 unsigned u16LimitLow : 16;
3407 /** 10 - Base address - low word.
3408 * Don't try set this to 24 because MSC is doing stupid things then. */
3409 unsigned u16BaseLow : 16;
3410 /** 20 - Base address - first 8 bits of high word. */
3411 unsigned u8BaseHigh1 : 8;
3412 /** 28 - Segment Type. */
3413 unsigned u4Type : 4;
3414 /** 2c - Descriptor Type. System(=0) or code/data selector */
3415 unsigned u1DescType : 1;
3416 /** 2d - Descriptor Privilege level. */
3417 unsigned u2Dpl : 2;
3418 /** 2f - Flags selector present(=1) or not. */
3419 unsigned u1Present : 1;
3420 /** 30 - Segment limit 16-19. */
3421 unsigned u4LimitHigh : 4;
3422 /** 34 - Available for system software. */
3423 unsigned u1Available : 1;
3424 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3425 unsigned u1Long : 1;
3426 /** 36 - This flags meaning depends on the segment type. Try make sense out
3427 * of the intel manual yourself. */
3428 unsigned u1DefBig : 1;
3429 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
3430 * clear byte. */
3431 unsigned u1Granularity : 1;
3432 /** 38 - Base address - highest 8 bits. */
3433 unsigned u8BaseHigh2 : 8;
3434} X86DESCGENERIC;
3435#pragma pack()
3436/** Pointer to a generic descriptor entry. */
3437typedef X86DESCGENERIC *PX86DESCGENERIC;
3438/** Pointer to a const generic descriptor entry. */
3439typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3440
3441/** @name Bit offsets of X86DESCGENERIC members.
3442 * @{*/
3443#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
3444#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
3445#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
3446#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
3447#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
3448#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
3449#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
3450#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
3451#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
3452#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
3453#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
3454#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
3455#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
3456/** @} */
3457
3458
3459/** @name LAR mask
3460 * @{ */
3461#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3462#define X86LAR_F_DT UINT16_C( 0x1000)
3463#define X86LAR_F_DPL UINT16_C( 0x6000)
3464#define X86LAR_F_DPL_SHIFT 13 /**< Shift count for the DPL value. */
3465#define X86LAR_F_P UINT16_C( 0x8000)
3466#define X86LAR_F_AVL UINT32_C(0x00100000)
3467#define X86LAR_F_L UINT32_C(0x00200000)
3468#define X86LAR_F_D UINT32_C(0x00400000)
3469#define X86LAR_F_G UINT32_C(0x00800000)
3470/** @} */
3471
3472
3473/**
3474 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3475 */
3476typedef struct X86DESCGATE
3477{
3478 /** 00 - Target code segment offset - Low word.
3479 * Ignored if task-gate. */
3480 unsigned u16OffsetLow : 16;
3481 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3482 * TSS selector if task-gate. */
3483 unsigned u16Sel : 16;
3484 /** 20 - Number of parameters for a call-gate.
3485 * Ignored if interrupt-, trap- or task-gate. */
3486 unsigned u5ParmCount : 5;
3487 /** 25 - Reserved / ignored. */
3488 unsigned u3Reserved : 3;
3489 /** 28 - Segment Type. */
3490 unsigned u4Type : 4;
3491 /** 2c - Descriptor Type (0 = system). */
3492 unsigned u1DescType : 1;
3493 /** 2d - Descriptor Privilege level. */
3494 unsigned u2Dpl : 2;
3495 /** 2f - Flags selector present(=1) or not. */
3496 unsigned u1Present : 1;
3497 /** 30 - Target code segment offset - High word.
3498 * Ignored if task-gate. */
3499 unsigned u16OffsetHigh : 16;
3500} X86DESCGATE;
3501/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3502typedef X86DESCGATE *PX86DESCGATE;
3503/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3504typedef const X86DESCGATE *PCX86DESCGATE;
3505
3506#endif /* VBOX_FOR_DTRACE_LIB */
3507
3508/**
3509 * Descriptor table entry.
3510 */
3511#pragma pack(1)
3512typedef union X86DESC
3513{
3514#ifndef VBOX_FOR_DTRACE_LIB
3515 /** Generic descriptor view. */
3516 X86DESCGENERIC Gen;
3517 /** Gate descriptor view. */
3518 X86DESCGATE Gate;
3519#endif
3520
3521 /** 8 bit unsigned integer view. */
3522 uint8_t au8[8];
3523 /** 16 bit unsigned integer view. */
3524 uint16_t au16[4];
3525 /** 32 bit unsigned integer view. */
3526 uint32_t au32[2];
3527 /** 64 bit unsigned integer view. */
3528 uint64_t au64[1];
3529 /** Unsigned integer view. */
3530 uint64_t u;
3531} X86DESC;
3532#ifndef VBOX_FOR_DTRACE_LIB
3533AssertCompileSize(X86DESC, 8);
3534#endif
3535#pragma pack()
3536/** Pointer to descriptor table entry. */
3537typedef X86DESC *PX86DESC;
3538/** Pointer to const descriptor table entry. */
3539typedef const X86DESC *PCX86DESC;
3540
3541/** @def X86DESC_BASE
3542 * Return the base address of a descriptor.
3543 */
3544#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
3545 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3546 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3547 | ( (a_pDesc)->Gen.u16BaseLow ) )
3548
3549/** @def X86DESC_LIMIT
3550 * Return the limit of a descriptor.
3551 */
3552#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
3553 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3554 | ( (a_pDesc)->Gen.u16LimitLow ) )
3555
3556/** @def X86DESC_LIMIT_G
3557 * Return the limit of a descriptor with the granularity bit taken into account.
3558 * @returns Selector limit (uint32_t).
3559 * @param a_pDesc Pointer to the descriptor.
3560 */
3561#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
3562 ( (a_pDesc)->Gen.u1Granularity \
3563 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
3564 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
3565 )
3566
3567/** @def X86DESC_GET_HID_ATTR
3568 * Get the descriptor attributes for the hidden register.
3569 */
3570#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
3571 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3572
3573#ifndef VBOX_FOR_DTRACE_LIB
3574
3575/**
3576 * 64 bits generic descriptor table entry
3577 * Note: most of these bits have no meaning in long mode.
3578 */
3579#pragma pack(1)
3580typedef struct X86DESC64GENERIC
3581{
3582 /** Limit - Low word - *IGNORED*. */
3583 uint32_t u16LimitLow : 16;
3584 /** Base address - low word. - *IGNORED*
3585 * Don't try set this to 24 because MSC is doing stupid things then. */
3586 uint32_t u16BaseLow : 16;
3587 /** Base address - first 8 bits of high word. - *IGNORED* */
3588 uint32_t u8BaseHigh1 : 8;
3589 /** Segment Type. */
3590 uint32_t u4Type : 4;
3591 /** Descriptor Type. System(=0) or code/data selector */
3592 uint32_t u1DescType : 1;
3593 /** Descriptor Privilege level. */
3594 uint32_t u2Dpl : 2;
3595 /** Flags selector present(=1) or not. */
3596 uint32_t u1Present : 1;
3597 /** Segment limit 16-19. - *IGNORED* */
3598 uint32_t u4LimitHigh : 4;
3599 /** Available for system software. - *IGNORED* */
3600 uint32_t u1Available : 1;
3601 /** Long mode flag. */
3602 uint32_t u1Long : 1;
3603 /** This flags meaning depends on the segment type. Try make sense out
3604 * of the intel manual yourself. */
3605 uint32_t u1DefBig : 1;
3606 /** Granularity of the limit. If set 4KB granularity is used, if
3607 * clear byte. - *IGNORED* */
3608 uint32_t u1Granularity : 1;
3609 /** Base address - highest 8 bits. - *IGNORED* */
3610 uint32_t u8BaseHigh2 : 8;
3611 /** Base address - bits 63-32. */
3612 uint32_t u32BaseHigh3 : 32;
3613 uint32_t u8Reserved : 8;
3614 uint32_t u5Zeros : 5;
3615 uint32_t u19Reserved : 19;
3616} X86DESC64GENERIC;
3617#pragma pack()
3618/** Pointer to a generic descriptor entry. */
3619typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3620/** Pointer to a const generic descriptor entry. */
3621typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3622
3623/**
3624 * System descriptor table entry (64 bits)
3625 *
3626 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3627 */
3628#pragma pack(1)
3629typedef struct X86DESC64SYSTEM
3630{
3631 /** Limit - Low word. */
3632 uint32_t u16LimitLow : 16;
3633 /** Base address - low word.
3634 * Don't try set this to 24 because MSC is doing stupid things then. */
3635 uint32_t u16BaseLow : 16;
3636 /** Base address - first 8 bits of high word. */
3637 uint32_t u8BaseHigh1 : 8;
3638 /** Segment Type. */
3639 uint32_t u4Type : 4;
3640 /** Descriptor Type. System(=0) or code/data selector */
3641 uint32_t u1DescType : 1;
3642 /** Descriptor Privilege level. */
3643 uint32_t u2Dpl : 2;
3644 /** Flags selector present(=1) or not. */
3645 uint32_t u1Present : 1;
3646 /** Segment limit 16-19. */
3647 uint32_t u4LimitHigh : 4;
3648 /** Available for system software. */
3649 uint32_t u1Available : 1;
3650 /** Reserved - 0. */
3651 uint32_t u1Reserved : 1;
3652 /** This flags meaning depends on the segment type. Try make sense out
3653 * of the intel manual yourself. */
3654 uint32_t u1DefBig : 1;
3655 /** Granularity of the limit. If set 4KB granularity is used, if
3656 * clear byte. */
3657 uint32_t u1Granularity : 1;
3658 /** Base address - bits 31-24. */
3659 uint32_t u8BaseHigh2 : 8;
3660 /** Base address - bits 63-32. */
3661 uint32_t u32BaseHigh3 : 32;
3662 uint32_t u8Reserved : 8;
3663 uint32_t u5Zeros : 5;
3664 uint32_t u19Reserved : 19;
3665} X86DESC64SYSTEM;
3666#pragma pack()
3667/** Pointer to a system descriptor entry. */
3668typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3669/** Pointer to a const system descriptor entry. */
3670typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3671
3672/**
3673 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3674 */
3675typedef struct X86DESC64GATE
3676{
3677 /** Target code segment offset - Low word. */
3678 uint32_t u16OffsetLow : 16;
3679 /** Target code segment selector. */
3680 uint32_t u16Sel : 16;
3681 /** Interrupt stack table for interrupt- and trap-gates.
3682 * Ignored by call-gates. */
3683 uint32_t u3IST : 3;
3684 /** Reserved / ignored. */
3685 uint32_t u5Reserved : 5;
3686 /** Segment Type. */
3687 uint32_t u4Type : 4;
3688 /** Descriptor Type (0 = system). */
3689 uint32_t u1DescType : 1;
3690 /** Descriptor Privilege level. */
3691 uint32_t u2Dpl : 2;
3692 /** Flags selector present(=1) or not. */
3693 uint32_t u1Present : 1;
3694 /** Target code segment offset - High word.
3695 * Ignored if task-gate. */
3696 uint32_t u16OffsetHigh : 16;
3697 /** Target code segment offset - Top dword.
3698 * Ignored if task-gate. */
3699 uint32_t u32OffsetTop : 32;
3700 /** Reserved / ignored / must be zero.
3701 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3702 uint32_t u32Reserved : 32;
3703} X86DESC64GATE;
3704AssertCompileSize(X86DESC64GATE, 16);
3705/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3706typedef X86DESC64GATE *PX86DESC64GATE;
3707/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3708typedef const X86DESC64GATE *PCX86DESC64GATE;
3709
3710#endif /* VBOX_FOR_DTRACE_LIB */
3711
3712/**
3713 * Descriptor table entry.
3714 */
3715#pragma pack(1)
3716typedef union X86DESC64
3717{
3718#ifndef VBOX_FOR_DTRACE_LIB
3719 /** Generic descriptor view. */
3720 X86DESC64GENERIC Gen;
3721 /** System descriptor view. */
3722 X86DESC64SYSTEM System;
3723 /** Gate descriptor view. */
3724 X86DESC64GATE Gate;
3725#endif
3726
3727 /** 8 bit unsigned integer view. */
3728 uint8_t au8[16];
3729 /** 16 bit unsigned integer view. */
3730 uint16_t au16[8];
3731 /** 32 bit unsigned integer view. */
3732 uint32_t au32[4];
3733 /** 64 bit unsigned integer view. */
3734 uint64_t au64[2];
3735} X86DESC64;
3736#ifndef VBOX_FOR_DTRACE_LIB
3737AssertCompileSize(X86DESC64, 16);
3738#endif
3739#pragma pack()
3740/** Pointer to descriptor table entry. */
3741typedef X86DESC64 *PX86DESC64;
3742/** Pointer to const descriptor table entry. */
3743typedef const X86DESC64 *PCX86DESC64;
3744
3745/** @def X86DESC64_BASE
3746 * Return the base of a 64-bit descriptor.
3747 */
3748#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
3749 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3750 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3751 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3752 | ( (a_pDesc)->Gen.u16BaseLow ) )
3753
3754
3755
3756/** @name Host system descriptor table entry - Use with care!
3757 * @{ */
3758/** Host system descriptor table entry. */
3759#if HC_ARCH_BITS == 64
3760typedef X86DESC64 X86DESCHC;
3761#else
3762typedef X86DESC X86DESCHC;
3763#endif
3764/** Pointer to a host system descriptor table entry. */
3765#if HC_ARCH_BITS == 64
3766typedef PX86DESC64 PX86DESCHC;
3767#else
3768typedef PX86DESC PX86DESCHC;
3769#endif
3770/** Pointer to a const host system descriptor table entry. */
3771#if HC_ARCH_BITS == 64
3772typedef PCX86DESC64 PCX86DESCHC;
3773#else
3774typedef PCX86DESC PCX86DESCHC;
3775#endif
3776/** @} */
3777
3778
3779/** @name Selector Descriptor Types.
3780 * @{
3781 */
3782
3783/** @name Non-System Selector Types.
3784 * @{ */
3785/** Code(=set)/Data(=clear) bit. */
3786#define X86_SEL_TYPE_CODE 8
3787/** Memory(=set)/System(=clear) bit. */
3788#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3789/** Accessed bit. */
3790#define X86_SEL_TYPE_ACCESSED 1
3791/** Expand down bit (for data selectors only). */
3792#define X86_SEL_TYPE_DOWN 4
3793/** Conforming bit (for code selectors only). */
3794#define X86_SEL_TYPE_CONF 4
3795/** Write bit (for data selectors only). */
3796#define X86_SEL_TYPE_WRITE 2
3797/** Read bit (for code selectors only). */
3798#define X86_SEL_TYPE_READ 2
3799/** The bit number of the code segment read bit (relative to u4Type). */
3800#define X86_SEL_TYPE_READ_BIT 1
3801
3802/** Read only selector type. */
3803#define X86_SEL_TYPE_RO 0
3804/** Accessed read only selector type. */
3805#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
3806/** Read write selector type. */
3807#define X86_SEL_TYPE_RW 2
3808/** Accessed read write selector type. */
3809#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
3810/** Expand down read only selector type. */
3811#define X86_SEL_TYPE_RO_DOWN 4
3812/** Accessed expand down read only selector type. */
3813#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
3814/** Expand down read write selector type. */
3815#define X86_SEL_TYPE_RW_DOWN 6
3816/** Accessed expand down read write selector type. */
3817#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
3818/** Execute only selector type. */
3819#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
3820/** Accessed execute only selector type. */
3821#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3822/** Execute and read selector type. */
3823#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
3824/** Accessed execute and read selector type. */
3825#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3826/** Conforming execute only selector type. */
3827#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
3828/** Accessed Conforming execute only selector type. */
3829#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3830/** Conforming execute and write selector type. */
3831#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
3832/** Accessed Conforming execute and write selector type. */
3833#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3834/** @} */
3835
3836
3837/** @name System Selector Types.
3838 * @{ */
3839/** The TSS busy bit mask. */
3840#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3841
3842/** Undefined system selector type. */
3843#define X86_SEL_TYPE_SYS_UNDEFINED 0
3844/** 286 TSS selector. */
3845#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3846/** LDT selector. */
3847#define X86_SEL_TYPE_SYS_LDT 2
3848/** 286 TSS selector - Busy. */
3849#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3850/** 286 Callgate selector. */
3851#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3852/** Taskgate selector. */
3853#define X86_SEL_TYPE_SYS_TASK_GATE 5
3854/** 286 Interrupt gate selector. */
3855#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3856/** 286 Trapgate selector. */
3857#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3858/** Undefined system selector. */
3859#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3860/** 386 TSS selector. */
3861#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3862/** Undefined system selector. */
3863#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3864/** 386 TSS selector - Busy. */
3865#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3866/** 386 Callgate selector. */
3867#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3868/** Undefined system selector. */
3869#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3870/** 386 Interruptgate selector. */
3871#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3872/** 386 Trapgate selector. */
3873#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3874/** @} */
3875
3876/** @name AMD64 System Selector Types.
3877 * @{ */
3878/** LDT selector. */
3879#define AMD64_SEL_TYPE_SYS_LDT 2
3880/** TSS selector - Busy. */
3881#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3882/** TSS selector - Busy. */
3883#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3884/** Callgate selector. */
3885#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3886/** Interruptgate selector. */
3887#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3888/** Trapgate selector. */
3889#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3890/** @} */
3891
3892/** @} */
3893
3894
3895/** @name Descriptor Table Entry Flag Masks.
3896 * These are for the 2nd 32-bit word of a descriptor.
3897 * @{ */
3898/** Bits 8-11 - TYPE - Descriptor type mask. */
3899#define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
3900/** Bit 12 - S - System (=0) or Code/Data (=1). */
3901#define X86_DESC_S RT_BIT_32(12)
3902/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3903#define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
3904/** Bit 15 - P - Present. */
3905#define X86_DESC_P RT_BIT_32(15)
3906/** Bit 20 - AVL - Available for system software. */
3907#define X86_DESC_AVL RT_BIT_32(20)
3908/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3909#define X86_DESC_DB RT_BIT_32(22)
3910/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3911 * used, if clear byte. */
3912#define X86_DESC_G RT_BIT_32(23)
3913/** @} */
3914
3915/** @} */
3916
3917
3918/** @name Task Segments.
3919 * @{
3920 */
3921
3922/**
3923 * The minimum TSS descriptor limit for 286 tasks.
3924 */
3925#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3926
3927/**
3928 * The minimum TSS descriptor segment limit for 386 tasks.
3929 */
3930#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3931
3932/**
3933 * 16-bit Task Segment (TSS).
3934 */
3935#pragma pack(1)
3936typedef struct X86TSS16
3937{
3938 /** Back link to previous task. (static) */
3939 RTSEL selPrev;
3940 /** Ring-0 stack pointer. (static) */
3941 uint16_t sp0;
3942 /** Ring-0 stack segment. (static) */
3943 RTSEL ss0;
3944 /** Ring-1 stack pointer. (static) */
3945 uint16_t sp1;
3946 /** Ring-1 stack segment. (static) */
3947 RTSEL ss1;
3948 /** Ring-2 stack pointer. (static) */
3949 uint16_t sp2;
3950 /** Ring-2 stack segment. (static) */
3951 RTSEL ss2;
3952 /** IP before task switch. */
3953 uint16_t ip;
3954 /** FLAGS before task switch. */
3955 uint16_t flags;
3956 /** AX before task switch. */
3957 uint16_t ax;
3958 /** CX before task switch. */
3959 uint16_t cx;
3960 /** DX before task switch. */
3961 uint16_t dx;
3962 /** BX before task switch. */
3963 uint16_t bx;
3964 /** SP before task switch. */
3965 uint16_t sp;
3966 /** BP before task switch. */
3967 uint16_t bp;
3968 /** SI before task switch. */
3969 uint16_t si;
3970 /** DI before task switch. */
3971 uint16_t di;
3972 /** ES before task switch. */
3973 RTSEL es;
3974 /** CS before task switch. */
3975 RTSEL cs;
3976 /** SS before task switch. */
3977 RTSEL ss;
3978 /** DS before task switch. */
3979 RTSEL ds;
3980 /** LDTR before task switch. */
3981 RTSEL selLdt;
3982} X86TSS16;
3983#ifndef VBOX_FOR_DTRACE_LIB
3984AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
3985#endif
3986#pragma pack()
3987/** Pointer to a 16-bit task segment. */
3988typedef X86TSS16 *PX86TSS16;
3989/** Pointer to a const 16-bit task segment. */
3990typedef const X86TSS16 *PCX86TSS16;
3991
3992
3993/**
3994 * 32-bit Task Segment (TSS).
3995 */
3996#pragma pack(1)
3997typedef struct X86TSS32
3998{
3999 /** Back link to previous task. (static) */
4000 RTSEL selPrev;
4001 uint16_t padding1;
4002 /** Ring-0 stack pointer. (static) */
4003 uint32_t esp0;
4004 /** Ring-0 stack segment. (static) */
4005 RTSEL ss0;
4006 uint16_t padding_ss0;
4007 /** Ring-1 stack pointer. (static) */
4008 uint32_t esp1;
4009 /** Ring-1 stack segment. (static) */
4010 RTSEL ss1;
4011 uint16_t padding_ss1;
4012 /** Ring-2 stack pointer. (static) */
4013 uint32_t esp2;
4014 /** Ring-2 stack segment. (static) */
4015 RTSEL ss2;
4016 uint16_t padding_ss2;
4017 /** Page directory for the task. (static) */
4018 uint32_t cr3;
4019 /** EIP before task switch. */
4020 uint32_t eip;
4021 /** EFLAGS before task switch. */
4022 uint32_t eflags;
4023 /** EAX before task switch. */
4024 uint32_t eax;
4025 /** ECX before task switch. */
4026 uint32_t ecx;
4027 /** EDX before task switch. */
4028 uint32_t edx;
4029 /** EBX before task switch. */
4030 uint32_t ebx;
4031 /** ESP before task switch. */
4032 uint32_t esp;
4033 /** EBP before task switch. */
4034 uint32_t ebp;
4035 /** ESI before task switch. */
4036 uint32_t esi;
4037 /** EDI before task switch. */
4038 uint32_t edi;
4039 /** ES before task switch. */
4040 RTSEL es;
4041 uint16_t padding_es;
4042 /** CS before task switch. */
4043 RTSEL cs;
4044 uint16_t padding_cs;
4045 /** SS before task switch. */
4046 RTSEL ss;
4047 uint16_t padding_ss;
4048 /** DS before task switch. */
4049 RTSEL ds;
4050 uint16_t padding_ds;
4051 /** FS before task switch. */
4052 RTSEL fs;
4053 uint16_t padding_fs;
4054 /** GS before task switch. */
4055 RTSEL gs;
4056 uint16_t padding_gs;
4057 /** LDTR before task switch. */
4058 RTSEL selLdt;
4059 uint16_t padding_ldt;
4060 /** Debug trap flag */
4061 uint16_t fDebugTrap;
4062 /** Offset relative to the TSS of the start of the I/O Bitmap
4063 * and the end of the interrupt redirection bitmap. */
4064 uint16_t offIoBitmap;
4065} X86TSS32;
4066#pragma pack()
4067/** Pointer to task segment. */
4068typedef X86TSS32 *PX86TSS32;
4069/** Pointer to const task segment. */
4070typedef const X86TSS32 *PCX86TSS32;
4071#ifndef VBOX_FOR_DTRACE_LIB
4072AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4073AssertCompileMemberOffset(X86TSS32, cr3, 28);
4074AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4075#endif
4076
4077/**
4078 * 64-bit Task segment.
4079 */
4080#pragma pack(1)
4081typedef struct X86TSS64
4082{
4083 /** Reserved. */
4084 uint32_t u32Reserved;
4085 /** Ring-0 stack pointer. (static) */
4086 uint64_t rsp0;
4087 /** Ring-1 stack pointer. (static) */
4088 uint64_t rsp1;
4089 /** Ring-2 stack pointer. (static) */
4090 uint64_t rsp2;
4091 /** Reserved. */
4092 uint32_t u32Reserved2[2];
4093 /* IST */
4094 uint64_t ist1;
4095 uint64_t ist2;
4096 uint64_t ist3;
4097 uint64_t ist4;
4098 uint64_t ist5;
4099 uint64_t ist6;
4100 uint64_t ist7;
4101 /* Reserved. */
4102 uint16_t u16Reserved[5];
4103 /** Offset relative to the TSS of the start of the I/O Bitmap
4104 * and the end of the interrupt redirection bitmap. */
4105 uint16_t offIoBitmap;
4106} X86TSS64;
4107#pragma pack()
4108/** Pointer to a 64-bit task segment. */
4109typedef X86TSS64 *PX86TSS64;
4110/** Pointer to a const 64-bit task segment. */
4111typedef const X86TSS64 *PCX86TSS64;
4112#ifndef VBOX_FOR_DTRACE_LIB
4113AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4114#endif
4115
4116/** @} */
4117
4118
4119/** @name Selectors.
4120 * @{
4121 */
4122
4123/**
4124 * The shift used to convert a selector from and to index an index (C).
4125 */
4126#define X86_SEL_SHIFT 3
4127
4128/**
4129 * The mask used to mask off the table indicator and RPL of an selector.
4130 */
4131#define X86_SEL_MASK 0xfff8U
4132
4133/**
4134 * The mask used to mask off the RPL of an selector.
4135 * This is suitable for checking for NULL selectors.
4136 */
4137#define X86_SEL_MASK_OFF_RPL 0xfffcU
4138
4139/**
4140 * The bit indicating that a selector is in the LDT and not in the GDT.
4141 */
4142#define X86_SEL_LDT 0x0004U
4143
4144/**
4145 * The bit mask for getting the RPL of a selector.
4146 */
4147#define X86_SEL_RPL 0x0003U
4148
4149/**
4150 * The mask covering both RPL and LDT.
4151 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4152 * checks.
4153 */
4154#define X86_SEL_RPL_LDT 0x0007U
4155
4156/** @} */
4157
4158
4159/**
4160 * x86 Exceptions/Faults/Traps.
4161 */
4162typedef enum X86XCPT
4163{
4164 /** \#DE - Divide error. */
4165 X86_XCPT_DE = 0x00,
4166 /** \#DB - Debug event (single step, DRx, ..) */
4167 X86_XCPT_DB = 0x01,
4168 /** NMI - Non-Maskable Interrupt */
4169 X86_XCPT_NMI = 0x02,
4170 /** \#BP - Breakpoint (INT3). */
4171 X86_XCPT_BP = 0x03,
4172 /** \#OF - Overflow (INTO). */
4173 X86_XCPT_OF = 0x04,
4174 /** \#BR - Bound range exceeded (BOUND). */
4175 X86_XCPT_BR = 0x05,
4176 /** \#UD - Undefined opcode. */
4177 X86_XCPT_UD = 0x06,
4178 /** \#NM - Device not available (math coprocessor device). */
4179 X86_XCPT_NM = 0x07,
4180 /** \#DF - Double fault. */
4181 X86_XCPT_DF = 0x08,
4182 /** ??? - Coprocessor segment overrun (obsolete). */
4183 X86_XCPT_CO_SEG_OVERRUN = 0x09,
4184 /** \#TS - Taskswitch (TSS). */
4185 X86_XCPT_TS = 0x0a,
4186 /** \#NP - Segment no present. */
4187 X86_XCPT_NP = 0x0b,
4188 /** \#SS - Stack segment fault. */
4189 X86_XCPT_SS = 0x0c,
4190 /** \#GP - General protection fault. */
4191 X86_XCPT_GP = 0x0d,
4192 /** \#PF - Page fault. */
4193 X86_XCPT_PF = 0x0e,
4194 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4195 /** \#MF - Math fault (FPU). */
4196 X86_XCPT_MF = 0x10,
4197 /** \#AC - Alignment check. */
4198 X86_XCPT_AC = 0x11,
4199 /** \#MC - Machine check. */
4200 X86_XCPT_MC = 0x12,
4201 /** \#XF - SIMD Floating-Pointer Exception. */
4202 X86_XCPT_XF = 0x13,
4203 /** \#VE - Virtualization Exception. */
4204 X86_XCPT_VE = 0x14,
4205 /** \#SX - Security Exception. */
4206 X86_XCPT_SX = 0x1e
4207} X86XCPT;
4208/** Pointer to a x86 exception code. */
4209typedef X86XCPT *PX86XCPT;
4210/** Pointer to a const x86 exception code. */
4211typedef const X86XCPT *PCX86XCPT;
4212/** The last valid (currently reserved) exception value. */
4213#define X86_XCPT_LAST 0x1f
4214
4215
4216/** @name Trap Error Codes
4217 * @{
4218 */
4219/** External indicator. */
4220#define X86_TRAP_ERR_EXTERNAL 1
4221/** IDT indicator. */
4222#define X86_TRAP_ERR_IDT 2
4223/** Descriptor table indicator - If set LDT, if clear GDT. */
4224#define X86_TRAP_ERR_TI 4
4225/** Mask for getting the selector. */
4226#define X86_TRAP_ERR_SEL_MASK 0xfff8
4227/** Shift for getting the selector table index (C type index). */
4228#define X86_TRAP_ERR_SEL_SHIFT 3
4229/** @} */
4230
4231
4232/** @name \#PF Trap Error Codes
4233 * @{
4234 */
4235/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4236#define X86_TRAP_PF_P RT_BIT_32(0)
4237/** Bit 1 - R/W - Read (clear) or write (set) access. */
4238#define X86_TRAP_PF_RW RT_BIT_32(1)
4239/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4240#define X86_TRAP_PF_US RT_BIT_32(2)
4241/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4242#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4243/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4244#define X86_TRAP_PF_ID RT_BIT_32(4)
4245/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4246#define X86_TRAP_PF_PK RT_BIT_32(5)
4247/** @} */
4248
4249#pragma pack(1)
4250/**
4251 * 16-bit IDTR.
4252 */
4253typedef struct X86IDTR16
4254{
4255 /** Offset. */
4256 uint16_t offSel;
4257 /** Selector. */
4258 uint16_t uSel;
4259} X86IDTR16, *PX86IDTR16;
4260#pragma pack()
4261
4262#pragma pack(1)
4263/**
4264 * 32-bit IDTR/GDTR.
4265 */
4266typedef struct X86XDTR32
4267{
4268 /** Size of the descriptor table. */
4269 uint16_t cb;
4270 /** Address of the descriptor table. */
4271#ifndef VBOX_FOR_DTRACE_LIB
4272 uint32_t uAddr;
4273#else
4274 uint16_t au16Addr[2];
4275#endif
4276} X86XDTR32, *PX86XDTR32;
4277#pragma pack()
4278
4279#pragma pack(1)
4280/**
4281 * 64-bit IDTR/GDTR.
4282 */
4283typedef struct X86XDTR64
4284{
4285 /** Size of the descriptor table. */
4286 uint16_t cb;
4287 /** Address of the descriptor table. */
4288#ifndef VBOX_FOR_DTRACE_LIB
4289 uint64_t uAddr;
4290#else
4291 uint16_t au16Addr[4];
4292#endif
4293} X86XDTR64, *PX86XDTR64;
4294#pragma pack()
4295
4296
4297/** @name ModR/M
4298 * @{ */
4299#define X86_MODRM_RM_MASK UINT8_C(0x07)
4300#define X86_MODRM_REG_MASK UINT8_C(0x38)
4301#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4302#define X86_MODRM_REG_SHIFT 3
4303#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4304#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4305#define X86_MODRM_MOD_SHIFT 6
4306#ifndef VBOX_FOR_DTRACE_LIB
4307AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
4308AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4309AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4310/** @def X86_MODRM_MAKE
4311 * @param a_Mod The mod value (0..3).
4312 * @param a_Reg The register value (0..7).
4313 * @param a_RegMem The register or memory value (0..7). */
4314# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
4315#endif
4316/** @} */
4317
4318/** @name SIB
4319 * @{ */
4320#define X86_SIB_BASE_MASK UINT8_C(0x07)
4321#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4322#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4323#define X86_SIB_INDEX_SHIFT 3
4324#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4325#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4326#define X86_SIB_SCALE_SHIFT 6
4327#ifndef VBOX_FOR_DTRACE_LIB
4328AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
4329AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4330AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4331#endif
4332/** @} */
4333
4334/** @name General register indexes
4335 * @{ */
4336#define X86_GREG_xAX 0
4337#define X86_GREG_xCX 1
4338#define X86_GREG_xDX 2
4339#define X86_GREG_xBX 3
4340#define X86_GREG_xSP 4
4341#define X86_GREG_xBP 5
4342#define X86_GREG_xSI 6
4343#define X86_GREG_xDI 7
4344#define X86_GREG_x8 8
4345#define X86_GREG_x9 9
4346#define X86_GREG_x10 10
4347#define X86_GREG_x11 11
4348#define X86_GREG_x12 12
4349#define X86_GREG_x13 13
4350#define X86_GREG_x14 14
4351#define X86_GREG_x15 15
4352/** @} */
4353
4354/** @name X86_SREG_XXX - Segment register indexes.
4355 * @{ */
4356#define X86_SREG_ES 0
4357#define X86_SREG_CS 1
4358#define X86_SREG_SS 2
4359#define X86_SREG_DS 3
4360#define X86_SREG_FS 4
4361#define X86_SREG_GS 5
4362/** @} */
4363/** Segment register count. */
4364#define X86_SREG_COUNT 6
4365
4366
4367/** @name X86_OP_XXX - Prefixes
4368 * @{ */
4369#define X86_OP_PRF_CS UINT8_C(0x2e)
4370#define X86_OP_PRF_SS UINT8_C(0x36)
4371#define X86_OP_PRF_DS UINT8_C(0x3e)
4372#define X86_OP_PRF_ES UINT8_C(0x26)
4373#define X86_OP_PRF_FS UINT8_C(0x64)
4374#define X86_OP_PRF_GS UINT8_C(0x65)
4375#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4376#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4377#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4378#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4379#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4380#define X86_OP_REX_B UINT8_C(0x41)
4381#define X86_OP_REX_X UINT8_C(0x42)
4382#define X86_OP_REX_R UINT8_C(0x44)
4383#define X86_OP_REX_W UINT8_C(0x48)
4384/** @} */
4385
4386
4387/** @} */
4388
4389#endif
4390
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