[23639] | 1 | /** @file
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[37955] | 2 | * IPRT - X86 and AMD64 Structures and Definitions.
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[20542] | 3 | *
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[37955] | 4 | * @note x86.mac is generated from this file by running 'kmk incs' in the root.
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[1] | 5 | */
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| 6 |
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| 7 | /*
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[76553] | 8 | * Copyright (C) 2006-2019 Oracle Corporation
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[1] | 9 | *
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| 10 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 11 | * available from http://www.virtualbox.org. This file is free software;
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| 12 | * you can redistribute it and/or modify it under the terms of the GNU
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[5999] | 13 | * General Public License (GPL) as published by the Free Software
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| 14 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 15 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 16 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 17 | *
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| 18 | * The contents of this file may alternatively be used under the terms
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| 19 | * of the Common Development and Distribution License Version 1.0
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| 20 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 21 | * VirtualBox OSE distribution, in which case the provisions of the
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| 22 | * CDDL are applicable instead of those of the GPL.
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| 23 | *
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| 24 | * You may elect to license modified versions of this file under the
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| 25 | * terms and conditions of either the GPL or the CDDL or both.
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[1] | 26 | */
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| 27 |
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[76557] | 28 | #ifndef IPRT_INCLUDED_x86_h
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| 29 | #define IPRT_INCLUDED_x86_h
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[76507] | 30 | #ifndef RT_WITHOUT_PRAGMA_ONCE
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| 31 | # pragma once
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| 32 | #endif
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[1] | 33 |
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[41247] | 34 | #ifndef VBOX_FOR_DTRACE_LIB
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| 35 | # include <iprt/types.h>
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| 36 | # include <iprt/assert.h>
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| 37 | #else
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| 38 | # pragma D depends_on library vbox-types.d
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| 39 | #endif
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[1] | 40 |
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[3913] | 41 | /* Workaround for Solaris sys/regset.h defining CS, DS */
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[20742] | 42 | #ifdef RT_OS_SOLARIS
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[3913] | 43 | # undef CS
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| 44 | # undef DS
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| 45 | #endif
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| 46 |
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[37955] | 47 | /** @defgroup grp_rt_x86 x86 Types and Definitions
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| 48 | * @ingroup grp_rt
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[1] | 49 | * @{
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| 50 | */
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| 51 |
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[41268] | 52 | #ifndef VBOX_FOR_DTRACE_LIB
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[1] | 53 | /**
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| 54 | * EFLAGS Bits.
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| 55 | */
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| 56 | typedef struct X86EFLAGSBITS
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| 57 | {
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| 58 | /** Bit 0 - CF - Carry flag - Status flag. */
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| 59 | unsigned u1CF : 1;
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| 60 | /** Bit 1 - 1 - Reserved flag. */
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| 61 | unsigned u1Reserved0 : 1;
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| 62 | /** Bit 2 - PF - Parity flag - Status flag. */
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| 63 | unsigned u1PF : 1;
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| 64 | /** Bit 3 - 0 - Reserved flag. */
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| 65 | unsigned u1Reserved1 : 1;
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| 66 | /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
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| 67 | unsigned u1AF : 1;
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| 68 | /** Bit 5 - 0 - Reserved flag. */
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| 69 | unsigned u1Reserved2 : 1;
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| 70 | /** Bit 6 - ZF - Zero flag - Status flag. */
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| 71 | unsigned u1ZF : 1;
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| 72 | /** Bit 7 - SF - Signed flag - Status flag. */
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| 73 | unsigned u1SF : 1;
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| 74 | /** Bit 8 - TF - Trap flag - System flag. */
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| 75 | unsigned u1TF : 1;
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| 76 | /** Bit 9 - IF - Interrupt flag - System flag. */
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| 77 | unsigned u1IF : 1;
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| 78 | /** Bit 10 - DF - Direction flag - Control flag. */
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| 79 | unsigned u1DF : 1;
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| 80 | /** Bit 11 - OF - Overflow flag - Status flag. */
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| 81 | unsigned u1OF : 1;
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[53194] | 82 | /** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
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[1] | 83 | unsigned u2IOPL : 2;
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| 84 | /** Bit 14 - NT - Nested task flag - System flag. */
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| 85 | unsigned u1NT : 1;
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| 86 | /** Bit 15 - 0 - Reserved flag. */
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| 87 | unsigned u1Reserved3 : 1;
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| 88 | /** Bit 16 - RF - Resume flag - System flag. */
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| 89 | unsigned u1RF : 1;
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| 90 | /** Bit 17 - VM - Virtual 8086 mode - System flag. */
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| 91 | unsigned u1VM : 1;
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| 92 | /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
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| 93 | unsigned u1AC : 1;
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[33540] | 94 | /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
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[1] | 95 | unsigned u1VIF : 1;
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[33540] | 96 | /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
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[1] | 97 | unsigned u1VIP : 1;
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| 98 | /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
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| 99 | unsigned u1ID : 1;
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| 100 | /** Bit 22-31 - 0 - Reserved flag. */
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| 101 | unsigned u10Reserved4 : 10;
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| 102 | } X86EFLAGSBITS;
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| 103 | /** Pointer to EFLAGS bits. */
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| 104 | typedef X86EFLAGSBITS *PX86EFLAGSBITS;
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| 105 | /** Pointer to const EFLAGS bits. */
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| 106 | typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
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[41268] | 107 | #endif /* !VBOX_FOR_DTRACE_LIB */
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[1] | 108 |
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| 109 | /**
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| 110 | * EFLAGS.
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| 111 | */
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| 112 | typedef union X86EFLAGS
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| 113 | {
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[14135] | 114 | /** The plain unsigned view. */
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| 115 | uint32_t u;
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[41268] | 116 | #ifndef VBOX_FOR_DTRACE_LIB
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[1] | 117 | /** The bitfield view. */
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| 118 | X86EFLAGSBITS Bits;
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[41268] | 119 | #endif
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[1] | 120 | /** The 8-bit view. */
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| 121 | uint8_t au8[4];
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| 122 | /** The 16-bit view. */
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| 123 | uint16_t au16[2];
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| 124 | /** The 32-bit view. */
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| 125 | uint32_t au32[1];
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| 126 | /** The 32-bit view. */
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| 127 | uint32_t u32;
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| 128 | } X86EFLAGS;
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| 129 | /** Pointer to EFLAGS. */
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| 130 | typedef X86EFLAGS *PX86EFLAGS;
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| 131 | /** Pointer to const EFLAGS. */
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| 132 | typedef const X86EFLAGS *PCX86EFLAGS;
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| 133 |
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[7095] | 134 | /**
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[7121] | 135 | * RFLAGS (32 upper bits are reserved).
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[7095] | 136 | */
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| 137 | typedef union X86RFLAGS
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| 138 | {
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[14135] | 139 | /** The plain unsigned view. */
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| 140 | uint64_t u;
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[41268] | 141 | #ifndef VBOX_FOR_DTRACE_LIB
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[7095] | 142 | /** The bitfield view. */
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| 143 | X86EFLAGSBITS Bits;
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[41268] | 144 | #endif
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[7095] | 145 | /** The 8-bit view. */
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| 146 | uint8_t au8[8];
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| 147 | /** The 16-bit view. */
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| 148 | uint16_t au16[4];
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| 149 | /** The 32-bit view. */
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| 150 | uint32_t au32[2];
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| 151 | /** The 64-bit view. */
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| 152 | uint64_t au64[1];
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| 153 | /** The 64-bit view. */
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[7096] | 154 | uint64_t u64;
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[7095] | 155 | } X86RFLAGS;
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| 156 | /** Pointer to RFLAGS. */
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| 157 | typedef X86RFLAGS *PX86RFLAGS;
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| 158 | /** Pointer to const RFLAGS. */
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| 159 | typedef const X86RFLAGS *PCX86RFLAGS;
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[1] | 160 |
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[7095] | 161 |
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[1] | 162 | /** @name EFLAGS
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| 163 | * @{
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| 164 | */
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| 165 | /** Bit 0 - CF - Carry flag - Status flag. */
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[59961] | 166 | #define X86_EFL_CF RT_BIT_32(0)
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[48143] | 167 | #define X86_EFL_CF_BIT 0
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[36793] | 168 | /** Bit 1 - Reserved, reads as 1. */
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[59961] | 169 | #define X86_EFL_1 RT_BIT_32(1)
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[1] | 170 | /** Bit 2 - PF - Parity flag - Status flag. */
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[59961] | 171 | #define X86_EFL_PF RT_BIT_32(2)
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[1] | 172 | /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
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[59961] | 173 | #define X86_EFL_AF RT_BIT_32(4)
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[48143] | 174 | #define X86_EFL_AF_BIT 4
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[1] | 175 | /** Bit 6 - ZF - Zero flag - Status flag. */
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[59961] | 176 | #define X86_EFL_ZF RT_BIT_32(6)
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[48143] | 177 | #define X86_EFL_ZF_BIT 6
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[1] | 178 | /** Bit 7 - SF - Signed flag - Status flag. */
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[59961] | 179 | #define X86_EFL_SF RT_BIT_32(7)
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[48143] | 180 | #define X86_EFL_SF_BIT 7
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[1] | 181 | /** Bit 8 - TF - Trap flag - System flag. */
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[59961] | 182 | #define X86_EFL_TF RT_BIT_32(8)
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[1] | 183 | /** Bit 9 - IF - Interrupt flag - System flag. */
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[59961] | 184 | #define X86_EFL_IF RT_BIT_32(9)
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[1] | 185 | /** Bit 10 - DF - Direction flag - Control flag. */
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[59961] | 186 | #define X86_EFL_DF RT_BIT_32(10)
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[1] | 187 | /** Bit 11 - OF - Overflow flag - Status flag. */
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[59961] | 188 | #define X86_EFL_OF RT_BIT_32(11)
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[48143] | 189 | #define X86_EFL_OF_BIT 11
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[53191] | 190 | /** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
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[59961] | 191 | #define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
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[1] | 192 | /** Bit 14 - NT - Nested task flag - System flag. */
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[59961] | 193 | #define X86_EFL_NT RT_BIT_32(14)
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[1] | 194 | /** Bit 16 - RF - Resume flag - System flag. */
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[59961] | 195 | #define X86_EFL_RF RT_BIT_32(16)
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[1] | 196 | /** Bit 17 - VM - Virtual 8086 mode - System flag. */
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[59961] | 197 | #define X86_EFL_VM RT_BIT_32(17)
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[1] | 198 | /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
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[59961] | 199 | #define X86_EFL_AC RT_BIT_32(18)
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[33540] | 200 | /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
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[59961] | 201 | #define X86_EFL_VIF RT_BIT_32(19)
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[33540] | 202 | /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
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[59961] | 203 | #define X86_EFL_VIP RT_BIT_32(20)
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[1] | 204 | /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
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[59961] | 205 | #define X86_EFL_ID RT_BIT_32(21)
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[47547] | 206 | /** All live bits. */
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| 207 | #define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
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| 208 | /** Read as 1 bits. */
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| 209 | #define X86_EFL_RA1_MASK RT_BIT_32(1)
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[1] | 210 | /** IOPL shift. */
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| 211 | #define X86_EFL_IOPL_SHIFT 12
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[53191] | 212 | /** The IOPL level from the flags. */
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[1] | 213 | #define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
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[17702] | 214 | /** Bits restored by popf */
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[47381] | 215 | #define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
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| 216 | | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
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[60665] | 217 | /** Bits restored by popf */
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| 218 | #define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
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| 219 | | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
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[48143] | 220 | /** The status bits commonly updated by arithmetic instructions. */
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| 221 | #define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
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[1] | 222 | /** @} */
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| 223 |
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| 224 |
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| 225 | /** CPUID Feature information - ECX.
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| 226 | * CPUID query with EAX=1.
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| 227 | */
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[41259] | 228 | #ifndef VBOX_FOR_DTRACE_LIB
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[1] | 229 | typedef struct X86CPUIDFEATECX
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| 230 | {
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| 231 | /** Bit 0 - SSE3 - Supports SSE3 or not. */
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| 232 | unsigned u1SSE3 : 1;
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[34328] | 233 | /** Bit 1 - PCLMULQDQ. */
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| 234 | unsigned u1PCLMULQDQ : 1;
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[21320] | 235 | /** Bit 2 - DS Area 64-bit layout. */
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| 236 | unsigned u1DTE64 : 1;
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[1] | 237 | /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
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| 238 | unsigned u1Monitor : 1;
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| 239 | /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
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| 240 | unsigned u1CPLDS : 1;
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| 241 | /** Bit 5 - VMX - Virtual Machine Technology. */
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| 242 | unsigned u1VMX : 1;
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[21320] | 243 | /** Bit 6 - SMX: Safer Mode Extensions. */
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| 244 | unsigned u1SMX : 1;
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[1] | 245 | /** Bit 7 - EST - Enh. SpeedStep Tech. */
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| 246 | unsigned u1EST : 1;
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| 247 | /** Bit 8 - TM2 - Terminal Monitor 2. */
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| 248 | unsigned u1TM2 : 1;
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[4425] | 249 | /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
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| 250 | unsigned u1SSSE3 : 1;
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[1] | 251 | /** Bit 10 - CNTX-ID - L1 Context ID. */
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| 252 | unsigned u1CNTXID : 1;
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[34328] | 253 | /** Bit 11 - Reserved. */
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| 254 | unsigned u1Reserved1 : 1;
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| 255 | /** Bit 12 - FMA. */
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[24453] | 256 | unsigned u1FMA : 1;
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[1] | 257 | /** Bit 13 - CX16 - CMPXCHG16B. */
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| 258 | unsigned u1CX16 : 1;
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[4425] | 259 | /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
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| 260 | unsigned u1TPRUpdate : 1;
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[21320] | 261 | /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
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| 262 | unsigned u1PDCM : 1;
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[34328] | 263 | /** Bit 16 - Reserved. */
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| 264 | unsigned u1Reserved2 : 1;
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| 265 | /** Bit 17 - PCID - Process-context identifiers. */
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| 266 | unsigned u1PCID : 1;
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[21320] | 267 | /** Bit 18 - Direct Cache Access. */
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| 268 | unsigned u1DCA : 1;
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| 269 | /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
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| 270 | unsigned u1SSE4_1 : 1;
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| 271 | /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
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| 272 | unsigned u1SSE4_2 : 1;
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| 273 | /** Bit 21 - x2APIC. */
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| 274 | unsigned u1x2APIC : 1;
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| 275 | /** Bit 22 - MOVBE - Supports MOVBE. */
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| 276 | unsigned u1MOVBE : 1;
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| 277 | /** Bit 23 - POPCNT - Supports POPCNT. */
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| 278 | unsigned u1POPCNT : 1;
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[34328] | 279 | /** Bit 24 - TSC-Deadline. */
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| 280 | unsigned u1TSCDEADLINE : 1;
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[24453] | 281 | /** Bit 25 - AES. */
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| 282 | unsigned u1AES : 1;
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[21320] | 283 | /** Bit 26 - XSAVE - Supports XSAVE. */
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| 284 | unsigned u1XSAVE : 1;
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| 285 | /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
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| 286 | unsigned u1OSXSAVE : 1;
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[34328] | 287 | /** Bit 28 - AVX - Supports AVX instruction extensions. */
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| 288 | unsigned u1AVX : 1;
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[50255] | 289 | /** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
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| 290 | unsigned u1F16C : 1;
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| 291 | /** Bit 30 - RDRAND - Supports RDRAND. */
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| 292 | unsigned u1RDRAND : 1;
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[37133] | 293 | /** Bit 31 - Hypervisor present (we're a guest). */
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| 294 | unsigned u1HVP : 1;
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[1] | 295 | } X86CPUIDFEATECX;
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[41259] | 296 | #else /* VBOX_FOR_DTRACE_LIB */
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| 297 | typedef uint32_t X86CPUIDFEATECX;
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| 298 | #endif /* VBOX_FOR_DTRACE_LIB */
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[1] | 299 | /** Pointer to CPUID Feature Information - ECX. */
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| 300 | typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
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| 301 | /** Pointer to const CPUID Feature Information - ECX. */
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| 302 | typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
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| 303 |
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| 304 |
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| 305 | /** CPUID Feature Information - EDX.
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| 306 | * CPUID query with EAX=1.
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| 307 | */
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[41259] | 308 | #ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
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[1] | 309 | typedef struct X86CPUIDFEATEDX
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| 310 | {
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| 311 | /** Bit 0 - FPU - x87 FPU on Chip. */
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| 312 | unsigned u1FPU : 1;
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| 313 | /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
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| 314 | unsigned u1VME : 1;
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| 315 | /** Bit 2 - DE - Debugging extensions. */
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| 316 | unsigned u1DE : 1;
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| 317 | /** Bit 3 - PSE - Page Size Extension. */
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| 318 | unsigned u1PSE : 1;
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[5191] | 319 | /** Bit 4 - TSC - Time Stamp Counter. */
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[1] | 320 | unsigned u1TSC : 1;
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| 321 | /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
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| 322 | unsigned u1MSR : 1;
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| 323 | /** Bit 6 - PAE - Physical Address Extension. */
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| 324 | unsigned u1PAE : 1;
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| 325 | /** Bit 7 - MCE - Machine Check Exception. */
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| 326 | unsigned u1MCE : 1;
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| 327 | /** Bit 8 - CX8 - CMPXCHG8B instruction. */
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| 328 | unsigned u1CX8 : 1;
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[9069] | 329 | /** Bit 9 - APIC - APIC On-Chip. */
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[1] | 330 | unsigned u1APIC : 1;
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| 331 | /** Bit 10 - Reserved. */
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| 332 | unsigned u1Reserved1 : 1;
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| 333 | /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
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| 334 | unsigned u1SEP : 1;
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| 335 | /** Bit 12 - MTRR - Memory Type Range Registers. */
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| 336 | unsigned u1MTRR : 1;
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| 337 | /** Bit 13 - PGE - PTE Global Bit. */
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| 338 | unsigned u1PGE : 1;
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| 339 | /** Bit 14 - MCA - Machine Check Architecture. */
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| 340 | unsigned u1MCA : 1;
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| 341 | /** Bit 15 - CMOV - Conditional Move Instructions. */
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| 342 | unsigned u1CMOV : 1;
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| 343 | /** Bit 16 - PAT - Page Attribute Table. */
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| 344 | unsigned u1PAT : 1;
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[53191] | 345 | /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
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[1] | 346 | unsigned u1PSE36 : 1;
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| 347 | /** Bit 18 - PSN - Processor Serial Number. */
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| 348 | unsigned u1PSN : 1;
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| 349 | /** Bit 19 - CLFSH - CLFLUSH Instruction. */
|
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| 350 | unsigned u1CLFSH : 1;
|
---|
| 351 | /** Bit 20 - Reserved. */
|
---|
| 352 | unsigned u1Reserved2 : 1;
|
---|
| 353 | /** Bit 21 - DS - Debug Store. */
|
---|
| 354 | unsigned u1DS : 1;
|
---|
| 355 | /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
|
---|
| 356 | unsigned u1ACPI : 1;
|
---|
| 357 | /** Bit 23 - MMX - Intel MMX 'Technology'. */
|
---|
| 358 | unsigned u1MMX : 1;
|
---|
| 359 | /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
|
---|
| 360 | unsigned u1FXSR : 1;
|
---|
| 361 | /** Bit 25 - SSE - SSE Support. */
|
---|
| 362 | unsigned u1SSE : 1;
|
---|
| 363 | /** Bit 26 - SSE2 - SSE2 Support. */
|
---|
| 364 | unsigned u1SSE2 : 1;
|
---|
| 365 | /** Bit 27 - SS - Self Snoop. */
|
---|
| 366 | unsigned u1SS : 1;
|
---|
| 367 | /** Bit 28 - HTT - Hyper-Threading Technology. */
|
---|
| 368 | unsigned u1HTT : 1;
|
---|
| 369 | /** Bit 29 - TM - Thermal Monitor. */
|
---|
| 370 | unsigned u1TM : 1;
|
---|
| 371 | /** Bit 30 - Reserved - . */
|
---|
| 372 | unsigned u1Reserved3 : 1;
|
---|
| 373 | /** Bit 31 - PBE - Pending Break Enabled. */
|
---|
| 374 | unsigned u1PBE : 1;
|
---|
| 375 | } X86CPUIDFEATEDX;
|
---|
[41259] | 376 | #else /* VBOX_FOR_DTRACE_LIB */
|
---|
| 377 | typedef uint32_t X86CPUIDFEATEDX;
|
---|
| 378 | #endif /* VBOX_FOR_DTRACE_LIB */
|
---|
[1] | 379 | /** Pointer to CPUID Feature Information - EDX. */
|
---|
| 380 | typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
|
---|
| 381 | /** Pointer to const CPUID Feature Information - EDX. */
|
---|
| 382 | typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
|
---|
| 383 |
|
---|
[3941] | 384 | /** @name CPUID Vendor information.
|
---|
| 385 | * CPUID query with EAX=0.
|
---|
| 386 | * @{
|
---|
| 387 | */
|
---|
[3942] | 388 | #define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
|
---|
| 389 | #define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
|
---|
| 390 | #define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
|
---|
[1] | 391 |
|
---|
[3942] | 392 | #define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
|
---|
| 393 | #define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
|
---|
| 394 | #define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
|
---|
[42157] | 395 |
|
---|
| 396 | #define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
|
---|
| 397 | #define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
|
---|
| 398 | #define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
|
---|
[76886] | 399 |
|
---|
| 400 | #define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
|
---|
| 401 | #define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
|
---|
| 402 | #define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
|
---|
[3941] | 403 | /** @} */
|
---|
| 404 |
|
---|
| 405 |
|
---|
[1] | 406 | /** @name CPUID Feature information.
|
---|
| 407 | * CPUID query with EAX=1.
|
---|
| 408 | * @{
|
---|
| 409 | */
|
---|
| 410 | /** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
|
---|
[59961] | 411 | #define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
|
---|
[24453] | 412 | /** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
|
---|
[59961] | 413 | #define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
|
---|
[21327] | 414 | /** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
|
---|
[59961] | 415 | #define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
|
---|
[1] | 416 | /** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
|
---|
[59961] | 417 | #define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
|
---|
[1] | 418 | /** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
|
---|
[59961] | 419 | #define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
|
---|
[1] | 420 | /** ECX Bit 5 - VMX - Virtual Machine Technology. */
|
---|
[59961] | 421 | #define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
|
---|
[21327] | 422 | /** ECX Bit 6 - SMX - Safer Mode Extensions. */
|
---|
[59961] | 423 | #define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
|
---|
[1] | 424 | /** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
|
---|
[59961] | 425 | #define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
|
---|
[1] | 426 | /** ECX Bit 8 - TM2 - Terminal Monitor 2. */
|
---|
[59961] | 427 | #define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
|
---|
[4425] | 428 | /** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
|
---|
[59961] | 429 | #define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
|
---|
[1] | 430 | /** ECX Bit 10 - CNTX-ID - L1 Context ID. */
|
---|
[59961] | 431 | #define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
|
---|
[54887] | 432 | /** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
|
---|
| 433 | * See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
|
---|
[59961] | 434 | #define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
|
---|
[24453] | 435 | /** ECX Bit 12 - FMA. */
|
---|
[59961] | 436 | #define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
|
---|
[4425] | 437 | /** ECX Bit 13 - CX16 - CMPXCHG16B. */
|
---|
[59961] | 438 | #define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
|
---|
[4425] | 439 | /** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
|
---|
[59961] | 440 | #define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
|
---|
[21327] | 441 | /** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
|
---|
[59961] | 442 | #define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
|
---|
[34328] | 443 | /** ECX Bit 17 - PCID - Process-context identifiers. */
|
---|
[59961] | 444 | #define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
|
---|
[21327] | 445 | /** ECX Bit 18 - DCA - Direct Cache Access. */
|
---|
[59961] | 446 | #define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
|
---|
[21327] | 447 | /** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
|
---|
[59961] | 448 | #define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
|
---|
[21327] | 449 | /** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
|
---|
[59961] | 450 | #define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
|
---|
[12971] | 451 | /** ECX Bit 21 - x2APIC support. */
|
---|
[59961] | 452 | #define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
|
---|
[21327] | 453 | /** ECX Bit 22 - MOVBE instruction. */
|
---|
[59961] | 454 | #define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
|
---|
[24453] | 455 | /** ECX Bit 23 - POPCNT instruction. */
|
---|
[59961] | 456 | #define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
|
---|
[34328] | 457 | /** ECX Bir 24 - TSC-Deadline. */
|
---|
[59961] | 458 | #define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
|
---|
[24453] | 459 | /** ECX Bit 25 - AES instructions. */
|
---|
[59961] | 460 | #define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
|
---|
[21327] | 461 | /** ECX Bit 26 - XSAVE instruction. */
|
---|
[59961] | 462 | #define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
|
---|
[61776] | 463 | /** ECX Bit 27 - Copy of CR4.OSXSAVE. */
|
---|
[59961] | 464 | #define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
|
---|
[24453] | 465 | /** ECX Bit 28 - AVX. */
|
---|
[59961] | 466 | #define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
|
---|
[49083] | 467 | /** ECX Bit 29 - F16C - Half-precision convert instruction support. */
|
---|
[59961] | 468 | #define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
|
---|
[50255] | 469 | /** ECX Bit 30 - RDRAND instruction. */
|
---|
[59961] | 470 | #define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
|
---|
[37139] | 471 | /** ECX Bit 31 - Hypervisor Present (software only). */
|
---|
[59961] | 472 | #define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
|
---|
[1] | 473 |
|
---|
| 474 |
|
---|
| 475 | /** Bit 0 - FPU - x87 FPU on Chip. */
|
---|
[59961] | 476 | #define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
|
---|
[1] | 477 | /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
|
---|
[59961] | 478 | #define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
|
---|
[1] | 479 | /** Bit 2 - DE - Debugging extensions. */
|
---|
[59961] | 480 | #define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
|
---|
[1] | 481 | /** Bit 3 - PSE - Page Size Extension. */
|
---|
[59961] | 482 | #define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
|
---|
[60313] | 483 | #define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /**< Bit number for X86_CPUID_FEATURE_EDX_PSE. */
|
---|
[1] | 484 | /** Bit 4 - TSC - Time Stamp Counter. */
|
---|
[59961] | 485 | #define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
|
---|
[1] | 486 | /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
|
---|
[59961] | 487 | #define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
|
---|
[1] | 488 | /** Bit 6 - PAE - Physical Address Extension. */
|
---|
[59961] | 489 | #define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
|
---|
[60313] | 490 | #define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /**< Bit number for X86_CPUID_FEATURE_EDX_PAE. */
|
---|
[1] | 491 | /** Bit 7 - MCE - Machine Check Exception. */
|
---|
[59961] | 492 | #define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
|
---|
[1] | 493 | /** Bit 8 - CX8 - CMPXCHG8B instruction. */
|
---|
[59961] | 494 | #define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
|
---|
[1] | 495 | /** Bit 9 - APIC - APIC On-Chip. */
|
---|
[59961] | 496 | #define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
|
---|
[42024] | 497 | /** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
|
---|
[59961] | 498 | #define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
|
---|
[1] | 499 | /** Bit 12 - MTRR - Memory Type Range Registers. */
|
---|
[59961] | 500 | #define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
|
---|
[1] | 501 | /** Bit 13 - PGE - PTE Global Bit. */
|
---|
[59961] | 502 | #define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
|
---|
[1] | 503 | /** Bit 14 - MCA - Machine Check Architecture. */
|
---|
[59961] | 504 | #define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
|
---|
[1] | 505 | /** Bit 15 - CMOV - Conditional Move Instructions. */
|
---|
[59961] | 506 | #define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
|
---|
[1] | 507 | /** Bit 16 - PAT - Page Attribute Table. */
|
---|
[59961] | 508 | #define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
|
---|
[49417] | 509 | /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
|
---|
[59961] | 510 | #define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
|
---|
[1] | 511 | /** Bit 18 - PSN - Processor Serial Number. */
|
---|
[59961] | 512 | #define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
|
---|
[1] | 513 | /** Bit 19 - CLFSH - CLFLUSH Instruction. */
|
---|
[59961] | 514 | #define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
|
---|
[1] | 515 | /** Bit 21 - DS - Debug Store. */
|
---|
[59961] | 516 | #define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
|
---|
[53191] | 517 | /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
|
---|
[59961] | 518 | #define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
|
---|
[1] | 519 | /** Bit 23 - MMX - Intel MMX Technology. */
|
---|
[59961] | 520 | #define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
|
---|
[1] | 521 | /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
|
---|
[59961] | 522 | #define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
|
---|
[1] | 523 | /** Bit 25 - SSE - SSE Support. */
|
---|
[59961] | 524 | #define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
|
---|
[1] | 525 | /** Bit 26 - SSE2 - SSE2 Support. */
|
---|
[59961] | 526 | #define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
|
---|
[1] | 527 | /** Bit 27 - SS - Self Snoop. */
|
---|
[59961] | 528 | #define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
|
---|
[1] | 529 | /** Bit 28 - HTT - Hyper-Threading Technology. */
|
---|
[59961] | 530 | #define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
|
---|
[1] | 531 | /** Bit 29 - TM - Therm. Monitor. */
|
---|
[59961] | 532 | #define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
|
---|
[1] | 533 | /** Bit 31 - PBE - Pending Break Enabled. */
|
---|
[59961] | 534 | #define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
|
---|
[1] | 535 | /** @} */
|
---|
| 536 |
|
---|
[26658] | 537 | /** @name CPUID mwait/monitor information.
|
---|
[26657] | 538 | * CPUID query with EAX=5.
|
---|
| 539 | * @{
|
---|
| 540 | */
|
---|
| 541 | /** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
|
---|
[59961] | 542 | #define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
|
---|
[26657] | 543 | /** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
|
---|
[59961] | 544 | #define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
|
---|
[26657] | 545 | /** @} */
|
---|
[1] | 546 |
|
---|
[26657] | 547 |
|
---|
[50765] | 548 | /** @name CPUID Structured Extended Feature information.
|
---|
| 549 | * CPUID query with EAX=7.
|
---|
| 550 | * @{
|
---|
| 551 | */
|
---|
| 552 | /** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
|
---|
[59961] | 553 | #define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
|
---|
[50765] | 554 | /** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
|
---|
[59961] | 555 | #define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
|
---|
[60996] | 556 | /** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
|
---|
| 557 | #define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
|
---|
[50765] | 558 | /** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
|
---|
[59961] | 559 | #define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
|
---|
[50765] | 560 | /** EBX Bit 4 - HLE - Hardware Lock Elision. */
|
---|
[59961] | 561 | #define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
|
---|
[50765] | 562 | /** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
|
---|
[59961] | 563 | #define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
|
---|
[60996] | 564 | /** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
|
---|
| 565 | #define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
|
---|
[50765] | 566 | /** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
|
---|
[59961] | 567 | #define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
|
---|
[50765] | 568 | /** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
|
---|
[59961] | 569 | #define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
|
---|
[50765] | 570 | /** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
|
---|
[59961] | 571 | #define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
|
---|
[50765] | 572 | /** EBX Bit 10 - INVPCID - Supports INVPCID. */
|
---|
[59961] | 573 | #define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
|
---|
[50765] | 574 | /** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
|
---|
[59961] | 575 | #define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
|
---|
[50765] | 576 | /** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
|
---|
[59961] | 577 | #define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
|
---|
[50765] | 578 | /** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
|
---|
[59961] | 579 | #define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
|
---|
[50765] | 580 | /** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
|
---|
[59961] | 581 | #define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
|
---|
[50765] | 582 | /** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
|
---|
[59961] | 583 | #define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
|
---|
[50765] | 584 | /** EBX Bit 16 - AVX512F - Supports AVX512F. */
|
---|
[59961] | 585 | #define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
|
---|
[50765] | 586 | /** EBX Bit 18 - RDSEED - Supports RDSEED. */
|
---|
[59961] | 587 | #define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
|
---|
[50765] | 588 | /** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
|
---|
[59961] | 589 | #define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
|
---|
[50765] | 590 | /** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
|
---|
[59961] | 591 | #define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
|
---|
[50765] | 592 | /** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
|
---|
[59961] | 593 | #define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
|
---|
[50765] | 594 | /** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
|
---|
[59961] | 595 | #define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
|
---|
[50765] | 596 | /** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
|
---|
[59961] | 597 | #define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
|
---|
[50765] | 598 | /** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
|
---|
[59961] | 599 | #define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
|
---|
[50765] | 600 | /** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
|
---|
[59961] | 601 | #define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
|
---|
[50765] | 602 | /** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
|
---|
[59961] | 603 | #define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
|
---|
[54738] | 604 |
|
---|
| 605 | /** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
|
---|
[59961] | 606 | #define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
|
---|
[70606] | 607 | /** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
|
---|
| 608 | #define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
|
---|
| 609 | /** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
|
---|
| 610 | #define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
|
---|
| 611 | /** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
|
---|
| 612 | #define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
|
---|
| 613 | /** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
|
---|
| 614 | #define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
|
---|
| 615 | /** ECX Bit 22 - RDPID - Support pread process ID. */
|
---|
| 616 | #define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
|
---|
| 617 | /** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
|
---|
| 618 | #define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
|
---|
| 619 |
|
---|
| 620 | /** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
|
---|
| 621 | * IBPB command in IA32_PRED_CMD. */
|
---|
| 622 | #define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
|
---|
| 623 | /** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
|
---|
| 624 | #define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
|
---|
[76678] | 625 | /** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
|
---|
| 626 | #define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
|
---|
[70913] | 627 | /** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
|
---|
[70606] | 628 | #define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
|
---|
| 629 |
|
---|
[50765] | 630 | /** @} */
|
---|
| 631 |
|
---|
| 632 |
|
---|
[42024] | 633 | /** @name CPUID Extended Feature information.
|
---|
| 634 | * CPUID query with EAX=0x80000001.
|
---|
| 635 | * @{
|
---|
| 636 | */
|
---|
| 637 | /** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
|
---|
[59961] | 638 | #define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
|
---|
[42024] | 639 |
|
---|
| 640 | /** EDX Bit 11 - SYSCALL/SYSRET. */
|
---|
[59961] | 641 | #define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
|
---|
[42024] | 642 | /** EDX Bit 20 - No-Execute/Execute-Disable. */
|
---|
[59961] | 643 | #define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
|
---|
[42024] | 644 | /** EDX Bit 26 - 1 GB large page. */
|
---|
[59961] | 645 | #define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
|
---|
[42024] | 646 | /** EDX Bit 27 - RDTSCP. */
|
---|
[59961] | 647 | #define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
|
---|
[42024] | 648 | /** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
|
---|
[59961] | 649 | #define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
|
---|
[42024] | 650 | /** @}*/
|
---|
| 651 |
|
---|
[1] | 652 | /** @name CPUID AMD Feature information.
|
---|
| 653 | * CPUID query with EAX=0x80000001.
|
---|
| 654 | * @{
|
---|
| 655 | */
|
---|
| 656 | /** Bit 0 - FPU - x87 FPU on Chip. */
|
---|
[59961] | 657 | #define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
|
---|
[1] | 658 | /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
|
---|
[59961] | 659 | #define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
|
---|
[1] | 660 | /** Bit 2 - DE - Debugging extensions. */
|
---|
[59961] | 661 | #define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
|
---|
[1] | 662 | /** Bit 3 - PSE - Page Size Extension. */
|
---|
[59961] | 663 | #define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
|
---|
[1] | 664 | /** Bit 4 - TSC - Time Stamp Counter. */
|
---|
[59961] | 665 | #define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
|
---|
[1] | 666 | /** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
|
---|
[59961] | 667 | #define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
|
---|
[1] | 668 | /** Bit 6 - PAE - Physical Address Extension. */
|
---|
[59961] | 669 | #define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
|
---|
[1] | 670 | /** Bit 7 - MCE - Machine Check Exception. */
|
---|
[59961] | 671 | #define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
|
---|
[1] | 672 | /** Bit 8 - CX8 - CMPXCHG8B instruction. */
|
---|
[59961] | 673 | #define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
|
---|
[1] | 674 | /** Bit 9 - APIC - APIC On-Chip. */
|
---|
[59961] | 675 | #define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
|
---|
[1] | 676 | /** Bit 12 - MTRR - Memory Type Range Registers. */
|
---|
[59961] | 677 | #define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
|
---|
[1] | 678 | /** Bit 13 - PGE - PTE Global Bit. */
|
---|
[59961] | 679 | #define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
|
---|
[1] | 680 | /** Bit 14 - MCA - Machine Check Architecture. */
|
---|
[59961] | 681 | #define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
|
---|
[1] | 682 | /** Bit 15 - CMOV - Conditional Move Instructions. */
|
---|
[59961] | 683 | #define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
|
---|
[1] | 684 | /** Bit 16 - PAT - Page Attribute Table. */
|
---|
[59961] | 685 | #define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
|
---|
[53191] | 686 | /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
|
---|
[59961] | 687 | #define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
|
---|
[1] | 688 | /** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
|
---|
[59961] | 689 | #define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
|
---|
[1] | 690 | /** Bit 23 - MMX - Intel MMX Technology. */
|
---|
[59961] | 691 | #define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
|
---|
[1] | 692 | /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
|
---|
[59961] | 693 | #define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
|
---|
[4425] | 694 | /** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
|
---|
[59961] | 695 | #define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
|
---|
[4425] | 696 | /** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
|
---|
[59961] | 697 | #define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
|
---|
[4425] | 698 | /** Bit 31 - 3DNOW - AMD 3DNow. */
|
---|
[59961] | 699 | #define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
|
---|
[1] | 700 |
|
---|
[54738] | 701 | /** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
|
---|
[59961] | 702 | #define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
|
---|
[1] | 703 | /** Bit 2 - SVM - AMD VM extensions. */
|
---|
[59961] | 704 | #define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
|
---|
[4425] | 705 | /** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
|
---|
[59961] | 706 | #define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
|
---|
[4425] | 707 | /** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
|
---|
[59961] | 708 | #define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
|
---|
[4425] | 709 | /** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
|
---|
[59961] | 710 | #define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
|
---|
[4425] | 711 | /** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
|
---|
[59961] | 712 | #define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
|
---|
[4425] | 713 | /** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
|
---|
[59961] | 714 | #define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
|
---|
[4425] | 715 | /** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
|
---|
[59961] | 716 | #define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
|
---|
[4425] | 717 | /** Bit 9 - OSVW - AMD OS visible workaround. */
|
---|
[59961] | 718 | #define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
|
---|
[24453] | 719 | /** Bit 10 - IBS - Instruct based sampling. */
|
---|
[59961] | 720 | #define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
|
---|
[54894] | 721 | /** Bit 11 - XOP - Extended operation support (see APM6). */
|
---|
[59961] | 722 | #define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
|
---|
[4425] | 723 | /** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
|
---|
[59961] | 724 | #define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
|
---|
[4425] | 725 | /** Bit 13 - WDT - AMD Watchdog timer support. */
|
---|
[59961] | 726 | #define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
|
---|
[54738] | 727 | /** Bit 15 - LWP - Lightweight profiling support. */
|
---|
[59961] | 728 | #define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
|
---|
[54738] | 729 | /** Bit 16 - FMA4 - Four operand FMA instruction support. */
|
---|
[59961] | 730 | #define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
|
---|
[54738] | 731 | /** Bit 19 - NodeId - Indicates support for
|
---|
| 732 | * MSR_C001_100C[NodeId,NodesPerProcessr]. */
|
---|
[59961] | 733 | #define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
|
---|
[54738] | 734 | /** Bit 21 - TBM - Trailing bit manipulation instruction support. */
|
---|
[59961] | 735 | #define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
|
---|
[54738] | 736 | /** Bit 22 - TopologyExtensions - . */
|
---|
[59961] | 737 | #define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
|
---|
[1] | 738 | /** @} */
|
---|
| 739 |
|
---|
| 740 |
|
---|
[10568] | 741 | /** @name CPUID AMD Feature information.
|
---|
| 742 | * CPUID query with EAX=0x80000007.
|
---|
| 743 | * @{
|
---|
| 744 | */
|
---|
| 745 | /** Bit 0 - TS - Temperature Sensor. */
|
---|
[59961] | 746 | #define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
|
---|
[10568] | 747 | /** Bit 1 - FID - Frequency ID Control. */
|
---|
[59961] | 748 | #define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
|
---|
[10568] | 749 | /** Bit 2 - VID - Voltage ID Control. */
|
---|
[59961] | 750 | #define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
|
---|
[10568] | 751 | /** Bit 3 - TTP - THERMTRIP. */
|
---|
[59961] | 752 | #define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
|
---|
[10568] | 753 | /** Bit 4 - TM - Hardware Thermal Control. */
|
---|
[59961] | 754 | #define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
|
---|
[10568] | 755 | /** Bit 5 - STC - Software Thermal Control. */
|
---|
[59961] | 756 | #define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
|
---|
[10568] | 757 | /** Bit 6 - MC - 100 Mhz Multiplier Control. */
|
---|
[59961] | 758 | #define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
|
---|
[10568] | 759 | /** Bit 7 - HWPSTATE - Hardware P-State Control. */
|
---|
[59961] | 760 | #define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
|
---|
[10568] | 761 | /** Bit 8 - TSCINVAR - TSC Invariant. */
|
---|
[59961] | 762 | #define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
|
---|
[54738] | 763 | /** Bit 9 - CPB - TSC Invariant. */
|
---|
[59961] | 764 | #define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
|
---|
[54738] | 765 | /** Bit 10 - EffFreqRO - MPERF/APERF. */
|
---|
[59961] | 766 | #define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
|
---|
[54738] | 767 | /** Bit 11 - PFI - Processor feedback interface (see EAX). */
|
---|
[59961] | 768 | #define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
|
---|
[54738] | 769 | /** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
|
---|
[59961] | 770 | #define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
|
---|
[10568] | 771 | /** @} */
|
---|
| 772 |
|
---|
| 773 |
|
---|
[70606] | 774 | /** @name CPUID AMD extended feature extensions ID (EBX).
|
---|
| 775 | * CPUID query with EAX=0x80000008.
|
---|
| 776 | * @{
|
---|
| 777 | */
|
---|
| 778 | /** Bit 0 - CLZERO - Clear zero instruction. */
|
---|
| 779 | #define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
|
---|
| 780 | /** Bit 1 - IRPerf - Instructions retired count support. */
|
---|
| 781 | #define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
|
---|
| 782 | /** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
|
---|
| 783 | #define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
|
---|
| 784 | /* AMD pipeline length: 9 feature bits ;-) */
|
---|
| 785 | /** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
|
---|
| 786 | #define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
|
---|
| 787 | /** @} */
|
---|
| 788 |
|
---|
| 789 |
|
---|
[66581] | 790 | /** @name CPUID AMD SVM Feature information.
|
---|
| 791 | * CPUID query with EAX=0x8000000a.
|
---|
| 792 | * @{
|
---|
| 793 | */
|
---|
| 794 | /** Bit 0 - NP - Nested Paging supported. */
|
---|
| 795 | #define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
|
---|
| 796 | /** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
|
---|
| 797 | #define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
|
---|
| 798 | /** Bit 2 - SVML - SVM locking bit supported. */
|
---|
| 799 | #define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
|
---|
| 800 | /** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
|
---|
| 801 | #define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
|
---|
| 802 | /** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
|
---|
| 803 | #define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
|
---|
| 804 | /** Bit 5 - VmcbClean - Support VMCB clean bits. */
|
---|
| 805 | #define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
|
---|
| 806 | /** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
|
---|
| 807 | * VMCB.TLB_Control is supported. */
|
---|
| 808 | #define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
|
---|
[70254] | 809 | /** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
|
---|
| 810 | #define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
|
---|
[66581] | 811 | /** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
|
---|
| 812 | #define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
|
---|
| 813 | /** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
|
---|
| 814 | * intercept filter cycle count threshold. */
|
---|
| 815 | #define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
|
---|
| 816 | /** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
|
---|
| 817 | #define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
|
---|
[66684] | 818 | /** Bit 15 - V_VMSAVE_VMLOAD - Supports virtualized VMSAVE/VMLOAD. */
|
---|
| 819 | #define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
|
---|
| 820 | /** Bit 16 - V_VMSAVE_VMLOAD - Supports virtualized GIF. */
|
---|
| 821 | #define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
|
---|
[66581] | 822 | /** @} */
|
---|
| 823 |
|
---|
| 824 |
|
---|
[1] | 825 | /** @name CR0
|
---|
[60667] | 826 | * @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
|
---|
| 827 | * reserved flags.
|
---|
[1] | 828 | * @{ */
|
---|
| 829 | /** Bit 0 - PE - Protection Enabled */
|
---|
[59961] | 830 | #define X86_CR0_PE RT_BIT_32(0)
|
---|
| 831 | #define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
|
---|
[1] | 832 | /** Bit 1 - MP - Monitor Coprocessor */
|
---|
[59961] | 833 | #define X86_CR0_MP RT_BIT_32(1)
|
---|
| 834 | #define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
|
---|
[1] | 835 | /** Bit 2 - EM - Emulation. */
|
---|
[59961] | 836 | #define X86_CR0_EM RT_BIT_32(2)
|
---|
| 837 | #define X86_CR0_EMULATE_FPU RT_BIT_32(2)
|
---|
[1] | 838 | /** Bit 3 - TS - Task Switch. */
|
---|
[59961] | 839 | #define X86_CR0_TS RT_BIT_32(3)
|
---|
| 840 | #define X86_CR0_TASK_SWITCH RT_BIT_32(3)
|
---|
[60667] | 841 | /** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
|
---|
[59961] | 842 | #define X86_CR0_ET RT_BIT_32(4)
|
---|
| 843 | #define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
|
---|
[60667] | 844 | /** Bit 5 - NE - Numeric error (486+). */
|
---|
[59961] | 845 | #define X86_CR0_NE RT_BIT_32(5)
|
---|
| 846 | #define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
|
---|
[60667] | 847 | /** Bit 16 - WP - Write Protect (486+). */
|
---|
[59961] | 848 | #define X86_CR0_WP RT_BIT_32(16)
|
---|
| 849 | #define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
|
---|
[60667] | 850 | /** Bit 18 - AM - Alignment Mask (486+). */
|
---|
[59961] | 851 | #define X86_CR0_AM RT_BIT_32(18)
|
---|
| 852 | #define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
|
---|
[60667] | 853 | /** Bit 29 - NW - Not Write-though (486+). */
|
---|
[59961] | 854 | #define X86_CR0_NW RT_BIT_32(29)
|
---|
| 855 | #define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
|
---|
[60667] | 856 | /** Bit 30 - WP - Cache Disable (486+). */
|
---|
[59961] | 857 | #define X86_CR0_CD RT_BIT_32(30)
|
---|
| 858 | #define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
|
---|
[1] | 859 | /** Bit 31 - PG - Paging. */
|
---|
[59961] | 860 | #define X86_CR0_PG RT_BIT_32(31)
|
---|
| 861 | #define X86_CR0_PAGING RT_BIT_32(31)
|
---|
[74099] | 862 | #define X86_CR0_BIT_PG 31 /**< Bit number of X86_CR0_PG */
|
---|
[1] | 863 | /** @} */
|
---|
| 864 |
|
---|
| 865 |
|
---|
| 866 | /** @name CR3
|
---|
| 867 | * @{ */
|
---|
| 868 | /** Bit 3 - PWT - Page-level Writes Transparent. */
|
---|
[59961] | 869 | #define X86_CR3_PWT RT_BIT_32(3)
|
---|
[1] | 870 | /** Bit 4 - PCD - Page-level Cache Disable. */
|
---|
[59961] | 871 | #define X86_CR3_PCD RT_BIT_32(4)
|
---|
[1] | 872 | /** Bits 12-31 - - Page directory page number. */
|
---|
| 873 | #define X86_CR3_PAGE_MASK (0xfffff000)
|
---|
| 874 | /** Bits 5-31 - - PAE Page directory page number. */
|
---|
| 875 | #define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
|
---|
[9887] | 876 | /** Bits 12-51 - - AMD64 Page directory page number. */
|
---|
| 877 | #define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
|
---|
[1] | 878 | /** @} */
|
---|
| 879 |
|
---|
| 880 |
|
---|
| 881 | /** @name CR4
|
---|
| 882 | * @{ */
|
---|
| 883 | /** Bit 0 - VME - Virtual-8086 Mode Extensions. */
|
---|
[59961] | 884 | #define X86_CR4_VME RT_BIT_32(0)
|
---|
[1] | 885 | /** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
|
---|
[59961] | 886 | #define X86_CR4_PVI RT_BIT_32(1)
|
---|
[1] | 887 | /** Bit 2 - TSD - Time Stamp Disable. */
|
---|
[59961] | 888 | #define X86_CR4_TSD RT_BIT_32(2)
|
---|
[1] | 889 | /** Bit 3 - DE - Debugging Extensions. */
|
---|
[59961] | 890 | #define X86_CR4_DE RT_BIT_32(3)
|
---|
[1] | 891 | /** Bit 4 - PSE - Page Size Extension. */
|
---|
[59961] | 892 | #define X86_CR4_PSE RT_BIT_32(4)
|
---|
[1] | 893 | /** Bit 5 - PAE - Physical Address Extension. */
|
---|
[59961] | 894 | #define X86_CR4_PAE RT_BIT_32(5)
|
---|
[1] | 895 | /** Bit 6 - MCE - Machine-Check Enable. */
|
---|
[59961] | 896 | #define X86_CR4_MCE RT_BIT_32(6)
|
---|
[1] | 897 | /** Bit 7 - PGE - Page Global Enable. */
|
---|
[59961] | 898 | #define X86_CR4_PGE RT_BIT_32(7)
|
---|
[1] | 899 | /** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
|
---|
[59961] | 900 | #define X86_CR4_PCE RT_BIT_32(8)
|
---|
[54862] | 901 | /** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
|
---|
[59961] | 902 | #define X86_CR4_OSFXSR RT_BIT_32(9)
|
---|
[1] | 903 | /** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
|
---|
[59961] | 904 | #define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
|
---|
[1] | 905 | /** Bit 13 - VMXE - VMX mode is enabled. */
|
---|
[59961] | 906 | #define X86_CR4_VMXE RT_BIT_32(13)
|
---|
[37954] | 907 | /** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
|
---|
[59961] | 908 | #define X86_CR4_SMXE RT_BIT_32(14)
|
---|
[70612] | 909 | /** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
|
---|
| 910 | #define X86_CR4_FSGSBASE RT_BIT_32(16)
|
---|
[37954] | 911 | /** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
|
---|
[59961] | 912 | #define X86_CR4_PCIDE RT_BIT_32(17)
|
---|
[37954] | 913 | /** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
|
---|
| 914 | * extended states. */
|
---|
[59961] | 915 | #define X86_CR4_OSXSAVE RT_BIT_32(18)
|
---|
[37954] | 916 | /** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
|
---|
[59961] | 917 | #define X86_CR4_SMEP RT_BIT_32(20)
|
---|
[50765] | 918 | /** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
|
---|
[59961] | 919 | #define X86_CR4_SMAP RT_BIT_32(21)
|
---|
[55690] | 920 | /** Bit 22 - PKE - Protection Key Enable. */
|
---|
[59961] | 921 | #define X86_CR4_PKE RT_BIT_32(22)
|
---|
[1] | 922 | /** @} */
|
---|
| 923 |
|
---|
| 924 |
|
---|
| 925 | /** @name DR6
|
---|
| 926 | * @{ */
|
---|
| 927 | /** Bit 0 - B0 - Breakpoint 0 condition detected. */
|
---|
[59961] | 928 | #define X86_DR6_B0 RT_BIT_32(0)
|
---|
[1] | 929 | /** Bit 1 - B1 - Breakpoint 1 condition detected. */
|
---|
[59961] | 930 | #define X86_DR6_B1 RT_BIT_32(1)
|
---|
[1] | 931 | /** Bit 2 - B2 - Breakpoint 2 condition detected. */
|
---|
[59961] | 932 | #define X86_DR6_B2 RT_BIT_32(2)
|
---|
[1] | 933 | /** Bit 3 - B3 - Breakpoint 3 condition detected. */
|
---|
[59961] | 934 | #define X86_DR6_B3 RT_BIT_32(3)
|
---|
[47432] | 935 | /** Mask of all the Bx bits. */
|
---|
| 936 | #define X86_DR6_B_MASK UINT64_C(0x0000000f)
|
---|
[1] | 937 | /** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
|
---|
[59961] | 938 | #define X86_DR6_BD RT_BIT_32(13)
|
---|
[1] | 939 | /** Bit 14 - BS - Single step */
|
---|
[59961] | 940 | #define X86_DR6_BS RT_BIT_32(14)
|
---|
[1] | 941 | /** Bit 15 - BT - Task switch. (TSS T bit.) */
|
---|
[59961] | 942 | #define X86_DR6_BT RT_BIT_32(15)
|
---|
[72131] | 943 | /** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
|
---|
| 944 | #define X86_DR6_RTM RT_BIT_32(16)
|
---|
[12119] | 945 | /** Value of DR6 after powerup/reset. */
|
---|
[75916] | 946 | #define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
|
---|
[47328] | 947 | /** Bits which must be 1s in DR6. */
|
---|
| 948 | #define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
|
---|
[72131] | 949 | /** Bits which must be 1s in DR6, when RTM is supported. */
|
---|
| 950 | #define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
|
---|
[47328] | 951 | /** Bits which must be 0s in DR6. */
|
---|
| 952 | #define X86_DR6_RAZ_MASK RT_BIT_64(12)
|
---|
| 953 | /** Bits which must be 0s on writes to DR6. */
|
---|
| 954 | #define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
|
---|
[1] | 955 | /** @} */
|
---|
| 956 |
|
---|
[47432] | 957 | /** Get the DR6.Bx bit for a the given breakpoint. */
|
---|
| 958 | #define X86_DR6_B(iBp) RT_BIT_64(iBp)
|
---|
[1] | 959 |
|
---|
[47432] | 960 |
|
---|
[1] | 961 | /** @name DR7
|
---|
| 962 | * @{ */
|
---|
| 963 | /** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
|
---|
[59961] | 964 | #define X86_DR7_L0 RT_BIT_32(0)
|
---|
[1] | 965 | /** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
|
---|
[59961] | 966 | #define X86_DR7_G0 RT_BIT_32(1)
|
---|
[1] | 967 | /** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
|
---|
[59961] | 968 | #define X86_DR7_L1 RT_BIT_32(2)
|
---|
[1] | 969 | /** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
|
---|
[59961] | 970 | #define X86_DR7_G1 RT_BIT_32(3)
|
---|
[1] | 971 | /** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
|
---|
[59961] | 972 | #define X86_DR7_L2 RT_BIT_32(4)
|
---|
[1] | 973 | /** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
|
---|
[59961] | 974 | #define X86_DR7_G2 RT_BIT_32(5)
|
---|
[1] | 975 | /** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
|
---|
[59961] | 976 | #define X86_DR7_L3 RT_BIT_32(6)
|
---|
[1] | 977 | /** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
|
---|
[59961] | 978 | #define X86_DR7_G3 RT_BIT_32(7)
|
---|
[1] | 979 | /** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
|
---|
[59961] | 980 | #define X86_DR7_LE RT_BIT_32(8)
|
---|
[73459] | 981 | /** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
|
---|
[59961] | 982 | #define X86_DR7_GE RT_BIT_32(9)
|
---|
[1] | 983 |
|
---|
[47660] | 984 | /** L0, L1, L2, and L3. */
|
---|
| 985 | #define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
|
---|
| 986 | /** L0, L1, L2, and L3. */
|
---|
| 987 | #define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
|
---|
| 988 |
|
---|
[72131] | 989 | /** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
|
---|
| 990 | * Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
|
---|
| 991 | #define X86_DR7_RTM RT_BIT_32(11)
|
---|
[53187] | 992 | /** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
|
---|
[53192] | 993 | * Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
|
---|
[53187] | 994 | * May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
|
---|
| 995 | * instruction is executed.
|
---|
| 996 | * @see http://www.rcollins.org/secrets/DR7.html */
|
---|
[59961] | 997 | #define X86_DR7_ICE_IR RT_BIT_32(12)
|
---|
[1] | 998 | /** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
|
---|
| 999 | * any DR register is accessed. */
|
---|
[59961] | 1000 | #define X86_DR7_GD RT_BIT_32(13)
|
---|
[53187] | 1001 | /** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
|
---|
| 1002 | * Pentium. */
|
---|
[59961] | 1003 | #define X86_DR7_ICE_TR1 RT_BIT_32(14)
|
---|
[53187] | 1004 | /** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
|
---|
[59961] | 1005 | #define X86_DR7_ICE_TR2 RT_BIT_32(15)
|
---|
[1] | 1006 | /** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
|
---|
| 1007 | #define X86_DR7_RW0_MASK (3 << 16)
|
---|
| 1008 | /** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
|
---|
| 1009 | #define X86_DR7_LEN0_MASK (3 << 18)
|
---|
| 1010 | /** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
|
---|
| 1011 | #define X86_DR7_RW1_MASK (3 << 20)
|
---|
| 1012 | /** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
|
---|
| 1013 | #define X86_DR7_LEN1_MASK (3 << 22)
|
---|
| 1014 | /** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
|
---|
| 1015 | #define X86_DR7_RW2_MASK (3 << 24)
|
---|
| 1016 | /** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
|
---|
| 1017 | #define X86_DR7_LEN2_MASK (3 << 26)
|
---|
| 1018 | /** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
|
---|
| 1019 | #define X86_DR7_RW3_MASK (3 << 28)
|
---|
| 1020 | /** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
|
---|
| 1021 | #define X86_DR7_LEN3_MASK (3 << 30)
|
---|
| 1022 |
|
---|
[47328] | 1023 | /** Bits which reads as 1s. */
|
---|
[59961] | 1024 | #define X86_DR7_RA1_MASK RT_BIT_32(10)
|
---|
[53187] | 1025 | /** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
|
---|
[47328] | 1026 | #define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
|
---|
| 1027 | /** Bits which must be 0s when writing to DR7. */
|
---|
| 1028 | #define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
|
---|
[1] | 1029 |
|
---|
| 1030 | /** Calcs the L bit of Nth breakpoint.
|
---|
| 1031 | * @param iBp The breakpoint number [0..3].
|
---|
| 1032 | */
|
---|
[12795] | 1033 | #define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
|
---|
[1] | 1034 |
|
---|
| 1035 | /** Calcs the G bit of Nth breakpoint.
|
---|
| 1036 | * @param iBp The breakpoint number [0..3].
|
---|
| 1037 | */
|
---|
[12795] | 1038 | #define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
|
---|
[1] | 1039 |
|
---|
[47432] | 1040 | /** Calcs the L and G bits of Nth breakpoint.
|
---|
| 1041 | * @param iBp The breakpoint number [0..3].
|
---|
| 1042 | */
|
---|
| 1043 | #define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
|
---|
| 1044 |
|
---|
[1] | 1045 | /** @name Read/Write values.
|
---|
| 1046 | * @{ */
|
---|
| 1047 | /** Break on instruction fetch only. */
|
---|
[72127] | 1048 | #define X86_DR7_RW_EO UINT32_C(0)
|
---|
[1] | 1049 | /** Break on write only. */
|
---|
[72127] | 1050 | #define X86_DR7_RW_WO UINT32_C(1)
|
---|
[1] | 1051 | /** Break on I/O read/write. This is only defined if CR4.DE is set. */
|
---|
[72127] | 1052 | #define X86_DR7_RW_IO UINT32_C(2)
|
---|
[1] | 1053 | /** Break on read or write (but not instruction fetches). */
|
---|
[72127] | 1054 | #define X86_DR7_RW_RW UINT32_C(3)
|
---|
[1] | 1055 | /** @} */
|
---|
| 1056 |
|
---|
| 1057 | /** Shifts a X86_DR7_RW_* value to its right place.
|
---|
| 1058 | * @param iBp The breakpoint number [0..3].
|
---|
| 1059 | * @param fRw One of the X86_DR7_RW_* value.
|
---|
| 1060 | */
|
---|
| 1061 | #define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
|
---|
| 1062 |
|
---|
[53191] | 1063 | /** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
|
---|
[47432] | 1064 | * one of the X86_DR7_RW_XXX constants).
|
---|
| 1065 | *
|
---|
| 1066 | * @returns X86_DR7_RW_XXX
|
---|
| 1067 | * @param uDR7 DR7 value
|
---|
| 1068 | * @param iBp The breakpoint number [0..3].
|
---|
| 1069 | */
|
---|
| 1070 | #define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
|
---|
| 1071 |
|
---|
| 1072 | /** R/W0, R/W1, R/W2, and R/W3. */
|
---|
| 1073 | #define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
|
---|
| 1074 |
|
---|
[53630] | 1075 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
[47432] | 1076 | /** Checks if there are any I/O breakpoint types configured in the RW
|
---|
| 1077 | * registers. Does NOT check if these are enabled, sorry. */
|
---|
[53630] | 1078 | # define X86_DR7_ANY_RW_IO(uDR7) \
|
---|
[47432] | 1079 | ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
|
---|
| 1080 | && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
|
---|
| 1081 | AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
|
---|
| 1082 | AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
|
---|
| 1083 | AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
|
---|
| 1084 | AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
|
---|
| 1085 | AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
|
---|
| 1086 | AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
|
---|
| 1087 | AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
|
---|
| 1088 | AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
|
---|
| 1089 | AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
|
---|
[53630] | 1090 | #endif /* !VBOX_FOR_DTRACE_LIB */
|
---|
[47432] | 1091 |
|
---|
[1] | 1092 | /** @name Length values.
|
---|
| 1093 | * @{ */
|
---|
[72127] | 1094 | #define X86_DR7_LEN_BYTE UINT32_C(0)
|
---|
| 1095 | #define X86_DR7_LEN_WORD UINT32_C(1)
|
---|
| 1096 | #define X86_DR7_LEN_QWORD UINT32_C(2) /**< AMD64 long mode only. */
|
---|
| 1097 | #define X86_DR7_LEN_DWORD UINT32_C(3)
|
---|
[1] | 1098 | /** @} */
|
---|
| 1099 |
|
---|
| 1100 | /** Shifts a X86_DR7_LEN_* value to its right place.
|
---|
| 1101 | * @param iBp The breakpoint number [0..3].
|
---|
| 1102 | * @param cb One of the X86_DR7_LEN_* values.
|
---|
| 1103 | */
|
---|
| 1104 | #define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
|
---|
| 1105 |
|
---|
[12666] | 1106 | /** Fetch the breakpoint length bits from the DR7 value.
|
---|
| 1107 | * @param uDR7 DR7 value
|
---|
| 1108 | * @param iBp The breakpoint number [0..3].
|
---|
| 1109 | */
|
---|
[47432] | 1110 | #define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
|
---|
[12666] | 1111 |
|
---|
[1] | 1112 | /** Mask used to check if any breakpoints are enabled. */
|
---|
[47432] | 1113 | #define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
|
---|
[1] | 1114 |
|
---|
[47667] | 1115 | /** LEN0, LEN1, LEN2, and LEN3. */
|
---|
| 1116 | #define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
|
---|
| 1117 | /** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
|
---|
| 1118 | #define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
|
---|
| 1119 |
|
---|
[12578] | 1120 | /** Value of DR7 after powerup/reset. */
|
---|
| 1121 | #define X86_DR7_INIT_VAL 0x400
|
---|
[1] | 1122 | /** @} */
|
---|
| 1123 |
|
---|
| 1124 |
|
---|
| 1125 | /** @name Machine Specific Registers
|
---|
| 1126 | * @{
|
---|
| 1127 | */
|
---|
[48143] | 1128 | /** Machine check address register (P5). */
|
---|
| 1129 | #define MSR_P5_MC_ADDR UINT32_C(0x00000000)
|
---|
| 1130 | /** Machine check type register (P5). */
|
---|
| 1131 | #define MSR_P5_MC_TYPE UINT32_C(0x00000001)
|
---|
[10213] | 1132 | /** Time Stamp Counter. */
|
---|
| 1133 | #define MSR_IA32_TSC 0x10
|
---|
[48143] | 1134 | #define MSR_IA32_CESR UINT32_C(0x00000011)
|
---|
| 1135 | #define MSR_IA32_CTR0 UINT32_C(0x00000012)
|
---|
| 1136 | #define MSR_IA32_CTR1 UINT32_C(0x00000013)
|
---|
[10213] | 1137 |
|
---|
[11688] | 1138 | #define MSR_IA32_PLATFORM_ID 0x17
|
---|
| 1139 |
|
---|
[33540] | 1140 | #ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
|
---|
[47839] | 1141 | # define MSR_IA32_APICBASE 0x1b
|
---|
| 1142 | /** Local APIC enabled. */
|
---|
| 1143 | # define MSR_IA32_APICBASE_EN RT_BIT_64(11)
|
---|
| 1144 | /** X2APIC enabled (requires the EN bit to be set). */
|
---|
| 1145 | # define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
|
---|
| 1146 | /** The processor is the boot strap processor (BSP). */
|
---|
| 1147 | # define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
|
---|
| 1148 | /** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
|
---|
| 1149 | * width. */
|
---|
| 1150 | # define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
|
---|
[61072] | 1151 | /** The default physical base address of the APIC. */
|
---|
| 1152 | # define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
|
---|
| 1153 | /** Gets the physical base address from the MSR. */
|
---|
| 1154 | # define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
|
---|
[9069] | 1155 | #endif
|
---|
| 1156 |
|
---|
[48695] | 1157 | /** Undocumented intel MSR for reporting thread and core counts.
|
---|
| 1158 | * Judging from the XNU sources, it seems to be introduced in Nehalem. The
|
---|
| 1159 | * first 16 bits is the thread count. The next 16 bits the core count, except
|
---|
[48698] | 1160 | * on Westmere where it seems it's only the next 4 bits for some reason. */
|
---|
[48695] | 1161 | #define MSR_CORE_THREAD_COUNT 0x35
|
---|
| 1162 |
|
---|
[1] | 1163 | /** CPU Feature control. */
|
---|
[73225] | 1164 | #define MSR_IA32_FEATURE_CONTROL 0x3A
|
---|
| 1165 | /** Feature control - Lock MSR from writes (R/W0). */
|
---|
| 1166 | #define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
|
---|
| 1167 | /** Feature control - Enable VMX inside SMX operation (R/WL). */
|
---|
| 1168 | #define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
|
---|
[73605] | 1169 | /** Feature control - Enable VMX outside SMX operation (R/WL). */
|
---|
[73225] | 1170 | #define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
|
---|
| 1171 | /** Feature control - SENTER local functions enable (R/WL). */
|
---|
| 1172 | #define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
|
---|
| 1173 | #define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
|
---|
| 1174 | #define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
|
---|
| 1175 | #define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
|
---|
| 1176 | #define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
|
---|
| 1177 | #define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
|
---|
| 1178 | #define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
|
---|
| 1179 | /** Feature control - SENTER global enable (R/WL). */
|
---|
| 1180 | #define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
|
---|
| 1181 | /** Feature control - SGX launch control enable (R/WL). */
|
---|
| 1182 | #define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
|
---|
| 1183 | /** Feature control - SGX global enable (R/WL). */
|
---|
| 1184 | #define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
|
---|
| 1185 | /** Feature control - LMCE on (R/WL). */
|
---|
| 1186 | #define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
|
---|
[1] | 1187 |
|
---|
[50765] | 1188 | /** Per-processor TSC adjust MSR. */
|
---|
| 1189 | #define MSR_IA32_TSC_ADJUST 0x3B
|
---|
| 1190 |
|
---|
[70606] | 1191 | /** Spectre control register.
|
---|
| 1192 | * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
|
---|
| 1193 | #define MSR_IA32_SPEC_CTRL 0x48
|
---|
| 1194 | /** IBRS - Indirect branch restricted speculation. */
|
---|
| 1195 | #define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
|
---|
| 1196 | /** STIBP - Single thread indirect branch predictors. */
|
---|
| 1197 | #define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
|
---|
| 1198 |
|
---|
| 1199 | /** Prediction command register.
|
---|
| 1200 | * Write only, logical processor scope, no state since write only. */
|
---|
| 1201 | #define MSR_IA32_PRED_CMD 0x49
|
---|
| 1202 | /** IBPB - Indirect branch prediction barrie when written as 1. */
|
---|
| 1203 | #define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
|
---|
| 1204 |
|
---|
[11688] | 1205 | /** BIOS update trigger (microcode update). */
|
---|
| 1206 | #define MSR_IA32_BIOS_UPDT_TRIG 0x79
|
---|
| 1207 |
|
---|
| 1208 | /** BIOS update signature (microcode). */
|
---|
| 1209 | #define MSR_IA32_BIOS_SIGN_ID 0x8B
|
---|
| 1210 |
|
---|
[59019] | 1211 | /** SMM monitor control. */
|
---|
| 1212 | #define MSR_IA32_SMM_MONITOR_CTL 0x9B
|
---|
[73605] | 1213 | /** SMM control - Valid. */
|
---|
| 1214 | #define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
|
---|
| 1215 | /** SMM control - VMXOFF unblocks SMI. */
|
---|
| 1216 | #define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
|
---|
| 1217 | /** SMM control - MSEG base physical address. */
|
---|
| 1218 | #define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
|
---|
[59019] | 1219 |
|
---|
[74388] | 1220 | /** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
|
---|
| 1221 | #define MSR_IA32_SMBASE 0x9E
|
---|
| 1222 |
|
---|
[27574] | 1223 | /** General performance counter no. 0. */
|
---|
[27395] | 1224 | #define MSR_IA32_PMC0 0xC1
|
---|
[27574] | 1225 | /** General performance counter no. 1. */
|
---|
[27395] | 1226 | #define MSR_IA32_PMC1 0xC2
|
---|
[27574] | 1227 | /** General performance counter no. 2. */
|
---|
[27395] | 1228 | #define MSR_IA32_PMC2 0xC3
|
---|
[27574] | 1229 | /** General performance counter no. 3. */
|
---|
[27395] | 1230 | #define MSR_IA32_PMC3 0xC4
|
---|
| 1231 |
|
---|
[27094] | 1232 | /** Nehalem power control. */
|
---|
[26993] | 1233 | #define MSR_IA32_PLATFORM_INFO 0xCE
|
---|
| 1234 |
|
---|
[28030] | 1235 | /** Get FSB clock status (Intel-specific). */
|
---|
| 1236 | #define MSR_IA32_FSB_CLOCK_STS 0xCD
|
---|
| 1237 |
|
---|
[48368] | 1238 | /** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
|
---|
| 1239 | #define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
|
---|
| 1240 |
|
---|
[48357] | 1241 | /** C0 Maximum Frequency Clock Count */
|
---|
| 1242 | #define MSR_IA32_MPERF 0xE7
|
---|
| 1243 | /** C0 Actual Frequency Clock Count */
|
---|
| 1244 | #define MSR_IA32_APERF 0xE8
|
---|
| 1245 |
|
---|
[10213] | 1246 | /** MTRR Capabilities. */
|
---|
| 1247 | #define MSR_IA32_MTRR_CAP 0xFE
|
---|
[1] | 1248 |
|
---|
[76678] | 1249 | /** Architecture capabilities (bugfixes). */
|
---|
[70913] | 1250 | #define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
|
---|
[76678] | 1251 | /** CPU is no subject to meltdown problems. */
|
---|
| 1252 | #define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
|
---|
[70606] | 1253 | /** CPU has better IBRS and you can leave it on all the time. */
|
---|
[76678] | 1254 | #define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
|
---|
| 1255 | /** CPU has return stack buffer (RSB) override. */
|
---|
| 1256 | #define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
|
---|
| 1257 | /** Virtual machine monitors need not flush the level 1 data cache on VM entry.
|
---|
| 1258 | * This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
|
---|
| 1259 | #define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
|
---|
[70606] | 1260 |
|
---|
[76678] | 1261 | /** Flush command register. */
|
---|
| 1262 | #define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
|
---|
| 1263 | /** Flush the level 1 data cache when this bit is written. */
|
---|
| 1264 | #define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
|
---|
| 1265 |
|
---|
[48120] | 1266 | /** Cache control/info. */
|
---|
[48119] | 1267 | #define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
|
---|
[10213] | 1268 |
|
---|
[33540] | 1269 | #ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
|
---|
[1] | 1270 | /** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
|
---|
| 1271 | * R0 SS == CS + 8
|
---|
| 1272 | * R3 CS == CS + 16
|
---|
| 1273 | * R3 SS == CS + 24
|
---|
| 1274 | */
|
---|
| 1275 | #define MSR_IA32_SYSENTER_CS 0x174
|
---|
| 1276 | /** SYSENTER_ESP - the R0 ESP. */
|
---|
| 1277 | #define MSR_IA32_SYSENTER_ESP 0x175
|
---|
| 1278 | /** SYSENTER_EIP - the R0 EIP. */
|
---|
| 1279 | #define MSR_IA32_SYSENTER_EIP 0x176
|
---|
| 1280 | #endif
|
---|
| 1281 |
|
---|
[10213] | 1282 | /** Machine Check Global Capabilities Register. */
|
---|
[48066] | 1283 | #define MSR_IA32_MCG_CAP 0x179
|
---|
[10213] | 1284 | /** Machine Check Global Status Register. */
|
---|
[48066] | 1285 | #define MSR_IA32_MCG_STATUS 0x17A
|
---|
[10213] | 1286 | /** Machine Check Global Control Register. */
|
---|
[48066] | 1287 | #define MSR_IA32_MCG_CTRL 0x17B
|
---|
[10213] | 1288 |
|
---|
[36398] | 1289 | /** Page Attribute Table. */
|
---|
[9069] | 1290 | #define MSR_IA32_CR_PAT 0x277
|
---|
[71755] | 1291 | /** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
|
---|
| 1292 | * "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
|
---|
| 1293 | #define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
|
---|
[7695] | 1294 |
|
---|
[18763] | 1295 | /** Performance counter MSRs. (Intel only) */
|
---|
| 1296 | #define MSR_IA32_PERFEVTSEL0 0x186
|
---|
| 1297 | #define MSR_IA32_PERFEVTSEL1 0x187
|
---|
[48695] | 1298 | /** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
|
---|
| 1299 | * The 16th bit whether flex ratio is being used, in which case bits 15:8
|
---|
| 1300 | * holds a ratio that Apple takes for TSC granularity.
|
---|
| 1301 | *
|
---|
[53191] | 1302 | * @note This MSR conflicts the P4 MSR_MCG_R12 register. */
|
---|
[48695] | 1303 | #define MSR_FLEX_RATIO 0x194
|
---|
| 1304 | /** Performance state value and starting with Intel core more.
|
---|
| 1305 | * Apple uses the >=core features to determine TSC granularity on older CPUs. */
|
---|
[18763] | 1306 | #define MSR_IA32_PERF_STATUS 0x198
|
---|
| 1307 | #define MSR_IA32_PERF_CTL 0x199
|
---|
[28030] | 1308 | #define MSR_IA32_THERM_STATUS 0x19c
|
---|
[18763] | 1309 |
|
---|
[27319] | 1310 | /** Enable misc. processor features (R/W). */
|
---|
[36315] | 1311 | #define MSR_IA32_MISC_ENABLE 0x1A0
|
---|
[36398] | 1312 | /** Enable fast-strings feature (for REP MOVS and REP STORS). */
|
---|
[49893] | 1313 | #define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
|
---|
[36398] | 1314 | /** Automatic Thermal Control Circuit Enable (R/W). */
|
---|
[49893] | 1315 | #define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
|
---|
[36398] | 1316 | /** Performance Monitoring Available (R). */
|
---|
[49893] | 1317 | #define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
|
---|
[36398] | 1318 | /** Branch Trace Storage Unavailable (R/O). */
|
---|
[49893] | 1319 | #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
|
---|
[36398] | 1320 | /** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
|
---|
[49893] | 1321 | #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
|
---|
[36398] | 1322 | /** Enhanced Intel SpeedStep Technology Enable (R/W). */
|
---|
[49893] | 1323 | #define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
|
---|
[36398] | 1324 | /** If MONITOR/MWAIT is supported (R/W). */
|
---|
[49893] | 1325 | #define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
|
---|
[36398] | 1326 | /** Limit CPUID Maxval to 3 leafs (R/W). */
|
---|
[49893] | 1327 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
|
---|
[36398] | 1328 | /** When set to 1, xTPR messages are disabled (R/W). */
|
---|
[49893] | 1329 | #define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
|
---|
[36398] | 1330 | /** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
|
---|
[49893] | 1331 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
|
---|
[27319] | 1332 |
|
---|
[48151] | 1333 | /** Trace/Profile Resource Control (R/W) */
|
---|
| 1334 | #define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
|
---|
[70265] | 1335 | /** Last branch record. */
|
---|
| 1336 | #define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
|
---|
| 1337 | /** Branch trace flag (single step on branches). */
|
---|
| 1338 | #define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
|
---|
| 1339 | /** Performance monitoring pin control (AMD only). */
|
---|
| 1340 | #define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
|
---|
| 1341 | #define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
|
---|
| 1342 | #define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
|
---|
| 1343 | #define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
|
---|
| 1344 | /** Trace message enable (Intel only). */
|
---|
| 1345 | #define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
|
---|
| 1346 | /** Branch trace store (Intel only). */
|
---|
| 1347 | #define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
|
---|
| 1348 | /** Branch trace interrupt (Intel only). */
|
---|
| 1349 | #define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
|
---|
| 1350 | /** Branch trace off in privileged code (Intel only). */
|
---|
| 1351 | #define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
|
---|
| 1352 | /** Branch trace off in user code (Intel only). */
|
---|
| 1353 | #define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
|
---|
| 1354 | /** Freeze LBR on PMI flag (Intel only). */
|
---|
| 1355 | #define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
|
---|
| 1356 | /** Freeze PERFMON on PMI flag (Intel only). */
|
---|
| 1357 | #define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
|
---|
| 1358 | /** Freeze while SMM enabled (Intel only). */
|
---|
| 1359 | #define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
|
---|
| 1360 | /** Advanced debugging of RTM regions (Intel only). */
|
---|
| 1361 | #define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
|
---|
[74131] | 1362 | /** Debug control MSR valid bits (Intel only). */
|
---|
| 1363 | #define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \
|
---|
| 1364 | | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \
|
---|
| 1365 | | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
|
---|
| 1366 | | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
|
---|
| 1367 | | MSR_IA32_DEBUGCTL_RTM)
|
---|
[70265] | 1368 |
|
---|
[48151] | 1369 | /** The number (0..3 or 0..15) of the last branch record register on P4 and
|
---|
| 1370 | * related Xeons. */
|
---|
| 1371 | #define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
|
---|
| 1372 | /** @name Last branch registers for P4 and Xeon, models 0 thru 2.
|
---|
| 1373 | * @{ */
|
---|
| 1374 | #define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
|
---|
| 1375 | #define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
|
---|
| 1376 | #define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
|
---|
| 1377 | #define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
|
---|
| 1378 | /** @} */
|
---|
| 1379 |
|
---|
| 1380 |
|
---|
[40170] | 1381 | #define IA32_MTRR_PHYSBASE0 0x200
|
---|
| 1382 | #define IA32_MTRR_PHYSMASK0 0x201
|
---|
| 1383 | #define IA32_MTRR_PHYSBASE1 0x202
|
---|
| 1384 | #define IA32_MTRR_PHYSMASK1 0x203
|
---|
| 1385 | #define IA32_MTRR_PHYSBASE2 0x204
|
---|
| 1386 | #define IA32_MTRR_PHYSMASK2 0x205
|
---|
| 1387 | #define IA32_MTRR_PHYSBASE3 0x206
|
---|
| 1388 | #define IA32_MTRR_PHYSMASK3 0x207
|
---|
| 1389 | #define IA32_MTRR_PHYSBASE4 0x208
|
---|
| 1390 | #define IA32_MTRR_PHYSMASK4 0x209
|
---|
| 1391 | #define IA32_MTRR_PHYSBASE5 0x20a
|
---|
| 1392 | #define IA32_MTRR_PHYSMASK5 0x20b
|
---|
| 1393 | #define IA32_MTRR_PHYSBASE6 0x20c
|
---|
| 1394 | #define IA32_MTRR_PHYSMASK6 0x20d
|
---|
| 1395 | #define IA32_MTRR_PHYSBASE7 0x20e
|
---|
| 1396 | #define IA32_MTRR_PHYSMASK7 0x20f
|
---|
| 1397 | #define IA32_MTRR_PHYSBASE8 0x210
|
---|
| 1398 | #define IA32_MTRR_PHYSMASK8 0x211
|
---|
| 1399 | #define IA32_MTRR_PHYSBASE9 0x212
|
---|
| 1400 | #define IA32_MTRR_PHYSMASK9 0x213
|
---|
| 1401 |
|
---|
| 1402 | /** Fixed range MTRRs.
|
---|
| 1403 | * @{ */
|
---|
| 1404 | #define IA32_MTRR_FIX64K_00000 0x250
|
---|
| 1405 | #define IA32_MTRR_FIX16K_80000 0x258
|
---|
| 1406 | #define IA32_MTRR_FIX16K_A0000 0x259
|
---|
| 1407 | #define IA32_MTRR_FIX4K_C0000 0x268
|
---|
| 1408 | #define IA32_MTRR_FIX4K_C8000 0x269
|
---|
| 1409 | #define IA32_MTRR_FIX4K_D0000 0x26a
|
---|
| 1410 | #define IA32_MTRR_FIX4K_D8000 0x26b
|
---|
| 1411 | #define IA32_MTRR_FIX4K_E0000 0x26c
|
---|
| 1412 | #define IA32_MTRR_FIX4K_E8000 0x26d
|
---|
| 1413 | #define IA32_MTRR_FIX4K_F0000 0x26e
|
---|
| 1414 | #define IA32_MTRR_FIX4K_F8000 0x26f
|
---|
| 1415 | /** @} */
|
---|
| 1416 |
|
---|
[10213] | 1417 | /** MTRR Default Range. */
|
---|
| 1418 | #define MSR_IA32_MTRR_DEF_TYPE 0x2FF
|
---|
| 1419 |
|
---|
[61229] | 1420 | /** Global performance counter control facilities (Intel only). */
|
---|
| 1421 | #define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
|
---|
| 1422 | #define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
|
---|
| 1423 | #define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
|
---|
| 1424 |
|
---|
| 1425 | /** Precise Event Based sampling (Intel only). */
|
---|
[61249] | 1426 | #define MSR_IA32_PEBS_ENABLE 0x3F1
|
---|
[61229] | 1427 |
|
---|
[11688] | 1428 | #define MSR_IA32_MC0_CTL 0x400
|
---|
| 1429 | #define MSR_IA32_MC0_STATUS 0x401
|
---|
| 1430 |
|
---|
[1] | 1431 | /** Basic VMX information. */
|
---|
[73291] | 1432 | #define MSR_IA32_VMX_BASIC 0x480
|
---|
| 1433 | /** Allowed settings for pin-based VM execution controls. */
|
---|
[1] | 1434 | #define MSR_IA32_VMX_PINBASED_CTLS 0x481
|
---|
[73291] | 1435 | /** Allowed settings for proc-based VM execution controls. */
|
---|
[1] | 1436 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x482
|
---|
[73389] | 1437 | /** Allowed settings for the VM-exit controls. */
|
---|
[1] | 1438 | #define MSR_IA32_VMX_EXIT_CTLS 0x483
|
---|
[73389] | 1439 | /** Allowed settings for the VM-entry controls. */
|
---|
[1] | 1440 | #define MSR_IA32_VMX_ENTRY_CTLS 0x484
|
---|
| 1441 | /** Misc VMX info. */
|
---|
| 1442 | #define MSR_IA32_VMX_MISC 0x485
|
---|
| 1443 | /** Fixed cleared bits in CR0. */
|
---|
| 1444 | #define MSR_IA32_VMX_CR0_FIXED0 0x486
|
---|
| 1445 | /** Fixed set bits in CR0. */
|
---|
| 1446 | #define MSR_IA32_VMX_CR0_FIXED1 0x487
|
---|
| 1447 | /** Fixed cleared bits in CR4. */
|
---|
| 1448 | #define MSR_IA32_VMX_CR4_FIXED0 0x488
|
---|
| 1449 | /** Fixed set bits in CR4. */
|
---|
| 1450 | #define MSR_IA32_VMX_CR4_FIXED1 0x489
|
---|
| 1451 | /** Information for enumerating fields in the VMCS. */
|
---|
| 1452 | #define MSR_IA32_VMX_VMCS_ENUM 0x48A
|
---|
[10817] | 1453 | /** Allowed settings for secondary proc-based VM execution controls */
|
---|
| 1454 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
|
---|
| 1455 | /** EPT capabilities. */
|
---|
[43803] | 1456 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
|
---|
[64113] | 1457 | /** Allowed settings of all pin-based VM execution controls. */
|
---|
| 1458 | #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
|
---|
| 1459 | /** Allowed settings of all proc-based VM execution controls. */
|
---|
| 1460 | #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
|
---|
| 1461 | /** Allowed settings of all VMX exit controls. */
|
---|
| 1462 | #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
|
---|
| 1463 | /** Allowed settings of all VMX entry controls. */
|
---|
| 1464 | #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
|
---|
[73248] | 1465 | /** Allowed settings for the VM-function controls. */
|
---|
| 1466 | #define MSR_IA32_VMX_VMFUNC 0x491
|
---|
[64113] | 1467 |
|
---|
[74648] | 1468 | /** Intel PT - Enable and control for trace packet generation. */
|
---|
| 1469 | #define MSR_IA32_RTIT_CTL 0x570
|
---|
[73291] | 1470 |
|
---|
[24281] | 1471 | /** DS Save Area (R/W). */
|
---|
| 1472 | #define MSR_IA32_DS_AREA 0x600
|
---|
[47988] | 1473 | /** Running Average Power Limit (RAPL) power units. */
|
---|
| 1474 | #define MSR_RAPL_POWER_UNIT 0x606
|
---|
[59897] | 1475 |
|
---|
| 1476 | /** X2APIC MSR range start. */
|
---|
[43974] | 1477 | #define MSR_IA32_X2APIC_START 0x800
|
---|
[59897] | 1478 | /** X2APIC MSR - APIC ID Register. */
|
---|
| 1479 | #define MSR_IA32_X2APIC_ID 0x802
|
---|
| 1480 | /** X2APIC MSR - APIC Version Register. */
|
---|
| 1481 | #define MSR_IA32_X2APIC_VERSION 0x803
|
---|
| 1482 | /** X2APIC MSR - Task Priority Register. */
|
---|
[43974] | 1483 | #define MSR_IA32_X2APIC_TPR 0x808
|
---|
[59897] | 1484 | /** X2APIC MSR - Processor Priority register. */
|
---|
| 1485 | #define MSR_IA32_X2APIC_PPR 0x80A
|
---|
| 1486 | /** X2APIC MSR - End Of Interrupt register. */
|
---|
| 1487 | #define MSR_IA32_X2APIC_EOI 0x80B
|
---|
| 1488 | /** X2APIC MSR - Logical Destination Register. */
|
---|
| 1489 | #define MSR_IA32_X2APIC_LDR 0x80D
|
---|
| 1490 | /** X2APIC MSR - Spurious Interrupt Vector Register. */
|
---|
| 1491 | #define MSR_IA32_X2APIC_SVR 0x80F
|
---|
| 1492 | /** X2APIC MSR - In-service Register (bits 31:0). */
|
---|
| 1493 | #define MSR_IA32_X2APIC_ISR0 0x810
|
---|
| 1494 | /** X2APIC MSR - In-service Register (bits 63:32). */
|
---|
| 1495 | #define MSR_IA32_X2APIC_ISR1 0x811
|
---|
| 1496 | /** X2APIC MSR - In-service Register (bits 95:64). */
|
---|
| 1497 | #define MSR_IA32_X2APIC_ISR2 0x812
|
---|
| 1498 | /** X2APIC MSR - In-service Register (bits 127:96). */
|
---|
| 1499 | #define MSR_IA32_X2APIC_ISR3 0x813
|
---|
| 1500 | /** X2APIC MSR - In-service Register (bits 159:128). */
|
---|
| 1501 | #define MSR_IA32_X2APIC_ISR4 0x814
|
---|
| 1502 | /** X2APIC MSR - In-service Register (bits 191:160). */
|
---|
| 1503 | #define MSR_IA32_X2APIC_ISR5 0x815
|
---|
| 1504 | /** X2APIC MSR - In-service Register (bits 223:192). */
|
---|
| 1505 | #define MSR_IA32_X2APIC_ISR6 0x816
|
---|
| 1506 | /** X2APIC MSR - In-service Register (bits 255:224). */
|
---|
| 1507 | #define MSR_IA32_X2APIC_ISR7 0x817
|
---|
| 1508 | /** X2APIC MSR - Trigger Mode Register (bits 31:0). */
|
---|
| 1509 | #define MSR_IA32_X2APIC_TMR0 0x818
|
---|
| 1510 | /** X2APIC MSR - Trigger Mode Register (bits 63:32). */
|
---|
| 1511 | #define MSR_IA32_X2APIC_TMR1 0x819
|
---|
| 1512 | /** X2APIC MSR - Trigger Mode Register (bits 95:64). */
|
---|
| 1513 | #define MSR_IA32_X2APIC_TMR2 0x81A
|
---|
| 1514 | /** X2APIC MSR - Trigger Mode Register (bits 127:96). */
|
---|
| 1515 | #define MSR_IA32_X2APIC_TMR3 0x81B
|
---|
| 1516 | /** X2APIC MSR - Trigger Mode Register (bits 159:128). */
|
---|
| 1517 | #define MSR_IA32_X2APIC_TMR4 0x81C
|
---|
| 1518 | /** X2APIC MSR - Trigger Mode Register (bits 191:160). */
|
---|
| 1519 | #define MSR_IA32_X2APIC_TMR5 0x81D
|
---|
| 1520 | /** X2APIC MSR - Trigger Mode Register (bits 223:192). */
|
---|
| 1521 | #define MSR_IA32_X2APIC_TMR6 0x81E
|
---|
| 1522 | /** X2APIC MSR - Trigger Mode Register (bits 255:224). */
|
---|
| 1523 | #define MSR_IA32_X2APIC_TMR7 0x81F
|
---|
| 1524 | /** X2APIC MSR - Interrupt Request Register (bits 31:0). */
|
---|
| 1525 | #define MSR_IA32_X2APIC_IRR0 0x820
|
---|
| 1526 | /** X2APIC MSR - Interrupt Request Register (bits 63:32). */
|
---|
| 1527 | #define MSR_IA32_X2APIC_IRR1 0x821
|
---|
| 1528 | /** X2APIC MSR - Interrupt Request Register (bits 95:64). */
|
---|
| 1529 | #define MSR_IA32_X2APIC_IRR2 0x822
|
---|
| 1530 | /** X2APIC MSR - Interrupt Request Register (bits 127:96). */
|
---|
| 1531 | #define MSR_IA32_X2APIC_IRR3 0x823
|
---|
| 1532 | /** X2APIC MSR - Interrupt Request Register (bits 159:128). */
|
---|
| 1533 | #define MSR_IA32_X2APIC_IRR4 0x824
|
---|
| 1534 | /** X2APIC MSR - Interrupt Request Register (bits 191:160). */
|
---|
| 1535 | #define MSR_IA32_X2APIC_IRR5 0x825
|
---|
| 1536 | /** X2APIC MSR - Interrupt Request Register (bits 223:192). */
|
---|
| 1537 | #define MSR_IA32_X2APIC_IRR6 0x826
|
---|
| 1538 | /** X2APIC MSR - Interrupt Request Register (bits 255:224). */
|
---|
| 1539 | #define MSR_IA32_X2APIC_IRR7 0x827
|
---|
| 1540 | /** X2APIC MSR - Error Status Register. */
|
---|
| 1541 | #define MSR_IA32_X2APIC_ESR 0x828
|
---|
| 1542 | /** X2APIC MSR - LVT CMCI Register. */
|
---|
| 1543 | #define MSR_IA32_X2APIC_LVT_CMCI 0x82F
|
---|
| 1544 | /** X2APIC MSR - Interrupt Command Register. */
|
---|
| 1545 | #define MSR_IA32_X2APIC_ICR 0x830
|
---|
| 1546 | /** X2APIC MSR - LVT Timer Register. */
|
---|
| 1547 | #define MSR_IA32_X2APIC_LVT_TIMER 0x832
|
---|
| 1548 | /** X2APIC MSR - LVT Thermal Sensor Register. */
|
---|
| 1549 | #define MSR_IA32_X2APIC_LVT_THERMAL 0x833
|
---|
| 1550 | /** X2APIC MSR - LVT Performance Counter Register. */
|
---|
| 1551 | #define MSR_IA32_X2APIC_LVT_PERF 0x834
|
---|
| 1552 | /** X2APIC MSR - LVT LINT0 Register. */
|
---|
| 1553 | #define MSR_IA32_X2APIC_LVT_LINT0 0x835
|
---|
| 1554 | /** X2APIC MSR - LVT LINT1 Register. */
|
---|
| 1555 | #define MSR_IA32_X2APIC_LVT_LINT1 0x836
|
---|
| 1556 | /** X2APIC MSR - LVT Error Register . */
|
---|
| 1557 | #define MSR_IA32_X2APIC_LVT_ERROR 0x837
|
---|
| 1558 | /** X2APIC MSR - Timer Initial Count Register. */
|
---|
| 1559 | #define MSR_IA32_X2APIC_TIMER_ICR 0x838
|
---|
| 1560 | /** X2APIC MSR - Timer Current Count Register. */
|
---|
| 1561 | #define MSR_IA32_X2APIC_TIMER_CCR 0x839
|
---|
| 1562 | /** X2APIC MSR - Timer Divide Configuration Register. */
|
---|
[59988] | 1563 | #define MSR_IA32_X2APIC_TIMER_DCR 0x83E
|
---|
[59897] | 1564 | /** X2APIC MSR - Self IPI. */
|
---|
| 1565 | #define MSR_IA32_X2APIC_SELF_IPI 0x83F
|
---|
| 1566 | /** X2APIC MSR range end. */
|
---|
[43974] | 1567 | #define MSR_IA32_X2APIC_END 0xBFF
|
---|
[59988] | 1568 | /** X2APIC MSR - LVT start range. */
|
---|
| 1569 | #define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
|
---|
| 1570 | /** X2APIC MSR - LVT end range (inclusive). */
|
---|
| 1571 | #define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
|
---|
[1] | 1572 |
|
---|
| 1573 | /** K6 EFER - Extended Feature Enable Register. */
|
---|
[47996] | 1574 | #define MSR_K6_EFER UINT32_C(0xc0000080)
|
---|
[1] | 1575 | /** @todo document EFER */
|
---|
| 1576 | /** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
|
---|
[59961] | 1577 | #define MSR_K6_EFER_SCE RT_BIT_32(0)
|
---|
[1] | 1578 | /** Bit 8 - LME - Long mode enabled. (R/W) */
|
---|
[59961] | 1579 | #define MSR_K6_EFER_LME RT_BIT_32(8)
|
---|
[74099] | 1580 | #define MSR_K6_EFER_BIT_LME 8 /**< Bit number of MSR_K6_EFER_LME */
|
---|
[1] | 1581 | /** Bit 10 - LMA - Long mode active. (R) */
|
---|
[59961] | 1582 | #define MSR_K6_EFER_LMA RT_BIT_32(10)
|
---|
[74099] | 1583 | #define MSR_K6_EFER_BIT_LMA 10 /**< Bit number of MSR_K6_EFER_LMA */
|
---|
[1] | 1584 | /** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
|
---|
[59961] | 1585 | #define MSR_K6_EFER_NXE RT_BIT_32(11)
|
---|
[62288] | 1586 | #define MSR_K6_EFER_BIT_NXE 11 /**< Bit number of MSR_K6_EFER_NXE */
|
---|
[1] | 1587 | /** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
|
---|
[59961] | 1588 | #define MSR_K6_EFER_SVME RT_BIT_32(12)
|
---|
[1] | 1589 | /** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
|
---|
[59961] | 1590 | #define MSR_K6_EFER_LMSLE RT_BIT_32(13)
|
---|
[1] | 1591 | /** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
|
---|
[59961] | 1592 | #define MSR_K6_EFER_FFXSR RT_BIT_32(14)
|
---|
[52778] | 1593 | /** Bit 15 - TCE - Translation Cache Extension. (R/W) */
|
---|
[59961] | 1594 | #define MSR_K6_EFER_TCE RT_BIT_32(15)
|
---|
[1] | 1595 | /** K6 STAR - SYSCALL/RET targets. */
|
---|
[47996] | 1596 | #define MSR_K6_STAR UINT32_C(0xc0000081)
|
---|
[1] | 1597 | /** Shift value for getting the SYSRET CS and SS value. */
|
---|
| 1598 | #define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
|
---|
| 1599 | /** Shift value for getting the SYSCALL CS and SS value. */
|
---|
| 1600 | #define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
|
---|
| 1601 | /** Selector mask for use after shifting. */
|
---|
[47996] | 1602 | #define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
|
---|
[1] | 1603 | /** The mask which give the SYSCALL EIP. */
|
---|
[47996] | 1604 | #define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
|
---|
[1] | 1605 | /** K6 WHCR - Write Handling Control Register. */
|
---|
[47996] | 1606 | #define MSR_K6_WHCR UINT32_C(0xc0000082)
|
---|
[1] | 1607 | /** K6 UWCCR - UC/WC Cacheability Control Register. */
|
---|
[47996] | 1608 | #define MSR_K6_UWCCR UINT32_C(0xc0000085)
|
---|
[1] | 1609 | /** K6 PSOR - Processor State Observability Register. */
|
---|
[47996] | 1610 | #define MSR_K6_PSOR UINT32_C(0xc0000087)
|
---|
[1] | 1611 | /** K6 PFIR - Page Flush/Invalidate Register. */
|
---|
[47996] | 1612 | #define MSR_K6_PFIR UINT32_C(0xc0000088)
|
---|
[1] | 1613 |
|
---|
[18763] | 1614 | /** Performance counter MSRs. (AMD only) */
|
---|
[47996] | 1615 | #define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
|
---|
| 1616 | #define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
|
---|
| 1617 | #define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
|
---|
| 1618 | #define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
|
---|
| 1619 | #define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
|
---|
| 1620 | #define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
|
---|
| 1621 | #define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
|
---|
| 1622 | #define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
|
---|
[1] | 1623 |
|
---|
| 1624 | /** K8 LSTAR - Long mode SYSCALL target (RIP). */
|
---|
[47996] | 1625 | #define MSR_K8_LSTAR UINT32_C(0xc0000082)
|
---|
[1] | 1626 | /** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
|
---|
[47996] | 1627 | #define MSR_K8_CSTAR UINT32_C(0xc0000083)
|
---|
[1] | 1628 | /** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
|
---|
[47996] | 1629 | #define MSR_K8_SF_MASK UINT32_C(0xc0000084)
|
---|
[1] | 1630 | /** K8 FS.base - The 64-bit base FS register. */
|
---|
[47996] | 1631 | #define MSR_K8_FS_BASE UINT32_C(0xc0000100)
|
---|
[48267] | 1632 | /** K8 GS.base - The 64-bit base GS register. */
|
---|
[47996] | 1633 | #define MSR_K8_GS_BASE UINT32_C(0xc0000101)
|
---|
[1] | 1634 | /** K8 KernelGSbase - Used with SWAPGS. */
|
---|
[47996] | 1635 | #define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
|
---|
[42056] | 1636 | /** K8 TSC_AUX - Used with RDTSCP. */
|
---|
[47996] | 1637 | #define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
|
---|
| 1638 | #define MSR_K8_SYSCFG UINT32_C(0xc0010010)
|
---|
| 1639 | #define MSR_K8_HWCR UINT32_C(0xc0010015)
|
---|
| 1640 | #define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
|
---|
| 1641 | #define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
|
---|
| 1642 | #define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
|
---|
| 1643 | #define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
|
---|
| 1644 | #define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
|
---|
| 1645 | #define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
|
---|
| 1646 | /** North bridge config? See BIOS & Kernel dev guides for
|
---|
| 1647 | * details. */
|
---|
| 1648 | #define MSR_K8_NB_CFG UINT32_C(0xc001001f)
|
---|
| 1649 |
|
---|
[47942] | 1650 | /** Hypertransport interrupt pending register.
|
---|
| 1651 | * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
|
---|
[47996] | 1652 | #define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
|
---|
[65904] | 1653 |
|
---|
| 1654 | /** SVM Control. */
|
---|
[47996] | 1655 | #define MSR_K8_VM_CR UINT32_C(0xc0010114)
|
---|
[65904] | 1656 | /** Disables HDT (Hardware Debug Tool) and certain internal debug
|
---|
| 1657 | * features. */
|
---|
| 1658 | #define MSR_K8_VM_CR_DPD RT_BIT_32(0)
|
---|
| 1659 | /** If set, non-intercepted INIT signals are converted to \#SX
|
---|
| 1660 | * exceptions. */
|
---|
| 1661 | #define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
|
---|
| 1662 | /** Disables A20 masking. */
|
---|
| 1663 | #define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
|
---|
| 1664 | /** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
|
---|
| 1665 | #define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
|
---|
| 1666 | /** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
|
---|
| 1667 | * clear, EFER.SVME can be written normally. */
|
---|
[59961] | 1668 | #define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
|
---|
[3748] | 1669 |
|
---|
[47996] | 1670 | #define MSR_K8_IGNNE UINT32_C(0xc0010115)
|
---|
| 1671 | #define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
|
---|
[1] | 1672 | /** SVM - VM_HSAVE_PA - Physical address for saving and restoring
|
---|
[47996] | 1673 | * host state during world switch. */
|
---|
| 1674 | #define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
|
---|
[1] | 1675 |
|
---|
| 1676 | /** @} */
|
---|
| 1677 |
|
---|
| 1678 |
|
---|
| 1679 | /** @name Page Table / Directory / Directory Pointers / L4.
|
---|
| 1680 | * @{
|
---|
| 1681 | */
|
---|
| 1682 |
|
---|
| 1683 | /** Page table/directory entry as an unsigned integer. */
|
---|
| 1684 | typedef uint32_t X86PGUINT;
|
---|
| 1685 | /** Pointer to a page table/directory table entry as an unsigned integer. */
|
---|
| 1686 | typedef X86PGUINT *PX86PGUINT;
|
---|
[14747] | 1687 | /** Pointer to an const page table/directory table entry as an unsigned integer. */
|
---|
| 1688 | typedef X86PGUINT const *PCX86PGUINT;
|
---|
[1] | 1689 |
|
---|
| 1690 | /** Number of entries in a 32-bit PT/PD. */
|
---|
| 1691 | #define X86_PG_ENTRIES 1024
|
---|
| 1692 |
|
---|
| 1693 |
|
---|
[7705] | 1694 | /** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
|
---|
[1] | 1695 | typedef uint64_t X86PGPAEUINT;
|
---|
[7705] | 1696 | /** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
|
---|
[1] | 1697 | typedef X86PGPAEUINT *PX86PGPAEUINT;
|
---|
[14747] | 1698 | /** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
|
---|
| 1699 | typedef X86PGPAEUINT const *PCX86PGPAEUINT;
|
---|
[1] | 1700 |
|
---|
[7705] | 1701 | /** Number of entries in a PAE PT/PD. */
|
---|
[1] | 1702 | #define X86_PG_PAE_ENTRIES 512
|
---|
[7705] | 1703 | /** Number of entries in a PAE PDPT. */
|
---|
[7677] | 1704 | #define X86_PG_PAE_PDPE_ENTRIES 4
|
---|
[1] | 1705 |
|
---|
[7705] | 1706 | /** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
|
---|
[7676] | 1707 | #define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
|
---|
[7705] | 1708 | /** Number of entries in an AMD64 PDPT.
|
---|
| 1709 | * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
|
---|
| 1710 | #define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
|
---|
[1] | 1711 |
|
---|
[60677] | 1712 | /** The size of a default page. */
|
---|
| 1713 | #define X86_PAGE_SIZE X86_PAGE_4K_SIZE
|
---|
| 1714 | /** The page shift of a default page. */
|
---|
| 1715 | #define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
|
---|
| 1716 | /** The default page offset mask. */
|
---|
| 1717 | #define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
|
---|
[61072] | 1718 | /** The default page base mask for virtual addresses. */
|
---|
[60677] | 1719 | #define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
|
---|
| 1720 | /** The default page base mask for virtual addresses - 32bit version. */
|
---|
| 1721 | #define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
|
---|
| 1722 |
|
---|
[1] | 1723 | /** The size of a 4KB page. */
|
---|
| 1724 | #define X86_PAGE_4K_SIZE _4K
|
---|
| 1725 | /** The page shift of a 4KB page. */
|
---|
| 1726 | #define X86_PAGE_4K_SHIFT 12
|
---|
| 1727 | /** The 4KB page offset mask. */
|
---|
| 1728 | #define X86_PAGE_4K_OFFSET_MASK 0xfff
|
---|
| 1729 | /** The 4KB page base mask for virtual addresses. */
|
---|
| 1730 | #define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
|
---|
| 1731 | /** The 4KB page base mask for virtual addresses - 32bit version. */
|
---|
| 1732 | #define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
|
---|
| 1733 |
|
---|
| 1734 | /** The size of a 2MB page. */
|
---|
| 1735 | #define X86_PAGE_2M_SIZE _2M
|
---|
| 1736 | /** The page shift of a 2MB page. */
|
---|
| 1737 | #define X86_PAGE_2M_SHIFT 21
|
---|
| 1738 | /** The 2MB page offset mask. */
|
---|
| 1739 | #define X86_PAGE_2M_OFFSET_MASK 0x001fffff
|
---|
| 1740 | /** The 2MB page base mask for virtual addresses. */
|
---|
| 1741 | #define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
|
---|
| 1742 | /** The 2MB page base mask for virtual addresses - 32bit version. */
|
---|
| 1743 | #define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
|
---|
| 1744 |
|
---|
| 1745 | /** The size of a 4MB page. */
|
---|
| 1746 | #define X86_PAGE_4M_SIZE _4M
|
---|
| 1747 | /** The page shift of a 4MB page. */
|
---|
| 1748 | #define X86_PAGE_4M_SHIFT 22
|
---|
| 1749 | /** The 4MB page offset mask. */
|
---|
| 1750 | #define X86_PAGE_4M_OFFSET_MASK 0x003fffff
|
---|
| 1751 | /** The 4MB page base mask for virtual addresses. */
|
---|
| 1752 | #define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
|
---|
| 1753 | /** The 4MB page base mask for virtual addresses - 32bit version. */
|
---|
| 1754 | #define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
|
---|
| 1755 |
|
---|
[73073] | 1756 | /** The size of a 1GB page. */
|
---|
| 1757 | #define X86_PAGE_1G_SIZE _1G
|
---|
| 1758 | /** The page shift of a 1GB page. */
|
---|
| 1759 | #define X86_PAGE_1G_SHIFT 30
|
---|
| 1760 | /** The 1GB page offset mask. */
|
---|
| 1761 | #define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
|
---|
| 1762 | /** The 1GB page base mask for virtual addresses. */
|
---|
| 1763 | #define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
|
---|
| 1764 |
|
---|
[49391] | 1765 | /**
|
---|
| 1766 | * Check if the given address is canonical.
|
---|
| 1767 | */
|
---|
| 1768 | #define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
|
---|
[1] | 1769 |
|
---|
| 1770 |
|
---|
| 1771 | /** @name Page Table Entry
|
---|
| 1772 | * @{
|
---|
| 1773 | */
|
---|
| 1774 | /** Bit 0 - P - Present bit. */
|
---|
[14741] | 1775 | #define X86_PTE_BIT_P 0
|
---|
| 1776 | /** Bit 1 - R/W - Read (clear) / Write (set) bit. */
|
---|
[18090] | 1777 | #define X86_PTE_BIT_RW 1
|
---|
[14741] | 1778 | /** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
|
---|
| 1779 | #define X86_PTE_BIT_US 2
|
---|
| 1780 | /** Bit 3 - PWT - Page level write thru bit. */
|
---|
| 1781 | #define X86_PTE_BIT_PWT 3
|
---|
| 1782 | /** Bit 4 - PCD - Page level cache disable bit. */
|
---|
| 1783 | #define X86_PTE_BIT_PCD 4
|
---|
| 1784 | /** Bit 5 - A - Access bit. */
|
---|
| 1785 | #define X86_PTE_BIT_A 5
|
---|
| 1786 | /** Bit 6 - D - Dirty bit. */
|
---|
| 1787 | #define X86_PTE_BIT_D 6
|
---|
| 1788 | /** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
|
---|
| 1789 | #define X86_PTE_BIT_PAT 7
|
---|
| 1790 | /** Bit 8 - G - Global flag. */
|
---|
| 1791 | #define X86_PTE_BIT_G 8
|
---|
[62288] | 1792 | /** Bits 63 - NX - PAE/LM - No execution flag. */
|
---|
| 1793 | #define X86_PTE_PAE_BIT_NX 63
|
---|
[14741] | 1794 |
|
---|
| 1795 | /** Bit 0 - P - Present bit mask. */
|
---|
[59961] | 1796 | #define X86_PTE_P RT_BIT_32(0)
|
---|
[14741] | 1797 | /** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
|
---|
[59961] | 1798 | #define X86_PTE_RW RT_BIT_32(1)
|
---|
[14741] | 1799 | /** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
|
---|
[59961] | 1800 | #define X86_PTE_US RT_BIT_32(2)
|
---|
[14741] | 1801 | /** Bit 3 - PWT - Page level write thru bit mask. */
|
---|
[59961] | 1802 | #define X86_PTE_PWT RT_BIT_32(3)
|
---|
[14741] | 1803 | /** Bit 4 - PCD - Page level cache disable bit mask. */
|
---|
[59961] | 1804 | #define X86_PTE_PCD RT_BIT_32(4)
|
---|
[14741] | 1805 | /** Bit 5 - A - Access bit mask. */
|
---|
[59961] | 1806 | #define X86_PTE_A RT_BIT_32(5)
|
---|
[14741] | 1807 | /** Bit 6 - D - Dirty bit mask. */
|
---|
[59961] | 1808 | #define X86_PTE_D RT_BIT_32(6)
|
---|
[14741] | 1809 | /** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
|
---|
[59961] | 1810 | #define X86_PTE_PAT RT_BIT_32(7)
|
---|
[14741] | 1811 | /** Bit 8 - G - Global bit mask. */
|
---|
[59961] | 1812 | #define X86_PTE_G RT_BIT_32(8)
|
---|
[14741] | 1813 |
|
---|
[1] | 1814 | /** Bits 9-11 - - Available for use to system software. */
|
---|
[59961] | 1815 | #define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
|
---|
[1] | 1816 | /** Bits 12-31 - - Physical Page number of the next level. */
|
---|
| 1817 | #define X86_PTE_PG_MASK ( 0xfffff000 )
|
---|
| 1818 |
|
---|
[7705] | 1819 | /** Bits 12-51 - - PAE - Physical Page number of the next level. */
|
---|
[32036] | 1820 | #define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
|
---|
[30889] | 1821 | /** Bits 63 - NX - PAE/LM - No execution flag. */
|
---|
[5605] | 1822 | #define X86_PTE_PAE_NX RT_BIT_64(63)
|
---|
[30889] | 1823 | /** Bits 62-52 - - PAE - MBZ bits when NX is active. */
|
---|
| 1824 | #define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
|
---|
| 1825 | /** Bits 63-52 - - PAE - MBZ bits when no NX. */
|
---|
| 1826 | #define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
|
---|
| 1827 | /** No bits - - LM - MBZ bits when NX is active. */
|
---|
| 1828 | #define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
|
---|
| 1829 | /** Bits 63 - - LM - MBZ bits when no NX. */
|
---|
| 1830 | #define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
|
---|
[1] | 1831 |
|
---|
| 1832 | /**
|
---|
| 1833 | * Page table entry.
|
---|
| 1834 | */
|
---|
| 1835 | typedef struct X86PTEBITS
|
---|
| 1836 | {
|
---|
| 1837 | /** Flags whether(=1) or not the page is present. */
|
---|
[58693] | 1838 | uint32_t u1Present : 1;
|
---|
[1] | 1839 | /** Read(=0) / Write(=1) flag. */
|
---|
[58693] | 1840 | uint32_t u1Write : 1;
|
---|
[1] | 1841 | /** User(=1) / Supervisor (=0) flag. */
|
---|
[58693] | 1842 | uint32_t u1User : 1;
|
---|
[1] | 1843 | /** Write Thru flag. If PAT enabled, bit 0 of the index. */
|
---|
[58693] | 1844 | uint32_t u1WriteThru : 1;
|
---|
[1] | 1845 | /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
|
---|
[58693] | 1846 | uint32_t u1CacheDisable : 1;
|
---|
[1] | 1847 | /** Accessed flag.
|
---|
| 1848 | * Indicates that the page have been read or written to. */
|
---|
[58693] | 1849 | uint32_t u1Accessed : 1;
|
---|
[1] | 1850 | /** Dirty flag.
|
---|
[27109] | 1851 | * Indicates that the page has been written to. */
|
---|
[58693] | 1852 | uint32_t u1Dirty : 1;
|
---|
[1] | 1853 | /** Reserved / If PAT enabled, bit 2 of the index. */
|
---|
[58693] | 1854 | uint32_t u1PAT : 1;
|
---|
[1] | 1855 | /** Global flag. (Ignored in all but final level.) */
|
---|
[58693] | 1856 | uint32_t u1Global : 1;
|
---|
[1] | 1857 | /** Available for use to system software. */
|
---|
[58693] | 1858 | uint32_t u3Available : 3;
|
---|
[1] | 1859 | /** Physical Page number of the next level. */
|
---|
[58693] | 1860 | uint32_t u20PageNo : 20;
|
---|
[1] | 1861 | } X86PTEBITS;
|
---|
[59238] | 1862 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1863 | AssertCompileSize(X86PTEBITS, 4);
|
---|
| 1864 | #endif
|
---|
[1] | 1865 | /** Pointer to a page table entry. */
|
---|
| 1866 | typedef X86PTEBITS *PX86PTEBITS;
|
---|
| 1867 | /** Pointer to a const page table entry. */
|
---|
| 1868 | typedef const X86PTEBITS *PCX86PTEBITS;
|
---|
| 1869 |
|
---|
| 1870 | /**
|
---|
| 1871 | * Page table entry.
|
---|
| 1872 | */
|
---|
| 1873 | typedef union X86PTE
|
---|
| 1874 | {
|
---|
[14135] | 1875 | /** Unsigned integer view */
|
---|
| 1876 | X86PGUINT u;
|
---|
[1] | 1877 | /** Bit field view. */
|
---|
| 1878 | X86PTEBITS n;
|
---|
| 1879 | /** 32-bit view. */
|
---|
| 1880 | uint32_t au32[1];
|
---|
| 1881 | /** 16-bit view. */
|
---|
| 1882 | uint16_t au16[2];
|
---|
| 1883 | /** 8-bit view. */
|
---|
| 1884 | uint8_t au8[4];
|
---|
| 1885 | } X86PTE;
|
---|
[59238] | 1886 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1887 | AssertCompileSize(X86PTE, 4);
|
---|
| 1888 | #endif
|
---|
[1] | 1889 | /** Pointer to a page table entry. */
|
---|
| 1890 | typedef X86PTE *PX86PTE;
|
---|
| 1891 | /** Pointer to a const page table entry. */
|
---|
| 1892 | typedef const X86PTE *PCX86PTE;
|
---|
| 1893 |
|
---|
| 1894 |
|
---|
| 1895 | /**
|
---|
| 1896 | * PAE page table entry.
|
---|
| 1897 | */
|
---|
| 1898 | typedef struct X86PTEPAEBITS
|
---|
| 1899 | {
|
---|
| 1900 | /** Flags whether(=1) or not the page is present. */
|
---|
| 1901 | uint32_t u1Present : 1;
|
---|
| 1902 | /** Read(=0) / Write(=1) flag. */
|
---|
| 1903 | uint32_t u1Write : 1;
|
---|
| 1904 | /** User(=1) / Supervisor(=0) flag. */
|
---|
| 1905 | uint32_t u1User : 1;
|
---|
| 1906 | /** Write Thru flag. If PAT enabled, bit 0 of the index. */
|
---|
| 1907 | uint32_t u1WriteThru : 1;
|
---|
| 1908 | /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
|
---|
| 1909 | uint32_t u1CacheDisable : 1;
|
---|
| 1910 | /** Accessed flag.
|
---|
| 1911 | * Indicates that the page have been read or written to. */
|
---|
| 1912 | uint32_t u1Accessed : 1;
|
---|
| 1913 | /** Dirty flag.
|
---|
[27109] | 1914 | * Indicates that the page has been written to. */
|
---|
[1] | 1915 | uint32_t u1Dirty : 1;
|
---|
| 1916 | /** Reserved / If PAT enabled, bit 2 of the index. */
|
---|
| 1917 | uint32_t u1PAT : 1;
|
---|
| 1918 | /** Global flag. (Ignored in all but final level.) */
|
---|
| 1919 | uint32_t u1Global : 1;
|
---|
| 1920 | /** Available for use to system software. */
|
---|
| 1921 | uint32_t u3Available : 3;
|
---|
| 1922 | /** Physical Page number of the next level - Low Part. Don't use this. */
|
---|
| 1923 | uint32_t u20PageNoLow : 20;
|
---|
| 1924 | /** Physical Page number of the next level - High Part. Don't use this. */
|
---|
| 1925 | uint32_t u20PageNoHigh : 20;
|
---|
| 1926 | /** MBZ bits */
|
---|
| 1927 | uint32_t u11Reserved : 11;
|
---|
| 1928 | /** No Execute flag. */
|
---|
| 1929 | uint32_t u1NoExecute : 1;
|
---|
| 1930 | } X86PTEPAEBITS;
|
---|
[59238] | 1931 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1932 | AssertCompileSize(X86PTEPAEBITS, 8);
|
---|
| 1933 | #endif
|
---|
[1] | 1934 | /** Pointer to a page table entry. */
|
---|
| 1935 | typedef X86PTEPAEBITS *PX86PTEPAEBITS;
|
---|
| 1936 | /** Pointer to a page table entry. */
|
---|
| 1937 | typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
|
---|
| 1938 |
|
---|
| 1939 | /**
|
---|
| 1940 | * PAE Page table entry.
|
---|
| 1941 | */
|
---|
| 1942 | typedef union X86PTEPAE
|
---|
| 1943 | {
|
---|
[14135] | 1944 | /** Unsigned integer view */
|
---|
| 1945 | X86PGPAEUINT u;
|
---|
[1] | 1946 | /** Bit field view. */
|
---|
| 1947 | X86PTEPAEBITS n;
|
---|
| 1948 | /** 32-bit view. */
|
---|
| 1949 | uint32_t au32[2];
|
---|
| 1950 | /** 16-bit view. */
|
---|
| 1951 | uint16_t au16[4];
|
---|
| 1952 | /** 8-bit view. */
|
---|
| 1953 | uint8_t au8[8];
|
---|
| 1954 | } X86PTEPAE;
|
---|
[59238] | 1955 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1956 | AssertCompileSize(X86PTEPAE, 8);
|
---|
| 1957 | #endif
|
---|
[1] | 1958 | /** Pointer to a PAE page table entry. */
|
---|
| 1959 | typedef X86PTEPAE *PX86PTEPAE;
|
---|
| 1960 | /** Pointer to a const PAE page table entry. */
|
---|
| 1961 | typedef const X86PTEPAE *PCX86PTEPAE;
|
---|
| 1962 | /** @} */
|
---|
| 1963 |
|
---|
| 1964 | /**
|
---|
| 1965 | * Page table.
|
---|
| 1966 | */
|
---|
| 1967 | typedef struct X86PT
|
---|
| 1968 | {
|
---|
| 1969 | /** PTE Array. */
|
---|
| 1970 | X86PTE a[X86_PG_ENTRIES];
|
---|
| 1971 | } X86PT;
|
---|
[59238] | 1972 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1973 | AssertCompileSize(X86PT, 4096);
|
---|
| 1974 | #endif
|
---|
[1] | 1975 | /** Pointer to a page table. */
|
---|
| 1976 | typedef X86PT *PX86PT;
|
---|
| 1977 | /** Pointer to a const page table. */
|
---|
| 1978 | typedef const X86PT *PCX86PT;
|
---|
| 1979 |
|
---|
| 1980 | /** The page shift to get the PT index. */
|
---|
| 1981 | #define X86_PT_SHIFT 12
|
---|
| 1982 | /** The PT index mask (apply to a shifted page address). */
|
---|
| 1983 | #define X86_PT_MASK 0x3ff
|
---|
| 1984 |
|
---|
| 1985 |
|
---|
| 1986 | /**
|
---|
| 1987 | * Page directory.
|
---|
| 1988 | */
|
---|
| 1989 | typedef struct X86PTPAE
|
---|
| 1990 | {
|
---|
| 1991 | /** PTE Array. */
|
---|
| 1992 | X86PTEPAE a[X86_PG_PAE_ENTRIES];
|
---|
| 1993 | } X86PTPAE;
|
---|
[59238] | 1994 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1995 | AssertCompileSize(X86PTPAE, 4096);
|
---|
| 1996 | #endif
|
---|
[1] | 1997 | /** Pointer to a page table. */
|
---|
| 1998 | typedef X86PTPAE *PX86PTPAE;
|
---|
| 1999 | /** Pointer to a const page table. */
|
---|
| 2000 | typedef const X86PTPAE *PCX86PTPAE;
|
---|
| 2001 |
|
---|
| 2002 | /** The page shift to get the PA PTE index. */
|
---|
| 2003 | #define X86_PT_PAE_SHIFT 12
|
---|
| 2004 | /** The PAE PT index mask (apply to a shifted page address). */
|
---|
| 2005 | #define X86_PT_PAE_MASK 0x1ff
|
---|
| 2006 |
|
---|
| 2007 |
|
---|
| 2008 | /** @name 4KB Page Directory Entry
|
---|
| 2009 | * @{
|
---|
| 2010 | */
|
---|
| 2011 | /** Bit 0 - P - Present bit. */
|
---|
[59961] | 2012 | #define X86_PDE_P RT_BIT_32(0)
|
---|
[1] | 2013 | /** Bit 1 - R/W - Read (clear) / Write (set) bit. */
|
---|
[59961] | 2014 | #define X86_PDE_RW RT_BIT_32(1)
|
---|
[1] | 2015 | /** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
|
---|
[59961] | 2016 | #define X86_PDE_US RT_BIT_32(2)
|
---|
[1] | 2017 | /** Bit 3 - PWT - Page level write thru bit. */
|
---|
[59961] | 2018 | #define X86_PDE_PWT RT_BIT_32(3)
|
---|
[1] | 2019 | /** Bit 4 - PCD - Page level cache disable bit. */
|
---|
[59961] | 2020 | #define X86_PDE_PCD RT_BIT_32(4)
|
---|
[1] | 2021 | /** Bit 5 - A - Access bit. */
|
---|
[59961] | 2022 | #define X86_PDE_A RT_BIT_32(5)
|
---|
[1] | 2023 | /** Bit 7 - PS - Page size attribute.
|
---|
| 2024 | * Clear mean 4KB pages, set means large pages (2/4MB). */
|
---|
[59961] | 2025 | #define X86_PDE_PS RT_BIT_32(7)
|
---|
[1] | 2026 | /** Bits 9-11 - - Available for use to system software. */
|
---|
[59961] | 2027 | #define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
|
---|
[1] | 2028 | /** Bits 12-31 - - Physical Page number of the next level. */
|
---|
| 2029 | #define X86_PDE_PG_MASK ( 0xfffff000 )
|
---|
| 2030 |
|
---|
| 2031 | /** Bits 12-51 - - PAE - Physical Page number of the next level. */
|
---|
[32034] | 2032 | #define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
|
---|
[30889] | 2033 | /** Bits 63 - NX - PAE/LM - No execution flag. */
|
---|
[5605] | 2034 | #define X86_PDE_PAE_NX RT_BIT_64(63)
|
---|
[30889] | 2035 | /** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
|
---|
| 2036 | #define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
|
---|
| 2037 | /** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
|
---|
| 2038 | #define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
|
---|
| 2039 | /** Bit 7 - - LM - MBZ bits when NX is active. */
|
---|
| 2040 | #define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
|
---|
| 2041 | /** Bits 63, 7 - - LM - MBZ bits when no NX. */
|
---|
| 2042 | #define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
|
---|
[1] | 2043 |
|
---|
| 2044 | /**
|
---|
| 2045 | * Page directory entry.
|
---|
| 2046 | */
|
---|
| 2047 | typedef struct X86PDEBITS
|
---|
| 2048 | {
|
---|
| 2049 | /** Flags whether(=1) or not the page is present. */
|
---|
[58693] | 2050 | uint32_t u1Present : 1;
|
---|
[1] | 2051 | /** Read(=0) / Write(=1) flag. */
|
---|
[58693] | 2052 | uint32_t u1Write : 1;
|
---|
[1] | 2053 | /** User(=1) / Supervisor (=0) flag. */
|
---|
[58693] | 2054 | uint32_t u1User : 1;
|
---|
[1] | 2055 | /** Write Thru flag. If PAT enabled, bit 0 of the index. */
|
---|
[58693] | 2056 | uint32_t u1WriteThru : 1;
|
---|
[1] | 2057 | /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
|
---|
[58693] | 2058 | uint32_t u1CacheDisable : 1;
|
---|
[1] | 2059 | /** Accessed flag.
|
---|
[27109] | 2060 | * Indicates that the page has been read or written to. */
|
---|
[58693] | 2061 | uint32_t u1Accessed : 1;
|
---|
[1] | 2062 | /** Reserved / Ignored (dirty bit). */
|
---|
[58693] | 2063 | uint32_t u1Reserved0 : 1;
|
---|
[1] | 2064 | /** Size bit if PSE is enabled - in any event it's 0. */
|
---|
[58693] | 2065 | uint32_t u1Size : 1;
|
---|
[1] | 2066 | /** Reserved / Ignored (global bit). */
|
---|
[58693] | 2067 | uint32_t u1Reserved1 : 1;
|
---|
[1] | 2068 | /** Available for use to system software. */
|
---|
[58693] | 2069 | uint32_t u3Available : 3;
|
---|
[1] | 2070 | /** Physical Page number of the next level. */
|
---|
[58693] | 2071 | uint32_t u20PageNo : 20;
|
---|
[1] | 2072 | } X86PDEBITS;
|
---|
[59238] | 2073 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2074 | AssertCompileSize(X86PDEBITS, 4);
|
---|
| 2075 | #endif
|
---|
[1] | 2076 | /** Pointer to a page directory entry. */
|
---|
| 2077 | typedef X86PDEBITS *PX86PDEBITS;
|
---|
| 2078 | /** Pointer to a const page directory entry. */
|
---|
| 2079 | typedef const X86PDEBITS *PCX86PDEBITS;
|
---|
| 2080 |
|
---|
| 2081 |
|
---|
| 2082 | /**
|
---|
| 2083 | * PAE page directory entry.
|
---|
| 2084 | */
|
---|
| 2085 | typedef struct X86PDEPAEBITS
|
---|
| 2086 | {
|
---|
| 2087 | /** Flags whether(=1) or not the page is present. */
|
---|
| 2088 | uint32_t u1Present : 1;
|
---|
| 2089 | /** Read(=0) / Write(=1) flag. */
|
---|
| 2090 | uint32_t u1Write : 1;
|
---|
| 2091 | /** User(=1) / Supervisor (=0) flag. */
|
---|
| 2092 | uint32_t u1User : 1;
|
---|
| 2093 | /** Write Thru flag. If PAT enabled, bit 0 of the index. */
|
---|
| 2094 | uint32_t u1WriteThru : 1;
|
---|
| 2095 | /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
|
---|
| 2096 | uint32_t u1CacheDisable : 1;
|
---|
| 2097 | /** Accessed flag.
|
---|
[27109] | 2098 | * Indicates that the page has been read or written to. */
|
---|
[1] | 2099 | uint32_t u1Accessed : 1;
|
---|
| 2100 | /** Reserved / Ignored (dirty bit). */
|
---|
| 2101 | uint32_t u1Reserved0 : 1;
|
---|
| 2102 | /** Size bit if PSE is enabled - in any event it's 0. */
|
---|
| 2103 | uint32_t u1Size : 1;
|
---|
| 2104 | /** Reserved / Ignored (global bit). / */
|
---|
| 2105 | uint32_t u1Reserved1 : 1;
|
---|
| 2106 | /** Available for use to system software. */
|
---|
| 2107 | uint32_t u3Available : 3;
|
---|
| 2108 | /** Physical Page number of the next level - Low Part. Don't use! */
|
---|
| 2109 | uint32_t u20PageNoLow : 20;
|
---|
| 2110 | /** Physical Page number of the next level - High Part. Don't use! */
|
---|
| 2111 | uint32_t u20PageNoHigh : 20;
|
---|
| 2112 | /** MBZ bits */
|
---|
| 2113 | uint32_t u11Reserved : 11;
|
---|
| 2114 | /** No Execute flag. */
|
---|
| 2115 | uint32_t u1NoExecute : 1;
|
---|
| 2116 | } X86PDEPAEBITS;
|
---|
[59238] | 2117 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2118 | AssertCompileSize(X86PDEPAEBITS, 8);
|
---|
| 2119 | #endif
|
---|
[1] | 2120 | /** Pointer to a page directory entry. */
|
---|
| 2121 | typedef X86PDEPAEBITS *PX86PDEPAEBITS;
|
---|
| 2122 | /** Pointer to a const page directory entry. */
|
---|
| 2123 | typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
|
---|
| 2124 |
|
---|
| 2125 | /** @} */
|
---|
| 2126 |
|
---|
| 2127 |
|
---|
| 2128 | /** @name 2/4MB Page Directory Entry
|
---|
| 2129 | * @{
|
---|
| 2130 | */
|
---|
| 2131 | /** Bit 0 - P - Present bit. */
|
---|
[59961] | 2132 | #define X86_PDE4M_P RT_BIT_32(0)
|
---|
[1] | 2133 | /** Bit 1 - R/W - Read (clear) / Write (set) bit. */
|
---|
[59961] | 2134 | #define X86_PDE4M_RW RT_BIT_32(1)
|
---|
[1] | 2135 | /** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
|
---|
[59961] | 2136 | #define X86_PDE4M_US RT_BIT_32(2)
|
---|
[1] | 2137 | /** Bit 3 - PWT - Page level write thru bit. */
|
---|
[59961] | 2138 | #define X86_PDE4M_PWT RT_BIT_32(3)
|
---|
[1] | 2139 | /** Bit 4 - PCD - Page level cache disable bit. */
|
---|
[59961] | 2140 | #define X86_PDE4M_PCD RT_BIT_32(4)
|
---|
[1] | 2141 | /** Bit 5 - A - Access bit. */
|
---|
[59961] | 2142 | #define X86_PDE4M_A RT_BIT_32(5)
|
---|
[1] | 2143 | /** Bit 6 - D - Dirty bit. */
|
---|
[59961] | 2144 | #define X86_PDE4M_D RT_BIT_32(6)
|
---|
[1] | 2145 | /** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
|
---|
[59961] | 2146 | #define X86_PDE4M_PS RT_BIT_32(7)
|
---|
[1] | 2147 | /** Bit 8 - G - Global flag. */
|
---|
[59961] | 2148 | #define X86_PDE4M_G RT_BIT_32(8)
|
---|
[1] | 2149 | /** Bits 9-11 - AVL - Available for use to system software. */
|
---|
[59961] | 2150 | #define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
|
---|
[1] | 2151 | /** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
|
---|
[59961] | 2152 | #define X86_PDE4M_PAT RT_BIT_32(12)
|
---|
[1] | 2153 | /** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
|
---|
| 2154 | #define X86_PDE4M_PAT_SHIFT (12 - 7)
|
---|
| 2155 | /** Bits 22-31 - - Physical Page number. */
|
---|
| 2156 | #define X86_PDE4M_PG_MASK ( 0xffc00000 )
|
---|
[30889] | 2157 | /** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
|
---|
[1] | 2158 | #define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
|
---|
| 2159 | /** The number of bits to the high part of the page number. */
|
---|
| 2160 | #define X86_PDE4M_PG_HIGH_SHIFT 19
|
---|
[30889] | 2161 | /** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
|
---|
| 2162 | #define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
|
---|
[1] | 2163 |
|
---|
[30889] | 2164 | /** Bits 21-51 - - PAE/LM - Physical Page number.
|
---|
[7705] | 2165 | * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
|
---|
[30889] | 2166 | #define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
|
---|
| 2167 | /** Bits 63 - NX - PAE/LM - No execution flag. */
|
---|
| 2168 | #define X86_PDE2M_PAE_NX RT_BIT_64(63)
|
---|
| 2169 | /** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
|
---|
| 2170 | #define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
|
---|
| 2171 | /** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
|
---|
| 2172 | #define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
|
---|
| 2173 | /** Bits 20-13 - - LM - MBZ bits when NX is active. */
|
---|
| 2174 | #define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
|
---|
| 2175 | /** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
|
---|
| 2176 | #define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
|
---|
[1] | 2177 |
|
---|
| 2178 | /**
|
---|
| 2179 | * 4MB page directory entry.
|
---|
| 2180 | */
|
---|
| 2181 | typedef struct X86PDE4MBITS
|
---|
| 2182 | {
|
---|
| 2183 | /** Flags whether(=1) or not the page is present. */
|
---|
[59238] | 2184 | uint32_t u1Present : 1;
|
---|
[1] | 2185 | /** Read(=0) / Write(=1) flag. */
|
---|
[59238] | 2186 | uint32_t u1Write : 1;
|
---|
[1] | 2187 | /** User(=1) / Supervisor (=0) flag. */
|
---|
[59238] | 2188 | uint32_t u1User : 1;
|
---|
[1] | 2189 | /** Write Thru flag. If PAT enabled, bit 0 of the index. */
|
---|
[59238] | 2190 | uint32_t u1WriteThru : 1;
|
---|
[1] | 2191 | /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
|
---|
[59238] | 2192 | uint32_t u1CacheDisable : 1;
|
---|
[1] | 2193 | /** Accessed flag.
|
---|
| 2194 | * Indicates that the page have been read or written to. */
|
---|
[59238] | 2195 | uint32_t u1Accessed : 1;
|
---|
[1] | 2196 | /** Dirty flag.
|
---|
[27109] | 2197 | * Indicates that the page has been written to. */
|
---|
[59238] | 2198 | uint32_t u1Dirty : 1;
|
---|
[1] | 2199 | /** Page size flag - always 1 for 4MB entries. */
|
---|
[59238] | 2200 | uint32_t u1Size : 1;
|
---|
[1] | 2201 | /** Global flag. */
|
---|
[59238] | 2202 | uint32_t u1Global : 1;
|
---|
[1] | 2203 | /** Available for use to system software. */
|
---|
[59238] | 2204 | uint32_t u3Available : 3;
|
---|
[1] | 2205 | /** Reserved / If PAT enabled, bit 2 of the index. */
|
---|
[59238] | 2206 | uint32_t u1PAT : 1;
|
---|
[1] | 2207 | /** Bits 32-39 of the page number on AMD64.
|
---|
| 2208 | * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
|
---|
[59238] | 2209 | uint32_t u8PageNoHigh : 8;
|
---|
[1] | 2210 | /** Reserved. */
|
---|
[59238] | 2211 | uint32_t u1Reserved : 1;
|
---|
[1] | 2212 | /** Physical Page number of the page. */
|
---|
[59238] | 2213 | uint32_t u10PageNo : 10;
|
---|
[1] | 2214 | } X86PDE4MBITS;
|
---|
[59238] | 2215 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2216 | AssertCompileSize(X86PDE4MBITS, 4);
|
---|
| 2217 | #endif
|
---|
[1] | 2218 | /** Pointer to a page table entry. */
|
---|
| 2219 | typedef X86PDE4MBITS *PX86PDE4MBITS;
|
---|
| 2220 | /** Pointer to a const page table entry. */
|
---|
| 2221 | typedef const X86PDE4MBITS *PCX86PDE4MBITS;
|
---|
| 2222 |
|
---|
| 2223 |
|
---|
| 2224 | /**
|
---|
| 2225 | * 2MB PAE page directory entry.
|
---|
| 2226 | */
|
---|
| 2227 | typedef struct X86PDE2MPAEBITS
|
---|
| 2228 | {
|
---|
| 2229 | /** Flags whether(=1) or not the page is present. */
|
---|
| 2230 | uint32_t u1Present : 1;
|
---|
| 2231 | /** Read(=0) / Write(=1) flag. */
|
---|
| 2232 | uint32_t u1Write : 1;
|
---|
| 2233 | /** User(=1) / Supervisor(=0) flag. */
|
---|
| 2234 | uint32_t u1User : 1;
|
---|
| 2235 | /** Write Thru flag. If PAT enabled, bit 0 of the index. */
|
---|
| 2236 | uint32_t u1WriteThru : 1;
|
---|
| 2237 | /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
|
---|
| 2238 | uint32_t u1CacheDisable : 1;
|
---|
| 2239 | /** Accessed flag.
|
---|
| 2240 | * Indicates that the page have been read or written to. */
|
---|
| 2241 | uint32_t u1Accessed : 1;
|
---|
| 2242 | /** Dirty flag.
|
---|
[27109] | 2243 | * Indicates that the page has been written to. */
|
---|
[1] | 2244 | uint32_t u1Dirty : 1;
|
---|
| 2245 | /** Page size flag - always 1 for 2MB entries. */
|
---|
| 2246 | uint32_t u1Size : 1;
|
---|
| 2247 | /** Global flag. */
|
---|
| 2248 | uint32_t u1Global : 1;
|
---|
| 2249 | /** Available for use to system software. */
|
---|
| 2250 | uint32_t u3Available : 3;
|
---|
| 2251 | /** Reserved / If PAT enabled, bit 2 of the index. */
|
---|
| 2252 | uint32_t u1PAT : 1;
|
---|
| 2253 | /** Reserved. */
|
---|
| 2254 | uint32_t u9Reserved : 9;
|
---|
| 2255 | /** Physical Page number of the next level - Low part. Don't use! */
|
---|
| 2256 | uint32_t u10PageNoLow : 10;
|
---|
| 2257 | /** Physical Page number of the next level - High part. Don't use! */
|
---|
| 2258 | uint32_t u20PageNoHigh : 20;
|
---|
| 2259 | /** MBZ bits */
|
---|
| 2260 | uint32_t u11Reserved : 11;
|
---|
| 2261 | /** No Execute flag. */
|
---|
| 2262 | uint32_t u1NoExecute : 1;
|
---|
| 2263 | } X86PDE2MPAEBITS;
|
---|
[59238] | 2264 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2265 | AssertCompileSize(X86PDE2MPAEBITS, 8);
|
---|
| 2266 | #endif
|
---|
[24625] | 2267 | /** Pointer to a 2MB PAE page table entry. */
|
---|
[1] | 2268 | typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
|
---|
[24625] | 2269 | /** Pointer to a 2MB PAE page table entry. */
|
---|
[1] | 2270 | typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
|
---|
| 2271 |
|
---|
| 2272 | /** @} */
|
---|
| 2273 |
|
---|
| 2274 | /**
|
---|
| 2275 | * Page directory entry.
|
---|
| 2276 | */
|
---|
| 2277 | typedef union X86PDE
|
---|
| 2278 | {
|
---|
[14135] | 2279 | /** Unsigned integer view. */
|
---|
| 2280 | X86PGUINT u;
|
---|
[1] | 2281 | /** Normal view. */
|
---|
| 2282 | X86PDEBITS n;
|
---|
| 2283 | /** 4MB view (big). */
|
---|
| 2284 | X86PDE4MBITS b;
|
---|
| 2285 | /** 8 bit unsigned integer view. */
|
---|
| 2286 | uint8_t au8[4];
|
---|
| 2287 | /** 16 bit unsigned integer view. */
|
---|
| 2288 | uint16_t au16[2];
|
---|
| 2289 | /** 32 bit unsigned integer view. */
|
---|
| 2290 | uint32_t au32[1];
|
---|
| 2291 | } X86PDE;
|
---|
[59238] | 2292 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2293 | AssertCompileSize(X86PDE, 4);
|
---|
| 2294 | #endif
|
---|
[1] | 2295 | /** Pointer to a page directory entry. */
|
---|
| 2296 | typedef X86PDE *PX86PDE;
|
---|
| 2297 | /** Pointer to a const page directory entry. */
|
---|
| 2298 | typedef const X86PDE *PCX86PDE;
|
---|
| 2299 |
|
---|
| 2300 | /**
|
---|
| 2301 | * PAE page directory entry.
|
---|
| 2302 | */
|
---|
| 2303 | typedef union X86PDEPAE
|
---|
| 2304 | {
|
---|
[14135] | 2305 | /** Unsigned integer view. */
|
---|
| 2306 | X86PGPAEUINT u;
|
---|
[1] | 2307 | /** Normal view. */
|
---|
| 2308 | X86PDEPAEBITS n;
|
---|
| 2309 | /** 2MB page view (big). */
|
---|
| 2310 | X86PDE2MPAEBITS b;
|
---|
| 2311 | /** 8 bit unsigned integer view. */
|
---|
| 2312 | uint8_t au8[8];
|
---|
| 2313 | /** 16 bit unsigned integer view. */
|
---|
| 2314 | uint16_t au16[4];
|
---|
| 2315 | /** 32 bit unsigned integer view. */
|
---|
| 2316 | uint32_t au32[2];
|
---|
| 2317 | } X86PDEPAE;
|
---|
[59238] | 2318 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2319 | AssertCompileSize(X86PDEPAE, 8);
|
---|
| 2320 | #endif
|
---|
[1] | 2321 | /** Pointer to a page directory entry. */
|
---|
| 2322 | typedef X86PDEPAE *PX86PDEPAE;
|
---|
| 2323 | /** Pointer to a const page directory entry. */
|
---|
| 2324 | typedef const X86PDEPAE *PCX86PDEPAE;
|
---|
| 2325 |
|
---|
| 2326 | /**
|
---|
| 2327 | * Page directory.
|
---|
| 2328 | */
|
---|
| 2329 | typedef struct X86PD
|
---|
| 2330 | {
|
---|
| 2331 | /** PDE Array. */
|
---|
| 2332 | X86PDE a[X86_PG_ENTRIES];
|
---|
| 2333 | } X86PD;
|
---|
[59238] | 2334 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2335 | AssertCompileSize(X86PD, 4096);
|
---|
| 2336 | #endif
|
---|
[1] | 2337 | /** Pointer to a page directory. */
|
---|
| 2338 | typedef X86PD *PX86PD;
|
---|
| 2339 | /** Pointer to a const page directory. */
|
---|
| 2340 | typedef const X86PD *PCX86PD;
|
---|
| 2341 |
|
---|
| 2342 | /** The page shift to get the PD index. */
|
---|
| 2343 | #define X86_PD_SHIFT 22
|
---|
| 2344 | /** The PD index mask (apply to a shifted page address). */
|
---|
| 2345 | #define X86_PD_MASK 0x3ff
|
---|
| 2346 |
|
---|
| 2347 |
|
---|
| 2348 | /**
|
---|
| 2349 | * PAE page directory.
|
---|
| 2350 | */
|
---|
| 2351 | typedef struct X86PDPAE
|
---|
| 2352 | {
|
---|
| 2353 | /** PDE Array. */
|
---|
| 2354 | X86PDEPAE a[X86_PG_PAE_ENTRIES];
|
---|
| 2355 | } X86PDPAE;
|
---|
[59238] | 2356 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2357 | AssertCompileSize(X86PDPAE, 4096);
|
---|
| 2358 | #endif
|
---|
[1] | 2359 | /** Pointer to a PAE page directory. */
|
---|
| 2360 | typedef X86PDPAE *PX86PDPAE;
|
---|
| 2361 | /** Pointer to a const PAE page directory. */
|
---|
| 2362 | typedef const X86PDPAE *PCX86PDPAE;
|
---|
| 2363 |
|
---|
| 2364 | /** The page shift to get the PAE PD index. */
|
---|
| 2365 | #define X86_PD_PAE_SHIFT 21
|
---|
| 2366 | /** The PAE PD index mask (apply to a shifted page address). */
|
---|
| 2367 | #define X86_PD_PAE_MASK 0x1ff
|
---|
| 2368 |
|
---|
| 2369 |
|
---|
| 2370 | /** @name Page Directory Pointer Table Entry (PAE)
|
---|
| 2371 | * @{
|
---|
| 2372 | */
|
---|
| 2373 | /** Bit 0 - P - Present bit. */
|
---|
[59961] | 2374 | #define X86_PDPE_P RT_BIT_32(0)
|
---|
[1] | 2375 | /** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
|
---|
[59961] | 2376 | #define X86_PDPE_RW RT_BIT_32(1)
|
---|
[1] | 2377 | /** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
|
---|
[59961] | 2378 | #define X86_PDPE_US RT_BIT_32(2)
|
---|
[1] | 2379 | /** Bit 3 - PWT - Page level write thru bit. */
|
---|
[59961] | 2380 | #define X86_PDPE_PWT RT_BIT_32(3)
|
---|
[1] | 2381 | /** Bit 4 - PCD - Page level cache disable bit. */
|
---|
[59961] | 2382 | #define X86_PDPE_PCD RT_BIT_32(4)
|
---|
[1] | 2383 | /** Bit 5 - A - Access bit. Long Mode only. */
|
---|
[59961] | 2384 | #define X86_PDPE_A RT_BIT_32(5)
|
---|
[30889] | 2385 | /** Bit 7 - PS - Page size (1GB). Long Mode only. */
|
---|
[59961] | 2386 | #define X86_PDPE_LM_PS RT_BIT_32(7)
|
---|
[1] | 2387 | /** Bits 9-11 - - Available for use to system software. */
|
---|
[59961] | 2388 | #define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
|
---|
[1] | 2389 | /** Bits 12-51 - - PAE - Physical Page number of the next level. */
|
---|
[30889] | 2390 | #define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
|
---|
| 2391 | /** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
|
---|
| 2392 | #define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
|
---|
| 2393 | /** Bits 63 - NX - LM - No execution flag. Long Mode only. */
|
---|
| 2394 | #define X86_PDPE_LM_NX RT_BIT_64(63)
|
---|
| 2395 | /** Bits 8, 7 - - LM - MBZ bits when NX is active. */
|
---|
| 2396 | #define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
|
---|
| 2397 | /** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
|
---|
| 2398 | #define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
|
---|
| 2399 | /** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
|
---|
| 2400 | #define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
|
---|
| 2401 | /** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
|
---|
| 2402 | #define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
|
---|
[1] | 2403 |
|
---|
[30889] | 2404 |
|
---|
[1] | 2405 | /**
|
---|
| 2406 | * Page directory pointer table entry.
|
---|
| 2407 | */
|
---|
| 2408 | typedef struct X86PDPEBITS
|
---|
| 2409 | {
|
---|
| 2410 | /** Flags whether(=1) or not the page is present. */
|
---|
| 2411 | uint32_t u1Present : 1;
|
---|
[8536] | 2412 | /** Chunk of reserved bits. */
|
---|
| 2413 | uint32_t u2Reserved : 2;
|
---|
| 2414 | /** Write Thru flag. If PAT enabled, bit 0 of the index. */
|
---|
| 2415 | uint32_t u1WriteThru : 1;
|
---|
| 2416 | /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
|
---|
| 2417 | uint32_t u1CacheDisable : 1;
|
---|
| 2418 | /** Chunk of reserved bits. */
|
---|
| 2419 | uint32_t u4Reserved : 4;
|
---|
| 2420 | /** Available for use to system software. */
|
---|
| 2421 | uint32_t u3Available : 3;
|
---|
| 2422 | /** Physical Page number of the next level - Low Part. Don't use! */
|
---|
| 2423 | uint32_t u20PageNoLow : 20;
|
---|
| 2424 | /** Physical Page number of the next level - High Part. Don't use! */
|
---|
| 2425 | uint32_t u20PageNoHigh : 20;
|
---|
| 2426 | /** MBZ bits */
|
---|
| 2427 | uint32_t u12Reserved : 12;
|
---|
| 2428 | } X86PDPEBITS;
|
---|
[59238] | 2429 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2430 | AssertCompileSize(X86PDPEBITS, 8);
|
---|
| 2431 | #endif
|
---|
[8536] | 2432 | /** Pointer to a page directory pointer table entry. */
|
---|
| 2433 | typedef X86PDPEBITS *PX86PTPEBITS;
|
---|
| 2434 | /** Pointer to a const page directory pointer table entry. */
|
---|
| 2435 | typedef const X86PDPEBITS *PCX86PTPEBITS;
|
---|
| 2436 |
|
---|
| 2437 | /**
|
---|
| 2438 | * Page directory pointer table entry. AMD64 version
|
---|
| 2439 | */
|
---|
| 2440 | typedef struct X86PDPEAMD64BITS
|
---|
| 2441 | {
|
---|
| 2442 | /** Flags whether(=1) or not the page is present. */
|
---|
| 2443 | uint32_t u1Present : 1;
|
---|
[1] | 2444 | /** Read(=0) / Write(=1) flag. */
|
---|
| 2445 | uint32_t u1Write : 1;
|
---|
| 2446 | /** User(=1) / Supervisor (=0) flag. */
|
---|
| 2447 | uint32_t u1User : 1;
|
---|
| 2448 | /** Write Thru flag. If PAT enabled, bit 0 of the index. */
|
---|
| 2449 | uint32_t u1WriteThru : 1;
|
---|
| 2450 | /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
|
---|
| 2451 | uint32_t u1CacheDisable : 1;
|
---|
| 2452 | /** Accessed flag.
|
---|
| 2453 | * Indicates that the page have been read or written to. */
|
---|
| 2454 | uint32_t u1Accessed : 1;
|
---|
| 2455 | /** Chunk of reserved bits. */
|
---|
| 2456 | uint32_t u3Reserved : 3;
|
---|
| 2457 | /** Available for use to system software. */
|
---|
| 2458 | uint32_t u3Available : 3;
|
---|
| 2459 | /** Physical Page number of the next level - Low Part. Don't use! */
|
---|
| 2460 | uint32_t u20PageNoLow : 20;
|
---|
| 2461 | /** Physical Page number of the next level - High Part. Don't use! */
|
---|
| 2462 | uint32_t u20PageNoHigh : 20;
|
---|
| 2463 | /** MBZ bits */
|
---|
| 2464 | uint32_t u11Reserved : 11;
|
---|
| 2465 | /** No Execute flag. */
|
---|
| 2466 | uint32_t u1NoExecute : 1;
|
---|
[8536] | 2467 | } X86PDPEAMD64BITS;
|
---|
[59238] | 2468 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2469 | AssertCompileSize(X86PDPEAMD64BITS, 8);
|
---|
| 2470 | #endif
|
---|
[1] | 2471 | /** Pointer to a page directory pointer table entry. */
|
---|
[8536] | 2472 | typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
|
---|
[1] | 2473 | /** Pointer to a const page directory pointer table entry. */
|
---|
[35493] | 2474 | typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
|
---|
[1] | 2475 |
|
---|
| 2476 | /**
|
---|
[60228] | 2477 | * Page directory pointer table entry for 1GB page. (AMD64 only)
|
---|
| 2478 | */
|
---|
| 2479 | typedef struct X86PDPE1GB
|
---|
| 2480 | {
|
---|
| 2481 | /** 0: Flags whether(=1) or not the page is present. */
|
---|
| 2482 | uint32_t u1Present : 1;
|
---|
| 2483 | /** 1: Read(=0) / Write(=1) flag. */
|
---|
| 2484 | uint32_t u1Write : 1;
|
---|
| 2485 | /** 2: User(=1) / Supervisor (=0) flag. */
|
---|
| 2486 | uint32_t u1User : 1;
|
---|
| 2487 | /** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
|
---|
| 2488 | uint32_t u1WriteThru : 1;
|
---|
| 2489 | /** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
|
---|
| 2490 | uint32_t u1CacheDisable : 1;
|
---|
| 2491 | /** 5: Accessed flag.
|
---|
| 2492 | * Indicates that the page have been read or written to. */
|
---|
| 2493 | uint32_t u1Accessed : 1;
|
---|
| 2494 | /** 6: Dirty flag for 1GB pages. */
|
---|
| 2495 | uint32_t u1Dirty : 1;
|
---|
| 2496 | /** 7: Indicates 1GB page if set. */
|
---|
| 2497 | uint32_t u1Size : 1;
|
---|
| 2498 | /** 8: Global 1GB page. */
|
---|
| 2499 | uint32_t u1Global: 1;
|
---|
| 2500 | /** 9-11: Available for use to system software. */
|
---|
| 2501 | uint32_t u3Available : 3;
|
---|
| 2502 | /** 12: PAT bit for 1GB page. */
|
---|
| 2503 | uint32_t u1PAT : 1;
|
---|
| 2504 | /** 13-29: MBZ bits. */
|
---|
| 2505 | uint32_t u17Reserved : 17;
|
---|
| 2506 | /** 30-31: Physical page number - Low Part. Don't use! */
|
---|
| 2507 | uint32_t u2PageNoLow : 2;
|
---|
| 2508 | /** 32-51: Physical Page number of the next level - High Part. Don't use! */
|
---|
| 2509 | uint32_t u20PageNoHigh : 20;
|
---|
| 2510 | /** 52-62: MBZ bits */
|
---|
| 2511 | uint32_t u11Reserved : 11;
|
---|
| 2512 | /** 63: No Execute flag. */
|
---|
| 2513 | uint32_t u1NoExecute : 1;
|
---|
| 2514 | } X86PDPE1GB;
|
---|
| 2515 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2516 | AssertCompileSize(X86PDPE1GB, 8);
|
---|
| 2517 | #endif
|
---|
| 2518 | /** Pointer to a page directory pointer table entry for a 1GB page. */
|
---|
| 2519 | typedef X86PDPE1GB *PX86PDPE1GB;
|
---|
| 2520 | /** Pointer to a const page directory pointer table entry for a 1GB page. */
|
---|
| 2521 | typedef const X86PDPE1GB *PCX86PDPE1GB;
|
---|
| 2522 |
|
---|
| 2523 | /**
|
---|
[1] | 2524 | * Page directory pointer table entry.
|
---|
| 2525 | */
|
---|
| 2526 | typedef union X86PDPE
|
---|
| 2527 | {
|
---|
[14135] | 2528 | /** Unsigned integer view. */
|
---|
| 2529 | X86PGPAEUINT u;
|
---|
[1] | 2530 | /** Normal view. */
|
---|
| 2531 | X86PDPEBITS n;
|
---|
[8536] | 2532 | /** AMD64 view. */
|
---|
| 2533 | X86PDPEAMD64BITS lm;
|
---|
[60228] | 2534 | /** AMD64 big view. */
|
---|
| 2535 | X86PDPE1GB b;
|
---|
[1] | 2536 | /** 8 bit unsigned integer view. */
|
---|
| 2537 | uint8_t au8[8];
|
---|
| 2538 | /** 16 bit unsigned integer view. */
|
---|
| 2539 | uint16_t au16[4];
|
---|
| 2540 | /** 32 bit unsigned integer view. */
|
---|
| 2541 | uint32_t au32[2];
|
---|
| 2542 | } X86PDPE;
|
---|
[59238] | 2543 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2544 | AssertCompileSize(X86PDPE, 8);
|
---|
| 2545 | #endif
|
---|
[1] | 2546 | /** Pointer to a page directory pointer table entry. */
|
---|
| 2547 | typedef X86PDPE *PX86PDPE;
|
---|
| 2548 | /** Pointer to a const page directory pointer table entry. */
|
---|
| 2549 | typedef const X86PDPE *PCX86PDPE;
|
---|
| 2550 |
|
---|
| 2551 |
|
---|
| 2552 | /**
|
---|
| 2553 | * Page directory pointer table.
|
---|
| 2554 | */
|
---|
[7715] | 2555 | typedef struct X86PDPT
|
---|
[1] | 2556 | {
|
---|
| 2557 | /** PDE Array. */
|
---|
[7677] | 2558 | X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
|
---|
[7715] | 2559 | } X86PDPT;
|
---|
[59238] | 2560 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2561 | AssertCompileSize(X86PDPT, 4096);
|
---|
| 2562 | #endif
|
---|
[1] | 2563 | /** Pointer to a page directory pointer table. */
|
---|
[7715] | 2564 | typedef X86PDPT *PX86PDPT;
|
---|
[1] | 2565 | /** Pointer to a const page directory pointer table. */
|
---|
[7715] | 2566 | typedef const X86PDPT *PCX86PDPT;
|
---|
[1] | 2567 |
|
---|
[7715] | 2568 | /** The page shift to get the PDPT index. */
|
---|
| 2569 | #define X86_PDPT_SHIFT 30
|
---|
| 2570 | /** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
|
---|
[7728] | 2571 | #define X86_PDPT_MASK_PAE 0x3
|
---|
[7715] | 2572 | /** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
|
---|
[7728] | 2573 | #define X86_PDPT_MASK_AMD64 0x1ff
|
---|
[1] | 2574 |
|
---|
| 2575 | /** @} */
|
---|
| 2576 |
|
---|
| 2577 |
|
---|
| 2578 | /** @name Page Map Level-4 Entry (Long Mode PAE)
|
---|
| 2579 | * @{
|
---|
| 2580 | */
|
---|
| 2581 | /** Bit 0 - P - Present bit. */
|
---|
[59961] | 2582 | #define X86_PML4E_P RT_BIT_32(0)
|
---|
[1] | 2583 | /** Bit 1 - R/W - Read (clear) / Write (set) bit. */
|
---|
[59961] | 2584 | #define X86_PML4E_RW RT_BIT_32(1)
|
---|
[1] | 2585 | /** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
|
---|
[59961] | 2586 | #define X86_PML4E_US RT_BIT_32(2)
|
---|
[1] | 2587 | /** Bit 3 - PWT - Page level write thru bit. */
|
---|
[59961] | 2588 | #define X86_PML4E_PWT RT_BIT_32(3)
|
---|
[1] | 2589 | /** Bit 4 - PCD - Page level cache disable bit. */
|
---|
[59961] | 2590 | #define X86_PML4E_PCD RT_BIT_32(4)
|
---|
[1] | 2591 | /** Bit 5 - A - Access bit. */
|
---|
[59961] | 2592 | #define X86_PML4E_A RT_BIT_32(5)
|
---|
[1] | 2593 | /** Bits 9-11 - - Available for use to system software. */
|
---|
[59961] | 2594 | #define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
|
---|
[1] | 2595 | /** Bits 12-51 - - PAE - Physical Page number of the next level. */
|
---|
[32000] | 2596 | #define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
|
---|
[30889] | 2597 | /** Bits 8, 7 - - MBZ bits when NX is active. */
|
---|
| 2598 | #define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
|
---|
| 2599 | /** Bits 63, 7 - - MBZ bits when no NX. */
|
---|
| 2600 | #define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
|
---|
[1] | 2601 | /** Bits 63 - NX - PAE - No execution flag. */
|
---|
[5605] | 2602 | #define X86_PML4E_NX RT_BIT_64(63)
|
---|
[1] | 2603 |
|
---|
| 2604 | /**
|
---|
| 2605 | * Page Map Level-4 Entry
|
---|
| 2606 | */
|
---|
| 2607 | typedef struct X86PML4EBITS
|
---|
| 2608 | {
|
---|
| 2609 | /** Flags whether(=1) or not the page is present. */
|
---|
| 2610 | uint32_t u1Present : 1;
|
---|
| 2611 | /** Read(=0) / Write(=1) flag. */
|
---|
| 2612 | uint32_t u1Write : 1;
|
---|
| 2613 | /** User(=1) / Supervisor (=0) flag. */
|
---|
| 2614 | uint32_t u1User : 1;
|
---|
| 2615 | /** Write Thru flag. If PAT enabled, bit 0 of the index. */
|
---|
| 2616 | uint32_t u1WriteThru : 1;
|
---|
| 2617 | /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
|
---|
| 2618 | uint32_t u1CacheDisable : 1;
|
---|
| 2619 | /** Accessed flag.
|
---|
| 2620 | * Indicates that the page have been read or written to. */
|
---|
| 2621 | uint32_t u1Accessed : 1;
|
---|
| 2622 | /** Chunk of reserved bits. */
|
---|
| 2623 | uint32_t u3Reserved : 3;
|
---|
| 2624 | /** Available for use to system software. */
|
---|
| 2625 | uint32_t u3Available : 3;
|
---|
| 2626 | /** Physical Page number of the next level - Low Part. Don't use! */
|
---|
| 2627 | uint32_t u20PageNoLow : 20;
|
---|
| 2628 | /** Physical Page number of the next level - High Part. Don't use! */
|
---|
| 2629 | uint32_t u20PageNoHigh : 20;
|
---|
| 2630 | /** MBZ bits */
|
---|
| 2631 | uint32_t u11Reserved : 11;
|
---|
| 2632 | /** No Execute flag. */
|
---|
| 2633 | uint32_t u1NoExecute : 1;
|
---|
| 2634 | } X86PML4EBITS;
|
---|
[59238] | 2635 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2636 | AssertCompileSize(X86PML4EBITS, 8);
|
---|
| 2637 | #endif
|
---|
[1] | 2638 | /** Pointer to a page map level-4 entry. */
|
---|
| 2639 | typedef X86PML4EBITS *PX86PML4EBITS;
|
---|
| 2640 | /** Pointer to a const page map level-4 entry. */
|
---|
| 2641 | typedef const X86PML4EBITS *PCX86PML4EBITS;
|
---|
| 2642 |
|
---|
| 2643 | /**
|
---|
| 2644 | * Page Map Level-4 Entry.
|
---|
| 2645 | */
|
---|
| 2646 | typedef union X86PML4E
|
---|
| 2647 | {
|
---|
[14135] | 2648 | /** Unsigned integer view. */
|
---|
| 2649 | X86PGPAEUINT u;
|
---|
[1] | 2650 | /** Normal view. */
|
---|
| 2651 | X86PML4EBITS n;
|
---|
| 2652 | /** 8 bit unsigned integer view. */
|
---|
| 2653 | uint8_t au8[8];
|
---|
| 2654 | /** 16 bit unsigned integer view. */
|
---|
| 2655 | uint16_t au16[4];
|
---|
| 2656 | /** 32 bit unsigned integer view. */
|
---|
| 2657 | uint32_t au32[2];
|
---|
| 2658 | } X86PML4E;
|
---|
[59238] | 2659 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2660 | AssertCompileSize(X86PML4E, 8);
|
---|
| 2661 | #endif
|
---|
[1] | 2662 | /** Pointer to a page map level-4 entry. */
|
---|
| 2663 | typedef X86PML4E *PX86PML4E;
|
---|
| 2664 | /** Pointer to a const page map level-4 entry. */
|
---|
| 2665 | typedef const X86PML4E *PCX86PML4E;
|
---|
| 2666 |
|
---|
| 2667 |
|
---|
| 2668 | /**
|
---|
| 2669 | * Page Map Level-4.
|
---|
| 2670 | */
|
---|
| 2671 | typedef struct X86PML4
|
---|
| 2672 | {
|
---|
| 2673 | /** PDE Array. */
|
---|
| 2674 | X86PML4E a[X86_PG_PAE_ENTRIES];
|
---|
| 2675 | } X86PML4;
|
---|
[59238] | 2676 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2677 | AssertCompileSize(X86PML4, 4096);
|
---|
| 2678 | #endif
|
---|
[1] | 2679 | /** Pointer to a page map level-4. */
|
---|
| 2680 | typedef X86PML4 *PX86PML4;
|
---|
| 2681 | /** Pointer to a const page map level-4. */
|
---|
| 2682 | typedef const X86PML4 *PCX86PML4;
|
---|
| 2683 |
|
---|
| 2684 | /** The page shift to get the PML4 index. */
|
---|
[9614] | 2685 | #define X86_PML4_SHIFT 39
|
---|
[1] | 2686 | /** The PML4 index mask (apply to a shifted page address). */
|
---|
| 2687 | #define X86_PML4_MASK 0x1ff
|
---|
| 2688 |
|
---|
| 2689 | /** @} */
|
---|
| 2690 |
|
---|
| 2691 | /** @} */
|
---|
| 2692 |
|
---|
[49731] | 2693 | /**
|
---|
[70612] | 2694 | * Intel PCID invalidation types.
|
---|
| 2695 | */
|
---|
| 2696 | /** Individual address invalidation. */
|
---|
| 2697 | #define X86_INVPCID_TYPE_INDV_ADDR 0
|
---|
| 2698 | /** Single-context invalidation. */
|
---|
| 2699 | #define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
|
---|
| 2700 | /** All-context including globals invalidation. */
|
---|
| 2701 | #define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
|
---|
| 2702 | /** All-context excluding globals invalidation. */
|
---|
| 2703 | #define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
|
---|
| 2704 | /** The maximum valid invalidation type value. */
|
---|
| 2705 | #define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
|
---|
| 2706 |
|
---|
| 2707 | /**
|
---|
[49731] | 2708 | * 32-bit protected mode FSTENV image.
|
---|
| 2709 | */
|
---|
| 2710 | typedef struct X86FSTENV32P
|
---|
| 2711 | {
|
---|
| 2712 | uint16_t FCW;
|
---|
| 2713 | uint16_t padding1;
|
---|
| 2714 | uint16_t FSW;
|
---|
| 2715 | uint16_t padding2;
|
---|
| 2716 | uint16_t FTW;
|
---|
| 2717 | uint16_t padding3;
|
---|
| 2718 | uint32_t FPUIP;
|
---|
| 2719 | uint16_t FPUCS;
|
---|
| 2720 | uint16_t FOP;
|
---|
| 2721 | uint32_t FPUDP;
|
---|
| 2722 | uint16_t FPUDS;
|
---|
| 2723 | uint16_t padding4;
|
---|
| 2724 | } X86FSTENV32P;
|
---|
| 2725 | /** Pointer to a 32-bit protected mode FSTENV image. */
|
---|
| 2726 | typedef X86FSTENV32P *PX86FSTENV32P;
|
---|
| 2727 | /** Pointer to a const 32-bit protected mode FSTENV image. */
|
---|
| 2728 | typedef X86FSTENV32P const *PCX86FSTENV32P;
|
---|
[1] | 2729 |
|
---|
[49731] | 2730 |
|
---|
[1] | 2731 | /**
|
---|
| 2732 | * 80-bit MMX/FPU register type.
|
---|
| 2733 | */
|
---|
| 2734 | typedef struct X86FPUMMX
|
---|
| 2735 | {
|
---|
| 2736 | uint8_t reg[10];
|
---|
| 2737 | } X86FPUMMX;
|
---|
[54896] | 2738 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2739 | AssertCompileSize(X86FPUMMX, 10);
|
---|
| 2740 | #endif
|
---|
[1] | 2741 | /** Pointer to a 80-bit MMX/FPU register type. */
|
---|
| 2742 | typedef X86FPUMMX *PX86FPUMMX;
|
---|
| 2743 | /** Pointer to a const 80-bit MMX/FPU register type. */
|
---|
| 2744 | typedef const X86FPUMMX *PCX86FPUMMX;
|
---|
| 2745 |
|
---|
[54896] | 2746 | /** FPU (x87) register. */
|
---|
| 2747 | typedef union X86FPUREG
|
---|
| 2748 | {
|
---|
| 2749 | /** MMX view. */
|
---|
| 2750 | uint64_t mmx;
|
---|
| 2751 | /** FPU view - todo. */
|
---|
| 2752 | X86FPUMMX fpu;
|
---|
| 2753 | /** Extended precision floating point view. */
|
---|
| 2754 | RTFLOAT80U r80;
|
---|
| 2755 | /** Extended precision floating point view v2 */
|
---|
| 2756 | RTFLOAT80U2 r80Ex;
|
---|
| 2757 | /** 8-bit view. */
|
---|
| 2758 | uint8_t au8[16];
|
---|
| 2759 | /** 16-bit view. */
|
---|
| 2760 | uint16_t au16[8];
|
---|
| 2761 | /** 32-bit view. */
|
---|
| 2762 | uint32_t au32[4];
|
---|
| 2763 | /** 64-bit view. */
|
---|
| 2764 | uint64_t au64[2];
|
---|
| 2765 | /** 128-bit view. (yeah, very helpful) */
|
---|
| 2766 | uint128_t au128[1];
|
---|
| 2767 | } X86FPUREG;
|
---|
| 2768 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2769 | AssertCompileSize(X86FPUREG, 16);
|
---|
| 2770 | #endif
|
---|
| 2771 | /** Pointer to a FPU register. */
|
---|
| 2772 | typedef X86FPUREG *PX86FPUREG;
|
---|
| 2773 | /** Pointer to a const FPU register. */
|
---|
| 2774 | typedef X86FPUREG const *PCX86FPUREG;
|
---|
| 2775 |
|
---|
[1] | 2776 | /**
|
---|
[54896] | 2777 | * XMM register union.
|
---|
| 2778 | */
|
---|
| 2779 | typedef union X86XMMREG
|
---|
| 2780 | {
|
---|
[66314] | 2781 | /** XMM Register view. */
|
---|
[54896] | 2782 | uint128_t xmm;
|
---|
| 2783 | /** 8-bit view. */
|
---|
| 2784 | uint8_t au8[16];
|
---|
| 2785 | /** 16-bit view. */
|
---|
| 2786 | uint16_t au16[8];
|
---|
| 2787 | /** 32-bit view. */
|
---|
| 2788 | uint32_t au32[4];
|
---|
| 2789 | /** 64-bit view. */
|
---|
| 2790 | uint64_t au64[2];
|
---|
| 2791 | /** 128-bit view. (yeah, very helpful) */
|
---|
| 2792 | uint128_t au128[1];
|
---|
[74241] | 2793 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
[66314] | 2794 | /** Confusing nested 128-bit union view (this is what xmm should've been). */
|
---|
| 2795 | RTUINT128U uXmm;
|
---|
[74241] | 2796 | #endif
|
---|
[54896] | 2797 | } X86XMMREG;
|
---|
| 2798 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2799 | AssertCompileSize(X86XMMREG, 16);
|
---|
| 2800 | #endif
|
---|
| 2801 | /** Pointer to an XMM register state. */
|
---|
| 2802 | typedef X86XMMREG *PX86XMMREG;
|
---|
| 2803 | /** Pointer to a const XMM register state. */
|
---|
| 2804 | typedef X86XMMREG const *PCX86XMMREG;
|
---|
| 2805 |
|
---|
| 2806 | /**
|
---|
| 2807 | * YMM register union.
|
---|
| 2808 | */
|
---|
| 2809 | typedef union X86YMMREG
|
---|
| 2810 | {
|
---|
| 2811 | /** 8-bit view. */
|
---|
| 2812 | uint8_t au8[32];
|
---|
| 2813 | /** 16-bit view. */
|
---|
| 2814 | uint16_t au16[16];
|
---|
| 2815 | /** 32-bit view. */
|
---|
| 2816 | uint32_t au32[8];
|
---|
| 2817 | /** 64-bit view. */
|
---|
| 2818 | uint64_t au64[4];
|
---|
| 2819 | /** 128-bit view. (yeah, very helpful) */
|
---|
| 2820 | uint128_t au128[2];
|
---|
| 2821 | /** XMM sub register view. */
|
---|
| 2822 | X86XMMREG aXmm[2];
|
---|
| 2823 | } X86YMMREG;
|
---|
| 2824 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2825 | AssertCompileSize(X86YMMREG, 32);
|
---|
| 2826 | #endif
|
---|
| 2827 | /** Pointer to an YMM register state. */
|
---|
| 2828 | typedef X86YMMREG *PX86YMMREG;
|
---|
| 2829 | /** Pointer to a const YMM register state. */
|
---|
| 2830 | typedef X86YMMREG const *PCX86YMMREG;
|
---|
| 2831 |
|
---|
| 2832 | /**
|
---|
| 2833 | * ZMM register union.
|
---|
| 2834 | */
|
---|
| 2835 | typedef union X86ZMMREG
|
---|
| 2836 | {
|
---|
| 2837 | /** 8-bit view. */
|
---|
| 2838 | uint8_t au8[64];
|
---|
| 2839 | /** 16-bit view. */
|
---|
| 2840 | uint16_t au16[32];
|
---|
| 2841 | /** 32-bit view. */
|
---|
| 2842 | uint32_t au32[16];
|
---|
| 2843 | /** 64-bit view. */
|
---|
| 2844 | uint64_t au64[8];
|
---|
| 2845 | /** 128-bit view. (yeah, very helpful) */
|
---|
| 2846 | uint128_t au128[4];
|
---|
| 2847 | /** XMM sub register view. */
|
---|
| 2848 | X86XMMREG aXmm[4];
|
---|
| 2849 | /** YMM sub register view. */
|
---|
| 2850 | X86YMMREG aYmm[2];
|
---|
| 2851 | } X86ZMMREG;
|
---|
| 2852 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 2853 | AssertCompileSize(X86ZMMREG, 64);
|
---|
| 2854 | #endif
|
---|
| 2855 | /** Pointer to an ZMM register state. */
|
---|
| 2856 | typedef X86ZMMREG *PX86ZMMREG;
|
---|
| 2857 | /** Pointer to a const ZMM register state. */
|
---|
| 2858 | typedef X86ZMMREG const *PCX86ZMMREG;
|
---|
| 2859 |
|
---|
| 2860 |
|
---|
| 2861 | /**
|
---|
[36849] | 2862 | * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
|
---|
| 2863 | * @todo verify this...
|
---|
[1] | 2864 | */
|
---|
| 2865 | #pragma pack(1)
|
---|
| 2866 | typedef struct X86FPUSTATE
|
---|
| 2867 | {
|
---|
[36849] | 2868 | /** 0x00 - Control word. */
|
---|
[1] | 2869 | uint16_t FCW;
|
---|
[36849] | 2870 | /** 0x02 - Alignment word */
|
---|
[1] | 2871 | uint16_t Dummy1;
|
---|
[36849] | 2872 | /** 0x04 - Status word. */
|
---|
[1] | 2873 | uint16_t FSW;
|
---|
[36849] | 2874 | /** 0x06 - Alignment word */
|
---|
[1] | 2875 | uint16_t Dummy2;
|
---|
[36849] | 2876 | /** 0x08 - Tag word */
|
---|
[1] | 2877 | uint16_t FTW;
|
---|
[36849] | 2878 | /** 0x0a - Alignment word */
|
---|
[1] | 2879 | uint16_t Dummy3;
|
---|
| 2880 |
|
---|
[36849] | 2881 | /** 0x0c - Instruction pointer. */
|
---|
[1] | 2882 | uint32_t FPUIP;
|
---|
[36849] | 2883 | /** 0x10 - Code selector. */
|
---|
[1] | 2884 | uint16_t CS;
|
---|
[36849] | 2885 | /** 0x12 - Opcode. */
|
---|
[1] | 2886 | uint16_t FOP;
|
---|
[36849] | 2887 | /** 0x14 - FOO. */
|
---|
[1] | 2888 | uint32_t FPUOO;
|
---|
[36849] | 2889 | /** 0x18 - FOS. */
|
---|
[1] | 2890 | uint32_t FPUOS;
|
---|
[54896] | 2891 | /** 0x1c - FPU register. */
|
---|
| 2892 | X86FPUREG regs[8];
|
---|
[1] | 2893 | } X86FPUSTATE;
|
---|
| 2894 | #pragma pack()
|
---|
| 2895 | /** Pointer to a FPU state. */
|
---|
| 2896 | typedef X86FPUSTATE *PX86FPUSTATE;
|
---|
| 2897 | /** Pointer to a const FPU state. */
|
---|
| 2898 | typedef const X86FPUSTATE *PCX86FPUSTATE;
|
---|
| 2899 |
|
---|
| 2900 | /**
|
---|
| 2901 | * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
|
---|
| 2902 | */
|
---|
| 2903 | #pragma pack(1)
|
---|
| 2904 | typedef struct X86FXSTATE
|
---|
| 2905 | {
|
---|
[36849] | 2906 | /** 0x00 - Control word. */
|
---|
[1] | 2907 | uint16_t FCW;
|
---|
[36849] | 2908 | /** 0x02 - Status word. */
|
---|
[1] | 2909 | uint16_t FSW;
|
---|
[36849] | 2910 | /** 0x04 - Tag word. (The upper byte is always zero.) */
|
---|
[24848] | 2911 | uint16_t FTW;
|
---|
[36849] | 2912 | /** 0x06 - Opcode. */
|
---|
[1] | 2913 | uint16_t FOP;
|
---|
[36849] | 2914 | /** 0x08 - Instruction pointer. */
|
---|
[1] | 2915 | uint32_t FPUIP;
|
---|
[36849] | 2916 | /** 0x0c - Code selector. */
|
---|
[1] | 2917 | uint16_t CS;
|
---|
[36857] | 2918 | uint16_t Rsrvd1;
|
---|
[36849] | 2919 | /** 0x10 - Data pointer. */
|
---|
[1] | 2920 | uint32_t FPUDP;
|
---|
[36849] | 2921 | /** 0x14 - Data segment */
|
---|
[1] | 2922 | uint16_t DS;
|
---|
[36849] | 2923 | /** 0x16 */
|
---|
[1] | 2924 | uint16_t Rsrvd2;
|
---|
[36849] | 2925 | /** 0x18 */
|
---|
[1] | 2926 | uint32_t MXCSR;
|
---|
[36849] | 2927 | /** 0x1c */
|
---|
[1] | 2928 | uint32_t MXCSR_MASK;
|
---|
[54896] | 2929 | /** 0x20 - FPU registers. */
|
---|
| 2930 | X86FPUREG aRegs[8];
|
---|
| 2931 | /** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
|
---|
| 2932 | X86XMMREG aXMM[16];
|
---|
[7095] | 2933 | /* - offset 416 - */
|
---|
[52465] | 2934 | uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
|
---|
| 2935 | /* - offset 464 - Software usable reserved bits. */
|
---|
| 2936 | uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
|
---|
[1] | 2937 | } X86FXSTATE;
|
---|
| 2938 | #pragma pack()
|
---|
| 2939 | /** Pointer to a FPU Extended state. */
|
---|
| 2940 | typedef X86FXSTATE *PX86FXSTATE;
|
---|
| 2941 | /** Pointer to a const FPU Extended state. */
|
---|
| 2942 | typedef const X86FXSTATE *PCX86FXSTATE;
|
---|
| 2943 |
|
---|
[52465] | 2944 | /** Offset for software usable reserved bits (464:511) where we store a 32-bit
|
---|
| 2945 | * magic. Don't forget to update x86.mac if you change this! */
|
---|
| 2946 | #define X86_OFF_FXSTATE_RSVD 0x1d0
|
---|
| 2947 | /** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
|
---|
[55048] | 2948 | * forget to update x86.mac if you change this!
|
---|
| 2949 | * @todo r=bird: This has nothing what-so-ever to do here.... */
|
---|
[52465] | 2950 | #define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
|
---|
[53630] | 2951 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
[52465] | 2952 | AssertCompileSize(X86FXSTATE, 512);
|
---|
[52466] | 2953 | AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
|
---|
[53630] | 2954 | #endif
|
---|
[52465] | 2955 |
|
---|
[36849] | 2956 | /** @name FPU status word flags.
|
---|
| 2957 | * @{ */
|
---|
| 2958 | /** Exception Flag: Invalid operation. */
|
---|
[59961] | 2959 | #define X86_FSW_IE RT_BIT_32(0)
|
---|
[36849] | 2960 | /** Exception Flag: Denormalized operand. */
|
---|
[59961] | 2961 | #define X86_FSW_DE RT_BIT_32(1)
|
---|
[36849] | 2962 | /** Exception Flag: Zero divide. */
|
---|
[59961] | 2963 | #define X86_FSW_ZE RT_BIT_32(2)
|
---|
[36849] | 2964 | /** Exception Flag: Overflow. */
|
---|
[59961] | 2965 | #define X86_FSW_OE RT_BIT_32(3)
|
---|
[36849] | 2966 | /** Exception Flag: Underflow. */
|
---|
[59961] | 2967 | #define X86_FSW_UE RT_BIT_32(4)
|
---|
[36849] | 2968 | /** Exception Flag: Precision. */
|
---|
[59961] | 2969 | #define X86_FSW_PE RT_BIT_32(5)
|
---|
[36849] | 2970 | /** Stack fault. */
|
---|
[59961] | 2971 | #define X86_FSW_SF RT_BIT_32(6)
|
---|
[36849] | 2972 | /** Error summary status. */
|
---|
[59961] | 2973 | #define X86_FSW_ES RT_BIT_32(7)
|
---|
[40144] | 2974 | /** Mask of exceptions flags, excluding the summary bit. */
|
---|
| 2975 | #define X86_FSW_XCPT_MASK UINT16_C(0x007f)
|
---|
| 2976 | /** Mask of exceptions flags, including the summary bit. */
|
---|
| 2977 | #define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
|
---|
[36849] | 2978 | /** Condition code 0. */
|
---|
[59961] | 2979 | #define X86_FSW_C0 RT_BIT_32(8)
|
---|
[36849] | 2980 | /** Condition code 1. */
|
---|
[59961] | 2981 | #define X86_FSW_C1 RT_BIT_32(9)
|
---|
[36849] | 2982 | /** Condition code 2. */
|
---|
[59961] | 2983 | #define X86_FSW_C2 RT_BIT_32(10)
|
---|
[36849] | 2984 | /** Top of the stack mask. */
|
---|
| 2985 | #define X86_FSW_TOP_MASK UINT16_C(0x3800)
|
---|
| 2986 | /** TOP shift value. */
|
---|
| 2987 | #define X86_FSW_TOP_SHIFT 11
|
---|
| 2988 | /** Mask for getting TOP value after shifting it right. */
|
---|
| 2989 | #define X86_FSW_TOP_SMASK UINT16_C(0x0007)
|
---|
| 2990 | /** Get the TOP value. */
|
---|
| 2991 | #define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
|
---|
| 2992 | /** Condition code 3. */
|
---|
[59961] | 2993 | #define X86_FSW_C3 RT_BIT_32(14)
|
---|
[40144] | 2994 | /** Mask of exceptions flags, including the summary bit. */
|
---|
| 2995 | #define X86_FSW_C_MASK UINT16_C(0x4700)
|
---|
[36849] | 2996 | /** FPU busy. */
|
---|
[59961] | 2997 | #define X86_FSW_B RT_BIT_32(15)
|
---|
[36849] | 2998 | /** @} */
|
---|
[1] | 2999 |
|
---|
[36849] | 3000 |
|
---|
[40069] | 3001 | /** @name FPU control word flags.
|
---|
| 3002 | * @{ */
|
---|
| 3003 | /** Exception Mask: Invalid operation. */
|
---|
[59961] | 3004 | #define X86_FCW_IM RT_BIT_32(0)
|
---|
[40069] | 3005 | /** Exception Mask: Denormalized operand. */
|
---|
[59961] | 3006 | #define X86_FCW_DM RT_BIT_32(1)
|
---|
[40069] | 3007 | /** Exception Mask: Zero divide. */
|
---|
[59961] | 3008 | #define X86_FCW_ZM RT_BIT_32(2)
|
---|
[40069] | 3009 | /** Exception Mask: Overflow. */
|
---|
[59961] | 3010 | #define X86_FCW_OM RT_BIT_32(3)
|
---|
[40069] | 3011 | /** Exception Mask: Underflow. */
|
---|
[59961] | 3012 | #define X86_FCW_UM RT_BIT_32(4)
|
---|
[40069] | 3013 | /** Exception Mask: Precision. */
|
---|
[59961] | 3014 | #define X86_FCW_PM RT_BIT_32(5)
|
---|
[40222] | 3015 | /** Mask all exceptions, the value typically loaded (by for instance fninit).
|
---|
| 3016 | * @remarks This includes reserved bit 6. */
|
---|
[40076] | 3017 | #define X86_FCW_MASK_ALL UINT16_C(0x007f)
|
---|
[40222] | 3018 | /** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
|
---|
| 3019 | #define X86_FCW_XCPT_MASK UINT16_C(0x003f)
|
---|
[40069] | 3020 | /** Precision control mask. */
|
---|
| 3021 | #define X86_FCW_PC_MASK UINT16_C(0x0300)
|
---|
| 3022 | /** Precision control: 24-bit. */
|
---|
| 3023 | #define X86_FCW_PC_24 UINT16_C(0x0000)
|
---|
| 3024 | /** Precision control: Reserved. */
|
---|
| 3025 | #define X86_FCW_PC_RSVD UINT16_C(0x0100)
|
---|
| 3026 | /** Precision control: 53-bit. */
|
---|
| 3027 | #define X86_FCW_PC_53 UINT16_C(0x0200)
|
---|
| 3028 | /** Precision control: 64-bit. */
|
---|
| 3029 | #define X86_FCW_PC_64 UINT16_C(0x0300)
|
---|
| 3030 | /** Rounding control mask. */
|
---|
| 3031 | #define X86_FCW_RC_MASK UINT16_C(0x0c00)
|
---|
| 3032 | /** Rounding control: To nearest. */
|
---|
| 3033 | #define X86_FCW_RC_NEAREST UINT16_C(0x0000)
|
---|
| 3034 | /** Rounding control: Down. */
|
---|
| 3035 | #define X86_FCW_RC_DOWN UINT16_C(0x0400)
|
---|
| 3036 | /** Rounding control: Up. */
|
---|
| 3037 | #define X86_FCW_RC_UP UINT16_C(0x0800)
|
---|
| 3038 | /** Rounding control: Towards zero. */
|
---|
| 3039 | #define X86_FCW_RC_ZERO UINT16_C(0x0c00)
|
---|
[40222] | 3040 | /** Bits which should be zero, apparently. */
|
---|
| 3041 | #define X86_FCW_ZERO_MASK UINT16_C(0xf080)
|
---|
[40069] | 3042 | /** @} */
|
---|
| 3043 |
|
---|
[47406] | 3044 | /** @name SSE MXCSR
|
---|
| 3045 | * @{ */
|
---|
| 3046 | /** Exception Flag: Invalid operation. */
|
---|
[66392] | 3047 | #define X86_MXCSR_IE RT_BIT_32(0)
|
---|
[47406] | 3048 | /** Exception Flag: Denormalized operand. */
|
---|
[66392] | 3049 | #define X86_MXCSR_DE RT_BIT_32(1)
|
---|
[47406] | 3050 | /** Exception Flag: Zero divide. */
|
---|
[66392] | 3051 | #define X86_MXCSR_ZE RT_BIT_32(2)
|
---|
[47406] | 3052 | /** Exception Flag: Overflow. */
|
---|
[66392] | 3053 | #define X86_MXCSR_OE RT_BIT_32(3)
|
---|
[47406] | 3054 | /** Exception Flag: Underflow. */
|
---|
[66392] | 3055 | #define X86_MXCSR_UE RT_BIT_32(4)
|
---|
[47406] | 3056 | /** Exception Flag: Precision. */
|
---|
[66392] | 3057 | #define X86_MXCSR_PE RT_BIT_32(5)
|
---|
[40069] | 3058 |
|
---|
[47406] | 3059 | /** Denormals are zero. */
|
---|
[66392] | 3060 | #define X86_MXCSR_DAZ RT_BIT_32(6)
|
---|
[47406] | 3061 |
|
---|
| 3062 | /** Exception Mask: Invalid operation. */
|
---|
[66392] | 3063 | #define X86_MXCSR_IM RT_BIT_32(7)
|
---|
[47406] | 3064 | /** Exception Mask: Denormalized operand. */
|
---|
[66392] | 3065 | #define X86_MXCSR_DM RT_BIT_32(8)
|
---|
[47406] | 3066 | /** Exception Mask: Zero divide. */
|
---|
[66392] | 3067 | #define X86_MXCSR_ZM RT_BIT_32(9)
|
---|
[47406] | 3068 | /** Exception Mask: Overflow. */
|
---|
[66392] | 3069 | #define X86_MXCSR_OM RT_BIT_32(10)
|
---|
[47406] | 3070 | /** Exception Mask: Underflow. */
|
---|
[66392] | 3071 | #define X86_MXCSR_UM RT_BIT_32(11)
|
---|
[47406] | 3072 | /** Exception Mask: Precision. */
|
---|
[66392] | 3073 | #define X86_MXCSR_PM RT_BIT_32(12)
|
---|
[47406] | 3074 |
|
---|
| 3075 | /** Rounding control mask. */
|
---|
[66392] | 3076 | #define X86_MXCSR_RC_MASK UINT16_C(0x6000)
|
---|
[47406] | 3077 | /** Rounding control: To nearest. */
|
---|
[66392] | 3078 | #define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
|
---|
[47406] | 3079 | /** Rounding control: Down. */
|
---|
[66392] | 3080 | #define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
|
---|
[47406] | 3081 | /** Rounding control: Up. */
|
---|
[66392] | 3082 | #define X86_MXCSR_RC_UP UINT16_C(0x4000)
|
---|
[47406] | 3083 | /** Rounding control: Towards zero. */
|
---|
[66392] | 3084 | #define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
|
---|
[47406] | 3085 |
|
---|
| 3086 | /** Flush-to-zero for masked underflow. */
|
---|
[66392] | 3087 | #define X86_MXCSR_FZ RT_BIT_32(15)
|
---|
[47406] | 3088 |
|
---|
[54893] | 3089 | /** Misaligned Exception Mask (AMD MISALIGNSSE). */
|
---|
[66392] | 3090 | #define X86_MXCSR_MM RT_BIT_32(17)
|
---|
[47406] | 3091 | /** @} */
|
---|
| 3092 |
|
---|
[54896] | 3093 | /**
|
---|
| 3094 | * XSAVE header.
|
---|
| 3095 | */
|
---|
| 3096 | typedef struct X86XSAVEHDR
|
---|
| 3097 | {
|
---|
| 3098 | /** XTATE_BV - Bitmap indicating whether a component is in the state. */
|
---|
| 3099 | uint64_t bmXState;
|
---|
| 3100 | /** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
|
---|
| 3101 | uint64_t bmXComp;
|
---|
| 3102 | /** Reserved for furture extensions, probably MBZ. */
|
---|
| 3103 | uint64_t au64Reserved[6];
|
---|
| 3104 | } X86XSAVEHDR;
|
---|
| 3105 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 3106 | AssertCompileSize(X86XSAVEHDR, 64);
|
---|
| 3107 | #endif
|
---|
| 3108 | /** Pointer to an XSAVE header. */
|
---|
| 3109 | typedef X86XSAVEHDR *PX86XSAVEHDR;
|
---|
| 3110 | /** Pointer to a const XSAVE header. */
|
---|
| 3111 | typedef X86XSAVEHDR const *PCX86XSAVEHDR;
|
---|
[47406] | 3112 |
|
---|
[54896] | 3113 |
|
---|
| 3114 | /**
|
---|
| 3115 | * The high 128-bit YMM register state (XSAVE_C_YMM).
|
---|
| 3116 | * (The lower 128-bits being in X86FXSTATE.)
|
---|
| 3117 | */
|
---|
| 3118 | typedef struct X86XSAVEYMMHI
|
---|
| 3119 | {
|
---|
| 3120 | /** 16 registers in 64-bit mode, 8 in 32-bit mode. */
|
---|
| 3121 | X86XMMREG aYmmHi[16];
|
---|
| 3122 | } X86XSAVEYMMHI;
|
---|
| 3123 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 3124 | AssertCompileSize(X86XSAVEYMMHI, 256);
|
---|
| 3125 | #endif
|
---|
| 3126 | /** Pointer to a high 128-bit YMM register state. */
|
---|
| 3127 | typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
|
---|
| 3128 | /** Pointer to a const high 128-bit YMM register state. */
|
---|
| 3129 | typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
|
---|
| 3130 |
|
---|
| 3131 | /**
|
---|
| 3132 | * Intel MPX bound registers state (XSAVE_C_BNDREGS).
|
---|
| 3133 | */
|
---|
| 3134 | typedef struct X86XSAVEBNDREGS
|
---|
| 3135 | {
|
---|
| 3136 | /** Array of registers (BND0...BND3). */
|
---|
| 3137 | struct
|
---|
| 3138 | {
|
---|
| 3139 | /** Lower bound. */
|
---|
| 3140 | uint64_t uLowerBound;
|
---|
| 3141 | /** Upper bound. */
|
---|
| 3142 | uint64_t uUpperBound;
|
---|
| 3143 | } aRegs[4];
|
---|
| 3144 | } X86XSAVEBNDREGS;
|
---|
| 3145 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 3146 | AssertCompileSize(X86XSAVEBNDREGS, 64);
|
---|
| 3147 | #endif
|
---|
| 3148 | /** Pointer to a MPX bound register state. */
|
---|
| 3149 | typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
|
---|
| 3150 | /** Pointer to a const MPX bound register state. */
|
---|
| 3151 | typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
|
---|
| 3152 |
|
---|
| 3153 | /**
|
---|
| 3154 | * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
|
---|
| 3155 | */
|
---|
| 3156 | typedef struct X86XSAVEBNDCFG
|
---|
| 3157 | {
|
---|
| 3158 | uint64_t fConfig;
|
---|
| 3159 | uint64_t fStatus;
|
---|
| 3160 | } X86XSAVEBNDCFG;
|
---|
| 3161 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 3162 | AssertCompileSize(X86XSAVEBNDCFG, 16);
|
---|
| 3163 | #endif
|
---|
| 3164 | /** Pointer to a MPX bound config and status register state. */
|
---|
| 3165 | typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
|
---|
| 3166 | /** Pointer to a const MPX bound config and status register state. */
|
---|
| 3167 | typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
|
---|
| 3168 |
|
---|
| 3169 | /**
|
---|
| 3170 | * AVX-512 opmask state (XSAVE_C_OPMASK).
|
---|
| 3171 | */
|
---|
| 3172 | typedef struct X86XSAVEOPMASK
|
---|
| 3173 | {
|
---|
| 3174 | /** The K0..K7 values. */
|
---|
| 3175 | uint64_t aKRegs[8];
|
---|
| 3176 | } X86XSAVEOPMASK;
|
---|
| 3177 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 3178 | AssertCompileSize(X86XSAVEOPMASK, 64);
|
---|
| 3179 | #endif
|
---|
| 3180 | /** Pointer to a AVX-512 opmask state. */
|
---|
| 3181 | typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
|
---|
| 3182 | /** Pointer to a const AVX-512 opmask state. */
|
---|
| 3183 | typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
|
---|
| 3184 |
|
---|
| 3185 | /**
|
---|
| 3186 | * ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
|
---|
| 3187 | */
|
---|
| 3188 | typedef struct X86XSAVEZMMHI256
|
---|
| 3189 | {
|
---|
| 3190 | /** Upper 256-bits of ZMM0-15. */
|
---|
| 3191 | X86YMMREG aHi256Regs[16];
|
---|
| 3192 | } X86XSAVEZMMHI256;
|
---|
| 3193 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 3194 | AssertCompileSize(X86XSAVEZMMHI256, 512);
|
---|
| 3195 | #endif
|
---|
| 3196 | /** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
|
---|
| 3197 | typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
|
---|
| 3198 | /** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
|
---|
| 3199 | typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
|
---|
| 3200 |
|
---|
| 3201 | /**
|
---|
| 3202 | * ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
|
---|
| 3203 | */
|
---|
| 3204 | typedef struct X86XSAVEZMM16HI
|
---|
| 3205 | {
|
---|
| 3206 | /** ZMM16 thru ZMM31. */
|
---|
| 3207 | X86ZMMREG aRegs[16];
|
---|
| 3208 | } X86XSAVEZMM16HI;
|
---|
| 3209 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 3210 | AssertCompileSize(X86XSAVEZMM16HI, 1024);
|
---|
| 3211 | #endif
|
---|
| 3212 | /** Pointer to a state comprising ZMM16-32. */
|
---|
| 3213 | typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
|
---|
| 3214 | /** Pointer to a const state comprising ZMM16-32. */
|
---|
| 3215 | typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
|
---|
| 3216 |
|
---|
| 3217 | /**
|
---|
| 3218 | * AMD Light weight profiling state (XSAVE_C_LWP).
|
---|
| 3219 | *
|
---|
| 3220 | * We probably won't play with this as AMD seems to be dropping from their "zen"
|
---|
| 3221 | * processor micro architecture.
|
---|
| 3222 | */
|
---|
| 3223 | typedef struct X86XSAVELWP
|
---|
| 3224 | {
|
---|
| 3225 | /** Details when needed. */
|
---|
| 3226 | uint64_t auLater[128/8];
|
---|
| 3227 | } X86XSAVELWP;
|
---|
| 3228 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 3229 | AssertCompileSize(X86XSAVELWP, 128);
|
---|
| 3230 | #endif
|
---|
| 3231 |
|
---|
| 3232 |
|
---|
[56514] | 3233 | /**
|
---|
| 3234 | * x86 FPU/SSE/AVX/XXXX state.
|
---|
| 3235 | *
|
---|
| 3236 | * Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
|
---|
| 3237 | * changes to this structure.
|
---|
| 3238 | */
|
---|
[54896] | 3239 | typedef struct X86XSAVEAREA
|
---|
| 3240 | {
|
---|
| 3241 | /** The x87 and SSE region (or legacy region if you like). */
|
---|
| 3242 | X86FXSTATE x87;
|
---|
| 3243 | /** The XSAVE header. */
|
---|
| 3244 | X86XSAVEHDR Hdr;
|
---|
| 3245 | /** Beyond the header, there isn't really a fixed layout, but we can
|
---|
| 3246 | generally assume the YMM (AVX) register extensions are present and
|
---|
| 3247 | follows immediately. */
|
---|
| 3248 | union
|
---|
| 3249 | {
|
---|
[66883] | 3250 | /** The high 128-bit AVX registers for easy access by IEM.
|
---|
| 3251 | * @note This ASSUMES they will always be here... */
|
---|
| 3252 | X86XSAVEYMMHI YmmHi;
|
---|
| 3253 |
|
---|
[54896] | 3254 | /** This is a typical layout on intel CPUs (good for debuggers). */
|
---|
| 3255 | struct
|
---|
| 3256 | {
|
---|
| 3257 | X86XSAVEYMMHI YmmHi;
|
---|
| 3258 | X86XSAVEBNDREGS BndRegs;
|
---|
| 3259 | X86XSAVEBNDCFG BndCfg;
|
---|
| 3260 | uint8_t abFudgeToMatchDocs[0xB0];
|
---|
| 3261 | X86XSAVEOPMASK Opmask;
|
---|
| 3262 | X86XSAVEZMMHI256 ZmmHi256;
|
---|
| 3263 | X86XSAVEZMM16HI Zmm16Hi;
|
---|
| 3264 | } Intel;
|
---|
| 3265 |
|
---|
| 3266 | /** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
|
---|
| 3267 | struct
|
---|
| 3268 | {
|
---|
| 3269 | X86XSAVEYMMHI YmmHi;
|
---|
| 3270 | X86XSAVELWP Lwp;
|
---|
| 3271 | } AmdBd;
|
---|
| 3272 |
|
---|
[54898] | 3273 | /** To enbling static deployments that have a reasonable chance of working for
|
---|
| 3274 | * the next 3-6 CPU generations without running short on space, we allocate a
|
---|
| 3275 | * lot of extra space here, making the structure a round 8KB in size. This
|
---|
| 3276 | * leaves us 7616 bytes for extended state. The skylake xeons are likely to use
|
---|
| 3277 | * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
|
---|
[54896] | 3278 | uint8_t ab[8192 - 512 - 64];
|
---|
| 3279 | } u;
|
---|
| 3280 | } X86XSAVEAREA;
|
---|
| 3281 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 3282 | AssertCompileSize(X86XSAVEAREA, 8192);
|
---|
[54898] | 3283 | AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
|
---|
[54896] | 3284 | AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
|
---|
| 3285 | AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
|
---|
| 3286 | AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
|
---|
| 3287 | AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
|
---|
| 3288 | AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
|
---|
| 3289 | AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
|
---|
| 3290 | AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
|
---|
| 3291 | #endif
|
---|
[55048] | 3292 | /** Pointer to a XSAVE area. */
|
---|
| 3293 | typedef X86XSAVEAREA *PX86XSAVEAREA;
|
---|
| 3294 | /** Pointer to a const XSAVE area. */
|
---|
| 3295 | typedef X86XSAVEAREA const *PCX86XSAVEAREA;
|
---|
[54896] | 3296 |
|
---|
| 3297 |
|
---|
[66218] | 3298 | /** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
|
---|
[54896] | 3299 | * @{ */
|
---|
[55456] | 3300 | /** Bit 0 - x87 - Legacy FPU state (bit number) */
|
---|
| 3301 | #define XSAVE_C_X87_BIT 0
|
---|
[54896] | 3302 | /** Bit 0 - x87 - Legacy FPU state. */
|
---|
[55456] | 3303 | #define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
|
---|
| 3304 | /** Bit 1 - SSE - 128-bit SSE state (bit number). */
|
---|
| 3305 | #define XSAVE_C_SSE_BIT 1
|
---|
[54896] | 3306 | /** Bit 1 - SSE - 128-bit SSE state. */
|
---|
[55456] | 3307 | #define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
|
---|
| 3308 | /** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
|
---|
| 3309 | #define XSAVE_C_YMM_BIT 2
|
---|
[54896] | 3310 | /** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
|
---|
[55456] | 3311 | #define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
|
---|
| 3312 | /** Bit 3 - BNDREGS - MPX bound register state (bit number). */
|
---|
| 3313 | #define XSAVE_C_BNDREGS_BIT 3
|
---|
[54896] | 3314 | /** Bit 3 - BNDREGS - MPX bound register state. */
|
---|
[55456] | 3315 | #define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
|
---|
| 3316 | /** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
|
---|
| 3317 | #define XSAVE_C_BNDCSR_BIT 4
|
---|
[54896] | 3318 | /** Bit 4 - BNDCSR - MPX bound config and status state. */
|
---|
[55456] | 3319 | #define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
|
---|
| 3320 | /** Bit 5 - Opmask - opmask state (bit number). */
|
---|
| 3321 | #define XSAVE_C_OPMASK_BIT 5
|
---|
[54896] | 3322 | /** Bit 5 - Opmask - opmask state. */
|
---|
[55456] | 3323 | #define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
|
---|
| 3324 | /** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
|
---|
| 3325 | #define XSAVE_C_ZMM_HI256_BIT 6
|
---|
[54896] | 3326 | /** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
|
---|
[55456] | 3327 | #define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
|
---|
| 3328 | /** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
|
---|
| 3329 | #define XSAVE_C_ZMM_16HI_BIT 7
|
---|
[54896] | 3330 | /** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
|
---|
[55456] | 3331 | #define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
|
---|
[55690] | 3332 | /** Bit 9 - PKRU - Protection-key state (bit number). */
|
---|
| 3333 | #define XSAVE_C_PKRU_BIT 9
|
---|
| 3334 | /** Bit 9 - PKRU - Protection-key state. */
|
---|
| 3335 | #define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
|
---|
[55456] | 3336 | /** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
|
---|
| 3337 | #define XSAVE_C_LWP_BIT 62
|
---|
[54896] | 3338 | /** Bit 62 - LWP - Lightweight Profiling (AMD). */
|
---|
[55456] | 3339 | #define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
|
---|
[66218] | 3340 | /** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
|
---|
| 3341 | #define XSAVE_C_X_BIT 63
|
---|
| 3342 | /** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
|
---|
| 3343 | #define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
|
---|
[54896] | 3344 | /** @} */
|
---|
| 3345 |
|
---|
| 3346 |
|
---|
| 3347 |
|
---|
[1] | 3348 | /** @name Selector Descriptor
|
---|
| 3349 | * @{
|
---|
| 3350 | */
|
---|
| 3351 |
|
---|
[41268] | 3352 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
[1] | 3353 | /**
|
---|
[47247] | 3354 | * Descriptor attributes (as seen by VT-x).
|
---|
[19304] | 3355 | */
|
---|
| 3356 | typedef struct X86DESCATTRBITS
|
---|
| 3357 | {
|
---|
[24851] | 3358 | /** 00 - Segment Type. */
|
---|
[19304] | 3359 | unsigned u4Type : 4;
|
---|
[24851] | 3360 | /** 04 - Descriptor Type. System(=0) or code/data selector */
|
---|
[19304] | 3361 | unsigned u1DescType : 1;
|
---|
[53191] | 3362 | /** 05 - Descriptor Privilege level. */
|
---|
[19304] | 3363 | unsigned u2Dpl : 2;
|
---|
[24851] | 3364 | /** 07 - Flags selector present(=1) or not. */
|
---|
[19304] | 3365 | unsigned u1Present : 1;
|
---|
[24851] | 3366 | /** 08 - Segment limit 16-19. */
|
---|
[19304] | 3367 | unsigned u4LimitHigh : 4;
|
---|
[24851] | 3368 | /** 0c - Available for system software. */
|
---|
[19304] | 3369 | unsigned u1Available : 1;
|
---|
[24851] | 3370 | /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
|
---|
[19304] | 3371 | unsigned u1Long : 1;
|
---|
[24851] | 3372 | /** 0e - This flags meaning depends on the segment type. Try make sense out
|
---|
[19304] | 3373 | * of the intel manual yourself. */
|
---|
| 3374 | unsigned u1DefBig : 1;
|
---|
[24851] | 3375 | /** 0f - Granularity of the limit. If set 4KB granularity is used, if
|
---|
[19304] | 3376 | * clear byte. */
|
---|
| 3377 | unsigned u1Granularity : 1;
|
---|
[47247] | 3378 | /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
|
---|
[47241] | 3379 | unsigned u1Unusable : 1;
|
---|
[19304] | 3380 | } X86DESCATTRBITS;
|
---|
[41268] | 3381 | #endif /* !VBOX_FOR_DTRACE_LIB */
|
---|
[19304] | 3382 |
|
---|
[47247] | 3383 | /** @name X86DESCATTR masks
|
---|
| 3384 | * @{ */
|
---|
| 3385 | #define X86DESCATTR_TYPE UINT32_C(0x0000000f)
|
---|
| 3386 | #define X86DESCATTR_DT UINT32_C(0x00000010)
|
---|
| 3387 | #define X86DESCATTR_DPL UINT32_C(0x00000060)
|
---|
[47267] | 3388 | #define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
|
---|
[47738] | 3389 | #define X86DESCATTR_P UINT32_C(0x00000080)
|
---|
[47247] | 3390 | #define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
|
---|
| 3391 | #define X86DESCATTR_AVL UINT32_C(0x00001000)
|
---|
| 3392 | #define X86DESCATTR_L UINT32_C(0x00002000)
|
---|
| 3393 | #define X86DESCATTR_D UINT32_C(0x00004000)
|
---|
| 3394 | #define X86DESCATTR_G UINT32_C(0x00008000)
|
---|
| 3395 | #define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
|
---|
| 3396 | /** @} */
|
---|
| 3397 |
|
---|
[19304] | 3398 | #pragma pack(1)
|
---|
| 3399 | typedef union X86DESCATTR
|
---|
| 3400 | {
|
---|
| 3401 | /** Unsigned integer view. */
|
---|
| 3402 | uint32_t u;
|
---|
[41268] | 3403 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
[19304] | 3404 | /** Normal view. */
|
---|
| 3405 | X86DESCATTRBITS n;
|
---|
[41268] | 3406 | #endif
|
---|
[19304] | 3407 | } X86DESCATTR;
|
---|
| 3408 | #pragma pack()
|
---|
| 3409 | /** Pointer to descriptor attributes. */
|
---|
| 3410 | typedef X86DESCATTR *PX86DESCATTR;
|
---|
| 3411 | /** Pointer to const descriptor attributes. */
|
---|
| 3412 | typedef const X86DESCATTR *PCX86DESCATTR;
|
---|
| 3413 |
|
---|
[41270] | 3414 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
[19304] | 3415 |
|
---|
| 3416 | /**
|
---|
[1] | 3417 | * Generic descriptor table entry
|
---|
| 3418 | */
|
---|
| 3419 | #pragma pack(1)
|
---|
| 3420 | typedef struct X86DESCGENERIC
|
---|
| 3421 | {
|
---|
[47172] | 3422 | /** 00 - Limit - Low word. */
|
---|
[1] | 3423 | unsigned u16LimitLow : 16;
|
---|
[60087] | 3424 | /** 10 - Base address - low word.
|
---|
[19304] | 3425 | * Don't try set this to 24 because MSC is doing stupid things then. */
|
---|
[1] | 3426 | unsigned u16BaseLow : 16;
|
---|
[47172] | 3427 | /** 20 - Base address - first 8 bits of high word. */
|
---|
[1] | 3428 | unsigned u8BaseHigh1 : 8;
|
---|
[47172] | 3429 | /** 28 - Segment Type. */
|
---|
[1] | 3430 | unsigned u4Type : 4;
|
---|
[47172] | 3431 | /** 2c - Descriptor Type. System(=0) or code/data selector */
|
---|
[1] | 3432 | unsigned u1DescType : 1;
|
---|
[53191] | 3433 | /** 2d - Descriptor Privilege level. */
|
---|
[1] | 3434 | unsigned u2Dpl : 2;
|
---|
[47172] | 3435 | /** 2f - Flags selector present(=1) or not. */
|
---|
[1] | 3436 | unsigned u1Present : 1;
|
---|
[47172] | 3437 | /** 30 - Segment limit 16-19. */
|
---|
[1] | 3438 | unsigned u4LimitHigh : 4;
|
---|
[47172] | 3439 | /** 34 - Available for system software. */
|
---|
[1] | 3440 | unsigned u1Available : 1;
|
---|
[47172] | 3441 | /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
|
---|
[9656] | 3442 | unsigned u1Long : 1;
|
---|
[47172] | 3443 | /** 36 - This flags meaning depends on the segment type. Try make sense out
|
---|
[1] | 3444 | * of the intel manual yourself. */
|
---|
| 3445 | unsigned u1DefBig : 1;
|
---|
[47172] | 3446 | /** 37 - Granularity of the limit. If set 4KB granularity is used, if
|
---|
[1] | 3447 | * clear byte. */
|
---|
| 3448 | unsigned u1Granularity : 1;
|
---|
[47172] | 3449 | /** 38 - Base address - highest 8 bits. */
|
---|
[1] | 3450 | unsigned u8BaseHigh2 : 8;
|
---|
| 3451 | } X86DESCGENERIC;
|
---|
| 3452 | #pragma pack()
|
---|
| 3453 | /** Pointer to a generic descriptor entry. */
|
---|
| 3454 | typedef X86DESCGENERIC *PX86DESCGENERIC;
|
---|
| 3455 | /** Pointer to a const generic descriptor entry. */
|
---|
| 3456 | typedef const X86DESCGENERIC *PCX86DESCGENERIC;
|
---|
| 3457 |
|
---|
[42588] | 3458 | /** @name Bit offsets of X86DESCGENERIC members.
|
---|
| 3459 | * @{*/
|
---|
| 3460 | #define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
|
---|
| 3461 | #define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
|
---|
| 3462 | #define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
|
---|
| 3463 | #define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
|
---|
| 3464 | #define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
|
---|
| 3465 | #define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
|
---|
| 3466 | #define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
|
---|
| 3467 | #define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
|
---|
| 3468 | #define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
|
---|
| 3469 | #define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
|
---|
| 3470 | #define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
|
---|
| 3471 | #define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
|
---|
| 3472 | #define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
|
---|
| 3473 | /** @} */
|
---|
| 3474 |
|
---|
[59965] | 3475 |
|
---|
| 3476 | /** @name LAR mask
|
---|
| 3477 | * @{ */
|
---|
| 3478 | #define X86LAR_F_TYPE UINT16_C( 0x0f00)
|
---|
| 3479 | #define X86LAR_F_DT UINT16_C( 0x1000)
|
---|
| 3480 | #define X86LAR_F_DPL UINT16_C( 0x6000)
|
---|
| 3481 | #define X86LAR_F_DPL_SHIFT 13 /**< Shift count for the DPL value. */
|
---|
| 3482 | #define X86LAR_F_P UINT16_C( 0x8000)
|
---|
[60087] | 3483 | #define X86LAR_F_AVL UINT32_C(0x00100000)
|
---|
| 3484 | #define X86LAR_F_L UINT32_C(0x00200000)
|
---|
| 3485 | #define X86LAR_F_D UINT32_C(0x00400000)
|
---|
| 3486 | #define X86LAR_F_G UINT32_C(0x00800000)
|
---|
[59965] | 3487 | /** @} */
|
---|
| 3488 |
|
---|
| 3489 |
|
---|
[1] | 3490 | /**
|
---|
[19304] | 3491 | * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
|
---|
[1] | 3492 | */
|
---|
[19304] | 3493 | typedef struct X86DESCGATE
|
---|
[1] | 3494 | {
|
---|
[30922] | 3495 | /** 00 - Target code segment offset - Low word.
|
---|
[19304] | 3496 | * Ignored if task-gate. */
|
---|
| 3497 | unsigned u16OffsetLow : 16;
|
---|
[30922] | 3498 | /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
|
---|
[19304] | 3499 | * TSS selector if task-gate. */
|
---|
| 3500 | unsigned u16Sel : 16;
|
---|
[30922] | 3501 | /** 20 - Number of parameters for a call-gate.
|
---|
[19304] | 3502 | * Ignored if interrupt-, trap- or task-gate. */
|
---|
[65595] | 3503 | unsigned u5ParmCount : 5;
|
---|
| 3504 | /** 25 - Reserved / ignored. */
|
---|
| 3505 | unsigned u3Reserved : 3;
|
---|
[30922] | 3506 | /** 28 - Segment Type. */
|
---|
[1] | 3507 | unsigned u4Type : 4;
|
---|
[30922] | 3508 | /** 2c - Descriptor Type (0 = system). */
|
---|
[1] | 3509 | unsigned u1DescType : 1;
|
---|
[53191] | 3510 | /** 2d - Descriptor Privilege level. */
|
---|
[1] | 3511 | unsigned u2Dpl : 2;
|
---|
[30922] | 3512 | /** 2f - Flags selector present(=1) or not. */
|
---|
[1] | 3513 | unsigned u1Present : 1;
|
---|
[30922] | 3514 | /** 30 - Target code segment offset - High word.
|
---|
[19304] | 3515 | * Ignored if task-gate. */
|
---|
| 3516 | unsigned u16OffsetHigh : 16;
|
---|
| 3517 | } X86DESCGATE;
|
---|
| 3518 | /** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
|
---|
| 3519 | typedef X86DESCGATE *PX86DESCGATE;
|
---|
| 3520 | /** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
|
---|
| 3521 | typedef const X86DESCGATE *PCX86DESCGATE;
|
---|
[1] | 3522 |
|
---|
[41270] | 3523 | #endif /* VBOX_FOR_DTRACE_LIB */
|
---|
| 3524 |
|
---|
[1] | 3525 | /**
|
---|
| 3526 | * Descriptor table entry.
|
---|
| 3527 | */
|
---|
| 3528 | #pragma pack(1)
|
---|
| 3529 | typedef union X86DESC
|
---|
| 3530 | {
|
---|
[41270] | 3531 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
[1] | 3532 | /** Generic descriptor view. */
|
---|
| 3533 | X86DESCGENERIC Gen;
|
---|
[19304] | 3534 | /** Gate descriptor view. */
|
---|
| 3535 | X86DESCGATE Gate;
|
---|
[41270] | 3536 | #endif
|
---|
[1] | 3537 |
|
---|
[33540] | 3538 | /** 8 bit unsigned integer view. */
|
---|
[1] | 3539 | uint8_t au8[8];
|
---|
[33540] | 3540 | /** 16 bit unsigned integer view. */
|
---|
[1] | 3541 | uint16_t au16[4];
|
---|
[33540] | 3542 | /** 32 bit unsigned integer view. */
|
---|
[1] | 3543 | uint32_t au32[2];
|
---|
[36760] | 3544 | /** 64 bit unsigned integer view. */
|
---|
| 3545 | uint64_t au64[1];
|
---|
| 3546 | /** Unsigned integer view. */
|
---|
| 3547 | uint64_t u;
|
---|
[1] | 3548 | } X86DESC;
|
---|
[41247] | 3549 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
[19304] | 3550 | AssertCompileSize(X86DESC, 8);
|
---|
[41247] | 3551 | #endif
|
---|
[1] | 3552 | #pragma pack()
|
---|
| 3553 | /** Pointer to descriptor table entry. */
|
---|
| 3554 | typedef X86DESC *PX86DESC;
|
---|
| 3555 | /** Pointer to const descriptor table entry. */
|
---|
| 3556 | typedef const X86DESC *PCX86DESC;
|
---|
| 3557 |
|
---|
[9412] | 3558 | /** @def X86DESC_BASE
|
---|
| 3559 | * Return the base address of a descriptor.
|
---|
| 3560 | */
|
---|
[42407] | 3561 | #define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
|
---|
| 3562 | ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
|
---|
| 3563 | | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
|
---|
| 3564 | | ( (a_pDesc)->Gen.u16BaseLow ) )
|
---|
[9412] | 3565 |
|
---|
| 3566 | /** @def X86DESC_LIMIT
|
---|
| 3567 | * Return the limit of a descriptor.
|
---|
| 3568 | */
|
---|
[42407] | 3569 | #define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
|
---|
| 3570 | ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
|
---|
| 3571 | | ( (a_pDesc)->Gen.u16LimitLow ) )
|
---|
[9412] | 3572 |
|
---|
[42407] | 3573 | /** @def X86DESC_LIMIT_G
|
---|
| 3574 | * Return the limit of a descriptor with the granularity bit taken into account.
|
---|
| 3575 | * @returns Selector limit (uint32_t).
|
---|
| 3576 | * @param a_pDesc Pointer to the descriptor.
|
---|
| 3577 | */
|
---|
| 3578 | #define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
|
---|
| 3579 | ( (a_pDesc)->Gen.u1Granularity \
|
---|
| 3580 | ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
|
---|
| 3581 | : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
|
---|
| 3582 | )
|
---|
| 3583 |
|
---|
[36860] | 3584 | /** @def X86DESC_GET_HID_ATTR
|
---|
| 3585 | * Get the descriptor attributes for the hidden register.
|
---|
| 3586 | */
|
---|
[42407] | 3587 | #define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
|
---|
| 3588 | ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
|
---|
[36860] | 3589 |
|
---|
[41270] | 3590 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
[36860] | 3591 |
|
---|
[2806] | 3592 | /**
|
---|
[2808] | 3593 | * 64 bits generic descriptor table entry
|
---|
| 3594 | * Note: most of these bits have no meaning in long mode.
|
---|
| 3595 | */
|
---|
| 3596 | #pragma pack(1)
|
---|
| 3597 | typedef struct X86DESC64GENERIC
|
---|
| 3598 | {
|
---|
| 3599 | /** Limit - Low word - *IGNORED*. */
|
---|
[58693] | 3600 | uint32_t u16LimitLow : 16;
|
---|
[40182] | 3601 | /** Base address - low word. - *IGNORED*
|
---|
[19304] | 3602 | * Don't try set this to 24 because MSC is doing stupid things then. */
|
---|
[58693] | 3603 | uint32_t u16BaseLow : 16;
|
---|
[2808] | 3604 | /** Base address - first 8 bits of high word. - *IGNORED* */
|
---|
[58693] | 3605 | uint32_t u8BaseHigh1 : 8;
|
---|
[2808] | 3606 | /** Segment Type. */
|
---|
[58693] | 3607 | uint32_t u4Type : 4;
|
---|
[2808] | 3608 | /** Descriptor Type. System(=0) or code/data selector */
|
---|
[58693] | 3609 | uint32_t u1DescType : 1;
|
---|
[53191] | 3610 | /** Descriptor Privilege level. */
|
---|
[58693] | 3611 | uint32_t u2Dpl : 2;
|
---|
[2808] | 3612 | /** Flags selector present(=1) or not. */
|
---|
[58693] | 3613 | uint32_t u1Present : 1;
|
---|
[2808] | 3614 | /** Segment limit 16-19. - *IGNORED* */
|
---|
[58693] | 3615 | uint32_t u4LimitHigh : 4;
|
---|
[2808] | 3616 | /** Available for system software. - *IGNORED* */
|
---|
[58693] | 3617 | uint32_t u1Available : 1;
|
---|
[2808] | 3618 | /** Long mode flag. */
|
---|
[58693] | 3619 | uint32_t u1Long : 1;
|
---|
[2808] | 3620 | /** This flags meaning depends on the segment type. Try make sense out
|
---|
| 3621 | * of the intel manual yourself. */
|
---|
[58693] | 3622 | uint32_t u1DefBig : 1;
|
---|
[2808] | 3623 | /** Granularity of the limit. If set 4KB granularity is used, if
|
---|
| 3624 | * clear byte. - *IGNORED* */
|
---|
[58693] | 3625 | uint32_t u1Granularity : 1;
|
---|
[2808] | 3626 | /** Base address - highest 8 bits. - *IGNORED* */
|
---|
[58693] | 3627 | uint32_t u8BaseHigh2 : 8;
|
---|
[2810] | 3628 | /** Base address - bits 63-32. */
|
---|
[58693] | 3629 | uint32_t u32BaseHigh3 : 32;
|
---|
| 3630 | uint32_t u8Reserved : 8;
|
---|
| 3631 | uint32_t u5Zeros : 5;
|
---|
| 3632 | uint32_t u19Reserved : 19;
|
---|
[2808] | 3633 | } X86DESC64GENERIC;
|
---|
| 3634 | #pragma pack()
|
---|
| 3635 | /** Pointer to a generic descriptor entry. */
|
---|
| 3636 | typedef X86DESC64GENERIC *PX86DESC64GENERIC;
|
---|
| 3637 | /** Pointer to a const generic descriptor entry. */
|
---|
| 3638 | typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
|
---|
| 3639 |
|
---|
| 3640 | /**
|
---|
[2806] | 3641 | * System descriptor table entry (64 bits)
|
---|
[19304] | 3642 | *
|
---|
| 3643 | * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
|
---|
[2806] | 3644 | */
|
---|
| 3645 | #pragma pack(1)
|
---|
| 3646 | typedef struct X86DESC64SYSTEM
|
---|
| 3647 | {
|
---|
| 3648 | /** Limit - Low word. */
|
---|
[58693] | 3649 | uint32_t u16LimitLow : 16;
|
---|
[60087] | 3650 | /** Base address - low word.
|
---|
[19304] | 3651 | * Don't try set this to 24 because MSC is doing stupid things then. */
|
---|
[58693] | 3652 | uint32_t u16BaseLow : 16;
|
---|
[2806] | 3653 | /** Base address - first 8 bits of high word. */
|
---|
[58693] | 3654 | uint32_t u8BaseHigh1 : 8;
|
---|
[2806] | 3655 | /** Segment Type. */
|
---|
[58693] | 3656 | uint32_t u4Type : 4;
|
---|
[2806] | 3657 | /** Descriptor Type. System(=0) or code/data selector */
|
---|
[58693] | 3658 | uint32_t u1DescType : 1;
|
---|
[53191] | 3659 | /** Descriptor Privilege level. */
|
---|
[58693] | 3660 | uint32_t u2Dpl : 2;
|
---|
[2806] | 3661 | /** Flags selector present(=1) or not. */
|
---|
[58693] | 3662 | uint32_t u1Present : 1;
|
---|
[2806] | 3663 | /** Segment limit 16-19. */
|
---|
[58693] | 3664 | uint32_t u4LimitHigh : 4;
|
---|
[2806] | 3665 | /** Available for system software. */
|
---|
[58693] | 3666 | uint32_t u1Available : 1;
|
---|
[2806] | 3667 | /** Reserved - 0. */
|
---|
[58693] | 3668 | uint32_t u1Reserved : 1;
|
---|
[2806] | 3669 | /** This flags meaning depends on the segment type. Try make sense out
|
---|
| 3670 | * of the intel manual yourself. */
|
---|
[58693] | 3671 | uint32_t u1DefBig : 1;
|
---|
[2806] | 3672 | /** Granularity of the limit. If set 4KB granularity is used, if
|
---|
| 3673 | * clear byte. */
|
---|
[58693] | 3674 | uint32_t u1Granularity : 1;
|
---|
[2806] | 3675 | /** Base address - bits 31-24. */
|
---|
[58693] | 3676 | uint32_t u8BaseHigh2 : 8;
|
---|
[2806] | 3677 | /** Base address - bits 63-32. */
|
---|
[58693] | 3678 | uint32_t u32BaseHigh3 : 32;
|
---|
| 3679 | uint32_t u8Reserved : 8;
|
---|
| 3680 | uint32_t u5Zeros : 5;
|
---|
| 3681 | uint32_t u19Reserved : 19;
|
---|
[2806] | 3682 | } X86DESC64SYSTEM;
|
---|
| 3683 | #pragma pack()
|
---|
[19304] | 3684 | /** Pointer to a system descriptor entry. */
|
---|
[2806] | 3685 | typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
|
---|
[19304] | 3686 | /** Pointer to a const system descriptor entry. */
|
---|
[2806] | 3687 | typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
|
---|
| 3688 |
|
---|
[19304] | 3689 | /**
|
---|
| 3690 | * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
|
---|
| 3691 | */
|
---|
| 3692 | typedef struct X86DESC64GATE
|
---|
| 3693 | {
|
---|
| 3694 | /** Target code segment offset - Low word. */
|
---|
[58693] | 3695 | uint32_t u16OffsetLow : 16;
|
---|
[19304] | 3696 | /** Target code segment selector. */
|
---|
[58693] | 3697 | uint32_t u16Sel : 16;
|
---|
[19304] | 3698 | /** Interrupt stack table for interrupt- and trap-gates.
|
---|
| 3699 | * Ignored by call-gates. */
|
---|
[58693] | 3700 | uint32_t u3IST : 3;
|
---|
[19304] | 3701 | /** Reserved / ignored. */
|
---|
[58693] | 3702 | uint32_t u5Reserved : 5;
|
---|
[19304] | 3703 | /** Segment Type. */
|
---|
[58693] | 3704 | uint32_t u4Type : 4;
|
---|
[19304] | 3705 | /** Descriptor Type (0 = system). */
|
---|
[58693] | 3706 | uint32_t u1DescType : 1;
|
---|
[53191] | 3707 | /** Descriptor Privilege level. */
|
---|
[58693] | 3708 | uint32_t u2Dpl : 2;
|
---|
[19304] | 3709 | /** Flags selector present(=1) or not. */
|
---|
[58693] | 3710 | uint32_t u1Present : 1;
|
---|
[19304] | 3711 | /** Target code segment offset - High word.
|
---|
| 3712 | * Ignored if task-gate. */
|
---|
[58693] | 3713 | uint32_t u16OffsetHigh : 16;
|
---|
[19304] | 3714 | /** Target code segment offset - Top dword.
|
---|
| 3715 | * Ignored if task-gate. */
|
---|
[58693] | 3716 | uint32_t u32OffsetTop : 32;
|
---|
[19304] | 3717 | /** Reserved / ignored / must be zero.
|
---|
| 3718 | * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
|
---|
[58693] | 3719 | uint32_t u32Reserved : 32;
|
---|
[19304] | 3720 | } X86DESC64GATE;
|
---|
| 3721 | AssertCompileSize(X86DESC64GATE, 16);
|
---|
| 3722 | /** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
|
---|
| 3723 | typedef X86DESC64GATE *PX86DESC64GATE;
|
---|
| 3724 | /** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
|
---|
| 3725 | typedef const X86DESC64GATE *PCX86DESC64GATE;
|
---|
[2806] | 3726 |
|
---|
[41270] | 3727 | #endif /* VBOX_FOR_DTRACE_LIB */
|
---|
[19304] | 3728 |
|
---|
[2806] | 3729 | /**
|
---|
| 3730 | * Descriptor table entry.
|
---|
| 3731 | */
|
---|
| 3732 | #pragma pack(1)
|
---|
| 3733 | typedef union X86DESC64
|
---|
| 3734 | {
|
---|
[41270] | 3735 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
[2806] | 3736 | /** Generic descriptor view. */
|
---|
[2808] | 3737 | X86DESC64GENERIC Gen;
|
---|
| 3738 | /** System descriptor view. */
|
---|
| 3739 | X86DESC64SYSTEM System;
|
---|
[19304] | 3740 | /** Gate descriptor view. */
|
---|
[2808] | 3741 | X86DESC64GATE Gate;
|
---|
[41270] | 3742 | #endif
|
---|
[2806] | 3743 |
|
---|
[33540] | 3744 | /** 8 bit unsigned integer view. */
|
---|
[2808] | 3745 | uint8_t au8[16];
|
---|
[33540] | 3746 | /** 16 bit unsigned integer view. */
|
---|
[2808] | 3747 | uint16_t au16[8];
|
---|
[33540] | 3748 | /** 32 bit unsigned integer view. */
|
---|
[2808] | 3749 | uint32_t au32[4];
|
---|
[33540] | 3750 | /** 64 bit unsigned integer view. */
|
---|
[2812] | 3751 | uint64_t au64[2];
|
---|
[2806] | 3752 | } X86DESC64;
|
---|
[41247] | 3753 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
[19304] | 3754 | AssertCompileSize(X86DESC64, 16);
|
---|
[41247] | 3755 | #endif
|
---|
[2806] | 3756 | #pragma pack()
|
---|
| 3757 | /** Pointer to descriptor table entry. */
|
---|
| 3758 | typedef X86DESC64 *PX86DESC64;
|
---|
| 3759 | /** Pointer to const descriptor table entry. */
|
---|
| 3760 | typedef const X86DESC64 *PCX86DESC64;
|
---|
| 3761 |
|
---|
[19304] | 3762 | /** @def X86DESC64_BASE
|
---|
[9412] | 3763 | * Return the base of a 64-bit descriptor.
|
---|
| 3764 | */
|
---|
[42407] | 3765 | #define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
|
---|
| 3766 | ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
|
---|
| 3767 | | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
|
---|
| 3768 | | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
|
---|
| 3769 | | ( (a_pDesc)->Gen.u16BaseLow ) )
|
---|
[9412] | 3770 |
|
---|
| 3771 |
|
---|
[22429] | 3772 |
|
---|
| 3773 | /** @name Host system descriptor table entry - Use with care!
|
---|
| 3774 | * @{ */
|
---|
| 3775 | /** Host system descriptor table entry. */
|
---|
| 3776 | #if HC_ARCH_BITS == 64
|
---|
| 3777 | typedef X86DESC64 X86DESCHC;
|
---|
| 3778 | #else
|
---|
| 3779 | typedef X86DESC X86DESCHC;
|
---|
| 3780 | #endif
|
---|
| 3781 | /** Pointer to a host system descriptor table entry. */
|
---|
| 3782 | #if HC_ARCH_BITS == 64
|
---|
| 3783 | typedef PX86DESC64 PX86DESCHC;
|
---|
| 3784 | #else
|
---|
| 3785 | typedef PX86DESC PX86DESCHC;
|
---|
| 3786 | #endif
|
---|
| 3787 | /** Pointer to a const host system descriptor table entry. */
|
---|
| 3788 | #if HC_ARCH_BITS == 64
|
---|
| 3789 | typedef PCX86DESC64 PCX86DESCHC;
|
---|
| 3790 | #else
|
---|
| 3791 | typedef PCX86DESC PCX86DESCHC;
|
---|
| 3792 | #endif
|
---|
| 3793 | /** @} */
|
---|
| 3794 |
|
---|
| 3795 |
|
---|
[1] | 3796 | /** @name Selector Descriptor Types.
|
---|
| 3797 | * @{
|
---|
| 3798 | */
|
---|
| 3799 |
|
---|
| 3800 | /** @name Non-System Selector Types.
|
---|
| 3801 | * @{ */
|
---|
| 3802 | /** Code(=set)/Data(=clear) bit. */
|
---|
| 3803 | #define X86_SEL_TYPE_CODE 8
|
---|
[2104] | 3804 | /** Memory(=set)/System(=clear) bit. */
|
---|
[59961] | 3805 | #define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
|
---|
[1] | 3806 | /** Accessed bit. */
|
---|
| 3807 | #define X86_SEL_TYPE_ACCESSED 1
|
---|
| 3808 | /** Expand down bit (for data selectors only). */
|
---|
| 3809 | #define X86_SEL_TYPE_DOWN 4
|
---|
| 3810 | /** Conforming bit (for code selectors only). */
|
---|
| 3811 | #define X86_SEL_TYPE_CONF 4
|
---|
| 3812 | /** Write bit (for data selectors only). */
|
---|
| 3813 | #define X86_SEL_TYPE_WRITE 2
|
---|
| 3814 | /** Read bit (for code selectors only). */
|
---|
| 3815 | #define X86_SEL_TYPE_READ 2
|
---|
[42588] | 3816 | /** The bit number of the code segment read bit (relative to u4Type). */
|
---|
| 3817 | #define X86_SEL_TYPE_READ_BIT 1
|
---|
[1] | 3818 |
|
---|
| 3819 | /** Read only selector type. */
|
---|
| 3820 | #define X86_SEL_TYPE_RO 0
|
---|
| 3821 | /** Accessed read only selector type. */
|
---|
| 3822 | #define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
|
---|
| 3823 | /** Read write selector type. */
|
---|
| 3824 | #define X86_SEL_TYPE_RW 2
|
---|
| 3825 | /** Accessed read write selector type. */
|
---|
| 3826 | #define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
|
---|
| 3827 | /** Expand down read only selector type. */
|
---|
| 3828 | #define X86_SEL_TYPE_RO_DOWN 4
|
---|
| 3829 | /** Accessed expand down read only selector type. */
|
---|
| 3830 | #define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
|
---|
| 3831 | /** Expand down read write selector type. */
|
---|
| 3832 | #define X86_SEL_TYPE_RW_DOWN 6
|
---|
| 3833 | /** Accessed expand down read write selector type. */
|
---|
| 3834 | #define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
|
---|
| 3835 | /** Execute only selector type. */
|
---|
| 3836 | #define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
|
---|
| 3837 | /** Accessed execute only selector type. */
|
---|
| 3838 | #define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
|
---|
| 3839 | /** Execute and read selector type. */
|
---|
| 3840 | #define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
|
---|
| 3841 | /** Accessed execute and read selector type. */
|
---|
| 3842 | #define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
|
---|
| 3843 | /** Conforming execute only selector type. */
|
---|
| 3844 | #define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
|
---|
| 3845 | /** Accessed Conforming execute only selector type. */
|
---|
| 3846 | #define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
|
---|
| 3847 | /** Conforming execute and write selector type. */
|
---|
| 3848 | #define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
|
---|
| 3849 | /** Accessed Conforming execute and write selector type. */
|
---|
| 3850 | #define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
|
---|
| 3851 | /** @} */
|
---|
| 3852 |
|
---|
| 3853 |
|
---|
| 3854 | /** @name System Selector Types.
|
---|
| 3855 | * @{ */
|
---|
[36642] | 3856 | /** The TSS busy bit mask. */
|
---|
| 3857 | #define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
|
---|
| 3858 |
|
---|
[1] | 3859 | /** Undefined system selector type. */
|
---|
[2806] | 3860 | #define X86_SEL_TYPE_SYS_UNDEFINED 0
|
---|
[1] | 3861 | /** 286 TSS selector. */
|
---|
[2806] | 3862 | #define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
|
---|
[1] | 3863 | /** LDT selector. */
|
---|
[2806] | 3864 | #define X86_SEL_TYPE_SYS_LDT 2
|
---|
[1] | 3865 | /** 286 TSS selector - Busy. */
|
---|
[2806] | 3866 | #define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
|
---|
[1] | 3867 | /** 286 Callgate selector. */
|
---|
[2806] | 3868 | #define X86_SEL_TYPE_SYS_286_CALL_GATE 4
|
---|
[1] | 3869 | /** Taskgate selector. */
|
---|
[2806] | 3870 | #define X86_SEL_TYPE_SYS_TASK_GATE 5
|
---|
[1] | 3871 | /** 286 Interrupt gate selector. */
|
---|
[2806] | 3872 | #define X86_SEL_TYPE_SYS_286_INT_GATE 6
|
---|
[1] | 3873 | /** 286 Trapgate selector. */
|
---|
[2806] | 3874 | #define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
|
---|
[1] | 3875 | /** Undefined system selector. */
|
---|
[2806] | 3876 | #define X86_SEL_TYPE_SYS_UNDEFINED2 8
|
---|
[1] | 3877 | /** 386 TSS selector. */
|
---|
[2806] | 3878 | #define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
|
---|
[1] | 3879 | /** Undefined system selector. */
|
---|
[2806] | 3880 | #define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
|
---|
[1] | 3881 | /** 386 TSS selector - Busy. */
|
---|
[2806] | 3882 | #define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
|
---|
[1] | 3883 | /** 386 Callgate selector. */
|
---|
[2806] | 3884 | #define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
|
---|
[1] | 3885 | /** Undefined system selector. */
|
---|
[2806] | 3886 | #define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
|
---|
[1] | 3887 | /** 386 Interruptgate selector. */
|
---|
[2806] | 3888 | #define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
|
---|
[1] | 3889 | /** 386 Trapgate selector. */
|
---|
[2806] | 3890 | #define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
|
---|
[1] | 3891 | /** @} */
|
---|
| 3892 |
|
---|
[2806] | 3893 | /** @name AMD64 System Selector Types.
|
---|
| 3894 | * @{ */
|
---|
[30922] | 3895 | /** LDT selector. */
|
---|
[2806] | 3896 | #define AMD64_SEL_TYPE_SYS_LDT 2
|
---|
[30922] | 3897 | /** TSS selector - Busy. */
|
---|
[2806] | 3898 | #define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
|
---|
[30922] | 3899 | /** TSS selector - Busy. */
|
---|
[2806] | 3900 | #define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
|
---|
[30922] | 3901 | /** Callgate selector. */
|
---|
[2806] | 3902 | #define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
|
---|
[30922] | 3903 | /** Interruptgate selector. */
|
---|
[2806] | 3904 | #define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
|
---|
[30922] | 3905 | /** Trapgate selector. */
|
---|
[2806] | 3906 | #define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
|
---|
[1] | 3907 | /** @} */
|
---|
| 3908 |
|
---|
[2806] | 3909 | /** @} */
|
---|
[1] | 3910 |
|
---|
[2806] | 3911 |
|
---|
[1] | 3912 | /** @name Descriptor Table Entry Flag Masks.
|
---|
| 3913 | * These are for the 2nd 32-bit word of a descriptor.
|
---|
| 3914 | * @{ */
|
---|
| 3915 | /** Bits 8-11 - TYPE - Descriptor type mask. */
|
---|
[59961] | 3916 | #define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
|
---|
[1] | 3917 | /** Bit 12 - S - System (=0) or Code/Data (=1). */
|
---|
[59961] | 3918 | #define X86_DESC_S RT_BIT_32(12)
|
---|
[1] | 3919 | /** Bits 13-14 - DPL - Descriptor Privilege Level. */
|
---|
[59961] | 3920 | #define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
|
---|
[1] | 3921 | /** Bit 15 - P - Present. */
|
---|
[59961] | 3922 | #define X86_DESC_P RT_BIT_32(15)
|
---|
[1] | 3923 | /** Bit 20 - AVL - Available for system software. */
|
---|
[59961] | 3924 | #define X86_DESC_AVL RT_BIT_32(20)
|
---|
[1] | 3925 | /** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
|
---|
[59961] | 3926 | #define X86_DESC_DB RT_BIT_32(22)
|
---|
[1] | 3927 | /** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
|
---|
| 3928 | * used, if clear byte. */
|
---|
[59961] | 3929 | #define X86_DESC_G RT_BIT_32(23)
|
---|
[1] | 3930 | /** @} */
|
---|
| 3931 |
|
---|
| 3932 | /** @} */
|
---|
| 3933 |
|
---|
[31490] | 3934 |
|
---|
| 3935 | /** @name Task Segments.
|
---|
[15631] | 3936 | * @{
|
---|
| 3937 | */
|
---|
[31490] | 3938 |
|
---|
| 3939 | /**
|
---|
[51182] | 3940 | * The minimum TSS descriptor limit for 286 tasks.
|
---|
| 3941 | */
|
---|
| 3942 | #define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
|
---|
| 3943 |
|
---|
| 3944 | /**
|
---|
| 3945 | * The minimum TSS descriptor segment limit for 386 tasks.
|
---|
| 3946 | */
|
---|
| 3947 | #define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
|
---|
| 3948 |
|
---|
| 3949 | /**
|
---|
[31490] | 3950 | * 16-bit Task Segment (TSS).
|
---|
| 3951 | */
|
---|
[15631] | 3952 | #pragma pack(1)
|
---|
[31490] | 3953 | typedef struct X86TSS16
|
---|
| 3954 | {
|
---|
| 3955 | /** Back link to previous task. (static) */
|
---|
| 3956 | RTSEL selPrev;
|
---|
| 3957 | /** Ring-0 stack pointer. (static) */
|
---|
| 3958 | uint16_t sp0;
|
---|
| 3959 | /** Ring-0 stack segment. (static) */
|
---|
| 3960 | RTSEL ss0;
|
---|
| 3961 | /** Ring-1 stack pointer. (static) */
|
---|
| 3962 | uint16_t sp1;
|
---|
| 3963 | /** Ring-1 stack segment. (static) */
|
---|
| 3964 | RTSEL ss1;
|
---|
| 3965 | /** Ring-2 stack pointer. (static) */
|
---|
| 3966 | uint16_t sp2;
|
---|
| 3967 | /** Ring-2 stack segment. (static) */
|
---|
| 3968 | RTSEL ss2;
|
---|
| 3969 | /** IP before task switch. */
|
---|
| 3970 | uint16_t ip;
|
---|
| 3971 | /** FLAGS before task switch. */
|
---|
| 3972 | uint16_t flags;
|
---|
| 3973 | /** AX before task switch. */
|
---|
| 3974 | uint16_t ax;
|
---|
| 3975 | /** CX before task switch. */
|
---|
| 3976 | uint16_t cx;
|
---|
| 3977 | /** DX before task switch. */
|
---|
| 3978 | uint16_t dx;
|
---|
| 3979 | /** BX before task switch. */
|
---|
| 3980 | uint16_t bx;
|
---|
| 3981 | /** SP before task switch. */
|
---|
| 3982 | uint16_t sp;
|
---|
| 3983 | /** BP before task switch. */
|
---|
| 3984 | uint16_t bp;
|
---|
| 3985 | /** SI before task switch. */
|
---|
| 3986 | uint16_t si;
|
---|
| 3987 | /** DI before task switch. */
|
---|
| 3988 | uint16_t di;
|
---|
| 3989 | /** ES before task switch. */
|
---|
| 3990 | RTSEL es;
|
---|
| 3991 | /** CS before task switch. */
|
---|
| 3992 | RTSEL cs;
|
---|
| 3993 | /** SS before task switch. */
|
---|
| 3994 | RTSEL ss;
|
---|
| 3995 | /** DS before task switch. */
|
---|
| 3996 | RTSEL ds;
|
---|
| 3997 | /** LDTR before task switch. */
|
---|
| 3998 | RTSEL selLdt;
|
---|
| 3999 | } X86TSS16;
|
---|
[41247] | 4000 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
[51182] | 4001 | AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
|
---|
[41247] | 4002 | #endif
|
---|
[31490] | 4003 | #pragma pack()
|
---|
| 4004 | /** Pointer to a 16-bit task segment. */
|
---|
| 4005 | typedef X86TSS16 *PX86TSS16;
|
---|
| 4006 | /** Pointer to a const 16-bit task segment. */
|
---|
| 4007 | typedef const X86TSS16 *PCX86TSS16;
|
---|
| 4008 |
|
---|
| 4009 |
|
---|
| 4010 | /**
|
---|
| 4011 | * 32-bit Task Segment (TSS).
|
---|
| 4012 | */
|
---|
| 4013 | #pragma pack(1)
|
---|
[15631] | 4014 | typedef struct X86TSS32
|
---|
| 4015 | {
|
---|
| 4016 | /** Back link to previous task. (static) */
|
---|
| 4017 | RTSEL selPrev;
|
---|
| 4018 | uint16_t padding1;
|
---|
| 4019 | /** Ring-0 stack pointer. (static) */
|
---|
| 4020 | uint32_t esp0;
|
---|
| 4021 | /** Ring-0 stack segment. (static) */
|
---|
| 4022 | RTSEL ss0;
|
---|
| 4023 | uint16_t padding_ss0;
|
---|
| 4024 | /** Ring-1 stack pointer. (static) */
|
---|
| 4025 | uint32_t esp1;
|
---|
| 4026 | /** Ring-1 stack segment. (static) */
|
---|
| 4027 | RTSEL ss1;
|
---|
| 4028 | uint16_t padding_ss1;
|
---|
| 4029 | /** Ring-2 stack pointer. (static) */
|
---|
| 4030 | uint32_t esp2;
|
---|
| 4031 | /** Ring-2 stack segment. (static) */
|
---|
| 4032 | RTSEL ss2;
|
---|
| 4033 | uint16_t padding_ss2;
|
---|
| 4034 | /** Page directory for the task. (static) */
|
---|
| 4035 | uint32_t cr3;
|
---|
| 4036 | /** EIP before task switch. */
|
---|
| 4037 | uint32_t eip;
|
---|
| 4038 | /** EFLAGS before task switch. */
|
---|
| 4039 | uint32_t eflags;
|
---|
| 4040 | /** EAX before task switch. */
|
---|
| 4041 | uint32_t eax;
|
---|
| 4042 | /** ECX before task switch. */
|
---|
| 4043 | uint32_t ecx;
|
---|
| 4044 | /** EDX before task switch. */
|
---|
| 4045 | uint32_t edx;
|
---|
| 4046 | /** EBX before task switch. */
|
---|
| 4047 | uint32_t ebx;
|
---|
| 4048 | /** ESP before task switch. */
|
---|
| 4049 | uint32_t esp;
|
---|
| 4050 | /** EBP before task switch. */
|
---|
| 4051 | uint32_t ebp;
|
---|
| 4052 | /** ESI before task switch. */
|
---|
| 4053 | uint32_t esi;
|
---|
| 4054 | /** EDI before task switch. */
|
---|
| 4055 | uint32_t edi;
|
---|
| 4056 | /** ES before task switch. */
|
---|
| 4057 | RTSEL es;
|
---|
| 4058 | uint16_t padding_es;
|
---|
| 4059 | /** CS before task switch. */
|
---|
| 4060 | RTSEL cs;
|
---|
| 4061 | uint16_t padding_cs;
|
---|
| 4062 | /** SS before task switch. */
|
---|
| 4063 | RTSEL ss;
|
---|
| 4064 | uint16_t padding_ss;
|
---|
| 4065 | /** DS before task switch. */
|
---|
| 4066 | RTSEL ds;
|
---|
| 4067 | uint16_t padding_ds;
|
---|
| 4068 | /** FS before task switch. */
|
---|
| 4069 | RTSEL fs;
|
---|
| 4070 | uint16_t padding_fs;
|
---|
| 4071 | /** GS before task switch. */
|
---|
| 4072 | RTSEL gs;
|
---|
| 4073 | uint16_t padding_gs;
|
---|
| 4074 | /** LDTR before task switch. */
|
---|
| 4075 | RTSEL selLdt;
|
---|
| 4076 | uint16_t padding_ldt;
|
---|
| 4077 | /** Debug trap flag */
|
---|
| 4078 | uint16_t fDebugTrap;
|
---|
| 4079 | /** Offset relative to the TSS of the start of the I/O Bitmap
|
---|
| 4080 | * and the end of the interrupt redirection bitmap. */
|
---|
| 4081 | uint16_t offIoBitmap;
|
---|
| 4082 | } X86TSS32;
|
---|
| 4083 | #pragma pack()
|
---|
| 4084 | /** Pointer to task segment. */
|
---|
| 4085 | typedef X86TSS32 *PX86TSS32;
|
---|
| 4086 | /** Pointer to const task segment. */
|
---|
| 4087 | typedef const X86TSS32 *PCX86TSS32;
|
---|
[59285] | 4088 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 4089 | AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
|
---|
| 4090 | AssertCompileMemberOffset(X86TSS32, cr3, 28);
|
---|
| 4091 | AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
|
---|
| 4092 | #endif
|
---|
[1] | 4093 |
|
---|
[31490] | 4094 | /**
|
---|
| 4095 | * 64-bit Task segment.
|
---|
[15631] | 4096 | */
|
---|
| 4097 | #pragma pack(1)
|
---|
| 4098 | typedef struct X86TSS64
|
---|
| 4099 | {
|
---|
| 4100 | /** Reserved. */
|
---|
| 4101 | uint32_t u32Reserved;
|
---|
| 4102 | /** Ring-0 stack pointer. (static) */
|
---|
| 4103 | uint64_t rsp0;
|
---|
| 4104 | /** Ring-1 stack pointer. (static) */
|
---|
| 4105 | uint64_t rsp1;
|
---|
| 4106 | /** Ring-2 stack pointer. (static) */
|
---|
| 4107 | uint64_t rsp2;
|
---|
| 4108 | /** Reserved. */
|
---|
| 4109 | uint32_t u32Reserved2[2];
|
---|
| 4110 | /* IST */
|
---|
| 4111 | uint64_t ist1;
|
---|
| 4112 | uint64_t ist2;
|
---|
| 4113 | uint64_t ist3;
|
---|
| 4114 | uint64_t ist4;
|
---|
| 4115 | uint64_t ist5;
|
---|
| 4116 | uint64_t ist6;
|
---|
| 4117 | uint64_t ist7;
|
---|
| 4118 | /* Reserved. */
|
---|
| 4119 | uint16_t u16Reserved[5];
|
---|
| 4120 | /** Offset relative to the TSS of the start of the I/O Bitmap
|
---|
| 4121 | * and the end of the interrupt redirection bitmap. */
|
---|
| 4122 | uint16_t offIoBitmap;
|
---|
| 4123 | } X86TSS64;
|
---|
| 4124 | #pragma pack()
|
---|
[31490] | 4125 | /** Pointer to a 64-bit task segment. */
|
---|
[15631] | 4126 | typedef X86TSS64 *PX86TSS64;
|
---|
[31490] | 4127 | /** Pointer to a const 64-bit task segment. */
|
---|
[15631] | 4128 | typedef const X86TSS64 *PCX86TSS64;
|
---|
[41247] | 4129 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
[59285] | 4130 | AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
|
---|
[41247] | 4131 | #endif
|
---|
[15631] | 4132 |
|
---|
| 4133 | /** @} */
|
---|
| 4134 |
|
---|
| 4135 |
|
---|
[1] | 4136 | /** @name Selectors.
|
---|
| 4137 | * @{
|
---|
| 4138 | */
|
---|
| 4139 |
|
---|
| 4140 | /**
|
---|
| 4141 | * The shift used to convert a selector from and to index an index (C).
|
---|
| 4142 | */
|
---|
[42427] | 4143 | #define X86_SEL_SHIFT 3
|
---|
[1] | 4144 |
|
---|
| 4145 | /**
|
---|
[42407] | 4146 | * The mask used to mask off the table indicator and RPL of an selector.
|
---|
[1] | 4147 | */
|
---|
[42427] | 4148 | #define X86_SEL_MASK 0xfff8U
|
---|
[1] | 4149 |
|
---|
| 4150 | /**
|
---|
[42407] | 4151 | * The mask used to mask off the RPL of an selector.
|
---|
[42427] | 4152 | * This is suitable for checking for NULL selectors.
|
---|
[42407] | 4153 | */
|
---|
[42427] | 4154 | #define X86_SEL_MASK_OFF_RPL 0xfffcU
|
---|
[42407] | 4155 |
|
---|
| 4156 | /**
|
---|
[1] | 4157 | * The bit indicating that a selector is in the LDT and not in the GDT.
|
---|
| 4158 | */
|
---|
[42427] | 4159 | #define X86_SEL_LDT 0x0004U
|
---|
| 4160 |
|
---|
[1] | 4161 | /**
|
---|
| 4162 | * The bit mask for getting the RPL of a selector.
|
---|
| 4163 | */
|
---|
[42427] | 4164 | #define X86_SEL_RPL 0x0003U
|
---|
[1] | 4165 |
|
---|
[42427] | 4166 | /**
|
---|
| 4167 | * The mask covering both RPL and LDT.
|
---|
| 4168 | * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
|
---|
| 4169 | * checks.
|
---|
| 4170 | */
|
---|
| 4171 | #define X86_SEL_RPL_LDT 0x0007U
|
---|
| 4172 |
|
---|
[1] | 4173 | /** @} */
|
---|
| 4174 |
|
---|
| 4175 |
|
---|
| 4176 | /**
|
---|
| 4177 | * x86 Exceptions/Faults/Traps.
|
---|
| 4178 | */
|
---|
| 4179 | typedef enum X86XCPT
|
---|
| 4180 | {
|
---|
| 4181 | /** \#DE - Divide error. */
|
---|
| 4182 | X86_XCPT_DE = 0x00,
|
---|
| 4183 | /** \#DB - Debug event (single step, DRx, ..) */
|
---|
| 4184 | X86_XCPT_DB = 0x01,
|
---|
| 4185 | /** NMI - Non-Maskable Interrupt */
|
---|
| 4186 | X86_XCPT_NMI = 0x02,
|
---|
| 4187 | /** \#BP - Breakpoint (INT3). */
|
---|
| 4188 | X86_XCPT_BP = 0x03,
|
---|
| 4189 | /** \#OF - Overflow (INTO). */
|
---|
| 4190 | X86_XCPT_OF = 0x04,
|
---|
| 4191 | /** \#BR - Bound range exceeded (BOUND). */
|
---|
| 4192 | X86_XCPT_BR = 0x05,
|
---|
| 4193 | /** \#UD - Undefined opcode. */
|
---|
| 4194 | X86_XCPT_UD = 0x06,
|
---|
| 4195 | /** \#NM - Device not available (math coprocessor device). */
|
---|
| 4196 | X86_XCPT_NM = 0x07,
|
---|
| 4197 | /** \#DF - Double fault. */
|
---|
| 4198 | X86_XCPT_DF = 0x08,
|
---|
| 4199 | /** ??? - Coprocessor segment overrun (obsolete). */
|
---|
| 4200 | X86_XCPT_CO_SEG_OVERRUN = 0x09,
|
---|
| 4201 | /** \#TS - Taskswitch (TSS). */
|
---|
| 4202 | X86_XCPT_TS = 0x0a,
|
---|
| 4203 | /** \#NP - Segment no present. */
|
---|
| 4204 | X86_XCPT_NP = 0x0b,
|
---|
| 4205 | /** \#SS - Stack segment fault. */
|
---|
| 4206 | X86_XCPT_SS = 0x0c,
|
---|
| 4207 | /** \#GP - General protection fault. */
|
---|
| 4208 | X86_XCPT_GP = 0x0d,
|
---|
| 4209 | /** \#PF - Page fault. */
|
---|
| 4210 | X86_XCPT_PF = 0x0e,
|
---|
[47152] | 4211 | /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
|
---|
[1] | 4212 | /** \#MF - Math fault (FPU). */
|
---|
| 4213 | X86_XCPT_MF = 0x10,
|
---|
| 4214 | /** \#AC - Alignment check. */
|
---|
| 4215 | X86_XCPT_AC = 0x11,
|
---|
| 4216 | /** \#MC - Machine check. */
|
---|
| 4217 | X86_XCPT_MC = 0x12,
|
---|
| 4218 | /** \#XF - SIMD Floating-Pointer Exception. */
|
---|
[47152] | 4219 | X86_XCPT_XF = 0x13,
|
---|
[53191] | 4220 | /** \#VE - Virtualization Exception. */
|
---|
[47152] | 4221 | X86_XCPT_VE = 0x14,
|
---|
| 4222 | /** \#SX - Security Exception. */
|
---|
[66599] | 4223 | X86_XCPT_SX = 0x1e
|
---|
[1] | 4224 | } X86XCPT;
|
---|
| 4225 | /** Pointer to a x86 exception code. */
|
---|
| 4226 | typedef X86XCPT *PX86XCPT;
|
---|
| 4227 | /** Pointer to a const x86 exception code. */
|
---|
| 4228 | typedef const X86XCPT *PCX86XCPT;
|
---|
[66599] | 4229 | /** The last valid (currently reserved) exception value. */
|
---|
| 4230 | #define X86_XCPT_LAST 0x1f
|
---|
[1] | 4231 |
|
---|
| 4232 |
|
---|
| 4233 | /** @name Trap Error Codes
|
---|
| 4234 | * @{
|
---|
| 4235 | */
|
---|
| 4236 | /** External indicator. */
|
---|
| 4237 | #define X86_TRAP_ERR_EXTERNAL 1
|
---|
| 4238 | /** IDT indicator. */
|
---|
| 4239 | #define X86_TRAP_ERR_IDT 2
|
---|
| 4240 | /** Descriptor table indicator - If set LDT, if clear GDT. */
|
---|
| 4241 | #define X86_TRAP_ERR_TI 4
|
---|
| 4242 | /** Mask for getting the selector. */
|
---|
| 4243 | #define X86_TRAP_ERR_SEL_MASK 0xfff8
|
---|
| 4244 | /** Shift for getting the selector table index (C type index). */
|
---|
| 4245 | #define X86_TRAP_ERR_SEL_SHIFT 3
|
---|
| 4246 | /** @} */
|
---|
| 4247 |
|
---|
| 4248 |
|
---|
| 4249 | /** @name \#PF Trap Error Codes
|
---|
| 4250 | * @{
|
---|
| 4251 | */
|
---|
| 4252 | /** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
|
---|
[59961] | 4253 | #define X86_TRAP_PF_P RT_BIT_32(0)
|
---|
[1] | 4254 | /** Bit 1 - R/W - Read (clear) or write (set) access. */
|
---|
[59961] | 4255 | #define X86_TRAP_PF_RW RT_BIT_32(1)
|
---|
[1] | 4256 | /** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
|
---|
[59961] | 4257 | #define X86_TRAP_PF_US RT_BIT_32(2)
|
---|
[1] | 4258 | /** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
|
---|
[59961] | 4259 | #define X86_TRAP_PF_RSVD RT_BIT_32(3)
|
---|
[1] | 4260 | /** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
|
---|
[59961] | 4261 | #define X86_TRAP_PF_ID RT_BIT_32(4)
|
---|
[55690] | 4262 | /** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
|
---|
[59961] | 4263 | #define X86_TRAP_PF_PK RT_BIT_32(5)
|
---|
[1] | 4264 | /** @} */
|
---|
| 4265 |
|
---|
[1283] | 4266 | #pragma pack(1)
|
---|
[7121] | 4267 | /**
|
---|
[48284] | 4268 | * 16-bit IDTR.
|
---|
| 4269 | */
|
---|
| 4270 | typedef struct X86IDTR16
|
---|
| 4271 | {
|
---|
| 4272 | /** Offset. */
|
---|
| 4273 | uint16_t offSel;
|
---|
| 4274 | /** Selector. */
|
---|
| 4275 | uint16_t uSel;
|
---|
| 4276 | } X86IDTR16, *PX86IDTR16;
|
---|
| 4277 | #pragma pack()
|
---|
| 4278 |
|
---|
| 4279 | #pragma pack(1)
|
---|
| 4280 | /**
|
---|
[1283] | 4281 | * 32-bit IDTR/GDTR.
|
---|
| 4282 | */
|
---|
| 4283 | typedef struct X86XDTR32
|
---|
| 4284 | {
|
---|
| 4285 | /** Size of the descriptor table. */
|
---|
| 4286 | uint16_t cb;
|
---|
| 4287 | /** Address of the descriptor table. */
|
---|
[41267] | 4288 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
[1283] | 4289 | uint32_t uAddr;
|
---|
[41267] | 4290 | #else
|
---|
| 4291 | uint16_t au16Addr[2];
|
---|
| 4292 | #endif
|
---|
[1283] | 4293 | } X86XDTR32, *PX86XDTR32;
|
---|
| 4294 | #pragma pack()
|
---|
[1] | 4295 |
|
---|
[1283] | 4296 | #pragma pack(1)
|
---|
[7121] | 4297 | /**
|
---|
[1283] | 4298 | * 64-bit IDTR/GDTR.
|
---|
| 4299 | */
|
---|
| 4300 | typedef struct X86XDTR64
|
---|
| 4301 | {
|
---|
| 4302 | /** Size of the descriptor table. */
|
---|
| 4303 | uint16_t cb;
|
---|
| 4304 | /** Address of the descriptor table. */
|
---|
[41267] | 4305 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
[1283] | 4306 | uint64_t uAddr;
|
---|
[41267] | 4307 | #else
|
---|
| 4308 | uint16_t au16Addr[4];
|
---|
| 4309 | #endif
|
---|
[1283] | 4310 | } X86XDTR64, *PX86XDTR64;
|
---|
| 4311 | #pragma pack()
|
---|
[1] | 4312 |
|
---|
[36760] | 4313 |
|
---|
| 4314 | /** @name ModR/M
|
---|
| 4315 | * @{ */
|
---|
| 4316 | #define X86_MODRM_RM_MASK UINT8_C(0x07)
|
---|
| 4317 | #define X86_MODRM_REG_MASK UINT8_C(0x38)
|
---|
| 4318 | #define X86_MODRM_REG_SMASK UINT8_C(0x07)
|
---|
| 4319 | #define X86_MODRM_REG_SHIFT 3
|
---|
| 4320 | #define X86_MODRM_MOD_MASK UINT8_C(0xc0)
|
---|
| 4321 | #define X86_MODRM_MOD_SMASK UINT8_C(0x03)
|
---|
| 4322 | #define X86_MODRM_MOD_SHIFT 6
|
---|
[41247] | 4323 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
[36760] | 4324 | AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
|
---|
| 4325 | AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
|
---|
| 4326 | AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
|
---|
[66056] | 4327 | /** @def X86_MODRM_MAKE
|
---|
| 4328 | * @param a_Mod The mod value (0..3).
|
---|
| 4329 | * @param a_Reg The register value (0..7).
|
---|
| 4330 | * @param a_RegMem The register or memory value (0..7). */
|
---|
| 4331 | # define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
|
---|
[41247] | 4332 | #endif
|
---|
[1] | 4333 | /** @} */
|
---|
| 4334 |
|
---|
[36760] | 4335 | /** @name SIB
|
---|
| 4336 | * @{ */
|
---|
| 4337 | #define X86_SIB_BASE_MASK UINT8_C(0x07)
|
---|
| 4338 | #define X86_SIB_INDEX_MASK UINT8_C(0x38)
|
---|
| 4339 | #define X86_SIB_INDEX_SMASK UINT8_C(0x07)
|
---|
| 4340 | #define X86_SIB_INDEX_SHIFT 3
|
---|
| 4341 | #define X86_SIB_SCALE_MASK UINT8_C(0xc0)
|
---|
| 4342 | #define X86_SIB_SCALE_SMASK UINT8_C(0x03)
|
---|
| 4343 | #define X86_SIB_SCALE_SHIFT 6
|
---|
[41247] | 4344 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
[36760] | 4345 | AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
|
---|
| 4346 | AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
|
---|
| 4347 | AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
|
---|
[41247] | 4348 | #endif
|
---|
[36760] | 4349 | /** @} */
|
---|
| 4350 |
|
---|
[77293] | 4351 | /** @name General register indexes.
|
---|
[36760] | 4352 | * @{ */
|
---|
| 4353 | #define X86_GREG_xAX 0
|
---|
| 4354 | #define X86_GREG_xCX 1
|
---|
| 4355 | #define X86_GREG_xDX 2
|
---|
| 4356 | #define X86_GREG_xBX 3
|
---|
| 4357 | #define X86_GREG_xSP 4
|
---|
| 4358 | #define X86_GREG_xBP 5
|
---|
| 4359 | #define X86_GREG_xSI 6
|
---|
| 4360 | #define X86_GREG_xDI 7
|
---|
| 4361 | #define X86_GREG_x8 8
|
---|
| 4362 | #define X86_GREG_x9 9
|
---|
| 4363 | #define X86_GREG_x10 10
|
---|
| 4364 | #define X86_GREG_x11 11
|
---|
| 4365 | #define X86_GREG_x12 12
|
---|
| 4366 | #define X86_GREG_x13 13
|
---|
| 4367 | #define X86_GREG_x14 14
|
---|
| 4368 | #define X86_GREG_x15 15
|
---|
| 4369 | /** @} */
|
---|
[77293] | 4370 | /** General register count. */
|
---|
| 4371 | #define X86_GREG_COUNT 16
|
---|
[36760] | 4372 |
|
---|
| 4373 | /** @name X86_SREG_XXX - Segment register indexes.
|
---|
| 4374 | * @{ */
|
---|
| 4375 | #define X86_SREG_ES 0
|
---|
| 4376 | #define X86_SREG_CS 1
|
---|
| 4377 | #define X86_SREG_SS 2
|
---|
| 4378 | #define X86_SREG_DS 3
|
---|
| 4379 | #define X86_SREG_FS 4
|
---|
| 4380 | #define X86_SREG_GS 5
|
---|
| 4381 | /** @} */
|
---|
[42337] | 4382 | /** Segment register count. */
|
---|
| 4383 | #define X86_SREG_COUNT 6
|
---|
[36760] | 4384 |
|
---|
| 4385 |
|
---|
[47305] | 4386 | /** @name X86_OP_XXX - Prefixes
|
---|
| 4387 | * @{ */
|
---|
| 4388 | #define X86_OP_PRF_CS UINT8_C(0x2e)
|
---|
| 4389 | #define X86_OP_PRF_SS UINT8_C(0x36)
|
---|
| 4390 | #define X86_OP_PRF_DS UINT8_C(0x3e)
|
---|
| 4391 | #define X86_OP_PRF_ES UINT8_C(0x26)
|
---|
| 4392 | #define X86_OP_PRF_FS UINT8_C(0x64)
|
---|
| 4393 | #define X86_OP_PRF_GS UINT8_C(0x65)
|
---|
| 4394 | #define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
|
---|
| 4395 | #define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
|
---|
| 4396 | #define X86_OP_PRF_LOCK UINT8_C(0xf0)
|
---|
[65776] | 4397 | #define X86_OP_PRF_REPZ UINT8_C(0xf3)
|
---|
| 4398 | #define X86_OP_PRF_REPNZ UINT8_C(0xf2)
|
---|
[47305] | 4399 | #define X86_OP_REX_B UINT8_C(0x41)
|
---|
| 4400 | #define X86_OP_REX_X UINT8_C(0x42)
|
---|
| 4401 | #define X86_OP_REX_R UINT8_C(0x44)
|
---|
| 4402 | #define X86_OP_REX_W UINT8_C(0x48)
|
---|
[36760] | 4403 | /** @} */
|
---|
| 4404 |
|
---|
[47305] | 4405 |
|
---|
| 4406 | /** @} */
|
---|
| 4407 |
|
---|
[76585] | 4408 | #endif /* !IPRT_INCLUDED_x86_h */
|
---|
[1] | 4409 |
|
---|