acpi-tables.h

Last change on this file was 106337, checked in by vboxsync, 6 weeks ago
Runtime: Add ACPI table builder API to dynamically generate a DSDT/SSDT, bugref:10733
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1	/* $Id: acpi-tables.h 106337 2024-10-16 08:11:52Z vboxsync $ */
2	/** @file
3	* IPRT, ACPI (Advanced Configuration and Power Interface) table format.
4	*
5	* Spec taken from: https://uefi.org/sites/default/files/resources/ACPI_Spec_6_5_Aug29.pdf (2024-07-25)
6	*/
7
8	/*
9	* Copyright (C) 2024 Oracle and/or its affiliates.
10	*
11	* This file is part of VirtualBox base platform packages, as
12	* available from https://www.virtualbox.org.
13	*
14	* This program is free software; you can redistribute it and/or
15	* modify it under the terms of the GNU General Public License
16	* as published by the Free Software Foundation, in version 3 of the
17	* License.
18	*
19	* This program is distributed in the hope that it will be useful, but
20	* WITHOUT ANY WARRANTY; without even the implied warranty of
21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
22	* General Public License for more details.
23	*
24	* You should have received a copy of the GNU General Public License
25	* along with this program; if not, see <https://www.gnu.org/licenses>.
26	*
27	* The contents of this file may alternatively be used under the terms
28	* of the Common Development and Distribution License Version 1.0
29	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
30	* in the VirtualBox distribution, in which case the provisions of the
31	* CDDL are applicable instead of those of the GPL.
32	*
33	* You may elect to license modified versions of this file under the
34	* terms and conditions of either the GPL or the CDDL or both.
35	*
36	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
37	*/
38
39	#ifndef IPRT_INCLUDED_formats_acpi_tables_h
40	#define IPRT_INCLUDED_formats_acpi_tables_h
41	#ifndef RT_WITHOUT_PRAGMA_ONCE
42	# pragma once
43	#endif
44
45	#include <iprt/types.h>
46	#include <iprt/cdefs.h>
47	#include <iprt/assertcompile.h>
48
49
50	/** @defgroup grp_rt_formats_acpi_tbl Advanced Configuration and Power Interface (ACPI) table structures and definitions
51	* @ingroup grp_rt_formats
52	* @{
53	*/
54
55	/**
56	* Generic Address Structure (GAS)
57	*
58	* @see @acpi65{05_ACPI_Software_Programming_Model,generic-address-structure-gas}
59	*/
60	#pragma pack(1)
61	typedef struct ACPIGAS
62	{
63	uint8_t bAddrSpaceId; /*< 0x00: The address space ID. /
64	uint8_t cRegBits; /*< 0x01: The Register bit width. /
65	uint8_t offReg; /*< 0x02: The register bit offset at the given address. /
66	uint8_t bAccSize; /*< 0x03: The access size. /
67	uint64_t u64Address; /*< 0x04: The 64-bit address of the data structure or register. /
68	} ACPIGAS;
69	#pragma pack()
70	AssertCompileSize(ACPIGAS, 12);
71	/** Pointer to an ACPI generic address structure. */
72	typedef ACPIGAS *PACPIGAS;
73	/** Pointer to a const ACPI generic address structure. */
74	typedef const ACPIGAS *PCACPIGAS;
75
76
77	/** @name ACPI_GAS_ADDRESS_SPACE_ID_XXX - ACPIGAS::bAddrSpaceId
78	* @{ */
79	/** System Memory space. */
80	#define ACPI_GAS_ADDRESS_SPACE_ID_SYS_MEM UINT8_C(0x00)
81	/** System I/O space. */
82	#define ACPI_GAS_ADDRESS_SPACE_ID_SYS_IO UINT8_C(0x01)
83	/** PCI Configuration space. */
84	#define ACPI_GAS_ADDRESS_SPACE_ID_PCI_CFG UINT8_C(0x02)
85	/** Embedded Controller. */
86	#define ACPI_GAS_ADDRESS_SPACE_ID_EMC UINT8_C(0x03)
87	/** SMBus. */
88	#define ACPI_GAS_ADDRESS_SPACE_ID_SMBUS UINT8_C(0x04)
89	/** System CMOS. */
90	#define ACPI_GAS_ADDRESS_SPACE_ID_SYS_CMOS UINT8_C(0x05)
91	/** PCI BAR target. */
92	#define ACPI_GAS_ADDRESS_SPACE_ID_PCI_BAR_TGT UINT8_C(0x06)
93	/** IPMI. */
94	#define ACPI_GAS_ADDRESS_SPACE_ID_IPMI UINT8_C(0x07)
95	/** General Purpose I/O. */
96	#define ACPI_GAS_ADDRESS_SPACE_ID_GPIO UINT8_C(0x08)
97	/** General Serial Bus. */
98	#define ACPI_GAS_ADDRESS_SPACE_ID_GEN_SER_BUS UINT8_C(0x09)
99	/** Platform Communications Channel. */
100	#define ACPI_GAS_ADDRESS_SPACE_ID_PCC UINT8_C(0x0a)
101	/** Platform Runtime Mechanism. */
102	#define ACPI_GAS_ADDRESS_SPACE_ID_PRM UINT8_C(0x0b)
103	/** Functional Fixed Hardware. */
104	#define ACPI_GAS_ADDRESS_SPACE_ID_FFH UINT8_C(0x7f)
105	/** @} */
106
107
108	/** @name ACPI_GAS_ACCESS_SIZE_XXX - ACPIGAS::bAccSize
109	* @{ */
110	/** Undefined (legacy reasons). */
111	#define ACPI_GAS_ACCESS_SIZE_UNDEFINED UINT8_C(0)
112	/** Byte access. */
113	#define ACPI_GAS_ACCESS_SIZE_BYTE UINT8_C(1)
114	/** Word access. */
115	#define ACPI_GAS_ACCESS_SIZE_WORD UINT8_C(2)
116	/** Dword access. */
117	#define ACPI_GAS_ACCESS_SIZE_DWORD UINT8_C(3)
118	/** Qword access. */
119	#define ACPI_GAS_ACCESS_SIZE_QWORD UINT8_C(4)
120	/** @} */
121
122
123	/**
124	* Root System Description Pointer (RSDP)
125	*
126	* @see @acpi65{05_ACPI_Software_Programming_Model,root-system-description-pointer-rsdp}
127	*
128	* @note This is the format for revision 2 and later.
129	*/
130	#pragma pack(1)
131	typedef struct ACPIRSDP
132	{
133	uint8_t abSignature[8]; /*< 0x000: The signature for identifcation ("RSD PTR "). /
134	uint8_t bChkSum; /*< 0x008: The checksum of the fields defined in the ACPI 1.0 specification. /
135	uint8_t abOemId[6]; /*< 0x009: An OEM supplied string that identifies the OEM. /
136	uint8_t bRevision; /*< 0x00f: The revision of this structure. /
137	uint32_t u32AddrRsdt; /*< 0x010: The 32-bit physical address of the RSDT. /
138	uint32_t cbRsdp; /*< 0x014: The length of the table including the header, starting from offset 0. /
139	uint64_t u64AddrXsdt; /*< 0x018: The 64-bit physical address of the XSDT. /
140	uint8_t bExtChkSum; /*< 0x020: Checksum of the entire table, including both checksum fields. /
141	uint8_t abRsvd[3]; /*< 0x021: Reserved fields. /
142	} ACPIRSDP;
143	#pragma pack()
144	AssertCompileSize(ACPIRSDP, 36);
145	/** Pointer to an ACPI Root System Descriptor Pointer. */
146	typedef ACPIRSDP *PACPIRSDP;
147	/** Pointer to a const ACPI Root System Descriptor Pointer. */
148	typedef const ACPIRSDP *PCACPIRSDP;
149
150	/** The RSDP signature. */
151	#define ACPI_RSDP_SIGNATURE "RSD PTR "
152
153
154	/**
155	* System Description Table Header
156	*
157	* @see @acpi65{05_ACPI_Software_Programming_Model,system-description-table-header}
158	*/
159	typedef struct ACPITBLHDR
160	{
161	uint32_t u32Signature; /*< 0x000: The signature for identifcation. /
162	uint32_t cbTbl; /*< 0x004: Length of the table in bytes starting from the beginning of the header. /
163	uint8_t bRevision; /*< 0x008: Revision of the structure corresponding to the signature field for this table. /
164	uint8_t bChkSum; /*< 0x009: Checksum of the entire table including this field, must sum up to zero to be valid. /
165	uint8_t abOemId[6]; /*< 0x00a: An OEM supplied string that identifies the OEM. /
166	uint8_t abOemTblId[8]; /*< 0x010: An OEM supplied string to identify the particular data table. /
167	uint32_t u32OemRevision; /*< 0x018: An OEM supplied revision number. /
168	uint8_t abCreatorId[4]; /*< 0x01c: Vendor ID of the utility that created the table. /
169	uint32_t u32CreatorRevision; /*< 0x020: Revision of the utility that created the table. /
170	} ACPITBLHDR;
171	AssertCompileSize(ACPITBLHDR, 36);
172	/** Pointer to an ACPI System Description Tablhe Header. */
173	typedef ACPITBLHDR *PACPITBLHDR;
174	/** Pointer to a const ACPI System Description Tablhe Header. */
175	typedef const ACPITBLHDR *PCACPITBLHDR;
176
177
178	/** @def ACPI_SIGNATURE_MAKE_FROM_U8
179	* Create a table signature from the supplied 4 characters.
180	*/
181	#ifdef RT_BIG_ENDIAN
182	# define ACPI_SIGNATURE_MAKE_FROM_U8(b0, b1, b2, b3) RT_MAKE_U32_FROM_MSB_U8(b0, b1, b2, b3)
183	#elif defined(RT_LITTLE_ENDIAN)
184	# define ACPI_SIGNATURE_MAKE_FROM_U8(b0, b1, b2, b3) RT_MAKE_U32_FROM_U8(b0, b1, b2, b3)
185	#else
186	# error "Whut?"
187	#endif
188
189
190	/** @name ACPI_TABLE_HDR_SIGNATURE_XXX - ACPITBLHDR::abSignature
191	* @see @acpi65{05_ACPI_Software_Programming_Model,description-header-signatures-for-tables-defined-by-acpi}
192	* @{ */
193	/** Multiple APIC Description Table. */
194	#define ACPI_TABLE_HDR_SIGNATURE_APIC ACPI_SIGNATURE_MAKE_FROM_U8('A', 'P', 'I', 'C')
195	/** Boot Error Record Table. */
196	#define ACPI_TABLE_HDR_SIGNATURE_BERT ACPI_SIGNATURE_MAKE_FROM_U8('B', 'E', 'R', 'T')
197	/** Boot Graphics Resource Table. */
198	#define ACPI_TABLE_HDR_SIGNATURE_BGRT ACPI_SIGNATURE_MAKE_FROM_U8('B', 'G', 'R', 'T')
199	/** Virtual Firmware Confidential Computing Event Log Table. */
200	#define ACPI_TABLE_HDR_SIGNATURE_CCEL ACPI_SIGNATURE_MAKE_FROM_U8('C', 'C', 'E', 'L')
201	/** Corrected Platform Error Polling Table. */
202	#define ACPI_TABLE_HDR_SIGNATURE_CPEP ACPI_SIGNATURE_MAKE_FROM_U8('C', 'P', 'E', 'P')
203	/** Differentiated System Description Table. */
204	#define ACPI_TABLE_HDR_SIGNATURE_DSDT ACPI_SIGNATURE_MAKE_FROM_U8('D', 'S', 'D', 'T')
205	/** Embedded Controller Boot Resource Table. */
206	#define ACPI_TABLE_HDR_SIGNATURE_ECDT ACPI_SIGNATURE_MAKE_FROM_U8('E', 'C', 'D', 'T')
207	/** Error Injection Table. */
208	#define ACPI_TABLE_HDR_SIGNATURE_EINJ ACPI_SIGNATURE_MAKE_FROM_U8('E', 'I', 'N', 'J')
209	/** Error Record Serialization Table. */
210	#define ACPI_TABLE_HDR_SIGNATURE_ERST ACPI_SIGNATURE_MAKE_FROM_U8('E', 'R', 'S', 'T')
211	/** Fixed ACPI Description Table. */
212	#define ACPI_TABLE_HDR_SIGNATURE_FACP ACPI_SIGNATURE_MAKE_FROM_U8('F', 'A', 'C', 'P')
213	/** Firmware ACPI Control Structure. */
214	#define ACPI_TABLE_HDR_SIGNATURE_FACS ACPI_SIGNATURE_MAKE_FROM_U8('F', 'A', 'C', 'S')
215	/** Firmware Performance Data Table. */
216	#define ACPI_TABLE_HDR_SIGNATURE_FPDT ACPI_SIGNATURE_MAKE_FROM_U8('F', 'P', 'D', 'T')
217	/** Generic Timer Description Table. */
218	#define ACPI_TABLE_HDR_SIGNATURE_GTDT ACPI_SIGNATURE_MAKE_FROM_U8('G', 'T', 'D', 'T')
219	/** Hardware Error Source Table. */
220	#define ACPI_TABLE_HDR_SIGNATURE_HEST ACPI_SIGNATURE_MAKE_FROM_U8('H', 'E', 'S', 'T')
221	/** Miscellaneous GUIDed Table Entries. */
222	#define ACPI_TABLE_HDR_SIGNATURE_MISC ACPI_SIGNATURE_MAKE_FROM_U8('M', 'I', 'S', 'C')
223	/** Maximum System Characteristics Table. */
224	#define ACPI_TABLE_HDR_SIGNATURE_MSCT ACPI_SIGNATURE_MAKE_FROM_U8('M', 'S', 'C', 'T')
225	/** Memory Power State Table. */
226	#define ACPI_TABLE_HDR_SIGNATURE_MPST ACPI_SIGNATURE_MAKE_FROM_U8('M', 'P', 'S', 'T')
227	/** NVDIMM Firmware Interface Table. */
228	#define ACPI_TABLE_HDR_SIGNATURE_NFIT ACPI_SIGNATURE_MAKE_FROM_U8('N', 'F', 'I', 'T')
229	/** OEM Specific Information Table. */
230	#define ACPI_TABLE_HDR_SIGNATURE_OEM(a_b3) ACPI_SIGNATURE_MAKE_FROM_U8('O', 'E', 'M', a_b3)
231	/** Platform Communications Channel Table. */
232	#define ACPI_TABLE_HDR_SIGNATURE_PCCT ACPI_SIGNATURE_MAKE_FROM_U8('P', 'C', 'C', 'T')
233	/** Platform Health Assessment Table. */
234	#define ACPI_TABLE_HDR_SIGNATURE_PHAT ACPI_SIGNATURE_MAKE_FROM_U8('P', 'H', 'A', 'T')
235	/** Platform Memory Topology Table. */
236	#define ACPI_TABLE_HDR_SIGNATURE_PMTT ACPI_SIGNATURE_MAKE_FROM_U8('P', 'M', 'T', 'T')
237	/** Processor Properties Topology Table. */
238	#define ACPI_TABLE_HDR_SIGNATURE_PPTT ACPI_SIGNATURE_MAKE_FROM_U8('P', 'P', 'T', 'T')
239	/** Persistent System Description Table. */
240	#define ACPI_TABLE_HDR_SIGNATURE_PSDT ACPI_SIGNATURE_MAKE_FROM_U8('P', 'S', 'D', 'T')
241	/** ACPI RAS Feature Table. */
242	#define ACPI_TABLE_HDR_SIGNATURE_RASF ACPI_SIGNATURE_MAKE_FROM_U8('R', 'A', 'S', 'F')
243	/** ACPI RAS2 Feature Table. */
244	#define ACPI_TABLE_HDR_SIGNATURE_RAS2 ACPI_SIGNATURE_MAKE_FROM_U8('R', 'A', 'S', '2')
245	/** Root System Description Table. */
246	#define ACPI_TABLE_HDR_SIGNATURE_RSDT ACPI_SIGNATURE_MAKE_FROM_U8('R', 'S', 'D', 'T')
247	/** Smart Battery Specification Table. */
248	#define ACPI_TABLE_HDR_SIGNATURE_SBST ACPI_SIGNATURE_MAKE_FROM_U8('S', 'B', 'S', 'T')
249	/** Secure DEVices Table. */
250	#define ACPI_TABLE_HDR_SIGNATURE_SDEV ACPI_SIGNATURE_MAKE_FROM_U8('S', 'D', 'E', 'V')
251	/** System Locality Distance Information Table. */
252	#define ACPI_TABLE_HDR_SIGNATURE_SLIT ACPI_SIGNATURE_MAKE_FROM_U8('S', 'L', 'I', 'T')
253	/** System Resource Affinity Table. */
254	#define ACPI_TABLE_HDR_SIGNATURE_SRAT ACPI_SIGNATURE_MAKE_FROM_U8('S', 'R', 'A', 'T')
255	/** Secondary System Description Table. */
256	#define ACPI_TABLE_HDR_SIGNATURE_SSDT ACPI_SIGNATURE_MAKE_FROM_U8('S', 'S', 'D', 'T')
257	/** Storage Volume Key Data Table. */
258	#define ACPI_TABLE_HDR_SIGNATURE_SVKL ACPI_SIGNATURE_MAKE_FROM_U8('S', 'V', 'K', 'L')
259	/** Extended System Description Table. */
260	#define ACPI_TABLE_HDR_SIGNATURE_XSDT ACPI_SIGNATURE_MAKE_FROM_U8('X', 'S', 'D', 'T')
261	/** @} */
262
263
264	/** @name ACPI_TABLE_HDR_SIGNATURE_RSVD_XXX - ACPITBLHDR::abSignature
265	* @see @acpi65{05_ACPI_Software_Programming_Model,description-header-signatures-for-tables-reserved-by-acpi}
266	* @{ */
267	/** ARM Error Source Table. */
268	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_AEST ACPI_SIGNATURE_MAKE_FROM_U8('A', 'E', 'S', 'T')
269	/** ARM Generic Diagnostic Dump and Reset Interface. */
270	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_AGDI ACPI_SIGNATURE_MAKE_FROM_U8('A', 'G', 'D', 'I')
271	/** ARM Performance Monitoring Unit Table. */
272	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_APMT ACPI_SIGNATURE_MAKE_FROM_U8('A', 'P', 'M', 'T')
273	/** BIOS Data ACPI Table. */
274	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_BDAT ACPI_SIGNATURE_MAKE_FROM_U8('B', 'D', 'A', 'T')
275	/** Reserved. */
276	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_BOOT ACPI_SIGNATURE_MAKE_FROM_U8('B', 'O', 'O', 'T')
277	/** CXL Early Discovery Table. */
278	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_CEDT ACPI_SIGNATURE_MAKE_FROM_U8('C', 'E', 'D', 'T')
279	/** Core System Resource Table. */
280	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_CSRT ACPI_SIGNATURE_MAKE_FROM_U8('C', 'S', 'R', 'T')
281	/** Debug Port Table. */
282	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_DBGP ACPI_SIGNATURE_MAKE_FROM_U8('D', 'B', 'G', 'P')
283	/** Debug Port Table 2. */
284	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_DBG2 ACPI_SIGNATURE_MAKE_FROM_U8('D', 'B', 'G', '2')
285	/** DMA Remapping Table. */
286	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_DMAR ACPI_SIGNATURE_MAKE_FROM_U8('D', 'M', 'A', 'R')
287	/** Dynamic Root of Trust for Measurement Table. */
288	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_DRTM ACPI_SIGNATURE_MAKE_FROM_U8('D', 'R', 'T', 'M')
289	/** DMA TXT Protected Range. */
290	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_DTPR ACPI_SIGNATURE_MAKE_FROM_U8('D', 'T', 'P', 'R')
291	/** Event Timer Description Table. */
292	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_ETDT ACPI_SIGNATURE_MAKE_FROM_U8('E', 'T', 'D', 'T')
293	/** IA-PC High Precision Event Timer Table. */
294	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_HPET ACPI_SIGNATURE_MAKE_FROM_U8('H', 'P', 'E', 'T')
295	/** iSCSI Boot Firmware Table. */
296	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_IBFT ACPI_SIGNATURE_MAKE_FROM_U8('I', 'B', 'F', 'T')
297	/** Inline Encryption Reporting Structure. */
298	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_IERS ACPI_SIGNATURE_MAKE_FROM_U8('I', 'E', 'R', 'S')
299	/** I/O Remapping Table. */
300	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_IORT ACPI_SIGNATURE_MAKE_FROM_U8('I', 'O', 'R', 'T')
301	/** I/O Virtualization Reporting Structure. */
302	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_IVRS ACPI_SIGNATURE_MAKE_FROM_U8('I', 'V', 'R', 'S')
303	/** Key Programming Interface for Root Complex Integrity and Data Encryption (IDE). */
304	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_KEYP ACPI_SIGNATURE_MAKE_FROM_U8('K', 'E', 'Y', 'P')
305	/** Low Power Idle Table. */
306	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_LPIT ACPI_SIGNATURE_MAKE_FROM_U8('L', 'P', 'I', 'T')
307	/** PCI Express Memory Mapped Configuration. */
308	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_MCFG ACPI_SIGNATURE_MAKE_FROM_U8('M', 'C', 'F', 'G')
309	/** Management Controller Host Interface Table. */
310	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_MCHI ACPI_SIGNATURE_MAKE_FROM_U8('M', 'C', 'H', 'I')
311	/** Microsoft Pluton Security Processor Table. */
312	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_MHSP ACPI_SIGNATURE_MAKE_FROM_U8('M', 'H', 'S', 'P')
313	/** ARM Memory Partitioning and Monitoring. */
314	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_MPAM ACPI_SIGNATURE_MAKE_FROM_U8('M', 'P', 'A', 'M')
315	/** Microsoft Data Management Table. */
316	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_MSDM ACPI_SIGNATURE_MAKE_FROM_U8('M', 'S', 'D', 'M')
317	/** NVMe-over-Fabric (NVMe-oF) Boot Firmware Table. */
318	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_NBFT ACPI_SIGNATURE_MAKE_FROM_U8('N', 'B', 'F', 'T')
319	/** Platform Runtime Mechanism Table. */
320	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_PRMT ACPI_SIGNATURE_MAKE_FROM_U8('P', 'R', 'M', 'T')
321	/** Regulatory Graphics Resource Table. */
322	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_RGRT ACPI_SIGNATURE_MAKE_FROM_U8('R', 'G', 'R', 'T')
323	/** Software Delegated Exceptions Interface. */
324	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_SDEI ACPI_SIGNATURE_MAKE_FROM_U8('S', 'D', 'E', 'I')
325	/** Microsoft Software Licensing Table. */
326	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_SLIC ACPI_SIGNATURE_MAKE_FROM_U8('S', 'L', 'I', 'C')
327	/** Microsoft Serial Port Console Redirection Table. */
328	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_SPCR ACPI_SIGNATURE_MAKE_FROM_U8('S', 'P', 'C', 'R')
329	/** Server Platform Management Interface Table. */
330	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_SPMI ACPI_SIGNATURE_MAKE_FROM_U8('S', 'P', 'M', 'I')
331	/** _STA OVerride Table. */
332	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_STAO ACPI_SIGNATURE_MAKE_FROM_U8('S', 'T', 'A', 'O')
333	/** Sound Wire File Table. */
334	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_SWFT ACPI_SIGNATURE_MAKE_FROM_U8('S', 'W', 'F', 'T')
335	/** Trusted Computing Platform Alliance Capabilities Table. */
336	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_TCPA ACPI_SIGNATURE_MAKE_FROM_U8('T', 'C', 'P', 'A')
337	/** Trusted Platform Module 2 Table. */
338	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_TPM2 ACPI_SIGNATURE_MAKE_FROM_U8('T', 'P', 'M', '2')
339	/** Unified Extensible Firmware Interface. */
340	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_UEFI ACPI_SIGNATURE_MAKE_FROM_U8('U', 'E', 'F', 'I')
341	/** Windows ACPI Emulated Devics Table. */
342	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_WAET ACPI_SIGNATURE_MAKE_FROM_U8('W', 'A', 'E', 'T')
343	/** Watchdog Action Table. */
344	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_WDAT ACPI_SIGNATURE_MAKE_FROM_U8('W', 'D', 'A', 'T')
345	/** Watchdog Descriptor Table. */
346	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_WDDT ACPI_SIGNATURE_MAKE_FROM_U8('W', 'D', 'D', 'T')
347	/** Watchdog Resource Table. */
348	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_WDRT ACPI_SIGNATURE_MAKE_FROM_U8('W', 'D', 'R', 'T')
349	/** Windows Platform Binary Table. */
350	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_WPBT ACPI_SIGNATURE_MAKE_FROM_U8('W', 'P', 'B', 'T')
351	/** Windows Security Mitigations Table. */
352	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_WSMT ACPI_SIGNATURE_MAKE_FROM_U8('W', 'S', 'M', 'T')
353	/** Xen Project. */
354	#define ACPI_TABLE_HDR_SIGNATURE_RSVD_XENV ACPI_SIGNATURE_MAKE_FROM_U8('X', 'E', 'N', 'V')
355	/** @} */
356
357
358	/**
359	* Root System Description Table (RSDT)
360	*
361	* @see @acpi65{05_ACPI_Software_Programming_Model,root-system-description-table-rsdt}
362	*/
363	typedef struct ACPIRSDT
364	{
365	ACPITBLHDR Hdr; /*< 0x000: The table header. /
366	RT_FLEXIBLE_ARRAY_EXTENSION
367	uint32_t au32AddrTbl[RT_FLEXIBLE_ARRAY]; /*< 0x024: Array of 32-bit physical addresses pointing to other tables, variable in size. /
368	} ACPIRSDT;
369	//AssertCompileSize(ACPIRSDT, 40);
370	/** Pointer to an ACPI Root System Description Table. */
371	typedef ACPIRSDT *PACPIRSDT;
372	/** Pointer to a const ACPI Root System Description Table. */
373	typedef const ACPIRSDT *PCACPIRSDT;
374
375
376	/** The ACPI RSDT signature. */
377	#define ACPI_RSDT_REVISION 1
378
379
380	/**
381	* Extended System Description Table (XSDT)
382	*
383	* @see @acpi65{05_ACPI_Software_Programming_Model,extended-system-description-table-xsdt}
384	*/
385	#pragma pack(1)
386	typedef struct ACPIXSDT
387	{
388	ACPITBLHDR Hdr; /*< 0x000: The table header. /
389	RT_FLEXIBLE_ARRAY_EXTENSION
390	uint64_t au64AddrTbl[RT_FLEXIBLE_ARRAY]; /*< 0x024: Array of 64-bit physical addresses pointing to other tables, variable in size. /
391	} ACPIXSDT;
392	#pragma pack()
393	//AssertCompileSize(ACPIXSDT, 44);
394	/** Pointer to an ACPI Extended System Description Table. */
395	typedef ACPIXSDT *PACPIXSDT;
396	/** Pointer to a const ACPI Extended System Description Table. */
397	typedef const ACPIXSDT *PCACPIXSDT;
398
399
400	/** The ACPI XSDT signature. */
401	#define ACPI_XSDT_REVISION 1
402
403
404	/**
405	* Fixed ACPI Description Table (ACPIFADT)
406	*
407	* @see @acpi65{05_ACPI_Software_Programming_Model,fixed-acpi-description-table-fadt}
408	*/
409	#pragma pack(1)
410	typedef struct ACPIFADT
411	{
412	ACPITBLHDR Hdr; /*< 0x000: The table header. /
413	uint32_t u32AddrFwCtrl; /*< 0x024: Physical memory address of the FACS, where OSPM and Firmware exchange control information. /
414	uint32_t u32AddrDsdt; /*< 0x028: Physical memory address of the DSDT. /
415	uint8_t bRsvd0; /*< 0x02c: Reserved from ACPI 2.0 onwards, ACPI 1.0 has a field named INT_MODEL. /
416	uint8_t bPreferredPmProfile; /*< 0x02d: Preferred power management profile set by OEM. /
417	uint16_t u16SciInt; /*< 0x02e: System vector the SCI interrupt is wired to in 8259 mode, if no 8259 is present this is the GSI. /
418	uint32_t u32PortSmiCmd; /*< 0x030: System port address of the SMI command port. /
419	uint8_t bAcpiEnable; /*< 0x034: Value to write to the SMI command port to disable SMI ownership of the ACPI hardware registers. /
420	uint8_t bAcpiDisable; /*< 0x035: Value to write to the SMI command port to re-enable SMI ownership of the ACPI hardware registers. /
421	uint8_t bS4BiosReq; /*< 0x036: Value to write to the SMI command port to enter the S4 BIOS state. /
422	uint8_t bPStateCnt; /*< 0x037: Value to write to the SMI command port to assume processor performance state control responsibility. /
423	uint32_t u32PortPm1aEvtBlk; /*< 0x038: System port address of the PM1a Event Register Block. /
424	uint32_t u32PortPm1bEvtBlk; /*< 0x03c: System port address of the PM1b Event Register Block. /
425	uint32_t u32PortPm1aCntBlk; /*< 0x040: System port address of the PM1a Control Register Block. /
426	uint32_t u32PortPm1bCntBlk; /*< 0x044: System port address of the PM1b Control Register Block. /
427	uint32_t u32PortPm2CntBlk; /*< 0x048: System port address of the PM2 Control Register Block. /
428	uint32_t u32PortPmTmrBlk; /*< 0x04c: System port address of the Power Management Timer Control Register Block. /
429	uint32_t u32PortGpe0Blk; /*< 0x050: System port address of the General Purpose Event 0 Register Block. /
430	uint32_t u32PortGpe1Blk; /*< 0x054: System port address of the General Purpose Event 1 Register Block. /
431	uint8_t cbPm1EvtDecoded; /*< 0x058: Number of bytes decoded by PM1a_EVT_BLK and, if supported, PM1b_EVT_BLK. /
432	uint8_t cbPm1CntDecoded; /*< 0x059: Number of bytes decoded by PM1a_CNT_BLK and, if supported, PM1b_CNT_BLK. /
433	uint8_t cbPm2CntDecoded; /*< 0x05a: Number of bytes decoded by PM2_CNT_BL. /
434	uint8_t cbPmTmrDecoded; /*< 0x05b: Number of bytes decoded by PM_TMR_BLK. /
435	uint8_t cbGpe0BlkDecoded; /*< 0x05c: Length of the register GPE0_BLK or X_GPE0_BLK. /
436	uint8_t cbGpe1BlkDecoded; /*< 0x05d: Length of the register GPE1_BLK or X_GPE1_BLK. /
437	uint8_t bGpe1BaseOff; /*< 0x05e: Offset within the ACPI general-purpose event model where GPE1 based events start. /
438	uint8_t bCstCnt; /*< 0x05f: If non-zero, value OSPM writes to the SMI command port to indicate OS support for the _CST object and C States Changed notification. /
439	uint16_t cLvl2LatUs; /*< 0x060: Worst-case latency in microseconds to enter and exit C2 state. /
440	uint16_t cLvl3LatUs; /*< 0x062: Worst-case latency in microseconds to enter and exit C3 state. /
441	uint16_t cFlushStridesSize; /*< 0x064: Number of flush strides needed to be read to flush dirty lines from processor's memory caches. /
442	uint16_t cbFlushStride; /*< 0x066: Cache line width in bytes. /
443	uint8_t bDutyOffset; /*< 0x068: Zero based index of where the processor's duty cycle setting is within the P_CNT register. /
444	uint8_t cBitsDutyWidth; /*< 0x069: The bit width of the processor's duty cacle setting value. /
445	uint8_t bCmosOffRtcDayAlarm; /*< 0x06a: RTC CMOS RAM index to the day-of-month alarm value. /
446	uint8_t bCmosOffRtcMonAlarm; /*< 0x06b: RTC CMOS RAM index to the month of year alarm value. /
447	uint8_t bCmosOffRtcCenturyAlarm; /*< 0x06c: RTC CMOS RAM index to the century data value. /
448	uint16_t fIaPcBootArch; /*< 0x06d: IA-PC Boot Architecture Flags. /
449	uint8_t bRsvd1; /*< 0x06f: Reserved, must be 0. /
450	uint32_t fFeatures; /*< 0x070: Fixed feature flags. /
451	ACPIGAS AddrResetReg; /*< 0x074: Address of the reset register. /
452	uint8_t bResetVal; /*< 0x080: Value to write to the reset register. /
453	uint16_t fArmBootArch; /*< 0x081: ARM Boot Architecture Flags. /
454	uint8_t bFadtVersionMinor; /*< 0x083: FADT minor version. /
455	uint64_t u64AddrXFwCtrl; /*< 0x084: 64-bit physical address of the FACS, where OSPM and Firmware exchange control information. /
456	uint64_t u64AddrXDsdt; /*< 0x08c: 64-bit physical memory address of the DSDT. /
457	ACPIGAS AddrXPm1aEvtBlk; /*< 0x094: Extended address of the PM1a Event Register Block. /
458	ACPIGAS AddrXPm1bEvtBlk; /*< 0x0a0: Extended address of the PM1b Event Register Block. /
459	ACPIGAS AddrXPm1aCntBlk; /*< 0x0ac: Extended address of the PM1a Control Register Block. /
460	ACPIGAS AddrXPm1bCntBlk; /*< 0x0b8: Extended address of the PM1b Control Register Block. /
461	ACPIGAS AddrXPm2bCntBlk; /*< 0x0c4: Extended address of the PM2 Control Register Block. /
462	ACPIGAS AddrXPmTmrBlk; /*< 0x0d0: Extended address of the Power Management Timer Control Register Block. /
463	ACPIGAS AddrXGpe0Blk; /*< 0x0dc: Extended address of the General Purpose Event 0 Register Block. /
464	ACPIGAS AddrXGpe1Blk; /*< 0x0e8: Extended address of the General Purpose Event 1 Register Block. /
465	ACPIGAS AddrSleepCtrlReg; /*< 0x0f4: Extended address of the Sleep Control register. /
466	ACPIGAS AddrSleepStsReg; /*< 0x100: Extended address of the Sleep Status register. /
467	uint64_t u64HypervisorId; /*< 0x10c: 64-bit hypervisor vendor. /
468	} ACPIFADT;
469	#pragma pack()
470	AssertCompileSize(ACPIFADT, 276);
471	/** Pointer to an ACPI Fixed ACPI Description Table. */
472	typedef ACPIFADT *PACPIFADT;
473	/** Pointer to a const ACPI Fixed ACPI Description Table. */
474	typedef const ACPIFADT *PCACPIFADT;
475
476
477	/** The ACPI FADT revision. */
478	#define ACPI_FADT_REVISION 6
479
480
481	/** @name ACPI_FADT_PM_PROFILE_XXX - ACPIFADT::bPreferredPmProfile
482	* @{ */
483	/** Unspecified. */
484	#define ACPI_FADT_PM_PROFILE_UNSPECIFIED 0
485	/** Desktop. */
486	#define ACPI_FADT_PM_PROFILE_DESKTOP 1
487	/** Mobile. */
488	#define ACPI_FADT_PM_PROFILE_MOBILE 2
489	/** Workstation. */
490	#define ACPI_FADT_PM_PROFILE_WORKSTATION 3
491	/** Enterprise Server. */
492	#define ACPI_FADT_PM_PROFILE_ENTERPRISE_SERVER 4
493	/** SOHO Server. */
494	#define ACPI_FADT_PM_PROFILE_SOHO_SERVER 5
495	/** Appliance PC. */
496	#define ACPI_FADT_PM_PROFILE_APPLIANCE_PC 6
497	/** Performance Server. */
498	#define ACPI_FADT_PM_PROFILE_PERFORMANCE_SERVER 7
499	/** Tablet. */
500	#define ACPI_FADT_PM_PROFILE_TABLET 8
501	/** @} */
502
503
504	/** @name ACPI_FADT_IAPC_BOOT_ARCH_F_XXX - ACPIFADT::fIaPcBootArch
505	* @{ */
506	/** Bit 0 - Indicates that the motherboard supports user-visible devices on the LPC or ISA bus if set. */
507	#define ACPI_FADT_IAPC_BOOT_ARCH_F_LEGACY_DEVS RT_BIT(0)
508	/** Bit 1 - Indicates that the motherboard contains support for a port 60 and 64 based keyboard controller. */
509	#define ACPI_FADT_IAPC_BOOT_ARCH_F_8042 RT_BIT(1)
510	/** Bit 2 - Indicates that the OSPM must not blindly probe the VGA hardware. */
511	#define ACPI_FADT_IAPC_BOOT_ARCH_F_NO_VGA RT_BIT(2)
512	/** Bit 3 - Indicates that the OSPM must not enable Message Signaled Interrupts on this platform. */
513	#define ACPI_FADT_IAPC_BOOT_ARCH_F_NO_MSI RT_BIT(3)
514	/** Bit 3 - Indicates that the OSPM must not enable OSPM ASPM on this platform. */
515	#define ACPI_FADT_IAPC_BOOT_ARCH_F_NO_PCIE_ASPM RT_BIT(4)
516	/** Bit 3 - Indicates that the CMOS RTC is either not implemented, or does not exist at legacy addresses. */
517	#define ACPI_FADT_IAPC_BOOT_ARCH_F_NO_RTC_CMOS RT_BIT(5)
518	/** @} */
519
520
521	/** @name ACPI_FADT_F_XXX - ACPIFADT::fFeatures
522	* @{ */
523	/** Bit 0 - Processor properly implements a function equivalent to the WBINVD IA-32 instruction. */
524	#define ACPI_FADT_F_WBINVD RT_BIT_32(0)
525	/** Bit 1 - If set, indicates that the hardware flushes all caches on the WBINVD instruction and maintains memory coherence. */
526	#define ACPI_FADT_F_WBINVD_FLUSH RT_BIT_32(1)
527	/** Bit 2 - Indicates that the C1 power state is supported on all processors. */
528	#define ACPI_FADT_F_C1 RT_BIT_32(2)
529	/** Bit 3 - Indicates that the C2 power state is configured to work on a UP or MP system. */
530	#define ACPI_FADT_F_P_LVL2_UP RT_BIT_32(3)
531	/** Bit 4 - Indicates that the power buttong is handled as a control method device if set. */
532	#define ACPI_FADT_F_POWER_BUTTON RT_BIT_32(4)
533	/** Bit 5 - Indicates that the sleep buttong is handled as a control method device if set. */
534	#define ACPI_FADT_F_SLEEP_BUTTON RT_BIT_32(5)
535	/** Bit 6 - Indicates that the RTC wake status is not supported in fixed register space if set. */
536	#define ACPI_FADT_F_FIX_RTC RT_BIT_32(6)
537	/** Bit 7 - Indicates whether the RTC alarm function can wake the system from the S4 state. */
538	#define ACPI_FADT_F_RTC_S4 RT_BIT_32(7)
539	/** Bit 8 - Indicates that the TMR_VAL is implemented as a 32-bit value if one, 24-bit if 0. */
540	#define ACPI_FADT_F_TMR_VAL_EXT RT_BIT_32(8)
541	/** Bit 9 - Indicates that the system can support docking if set. */
542	#define ACPI_FADT_F_DCK_CAP RT_BIT_32(9)
543	/** Bit 10 - Indicates that the system supports system reset via ACPIFADT::AddrResetReg if set. */
544	#define ACPI_FADT_F_RESET_REG_SUP RT_BIT_32(10)
545	/** Bit 11 - Indicates that the system has no internal expansion capabilities and the case is sealed. */
546	#define ACPI_FADT_F_SEALED_CASE RT_BIT_32(11)
547	/** Bit 12 - Indicates that the system cannot detect the monitor or keyboard/mouse devices. */
548	#define ACPI_FADT_F_HEADLESS RT_BIT_32(12)
549	/** Bit 13 - Indicates that the OSPM needs to execute a processor native instruction after writing the SLP_TYPx register. */
550	#define ACPI_FADT_F_CPU_SW_SLEEP RT_BIT_32(13)
551	/** Bit 14 - Indicates that the platform supports PCIEXP_WAKE_STS bit in the PM1 status register and PCIEXP_WAKE_EN bit in the PM1 enable register. */
552	#define ACPI_FADT_F_PCI_EXP_WAK RT_BIT_32(14)
553	/** Bit 15 - Indicates that the OSPM should use a platform provided timer to drive any monotonically non-decreasing counters. */
554	#define ACPI_FADT_F_USE_PLATFORM_CLOCK RT_BIT_32(15)
555	/** Bit 16 - Indicates that the contents of the RTC_STS flag is valid when waking the system from S4. */
556	#define ACPI_FADT_F_S4_RTC_STS_VALID RT_BIT_32(16)
557	/** Bit 17 - Indicates that the platform is compatible with remote power-on. */
558	#define ACPI_FADT_F_REMOTE_POWER_ON_CAPABLE RT_BIT_32(17)
559	/** Bit 18 - Indicates that all local APICs must be configured for the cluster destination model when delivering interrupts in logical mode. */
560	#define ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL RT_BIT_32(18)
561	/** Bit 19 - Indicates that all local APICs must be configured for physical destination mode. */
562	#define ACPI_FADT_F_FORCE_APIC_PHYS_DEST_MDOE RT_BIT_32(19)
563	/** Bit 20 - Indicates that the Hardware-Reduced ACPI is implemented. */
564	#define ACPI_FADT_F_HW_REDUCED_ACPI RT_BIT_32(20)
565	/** Bit 21 - Indicates that the platform is able to achieve power savings in S0 similar to or better than those typically achieved in S3. */
566	#define ACPI_FADT_F_LOW_POWER_S0_IDLE_CAPABLE RT_BIT_32(21)
567	/** Bit 22 - 23 - Describes whether the CPU caches and any other caches coherent with them, are considered by the platform to be persistent. */
568	#define ACPI_FADT_F_PERSISTENT_CPU_CACHES_MASK (RT_BIT_32(22) \| RT_BIT_32(23))
569	#define ACPI_FADT_F_PERSISTENT_CPU_CACHES_SHIFT 22
570	/** Not reported by the platform. */
571	# define ACPI_FADT_F_PERSISTENT_CPU_CACHES_NOT_REPORTED 0
572	/** CPU caches and any other caches coherent with them are not persistent. */
573	# define ACPI_FADT_F_PERSISTENT_CPU_CACHES_NOT_PERSISTENT 1
574	/** CPU caches and any other caches coherent with them are persistent. */
575	# define ACPI_FADT_F_PERSISTENT_CPU_CACHES_PERSISTENT 2
576	/** Reserved. */
577	# define ACPI_FADT_F_PERSISTENT_CPU_CACHES_RESERVED 3
578	/** @} */
579
580
581	/** @name ACPI_FADT_ARM_BOOT_ARCH_F_XXX - ACPIFADT::fArmBootArch
582	* @{ */
583	/** Bit 0 - Indicates that PSCI is implemented if set. */
584	#define ACPI_FADT_ARM_BOOT_ARCH_F_PSCI_COMP RT_BIT(0)
585	/** Bit 1 - Indicates that the HVC must be used as the PSCI conduit instead of SMC. */
586	#define ACPI_FADT_ARM_BOOT_ARCH_F_PSCI_USE_HVC RT_BIT(1)
587	/** @} */
588
589
590	/**
591	* Generic Timer Description Table (ACPIGTDT)
592	*
593	* @see @acpi65{05_ACPI_Software_Programming_Model,generic-timer-description-table-gtdt}
594	*/
595	#pragma pack(1)
596	typedef struct ACPIGTDT
597	{
598	ACPITBLHDR Hdr; /*< 0x000: The table header. /
599	uint64_t u64PhysAddrCntControlBase; /*< 0x024: The 64-bit physical address at which the Counter Control block is located, 0xffffffffffffffff if not provied. /
600	uint32_t u32Rsvd; /*< 0x02c: Reserved. /
601	uint32_t u32El1SecTimerGsiv; /*< 0x030: GSIV of the secure EL1 timer, optional. /
602	uint32_t fEl1SecTimer; /*< 0x034: Secure EL1 timer flags, optional. Combination of ACPI_GTDT_TIMER_F_XXX. /
603	uint32_t u32El1NonSecTimerGsiv; /*< 0x038: GSIV of the non-secure EL1 timer, optional. /
604	uint32_t fEl1NonSecTimer; /*< 0x03c: Non-Secure EL1 timer flags, optional. Combination of ACPI_GTDT_TIMER_F_XXX. /
605	uint32_t u32El1VirtTimerGsiv; /*< 0x040: GSIV of the virtual EL1 timer, optional. /
606	uint32_t fEl1VirtTimer; /*< 0x044: Virtual EL1 timer flags, optional. Combination of ACPI_GTDT_TIMER_F_XXX. /
607	uint32_t u32El2TimerGsiv; /*< 0x048: GSIV of the EL2 timer, optional. /
608	uint32_t fEl2Timer; /*< 0x04c: EL2 timer flags, optional. Combination of ACPI_GTDT_TIMER_F_XXX. /
609	uint64_t u64PhysAddrCndReadBase; /*< 0x050: The 64-bit physical address at which the Counter Read block is located, 0xffffffffffffffff if not provied. /
610	uint32_t cPlatformTimers; /*< 0x058: Number of entries in the plaform timer structure array. /
611	uint32_t offPlatformTimers; /*< 0x05c: Offset to the platform timer structure array from the start of this table. /
612	uint32_t u32El2VirtTimerGsiv; /*< 0x060: GSIV of the virtual EL2 timer, optional. /
613	uint32_t fEl2VirtTimer; /*< 0x064: Virtual EL2 timer flags, optional. Combination of ACPI_GTDT_TIMER_F_XXX. /
614	} ACPIGTDT;
615	#pragma pack()
616	AssertCompileSize(ACPIGTDT, 104);
617	/** Pointer to an ACPI Fixed ACPI Description Table. */
618	typedef ACPIGTDT *PACPIGTDT;
619	/** Pointer to a const ACPI Fixed ACPI Description Table. */
620	typedef const ACPIGTDT *PCACPIGTDT;
621
622
623	/** @name ACPI_GTDT_TIMER_F_XXX - ACPIGTDT::fEl1SecTimer, ACPIGTDT::fEl1NonSecTimer, ACPIGTDT::fEl1VirtTimer,
624	* ACPIGTDT::fEl2Timer, ACPIGTDT::fEl2VirtTimer
625	* @{ */
626	/** Bit 0 - Interrupt mode, level triggered. */
627	#define ACPI_GTDT_TIMER_F_INTR_MODE_LEVEL 0
628	/** Bit 0 - Interrupt mode, edge triggered. */
629	#define ACPI_GTDT_TIMER_F_INTR_MODE_EDGE RT_BIT_32(0)
630	/** Bit 1 - Interrupt polarity, active high. */
631	#define ACPI_GTDT_TIMER_F_INTR_POLARITY_ACTIVE_HIGH 0
632	/** Bit 1 - Interrupt polarity, active low. */
633	#define ACPI_GTDT_TIMER_F_INTR_POLARITY_ACTIVE_LOW RT_BIT_32(1)
634	/** Bit 2 - Timer is always active independent of the processor's power state,
635	* if clear the timer may lose context or not assert interrupts if the processor is in a low power state. */
636	#define ACPI_GTDT_TIMER_F_ALWAYS_ON_CAP RT_BIT_32(0)
637	/** @} */
638
639	/** @todo GT Block structure and Watchdog timer structure. */
640
641
642	/**
643	* Multiple APIC Description Table (ACPIMADT)
644	*
645	* @see @acpi65{05_ACPI_Software_Programming_Model,multiple-apic-description-table-madt}
646	*/
647	#pragma pack(1)
648	typedef struct ACPIMADT
649	{
650	ACPITBLHDR Hdr; /*< 0x000: The table header. /
651	uint32_t u32PhysAddrLocalIntrCtrl; /*< 0x024: The 32-bit physical address at which each processor can access its local interrupt controller. /
652	uint32_t fApic; /*< 0x028: Multiple APIC flags. Combination of ACPI_MADT_APIC_F_XXX. /
653	/* Variable number of interrupt controller structures follows. */
654	} ACPIMADT;
655	#pragma pack()
656	AssertCompileSize(ACPIMADT, 44);
657	/** Pointer to an ACPI Multiple APIC Description Table. */
658	typedef ACPIMADT *PACPIMADT;
659	/** Pointer to a const ACPI Multiple APIC Description Table. */
660	typedef const ACPIMADT *PCACPIMADT;
661
662
663	/** @name ACPI_MADT_APIC_F_XXX - ACPIMADT::fApic
664	* @{ */
665	/** Bit 0 - Indicates that the system has a PC-AT compatible dual 8259 setup. */
666	#define ACPI_MADT_APIC_F_PCAT_COMPAT RT_BIT_32(0)
667	/** @} */
668
669
670	/** @name ACPI_MADT_INTR_CTRL_TYPE_XXX - Interrupt Controller Structure Types.
671	* @{ */
672	/** Processor Local APIC. */
673	#define ACPI_MADT_INTR_CTRL_TYPE_PROCESSOR_LOCAL_APIC 0
674	/** I/O APIC. */
675	#define ACPI_MADT_INTR_CTRL_TYPE_IO_APIC 1
676	/** Interrupt source override. */
677	#define ACPI_MADT_INTR_CTRL_TYPE_INTR_SRC_OVERRIDE 2
678	/** Non-maskable Interrupt (NMI) Source. */
679	#define ACPI_MADT_INTR_CTRL_TYPE_NMI 3
680	/** Local APIC NMI. */
681	#define ACPI_MADT_INTR_CTRL_TYPE_LOCAL_APIC_NMI 4
682	/** Local APIC address override. */
683	#define ACPI_MADT_INTR_CTRL_TYPE_LOCAL_APIC_ADDR_OVERRIDE 5
684	/** I/O SAPIC. */
685	#define ACPI_MADT_INTR_CTRL_TYPE_IO_SAPIC 6
686	/** Local SAPIC. */
687	#define ACPI_MADT_INTR_CTRL_TYPE_LOCAL_SAPIC 7
688	/** Platform interrupt sources. */
689	#define ACPI_MADT_INTR_CTRL_TYPE_PLATFORM_INTR_SRCS 8
690	/** Processor Local x2APIC. */
691	#define ACPI_MADT_INTR_CTRL_TYPE_PROCESSOR_LOCAL_X2APIC 9
692	/** Local x2APIC NMI. */
693	#define ACPI_MADT_INTR_CTRL_TYPE_LOCAL_X2APIC_NMI 10
694	/** GIC CPU Interface (GICC). */
695	#define ACPI_MADT_INTR_CTRL_TYPE_GICC 11
696	/** GIC Distributor (GICD). */
697	#define ACPI_MADT_INTR_CTRL_TYPE_GICD 12
698	/** GIC MSI Frame. */
699	#define ACPI_MADT_INTR_CTRL_TYPE_GIC_MSI_FRAME 13
700	/** GIC Redistributor (GICR). */
701	#define ACPI_MADT_INTR_CTRL_TYPE_GICR 14
702	/** GIC Interrupt Translation Service (ITS). */
703	#define ACPI_MADT_INTR_CTRL_TYPE_GIC_ITS 15
704	/** @} */
705
706
707	/**
708	* GIC CPU Interface (GICC) Structure.
709	*
710	* @see @acpi65{05_ACPI_Software_Programming_Model,gic-cpu-interface-gicc-structure}
711	*/
712	#pragma pack(1)
713	typedef struct ACPIMADTGICC
714	{
715	uint8_t bType; /*< 0x000: The GICC structure type, ACPI_MADT_INTR_CTRL_TYPE_GICC. /
716	uint8_t cbThis; /*< 0x001: Length of this structure, 82. /
717	uint16_t u16Rsvd0; /*< 0x002: Reserved, MBZ. /
718	uint32_t u32CpuId; /*< 0x004: GIC's CPU Interface Number. /
719	uint32_t u32AcpiCpuUid; /*< 0x008: The matching processor object's _UID return value for this structure. /
720	uint32_t fGicc; /*< 0x00c: GICC CPU interface flags, see ACPI_MADT_GICC_F_XXX. /
721	uint32_t u32ParkingProtocolVersion; /*< 0x010: Version of the ARM-Processor Parking Protocol implemented. /
722	uint32_t u32PerformanceGsiv; /*< 0x014: The GSIV used for performance monitoring interrupts. /
723	uint64_t u64PhysAddrParked; /*< 0x018: The 64-bit physical address of the processor's parking protocol mailbox. /
724	uint64_t u64PhysAddrBase; /*< 0x020: Physical address at which the CPU can access the GIC CPU interface. /
725	uint64_t u64PhysAddrGicv; /*< 0x028: Address of the GIC virtual CPU interface registers. 0 if not present. /
726	uint64_t u64PhysAddrGich; /*< 0x030: Address of the GIC virtual interface control block registers. 0 if not present. /
727	uint32_t u32VGicMaintenanceGsiv; /*< 0x038: GSIV for the Virtual GIC maintenance interrupt. /
728	uint64_t u64PhysAddrGicrBase; /*< 0x03c: On GICv3+ holds the 64-bit physical address of the associated redistributor. /
729	uint64_t u64Mpidr; /*< 0x044: Matches the MPIDR register of the CPU associated with this structure. /
730	uint8_t bCpuEfficiencyClass; /*< 0x04c: Describes the relative power efficiency of the associated processor. /
731	uint8_t bRsvd1; /*< 0x04d: Reserved, MBZ. /
732	uint16_t u16SpeOverflowGsiv; /*< 0x04e: Statistical Profiling Extension buffer overflow GSIV, level triggered PPI. /
733	uint16_t u16TrbeGsiv; /*< 0x050: Trace Buffer Extension interrupt GSIV, level triggered PPI. /
734	} ACPIMADTGICC;
735	#pragma pack()
736	AssertCompileSize(ACPIMADTGICC, 82);
737	/** Pointer to an GIC CPU Interface (GICC) Structure. */
738	typedef ACPIMADTGICC *PACPIMADTGICC;
739	/** Pointer to a const GIC CPU Interface (GICC) Structure. */
740	typedef const ACPIMADTGICC *PCACPIMADTGICC;
741
742
743	/** @name ACPI_MADT_GICC_F_XXX - ACPIMADTGICC::fGicc
744	* @{ */
745	/** Bit 0 - If set the processor is ready for use. */
746	#define ACPI_MADT_GICC_F_ENABLED RT_BIT_32(0)
747	/** Bit 1 - The performance interrupt is edge triggered, if 0 level triggered. */
748	#define ACPI_MADT_GICC_F_PERF_INTR_MODE_EDGE RT_BIT_32(1)
749	/** Bit 2 - The VGIC maintenance interrupt is edge triggered, if 0 level triggered. */
750	#define ACPI_MADT_GICC_F_VGIC_MAINTENANCE_INTR_MODE_EDGE RT_BIT_32(2)
751	/** Bit 3 - System supports enabling this processor later during OS runtime. */
752	#define ACPI_MADT_GICC_F_ONLINE_CAPABLE RT_BIT_32(3)
753	/** @} */
754
755
756	/**
757	* GIC Distributor Interface (GICD) Structure.
758	*
759	* @see @acpi65{05_ACPI_Software_Programming_Model,gic-distributor-gicd-structure}
760	*/
761	#pragma pack(1)
762	typedef struct ACPIMADTGICD
763	{
764	uint8_t bType; /*< 0x000: The GICD structure type, ACPI_MADT_INTR_CTRL_TYPE_GICD. /
765	uint8_t cbThis; /*< 0x001: Length of this structure, 24. /
766	uint16_t u16Rsvd0; /*< 0x002: Reserved, MBZ. /
767	uint32_t u32GicdId; /*< 0x004: This GIC distributor's hardware ID. /
768	uint64_t u64PhysAddrBase; /*< 0x008: The 64-bit physical address for this distributor. /
769	uint32_t u32SystemVectorBase; /*< 0x010: Reserved, MBZ. /
770	uint8_t bGicVersion; /*< 0x014: GIC version, ACPI_MADT_GICD_VERSION_XXX. /
771	uint8_t abRsvd0[3]; /*< 0x015: Reserved, MBZ. /
772	} ACPIMADTGICD;
773	#pragma pack()
774	AssertCompileSize(ACPIMADTGICD, 24);
775	/** Pointer to an GIC Distributor Interface (GICD) Structure. */
776	typedef ACPIMADTGICD *PACPIMADTGICD;
777	/** Pointer to a const GIC Distributor Interface (GICD) Structure. */
778	typedef const ACPIMADTGICD *PCACPIMADTGICD;
779
780
781	/** @name ACPI_MADT_GICD_VERSION_XXX - ACPIMADTGICD::bGicVersion
782	* @{ */
783	/** No GIC version is specified, fall back to hardware discovery for GIC version. */
784	#define ACPI_MADT_GICD_VERSION_UNSPECIFIED 0
785	/** GICv1. */
786	#define ACPI_MADT_GICD_VERSION_GICv1 1
787	/** GICv2. */
788	#define ACPI_MADT_GICD_VERSION_GICv2 2
789	/** GICv3. */
790	#define ACPI_MADT_GICD_VERSION_GICv3 3
791	/** GICv4. */
792	#define ACPI_MADT_GICD_VERSION_GICv4 4
793	/** @} */
794
795
796	/** @todo GIC MSI Frame Structure. */
797
798
799	/**
800	* GIC Redistributor (GICR) Structure.
801	*
802	* @see @acpi65{05_ACPI_Software_Programming_Model,gic-redistributor-gicr-structure}
803	*/
804	#pragma pack(1)
805	typedef struct ACPIMADTGICR
806	{
807	uint8_t bType; /*< 0x000: The GICR structure type, ACPI_MADT_INTR_CTRL_TYPE_GICR. /
808	uint8_t cbThis; /*< 0x001: Length of this structure, 16. /
809	uint16_t u16Rsvd0; /*< 0x002: Reserved, MBZ. /
810	uint64_t u64PhysAddrGicrRangeBase; /*< 0x004: The 64-bit physical address of a page range containing all GIC Redistributors. /
811	uint32_t cbGicrRange; /*< 0x00c: The length of the GIC Redistributor discovery page range. /
812	} ACPIMADTGICR;
813	#pragma pack()
814	AssertCompileSize(ACPIMADTGICR, 16);
815	/** Pointer to an GIC Redistributor (GICR) Structure. */
816	typedef ACPIMADTGICR *PACPIMADTGICR;
817	/** Pointer to a const GIC Redistributor (GICR) Structure. */
818	typedef const ACPIMADTGICR *PCACPIMADTGICR;
819
820
821	/**
822	* GIC Interrupt Translation Service (ITS) Structure.
823	*
824	* @see @acpi65{05_ACPI_Software_Programming_Model,gic-interrupt-translation-service-its-structure}
825	*/
826	#pragma pack(1)
827	typedef struct ACPIMADTGICITS
828	{
829	uint8_t bType; /*< 0x000: The GICR structure type, ACPI_MADT_INTR_CTRL_TYPE_GICR. /
830	uint8_t cbThis; /*< 0x001: Length of this structure, 16. /
831	uint16_t u16Rsvd0; /*< 0x002: Reserved, MBZ. /
832	uint32_t u32GicItsId; /*< 0x004: This GIC ITS ID. /
833	uint64_t u64PhysAddrBase; /*< 0x008: The 64-bit physical address for the Interrupt Translation Service. /
834	uint32_t u32Rsvd1; /*< 0x010: Rserved, MBZ. /
835	} ACPIMADTGICITS;
836	#pragma pack()
837	AssertCompileSize(ACPIMADTGICITS, 20);
838	/** Pointer to an GIC Interrupt Translation Service (ITS) Structure. */
839	typedef ACPIMADTGICITS *PACPIMADTGICITS;
840	/** Pointer to a const GIC Interrupt Translation Service (ITS) Structure. */
841	typedef const ACPIMADTGICITS *PCACPIMADTGICITS;
842
843
844	/**
845	* Memory Mapped Configuration Space base address description table (MCFG). (part of the PCI Express spec).
846	*/
847	#pragma pack(1)
848	typedef struct ACPIMCFG
849	{
850	ACPITBLHDR Hdr; /*< 0x000: The table header. /
851	uint64_t u64Rsvd0; /*< 0x024: Reserved, MBZ. /
852	/* Variable number of base address allocation structures follows. */
853	} ACPIMCFG;
854	#pragma pack()
855	AssertCompileSize(ACPIMCFG, 44);
856	/** Pointer to an ACPI MCFG Table. */
857	typedef ACPIMCFG *PACPIMCFG;
858	/** Pointer to a const ACPI MCFG Table. */
859	typedef const ACPIMCFG *PCACPIMCFG;
860
861
862	/**
863	* MCFG allocation structure.
864	*/
865	#pragma pack(1)
866	typedef struct ACPIMCFGALLOC
867	{
868	uint64_t u64PhysAddrBase; /*< 0x000: Base address of the enhanced configuration mechanism. /
869	uint16_t u16PciSegGrpNr; /*< 0x008: PCI segment group number. /
870	uint8_t bPciBusFirst; /*< 0x00a: First PCI bus number decoded by this PCI host bridge. /
871	uint8_t bPciBusLast; /*< 0x00b: Last PCI bus number decoded by this PCI host bridge. /
872	uint32_t u32Rsvd0; /*< 0x00c: Reserved, MBZ. /
873	} ACPIMCFGALLOC;
874	#pragma pack()
875	AssertCompileSize(ACPIMCFGALLOC, 16);
876	/** Pointer to an ACPI MCFG Table. */
877	typedef ACPIMCFGALLOC *PACPIMCFGALLOC;
878	/** Pointer to a const ACPI MCFG Table. */
879	typedef const ACPIMCFGALLOC *PCACPIMCFGALLOC;
880
881
882	/**
883	* TPM: The ACPI table for a TPM 2.0 device
884	* (from: https://trustedcomputinggroup.org/wp-content/uploads/TCG_ACPIGeneralSpec_v1p3_r8_pub.pdf).
885	*/
886	#pragma pack(1)
887	typedef struct ACPITPM20
888	{
889	/** The common ACPI table header. */
890	ACPITBLHDR Hdr;
891	/** The platform class. */
892	uint16_t u16PlatCls;
893	/** Reserved. */
894	uint16_t u16Rsvd0;
895	/** Address of the CRB control area or FIFO base address. */
896	uint64_t u64BaseAddrCrbOrFifo;
897	/** The start method selector. */
898	uint32_t u32StartMethod;
899	/** Following are start method specific parameters and optional LAML and LASA fields we don't implement right now. */
900	/** @todo */
901	} ACPITPM20;
902	AssertCompileSize(ACPITPM20, 52);
903	#pragma pack()
904
905	/** Revision of the TPM2.0 ACPI table. */
906	#define ACPI_TPM20_REVISION 4
907
908
909	/** @name Possible values for the ACPITPM20::u16PlatCls member.
910	* @{ */
911	/** Client platform. */
912	#define ACPITBL_TPM20_PLAT_CLS_CLIENT UINT16_C(0)
913	/** Server platform. */
914	#define ACPITBL_TPM20_PLAT_CLS_SERVER UINT16_C(1)
915	/** @} */
916
917
918	/** @name Possible values for the ACPITPM20::u32StartMethod member.
919	* @{ */
920	/** MMIO interface (TIS1.2+Cancel). */
921	#define ACPITBL_TPM20_START_METHOD_TIS12 UINT16_C(6)
922	/** CRB interface. */
923	#define ACPITBL_TPM20_START_METHOD_CRB UINT16_C(7)
924	/** @} */
925
926
927	/** @} */
928
929	#endif /* !IPRT_INCLUDED_formats_acpi_tables_h */
930

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source: vbox/trunk/include/iprt/formats/acpi-tables.h

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