VirtualBox

source: vbox/trunk/include/iprt/asm-amd64-x86.h@ 57220

Last change on this file since 57220 was 57220, checked in by vboxsync, 9 years ago

SUPDrv,asm-amd64-x86.h: More EFLAGS.AC checks.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 72.8 KB
Line 
1/** @file
2 * IPRT - AMD64 and x86 Specific Assembly Functions.
3 */
4
5/*
6 * Copyright (C) 2006-2015 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___iprt_asm_amd64_x86_h
27#define ___iprt_asm_amd64_x86_h
28
29#include <iprt/types.h>
30#include <iprt/assert.h>
31#if !defined(RT_ARCH_AMD64) && !defined(RT_ARCH_X86)
32# error "Not on AMD64 or x86"
33#endif
34
35#if defined(_MSC_VER) && RT_INLINE_ASM_USES_INTRIN
36# include <intrin.h>
37 /* Emit the intrinsics at all optimization levels. */
38# pragma intrinsic(_ReadWriteBarrier)
39# pragma intrinsic(__cpuid)
40# pragma intrinsic(_enable)
41# pragma intrinsic(_disable)
42# pragma intrinsic(__rdtsc)
43# pragma intrinsic(__readmsr)
44# pragma intrinsic(__writemsr)
45# pragma intrinsic(__outbyte)
46# pragma intrinsic(__outbytestring)
47# pragma intrinsic(__outword)
48# pragma intrinsic(__outwordstring)
49# pragma intrinsic(__outdword)
50# pragma intrinsic(__outdwordstring)
51# pragma intrinsic(__inbyte)
52# pragma intrinsic(__inbytestring)
53# pragma intrinsic(__inword)
54# pragma intrinsic(__inwordstring)
55# pragma intrinsic(__indword)
56# pragma intrinsic(__indwordstring)
57# pragma intrinsic(__invlpg)
58# pragma intrinsic(__wbinvd)
59# pragma intrinsic(__readcr0)
60# pragma intrinsic(__readcr2)
61# pragma intrinsic(__readcr3)
62# pragma intrinsic(__readcr4)
63# pragma intrinsic(__writecr0)
64# pragma intrinsic(__writecr3)
65# pragma intrinsic(__writecr4)
66# pragma intrinsic(__readdr)
67# pragma intrinsic(__writedr)
68# ifdef RT_ARCH_AMD64
69# pragma intrinsic(__readcr8)
70# pragma intrinsic(__writecr8)
71# endif
72# if RT_INLINE_ASM_USES_INTRIN >= 15
73# pragma intrinsic(__readeflags)
74# pragma intrinsic(__writeeflags)
75# pragma intrinsic(__rdtscp)
76# endif
77#endif
78
79
80
81/** @defgroup grp_rt_asm_amd64_x86 AMD64 and x86 Specific ASM Routines
82 * @ingroup grp_rt_asm
83 * @{
84 */
85
86/** @todo find a more proper place for these structures? */
87
88#pragma pack(1)
89/** IDTR */
90typedef struct RTIDTR
91{
92 /** Size of the IDT. */
93 uint16_t cbIdt;
94 /** Address of the IDT. */
95 uintptr_t pIdt;
96} RTIDTR, *PRTIDTR;
97#pragma pack()
98
99#pragma pack(1)
100/** @internal */
101typedef struct RTIDTRALIGNEDINT
102{
103 /** Alignment padding. */
104 uint8_t au16Padding[ARCH_BITS == 64 ? 3 : 1];
105 /** The IDTR structure. */
106 RTIDTR Idtr;
107} RTIDTRALIGNEDINT;
108#pragma pack()
109
110/** Wrapped RTIDTR for preventing misalignment exceptions. */
111typedef union RTIDTRALIGNED
112{
113 /** Try make sure this structure has optimal alignment. */
114 uint64_t auAlignmentHack[ARCH_BITS == 64 ? 2 : 1];
115 /** Aligned structure. */
116 RTIDTRALIGNEDINT s;
117} RTIDTRALIGNED;
118AssertCompileSize(RTIDTRALIGNED, ARCH_BITS * 2 / 8);
119/** Pointer to a an RTIDTR alignment wrapper. */
120typedef RTIDTRALIGNED *PRIDTRALIGNED;
121
122
123#pragma pack(1)
124/** GDTR */
125typedef struct RTGDTR
126{
127 /** Size of the GDT. */
128 uint16_t cbGdt;
129 /** Address of the GDT. */
130 uintptr_t pGdt;
131} RTGDTR, *PRTGDTR;
132#pragma pack()
133
134#pragma pack(1)
135/** @internal */
136typedef struct RTGDTRALIGNEDINT
137{
138 /** Alignment padding. */
139 uint8_t au16Padding[ARCH_BITS == 64 ? 3 : 1];
140 /** The GDTR structure. */
141 RTGDTR Gdtr;
142} RTGDTRALIGNEDINT;
143#pragma pack()
144
145/** Wrapped RTGDTR for preventing misalignment exceptions. */
146typedef union RTGDTRALIGNED
147{
148 /** Try make sure this structure has optimal alignment. */
149 uint64_t auAlignmentHack[ARCH_BITS == 64 ? 2 : 1];
150 /** Aligned structure. */
151 RTGDTRALIGNEDINT s;
152} RTGDTRALIGNED;
153AssertCompileSize(RTGDTRALIGNED, ARCH_BITS * 2 / 8);
154/** Pointer to a an RTGDTR alignment wrapper. */
155typedef RTGDTRALIGNED *PRGDTRALIGNED;
156
157
158/**
159 * Gets the content of the IDTR CPU register.
160 * @param pIdtr Where to store the IDTR contents.
161 */
162#if RT_INLINE_ASM_EXTERNAL
163DECLASM(void) ASMGetIDTR(PRTIDTR pIdtr);
164#else
165DECLINLINE(void) ASMGetIDTR(PRTIDTR pIdtr)
166{
167# if RT_INLINE_ASM_GNU_STYLE
168 __asm__ __volatile__("sidt %0" : "=m" (*pIdtr));
169# else
170 __asm
171 {
172# ifdef RT_ARCH_AMD64
173 mov rax, [pIdtr]
174 sidt [rax]
175# else
176 mov eax, [pIdtr]
177 sidt [eax]
178# endif
179 }
180# endif
181}
182#endif
183
184
185/**
186 * Gets the content of the IDTR.LIMIT CPU register.
187 * @returns IDTR limit.
188 */
189#if RT_INLINE_ASM_EXTERNAL
190DECLASM(uint16_t) ASMGetIdtrLimit(void);
191#else
192DECLINLINE(uint16_t) ASMGetIdtrLimit(void)
193{
194 RTIDTRALIGNED TmpIdtr;
195# if RT_INLINE_ASM_GNU_STYLE
196 __asm__ __volatile__("sidt %0" : "=m" (TmpIdtr.s.Idtr));
197# else
198 __asm
199 {
200 sidt [TmpIdtr.s.Idtr]
201 }
202# endif
203 return TmpIdtr.s.Idtr.cbIdt;
204}
205#endif
206
207
208/**
209 * Sets the content of the IDTR CPU register.
210 * @param pIdtr Where to load the IDTR contents from
211 */
212#if RT_INLINE_ASM_EXTERNAL
213DECLASM(void) ASMSetIDTR(const RTIDTR *pIdtr);
214#else
215DECLINLINE(void) ASMSetIDTR(const RTIDTR *pIdtr)
216{
217# if RT_INLINE_ASM_GNU_STYLE
218 __asm__ __volatile__("lidt %0" : : "m" (*pIdtr));
219# else
220 __asm
221 {
222# ifdef RT_ARCH_AMD64
223 mov rax, [pIdtr]
224 lidt [rax]
225# else
226 mov eax, [pIdtr]
227 lidt [eax]
228# endif
229 }
230# endif
231}
232#endif
233
234
235/**
236 * Gets the content of the GDTR CPU register.
237 * @param pGdtr Where to store the GDTR contents.
238 */
239#if RT_INLINE_ASM_EXTERNAL
240DECLASM(void) ASMGetGDTR(PRTGDTR pGdtr);
241#else
242DECLINLINE(void) ASMGetGDTR(PRTGDTR pGdtr)
243{
244# if RT_INLINE_ASM_GNU_STYLE
245 __asm__ __volatile__("sgdt %0" : "=m" (*pGdtr));
246# else
247 __asm
248 {
249# ifdef RT_ARCH_AMD64
250 mov rax, [pGdtr]
251 sgdt [rax]
252# else
253 mov eax, [pGdtr]
254 sgdt [eax]
255# endif
256 }
257# endif
258}
259#endif
260
261
262/**
263 * Sets the content of the GDTR CPU register.
264 * @param pIdtr Where to load the GDTR contents from
265 */
266#if RT_INLINE_ASM_EXTERNAL
267DECLASM(void) ASMSetGDTR(const RTGDTR *pGdtr);
268#else
269DECLINLINE(void) ASMSetGDTR(const RTGDTR *pGdtr)
270{
271# if RT_INLINE_ASM_GNU_STYLE
272 __asm__ __volatile__("lgdt %0" : : "m" (*pGdtr));
273# else
274 __asm
275 {
276# ifdef RT_ARCH_AMD64
277 mov rax, [pGdtr]
278 lgdt [rax]
279# else
280 mov eax, [pGdtr]
281 lgdt [eax]
282# endif
283 }
284# endif
285}
286#endif
287
288
289
290/**
291 * Get the cs register.
292 * @returns cs.
293 */
294#if RT_INLINE_ASM_EXTERNAL
295DECLASM(RTSEL) ASMGetCS(void);
296#else
297DECLINLINE(RTSEL) ASMGetCS(void)
298{
299 RTSEL SelCS;
300# if RT_INLINE_ASM_GNU_STYLE
301 __asm__ __volatile__("movw %%cs, %0\n\t" : "=r" (SelCS));
302# else
303 __asm
304 {
305 mov ax, cs
306 mov [SelCS], ax
307 }
308# endif
309 return SelCS;
310}
311#endif
312
313
314/**
315 * Get the DS register.
316 * @returns DS.
317 */
318#if RT_INLINE_ASM_EXTERNAL
319DECLASM(RTSEL) ASMGetDS(void);
320#else
321DECLINLINE(RTSEL) ASMGetDS(void)
322{
323 RTSEL SelDS;
324# if RT_INLINE_ASM_GNU_STYLE
325 __asm__ __volatile__("movw %%ds, %0\n\t" : "=r" (SelDS));
326# else
327 __asm
328 {
329 mov ax, ds
330 mov [SelDS], ax
331 }
332# endif
333 return SelDS;
334}
335#endif
336
337
338/**
339 * Get the ES register.
340 * @returns ES.
341 */
342#if RT_INLINE_ASM_EXTERNAL
343DECLASM(RTSEL) ASMGetES(void);
344#else
345DECLINLINE(RTSEL) ASMGetES(void)
346{
347 RTSEL SelES;
348# if RT_INLINE_ASM_GNU_STYLE
349 __asm__ __volatile__("movw %%es, %0\n\t" : "=r" (SelES));
350# else
351 __asm
352 {
353 mov ax, es
354 mov [SelES], ax
355 }
356# endif
357 return SelES;
358}
359#endif
360
361
362/**
363 * Get the FS register.
364 * @returns FS.
365 */
366#if RT_INLINE_ASM_EXTERNAL
367DECLASM(RTSEL) ASMGetFS(void);
368#else
369DECLINLINE(RTSEL) ASMGetFS(void)
370{
371 RTSEL SelFS;
372# if RT_INLINE_ASM_GNU_STYLE
373 __asm__ __volatile__("movw %%fs, %0\n\t" : "=r" (SelFS));
374# else
375 __asm
376 {
377 mov ax, fs
378 mov [SelFS], ax
379 }
380# endif
381 return SelFS;
382}
383# endif
384
385
386/**
387 * Get the GS register.
388 * @returns GS.
389 */
390#if RT_INLINE_ASM_EXTERNAL
391DECLASM(RTSEL) ASMGetGS(void);
392#else
393DECLINLINE(RTSEL) ASMGetGS(void)
394{
395 RTSEL SelGS;
396# if RT_INLINE_ASM_GNU_STYLE
397 __asm__ __volatile__("movw %%gs, %0\n\t" : "=r" (SelGS));
398# else
399 __asm
400 {
401 mov ax, gs
402 mov [SelGS], ax
403 }
404# endif
405 return SelGS;
406}
407#endif
408
409
410/**
411 * Get the SS register.
412 * @returns SS.
413 */
414#if RT_INLINE_ASM_EXTERNAL
415DECLASM(RTSEL) ASMGetSS(void);
416#else
417DECLINLINE(RTSEL) ASMGetSS(void)
418{
419 RTSEL SelSS;
420# if RT_INLINE_ASM_GNU_STYLE
421 __asm__ __volatile__("movw %%ss, %0\n\t" : "=r" (SelSS));
422# else
423 __asm
424 {
425 mov ax, ss
426 mov [SelSS], ax
427 }
428# endif
429 return SelSS;
430}
431#endif
432
433
434/**
435 * Get the TR register.
436 * @returns TR.
437 */
438#if RT_INLINE_ASM_EXTERNAL
439DECLASM(RTSEL) ASMGetTR(void);
440#else
441DECLINLINE(RTSEL) ASMGetTR(void)
442{
443 RTSEL SelTR;
444# if RT_INLINE_ASM_GNU_STYLE
445 __asm__ __volatile__("str %w0\n\t" : "=r" (SelTR));
446# else
447 __asm
448 {
449 str ax
450 mov [SelTR], ax
451 }
452# endif
453 return SelTR;
454}
455#endif
456
457
458/**
459 * Get the LDTR register.
460 * @returns LDTR.
461 */
462#if RT_INLINE_ASM_EXTERNAL
463DECLASM(RTSEL) ASMGetLDTR(void);
464#else
465DECLINLINE(RTSEL) ASMGetLDTR(void)
466{
467 RTSEL SelLDTR;
468# if RT_INLINE_ASM_GNU_STYLE
469 __asm__ __volatile__("sldt %w0\n\t" : "=r" (SelLDTR));
470# else
471 __asm
472 {
473 sldt ax
474 mov [SelLDTR], ax
475 }
476# endif
477 return SelLDTR;
478}
479#endif
480
481
482/**
483 * Get the access rights for the segment selector.
484 *
485 * @returns The access rights on success or UINT32_MAX on failure.
486 * @param uSel The selector value.
487 *
488 * @remarks Using UINT32_MAX for failure is chosen because valid access rights
489 * always have bits 0:7 as 0 (on both Intel & AMD).
490 */
491#if RT_INLINE_ASM_EXTERNAL
492DECLASM(uint32_t) ASMGetSegAttr(uint32_t uSel);
493#else
494DECLINLINE(uint32_t) ASMGetSegAttr(uint32_t uSel)
495{
496 uint32_t uAttr;
497 /* LAR only accesses 16-bit of the source operand, but eax for the
498 destination operand is required for getting the full 32-bit access rights. */
499# if RT_INLINE_ASM_GNU_STYLE
500 __asm__ __volatile__("lar %1, %%eax\n\t"
501 "jz done%=\n\t"
502 "movl $0xffffffff, %%eax\n\t"
503 "done%=:\n\t"
504 "movl %%eax, %0\n\t"
505 : "=r" (uAttr)
506 : "r" (uSel)
507 : "cc", "%eax");
508# else
509 __asm
510 {
511 lar eax, [uSel]
512 jz done
513 mov eax, 0ffffffffh
514 done:
515 mov [uAttr], eax
516 }
517# endif
518 return uAttr;
519}
520#endif
521
522
523/**
524 * Get the [RE]FLAGS register.
525 * @returns [RE]FLAGS.
526 */
527#if RT_INLINE_ASM_EXTERNAL && RT_INLINE_ASM_USES_INTRIN < 15
528DECLASM(RTCCUINTREG) ASMGetFlags(void);
529#else
530DECLINLINE(RTCCUINTREG) ASMGetFlags(void)
531{
532 RTCCUINTREG uFlags;
533# if RT_INLINE_ASM_GNU_STYLE
534# ifdef RT_ARCH_AMD64
535 __asm__ __volatile__("pushfq\n\t"
536 "popq %0\n\t"
537 : "=r" (uFlags));
538# else
539 __asm__ __volatile__("pushfl\n\t"
540 "popl %0\n\t"
541 : "=r" (uFlags));
542# endif
543# elif RT_INLINE_ASM_USES_INTRIN >= 15
544 uFlags = __readeflags();
545# else
546 __asm
547 {
548# ifdef RT_ARCH_AMD64
549 pushfq
550 pop [uFlags]
551# else
552 pushfd
553 pop [uFlags]
554# endif
555 }
556# endif
557 return uFlags;
558}
559#endif
560
561
562/**
563 * Set the [RE]FLAGS register.
564 * @param uFlags The new [RE]FLAGS value.
565 */
566#if RT_INLINE_ASM_EXTERNAL && RT_INLINE_ASM_USES_INTRIN < 15
567DECLASM(void) ASMSetFlags(RTCCUINTREG uFlags);
568#else
569DECLINLINE(void) ASMSetFlags(RTCCUINTREG uFlags)
570{
571# if RT_INLINE_ASM_GNU_STYLE
572# ifdef RT_ARCH_AMD64
573 __asm__ __volatile__("pushq %0\n\t"
574 "popfq\n\t"
575 : : "g" (uFlags));
576# else
577 __asm__ __volatile__("pushl %0\n\t"
578 "popfl\n\t"
579 : : "g" (uFlags));
580# endif
581# elif RT_INLINE_ASM_USES_INTRIN >= 15
582 __writeeflags(uFlags);
583# else
584 __asm
585 {
586# ifdef RT_ARCH_AMD64
587 push [uFlags]
588 popfq
589# else
590 push [uFlags]
591 popfd
592# endif
593 }
594# endif
595}
596#endif
597
598
599/**
600 * Modifies the [RE]FLAGS register.
601 * @returns Original value.
602 * @param fAndEfl Flags to keep (applied first).
603 * @param fOrEfl Flags to be set.
604 */
605#if RT_INLINE_ASM_EXTERNAL && RT_INLINE_ASM_USES_INTRIN < 15
606DECLASM(RTCCUINTREG) ASMChangeFlags(RTCCUINTREG fAndEfl, RTCCUINTREG fOrEfl);
607#else
608DECLINLINE(RTCCUINTREG) ASMChangeFlags(RTCCUINTREG fAndEfl, RTCCUINTREG fOrEfl)
609{
610 RTCCUINTREG fOldEfl;
611# if RT_INLINE_ASM_GNU_STYLE
612# ifdef RT_ARCH_AMD64
613 __asm__ __volatile__("pushfq\n\t"
614 "movq (%%rsp), %0\n\t"
615 "andq %0, %1\n\t"
616 "orq %3, %1\n\t"
617 "mov %1, (%%rsp)\n\t"
618 "popfq\n\t"
619 : "=r" (fOldEfl),
620 "=g" (fAndEfl)
621 : "1" (fAndEfl),
622 "g" (fOrEfl) );
623# else
624 __asm__ __volatile__("pushfl\n\t"
625 "movl (%%esp), %0\n\t"
626 "andl %1, (%%esp)\n\t"
627 "orl %2, (%%esp)\n\t"
628 "popfl\n\t"
629 : "=r" (fOldEfl)
630 : "g" (fAndEfl),
631 "g" (fOrEfl) );
632# endif
633# elif RT_INLINE_ASM_USES_INTRIN >= 15
634 fOldEfl = __readeflags();
635 __writeeflags((fOldEfl & fAndEfl) | fOrEfl);
636# else
637 __asm
638 {
639# ifdef RT_ARCH_AMD64
640 mov rdx, [fAndEfl]
641 mov rcx, [fOrEfl]
642 pushfq
643 mov rax, [rsp]
644 and rdx, rax
645 or rdx, rcx
646 mov [rsp], rdx
647 popfq
648 mov [fOldEfl], rax
649# else
650 mov edx, [fAndEfl]
651 mov ecx, [fOrEfl]
652 pushfd
653 mov eax, [esp]
654 and edx, eax
655 or edx, ecx
656 mov [esp], edx
657 popfd
658 mov [fOldEfl], eax
659# endif
660 }
661# endif
662 return fOldEfl;
663}
664#endif
665
666
667/**
668 * Modifies the [RE]FLAGS register by ORing in one or more flags.
669 * @returns Original value.
670 * @param fOrEfl The flags to be set (ORed in).
671 */
672#if RT_INLINE_ASM_EXTERNAL && RT_INLINE_ASM_USES_INTRIN < 15
673DECLASM(RTCCUINTREG) ASMAddFlags(RTCCUINTREG fOrEfl);
674#else
675DECLINLINE(RTCCUINTREG) ASMAddFlags(RTCCUINTREG fOrEfl)
676{
677 RTCCUINTREG fOldEfl;
678# if RT_INLINE_ASM_GNU_STYLE
679# ifdef RT_ARCH_AMD64
680 __asm__ __volatile__("pushfq\n\t"
681 "movq (%%rsp), %0\n\t"
682 "orq %1, (%%rsp)\n\t"
683 "popfq\n\t"
684 : "=r" (fOldEfl)
685 : "g" (fOrEfl) );
686# else
687 __asm__ __volatile__("pushfl\n\t"
688 "movl (%%esp), %0\n\t"
689 "orl %1, (%%esp)\n\t"
690 "popfl\n\t"
691 : "=r" (fOldEfl)
692 : "g" (fOrEfl) );
693# endif
694# elif RT_INLINE_ASM_USES_INTRIN >= 15
695 fOldEfl = __readeflags();
696 __writeeflags(fOldEfl | fOrEfl);
697# else
698 __asm
699 {
700# ifdef RT_ARCH_AMD64
701 mov rcx, [fOrEfl]
702 pushfq
703 mov rdx, [rsp]
704 or [rsp], rcx
705 popfq
706 mov [fOldEfl], rax
707# else
708 mov ecx, [fOrEfl]
709 pushfd
710 mov edx, [esp]
711 or [esp], ecx
712 popfd
713 mov [fOldEfl], eax
714# endif
715 }
716# endif
717 return fOldEfl;
718}
719#endif
720
721
722/**
723 * Modifies the [RE]FLAGS register by AND'ing out one or more flags.
724 * @returns Original value.
725 * @param fAndEfl The flags to keep.
726 */
727#if RT_INLINE_ASM_EXTERNAL && RT_INLINE_ASM_USES_INTRIN < 15
728DECLASM(RTCCUINTREG) ASMClearFlags(RTCCUINTREG fAndEfl);
729#else
730DECLINLINE(RTCCUINTREG) ASMClearFlags(RTCCUINTREG fAndEfl)
731{
732 RTCCUINTREG fOldEfl;
733# if RT_INLINE_ASM_GNU_STYLE
734# ifdef RT_ARCH_AMD64
735 __asm__ __volatile__("pushfq\n\t"
736 "movq (%%rsp), %0\n\t"
737 "andq %1, (%%rsp)\n\t"
738 "popfq\n\t"
739 : "=r" (fOldEfl)
740 : "g" (fAndEfl) );
741# else
742 __asm__ __volatile__("pushfl\n\t"
743 "movl (%%esp), %0\n\t"
744 "andl %1, (%%esp)\n\t"
745 "popfl\n\t"
746 : "=r" (fOldEfl)
747 : "g" (fAndEfl) );
748# endif
749# elif RT_INLINE_ASM_USES_INTRIN >= 15
750 fOldEfl = __readeflags();
751 __writeeflags(fOldEfl & fAndEfl);
752# else
753 __asm
754 {
755# ifdef RT_ARCH_AMD64
756 mov rdx, [fAndEfl]
757 pushfq
758 mov rdx, [rsp]
759 and [rsp], rdx
760 popfq
761 mov [fOldEfl], rax
762# else
763 mov edx, [fAndEfl]
764 pushfd
765 mov edx, [esp]
766 and [esp], edx
767 popfd
768 mov [fOldEfl], eax
769# endif
770 }
771# endif
772 return fOldEfl;
773}
774#endif
775
776
777/**
778 * Gets the content of the CPU timestamp counter register.
779 *
780 * @returns TSC.
781 */
782#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
783DECLASM(uint64_t) ASMReadTSC(void);
784#else
785DECLINLINE(uint64_t) ASMReadTSC(void)
786{
787 RTUINT64U u;
788# if RT_INLINE_ASM_GNU_STYLE
789 __asm__ __volatile__("rdtsc\n\t" : "=a" (u.s.Lo), "=d" (u.s.Hi));
790# else
791# if RT_INLINE_ASM_USES_INTRIN
792 u.u = __rdtsc();
793# else
794 __asm
795 {
796 rdtsc
797 mov [u.s.Lo], eax
798 mov [u.s.Hi], edx
799 }
800# endif
801# endif
802 return u.u;
803}
804#endif
805
806
807/**
808 * Gets the content of the CPU timestamp counter register and the
809 * assoicated AUX value.
810 *
811 * @returns TSC.
812 * @param puAux Where to store the AUX value.
813 */
814#if RT_INLINE_ASM_EXTERNAL && RT_INLINE_ASM_USES_INTRIN < 15
815DECLASM(uint64_t) ASMReadTscWithAux(uint32_t *puAux);
816#else
817DECLINLINE(uint64_t) ASMReadTscWithAux(uint32_t *puAux)
818{
819 RTUINT64U u;
820# if RT_INLINE_ASM_GNU_STYLE
821 /* rdtscp is not supported by ancient linux build VM of course :-( */
822 /*__asm__ __volatile__("rdtscp\n\t" : "=a" (u.s.Lo), "=d" (u.s.Hi), "=c" (*puAux)); */
823 __asm__ __volatile__(".byte 0x0f,0x01,0xf9\n\t" : "=a" (u.s.Lo), "=d" (u.s.Hi), "=c" (*puAux));
824# else
825# if RT_INLINE_ASM_USES_INTRIN >= 15
826 u.u = __rdtscp(puAux);
827# else
828 __asm
829 {
830 rdtscp
831 mov [u.s.Lo], eax
832 mov [u.s.Hi], edx
833 mov eax, [puAux]
834 mov [eax], ecx
835 }
836# endif
837# endif
838 return u.u;
839}
840#endif
841
842
843/**
844 * Performs the cpuid instruction returning all registers.
845 *
846 * @param uOperator CPUID operation (eax).
847 * @param pvEAX Where to store eax.
848 * @param pvEBX Where to store ebx.
849 * @param pvECX Where to store ecx.
850 * @param pvEDX Where to store edx.
851 * @remark We're using void pointers to ease the use of special bitfield structures and such.
852 */
853#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
854DECLASM(void) ASMCpuId(uint32_t uOperator, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX);
855#else
856DECLINLINE(void) ASMCpuId(uint32_t uOperator, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX)
857{
858# if RT_INLINE_ASM_GNU_STYLE
859# ifdef RT_ARCH_AMD64
860 RTCCUINTREG uRAX, uRBX, uRCX, uRDX;
861 __asm__ __volatile__ ("cpuid\n\t"
862 : "=a" (uRAX),
863 "=b" (uRBX),
864 "=c" (uRCX),
865 "=d" (uRDX)
866 : "0" (uOperator), "2" (0));
867 *(uint32_t *)pvEAX = (uint32_t)uRAX;
868 *(uint32_t *)pvEBX = (uint32_t)uRBX;
869 *(uint32_t *)pvECX = (uint32_t)uRCX;
870 *(uint32_t *)pvEDX = (uint32_t)uRDX;
871# else
872 __asm__ __volatile__ ("xchgl %%ebx, %1\n\t"
873 "cpuid\n\t"
874 "xchgl %%ebx, %1\n\t"
875 : "=a" (*(uint32_t *)pvEAX),
876 "=r" (*(uint32_t *)pvEBX),
877 "=c" (*(uint32_t *)pvECX),
878 "=d" (*(uint32_t *)pvEDX)
879 : "0" (uOperator), "2" (0));
880# endif
881
882# elif RT_INLINE_ASM_USES_INTRIN
883 int aInfo[4];
884 __cpuid(aInfo, uOperator);
885 *(uint32_t *)pvEAX = aInfo[0];
886 *(uint32_t *)pvEBX = aInfo[1];
887 *(uint32_t *)pvECX = aInfo[2];
888 *(uint32_t *)pvEDX = aInfo[3];
889
890# else
891 uint32_t uEAX;
892 uint32_t uEBX;
893 uint32_t uECX;
894 uint32_t uEDX;
895 __asm
896 {
897 push ebx
898 mov eax, [uOperator]
899 cpuid
900 mov [uEAX], eax
901 mov [uEBX], ebx
902 mov [uECX], ecx
903 mov [uEDX], edx
904 pop ebx
905 }
906 *(uint32_t *)pvEAX = uEAX;
907 *(uint32_t *)pvEBX = uEBX;
908 *(uint32_t *)pvECX = uECX;
909 *(uint32_t *)pvEDX = uEDX;
910# endif
911}
912#endif
913
914
915/**
916 * Performs the CPUID instruction with EAX and ECX input returning ALL output
917 * registers.
918 *
919 * @param uOperator CPUID operation (eax).
920 * @param uIdxECX ecx index
921 * @param pvEAX Where to store eax.
922 * @param pvEBX Where to store ebx.
923 * @param pvECX Where to store ecx.
924 * @param pvEDX Where to store edx.
925 * @remark We're using void pointers to ease the use of special bitfield structures and such.
926 */
927#if RT_INLINE_ASM_EXTERNAL || RT_INLINE_ASM_USES_INTRIN
928DECLASM(void) ASMCpuId_Idx_ECX(uint32_t uOperator, uint32_t uIdxECX, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX);
929#else
930DECLINLINE(void) ASMCpuId_Idx_ECX(uint32_t uOperator, uint32_t uIdxECX, void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX)
931{
932# if RT_INLINE_ASM_GNU_STYLE
933# ifdef RT_ARCH_AMD64
934 RTCCUINTREG uRAX, uRBX, uRCX, uRDX;
935 __asm__ ("cpuid\n\t"
936 : "=a" (uRAX),
937 "=b" (uRBX),
938 "=c" (uRCX),
939 "=d" (uRDX)
940 : "0" (uOperator),
941 "2" (uIdxECX));
942 *(uint32_t *)pvEAX = (uint32_t)uRAX;
943 *(uint32_t *)pvEBX = (uint32_t)uRBX;
944 *(uint32_t *)pvECX = (uint32_t)uRCX;
945 *(uint32_t *)pvEDX = (uint32_t)uRDX;
946# else
947 __asm__ ("xchgl %%ebx, %1\n\t"
948 "cpuid\n\t"
949 "xchgl %%ebx, %1\n\t"
950 : "=a" (*(uint32_t *)pvEAX),
951 "=r" (*(uint32_t *)pvEBX),
952 "=c" (*(uint32_t *)pvECX),
953 "=d" (*(uint32_t *)pvEDX)
954 : "0" (uOperator),
955 "2" (uIdxECX));
956# endif
957
958# elif RT_INLINE_ASM_USES_INTRIN
959 int aInfo[4];
960 __cpuidex(aInfo, uOperator, uIdxECX);
961 *(uint32_t *)pvEAX = aInfo[0];
962 *(uint32_t *)pvEBX = aInfo[1];
963 *(uint32_t *)pvECX = aInfo[2];
964 *(uint32_t *)pvEDX = aInfo[3];
965
966# else
967 uint32_t uEAX;
968 uint32_t uEBX;
969 uint32_t uECX;
970 uint32_t uEDX;
971 __asm
972 {
973 push ebx
974 mov eax, [uOperator]
975 mov ecx, [uIdxECX]
976 cpuid
977 mov [uEAX], eax
978 mov [uEBX], ebx
979 mov [uECX], ecx
980 mov [uEDX], edx
981 pop ebx
982 }
983 *(uint32_t *)pvEAX = uEAX;
984 *(uint32_t *)pvEBX = uEBX;
985 *(uint32_t *)pvECX = uECX;
986 *(uint32_t *)pvEDX = uEDX;
987# endif
988}
989#endif
990
991
992/**
993 * CPUID variant that initializes all 4 registers before the CPUID instruction.
994 *
995 * @returns The EAX result value.
996 * @param uOperator CPUID operation (eax).
997 * @param uInitEBX The value to assign EBX prior to the CPUID instruction.
998 * @param uInitECX The value to assign ECX prior to the CPUID instruction.
999 * @param uInitEDX The value to assign EDX prior to the CPUID instruction.
1000 * @param pvEAX Where to store eax. Optional.
1001 * @param pvEBX Where to store ebx. Optional.
1002 * @param pvECX Where to store ecx. Optional.
1003 * @param pvEDX Where to store edx. Optional.
1004 */
1005DECLASM(uint32_t) ASMCpuIdExSlow(uint32_t uOperator, uint32_t uInitEBX, uint32_t uInitECX, uint32_t uInitEDX,
1006 void *pvEAX, void *pvEBX, void *pvECX, void *pvEDX);
1007
1008
1009/**
1010 * Performs the cpuid instruction returning ecx and edx.
1011 *
1012 * @param uOperator CPUID operation (eax).
1013 * @param pvECX Where to store ecx.
1014 * @param pvEDX Where to store edx.
1015 * @remark We're using void pointers to ease the use of special bitfield structures and such.
1016 */
1017#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1018DECLASM(void) ASMCpuId_ECX_EDX(uint32_t uOperator, void *pvECX, void *pvEDX);
1019#else
1020DECLINLINE(void) ASMCpuId_ECX_EDX(uint32_t uOperator, void *pvECX, void *pvEDX)
1021{
1022 uint32_t uEBX;
1023 ASMCpuId(uOperator, &uOperator, &uEBX, pvECX, pvEDX);
1024}
1025#endif
1026
1027
1028/**
1029 * Performs the cpuid instruction returning eax.
1030 *
1031 * @param uOperator CPUID operation (eax).
1032 * @returns EAX after cpuid operation.
1033 */
1034#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1035DECLASM(uint32_t) ASMCpuId_EAX(uint32_t uOperator);
1036#else
1037DECLINLINE(uint32_t) ASMCpuId_EAX(uint32_t uOperator)
1038{
1039 RTCCUINTREG xAX;
1040# if RT_INLINE_ASM_GNU_STYLE
1041# ifdef RT_ARCH_AMD64
1042 __asm__ ("cpuid"
1043 : "=a" (xAX)
1044 : "0" (uOperator)
1045 : "rbx", "rcx", "rdx");
1046# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
1047 __asm__ ("push %%ebx\n\t"
1048 "cpuid\n\t"
1049 "pop %%ebx\n\t"
1050 : "=a" (xAX)
1051 : "0" (uOperator)
1052 : "ecx", "edx");
1053# else
1054 __asm__ ("cpuid"
1055 : "=a" (xAX)
1056 : "0" (uOperator)
1057 : "edx", "ecx", "ebx");
1058# endif
1059
1060# elif RT_INLINE_ASM_USES_INTRIN
1061 int aInfo[4];
1062 __cpuid(aInfo, uOperator);
1063 xAX = aInfo[0];
1064
1065# else
1066 __asm
1067 {
1068 push ebx
1069 mov eax, [uOperator]
1070 cpuid
1071 mov [xAX], eax
1072 pop ebx
1073 }
1074# endif
1075 return (uint32_t)xAX;
1076}
1077#endif
1078
1079
1080/**
1081 * Performs the cpuid instruction returning ebx.
1082 *
1083 * @param uOperator CPUID operation (eax).
1084 * @returns EBX after cpuid operation.
1085 */
1086#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1087DECLASM(uint32_t) ASMCpuId_EBX(uint32_t uOperator);
1088#else
1089DECLINLINE(uint32_t) ASMCpuId_EBX(uint32_t uOperator)
1090{
1091 RTCCUINTREG xBX;
1092# if RT_INLINE_ASM_GNU_STYLE
1093# ifdef RT_ARCH_AMD64
1094 RTCCUINTREG uSpill;
1095 __asm__ ("cpuid"
1096 : "=a" (uSpill),
1097 "=b" (xBX)
1098 : "0" (uOperator)
1099 : "rdx", "rcx");
1100# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
1101 __asm__ ("push %%ebx\n\t"
1102 "cpuid\n\t"
1103 "mov %%ebx, %%edx\n\t"
1104 "pop %%ebx\n\t"
1105 : "=a" (uOperator),
1106 "=d" (xBX)
1107 : "0" (uOperator)
1108 : "ecx");
1109# else
1110 __asm__ ("cpuid"
1111 : "=a" (uOperator),
1112 "=b" (xBX)
1113 : "0" (uOperator)
1114 : "edx", "ecx");
1115# endif
1116
1117# elif RT_INLINE_ASM_USES_INTRIN
1118 int aInfo[4];
1119 __cpuid(aInfo, uOperator);
1120 xBX = aInfo[1];
1121
1122# else
1123 __asm
1124 {
1125 push ebx
1126 mov eax, [uOperator]
1127 cpuid
1128 mov [xBX], ebx
1129 pop ebx
1130 }
1131# endif
1132 return (uint32_t)xBX;
1133}
1134#endif
1135
1136
1137/**
1138 * Performs the cpuid instruction returning ecx.
1139 *
1140 * @param uOperator CPUID operation (eax).
1141 * @returns ECX after cpuid operation.
1142 */
1143#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1144DECLASM(uint32_t) ASMCpuId_ECX(uint32_t uOperator);
1145#else
1146DECLINLINE(uint32_t) ASMCpuId_ECX(uint32_t uOperator)
1147{
1148 RTCCUINTREG xCX;
1149# if RT_INLINE_ASM_GNU_STYLE
1150# ifdef RT_ARCH_AMD64
1151 RTCCUINTREG uSpill;
1152 __asm__ ("cpuid"
1153 : "=a" (uSpill),
1154 "=c" (xCX)
1155 : "0" (uOperator)
1156 : "rbx", "rdx");
1157# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
1158 __asm__ ("push %%ebx\n\t"
1159 "cpuid\n\t"
1160 "pop %%ebx\n\t"
1161 : "=a" (uOperator),
1162 "=c" (xCX)
1163 : "0" (uOperator)
1164 : "edx");
1165# else
1166 __asm__ ("cpuid"
1167 : "=a" (uOperator),
1168 "=c" (xCX)
1169 : "0" (uOperator)
1170 : "ebx", "edx");
1171
1172# endif
1173
1174# elif RT_INLINE_ASM_USES_INTRIN
1175 int aInfo[4];
1176 __cpuid(aInfo, uOperator);
1177 xCX = aInfo[2];
1178
1179# else
1180 __asm
1181 {
1182 push ebx
1183 mov eax, [uOperator]
1184 cpuid
1185 mov [xCX], ecx
1186 pop ebx
1187 }
1188# endif
1189 return (uint32_t)xCX;
1190}
1191#endif
1192
1193
1194/**
1195 * Performs the cpuid instruction returning edx.
1196 *
1197 * @param uOperator CPUID operation (eax).
1198 * @returns EDX after cpuid operation.
1199 */
1200#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1201DECLASM(uint32_t) ASMCpuId_EDX(uint32_t uOperator);
1202#else
1203DECLINLINE(uint32_t) ASMCpuId_EDX(uint32_t uOperator)
1204{
1205 RTCCUINTREG xDX;
1206# if RT_INLINE_ASM_GNU_STYLE
1207# ifdef RT_ARCH_AMD64
1208 RTCCUINTREG uSpill;
1209 __asm__ ("cpuid"
1210 : "=a" (uSpill),
1211 "=d" (xDX)
1212 : "0" (uOperator)
1213 : "rbx", "rcx");
1214# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
1215 __asm__ ("push %%ebx\n\t"
1216 "cpuid\n\t"
1217 "pop %%ebx\n\t"
1218 : "=a" (uOperator),
1219 "=d" (xDX)
1220 : "0" (uOperator)
1221 : "ecx");
1222# else
1223 __asm__ ("cpuid"
1224 : "=a" (uOperator),
1225 "=d" (xDX)
1226 : "0" (uOperator)
1227 : "ebx", "ecx");
1228# endif
1229
1230# elif RT_INLINE_ASM_USES_INTRIN
1231 int aInfo[4];
1232 __cpuid(aInfo, uOperator);
1233 xDX = aInfo[3];
1234
1235# else
1236 __asm
1237 {
1238 push ebx
1239 mov eax, [uOperator]
1240 cpuid
1241 mov [xDX], edx
1242 pop ebx
1243 }
1244# endif
1245 return (uint32_t)xDX;
1246}
1247#endif
1248
1249
1250/**
1251 * Checks if the current CPU supports CPUID.
1252 *
1253 * @returns true if CPUID is supported.
1254 */
1255DECLINLINE(bool) ASMHasCpuId(void)
1256{
1257#ifdef RT_ARCH_AMD64
1258 return true; /* ASSUME that all amd64 compatible CPUs have cpuid. */
1259#else /* !RT_ARCH_AMD64 */
1260 bool fRet = false;
1261# if RT_INLINE_ASM_GNU_STYLE
1262 uint32_t u1;
1263 uint32_t u2;
1264 __asm__ ("pushf\n\t"
1265 "pop %1\n\t"
1266 "mov %1, %2\n\t"
1267 "xorl $0x200000, %1\n\t"
1268 "push %1\n\t"
1269 "popf\n\t"
1270 "pushf\n\t"
1271 "pop %1\n\t"
1272 "cmpl %1, %2\n\t"
1273 "setne %0\n\t"
1274 "push %2\n\t"
1275 "popf\n\t"
1276 : "=m" (fRet), "=r" (u1), "=r" (u2));
1277# else
1278 __asm
1279 {
1280 pushfd
1281 pop eax
1282 mov ebx, eax
1283 xor eax, 0200000h
1284 push eax
1285 popfd
1286 pushfd
1287 pop eax
1288 cmp eax, ebx
1289 setne fRet
1290 push ebx
1291 popfd
1292 }
1293# endif
1294 return fRet;
1295#endif /* !RT_ARCH_AMD64 */
1296}
1297
1298
1299/**
1300 * Gets the APIC ID of the current CPU.
1301 *
1302 * @returns the APIC ID.
1303 */
1304#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1305DECLASM(uint8_t) ASMGetApicId(void);
1306#else
1307DECLINLINE(uint8_t) ASMGetApicId(void)
1308{
1309 RTCCUINTREG xBX;
1310# if RT_INLINE_ASM_GNU_STYLE
1311# ifdef RT_ARCH_AMD64
1312 RTCCUINTREG uSpill;
1313 __asm__ __volatile__ ("cpuid"
1314 : "=a" (uSpill),
1315 "=b" (xBX)
1316 : "0" (1)
1317 : "rcx", "rdx");
1318# elif (defined(PIC) || defined(__PIC__)) && defined(__i386__)
1319 RTCCUINTREG uSpill;
1320 __asm__ __volatile__ ("mov %%ebx,%1\n\t"
1321 "cpuid\n\t"
1322 "xchgl %%ebx,%1\n\t"
1323 : "=a" (uSpill),
1324 "=rm" (xBX)
1325 : "0" (1)
1326 : "ecx", "edx");
1327# else
1328 RTCCUINTREG uSpill;
1329 __asm__ __volatile__ ("cpuid"
1330 : "=a" (uSpill),
1331 "=b" (xBX)
1332 : "0" (1)
1333 : "ecx", "edx");
1334# endif
1335
1336# elif RT_INLINE_ASM_USES_INTRIN
1337 int aInfo[4];
1338 __cpuid(aInfo, 1);
1339 xBX = aInfo[1];
1340
1341# else
1342 __asm
1343 {
1344 push ebx
1345 mov eax, 1
1346 cpuid
1347 mov [xBX], ebx
1348 pop ebx
1349 }
1350# endif
1351 return (uint8_t)(xBX >> 24);
1352}
1353#endif
1354
1355
1356/**
1357 * Tests if it a genuine Intel CPU based on the ASMCpuId(0) output.
1358 *
1359 * @returns true/false.
1360 * @param uEBX EBX return from ASMCpuId(0)
1361 * @param uECX ECX return from ASMCpuId(0)
1362 * @param uEDX EDX return from ASMCpuId(0)
1363 */
1364DECLINLINE(bool) ASMIsIntelCpuEx(uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1365{
1366 return uEBX == UINT32_C(0x756e6547)
1367 && uECX == UINT32_C(0x6c65746e)
1368 && uEDX == UINT32_C(0x49656e69);
1369}
1370
1371
1372/**
1373 * Tests if this is a genuine Intel CPU.
1374 *
1375 * @returns true/false.
1376 * @remarks ASSUMES that cpuid is supported by the CPU.
1377 */
1378DECLINLINE(bool) ASMIsIntelCpu(void)
1379{
1380 uint32_t uEAX, uEBX, uECX, uEDX;
1381 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
1382 return ASMIsIntelCpuEx(uEBX, uECX, uEDX);
1383}
1384
1385
1386/**
1387 * Tests if it an authentic AMD CPU based on the ASMCpuId(0) output.
1388 *
1389 * @returns true/false.
1390 * @param uEBX EBX return from ASMCpuId(0)
1391 * @param uECX ECX return from ASMCpuId(0)
1392 * @param uEDX EDX return from ASMCpuId(0)
1393 */
1394DECLINLINE(bool) ASMIsAmdCpuEx(uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1395{
1396 return uEBX == UINT32_C(0x68747541)
1397 && uECX == UINT32_C(0x444d4163)
1398 && uEDX == UINT32_C(0x69746e65);
1399}
1400
1401
1402/**
1403 * Tests if this is an authentic AMD CPU.
1404 *
1405 * @returns true/false.
1406 * @remarks ASSUMES that cpuid is supported by the CPU.
1407 */
1408DECLINLINE(bool) ASMIsAmdCpu(void)
1409{
1410 uint32_t uEAX, uEBX, uECX, uEDX;
1411 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
1412 return ASMIsAmdCpuEx(uEBX, uECX, uEDX);
1413}
1414
1415
1416/**
1417 * Tests if it a centaur hauling VIA CPU based on the ASMCpuId(0) output.
1418 *
1419 * @returns true/false.
1420 * @param uEBX EBX return from ASMCpuId(0).
1421 * @param uECX ECX return from ASMCpuId(0).
1422 * @param uEDX EDX return from ASMCpuId(0).
1423 */
1424DECLINLINE(bool) ASMIsViaCentaurCpuEx(uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1425{
1426 return uEBX == UINT32_C(0x746e6543)
1427 && uECX == UINT32_C(0x736c7561)
1428 && uEDX == UINT32_C(0x48727561);
1429}
1430
1431
1432/**
1433 * Tests if this is a centaur hauling VIA CPU.
1434 *
1435 * @returns true/false.
1436 * @remarks ASSUMES that cpuid is supported by the CPU.
1437 */
1438DECLINLINE(bool) ASMIsViaCentaurCpu(void)
1439{
1440 uint32_t uEAX, uEBX, uECX, uEDX;
1441 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
1442 return ASMIsAmdCpuEx(uEBX, uECX, uEDX);
1443}
1444
1445
1446/**
1447 * Checks whether ASMCpuId_EAX(0x00000000) indicates a valid range.
1448 *
1449 *
1450 * @returns true/false.
1451 * @param uEAX The EAX value of CPUID leaf 0x00000000.
1452 *
1453 * @note This only succeeds if there are at least two leaves in the range.
1454 * @remarks The upper range limit is just some half reasonable value we've
1455 * picked out of thin air.
1456 */
1457DECLINLINE(bool) ASMIsValidStdRange(uint32_t uEAX)
1458{
1459 return uEAX >= UINT32_C(0x00000001) && uEAX <= UINT32_C(0x000fffff);
1460}
1461
1462
1463/**
1464 * Checks whether ASMCpuId_EAX(0x80000000) indicates a valid range.
1465 *
1466 * This only succeeds if there are at least two leaves in the range.
1467 *
1468 * @returns true/false.
1469 * @param uEAX The EAX value of CPUID leaf 0x80000000.
1470 *
1471 * @note This only succeeds if there are at least two leaves in the range.
1472 * @remarks The upper range limit is just some half reasonable value we've
1473 * picked out of thin air.
1474 */
1475DECLINLINE(bool) ASMIsValidExtRange(uint32_t uEAX)
1476{
1477 return uEAX >= UINT32_C(0x80000001) && uEAX <= UINT32_C(0x800fffff);
1478}
1479
1480
1481/**
1482 * Extracts the CPU family from ASMCpuId(1) or ASMCpuId(0x80000001)
1483 *
1484 * @returns Family.
1485 * @param uEAX EAX return from ASMCpuId(1) or ASMCpuId(0x80000001).
1486 */
1487DECLINLINE(uint32_t) ASMGetCpuFamily(uint32_t uEAX)
1488{
1489 return ((uEAX >> 8) & 0xf) == 0xf
1490 ? ((uEAX >> 20) & 0x7f) + 0xf
1491 : ((uEAX >> 8) & 0xf);
1492}
1493
1494
1495/**
1496 * Extracts the CPU model from ASMCpuId(1) or ASMCpuId(0x80000001), Intel variant.
1497 *
1498 * @returns Model.
1499 * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
1500 */
1501DECLINLINE(uint32_t) ASMGetCpuModelIntel(uint32_t uEAX)
1502{
1503 return ((uEAX >> 8) & 0xf) == 0xf || (((uEAX >> 8) & 0xf) == 0x6) /* family! */
1504 ? ((uEAX >> 4) & 0xf) | ((uEAX >> 12) & 0xf0)
1505 : ((uEAX >> 4) & 0xf);
1506}
1507
1508
1509/**
1510 * Extracts the CPU model from ASMCpuId(1) or ASMCpuId(0x80000001), AMD variant.
1511 *
1512 * @returns Model.
1513 * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
1514 */
1515DECLINLINE(uint32_t) ASMGetCpuModelAMD(uint32_t uEAX)
1516{
1517 return ((uEAX >> 8) & 0xf) == 0xf
1518 ? ((uEAX >> 4) & 0xf) | ((uEAX >> 12) & 0xf0)
1519 : ((uEAX >> 4) & 0xf);
1520}
1521
1522
1523/**
1524 * Extracts the CPU model from ASMCpuId(1) or ASMCpuId(0x80000001)
1525 *
1526 * @returns Model.
1527 * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
1528 * @param fIntel Whether it's an intel CPU. Use ASMIsIntelCpuEx() or ASMIsIntelCpu().
1529 */
1530DECLINLINE(uint32_t) ASMGetCpuModel(uint32_t uEAX, bool fIntel)
1531{
1532 return ((uEAX >> 8) & 0xf) == 0xf || (((uEAX >> 8) & 0xf) == 0x6 && fIntel) /* family! */
1533 ? ((uEAX >> 4) & 0xf) | ((uEAX >> 12) & 0xf0)
1534 : ((uEAX >> 4) & 0xf);
1535}
1536
1537
1538/**
1539 * Extracts the CPU stepping from ASMCpuId(1) or ASMCpuId(0x80000001)
1540 *
1541 * @returns Model.
1542 * @param uEAX EAX from ASMCpuId(1) or ASMCpuId(0x80000001).
1543 */
1544DECLINLINE(uint32_t) ASMGetCpuStepping(uint32_t uEAX)
1545{
1546 return uEAX & 0xf;
1547}
1548
1549
1550/**
1551 * Get cr0.
1552 * @returns cr0.
1553 */
1554#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1555DECLASM(RTCCUINTREG) ASMGetCR0(void);
1556#else
1557DECLINLINE(RTCCUINTREG) ASMGetCR0(void)
1558{
1559 RTCCUINTREG uCR0;
1560# if RT_INLINE_ASM_USES_INTRIN
1561 uCR0 = __readcr0();
1562
1563# elif RT_INLINE_ASM_GNU_STYLE
1564# ifdef RT_ARCH_AMD64
1565 __asm__ __volatile__("movq %%cr0, %0\t\n" : "=r" (uCR0));
1566# else
1567 __asm__ __volatile__("movl %%cr0, %0\t\n" : "=r" (uCR0));
1568# endif
1569# else
1570 __asm
1571 {
1572# ifdef RT_ARCH_AMD64
1573 mov rax, cr0
1574 mov [uCR0], rax
1575# else
1576 mov eax, cr0
1577 mov [uCR0], eax
1578# endif
1579 }
1580# endif
1581 return uCR0;
1582}
1583#endif
1584
1585
1586/**
1587 * Sets the CR0 register.
1588 * @param uCR0 The new CR0 value.
1589 */
1590#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1591DECLASM(void) ASMSetCR0(RTCCUINTREG uCR0);
1592#else
1593DECLINLINE(void) ASMSetCR0(RTCCUINTREG uCR0)
1594{
1595# if RT_INLINE_ASM_USES_INTRIN
1596 __writecr0(uCR0);
1597
1598# elif RT_INLINE_ASM_GNU_STYLE
1599# ifdef RT_ARCH_AMD64
1600 __asm__ __volatile__("movq %0, %%cr0\n\t" :: "r" (uCR0));
1601# else
1602 __asm__ __volatile__("movl %0, %%cr0\n\t" :: "r" (uCR0));
1603# endif
1604# else
1605 __asm
1606 {
1607# ifdef RT_ARCH_AMD64
1608 mov rax, [uCR0]
1609 mov cr0, rax
1610# else
1611 mov eax, [uCR0]
1612 mov cr0, eax
1613# endif
1614 }
1615# endif
1616}
1617#endif
1618
1619
1620/**
1621 * Get cr2.
1622 * @returns cr2.
1623 */
1624#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1625DECLASM(RTCCUINTREG) ASMGetCR2(void);
1626#else
1627DECLINLINE(RTCCUINTREG) ASMGetCR2(void)
1628{
1629 RTCCUINTREG uCR2;
1630# if RT_INLINE_ASM_USES_INTRIN
1631 uCR2 = __readcr2();
1632
1633# elif RT_INLINE_ASM_GNU_STYLE
1634# ifdef RT_ARCH_AMD64
1635 __asm__ __volatile__("movq %%cr2, %0\t\n" : "=r" (uCR2));
1636# else
1637 __asm__ __volatile__("movl %%cr2, %0\t\n" : "=r" (uCR2));
1638# endif
1639# else
1640 __asm
1641 {
1642# ifdef RT_ARCH_AMD64
1643 mov rax, cr2
1644 mov [uCR2], rax
1645# else
1646 mov eax, cr2
1647 mov [uCR2], eax
1648# endif
1649 }
1650# endif
1651 return uCR2;
1652}
1653#endif
1654
1655
1656/**
1657 * Sets the CR2 register.
1658 * @param uCR2 The new CR0 value.
1659 */
1660#if RT_INLINE_ASM_EXTERNAL
1661DECLASM(void) ASMSetCR2(RTCCUINTREG uCR2);
1662#else
1663DECLINLINE(void) ASMSetCR2(RTCCUINTREG uCR2)
1664{
1665# if RT_INLINE_ASM_GNU_STYLE
1666# ifdef RT_ARCH_AMD64
1667 __asm__ __volatile__("movq %0, %%cr2\n\t" :: "r" (uCR2));
1668# else
1669 __asm__ __volatile__("movl %0, %%cr2\n\t" :: "r" (uCR2));
1670# endif
1671# else
1672 __asm
1673 {
1674# ifdef RT_ARCH_AMD64
1675 mov rax, [uCR2]
1676 mov cr2, rax
1677# else
1678 mov eax, [uCR2]
1679 mov cr2, eax
1680# endif
1681 }
1682# endif
1683}
1684#endif
1685
1686
1687/**
1688 * Get cr3.
1689 * @returns cr3.
1690 */
1691#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1692DECLASM(RTCCUINTREG) ASMGetCR3(void);
1693#else
1694DECLINLINE(RTCCUINTREG) ASMGetCR3(void)
1695{
1696 RTCCUINTREG uCR3;
1697# if RT_INLINE_ASM_USES_INTRIN
1698 uCR3 = __readcr3();
1699
1700# elif RT_INLINE_ASM_GNU_STYLE
1701# ifdef RT_ARCH_AMD64
1702 __asm__ __volatile__("movq %%cr3, %0\t\n" : "=r" (uCR3));
1703# else
1704 __asm__ __volatile__("movl %%cr3, %0\t\n" : "=r" (uCR3));
1705# endif
1706# else
1707 __asm
1708 {
1709# ifdef RT_ARCH_AMD64
1710 mov rax, cr3
1711 mov [uCR3], rax
1712# else
1713 mov eax, cr3
1714 mov [uCR3], eax
1715# endif
1716 }
1717# endif
1718 return uCR3;
1719}
1720#endif
1721
1722
1723/**
1724 * Sets the CR3 register.
1725 *
1726 * @param uCR3 New CR3 value.
1727 */
1728#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1729DECLASM(void) ASMSetCR3(RTCCUINTREG uCR3);
1730#else
1731DECLINLINE(void) ASMSetCR3(RTCCUINTREG uCR3)
1732{
1733# if RT_INLINE_ASM_USES_INTRIN
1734 __writecr3(uCR3);
1735
1736# elif RT_INLINE_ASM_GNU_STYLE
1737# ifdef RT_ARCH_AMD64
1738 __asm__ __volatile__("movq %0, %%cr3\n\t" : : "r" (uCR3));
1739# else
1740 __asm__ __volatile__("movl %0, %%cr3\n\t" : : "r" (uCR3));
1741# endif
1742# else
1743 __asm
1744 {
1745# ifdef RT_ARCH_AMD64
1746 mov rax, [uCR3]
1747 mov cr3, rax
1748# else
1749 mov eax, [uCR3]
1750 mov cr3, eax
1751# endif
1752 }
1753# endif
1754}
1755#endif
1756
1757
1758/**
1759 * Reloads the CR3 register.
1760 */
1761#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1762DECLASM(void) ASMReloadCR3(void);
1763#else
1764DECLINLINE(void) ASMReloadCR3(void)
1765{
1766# if RT_INLINE_ASM_USES_INTRIN
1767 __writecr3(__readcr3());
1768
1769# elif RT_INLINE_ASM_GNU_STYLE
1770 RTCCUINTREG u;
1771# ifdef RT_ARCH_AMD64
1772 __asm__ __volatile__("movq %%cr3, %0\n\t"
1773 "movq %0, %%cr3\n\t"
1774 : "=r" (u));
1775# else
1776 __asm__ __volatile__("movl %%cr3, %0\n\t"
1777 "movl %0, %%cr3\n\t"
1778 : "=r" (u));
1779# endif
1780# else
1781 __asm
1782 {
1783# ifdef RT_ARCH_AMD64
1784 mov rax, cr3
1785 mov cr3, rax
1786# else
1787 mov eax, cr3
1788 mov cr3, eax
1789# endif
1790 }
1791# endif
1792}
1793#endif
1794
1795
1796/**
1797 * Get cr4.
1798 * @returns cr4.
1799 */
1800#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1801DECLASM(RTCCUINTREG) ASMGetCR4(void);
1802#else
1803DECLINLINE(RTCCUINTREG) ASMGetCR4(void)
1804{
1805 RTCCUINTREG uCR4;
1806# if RT_INLINE_ASM_USES_INTRIN
1807 uCR4 = __readcr4();
1808
1809# elif RT_INLINE_ASM_GNU_STYLE
1810# ifdef RT_ARCH_AMD64
1811 __asm__ __volatile__("movq %%cr4, %0\t\n" : "=r" (uCR4));
1812# else
1813 __asm__ __volatile__("movl %%cr4, %0\t\n" : "=r" (uCR4));
1814# endif
1815# else
1816 __asm
1817 {
1818# ifdef RT_ARCH_AMD64
1819 mov rax, cr4
1820 mov [uCR4], rax
1821# else
1822 push eax /* just in case */
1823 /*mov eax, cr4*/
1824 _emit 0x0f
1825 _emit 0x20
1826 _emit 0xe0
1827 mov [uCR4], eax
1828 pop eax
1829# endif
1830 }
1831# endif
1832 return uCR4;
1833}
1834#endif
1835
1836
1837/**
1838 * Sets the CR4 register.
1839 *
1840 * @param uCR4 New CR4 value.
1841 */
1842#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1843DECLASM(void) ASMSetCR4(RTCCUINTREG uCR4);
1844#else
1845DECLINLINE(void) ASMSetCR4(RTCCUINTREG uCR4)
1846{
1847# if RT_INLINE_ASM_USES_INTRIN
1848 __writecr4(uCR4);
1849
1850# elif RT_INLINE_ASM_GNU_STYLE
1851# ifdef RT_ARCH_AMD64
1852 __asm__ __volatile__("movq %0, %%cr4\n\t" : : "r" (uCR4));
1853# else
1854 __asm__ __volatile__("movl %0, %%cr4\n\t" : : "r" (uCR4));
1855# endif
1856# else
1857 __asm
1858 {
1859# ifdef RT_ARCH_AMD64
1860 mov rax, [uCR4]
1861 mov cr4, rax
1862# else
1863 mov eax, [uCR4]
1864 _emit 0x0F
1865 _emit 0x22
1866 _emit 0xE0 /* mov cr4, eax */
1867# endif
1868 }
1869# endif
1870}
1871#endif
1872
1873
1874/**
1875 * Get cr8.
1876 * @returns cr8.
1877 * @remark The lock prefix hack for access from non-64-bit modes is NOT used and 0 is returned.
1878 */
1879#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1880DECLASM(RTCCUINTREG) ASMGetCR8(void);
1881#else
1882DECLINLINE(RTCCUINTREG) ASMGetCR8(void)
1883{
1884# ifdef RT_ARCH_AMD64
1885 RTCCUINTREG uCR8;
1886# if RT_INLINE_ASM_USES_INTRIN
1887 uCR8 = __readcr8();
1888
1889# elif RT_INLINE_ASM_GNU_STYLE
1890 __asm__ __volatile__("movq %%cr8, %0\t\n" : "=r" (uCR8));
1891# else
1892 __asm
1893 {
1894 mov rax, cr8
1895 mov [uCR8], rax
1896 }
1897# endif
1898 return uCR8;
1899# else /* !RT_ARCH_AMD64 */
1900 return 0;
1901# endif /* !RT_ARCH_AMD64 */
1902}
1903#endif
1904
1905
1906/**
1907 * Get XCR0 (eXtended feature Control Register 0).
1908 * @returns xcr0.
1909 */
1910DECLASM(uint64_t) ASMGetXcr0(void);
1911
1912/**
1913 * Sets the XCR0 register.
1914 * @param uXcr0 The new XCR0 value.
1915 */
1916DECLASM(void) ASMSetXcr0(uint64_t uXcr0);
1917
1918struct X86XSAVEAREA;
1919/**
1920 * Save extended CPU state.
1921 * @param pXStateArea Where to save the state.
1922 * @param fComponents Which state components to save.
1923 */
1924DECLASM(void) ASMXSave(struct X86XSAVEAREA *pXStateArea, uint64_t fComponents);
1925
1926/**
1927 * Loads extended CPU state.
1928 * @param pXStateArea Where to load the state from.
1929 * @param fComponents Which state components to load.
1930 */
1931DECLASM(void) ASMXRstor(struct X86XSAVEAREA const *pXStateArea, uint64_t fComponents);
1932
1933
1934/**
1935 * Enables interrupts (EFLAGS.IF).
1936 */
1937#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1938DECLASM(void) ASMIntEnable(void);
1939#else
1940DECLINLINE(void) ASMIntEnable(void)
1941{
1942# if RT_INLINE_ASM_GNU_STYLE
1943 __asm("sti\n");
1944# elif RT_INLINE_ASM_USES_INTRIN
1945 _enable();
1946# else
1947 __asm sti
1948# endif
1949}
1950#endif
1951
1952
1953/**
1954 * Disables interrupts (!EFLAGS.IF).
1955 */
1956#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1957DECLASM(void) ASMIntDisable(void);
1958#else
1959DECLINLINE(void) ASMIntDisable(void)
1960{
1961# if RT_INLINE_ASM_GNU_STYLE
1962 __asm("cli\n");
1963# elif RT_INLINE_ASM_USES_INTRIN
1964 _disable();
1965# else
1966 __asm cli
1967# endif
1968}
1969#endif
1970
1971
1972/**
1973 * Disables interrupts and returns previous xFLAGS.
1974 */
1975#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
1976DECLASM(RTCCUINTREG) ASMIntDisableFlags(void);
1977#else
1978DECLINLINE(RTCCUINTREG) ASMIntDisableFlags(void)
1979{
1980 RTCCUINTREG xFlags;
1981# if RT_INLINE_ASM_GNU_STYLE
1982# ifdef RT_ARCH_AMD64
1983 __asm__ __volatile__("pushfq\n\t"
1984 "cli\n\t"
1985 "popq %0\n\t"
1986 : "=r" (xFlags));
1987# else
1988 __asm__ __volatile__("pushfl\n\t"
1989 "cli\n\t"
1990 "popl %0\n\t"
1991 : "=r" (xFlags));
1992# endif
1993# elif RT_INLINE_ASM_USES_INTRIN && !defined(RT_ARCH_X86)
1994 xFlags = ASMGetFlags();
1995 _disable();
1996# else
1997 __asm {
1998 pushfd
1999 cli
2000 pop [xFlags]
2001 }
2002# endif
2003 return xFlags;
2004}
2005#endif
2006
2007
2008/**
2009 * Are interrupts enabled?
2010 *
2011 * @returns true / false.
2012 */
2013DECLINLINE(bool) ASMIntAreEnabled(void)
2014{
2015 RTCCUINTREG uFlags = ASMGetFlags();
2016 return uFlags & 0x200 /* X86_EFL_IF */ ? true : false;
2017}
2018
2019
2020/**
2021 * Halts the CPU until interrupted.
2022 */
2023#if RT_INLINE_ASM_EXTERNAL
2024DECLASM(void) ASMHalt(void);
2025#else
2026DECLINLINE(void) ASMHalt(void)
2027{
2028# if RT_INLINE_ASM_GNU_STYLE
2029 __asm__ __volatile__("hlt\n\t");
2030# else
2031 __asm {
2032 hlt
2033 }
2034# endif
2035}
2036#endif
2037
2038
2039/**
2040 * Reads a machine specific register.
2041 *
2042 * @returns Register content.
2043 * @param uRegister Register to read.
2044 */
2045#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2046DECLASM(uint64_t) ASMRdMsr(uint32_t uRegister);
2047#else
2048DECLINLINE(uint64_t) ASMRdMsr(uint32_t uRegister)
2049{
2050 RTUINT64U u;
2051# if RT_INLINE_ASM_GNU_STYLE
2052 __asm__ __volatile__("rdmsr\n\t"
2053 : "=a" (u.s.Lo),
2054 "=d" (u.s.Hi)
2055 : "c" (uRegister));
2056
2057# elif RT_INLINE_ASM_USES_INTRIN
2058 u.u = __readmsr(uRegister);
2059
2060# else
2061 __asm
2062 {
2063 mov ecx, [uRegister]
2064 rdmsr
2065 mov [u.s.Lo], eax
2066 mov [u.s.Hi], edx
2067 }
2068# endif
2069
2070 return u.u;
2071}
2072#endif
2073
2074
2075/**
2076 * Writes a machine specific register.
2077 *
2078 * @returns Register content.
2079 * @param uRegister Register to write to.
2080 * @param u64Val Value to write.
2081 */
2082#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2083DECLASM(void) ASMWrMsr(uint32_t uRegister, uint64_t u64Val);
2084#else
2085DECLINLINE(void) ASMWrMsr(uint32_t uRegister, uint64_t u64Val)
2086{
2087 RTUINT64U u;
2088
2089 u.u = u64Val;
2090# if RT_INLINE_ASM_GNU_STYLE
2091 __asm__ __volatile__("wrmsr\n\t"
2092 ::"a" (u.s.Lo),
2093 "d" (u.s.Hi),
2094 "c" (uRegister));
2095
2096# elif RT_INLINE_ASM_USES_INTRIN
2097 __writemsr(uRegister, u.u);
2098
2099# else
2100 __asm
2101 {
2102 mov ecx, [uRegister]
2103 mov edx, [u.s.Hi]
2104 mov eax, [u.s.Lo]
2105 wrmsr
2106 }
2107# endif
2108}
2109#endif
2110
2111
2112/**
2113 * Reads a machine specific register, extended version (for AMD).
2114 *
2115 * @returns Register content.
2116 * @param uRegister Register to read.
2117 * @param uXDI RDI/EDI value.
2118 */
2119#if RT_INLINE_ASM_EXTERNAL
2120DECLASM(uint64_t) ASMRdMsrEx(uint32_t uRegister, RTCCUINTREG uXDI);
2121#else
2122DECLINLINE(uint64_t) ASMRdMsrEx(uint32_t uRegister, RTCCUINTREG uXDI)
2123{
2124 RTUINT64U u;
2125# if RT_INLINE_ASM_GNU_STYLE
2126 __asm__ __volatile__("rdmsr\n\t"
2127 : "=a" (u.s.Lo),
2128 "=d" (u.s.Hi)
2129 : "c" (uRegister),
2130 "D" (uXDI));
2131
2132# else
2133 __asm
2134 {
2135 mov ecx, [uRegister]
2136 xchg edi, [uXDI]
2137 rdmsr
2138 mov [u.s.Lo], eax
2139 mov [u.s.Hi], edx
2140 xchg edi, [uXDI]
2141 }
2142# endif
2143
2144 return u.u;
2145}
2146#endif
2147
2148
2149/**
2150 * Writes a machine specific register, extended version (for AMD).
2151 *
2152 * @returns Register content.
2153 * @param uRegister Register to write to.
2154 * @param uXDI RDI/EDI value.
2155 * @param u64Val Value to write.
2156 */
2157#if RT_INLINE_ASM_EXTERNAL
2158DECLASM(void) ASMWrMsrEx(uint32_t uRegister, RTCCUINTREG uXDI, uint64_t u64Val);
2159#else
2160DECLINLINE(void) ASMWrMsrEx(uint32_t uRegister, RTCCUINTREG uXDI, uint64_t u64Val)
2161{
2162 RTUINT64U u;
2163
2164 u.u = u64Val;
2165# if RT_INLINE_ASM_GNU_STYLE
2166 __asm__ __volatile__("wrmsr\n\t"
2167 ::"a" (u.s.Lo),
2168 "d" (u.s.Hi),
2169 "c" (uRegister),
2170 "D" (uXDI));
2171
2172# else
2173 __asm
2174 {
2175 mov ecx, [uRegister]
2176 xchg edi, [uXDI]
2177 mov edx, [u.s.Hi]
2178 mov eax, [u.s.Lo]
2179 wrmsr
2180 xchg edi, [uXDI]
2181 }
2182# endif
2183}
2184#endif
2185
2186
2187
2188/**
2189 * Reads low part of a machine specific register.
2190 *
2191 * @returns Register content.
2192 * @param uRegister Register to read.
2193 */
2194#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2195DECLASM(uint32_t) ASMRdMsr_Low(uint32_t uRegister);
2196#else
2197DECLINLINE(uint32_t) ASMRdMsr_Low(uint32_t uRegister)
2198{
2199 uint32_t u32;
2200# if RT_INLINE_ASM_GNU_STYLE
2201 __asm__ __volatile__("rdmsr\n\t"
2202 : "=a" (u32)
2203 : "c" (uRegister)
2204 : "edx");
2205
2206# elif RT_INLINE_ASM_USES_INTRIN
2207 u32 = (uint32_t)__readmsr(uRegister);
2208
2209#else
2210 __asm
2211 {
2212 mov ecx, [uRegister]
2213 rdmsr
2214 mov [u32], eax
2215 }
2216# endif
2217
2218 return u32;
2219}
2220#endif
2221
2222
2223/**
2224 * Reads high part of a machine specific register.
2225 *
2226 * @returns Register content.
2227 * @param uRegister Register to read.
2228 */
2229#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2230DECLASM(uint32_t) ASMRdMsr_High(uint32_t uRegister);
2231#else
2232DECLINLINE(uint32_t) ASMRdMsr_High(uint32_t uRegister)
2233{
2234 uint32_t u32;
2235# if RT_INLINE_ASM_GNU_STYLE
2236 __asm__ __volatile__("rdmsr\n\t"
2237 : "=d" (u32)
2238 : "c" (uRegister)
2239 : "eax");
2240
2241# elif RT_INLINE_ASM_USES_INTRIN
2242 u32 = (uint32_t)(__readmsr(uRegister) >> 32);
2243
2244# else
2245 __asm
2246 {
2247 mov ecx, [uRegister]
2248 rdmsr
2249 mov [u32], edx
2250 }
2251# endif
2252
2253 return u32;
2254}
2255#endif
2256
2257
2258/**
2259 * Gets dr0.
2260 *
2261 * @returns dr0.
2262 */
2263#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2264DECLASM(RTCCUINTREG) ASMGetDR0(void);
2265#else
2266DECLINLINE(RTCCUINTREG) ASMGetDR0(void)
2267{
2268 RTCCUINTREG uDR0;
2269# if RT_INLINE_ASM_USES_INTRIN
2270 uDR0 = __readdr(0);
2271# elif RT_INLINE_ASM_GNU_STYLE
2272# ifdef RT_ARCH_AMD64
2273 __asm__ __volatile__("movq %%dr0, %0\n\t" : "=r" (uDR0));
2274# else
2275 __asm__ __volatile__("movl %%dr0, %0\n\t" : "=r" (uDR0));
2276# endif
2277# else
2278 __asm
2279 {
2280# ifdef RT_ARCH_AMD64
2281 mov rax, dr0
2282 mov [uDR0], rax
2283# else
2284 mov eax, dr0
2285 mov [uDR0], eax
2286# endif
2287 }
2288# endif
2289 return uDR0;
2290}
2291#endif
2292
2293
2294/**
2295 * Gets dr1.
2296 *
2297 * @returns dr1.
2298 */
2299#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2300DECLASM(RTCCUINTREG) ASMGetDR1(void);
2301#else
2302DECLINLINE(RTCCUINTREG) ASMGetDR1(void)
2303{
2304 RTCCUINTREG uDR1;
2305# if RT_INLINE_ASM_USES_INTRIN
2306 uDR1 = __readdr(1);
2307# elif RT_INLINE_ASM_GNU_STYLE
2308# ifdef RT_ARCH_AMD64
2309 __asm__ __volatile__("movq %%dr1, %0\n\t" : "=r" (uDR1));
2310# else
2311 __asm__ __volatile__("movl %%dr1, %0\n\t" : "=r" (uDR1));
2312# endif
2313# else
2314 __asm
2315 {
2316# ifdef RT_ARCH_AMD64
2317 mov rax, dr1
2318 mov [uDR1], rax
2319# else
2320 mov eax, dr1
2321 mov [uDR1], eax
2322# endif
2323 }
2324# endif
2325 return uDR1;
2326}
2327#endif
2328
2329
2330/**
2331 * Gets dr2.
2332 *
2333 * @returns dr2.
2334 */
2335#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2336DECLASM(RTCCUINTREG) ASMGetDR2(void);
2337#else
2338DECLINLINE(RTCCUINTREG) ASMGetDR2(void)
2339{
2340 RTCCUINTREG uDR2;
2341# if RT_INLINE_ASM_USES_INTRIN
2342 uDR2 = __readdr(2);
2343# elif RT_INLINE_ASM_GNU_STYLE
2344# ifdef RT_ARCH_AMD64
2345 __asm__ __volatile__("movq %%dr2, %0\n\t" : "=r" (uDR2));
2346# else
2347 __asm__ __volatile__("movl %%dr2, %0\n\t" : "=r" (uDR2));
2348# endif
2349# else
2350 __asm
2351 {
2352# ifdef RT_ARCH_AMD64
2353 mov rax, dr2
2354 mov [uDR2], rax
2355# else
2356 mov eax, dr2
2357 mov [uDR2], eax
2358# endif
2359 }
2360# endif
2361 return uDR2;
2362}
2363#endif
2364
2365
2366/**
2367 * Gets dr3.
2368 *
2369 * @returns dr3.
2370 */
2371#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2372DECLASM(RTCCUINTREG) ASMGetDR3(void);
2373#else
2374DECLINLINE(RTCCUINTREG) ASMGetDR3(void)
2375{
2376 RTCCUINTREG uDR3;
2377# if RT_INLINE_ASM_USES_INTRIN
2378 uDR3 = __readdr(3);
2379# elif RT_INLINE_ASM_GNU_STYLE
2380# ifdef RT_ARCH_AMD64
2381 __asm__ __volatile__("movq %%dr3, %0\n\t" : "=r" (uDR3));
2382# else
2383 __asm__ __volatile__("movl %%dr3, %0\n\t" : "=r" (uDR3));
2384# endif
2385# else
2386 __asm
2387 {
2388# ifdef RT_ARCH_AMD64
2389 mov rax, dr3
2390 mov [uDR3], rax
2391# else
2392 mov eax, dr3
2393 mov [uDR3], eax
2394# endif
2395 }
2396# endif
2397 return uDR3;
2398}
2399#endif
2400
2401
2402/**
2403 * Gets dr6.
2404 *
2405 * @returns dr6.
2406 */
2407#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2408DECLASM(RTCCUINTREG) ASMGetDR6(void);
2409#else
2410DECLINLINE(RTCCUINTREG) ASMGetDR6(void)
2411{
2412 RTCCUINTREG uDR6;
2413# if RT_INLINE_ASM_USES_INTRIN
2414 uDR6 = __readdr(6);
2415# elif RT_INLINE_ASM_GNU_STYLE
2416# ifdef RT_ARCH_AMD64
2417 __asm__ __volatile__("movq %%dr6, %0\n\t" : "=r" (uDR6));
2418# else
2419 __asm__ __volatile__("movl %%dr6, %0\n\t" : "=r" (uDR6));
2420# endif
2421# else
2422 __asm
2423 {
2424# ifdef RT_ARCH_AMD64
2425 mov rax, dr6
2426 mov [uDR6], rax
2427# else
2428 mov eax, dr6
2429 mov [uDR6], eax
2430# endif
2431 }
2432# endif
2433 return uDR6;
2434}
2435#endif
2436
2437
2438/**
2439 * Reads and clears DR6.
2440 *
2441 * @returns DR6.
2442 */
2443#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2444DECLASM(RTCCUINTREG) ASMGetAndClearDR6(void);
2445#else
2446DECLINLINE(RTCCUINTREG) ASMGetAndClearDR6(void)
2447{
2448 RTCCUINTREG uDR6;
2449# if RT_INLINE_ASM_USES_INTRIN
2450 uDR6 = __readdr(6);
2451 __writedr(6, 0xffff0ff0U); /* 31-16 and 4-11 are 1's, 12 and 63-31 are zero. */
2452# elif RT_INLINE_ASM_GNU_STYLE
2453 RTCCUINTREG uNewValue = 0xffff0ff0U;/* 31-16 and 4-11 are 1's, 12 and 63-31 are zero. */
2454# ifdef RT_ARCH_AMD64
2455 __asm__ __volatile__("movq %%dr6, %0\n\t"
2456 "movq %1, %%dr6\n\t"
2457 : "=r" (uDR6)
2458 : "r" (uNewValue));
2459# else
2460 __asm__ __volatile__("movl %%dr6, %0\n\t"
2461 "movl %1, %%dr6\n\t"
2462 : "=r" (uDR6)
2463 : "r" (uNewValue));
2464# endif
2465# else
2466 __asm
2467 {
2468# ifdef RT_ARCH_AMD64
2469 mov rax, dr6
2470 mov [uDR6], rax
2471 mov rcx, rax
2472 mov ecx, 0ffff0ff0h; /* 31-16 and 4-11 are 1's, 12 and 63-31 are zero. */
2473 mov dr6, rcx
2474# else
2475 mov eax, dr6
2476 mov [uDR6], eax
2477 mov ecx, 0ffff0ff0h; /* 31-16 and 4-11 are 1's, 12 is zero. */
2478 mov dr6, ecx
2479# endif
2480 }
2481# endif
2482 return uDR6;
2483}
2484#endif
2485
2486
2487/**
2488 * Gets dr7.
2489 *
2490 * @returns dr7.
2491 */
2492#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2493DECLASM(RTCCUINTREG) ASMGetDR7(void);
2494#else
2495DECLINLINE(RTCCUINTREG) ASMGetDR7(void)
2496{
2497 RTCCUINTREG uDR7;
2498# if RT_INLINE_ASM_USES_INTRIN
2499 uDR7 = __readdr(7);
2500# elif RT_INLINE_ASM_GNU_STYLE
2501# ifdef RT_ARCH_AMD64
2502 __asm__ __volatile__("movq %%dr7, %0\n\t" : "=r" (uDR7));
2503# else
2504 __asm__ __volatile__("movl %%dr7, %0\n\t" : "=r" (uDR7));
2505# endif
2506# else
2507 __asm
2508 {
2509# ifdef RT_ARCH_AMD64
2510 mov rax, dr7
2511 mov [uDR7], rax
2512# else
2513 mov eax, dr7
2514 mov [uDR7], eax
2515# endif
2516 }
2517# endif
2518 return uDR7;
2519}
2520#endif
2521
2522
2523/**
2524 * Sets dr0.
2525 *
2526 * @param uDRVal Debug register value to write
2527 */
2528#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2529DECLASM(void) ASMSetDR0(RTCCUINTREG uDRVal);
2530#else
2531DECLINLINE(void) ASMSetDR0(RTCCUINTREG uDRVal)
2532{
2533# if RT_INLINE_ASM_USES_INTRIN
2534 __writedr(0, uDRVal);
2535# elif RT_INLINE_ASM_GNU_STYLE
2536# ifdef RT_ARCH_AMD64
2537 __asm__ __volatile__("movq %0, %%dr0\n\t" : : "r" (uDRVal));
2538# else
2539 __asm__ __volatile__("movl %0, %%dr0\n\t" : : "r" (uDRVal));
2540# endif
2541# else
2542 __asm
2543 {
2544# ifdef RT_ARCH_AMD64
2545 mov rax, [uDRVal]
2546 mov dr0, rax
2547# else
2548 mov eax, [uDRVal]
2549 mov dr0, eax
2550# endif
2551 }
2552# endif
2553}
2554#endif
2555
2556
2557/**
2558 * Sets dr1.
2559 *
2560 * @param uDRVal Debug register value to write
2561 */
2562#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2563DECLASM(void) ASMSetDR1(RTCCUINTREG uDRVal);
2564#else
2565DECLINLINE(void) ASMSetDR1(RTCCUINTREG uDRVal)
2566{
2567# if RT_INLINE_ASM_USES_INTRIN
2568 __writedr(1, uDRVal);
2569# elif RT_INLINE_ASM_GNU_STYLE
2570# ifdef RT_ARCH_AMD64
2571 __asm__ __volatile__("movq %0, %%dr1\n\t" : : "r" (uDRVal));
2572# else
2573 __asm__ __volatile__("movl %0, %%dr1\n\t" : : "r" (uDRVal));
2574# endif
2575# else
2576 __asm
2577 {
2578# ifdef RT_ARCH_AMD64
2579 mov rax, [uDRVal]
2580 mov dr1, rax
2581# else
2582 mov eax, [uDRVal]
2583 mov dr1, eax
2584# endif
2585 }
2586# endif
2587}
2588#endif
2589
2590
2591/**
2592 * Sets dr2.
2593 *
2594 * @param uDRVal Debug register value to write
2595 */
2596#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2597DECLASM(void) ASMSetDR2(RTCCUINTREG uDRVal);
2598#else
2599DECLINLINE(void) ASMSetDR2(RTCCUINTREG uDRVal)
2600{
2601# if RT_INLINE_ASM_USES_INTRIN
2602 __writedr(2, uDRVal);
2603# elif RT_INLINE_ASM_GNU_STYLE
2604# ifdef RT_ARCH_AMD64
2605 __asm__ __volatile__("movq %0, %%dr2\n\t" : : "r" (uDRVal));
2606# else
2607 __asm__ __volatile__("movl %0, %%dr2\n\t" : : "r" (uDRVal));
2608# endif
2609# else
2610 __asm
2611 {
2612# ifdef RT_ARCH_AMD64
2613 mov rax, [uDRVal]
2614 mov dr2, rax
2615# else
2616 mov eax, [uDRVal]
2617 mov dr2, eax
2618# endif
2619 }
2620# endif
2621}
2622#endif
2623
2624
2625/**
2626 * Sets dr3.
2627 *
2628 * @param uDRVal Debug register value to write
2629 */
2630#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2631DECLASM(void) ASMSetDR3(RTCCUINTREG uDRVal);
2632#else
2633DECLINLINE(void) ASMSetDR3(RTCCUINTREG uDRVal)
2634{
2635# if RT_INLINE_ASM_USES_INTRIN
2636 __writedr(3, uDRVal);
2637# elif RT_INLINE_ASM_GNU_STYLE
2638# ifdef RT_ARCH_AMD64
2639 __asm__ __volatile__("movq %0, %%dr3\n\t" : : "r" (uDRVal));
2640# else
2641 __asm__ __volatile__("movl %0, %%dr3\n\t" : : "r" (uDRVal));
2642# endif
2643# else
2644 __asm
2645 {
2646# ifdef RT_ARCH_AMD64
2647 mov rax, [uDRVal]
2648 mov dr3, rax
2649# else
2650 mov eax, [uDRVal]
2651 mov dr3, eax
2652# endif
2653 }
2654# endif
2655}
2656#endif
2657
2658
2659/**
2660 * Sets dr6.
2661 *
2662 * @param uDRVal Debug register value to write
2663 */
2664#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2665DECLASM(void) ASMSetDR6(RTCCUINTREG uDRVal);
2666#else
2667DECLINLINE(void) ASMSetDR6(RTCCUINTREG uDRVal)
2668{
2669# if RT_INLINE_ASM_USES_INTRIN
2670 __writedr(6, uDRVal);
2671# elif RT_INLINE_ASM_GNU_STYLE
2672# ifdef RT_ARCH_AMD64
2673 __asm__ __volatile__("movq %0, %%dr6\n\t" : : "r" (uDRVal));
2674# else
2675 __asm__ __volatile__("movl %0, %%dr6\n\t" : : "r" (uDRVal));
2676# endif
2677# else
2678 __asm
2679 {
2680# ifdef RT_ARCH_AMD64
2681 mov rax, [uDRVal]
2682 mov dr6, rax
2683# else
2684 mov eax, [uDRVal]
2685 mov dr6, eax
2686# endif
2687 }
2688# endif
2689}
2690#endif
2691
2692
2693/**
2694 * Sets dr7.
2695 *
2696 * @param uDRVal Debug register value to write
2697 */
2698#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2699DECLASM(void) ASMSetDR7(RTCCUINTREG uDRVal);
2700#else
2701DECLINLINE(void) ASMSetDR7(RTCCUINTREG uDRVal)
2702{
2703# if RT_INLINE_ASM_USES_INTRIN
2704 __writedr(7, uDRVal);
2705# elif RT_INLINE_ASM_GNU_STYLE
2706# ifdef RT_ARCH_AMD64
2707 __asm__ __volatile__("movq %0, %%dr7\n\t" : : "r" (uDRVal));
2708# else
2709 __asm__ __volatile__("movl %0, %%dr7\n\t" : : "r" (uDRVal));
2710# endif
2711# else
2712 __asm
2713 {
2714# ifdef RT_ARCH_AMD64
2715 mov rax, [uDRVal]
2716 mov dr7, rax
2717# else
2718 mov eax, [uDRVal]
2719 mov dr7, eax
2720# endif
2721 }
2722# endif
2723}
2724#endif
2725
2726
2727/**
2728 * Writes a 8-bit unsigned integer to an I/O port, ordered.
2729 *
2730 * @param Port I/O port to write to.
2731 * @param u8 8-bit integer to write.
2732 */
2733#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2734DECLASM(void) ASMOutU8(RTIOPORT Port, uint8_t u8);
2735#else
2736DECLINLINE(void) ASMOutU8(RTIOPORT Port, uint8_t u8)
2737{
2738# if RT_INLINE_ASM_GNU_STYLE
2739 __asm__ __volatile__("outb %b1, %w0\n\t"
2740 :: "Nd" (Port),
2741 "a" (u8));
2742
2743# elif RT_INLINE_ASM_USES_INTRIN
2744 __outbyte(Port, u8);
2745
2746# else
2747 __asm
2748 {
2749 mov dx, [Port]
2750 mov al, [u8]
2751 out dx, al
2752 }
2753# endif
2754}
2755#endif
2756
2757
2758/**
2759 * Reads a 8-bit unsigned integer from an I/O port, ordered.
2760 *
2761 * @returns 8-bit integer.
2762 * @param Port I/O port to read from.
2763 */
2764#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2765DECLASM(uint8_t) ASMInU8(RTIOPORT Port);
2766#else
2767DECLINLINE(uint8_t) ASMInU8(RTIOPORT Port)
2768{
2769 uint8_t u8;
2770# if RT_INLINE_ASM_GNU_STYLE
2771 __asm__ __volatile__("inb %w1, %b0\n\t"
2772 : "=a" (u8)
2773 : "Nd" (Port));
2774
2775# elif RT_INLINE_ASM_USES_INTRIN
2776 u8 = __inbyte(Port);
2777
2778# else
2779 __asm
2780 {
2781 mov dx, [Port]
2782 in al, dx
2783 mov [u8], al
2784 }
2785# endif
2786 return u8;
2787}
2788#endif
2789
2790
2791/**
2792 * Writes a 16-bit unsigned integer to an I/O port, ordered.
2793 *
2794 * @param Port I/O port to write to.
2795 * @param u16 16-bit integer to write.
2796 */
2797#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2798DECLASM(void) ASMOutU16(RTIOPORT Port, uint16_t u16);
2799#else
2800DECLINLINE(void) ASMOutU16(RTIOPORT Port, uint16_t u16)
2801{
2802# if RT_INLINE_ASM_GNU_STYLE
2803 __asm__ __volatile__("outw %w1, %w0\n\t"
2804 :: "Nd" (Port),
2805 "a" (u16));
2806
2807# elif RT_INLINE_ASM_USES_INTRIN
2808 __outword(Port, u16);
2809
2810# else
2811 __asm
2812 {
2813 mov dx, [Port]
2814 mov ax, [u16]
2815 out dx, ax
2816 }
2817# endif
2818}
2819#endif
2820
2821
2822/**
2823 * Reads a 16-bit unsigned integer from an I/O port, ordered.
2824 *
2825 * @returns 16-bit integer.
2826 * @param Port I/O port to read from.
2827 */
2828#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2829DECLASM(uint16_t) ASMInU16(RTIOPORT Port);
2830#else
2831DECLINLINE(uint16_t) ASMInU16(RTIOPORT Port)
2832{
2833 uint16_t u16;
2834# if RT_INLINE_ASM_GNU_STYLE
2835 __asm__ __volatile__("inw %w1, %w0\n\t"
2836 : "=a" (u16)
2837 : "Nd" (Port));
2838
2839# elif RT_INLINE_ASM_USES_INTRIN
2840 u16 = __inword(Port);
2841
2842# else
2843 __asm
2844 {
2845 mov dx, [Port]
2846 in ax, dx
2847 mov [u16], ax
2848 }
2849# endif
2850 return u16;
2851}
2852#endif
2853
2854
2855/**
2856 * Writes a 32-bit unsigned integer to an I/O port, ordered.
2857 *
2858 * @param Port I/O port to write to.
2859 * @param u32 32-bit integer to write.
2860 */
2861#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2862DECLASM(void) ASMOutU32(RTIOPORT Port, uint32_t u32);
2863#else
2864DECLINLINE(void) ASMOutU32(RTIOPORT Port, uint32_t u32)
2865{
2866# if RT_INLINE_ASM_GNU_STYLE
2867 __asm__ __volatile__("outl %1, %w0\n\t"
2868 :: "Nd" (Port),
2869 "a" (u32));
2870
2871# elif RT_INLINE_ASM_USES_INTRIN
2872 __outdword(Port, u32);
2873
2874# else
2875 __asm
2876 {
2877 mov dx, [Port]
2878 mov eax, [u32]
2879 out dx, eax
2880 }
2881# endif
2882}
2883#endif
2884
2885
2886/**
2887 * Reads a 32-bit unsigned integer from an I/O port, ordered.
2888 *
2889 * @returns 32-bit integer.
2890 * @param Port I/O port to read from.
2891 */
2892#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2893DECLASM(uint32_t) ASMInU32(RTIOPORT Port);
2894#else
2895DECLINLINE(uint32_t) ASMInU32(RTIOPORT Port)
2896{
2897 uint32_t u32;
2898# if RT_INLINE_ASM_GNU_STYLE
2899 __asm__ __volatile__("inl %w1, %0\n\t"
2900 : "=a" (u32)
2901 : "Nd" (Port));
2902
2903# elif RT_INLINE_ASM_USES_INTRIN
2904 u32 = __indword(Port);
2905
2906# else
2907 __asm
2908 {
2909 mov dx, [Port]
2910 in eax, dx
2911 mov [u32], eax
2912 }
2913# endif
2914 return u32;
2915}
2916#endif
2917
2918
2919/**
2920 * Writes a string of 8-bit unsigned integer items to an I/O port, ordered.
2921 *
2922 * @param Port I/O port to write to.
2923 * @param pau8 Pointer to the string buffer.
2924 * @param c The number of items to write.
2925 */
2926#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2927DECLASM(void) ASMOutStrU8(RTIOPORT Port, uint8_t const *pau8, size_t c);
2928#else
2929DECLINLINE(void) ASMOutStrU8(RTIOPORT Port, uint8_t const *pau8, size_t c)
2930{
2931# if RT_INLINE_ASM_GNU_STYLE
2932 __asm__ __volatile__("rep; outsb\n\t"
2933 : "+S" (pau8),
2934 "+c" (c)
2935 : "d" (Port));
2936
2937# elif RT_INLINE_ASM_USES_INTRIN
2938 __outbytestring(Port, (unsigned char *)pau8, (unsigned long)c);
2939
2940# else
2941 __asm
2942 {
2943 mov dx, [Port]
2944 mov ecx, [c]
2945 mov eax, [pau8]
2946 xchg esi, eax
2947 rep outsb
2948 xchg esi, eax
2949 }
2950# endif
2951}
2952#endif
2953
2954
2955/**
2956 * Reads a string of 8-bit unsigned integer items from an I/O port, ordered.
2957 *
2958 * @param Port I/O port to read from.
2959 * @param pau8 Pointer to the string buffer (output).
2960 * @param c The number of items to read.
2961 */
2962#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2963DECLASM(void) ASMInStrU8(RTIOPORT Port, uint8_t *pau8, size_t c);
2964#else
2965DECLINLINE(void) ASMInStrU8(RTIOPORT Port, uint8_t *pau8, size_t c)
2966{
2967# if RT_INLINE_ASM_GNU_STYLE
2968 __asm__ __volatile__("rep; insb\n\t"
2969 : "+D" (pau8),
2970 "+c" (c)
2971 : "d" (Port));
2972
2973# elif RT_INLINE_ASM_USES_INTRIN
2974 __inbytestring(Port, pau8, (unsigned long)c);
2975
2976# else
2977 __asm
2978 {
2979 mov dx, [Port]
2980 mov ecx, [c]
2981 mov eax, [pau8]
2982 xchg edi, eax
2983 rep insb
2984 xchg edi, eax
2985 }
2986# endif
2987}
2988#endif
2989
2990
2991/**
2992 * Writes a string of 16-bit unsigned integer items to an I/O port, ordered.
2993 *
2994 * @param Port I/O port to write to.
2995 * @param pau16 Pointer to the string buffer.
2996 * @param c The number of items to write.
2997 */
2998#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
2999DECLASM(void) ASMOutStrU16(RTIOPORT Port, uint16_t const *pau16, size_t c);
3000#else
3001DECLINLINE(void) ASMOutStrU16(RTIOPORT Port, uint16_t const *pau16, size_t c)
3002{
3003# if RT_INLINE_ASM_GNU_STYLE
3004 __asm__ __volatile__("rep; outsw\n\t"
3005 : "+S" (pau16),
3006 "+c" (c)
3007 : "d" (Port));
3008
3009# elif RT_INLINE_ASM_USES_INTRIN
3010 __outwordstring(Port, (unsigned short *)pau16, (unsigned long)c);
3011
3012# else
3013 __asm
3014 {
3015 mov dx, [Port]
3016 mov ecx, [c]
3017 mov eax, [pau16]
3018 xchg esi, eax
3019 rep outsw
3020 xchg esi, eax
3021 }
3022# endif
3023}
3024#endif
3025
3026
3027/**
3028 * Reads a string of 16-bit unsigned integer items from an I/O port, ordered.
3029 *
3030 * @param Port I/O port to read from.
3031 * @param pau16 Pointer to the string buffer (output).
3032 * @param c The number of items to read.
3033 */
3034#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
3035DECLASM(void) ASMInStrU16(RTIOPORT Port, uint16_t *pau16, size_t c);
3036#else
3037DECLINLINE(void) ASMInStrU16(RTIOPORT Port, uint16_t *pau16, size_t c)
3038{
3039# if RT_INLINE_ASM_GNU_STYLE
3040 __asm__ __volatile__("rep; insw\n\t"
3041 : "+D" (pau16),
3042 "+c" (c)
3043 : "d" (Port));
3044
3045# elif RT_INLINE_ASM_USES_INTRIN
3046 __inwordstring(Port, pau16, (unsigned long)c);
3047
3048# else
3049 __asm
3050 {
3051 mov dx, [Port]
3052 mov ecx, [c]
3053 mov eax, [pau16]
3054 xchg edi, eax
3055 rep insw
3056 xchg edi, eax
3057 }
3058# endif
3059}
3060#endif
3061
3062
3063/**
3064 * Writes a string of 32-bit unsigned integer items to an I/O port, ordered.
3065 *
3066 * @param Port I/O port to write to.
3067 * @param pau32 Pointer to the string buffer.
3068 * @param c The number of items to write.
3069 */
3070#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
3071DECLASM(void) ASMOutStrU32(RTIOPORT Port, uint32_t const *pau32, size_t c);
3072#else
3073DECLINLINE(void) ASMOutStrU32(RTIOPORT Port, uint32_t const *pau32, size_t c)
3074{
3075# if RT_INLINE_ASM_GNU_STYLE
3076 __asm__ __volatile__("rep; outsl\n\t"
3077 : "+S" (pau32),
3078 "+c" (c)
3079 : "d" (Port));
3080
3081# elif RT_INLINE_ASM_USES_INTRIN
3082 __outdwordstring(Port, (unsigned long *)pau32, (unsigned long)c);
3083
3084# else
3085 __asm
3086 {
3087 mov dx, [Port]
3088 mov ecx, [c]
3089 mov eax, [pau32]
3090 xchg esi, eax
3091 rep outsd
3092 xchg esi, eax
3093 }
3094# endif
3095}
3096#endif
3097
3098
3099/**
3100 * Reads a string of 32-bit unsigned integer items from an I/O port, ordered.
3101 *
3102 * @param Port I/O port to read from.
3103 * @param pau32 Pointer to the string buffer (output).
3104 * @param c The number of items to read.
3105 */
3106#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
3107DECLASM(void) ASMInStrU32(RTIOPORT Port, uint32_t *pau32, size_t c);
3108#else
3109DECLINLINE(void) ASMInStrU32(RTIOPORT Port, uint32_t *pau32, size_t c)
3110{
3111# if RT_INLINE_ASM_GNU_STYLE
3112 __asm__ __volatile__("rep; insl\n\t"
3113 : "+D" (pau32),
3114 "+c" (c)
3115 : "d" (Port));
3116
3117# elif RT_INLINE_ASM_USES_INTRIN
3118 __indwordstring(Port, (unsigned long *)pau32, (unsigned long)c);
3119
3120# else
3121 __asm
3122 {
3123 mov dx, [Port]
3124 mov ecx, [c]
3125 mov eax, [pau32]
3126 xchg edi, eax
3127 rep insd
3128 xchg edi, eax
3129 }
3130# endif
3131}
3132#endif
3133
3134
3135/**
3136 * Invalidate page.
3137 *
3138 * @param pv Address of the page to invalidate.
3139 */
3140#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
3141DECLASM(void) ASMInvalidatePage(void *pv);
3142#else
3143DECLINLINE(void) ASMInvalidatePage(void *pv)
3144{
3145# if RT_INLINE_ASM_USES_INTRIN
3146 __invlpg(pv);
3147
3148# elif RT_INLINE_ASM_GNU_STYLE
3149 __asm__ __volatile__("invlpg %0\n\t"
3150 : : "m" (*(uint8_t *)pv));
3151# else
3152 __asm
3153 {
3154# ifdef RT_ARCH_AMD64
3155 mov rax, [pv]
3156 invlpg [rax]
3157# else
3158 mov eax, [pv]
3159 invlpg [eax]
3160# endif
3161 }
3162# endif
3163}
3164#endif
3165
3166
3167/**
3168 * Write back the internal caches and invalidate them.
3169 */
3170#if RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN
3171DECLASM(void) ASMWriteBackAndInvalidateCaches(void);
3172#else
3173DECLINLINE(void) ASMWriteBackAndInvalidateCaches(void)
3174{
3175# if RT_INLINE_ASM_USES_INTRIN
3176 __wbinvd();
3177
3178# elif RT_INLINE_ASM_GNU_STYLE
3179 __asm__ __volatile__("wbinvd");
3180# else
3181 __asm
3182 {
3183 wbinvd
3184 }
3185# endif
3186}
3187#endif
3188
3189
3190/**
3191 * Invalidate internal and (perhaps) external caches without first
3192 * flushing dirty cache lines. Use with extreme care.
3193 */
3194#if RT_INLINE_ASM_EXTERNAL
3195DECLASM(void) ASMInvalidateInternalCaches(void);
3196#else
3197DECLINLINE(void) ASMInvalidateInternalCaches(void)
3198{
3199# if RT_INLINE_ASM_GNU_STYLE
3200 __asm__ __volatile__("invd");
3201# else
3202 __asm
3203 {
3204 invd
3205 }
3206# endif
3207}
3208#endif
3209
3210
3211/**
3212 * Memory load/store fence, waits for any pending writes and reads to complete.
3213 * Requires the X86_CPUID_FEATURE_EDX_SSE2 CPUID bit set.
3214 */
3215DECLINLINE(void) ASMMemoryFenceSSE2(void)
3216{
3217#if RT_INLINE_ASM_GNU_STYLE
3218 __asm__ __volatile__ (".byte 0x0f,0xae,0xf0\n\t");
3219#elif RT_INLINE_ASM_USES_INTRIN
3220 _mm_mfence();
3221#else
3222 __asm
3223 {
3224 _emit 0x0f
3225 _emit 0xae
3226 _emit 0xf0
3227 }
3228#endif
3229}
3230
3231
3232/**
3233 * Memory store fence, waits for any writes to complete.
3234 * Requires the X86_CPUID_FEATURE_EDX_SSE CPUID bit set.
3235 */
3236DECLINLINE(void) ASMWriteFenceSSE(void)
3237{
3238#if RT_INLINE_ASM_GNU_STYLE
3239 __asm__ __volatile__ (".byte 0x0f,0xae,0xf8\n\t");
3240#elif RT_INLINE_ASM_USES_INTRIN
3241 _mm_sfence();
3242#else
3243 __asm
3244 {
3245 _emit 0x0f
3246 _emit 0xae
3247 _emit 0xf8
3248 }
3249#endif
3250}
3251
3252
3253/**
3254 * Memory load fence, waits for any pending reads to complete.
3255 * Requires the X86_CPUID_FEATURE_EDX_SSE2 CPUID bit set.
3256 */
3257DECLINLINE(void) ASMReadFenceSSE2(void)
3258{
3259#if RT_INLINE_ASM_GNU_STYLE
3260 __asm__ __volatile__ (".byte 0x0f,0xae,0xe8\n\t");
3261#elif RT_INLINE_ASM_USES_INTRIN
3262 _mm_lfence();
3263#else
3264 __asm
3265 {
3266 _emit 0x0f
3267 _emit 0xae
3268 _emit 0xe8
3269 }
3270#endif
3271}
3272
3273#if !defined(_MSC_VER) || !defined(RT_ARCH_AMD64)
3274
3275/*
3276 * Clear the AC bit in the EFLAGS register.
3277 * Requires the X86_CPUID_STEXT_FEATURE_EBX_SMAP CPUID bit set.
3278 * Requires to be executed in R0.
3279 */
3280DECLINLINE(void) ASMClearAC(void)
3281{
3282#if RT_INLINE_ASM_GNU_STYLE
3283 __asm__ __volatile__ (".byte 0x0f,0x01,0xca\n\t");
3284#else
3285 __asm
3286 {
3287 _emit 0x0f
3288 _emit 0x01
3289 _emit 0xca
3290 }
3291#endif
3292}
3293
3294
3295/*
3296 * Set the AC bit in the EFLAGS register.
3297 * Requires the X86_CPUID_STEXT_FEATURE_EBX_SMAP CPUID bit set.
3298 * Requires to be executed in R0.
3299 */
3300DECLINLINE(void) ASMSetAC(void)
3301{
3302#if RT_INLINE_ASM_GNU_STYLE
3303 __asm__ __volatile__ (".byte 0x0f,0x01,0xcb\n\t");
3304#else
3305 __asm
3306 {
3307 _emit 0x0f
3308 _emit 0x01
3309 _emit 0xcb
3310 }
3311#endif
3312}
3313
3314#endif /* !_MSC_VER) || !RT_ARCH_AMD64 */
3315
3316/** @} */
3317#endif
3318
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette