VirtualBox

source: vbox/trunk/include/iprt/armv8.h@ 101102

Last change on this file since 101102 was 101102, checked in by vboxsync, 15 months ago

include/iprt/armv8.h: Change the ARMV8_ID_AA64*_EL1 register definitions to make them usable with the RT_BF_* macros, bugref:10525
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1/** @file
2 * IPRT - ARMv8 (AArch64 and AArch32) Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2023 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef IPRT_INCLUDED_armv8_h
37#define IPRT_INCLUDED_armv8_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#ifndef VBOX_FOR_DTRACE_LIB
43# include <iprt/types.h>
44# include <iprt/assert.h>
45#else
46# pragma D depends_on library vbox-types.d
47#endif
48
49/** @defgroup grp_rt_armv8 ARMv8 Types and Definitions
50 * @ingroup grp_rt
51 * @{
52 */
53
54/** @name The AArch64 register encoding.
55 * @{ */
56#define ARMV8_AARCH64_REG_X0 0
57#define ARMV8_AARCH64_REG_W0 ARMV8_AARCH64_REG_X0
58#define ARMV8_AARCH64_REG_X1 1
59#define ARMV8_AARCH64_REG_W1 ARMV8_AARCH64_REG_X1
60#define ARMV8_AARCH64_REG_X2 2
61#define ARMV8_AARCH64_REG_W2 ARMV8_AARCH64_REG_X2
62#define ARMV8_AARCH64_REG_X3 3
63#define ARMV8_AARCH64_REG_W3 ARMV8_AARCH64_REG_X3
64#define ARMV8_AARCH64_REG_X4 4
65#define ARMV8_AARCH64_REG_W4 ARMV8_AARCH64_REG_X4
66#define ARMV8_AARCH64_REG_X5 5
67#define ARMV8_AARCH64_REG_W5 ARMV8_AARCH64_REG_X5
68#define ARMV8_AARCH64_REG_X6 6
69#define ARMV8_AARCH64_REG_W6 ARMV8_AARCH64_REG_X6
70#define ARMV8_AARCH64_REG_X7 7
71#define ARMV8_AARCH64_REG_W7 ARMV8_AARCH64_REG_X7
72#define ARMV8_AARCH64_REG_X8 8
73#define ARMV8_AARCH64_REG_W8 ARMV8_AARCH64_REG_X8
74#define ARMV8_AARCH64_REG_X9 9
75#define ARMV8_AARCH64_REG_W9 ARMV8_AARCH64_REG_X9
76#define ARMV8_AARCH64_REG_X10 10
77#define ARMV8_AARCH64_REG_W10 ARMV8_AARCH64_REG_X10
78#define ARMV8_AARCH64_REG_X11 11
79#define ARMV8_AARCH64_REG_W11 ARMV8_AARCH64_REG_X11
80#define ARMV8_AARCH64_REG_X12 12
81#define ARMV8_AARCH64_REG_W12 ARMV8_AARCH64_REG_X12
82#define ARMV8_AARCH64_REG_X13 13
83#define ARMV8_AARCH64_REG_W13 ARMV8_AARCH64_REG_X13
84#define ARMV8_AARCH64_REG_X14 14
85#define ARMV8_AARCH64_REG_W14 ARMV8_AARCH64_REG_X14
86#define ARMV8_AARCH64_REG_X15 15
87#define ARMV8_AARCH64_REG_W15 ARMV8_AARCH64_REG_X15
88#define ARMV8_AARCH64_REG_X16 16
89#define ARMV8_AARCH64_REG_W16 ARMV8_AARCH64_REG_X16
90#define ARMV8_AARCH64_REG_X17 17
91#define ARMV8_AARCH64_REG_W17 ARMV8_AARCH64_REG_X17
92#define ARMV8_AARCH64_REG_X18 18
93#define ARMV8_AARCH64_REG_W18 ARMV8_AARCH64_REG_X18
94#define ARMV8_AARCH64_REG_X19 19
95#define ARMV8_AARCH64_REG_W19 ARMV8_AARCH64_REG_X19
96#define ARMV8_AARCH64_REG_X20 20
97#define ARMV8_AARCH64_REG_W20 ARMV8_AARCH64_REG_X20
98#define ARMV8_AARCH64_REG_X21 21
99#define ARMV8_AARCH64_REG_W21 ARMV8_AARCH64_REG_X21
100#define ARMV8_AARCH64_REG_X22 22
101#define ARMV8_AARCH64_REG_W22 ARMV8_AARCH64_REG_X22
102#define ARMV8_AARCH64_REG_X23 23
103#define ARMV8_AARCH64_REG_W23 ARMV8_AARCH64_REG_X23
104#define ARMV8_AARCH64_REG_X24 24
105#define ARMV8_AARCH64_REG_W24 ARMV8_AARCH64_REG_X24
106#define ARMV8_AARCH64_REG_X25 25
107#define ARMV8_AARCH64_REG_W25 ARMV8_AARCH64_REG_X25
108#define ARMV8_AARCH64_REG_X26 26
109#define ARMV8_AARCH64_REG_W26 ARMV8_AARCH64_REG_X26
110#define ARMV8_AARCH64_REG_X27 27
111#define ARMV8_AARCH64_REG_W27 ARMV8_AARCH64_REG_X27
112#define ARMV8_AARCH64_REG_X28 28
113#define ARMV8_AARCH64_REG_W28 ARMV8_AARCH64_REG_X28
114#define ARMV8_AARCH64_REG_X29 29
115#define ARMV8_AARCH64_REG_W29 ARMV8_AARCH64_REG_X29
116#define ARMV8_AARCH64_REG_X30 30
117#define ARMV8_AARCH64_REG_W30 ARMV8_AARCH64_REG_X30
118/** The zero register. */
119#define ARMV8_AARCH64_REG_ZR 31
120/** @} */
121
122
123/** @name System register encoding.
124 * @{
125 */
126/** Mask for the op0 part of an MSR/MRS instruction */
127#define ARMV8_AARCH64_SYSREG_OP0_MASK (RT_BIT_32(19) | RT_BIT_32(20))
128/** Shift for the op0 part of an MSR/MRS instruction */
129#define ARMV8_AARCH64_SYSREG_OP0_SHIFT 19
130/** Returns the op0 part of the given MRS/MSR instruction. */
131#define ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP0_MASK) >> ARMV8_AARCH64_SYSREG_OP0_SHIFT)
132/** Mask for the op1 part of an MSR/MRS instruction */
133#define ARMV8_AARCH64_SYSREG_OP1_MASK (RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18))
134/** Shift for the op1 part of an MSR/MRS instruction */
135#define ARMV8_AARCH64_SYSREG_OP1_SHIFT 16
136/** Returns the op1 part of the given MRS/MSR instruction. */
137#define ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP1_MASK) >> ARMV8_AARCH64_SYSREG_OP1_SHIFT)
138/** Mask for the CRn part of an MSR/MRS instruction */
139#define ARMV8_AARCH64_SYSREG_CRN_MASK ( RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) \
140 | RT_BIT_32(15) )
141/** Shift for the CRn part of an MSR/MRS instruction */
142#define ARMV8_AARCH64_SYSREG_CRN_SHIFT 12
143/** Returns the CRn part of the given MRS/MSR instruction. */
144#define ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRN_MASK) >> ARMV8_AARCH64_SYSREG_CRN_SHIFT)
145/** Mask for the CRm part of an MSR/MRS instruction */
146#define ARMV8_AARCH64_SYSREG_CRM_MASK ( RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) \
147 | RT_BIT_32(11) )
148/** Shift for the CRm part of an MSR/MRS instruction */
149#define ARMV8_AARCH64_SYSREG_CRM_SHIFT 8
150/** Returns the CRn part of the given MRS/MSR instruction. */
151#define ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRM_MASK) >> ARMV8_AARCH64_SYSREG_CRM_SHIFT)
152/** Mask for the op2 part of an MSR/MRS instruction */
153#define ARMV8_AARCH64_SYSREG_OP2_MASK (RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7))
154/** Shift for the op2 part of an MSR/MRS instruction */
155#define ARMV8_AARCH64_SYSREG_OP2_SHIFT 5
156/** Returns the op2 part of the given MRS/MSR instruction. */
157#define ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP2_MASK) >> ARMV8_AARCH64_SYSREG_OP2_SHIFT)
158/** Mask for all system register encoding relevant fields in an MRS/MSR instruction. */
159#define ARMV8_AARCH64_SYSREG_MASK ( ARMV8_AARCH64_SYSREG_OP0_MASK | ARMV8_AARCH64_SYSREG_OP1_MASK \
160 | ARMV8_AARCH64_SYSREG_CRN_MASK | ARMV8_AARCH64_SYSREG_CRN_MASK \
161 | ARMV8_AARCH64_SYSREG_OP2_MASK)
162/** @} */
163
164/** @name Mapping of op0:op1:CRn:CRm:op2 to a system register ID. This is
165 * IPRT specific and not part of the ARMv8 specification. */
166#define ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
167 UINT16_C( (((a_Op0) & 0x3) << 14) \
168 | (((a_Op1) & 0x7) << 11) \
169 | (((a_CRn) & 0xf) << 7) \
170 | (((a_CRm) & 0xf) << 3) \
171 | ((a_Op2) & 0x7))
172/** Returns the internal system register ID from the given MRS/MSR instruction. */
173#define ARMV8_AARCH64_SYSREG_ID_FROM_MRS_MSR(a_MsrMrsInsn) \
174 ARMV8_AARCH64_SYSREG_ID_CREATE(ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn), \
175 ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn), \
176 ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn), \
177 ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn), \
178 ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn))
179/** Encodes the given system register ID in the given MSR/MRS instruction. */
180#define ARMV8_AARCH64_SYSREG_ID_ENCODE_IN_MRS_MSR(a_MsrMrsInsn, a_SysregId) \
181 ((a_MsrMrsInsn) = ((a_MsrMrsInsn) & ~ARMV8_AARCH64_SYSREG_MASK) | (a_SysregId << ARMV8_AARCH64_SYSREG_OP2_SHIFT))
182/** @} */
183
184
185/** @name System register IDs.
186 * @{ */
187/** OSLAR_EL1 register - WO. */
188#define ARMV8_AARCH64_SYSREG_OSLAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 4)
189/** OSLSR_EL1 register - RO. */
190#define ARMV8_AARCH64_SYSREG_OSLSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 1, 4)
191/** OSDLR_EL1 register - RW. */
192#define ARMV8_AARCH64_SYSREG_OSDLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 3, 4)
193
194/** MIDR_EL1 register - RO. */
195#define ARMV8_AARCH64_SYSREG_MIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 0)
196/** MIPDR_EL1 register - RO. */
197#define ARMV8_AARCH64_SYSREG_MPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 5)
198/** REVIDR_EL1 register - RO. */
199#define ARMV8_AARCH64_SYSREG_REVIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 6)
200/** ID_PFR0_EL1 register - RO. */
201#define ARMV8_AARCH64_SYSREG_ID_PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 0)
202/** ID_PFR1_EL1 register - RO. */
203#define ARMV8_AARCH64_SYSREG_ID_PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 1)
204/** ID_DFR0_EL1 register - RO. */
205#define ARMV8_AARCH64_SYSREG_ID_DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 2)
206/** ID_AFR0_EL1 register - RO. */
207#define ARMV8_AARCH64_SYSREG_ID_AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 3)
208/** ID_MMFR0_EL1 register - RO. */
209#define ARMV8_AARCH64_SYSREG_ID_MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 4)
210/** ID_MMFR1_EL1 register - RO. */
211#define ARMV8_AARCH64_SYSREG_ID_MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 5)
212/** ID_MMFR2_EL1 register - RO. */
213#define ARMV8_AARCH64_SYSREG_ID_MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 6)
214/** ID_MMFR3_EL1 register - RO. */
215#define ARMV8_AARCH64_SYSREG_ID_MMFR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 7)
216
217/** ID_ISAR0_EL1 register - RO. */
218#define ARMV8_AARCH64_SYSREG_ID_ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 0)
219/** ID_ISAR1_EL1 register - RO. */
220#define ARMV8_AARCH64_SYSREG_ID_ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 1)
221/** ID_ISAR2_EL1 register - RO. */
222#define ARMV8_AARCH64_SYSREG_ID_ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 2)
223/** ID_ISAR3_EL1 register - RO. */
224#define ARMV8_AARCH64_SYSREG_ID_ISAR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 3)
225/** ID_ISAR4_EL1 register - RO. */
226#define ARMV8_AARCH64_SYSREG_ID_ISAR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 4)
227/** ID_ISAR5_EL1 register - RO. */
228#define ARMV8_AARCH64_SYSREG_ID_ISAR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 5)
229/** ID_MMFR4_EL1 register - RO. */
230#define ARMV8_AARCH64_SYSREG_ID_MMFR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 6)
231/** ID_ISAR6_EL1 register - RO. */
232#define ARMV8_AARCH64_SYSREG_ID_ISAR6_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 7)
233
234/** MVFR0_EL1 register - RO. */
235#define ARMV8_AARCH64_SYSREG_MVFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 0)
236/** MVFR1_EL1 register - RO. */
237#define ARMV8_AARCH64_SYSREG_MVFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 1)
238/** MVFR2_EL1 register - RO. */
239#define ARMV8_AARCH64_SYSREG_MVFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 2)
240/** ID_PFR2_EL1 register - RO. */
241#define ARMV8_AARCH64_SYSREG_ID_PFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 4)
242/** ID_DFR1_EL1 register - RO. */
243#define ARMV8_AARCH64_SYSREG_ID_DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 5)
244/** ID_MMFR5_EL1 register - RO. */
245#define ARMV8_AARCH64_SYSREG_ID_MMFR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 6)
246
247/** ID_AA64PFR0_EL1 register - RO. */
248#define ARMV8_AARCH64_SYSREG_ID_AA64PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 0)
249/** ID_AA64PFR0_EL1 register - RO. */
250#define ARMV8_AARCH64_SYSREG_ID_AA64PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 1)
251/** ID_AA64ZFR0_EL1 register - RO. */
252#define ARMV8_AARCH64_SYSREG_ID_AA64ZFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 4)
253/** ID_AA64SMFR0_EL1 register - RO. */
254#define ARMV8_AARCH64_SYSREG_ID_AA64SMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 5)
255
256/** ID_AA64DFR0_EL1 register - RO. */
257#define ARMV8_AARCH64_SYSREG_ID_AA64DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 0)
258/** ID_AA64DFR0_EL1 register - RO. */
259#define ARMV8_AARCH64_SYSREG_ID_AA64DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 1)
260/** ID_AA64AFR0_EL1 register - RO. */
261#define ARMV8_AARCH64_SYSREG_ID_AA64AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 4)
262/** ID_AA64AFR1_EL1 register - RO. */
263#define ARMV8_AARCH64_SYSREG_ID_AA64AFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 5)
264
265/** ID_AA64ISAR0_EL1 register - RO. */
266#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 0)
267/** ID_AA64ISAR1_EL1 register - RO. */
268#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 1)
269/** ID_AA64ISAR2_EL1 register - RO. */
270#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 2)
271
272/** ID_AA64MMFR0_EL1 register - RO. */
273#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 0)
274/** ID_AA64MMFR1_EL1 register - RO. */
275#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 1)
276/** ID_AA64MMFR2_EL1 register - RO. */
277#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 2)
278
279/** SCTRL_EL1 register - RW. */
280#define ARMV8_AARCH64_SYSREG_SCTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 0)
281/** ACTRL_EL1 register - RW. */
282#define ARMV8_AARCH64_SYSREG_ACTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 1)
283/** CPACR_EL1 register - RW. */
284#define ARMV8_AARCH64_SYSREG_CPACR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 2)
285/** RGSR_EL1 register - RW. */
286#define ARMV8_AARCH64_SYSREG_RGSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 5)
287/** GCR_EL1 register - RW. */
288#define ARMV8_AARCH64_SYSREG_GCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 6)
289
290/** ZCR_EL1 register - RW. */
291#define ARMV8_AARCH64_SYSREG_ZCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 0)
292/** TRFCR_EL1 register - RW. */
293#define ARMV8_AARCH64_SYSREG_TRFCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 1)
294/** SMPRI_EL1 register - RW. */
295#define ARMV8_AARCH64_SYSREG_SMPRI_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 4)
296/** SMCR_EL1 register - RW. */
297#define ARMV8_AARCH64_SYSREG_SMCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 6)
298
299/** TTBR0_EL1 register - RW. */
300#define ARMV8_AARCH64_SYSREG_TTBR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 0)
301/** TTBR1_EL1 register - RW. */
302#define ARMV8_AARCH64_SYSREG_TTBR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 1)
303/** TCR_EL1 register - RW. */
304#define ARMV8_AARCH64_SYSREG_TCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 2)
305
306/** @todo APIA,APIB,APDA,APDB,APGA registers. */
307
308/** SPSR_EL1 register - RW. */
309#define ARMV8_AARCH64_SYSREG_SPSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 0)
310/** ELR_EL1 register - RW. */
311#define ARMV8_AARCH64_SYSREG_ELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 1)
312
313/** SP_EL0 register - RW. */
314#define ARMV8_AARCH64_SYSREG_SP_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 1, 0)
315
316/** PSTATE.SPSel value. */
317#define ARMV8_AARCH64_SYSREG_SPSEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 0)
318/** PSTATE.CurrentEL value. */
319#define ARMV8_AARCH64_SYSREG_CURRENTEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 2)
320/** PSTATE.PAN value. */
321#define ARMV8_AARCH64_SYSREG_PAN ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 3)
322/** PSTATE.UAO value. */
323#define ARMV8_AARCH64_SYSREG_UAO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 4)
324
325/** PSTATE.ALLINT value. */
326#define ARMV8_AARCH64_SYSREG_ALLINT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 3, 0)
327
328/** ICC_PMR_EL1 register - RW. */
329#define ARMV8_AARCH64_SYSREG_ICC_PMR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 6, 0)
330
331/** AFSR0_EL1 register - RW. */
332#define ARMV8_AARCH64_SYSREG_AFSR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 0)
333/** AFSR1_EL1 register - RW. */
334#define ARMV8_AARCH64_SYSREG_AFSR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 1)
335
336/** ESR_EL1 register - RW. */
337#define ARMV8_AARCH64_SYSREG_ESR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 2, 0)
338
339/** ERRIDR_EL1 register - RO. */
340#define ARMV8_AARCH64_SYSREG_ERRIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 0)
341/** ERRSELR_EL1 register - RW. */
342#define ARMV8_AARCH64_SYSREG_ERRSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 1)
343
344/** ICC_IAR0_EL1 register - RO. */
345#define ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 0)
346/** ICC_EOIR0_EL1 register - WO. */
347#define ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 1)
348/** ICC_HPPIR0_EL1 register - WO. */
349#define ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 2)
350/** ICC_BPR0_EL1 register - RW. */
351#define ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 3)
352/** ICC_AP0R0_EL1 register - RW. */
353#define ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 4)
354/** ICC_AP0R1_EL1 register - RW. */
355#define ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 5)
356/** ICC_AP0R2_EL1 register - RW. */
357#define ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 6)
358/** ICC_AP0R3_EL1 register - RW. */
359#define ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 7)
360
361/** ICC_AP1R0_EL1 register - RW. */
362#define ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 0)
363/** ICC_AP1R1_EL1 register - RW. */
364#define ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 1)
365/** ICC_AP1R2_EL1 register - RW. */
366#define ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 2)
367/** ICC_AP1R3_EL1 register - RW. */
368#define ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 3)
369/** ICC_NMIAR1_EL1 register - RO. */
370#define ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 5)
371
372/** ICC_DIR_EL1 register - WO. */
373#define ARMV8_AARCH64_SYSREG_ICC_DIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 1)
374/** ICC_RPR_EL1 register - RO. */
375#define ARMV8_AARCH64_SYSREG_ICC_RPR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 3)
376/** ICC_SGI1R_EL1 register - WO. */
377#define ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 5)
378/** ICC_ASGI1R_EL1 register - WO. */
379#define ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 6)
380/** ICC_SGI0R_EL1 register - WO. */
381#define ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 7)
382
383/** ICC_IAR1_EL1 register - RO. */
384#define ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 0)
385/** ICC_EOIR1_EL1 register - WO. */
386#define ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 1)
387/** ICC_HPPIR1_EL1 register - RO. */
388#define ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 2)
389/** ICC_BPR1_EL1 register - RW. */
390#define ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 3)
391/** ICC_CTLR_EL1 register - RW. */
392#define ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 4)
393/** ICC_SRE_EL1 register - RW. */
394#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 5)
395/** ICC_IGRPEN0_EL1 register - RW. */
396#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 6)
397/** ICC_IGRPEN1_EL1 register - RW. */
398#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 7)
399
400/** CNTV_CTL_EL0 register - RW. */
401#define ARMV8_AARCH64_SYSREG_CNTV_CTL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 3, 1)
402/** @} */
403
404
405/**
406 * SPSR_EL2 (according to chapter C5.2.19)
407 */
408typedef union ARMV8SPSREL2
409{
410 /** The plain unsigned view. */
411 uint64_t u;
412 /** The 8-bit view. */
413 uint8_t au8[8];
414 /** The 16-bit view. */
415 uint16_t au16[4];
416 /** The 32-bit view. */
417 uint32_t au32[2];
418 /** The 64-bit view. */
419 uint64_t u64;
420} ARMV8SPSREL2;
421/** Pointer to SPSR_EL2. */
422typedef ARMV8SPSREL2 *PARMV8SPSREL2;
423/** Pointer to const SPSR_EL2. */
424typedef const ARMV8SPSREL2 *PCXARMV8SPSREL2;
425
426
427/** @name SPSR_EL2 (When exception is taken from AArch64 state)
428 * @{
429 */
430/** Bit 0 - 3 - M - AArch64 Exception level and selected stack pointer. */
431#define ARMV8_SPSR_EL2_AARCH64_M (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
432#define ARMV8_SPSR_EL2_AARCH64_GET_M(a_Spsr) ((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M)
433/** Bit 0 - SP - Selected stack pointer. */
434#define ARMV8_SPSR_EL2_AARCH64_SP RT_BIT_64(0)
435#define ARMV8_SPSR_EL2_AARCH64_SP_BIT 0
436/** Bit 1 - Reserved (read as zero). */
437#define ARMV8_SPSR_EL2_AARCH64_RSVD_1 RT_BIT_64(1)
438/** Bit 2 - 3 - EL - Exception level. */
439#define ARMV8_SPSR_EL2_AARCH64_EL (RT_BIT_64(2) | RT_BIT_64(3))
440#define ARMV8_SPSR_EL2_AARCH64_EL_SHIFT 2
441#define ARMV8_SPSR_EL2_AARCH64_GET_EL(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_EL_SHIFT) & 3)
442#define ARMV8_SPSR_EL2_AARCH64_SET_EL(a_El) ((a_El) << ARMV8_SPSR_EL2_AARCH64_EL_SHIFT)
443/** Bit 4 - M[4] - Execution state (0 means AArch64, when 1 this contains a AArch32 state). */
444#define ARMV8_SPSR_EL2_AARCH64_M4 RT_BIT_64(4)
445#define ARMV8_SPSR_EL2_AARCH64_M4_BIT 4
446/** Bit 5 - T - T32 instruction set state (only valid when ARMV8_SPSR_EL2_AARCH64_M4 is set). */
447#define ARMV8_SPSR_EL2_AARCH64_T RT_BIT_64(5)
448#define ARMV8_SPSR_EL2_AARCH64_T_BIT 5
449/** Bit 6 - I - FIQ interrupt mask. */
450#define ARMV8_SPSR_EL2_AARCH64_F RT_BIT_64(6)
451#define ARMV8_SPSR_EL2_AARCH64_F_BIT 6
452/** Bit 7 - I - IRQ interrupt mask. */
453#define ARMV8_SPSR_EL2_AARCH64_I RT_BIT_64(7)
454#define ARMV8_SPSR_EL2_AARCH64_I_BIT 7
455/** Bit 8 - A - SError interrupt mask. */
456#define ARMV8_SPSR_EL2_AARCH64_A RT_BIT_64(8)
457#define ARMV8_SPSR_EL2_AARCH64_A_BIT 8
458/** Bit 9 - D - Debug Exception mask. */
459#define ARMV8_SPSR_EL2_AARCH64_D RT_BIT_64(9)
460#define ARMV8_SPSR_EL2_AARCH64_D_BIT 9
461/** Bit 10 - 11 - BTYPE - Branch Type indicator. */
462#define ARMV8_SPSR_EL2_AARCH64_BYTPE (RT_BIT_64(10) | RT_BIT_64(11))
463#define ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT 10
464#define ARMV8_SPSR_EL2_AARCH64_GET_BYTPE(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT) & 3)
465/** Bit 12 - SSBS - Speculative Store Bypass. */
466#define ARMV8_SPSR_EL2_AARCH64_SSBS RT_BIT_64(12)
467#define ARMV8_SPSR_EL2_AARCH64_SSBS_BIT 12
468/** Bit 13 - ALLINT - All IRQ or FIQ interrupts mask. */
469#define ARMV8_SPSR_EL2_AARCH64_ALLINT RT_BIT_64(13)
470#define ARMV8_SPSR_EL2_AARCH64_ALLINT_BIT 13
471/** Bit 14 - 19 - Reserved (read as zero). */
472#define ARMV8_SPSR_EL2_AARCH64_RSVD_14_19 ( RT_BIT_64(14) | RT_BIT_64(15) | RT_BIT_64(16) \
473 | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
474/** Bit 20 - IL - Illegal Execution State flag. */
475#define ARMV8_SPSR_EL2_AARCH64_IL RT_BIT_64(20)
476#define ARMV8_SPSR_EL2_AARCH64_IL_BIT 20
477/** Bit 21 - SS - Software Step flag. */
478#define ARMV8_SPSR_EL2_AARCH64_SS RT_BIT_64(21)
479#define ARMV8_SPSR_EL2_AARCH64_SS_BIT 21
480/** Bit 22 - PAN - Privileged Access Never flag. */
481#define ARMV8_SPSR_EL2_AARCH64_PAN RT_BIT_64(25)
482#define ARMV8_SPSR_EL2_AARCH64_PAN_BIT 22
483/** Bit 23 - UAO - User Access Override flag. */
484#define ARMV8_SPSR_EL2_AARCH64_UAO RT_BIT_64(23)
485#define ARMV8_SPSR_EL2_AARCH64_UAO_BIT 23
486/** Bit 24 - DIT - Data Independent Timing flag. */
487#define ARMV8_SPSR_EL2_AARCH64_DIT RT_BIT_64(24)
488#define ARMV8_SPSR_EL2_AARCH64_DIT_BIT 24
489/** Bit 25 - TCO - Tag Check Override flag. */
490#define ARMV8_SPSR_EL2_AARCH64_TCO RT_BIT_64(25)
491#define ARMV8_SPSR_EL2_AARCH64_TCO_BIT 25
492/** Bit 26 - 27 - Reserved (read as zero). */
493#define ARMV8_SPSR_EL2_AARCH64_RSVD_26_27 (RT_BIT_64(26) | RT_BIT_64(27))
494/** Bit 28 - V - Overflow condition flag. */
495#define ARMV8_SPSR_EL2_AARCH64_V RT_BIT_64(28)
496#define ARMV8_SPSR_EL2_AARCH64_V_BIT 28
497/** Bit 29 - C - Carry condition flag. */
498#define ARMV8_SPSR_EL2_AARCH64_C RT_BIT_64(29)
499#define ARMV8_SPSR_EL2_AARCH64_C_BIT 29
500/** Bit 30 - Z - Zero condition flag. */
501#define ARMV8_SPSR_EL2_AARCH64_Z RT_BIT_64(30)
502#define ARMV8_SPSR_EL2_AARCH64_Z_BIT 30
503/** Bit 31 - N - Negative condition flag. */
504#define ARMV8_SPSR_EL2_AARCH64_N RT_BIT_64(31)
505#define ARMV8_SPSR_EL2_AARCH64_N_BIT 31
506/** Bit 32 - 63 - Reserved (read as zero). */
507#define ARMV8_SPSR_EL2_AARCH64_RSVD_32_63 (UINT64_C(0xffffffff00000000))
508/** Checks whether the given SPSR value contains a AARCH64 execution state. */
509#define ARMV8_SPSR_EL2_IS_AARCH64_STATE(a_Spsr) (!((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M4))
510/** @} */
511
512/** @name Aarch64 Exception levels
513 * @{ */
514/** Exception Level 0 - User mode. */
515#define ARMV8_AARCH64_EL_0 0
516/** Exception Level 1 - Supervisor mode. */
517#define ARMV8_AARCH64_EL_1 1
518/** Exception Level 2 - Hypervisor mode. */
519#define ARMV8_AARCH64_EL_2 2
520/** @} */
521
522
523/** @name ESR_EL2 (Exception Syndrome Register, EL2)
524 * @{
525 */
526/** Bit 0 - 24 - ISS - Instruction Specific Syndrome, encoding depends on the exception class. */
527#define ARMV8_ESR_EL2_ISS UINT64_C(0x1ffffff)
528#define ARMV8_ESR_EL2_ISS_GET(a_Esr) ((a_Esr) & ARMV8_ESR_EL2_ISS)
529/** Bit 25 - IL - Instruction length for synchronous exception (0 means 16-bit instruction, 1 32-bit instruction). */
530#define ARMV8_ESR_EL2_IL RT_BIT_64(25)
531#define ARMV8_ESR_EL2_IL_BIT 25
532#define ARMV8_ESR_EL2_IL_IS_32BIT(a_Esr) RT_BOOL((a_Esr) & ARMV8_ESR_EL2_IL)
533#define ARMV8_ESR_EL2_IL_IS_16BIT(a_Esr) (!((a_Esr) & ARMV8_ESR_EL2_IL))
534/** Bit 26 - 31 - EC - Exception class, indicates reason for the exception that this register holds information about. */
535#define ARMV8_ESR_EL2_EC ( RT_BIT_64(26) | RT_BIT_64(27) | RT_BIT_64(28) \
536 | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
537#define ARMV8_ESR_EL2_EC_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_EC) >> 26)
538/** Bit 32 - 36 - ISS2 - Only valid when FEAT_LS64_V and/or FEAT_LS64_ACCDATA is present. */
539#define ARMV8_ESR_EL2_ISS2 ( RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) \
540 | RT_BIT_64(35) | RT_BIT_64(36))
541#define ARMV8_ESR_EL2_ISS2_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_ISS2) >> 32)
542/** @} */
543
544
545/** @name ESR_EL2 Exception Classes (EC)
546 * @{ */
547/** Unknown exception reason. */
548#define ARMV8_ESR_EL2_EC_UNKNOWN UINT32_C(0)
549/** Trapped WF* instruction. */
550#define ARMV8_ESR_EL2_EC_TRAPPED_WFX UINT32_C(1)
551/** AArch32 - Trapped MCR or MRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
552#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15 UINT32_C(3)
553/** AArch32 - Trapped MCRR or MRRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
554#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15 UINT32_C(4)
555/** AArch32 - Trapped MCR or MRC access (coproc == 0b1110). */
556#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14 UINT32_C(5)
557/** AArch32 - Trapped LDC or STC access. */
558#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC UINT32_C(6)
559/** AArch32 - Trapped access to SME, SVE or Advanced SIMD or floating point fnunctionality. */
560#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON UINT32_C(7)
561/** AArch32 - Trapped VMRS access not reported using ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON. */
562#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS UINT32_C(8)
563/** AArch32 - Trapped pointer authentication instruction. */
564#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN UINT32_C(9)
565/** FEAT_LS64 - Exception from LD64B or ST64B instruction. */
566#define ARMV8_ESR_EL2_EC_LS64_EXCEPTION UINT32_C(10)
567/** AArch32 - Trapped MRRC access (coproc == 0b1110). */
568#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14 UINT32_C(12)
569/** FEAT_BTI - Branch Target Exception. */
570#define ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION UINT32_C(13)
571/** Illegal Execution State. */
572#define ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE UINT32_C(14)
573/** AArch32 - SVC instruction execution. */
574#define ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN UINT32_C(17)
575/** AArch32 - HVC instruction execution. */
576#define ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN UINT32_C(18)
577/** AArch32 - SMC instruction execution. */
578#define ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN UINT32_C(19)
579/** AArch64 - SVC instruction execution. */
580#define ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN UINT32_C(21)
581/** AArch64 - HVC instruction execution. */
582#define ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN UINT32_C(22)
583/** AArch64 - SMC instruction execution. */
584#define ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN UINT32_C(23)
585/** AArch64 - Trapped MSR, MRS or System instruction execution in AArch64 state. */
586#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN UINT32_C(24)
587/** FEAT_SVE - Access to SVE vunctionality not reported using ARMV8_ESR_EL2_EC_UNKNOWN. */
588#define ARMV8_ESR_EL2_EC_SVE_TRAPPED UINT32_C(25)
589/** FEAT_PAuth and FEAT_NV - Trapped ERET, ERETAA or ERTAB instruction. */
590#define ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB UINT32_C(26)
591/** FEAT_TME - Exception from TSTART instruction. */
592#define ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION UINT32_C(27)
593/** FEAT_FPAC - Exception from a Pointer Authentication instruction failure. */
594#define ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION UINT32_C(28)
595/** FEAT_SME - Access to SME functionality trapped. */
596#define ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS UINT32_C(29)
597/** FEAT_RME - Exception from Granule Protection Check. */
598#define ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION UINT32_C(30)
599/** Instruction Abort from a lower Exception level. */
600#define ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL UINT32_C(32)
601/** Instruction Abort from the same Exception level. */
602#define ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2 UINT32_C(33)
603/** PC alignment fault exception. */
604#define ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION UINT32_C(34)
605/** Data Abort from a lower Exception level. */
606#define ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL UINT32_C(36)
607/** Data Abort from the same Exception level (or access associated with VNCR_EL2). */
608#define ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2 UINT32_C(37)
609/** SP alignment fault exception. */
610#define ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION UINT32_C(38)
611/** FEAT_MOPS - Memory Operation Exception. */
612#define ARMV8_ESR_EL2_EC_MOPS_EXCEPTION UINT32_C(39)
613/** AArch32 - Trapped floating point exception. */
614#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION UINT32_C(40)
615/** AArch64 - Trapped floating point exception. */
616#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION UINT32_C(44)
617/** SError interrupt. */
618#define ARMV8_ESR_EL2_SERROR_INTERRUPT UINT32_C(47)
619/** Breakpoint Exception from a lower Exception level. */
620#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL UINT32_C(48)
621/** Breakpoint Exception from the same Exception level. */
622#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2 UINT32_C(49)
623/** Software Step Exception from a lower Exception level. */
624#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL UINT32_C(50)
625/** Software Step Exception from the same Exception level. */
626#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2 UINT32_C(51)
627/** Watchpoint Exception from a lower Exception level. */
628#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL UINT32_C(52)
629/** Watchpoint Exception from the same Exception level. */
630#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2 UINT32_C(53)
631/** AArch32 - BKPT instruction execution. */
632#define ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN UINT32_C(56)
633/** AArch32 - Vector Catch exception. */
634#define ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION UINT32_C(58)
635/** AArch64 - BRK instruction execution. */
636#define ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN UINT32_C(60)
637/** @} */
638
639
640/** @name ISS encoding for Data Abort exceptions.
641 * @{ */
642/** Bit 0 - 5 - DFSC - Data Fault Status Code. */
643#define ARMV8_EC_ISS_DATA_ABRT_DFSC ( RT_BIT_32(0) | RT_BIT_32(1) | RT_BIT_32(2) \
644 | RT_BIT_32(3) | RT_BIT_32(4) | RT_BIT_32(5))
645#define ARMV8_EC_ISS_DATA_ABRT_DFSC_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_DFSC)
646/** Bit 6 - WnR - Write not Read. */
647#define ARMV8_EC_ISS_DATA_ABRT_WNR RT_BIT_32(6)
648#define ARMV8_EC_ISS_DATA_ABRT_WNR_BIT 6
649/** Bit 7 - S1PTW - Stage 2 translation fault for an access made for a stage 1 translation table walk. */
650#define ARMV8_EC_ISS_DATA_ABRT_S1PTW RT_BIT_32(7)
651#define ARMV8_EC_ISS_DATA_ABRT_S1PTW_BIT 7
652/** Bit 8 - CM - Cache maintenance instruction. */
653#define ARMV8_EC_ISS_DATA_ABRT_CM RT_BIT_32(8)
654#define ARMV8_EC_ISS_DATA_ABRT_CM_BIT 8
655/** Bit 9 - EA - External abort type. */
656#define ARMV8_EC_ISS_DATA_ABRT_EA RT_BIT_32(9)
657#define ARMV8_EC_ISS_DATA_ABRT_EA_BIT 9
658/** Bit 10 - FnV - FAR not Valid. */
659#define ARMV8_EC_ISS_DATA_ABRT_FNV RT_BIT_32(10)
660#define ARMV8_EC_ISS_DATA_ABRT_FNV_BIT 10
661/** Bit 11 - 12 - LST - Load/Store Type. */
662#define ARMV8_EC_ISS_DATA_ABRT_LST (RT_BIT_32(11) | RT_BIT_32(12))
663#define ARMV8_EC_ISS_DATA_ABRT_LST_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_LST) >> 11)
664/** Bit 13 - VNCR - Fault came from use of VNCR_EL2 register by EL1 code. */
665#define ARMV8_EC_ISS_DATA_ABRT_VNCR RT_BIT_32(13)
666#define ARMV8_EC_ISS_DATA_ABRT_VNCR_BIT 13
667/** Bit 14 - AR - Acquire/Release semantics. */
668#define ARMV8_EC_ISS_DATA_ABRT_AR RT_BIT_32(14)
669#define ARMV8_EC_ISS_DATA_ABRT_AR_BIT 14
670/** Bit 15 - SF - Sixty Four bit general-purpose register transfer (only when ISV is 1). */
671#define ARMV8_EC_ISS_DATA_ABRT_SF RT_BIT_32(15)
672#define ARMV8_EC_ISS_DATA_ABRT_SF_BIT 15
673/** Bit 16 - 20 - SRT - Syndrome Register Transfer. */
674#define ARMV8_EC_ISS_DATA_ABRT_SRT ( RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18) \
675 | RT_BIT_32(19) | RT_BIT_32(20))
676#define ARMV8_EC_ISS_DATA_ABRT_SRT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SRT) >> 16)
677/** Bit 21 - SSE - Syndrome Sign Extend. */
678#define ARMV8_EC_ISS_DATA_ABRT_SSE RT_BIT_32(21)
679#define ARMV8_EC_ISS_DATA_ABRT_SSE_BIT 21
680/** Bit 22 - 23 - SAS - Syndrome Access Size. */
681#define ARMV8_EC_ISS_DATA_ABRT_SAS (RT_BIT_32(22) | RT_BIT_32(23))
682#define ARMV8_EC_ISS_DATA_ABRT_SAS_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SAS) >> 22)
683/** Bit 24 - ISV - Instruction Syndrome Valid. */
684#define ARMV8_EC_ISS_DATA_ABRT_ISV RT_BIT_32(24)
685#define ARMV8_EC_ISS_DATA_ABRT_ISV_BIT 24
686
687
688/** @name Data Fault Status Code (DFSC).
689 * @{ */
690/** Address size fault, level 0 of translation or translation table base register. */
691#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL0 0
692/** Address size fault, level 1. */
693#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL1 1
694/** Address size fault, level 2. */
695#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL2 2
696/** Address size fault, level 3. */
697#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL3 3
698/** Translation fault, level 0. */
699#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL0 4
700/** Translation fault, level 1. */
701#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL1 5
702/** Translation fault, level 2. */
703#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL2 6
704/** Translation fault, level 3. */
705#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL3 7
706/** FEAT_LPA2 - Access flag fault, level 0. */
707#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL0 8
708/** Access flag fault, level 1. */
709#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL1 9
710/** Access flag fault, level 2. */
711#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL2 10
712/** Access flag fault, level 3. */
713#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL3 11
714/** FEAT_LPA2 - Permission fault, level 0. */
715#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL0 12
716/** Permission fault, level 1. */
717#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL1 13
718/** Permission fault, level 2. */
719#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL2 14
720/** Permission fault, level 3. */
721#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL3 15
722/** Synchronous External abort, not a translation table walk or hardware update of translation table. */
723#define ARMV8_EC_ISS_DATA_ABRT_DFSC_SYNC_EXTERNAL 16
724/** FEAT_MTE2 - Synchronous Tag Check Fault. */
725#define ARMV8_EC_ISS_DATA_ABRT_DFSC_MTE2_SYNC_TAG_CHK_FAULT 17
726/** @todo Do the rest (lazy developer). */
727/** @} */
728
729
730/** @name SAS encoding.
731 * @{ */
732/** Byte access. */
733#define ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE 0
734/** Halfword access (uint16_t). */
735#define ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD 1
736/** Word access (uint32_t). */
737#define ARMV8_EC_ISS_DATA_ABRT_SAS_WORD 2
738/** Doubleword access (uint64_t). */
739#define ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD 3
740/** @} */
741
742
743/** @name ISS encoding for trapped MSR, MRS or System instruction exceptions.
744 * @{ */
745/** Bit 0 - Direction flag. */
746#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION RT_BIT_32(0)
747#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(a_Iss) RT_BOOL((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION)
748/** Bit 1 - 4 - CRm value from the instruction. */
749#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM ( RT_BIT_32(1) | RT_BIT_32(2) | RT_BIT_32(3) \
750 | RT_BIT_32(4))
751#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM) >> 1)
752/** Bit 5 - 9 - Rt value from the instruction. */
753#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT ( RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7) \
754 | RT_BIT_32(8) | RT_BIT_32(9))
755#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT) >> 5)
756/** Bit 10 - 13 - CRn value from the instruction. */
757#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN ( RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) \
758 | RT_BIT_32(13))
759#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN) >> 10)
760/** Bit 14 - 16 - Op2 value from the instruction. */
761#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1 (RT_BIT_32(14) | RT_BIT_32(15) | RT_BIT_32(16))
762#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1) >> 14)
763/** Bit 17 - 19 - Op2 value from the instruction. */
764#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2 (RT_BIT_32(17) | RT_BIT_32(18) | RT_BIT_32(19))
765#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2) >> 17)
766/** Bit 20 - 21 - Op0 value from the instruction. */
767#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0 (RT_BIT_32(20) | RT_BIT_32(21))
768#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0) >> 20)
769/** Bit 22 - 24 - Reserved. */
770#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RSVD (RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(24))
771/** @} */
772
773
774/** @name ISS encoding for trapped HVC instruction exceptions.
775 * @{ */
776/** Bit 0 - 15 - imm16 value of the instruction. */
777#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM (UINT16_C(0xffff))
778#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM)
779/** @} */
780
781
782/** @name TCR_EL1 - Translation Control Register (EL1)
783 * @{
784 */
785/** Bit 0 - 5 - Size offset of the memory region addressed by TTBR0_EL1 (2^(64-T0SZ)). */
786#define ARMV8_TCR_EL1_AARCH64_T0SZ ( RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) \
787 | RT_BIT_64(3) | RT_BIT_64(4) | RT_BIT_64(5))
788#define ARMV8_TCR_EL1_AARCH64_T0SZ_GET(a_Tcr) ((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ)
789/** Bit 7 - Translation table walk disable for translations using TTBR0_EL1. */
790#define ARMV8_TCR_EL1_AARCH64_EPD0 RT_BIT_64(7)
791#define ARMV8_TCR_EL1_AARCH64_EPD0_BIT 7
792/** Bit 8 - 9 - Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
793#define ARMV8_TCR_EL1_AARCH64_IRGN0 (RT_BIT_64(8) | RT_BIT_64(9))
794#define ARMV8_TCR_EL1_AARCH64_IRGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN0) >> 8)
795/** Non cacheable. */
796# define ARMV8_TCR_EL1_AARCH64_IRGN0_NON_CACHEABLE 0
797/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
798# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_WA 1
799/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
800# define ARMV8_TCR_EL1_AARCH64_IRGN0_WT_RA_NWA 2
801/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
802# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_NWA 3
803/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
804#define ARMV8_TCR_EL1_AARCH64_ORGN0 (RT_BIT_64(10) | RT_BIT_64(11))
805#define ARMV8_TCR_EL1_AARCH64_ORGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN0) >> 10)
806/** Non cacheable. */
807# define ARMV8_TCR_EL1_AARCH64_ORGN0_NON_CACHEABLE 0
808/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
809# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_WA 1
810/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
811# define ARMV8_TCR_EL1_AARCH64_ORGN0_WT_RA_NWA 2
812/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
813# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_NWA 3
814/** Bit 12 - 13 - Shareability attribute memory associated with translation table walks using TTBR0_EL1. */
815#define ARMV8_TCR_EL1_AARCH64_SH0 (RT_BIT_64(12) | RT_BIT_64(13))
816#define ARMV8_TCR_EL1_AARCH64_SH0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH0) >> 12)
817/** Non shareable. */
818# define ARMV8_TCR_EL1_AARCH64_SH0_NON_SHAREABLE 0
819/** Invalid value. */
820# define ARMV8_TCR_EL1_AARCH64_SH0_INVALID 1
821/** Outer Shareable. */
822# define ARMV8_TCR_EL1_AARCH64_SH0_OUTER_SHAREABLE 2
823/** Inner Shareable. */
824# define ARMV8_TCR_EL1_AARCH64_SH0_INNER_SHAREABLE 3
825/** Bit 14 - 15 - Translation Granule Size for TTBR0_EL1. */
826#define ARMV8_TCR_EL1_AARCH64_TG0 (RT_BIT_64(14) | RT_BIT_64(15))
827#define ARMV8_TCR_EL1_AARCH64_TG0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG0) >> 14)
828/** Invalid granule size. */
829# define ARMV8_TCR_EL1_AARCH64_TG0_INVALID 0
830/** 16KiB granule size. */
831# define ARMV8_TCR_EL1_AARCH64_TG0_16KB 1
832/** 4KiB granule size. */
833# define ARMV8_TCR_EL1_AARCH64_TG0_4KB 2
834/** 64KiB granule size. */
835# define ARMV8_TCR_EL1_AARCH64_TG0_64KB 3
836/** Bit 16 - 21 - Size offset of the memory region addressed by TTBR1_EL1 (2^(64-T1SZ)). */
837#define ARMV8_TCR_EL1_AARCH64_T1SZ ( RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) \
838 | RT_BIT_64(19) | RT_BIT_64(20) | RT_BIT_64(21))
839#define ARMV8_TCR_EL1_AARCH64_T1SZ_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ) >> 16)
840/** Bit 22 - Selects whether TTBR0_EL1 (0) or TTBR1_EL1 (1) defines the ASID. */
841#define ARMV8_TCR_EL1_AARCH64_A1 RT_BIT_64(22)
842#define ARMV8_TCR_EL1_AARCH64_A1_BIT 22
843/** Bit 23 - Translation table walk disable for translations using TTBR1_EL1. */
844#define ARMV8_TCR_EL1_AARCH64_EPD1 RT_BIT_64(23)
845#define ARMV8_TCR_EL1_AARCH64_EPD1_BIT 23
846/** Bit 24 - 25 - Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
847#define ARMV8_TCR_EL1_AARCH64_IRGN1 (RT_BIT_64(24) | RT_BIT_64(25))
848#define ARMV8_TCR_EL1_AARCH64_IRGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN1) >> 26)
849/** Non cacheable. */
850# define ARMV8_TCR_EL1_AARCH64_IRGN1_NON_CACHEABLE 0
851/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
852# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_WA 1
853/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
854# define ARMV8_TCR_EL1_AARCH64_IRGN1_WT_RA_NWA 2
855/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
856# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_NWA 3
857/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
858#define ARMV8_TCR_EL1_AARCH64_ORGN1 (RT_BIT_64(26) | RT_BIT_64(27))
859#define ARMV8_TCR_EL1_AARCH64_ORGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN1) >> 26)
860/** Non cacheable. */
861# define ARMV8_TCR_EL1_AARCH64_ORGN1_NON_CACHEABLE 0
862/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
863# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_WA 1
864/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
865# define ARMV8_TCR_EL1_AARCH64_ORGN1_WT_RA_NWA 2
866/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
867# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_NWA 3
868/** Bit 28 - 29 - Shareability attribute memory associated with translation table walks using TTBR1_EL1. */
869#define ARMV8_TCR_EL1_AARCH64_SH1 (RT_BIT_64(28) | RT_BIT_64(29))
870#define ARMV8_TCR_EL1_AARCH64_SH1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH1) >> 28)
871/** Non shareable. */
872# define ARMV8_TCR_EL1_AARCH64_SH1_NON_SHAREABLE 0
873/** Invalid value. */
874# define ARMV8_TCR_EL1_AARCH64_SH1_INVALID 1
875/** Outer Shareable. */
876# define ARMV8_TCR_EL1_AARCH64_SH1_OUTER_SHAREABLE 2
877/** Inner Shareable. */
878# define ARMV8_TCR_EL1_AARCH64_SH1_INNER_SHAREABLE 3
879/** Bit 30 - 31 - Translation Granule Size for TTBR1_EL1. */
880#define ARMV8_TCR_EL1_AARCH64_TG1 (RT_BIT_64(30) | RT_BIT_64(31))
881#define ARMV8_TCR_EL1_AARCH64_TG1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG1) >> 30)
882/** Invalid granule size. */
883# define ARMV8_TCR_EL1_AARCH64_TG1_INVALID 0
884/** 16KiB granule size. */
885# define ARMV8_TCR_EL1_AARCH64_TG1_16KB 1
886/** 4KiB granule size. */
887# define ARMV8_TCR_EL1_AARCH64_TG1_4KB 2
888/** 64KiB granule size. */
889# define ARMV8_TCR_EL1_AARCH64_TG1_64KB 3
890/** Bit 32 - 34 - Intermediate Physical Address Size. */
891#define ARMV8_TCR_EL1_AARCH64_IPS (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34))
892#define ARMV8_TCR_EL1_AARCH64_IPS_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IPS) >> 32)
893/** IPA - 32 bits, 4GiB. */
894# define ARMV8_TCR_EL1_AARCH64_IPS_32BITS 0
895/** IPA - 36 bits, 64GiB. */
896# define ARMV8_TCR_EL1_AARCH64_IPS_36BITS 1
897/** IPA - 40 bits, 1TiB. */
898# define ARMV8_TCR_EL1_AARCH64_IPS_40BITS 2
899/** IPA - 42 bits, 4TiB. */
900# define ARMV8_TCR_EL1_AARCH64_IPS_42BITS 3
901/** IPA - 44 bits, 16TiB. */
902# define ARMV8_TCR_EL1_AARCH64_IPS_44BITS 4
903/** IPA - 48 bits, 256TiB. */
904# define ARMV8_TCR_EL1_AARCH64_IPS_48BITS 5
905/** IPA - 52 bits, 4PiB. */
906# define ARMV8_TCR_EL1_AARCH64_IPS_52BITS 6
907/** Bit 36 - ASID Size (0 - 8 bit, 1 - 16 bit). */
908#define ARMV8_TCR_EL1_AARCH64_AS RT_BIT_64(36)
909#define ARMV8_TCR_EL1_AARCH64_AS_BIT 36
910/** Bit 37 - Top Byte Ignore for translations from TTBR0_EL1. */
911#define ARMV8_TCR_EL1_AARCH64_TBI0 RT_BIT_64(37)
912#define ARMV8_TCR_EL1_AARCH64_TBI0_BIT 37
913/** Bit 38 - Top Byte Ignore for translations from TTBR1_EL1. */
914#define ARMV8_TCR_EL1_AARCH64_TBI1 RT_BIT_64(38)
915#define ARMV8_TCR_EL1_AARCH64_TBI1_BIT 38
916/** Bit 39 - Hardware Access flag update in stage 1 translations from EL0 and EL1. */
917#define ARMV8_TCR_EL1_AARCH64_HA RT_BIT_64(39)
918#define ARMV8_TCR_EL1_AARCH64_HA_BIT 39
919/** Bit 40 - Hardware management of dirty state in stage 1 translations from EL0 and EL1. */
920#define ARMV8_TCR_EL1_AARCH64_HD RT_BIT_64(40)
921#define ARMV8_TCR_EL1_AARCH64_HD_BIT 40
922/** Bit 41 - Hierarchical Permission Disables for TTBR0_EL1. */
923#define ARMV8_TCR_EL1_AARCH64_HPD0 RT_BIT_64(41)
924#define ARMV8_TCR_EL1_AARCH64_HPD0_BIT 41
925/** Bit 42 - Hierarchical Permission Disables for TTBR1_EL1. */
926#define ARMV8_TCR_EL1_AARCH64_HPD1 RT_BIT_64(42)
927#define ARMV8_TCR_EL1_AARCH64_HPD1_BIT 42
928/** Bit 43 - Bit[59] Hardware Use for translations using TTBR0_EL1. */
929#define ARMV8_TCR_EL1_AARCH64_HWU059 RT_BIT_64(43)
930#define ARMV8_TCR_EL1_AARCH64_HWU059_BIT 43
931/** Bit 44 - Bit[60] Hardware Use for translations using TTBR0_EL1. */
932#define ARMV8_TCR_EL1_AARCH64_HWU060 RT_BIT_64(44)
933#define ARMV8_TCR_EL1_AARCH64_HWU060_BIT 44
934/** Bit 46 - Bit[61] Hardware Use for translations using TTBR0_EL1. */
935#define ARMV8_TCR_EL1_AARCH64_HWU061 RT_BIT_64(45)
936#define ARMV8_TCR_EL1_AARCH64_HWU061_BIT 45
937/** Bit 46 - Bit[62] Hardware Use for translations using TTBR0_EL1. */
938#define ARMV8_TCR_EL1_AARCH64_HWU062 RT_BIT_64(46)
939#define ARMV8_TCR_EL1_AARCH64_HWU062_BIT 46
940/** Bit 47 - Bit[59] Hardware Use for translations using TTBR1_EL1. */
941#define ARMV8_TCR_EL1_AARCH64_HWU159 RT_BIT_64(47)
942#define ARMV8_TCR_EL1_AARCH64_HWU159_BIT 47
943/** Bit 48 - Bit[60] Hardware Use for translations using TTBR1_EL1. */
944#define ARMV8_TCR_EL1_AARCH64_HWU160 RT_BIT_64(48)
945#define ARMV8_TCR_EL1_AARCH64_HWU160_BIT 48
946/** Bit 49 - Bit[61] Hardware Use for translations using TTBR1_EL1. */
947#define ARMV8_TCR_EL1_AARCH64_HWU161 RT_BIT_64(49)
948#define ARMV8_TCR_EL1_AARCH64_HWU161_BIT 49
949/** Bit 50 - Bit[62] Hardware Use for translations using TTBR1_EL1. */
950#define ARMV8_TCR_EL1_AARCH64_HWU162 RT_BIT_64(50)
951#define ARMV8_TCR_EL1_AARCH64_HWU162_BIT 50
952/** Bit 51 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR0_EL1. */
953#define ARMV8_TCR_EL1_AARCH64_TBID0 RT_BIT_64(51)
954#define ARMV8_TCR_EL1_AARCH64_TBID0_BIT 51
955/** Bit 52 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR1_EL1. */
956#define ARMV8_TCR_EL1_AARCH64_TBID1 RT_BIT_64(52)
957#define ARMV8_TCR_EL1_AARCH64_TBID1_BIT 52
958/** Bit 53 - Non fault translation table walk disable for stage 1 translations using TTBR0_EL1. */
959#define ARMV8_TCR_EL1_AARCH64_NFD0 RT_BIT_64(53)
960#define ARMV8_TCR_EL1_AARCH64_NFD0_BIT 53
961/** Bit 54 - Non fault translation table walk disable for stage 1 translations using TTBR1_EL1. */
962#define ARMV8_TCR_EL1_AARCH64_NFD1 RT_BIT_64(54)
963#define ARMV8_TCR_EL1_AARCH64_NFD1_BIT 54
964/** Bit 55 - Faulting Control for Unprivileged access to any address translated by TTBR0_EL1. */
965#define ARMV8_TCR_EL1_AARCH64_E0PD0 RT_BIT_64(55)
966#define ARMV8_TCR_EL1_AARCH64_E0PD0_BIT 55
967/** Bit 56 - Faulting Control for Unprivileged access to any address translated by TTBR1_EL1. */
968#define ARMV8_TCR_EL1_AARCH64_E0PD1 RT_BIT_64(56)
969#define ARMV8_TCR_EL1_AARCH64_E0PD1_BIT 56
970/** Bit 57 - TCMA0 */
971#define ARMV8_TCR_EL1_AARCH64_TCMA0 RT_BIT_64(57)
972#define ARMV8_TCR_EL1_AARCH64_TCMA0_BIT 57
973/** Bit 58 - TCMA1 */
974#define ARMV8_TCR_EL1_AARCH64_TCMA1 RT_BIT_64(58)
975#define ARMV8_TCR_EL1_AARCH64_TCMA1_BIT 58
976/** Bit 59 - Data Sharing(?). */
977#define ARMV8_TCR_EL1_AARCH64_DS RT_BIT_64(59)
978#define ARMV8_TCR_EL1_AARCH64_DS_BIT 59
979/** @} */
980
981
982/** @name TTBR<0,1>_EL1 - Translation Table Base Register <0,1> (EL1)
983 * @{
984 */
985/** Bit 0 - Common not Private (FEAT_TTCNP). */
986#define ARMV8_TTBR_EL1_AARCH64_CNP RT_BIT_64(0)
987#define ARMV8_TTBR_EL1_AARCH64_CNP_BIT 0
988/** Bit 1 - 47 - Translation table base address. */
989#define ARMV8_TTBR_EL1_AARCH64_BADDR UINT64_C(0x0000fffffffffffe)
990#define ARMV8_TTBR_EL1_AARCH64_BADDR_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_BADDR) >> 1)
991/** Bit 48 - 63 - ASID. */
992#define ARMV8_TTBR_EL1_AARCH64_ASID UINT64_C(0xffff000000000000)
993#define ARMV8_TTBR_EL1_AARCH64_ASID_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_ASID) >> 48)
994/** @} */
995
996
997/** @name ICC_PMR_EL1 - Interrupt Controller Interrupt Priority Mask Register
998 * @{ */
999/** Bit 0 - 7 - Priority - The priority mask level for the CPU interface. */
1000#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY UINT64_C(0xff)
1001#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_GET(a_Pmr) ((a_Pmr) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1002#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_SET(a_Prio) ((a_Prio) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1003/** @} */
1004
1005
1006/** @name ICC_BPR0_EL1 - The group priority for Group 0 interrupts.
1007 * @{ */
1008/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1009#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1010#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_GET(a_Bpr0) ((a_Bpr0) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1011#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1012/** @} */
1013
1014
1015/** @name ICC_BPR1_EL1 - The group priority for Group 1 interrupts.
1016 * @{ */
1017/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1018#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1019#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_GET(a_Bpr1) ((a_Bpr1) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1020#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1021/** @} */
1022
1023
1024/** @name ICC_CTLR_EL1 - Interrupt Controller Control Register (EL1)
1025 * @{ */
1026/** Bit 0 - Common Binary Pointer Register - RW. */
1027#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR RT_BIT_64(0)
1028#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR_BIT 0
1029/** Bit 1 - EOI mode for current security state, when set ICC_DIR_EL1 provides interrupt deactivation functionality - RW. */
1030#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE RT_BIT_64(1)
1031#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE_BIT 1
1032/** Bit 7 - Priority Mask Hint Enable - RW (under circumstances). */
1033#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE RT_BIT_64(7)
1034#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE_BIT 7
1035/** Bit 8 - 10 - Priority bits - RO. */
1036#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10))
1037#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS_SET(a_PriBits) (((a_PriBits) << 8) & ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS)
1038/** Bit 11 - 13 - Interrupt identifier bits - RO. */
1039#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS (RT_BIT_64(11) | RT_BIT_64(12) | RT_BIT_64(13))
1040#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_SET(a_IdBits) (((a_IdBits) << 11) & ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS)
1041/** INTIDS are 16-bit wide. */
1042# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_16BITS 0
1043/** INTIDS are 24-bit wide. */
1044# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_24BITS 1
1045/** Bit 14 - SEI Supported - RO. */
1046#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS RT_BIT_64(14)
1047#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS_BIT 14
1048/** Bit 15 - Affinity 3 Valid - RO. */
1049#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V RT_BIT_64(15)
1050#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V_BIT 15
1051/** Bit 18 - Range Selector Support - RO. */
1052#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS RT_BIT_64(18)
1053#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS_BIT 18
1054/** Bit 19 - Extended INTID range supported - RO. */
1055#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE RT_BIT_64(19)
1056#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE_BIT 19
1057/** All RW bits. */
1058#define ARMV8_ICC_CTLR_EL1_RW (ARMV8_ICC_CTLR_EL1_AARCH64_CBPR | ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE | ARMV8_ICC_CTLR_EL1_AARCH64_PMHE)
1059/** All RO bits (including Res0). */
1060#define ARMV8_ICC_CTLR_EL1_RO ~ARMV8_ICC_CTLR_EL1_RW
1061/** @} */
1062
1063
1064/** @name ICC_IGRPEN0_EL1 - Interrupt Controller Interrupt Group 0 Enable Register (EL1)
1065 * @{ */
1066/** Bit 0 - Enables Group 0 interrupts for the current Security state. */
1067#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE RT_BIT_64(0)
1068#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE_BIT 0
1069/** @} */
1070
1071
1072/** @name ICC_IGRPEN1_EL1 - Interrupt Controller Interrupt Group 1 Enable Register (EL1)
1073 * @{ */
1074/** Bit 0 - Enables Group 1 interrupts for the current Security state. */
1075#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE RT_BIT_64(0)
1076#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE_BIT 0
1077/** @} */
1078
1079
1080/** @name ICC_SGI1R_EL1 - Interrupt Controller Software Generated Interrupt Group 1 Register (EL1) - WO
1081 * @{ */
1082/** Bit 0 - 15 - Target List, the set of PEs for which SGI interrupts will be generated. */
1083#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST (UINT64_C(0x000000000000ffff))
1084#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST_GET(a_Sgi1R) ((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST)
1085/** Bit 16 - 23 - The affinity 1 of the affinity path of the cluster for which SGI interrupts will be generated. */
1086#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1 (UINT64_C(0x00000000007f0000))
1087#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1) >> 16)
1088/** Bit 24 - 27 - The INTID of the SGI. */
1089#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1090#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_INTID) >> 24)
1091/* Bit 28 - 31 - Reserved. */
1092/** Bit 32 - 39 - The affinity 2 of the affinity path of the cluster for which SGI interrupts will be generated. */
1093#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2 (UINT64_C(0x000000ff00000000))
1094#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2) >> 32)
1095/** Bit 40 - Interrupt Routing Mode - 1 means interrupts to all PEs in the system excluding the generating PE. */
1096#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM RT_BIT_64(40)
1097#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM_BIT 40
1098/* Bit 41 - 43 - Reserved. */
1099/** Bit 44 - 47 - Range selector. */
1100#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1101#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_RS) >> 44)
1102/** Bit 48 - 55 - The affinity 3 of the affinity path of the cluster for which SGI interrupts will be generated. */
1103#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3 (UINT64_C(0x00ff000000000000))
1104#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3) >> 48)
1105/* Bit 56 - 63 - Reserved. */
1106/** @} */
1107
1108
1109/** @name CNTV_CTL_EL0 - Counter-timer Virtual Timer Control register.
1110 * @{ */
1111/** Bit 0 - Enables the timer. */
1112#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE RT_BIT_64(0)
1113#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE_BIT 0
1114/** Bit 1 - Timer interrupt mask bit. */
1115#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK RT_BIT_64(1)
1116#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK_BIT 1
1117/** Bit 2 - Timer status bit. */
1118#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS RT_BIT_64(2)
1119#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS_BIT 2
1120/** @} */
1121
1122
1123/** @name OSLAR_EL1 - OS Lock Access Register.
1124 * @{ */
1125/** Bit 0 - The OS Lock status bit. */
1126#define ARMV8_OSLAR_EL1_AARCH64_OSLK RT_BIT_64(0)
1127#define ARMV8_OSLAR_EL1_AARCH64_OSLK_BIT 0
1128/** @} */
1129
1130
1131/** @name OSLSR_EL1 - OS Lock Status Register.
1132 * @{ */
1133/** Bit 0 - OSLM[0] Bit 0 of OS Lock model implemented. */
1134#define ARMV8_OSLSR_EL1_AARCH64_OSLM0 RT_BIT_64(0)
1135#define ARMV8_OSLSR_EL1_AARCH64_OSLM0_BIT 0
1136/** Bit 1 - The OS Lock status bit. */
1137#define ARMV8_OSLSR_EL1_AARCH64_OSLK RT_BIT_64(1)
1138#define ARMV8_OSLSR_EL1_AARCH64_OSLK_BIT 1
1139/** Bit 2 - Not 32-bit access. */
1140#define ARMV8_OSLSR_EL1_AARCH64_NTT RT_BIT_64(2)
1141#define ARMV8_OSLSR_EL1_AARCH64_NTT_BIT 2
1142/** Bit 0 - OSLM[1] Bit 1 of OS Lock model implemented. */
1143#define ARMV8_OSLSR_EL1_AARCH64_OSLM1 RT_BIT_64(3)
1144#define ARMV8_OSLSR_EL1_AARCH64_OSLM1_BIT 3
1145/** @} */
1146
1147
1148/** @name ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0.
1149 * @{ */
1150/* Bit 0 - 3 - Reserved. */
1151/** Bit 4 - 7 - Indicates support for AES instructions in AArch64 state. */
1152#define ARMV8_ID_AA64ISAR0_EL1_AES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1153#define ARMV8_ID_AA64ISAR0_EL1_AES_SHIFT 4
1154/** No AES instructions implemented. */
1155# define ARMV8_ID_AA64ISAR0_EL1_AES_NOT_IMPL 0
1156/** AES, AESD, AESMC and AESIMC instructions implemented (FEAT_AES). */
1157# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED 1
1158/** AES, AESD, AESMC and AESIMC instructions implemented and PMULL and PMULL2 instructions operating on 64bit source elements (FEAT_PMULL). */
1159# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL 2
1160/** Bit 8 - 11 - Indicates support for SHA1 instructions in AArch64 state. */
1161#define ARMV8_ID_AA64ISAR0_EL1_SHA1_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1162#define ARMV8_ID_AA64ISAR0_EL1_SHA1_SHIFT 8
1163/** No SHA1 instructions implemented. */
1164# define ARMV8_ID_AA64ISAR0_EL1_SHA1_NOT_IMPL 0
1165/** SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0 and SHA1SU1 instructions implemented (FEAT_SHA1). */
1166# define ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED 1
1167/** Bit 12 - 15 - Indicates support for SHA2 instructions in AArch64 state. */
1168#define ARMV8_ID_AA64ISAR0_EL1_SHA2_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1169#define ARMV8_ID_AA64ISAR0_EL1_SHA2_SHIFT 12
1170/** No SHA2 instructions implemented. */
1171# define ARMV8_ID_AA64ISAR0_EL1_SHA2_NOT_IMPL 0
1172/** SHA256 instructions implemented (FEAT_SHA256). */
1173# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256 1
1174/** SHA256 and SHA512 instructions implemented (FEAT_SHA512). */
1175# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512 2
1176/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1177#define ARMV8_ID_AA64ISAR0_EL1_CRC32_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1178#define ARMV8_ID_AA64ISAR0_EL1_CRC32_SHIFT 16
1179/** No CRC32 instructions implemented. */
1180# define ARMV8_ID_AA64ISAR0_EL1_CRC32_NOT_IMPL 0
1181/** CRC32 instructions implemented (FEAT_CRC32). */
1182# define ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED 1
1183/** Bit 20 - 23 - Indicates support for Atomic instructions in AArch64 state. */
1184#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1185#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20
1186/** No Atomic instructions implemented. */
1187# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_NOT_IMPL 0
1188/** Atomic instructions implemented (FEAT_LSE). */
1189# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SUPPORTED 2
1190/** Bit 24 - 27 - Indicates support for TME instructions. */
1191#define ARMV8_ID_AA64ISAR0_EL1_TME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1192#define ARMV8_ID_AA64ISAR0_EL1_TME_SHIFT 24
1193/** TME instructions are not implemented. */
1194# define ARMV8_ID_AA64ISAR0_EL1_TME_NOT_IMPL 0
1195/** TME instructions are implemented. */
1196# define ARMV8_ID_AA64ISAR0_EL1_TME_SUPPORTED 1
1197/** Bit 28 - 31 - Indicates support for SQRDMLAH and SQRDMLSH instructions in AArch64 state. */
1198#define ARMV8_ID_AA64ISAR0_EL1_RDM_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1199#define ARMV8_ID_AA64ISAR0_EL1_RDM_SHIFT 28
1200/** No RDMA instructions implemented. */
1201# define ARMV8_ID_AA64ISAR0_EL1_RDM_NOT_IMPL 0
1202/** SQRDMLAH and SQRDMLSH instructions implemented (FEAT_RDM). */
1203# define ARMV8_ID_AA64ISAR0_EL1_RDM_SUPPORTED 1
1204/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1205#define ARMV8_ID_AA64ISAR0_EL1_SHA3_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1206#define ARMV8_ID_AA64ISAR0_EL1_SHA3_SHIFT 32
1207/** No SHA3 instructions implemented. */
1208# define ARMV8_ID_AA64ISAR0_EL1_SHA3_NOT_IMPL 0
1209/** EOR3, RAX1, XAR and BCAX instructions implemented (FEAT_SHA3). */
1210# define ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED 1
1211/** Bit 36 - 39 - Indicates support for SM3 instructions in AArch64 state. */
1212#define ARMV8_ID_AA64ISAR0_EL1_SM3_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1213#define ARMV8_ID_AA64ISAR0_EL1_SM3_SHIFT 36
1214/** No SM3 instructions implemented. */
1215# define ARMV8_ID_AA64ISAR0_EL1_SM3_NOT_IMPL 0
1216/** SM3 instructions implemented (FEAT_SM3). */
1217# define ARMV8_ID_AA64ISAR0_EL1_SM3_SUPPORTED 1
1218/** Bit 40 - 43 - Indicates support for SM4 instructions in AArch64 state. */
1219#define ARMV8_ID_AA64ISAR0_EL1_SM4_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1220#define ARMV8_ID_AA64ISAR0_EL1_SM4_SHIFT 40
1221/** No SM4 instructions implemented. */
1222# define ARMV8_ID_AA64ISAR0_EL1_SM4_NOT_IMPL 0
1223/** SM4 instructions implemented (FEAT_SM4). */
1224# define ARMV8_ID_AA64ISAR0_EL1_SM4_SUPPORTED 1
1225/** Bit 44 - 47 - Indicates support for Dot Product instructions in AArch64 state. */
1226#define ARMV8_ID_AA64ISAR0_EL1_DP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1227#define ARMV8_ID_AA64ISAR0_EL1_DP_SHIFT 44
1228/** No Dot Product instructions implemented. */
1229# define ARMV8_ID_AA64ISAR0_EL1_DP_NOT_IMPL 0
1230/** UDOT and SDOT instructions implemented (FEAT_DotProd). */
1231# define ARMV8_ID_AA64ISAR0_EL1_DP_SUPPORTED 1
1232/** Bit 48 - 51 - Indicates support for FMLAL and FMLSL instructions. */
1233#define ARMV8_ID_AA64ISAR0_EL1_FHM_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1234#define ARMV8_ID_AA64ISAR0_EL1_FHM_SHIFT 48
1235/** FMLAL and FMLSL instructions are not implemented. */
1236# define ARMV8_ID_AA64ISAR0_EL1_FHM_NOT_IMPL 0
1237/** FMLAL and FMLSL instructions are implemented (FEAT_FHM). */
1238# define ARMV8_ID_AA64ISAR0_EL1_FHM_SUPPORTED 1
1239/** Bit 52 - 55 - Indicates support for flag manipulation instructions. */
1240#define ARMV8_ID_AA64ISAR0_EL1_TS_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1241#define ARMV8_ID_AA64ISAR0_EL1_TS_SHIFT 52
1242/** No flag manipulation instructions implemented. */
1243# define ARMV8_ID_AA64ISAR0_EL1_TS_NOT_IMPL 0
1244/** CFINV, RMIF, SETF16 and SETF8 instrutions are implemented (FEAT_FlagM). */
1245# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED 1
1246/** CFINV, RMIF, SETF16, SETF8, AXFLAG and XAFLAG instrutions are implemented (FEAT_FlagM2). */
1247# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED_2 2
1248/** Bit 56 - 59 - Indicates support for Outer Shareable and TLB range maintenance instructions. */
1249#define ARMV8_ID_AA64ISAR0_EL1_TLB_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1250#define ARMV8_ID_AA64ISAR0_EL1_TLB_SHIFT 56
1251/** Outer Sahreable and TLB range maintenance instructions are not implemented. */
1252# define ARMV8_ID_AA64ISAR0_EL1_TLB_NOT_IMPL 0
1253/** Outer Shareable TLB maintenance instructions are implemented (FEAT_TLBIOS). */
1254# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED 1
1255/** Outer Shareable and TLB range maintenance instructions are implemented (FEAT_TLBIRANGE). */
1256# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED_RANGE 2
1257/** Bit 60 - 63 - Indicates support for Random Number instructons in AArch64 state. */
1258#define ARMV8_ID_AA64ISAR0_EL1_RNDR_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1259#define ARMV8_ID_AA64ISAR0_EL1_RNDR_SHIFT 60
1260/** No Random Number instructions implemented. */
1261# define ARMV8_ID_AA64ISAR0_EL1_RNDR_NOT_IMPL 0
1262/** RNDR and RDNRRS registers are implemented . */
1263# define ARMV8_ID_AA64ISAR0_EL1_RNDR_SUPPORTED 1
1264/** @} */
1265
1266
1267/** @name ID_AA64ISAR1_EL1 - AArch64 Instruction Set Attribute Register 0.
1268 * @{ */
1269/** Bit 0 - 3 - Indicates support for Data Persistence writeback instructions in AArch64 state. */
1270#define ARMV8_ID_AA64ISAR1_EL1_DPB_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1271#define ARMV8_ID_AA64ISAR1_EL1_DPB_SHIFT 0
1272/** DC CVAP not supported. */
1273# define ARMV8_ID_AA64ISAR1_EL1_DPB_NOT_IMPL 0
1274/** DC CVAP supported (FEAT_DPB). */
1275# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED 1
1276/** DC CVAP and DC CVADP supported (FEAT_DPB2). */
1277# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED_2 2
1278/** Bit 4 - 7 - Indicates whether QARMA5 algorithm is implemented in the PE for address authentication. */
1279#define ARMV8_ID_AA64ISAR1_EL1_APA_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1280#define ARMV8_ID_AA64ISAR1_EL1_APA_SHIFT 4
1281/** Address Authentication using the QARMA5 algorithm is not implemented. */
1282# define ARMV8_ID_AA64ISAR1_EL1_APA_NOT_IMPL 0
1283/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA5). */
1284# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH 1
1285/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA5). */
1286# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_EPAC 2
1287/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA5). */
1288# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH2 3
1289/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA5). */
1290# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPAC 4
1291/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA5). */
1292# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPACCOMBINE 5
1293/** Bit 8 - 11 - Indicates whether an implementation defined algorithm is implemented in the PE for address authentication. */
1294#define ARMV8_ID_AA64ISAR1_EL1_API_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1295#define ARMV8_ID_AA64ISAR1_EL1_API_SHIFT 8
1296/** Address Authentication using the QARMA5 algorithm is not implemented. */
1297# define ARMV8_ID_AA64ISAR1_EL1_API_NOT_IMPL 0
1298/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACIMP). */
1299# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH 1
1300/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACIMP). */
1301# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_EPAC 2
1302/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACIMP). */
1303# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH2 3
1304/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACIMP). */
1305# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPAC 4
1306/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACIMP). */
1307# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPACCOMBINE 5
1308/** Bit 12 - 15 - Indicates support for JavaScript conversion from double precision floating values to integers in AArch64 state. */
1309#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1310#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SHIFT 12
1311/** No FJCVTZS instruction implemented. */
1312# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_NOT_IMPL 0
1313/** FJCVTZS instruction implemented (FEAT_JSCVT). */
1314# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SUPPORTED 1
1315/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1316#define ARMV8_ID_AA64ISAR1_EL1_FCMA_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1317#define ARMV8_ID_AA64ISAR1_EL1_FCMA_SHIFT 16
1318/** No FCMLA and FCADD instructions implemented. */
1319# define ARMV8_ID_AA64ISAR1_EL1_FCMA_NOT_IMPL 0
1320/** FCMLA and FCADD instructions implemented (FEAT_FCMA). */
1321# define ARMV8_ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1
1322/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1323#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1324#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SHIFT 20
1325/** No RCpc instructions implemented. */
1326# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_NOT_IMPL 0
1327/** The no offset LDAPR, LDAPRB and LDAPRH instructions are implemented (FEAT_LRCPC). */
1328# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED 1
1329/** The no offset LDAPR, LDAPRB, LDAPRH, LDAPR and STLR instructions are implemented (FEAT_LRCPC2). */
1330# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED_2 2
1331/** Bit 24 - 27 - Indicates whether the QARMA5 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1332#define ARMV8_ID_AA64ISAR1_EL1_GPA_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1333#define ARMV8_ID_AA64ISAR1_EL1_GPA_SHIFT 24
1334/** Generic Authentication using the QARMA5 algorithm is not implemented. */
1335# define ARMV8_ID_AA64ISAR1_EL1_GPA_NOT_IMPL 0
1336/** Generic Authentication using the QARMA5 algorithm is implemented (FEAT_PACQARMA5). */
1337# define ARMV8_ID_AA64ISAR1_EL1_GPA_SUPPORTED 1
1338/** Bit 28 - 31 - Indicates whether an implementation defined algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1339#define ARMV8_ID_AA64ISAR1_EL1_GPI_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1340#define ARMV8_ID_AA64ISAR1_EL1_GPI_SHIFT 28
1341/** Generic Authentication using an implementation defined algorithm is not implemented. */
1342# define ARMV8_ID_AA64ISAR1_EL1_GPI_NOT_IMPL 0
1343/** Generic Authentication using an implementation defined algorithm is implemented (FEAT_PACIMP). */
1344# define ARMV8_ID_AA64ISAR1_EL1_GPI_SUPPORTED 1
1345/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1346#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1347#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32
1348/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are not implemented. */
1349# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_NOT_IMPL 0
1350/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are implemented (FEAT_FRINTTS). */
1351# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1
1352/** Bit 36 - 39 - Indicates support for SB instructions in AArch64 state. */
1353#define ARMV8_ID_AA64ISAR1_EL1_SB_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1354#define ARMV8_ID_AA64ISAR1_EL1_SB_SHIFT 36
1355/** No SB instructions implemented. */
1356# define ARMV8_ID_AA64ISAR1_EL1_SB_NOT_IMPL 0
1357/** SB instructions implemented (FEAT_SB). */
1358# define ARMV8_ID_AA64ISAR1_EL1_SB_SUPPORTED 1
1359/** Bit 40 - 43 - Indicates support for prediction invalidation instructions in AArch64 state. */
1360#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1361#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SHIFT 40
1362/** Prediction invalidation instructions are not implemented. */
1363# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_NOT_IMPL 0
1364/** Prediction invalidation instructions are implemented (FEAT_SPECRES). */
1365# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
1366/** Bit 44 - 47 - Indicates support for Advanced SIMD and Floating-point BFloat16 instructions in AArch64 state. */
1367#define ARMV8_ID_AA64ISAR1_EL1_BF16_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1368#define ARMV8_ID_AA64ISAR1_EL1_BF16_SHIFT 44
1369/** BFloat16 instructions are not implemented. */
1370# define ARMV8_ID_AA64ISAR1_EL1_BF16_NOT_IMPL 0
1371/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented (FEAT_BF16). */
1372# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_BF16 1
1373/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented and FPCR.EBF is supported (FEAT_EBF16). */
1374# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_EBF16 2
1375/** Bit 48 - 51 - Indicates support for Data Gathering Hint instructions. */
1376#define ARMV8_ID_AA64ISAR1_EL1_DGH_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1377#define ARMV8_ID_AA64ISAR1_EL1_DGH_SHIFT 48
1378/** Data Gathering Hint instructions are not implemented. */
1379# define ARMV8_ID_AA64ISAR1_EL1_DGH_NOT_IMPL 0
1380/** Data Gathering Hint instructions are implemented (FEAT_DGH). */
1381# define ARMV8_ID_AA64ISAR1_EL1_DGH_SUPPORTED 1
1382/** Bit 52 - 55 - Indicates support for Advanced SIMD and Floating-point Int8 matri multiplication instructions. */
1383#define ARMV8_ID_AA64ISAR1_EL1_I8MM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1384#define ARMV8_ID_AA64ISAR1_EL1_I8MM_SHIFT 52
1385/** No Int8 matrix multiplication instructions implemented. */
1386# define ARMV8_ID_AA64ISAR1_EL1_I8MM_NOT_IMPL 0
1387/** SMMLA, SUDOT, UMMLA, USMMLA and USDOT instrutions are implemented (FEAT_I8MM). */
1388# define ARMV8_ID_AA64ISAR1_EL1_I8MM_SUPPORTED 1
1389/** Bit 56 - 59 - Indicates support for the XS attribute, the TLBI and DSB insturctions with the nXS qualifier in AArch64 state. */
1390#define ARMV8_ID_AA64ISAR1_EL1_XS_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1391#define ARMV8_ID_AA64ISAR1_EL1_XS_SHIFT 56
1392/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are not supported. */
1393# define ARMV8_ID_AA64ISAR1_EL1_XS_NOT_IMPL 0
1394/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are supported (FEAT_XS). */
1395# define ARMV8_ID_AA64ISAR1_EL1_XS_SUPPORTED 1
1396/** Bit 60 - 63 - Indicates support LD64B and ST64B* instructons and the ACCDATA_EL1 register. */
1397#define ARMV8_ID_AA64ISAR1_EL1_LS64_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1398#define ARMV8_ID_AA64ISAR1_EL1_LS64_SHIFT 60
1399/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are not supported. */
1400# define ARMV8_ID_AA64ISAR1_EL1_LS64_NOT_IMPL 0
1401/** The LD64B and ST64B instructions are supported (FEAT_LS64). */
1402# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED 1
1403/** The LD64B, ST64B, ST64BV and associated traps are not supported (FEAT_LS64_V). */
1404# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_V 2
1405/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are supported (FEAT_LS64_ACCDATA). */
1406# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_ACCDATA 3
1407/** @} */
1408
1409
1410/** @name ID_AA64ISAR2_EL1 - AArch64 Instruction Set Attribute Register 0.
1411 * @{ */
1412/** Bit 0 - 3 - Indicates support for WFET and WFIT instructions in AArch64 state. */
1413#define ARMV8_ID_AA64ISAR2_EL1_WFXT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1414#define ARMV8_ID_AA64ISAR2_EL1_WFXT_SHIFT 0
1415/** WFET and WFIT are not supported. */
1416# define ARMV8_ID_AA64ISAR2_EL1_WFXT_NOT_IMPL 0
1417/** WFET and WFIT are supported (FEAT_WFxT). */
1418# define ARMV8_ID_AA64ISAR2_EL1_WFXT_SUPPORTED 2
1419/** Bit 4 - 7 - Indicates support for 12 bits of mantissa in reciprocal and reciprocal square root instructions in AArch64 state, when FPCR.AH is 1. */
1420#define ARMV8_ID_AA64ISAR2_EL1_RPRES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1421#define ARMV8_ID_AA64ISAR2_EL1_RPRES_SHIFT 4
1422/** Reciprocal and reciprocal square root estimates give 8 bits of mantissa when FPCR.AH is 1. */
1423# define ARMV8_ID_AA64ISAR2_EL1_RPRES_NOT_IMPL 0
1424/** Reciprocal and reciprocal square root estimates give 12 bits of mantissa when FPCR.AH is 1 (FEAT_RPRES). */
1425# define ARMV8_ID_AA64ISAR2_EL1_RPRES_SUPPORTED 1
1426/** Bit 8 - 11 - Indicates whether the QARMA3 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1427#define ARMV8_ID_AA64ISAR2_EL1_GPA3_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1428#define ARMV8_ID_AA64ISAR2_EL1_GPA3_SHIFT 8
1429/** Generic Authentication using the QARMA3 algorithm is not implemented. */
1430# define ARMV8_ID_AA64ISAR2_EL1_GPA3_NOT_IMPL 0
1431/** Generic Authentication using the QARMA3 algorithm is implemented (FEAT_PACQARMA3). */
1432# define ARMV8_ID_AA64ISAR2_EL1_GPA3_SUPPORTED 1
1433/** Bit 12 - 15 - Indicates whether QARMA3 algorithm is implemented in the PE for address authentication. */
1434#define ARMV8_ID_AA64ISAR2_EL1_APA3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1435#define ARMV8_ID_AA64ISAR2_EL1_APA3_SHIFT 12
1436/** Address Authentication using the QARMA3 algorithm is not implemented. */
1437# define ARMV8_ID_AA64ISAR2_EL1_APA3_NOT_IMPL 0
1438/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA3). */
1439# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH 1
1440/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA3). */
1441# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_EPAC 2
1442/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA3). */
1443# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH2 3
1444/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA3). */
1445# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPAC 4
1446/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA3). */
1447# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPACCOMBINE 5
1448/** Bit 16 - 19 - Indicates support for Memory Copy and Memory Set instructions in AArch64 state. */
1449#define ARMV8_ID_AA64ISAR2_EL1_MOPS_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1450#define ARMV8_ID_AA64ISAR2_EL1_MOPS_SHIFT 16
1451/** No Memory Copy and Memory Set instructions implemented. */
1452# define ARMV8_ID_AA64ISAR2_EL1_MOPS_NOT_IMPL 0
1453/** Memory Copy and Memory Set instructions implemented (FEAT_MOPS). */
1454# define ARMV8_ID_AA64ISAR2_EL1_MOPS_SUPPORTED 1
1455/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1456#define ARMV8_ID_AA64ISAR2_EL1_BC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1457#define ARMV8_ID_AA64ISAR2_EL1_BC_SHIFT 20
1458/** BC instruction is not implemented. */
1459# define ARMV8_ID_AA64ISAR2_EL1_BC_NOT_IMPL 0
1460/** BC instruction is implemented (FEAT_HBC). */
1461# define ARMV8_ID_AA64ISAR2_EL1_BC_SUPPORTED 1
1462/** Bit 24 - 27 - Indicates whether the ConstPACField() functions used as part of PAC additions returns FALSE or TRUE. */
1463#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1464#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_SHIFT 24
1465/** ConstPACField() returns FALSE. */
1466# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_FALSE 0
1467/** ConstPACField() returns TRUE (FEAT_CONSTPACFIELD). */
1468# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_TRUE 1
1469/* Bit 28 - 63 - Reserved. */
1470/** @} */
1471
1472
1473/** @name ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0.
1474 * @{ */
1475/** Bit 0 - 3 - EL0 Exception level handling. */
1476#define ARMV8_ID_AA64PFR0_EL1_EL0_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1477#define ARMV8_ID_AA64PFR0_EL1_EL0_SHIFT 0
1478/** EL0 can be executed in AArch64 state only. */
1479# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_ONLY 1
1480/** EL0 can be executed in AArch64 and AArch32 state. */
1481# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_AARCH32 2
1482/** Bit 4 - 7 - EL1 Exception level handling. */
1483#define ARMV8_ID_AA64PFR0_EL1_EL1_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1484#define ARMV8_ID_AA64PFR0_EL1_EL1_SHIFT 4
1485/** EL1 can be executed in AArch64 state only. */
1486# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_ONLY 1
1487/** EL1 can be executed in AArch64 and AArch32 state. */
1488# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_AARCH32 2
1489/** Bit 8 - 11 - EL2 Exception level handling. */
1490#define ARMV8_ID_AA64PFR0_EL1_EL2_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1491#define ARMV8_ID_AA64PFR0_EL1_EL2_SHIFT 8
1492/** EL2 is not implemented. */
1493# define ARMV8_ID_AA64PFR0_EL1_EL2_NOT_IMPL 0
1494/** EL2 can be executed in AArch64 state only. */
1495# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_ONLY 1
1496/** EL2 can be executed in AArch64 and AArch32 state. */
1497# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_AARCH32 2
1498/** Bit 12 - 15 - EL3 Exception level handling. */
1499#define ARMV8_ID_AA64PFR0_EL1_EL3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1500#define ARMV8_ID_AA64PFR0_EL1_EL3_SHIFT 12
1501/** EL3 is not implemented. */
1502# define ARMV8_ID_AA64PFR0_EL1_EL3_NOT_IMPL 0
1503/** EL3 can be executed in AArch64 state only. */
1504# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_ONLY 1
1505/** EL3 can be executed in AArch64 and AArch32 state. */
1506# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_AARCH32 2
1507/** Bit 16 - 19 - Floating-point support. */
1508#define ARMV8_ID_AA64PFR0_EL1_FP_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1509#define ARMV8_ID_AA64PFR0_EL1_FP_SHIFT 16
1510/** Floating-point is implemented and support single and double precision. */
1511# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP 0
1512/** Floating-point is implemented and support single, double and half precision. */
1513# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP_HP 1
1514/** Floating-point is not implemented. */
1515# define ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL 0xf
1516/** Bit 20 - 23 - Advanced SIMD support. */
1517#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1518#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_SHIFT 20
1519/** Advanced SIMD is implemented and support single and double precision. */
1520# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP 0
1521/** Advanced SIMD is implemented and support single, double and half precision. */
1522# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP_HP 1
1523/** Advanced SIMD is not implemented. */
1524# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL 0xf
1525/** Bit 24 - 27 - System register GIC CPU interface support. */
1526#define ARMV8_ID_AA64PFR0_EL1_GIC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1527#define ARMV8_ID_AA64PFR0_EL1_GIC_SHIFT 24
1528/** GIC CPU interface system registers are not implemented. */
1529# define ARMV8_ID_AA64PFR0_EL1_GIC_NOT_IMPL 0
1530/** System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. */
1531# define ARMV8_ID_AA64PFR0_EL1_GIC_V3_V4 1
1532/** System register interface to version 4.1 of the GIC CPU interface is supported. */
1533# define ARMV8_ID_AA64PFR0_EL1_GIC_V4_1 3
1534/** Bit 28 - 31 - RAS Extension version. */
1535#define ARMV8_ID_AA64PFR0_EL1_RAS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1536#define ARMV8_ID_AA64PFR0_EL1_RAS_SHIFT 28
1537/** No RAS extension. */
1538# define ARMV8_ID_AA64PFR0_EL1_RAS_NOT_IMPL 0
1539/** RAS Extension implemented. */
1540# define ARMV8_ID_AA64PFR0_EL1_RAS_SUPPORTED 1
1541/** FEAT_RASv1p1 implemented. */
1542# define ARMV8_ID_AA64PFR0_EL1_RAS_V1P1 2
1543/** Bit 32 - 35 - Scalable Vector Extension (SVE) support. */
1544#define ARMV8_ID_AA64PFR0_EL1_SVE_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1545#define ARMV8_ID_AA64PFR0_EL1_SVE_SHIFT 32
1546/** SVE is not supported. */
1547# define ARMV8_ID_AA64PFR0_EL1_SVE_NOT_IMPL 0
1548/** SVE is supported. */
1549# define ARMV8_ID_AA64PFR0_EL1_SVE_SUPPORTED 1
1550/** Bit 36 - 39 - Secure EL2 support. */
1551#define ARMV8_ID_AA64PFR0_EL1_SEL2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1552#define ARMV8_ID_AA64PFR0_EL1_SEL2_SHIFT 36
1553/** Secure EL2 is not supported. */
1554# define ARMV8_ID_AA64PFR0_EL1_SEL2_NOT_IMPL 0
1555/** Secure EL2 is implemented. */
1556# define ARMV8_ID_AA64PFR0_EL1_SEL2_SUPPORTED 1
1557/** Bit 40 - 43 - MPAM support. */
1558#define ARMV8_ID_AA64PFR0_EL1_MPAM_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1559#define ARMV8_ID_AA64PFR0_EL1_MPAM_SHIFT 40
1560/** MPAM extension major version number is 0. */
1561# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V0 0
1562/** MPAM extension major version number is 1. */
1563# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V1 1
1564/** Bit 44 - 47 - Activity Monitor Extension support. */
1565#define ARMV8_ID_AA64PFR0_EL1_AMU_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1566#define ARMV8_ID_AA64PFR0_EL1_AMU_SHIFT 44
1567/** Activity Monitor extension is not implemented. */
1568# define ARMV8_ID_AA64PFR0_EL1_AMU_NOT_IMPL 0
1569/** Activity Monitor extension is implemented as of FEAT_AMUv1. */
1570# define ARMV8_ID_AA64PFR0_EL1_AMU_V1 1
1571/** Activity Monitor extension is implemented as of FEAT_AMUv1p1 including virtualization support. */
1572# define ARMV8_ID_AA64PFR0_EL1_AMU_V1P1 2
1573/** Bit 48 - 51 - Data Independent Timing support. */
1574#define ARMV8_ID_AA64PFR0_EL1_DIT_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1575#define ARMV8_ID_AA64PFR0_EL1_DIT_SHIFT 48
1576/** AArch64 does not guarantee constant execution time of any instructions. */
1577# define ARMV8_ID_AA64PFR0_EL1_DIT_NOT_IMPL 0
1578/** AArch64 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions (FEAT_DIT). */
1579# define ARMV8_ID_AA64PFR0_EL1_DIT_SUPPORTED 1
1580/** Bit 52 - 55 - Realm Management Extension support. */
1581#define ARMV8_ID_AA64PFR0_EL1_RME_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1582#define ARMV8_ID_AA64PFR0_EL1_RME_SHIFT 52
1583/** Realm Management Extension not implemented. */
1584# define ARMV8_ID_AA64PFR0_EL1_RME_NOT_IMPL 0
1585/** RMEv1 is implemented (FEAT_RME). */
1586# define ARMV8_ID_AA64PFR0_EL1_RME_SUPPORTED 1
1587/** Bit 56 - 59 - Speculative use out of context branch targets support. */
1588#define ARMV8_ID_AA64PFR0_EL1_CSV2_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1589#define ARMV8_ID_AA64PFR0_EL1_CSV2_SHIFT 56
1590/** Implementation does not disclose whether FEAT_CSV2 is implemented. */
1591# define ARMV8_ID_AA64PFR0_EL1_CSV2_NOT_EXPOSED 0
1592/** FEAT_CSV2 is implemented. */
1593# define ARMV8_ID_AA64PFR0_EL1_CSV2_SUPPORTED 1
1594/** FEAT_CSV2_2 is implemented. */
1595# define ARMV8_ID_AA64PFR0_EL1_CSV2_2_SUPPORTED 2
1596/** FEAT_CSV2_3 is implemented. */
1597# define ARMV8_ID_AA64PFR0_EL1_CSV2_3_SUPPORTED 3
1598/** Bit 60 - 63 - Speculative use of faulting data support. */
1599#define ARMV8_ID_AA64PFR0_EL1_CSV3_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1600#define ARMV8_ID_AA64PFR0_EL1_CSV3_SHIFT 60
1601/** Implementation does not disclose whether data loaded under speculation with a permission or domain fault can be used. */
1602# define ARMV8_ID_AA64PFR0_EL1_CSV3_NOT_EXPOSED 0
1603/** FEAT_CSV3 is supported . */
1604# define ARMV8_ID_AA64PFR0_EL1_CSV3_SUPPORTED 1
1605/** @} */
1606
1607
1608/** @name ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1.
1609 * @{ */
1610/** Bit 0 - 3 - Branch Target Identification support. */
1611#define ARMV8_ID_AA64PFR1_EL1_BT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1612#define ARMV8_ID_AA64PFR1_EL1_BT_SHIFT 0
1613/** The Branch Target Identification mechanism is not implemented. */
1614# define ARMV8_ID_AA64PFR1_EL1_BT_NOT_IMPL 0
1615/** The Branch Target Identifcation mechanism is implemented. */
1616# define ARMV8_ID_AA64PFR1_EL1_BT_SUPPORTED 1
1617/** Bit 4 - 7 - Speculative Store Bypassing control support. */
1618#define ARMV8_ID_AA64PFR1_EL1_SSBS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1619#define ARMV8_ID_AA64PFR1_EL1_SSBS_SHIFT 4
1620/** AArch64 provides no mechanism to control the use of Speculative Store Bypassing. */
1621# define ARMV8_ID_AA64PFR1_EL1_SSBS_NOT_IMPL 0
1622/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe. */
1623# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED 1
1624/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe and adds MSR and MRS instructions
1625 * to directly read and write the PSTATE.SSBS field. */
1626# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED_MSR_MRS 2
1627/** Bit 8 - 11 - Memory Tagging Extension support. */
1628#define ARMV8_ID_AA64PFR1_EL1_MTE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1629#define ARMV8_ID_AA64PFR1_EL1_MTE_SHIFT 8
1630/** MTE is not implemented. */
1631# define ARMV8_ID_AA64PFR1_EL1_MTE_NOT_IMPL 0
1632/** Instruction only Memory Tagging Extensions implemented. */
1633# define ARMV8_ID_AA64PFR1_EL1_MTE_INSN_ONLY 1
1634/** Full Memory Tagging Extension implemented. */
1635# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL 2
1636/** Full Memory Tagging Extension with asymmetric Tag Check Fault handling implemented. */
1637# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL_ASYM_TAG_FAULT_CHK 3
1638/** Bit 12 - 15 - RAS Extension fractional field. */
1639#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1640#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_SHIFT 12
1641/** RAS Extension is implemented. */
1642# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_IMPL 0
1643/** FEAT_RASv1p1 is implemented. */
1644# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_RASV1P1 1
1645/** Bit 16 - 19 - MPAM minor version number. */
1646#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1647#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_SHIFT 16
1648/** The minor version of number of the MPAM extension is 0. */
1649# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_0 0
1650/** The minor version of number of the MPAM extension is 1. */
1651# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_1 1
1652/* Bit 20 - 23 - Reserved. */
1653/** Bit 24 - 27 - Scalable Matrix Extension support. */
1654#define ARMV8_ID_AA64PFR1_EL1_SME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1655#define ARMV8_ID_AA64PFR1_EL1_SME_SHIFT 24
1656/** Scalable Matrix Extensions are not implemented. */
1657# define ARMV8_ID_AA64PFR1_EL1_SME_NOT_IMPL 0
1658/** Scalable Matrix Extensions are implemented (FEAT_SME). */
1659# define ARMV8_ID_AA64PFR1_EL1_SME_SUPPORTED 1
1660/** Scalable Matrix Extensions are implemented + SME2 ZT0 register(FEAT_SME2). */
1661# define ARMV8_ID_AA64PFR1_EL1_SME_SME2 2
1662/** Bit 28 - 31 - Random Number trap to EL3 support. */
1663#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1664#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SHIFT 28
1665/** Trapping of RNDR and RNDRRS to EL3 is not supported. */
1666# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_NOT_IMPL 0
1667/** Trapping of RNDR and RDNRRS to EL3 is supported. */
1668# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SUPPORTED 1
1669/** Bit 32 - 35 - CSV2 fractional field. */
1670#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1671#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_SHIFT 32
1672/** Either CSV2 not exposed or implementation does not expose whether FEAT_CSV2_1p1 is implemented. */
1673# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_NOT_EXPOSED 0
1674/** FEAT_CSV2_1p1 is implemented. */
1675# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P1 1
1676/** FEAT_CSV2_1p2 is implemented. */
1677# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P2 2
1678/** Bit 36 - 39 - Non-maskable Interrupt support. */
1679#define ARMV8_ID_AA64PFR1_EL1_NMI_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1680#define ARMV8_ID_AA64PFR1_EL1_NMI_SHIFT 36
1681/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are not supported. */
1682# define ARMV8_ID_AA64PFR1_EL1_NMI_NOT_IMPL 0
1683/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are supported (FEAT_NMI). */
1684# define ARMV8_ID_AA64PFR1_EL1_NMI_SUPPORTED 1
1685/** @} */
1686
1687
1688/** @name ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0.
1689 * @{ */
1690/** Bit 0 - 3 - Physical Address range supported. */
1691#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1692#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_SHIFT 0
1693/** Physical Address range is 32 bits, 4GiB. */
1694# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_32BITS 0
1695/** Physical Address range is 36 bits, 64GiB. */
1696# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_36BITS 1
1697/** Physical Address range is 40 bits, 1TiB. */
1698# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_40BITS 2
1699/** Physical Address range is 42 bits, 4TiB. */
1700# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_42BITS 3
1701/** Physical Address range is 44 bits, 16TiB. */
1702# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_44BITS 4
1703/** Physical Address range is 48 bits, 256TiB. */
1704# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_48BITS 5
1705/** Physical Address range is 52 bits, 4PiB. */
1706# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_52BITS 6
1707/** Bit 4 - 7 - Number of ASID bits. */
1708#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1709#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4
1710/** ASID bits is 8. */
1711# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_8 0
1712/** ASID bits is 16. */
1713# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_16 2
1714/** Bit 8 - 11 - Indicates support for mixed-endian configuration. */
1715#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1716#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SHIFT 8
1717/** No mixed-endian support. */
1718# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_NOT_IMPL 0
1719/** Mixed-endian supported. */
1720# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SUPPORTED 1
1721/** Bit 12 - 15 - Indicates support for a distinction between Secure and Non-secure Memory. */
1722#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1723#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12
1724/** No distinction between Secure and Non-secure Memory supported. */
1725# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_NOT_IMPL 0
1726/** Distinction between Secure and Non-secure Memory supported. */
1727# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SUPPORTED 1
1728/** Bit 16 - 19 - Indicates support for mixed-endian at EL0 only. */
1729#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1730#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16
1731/** No mixed-endian support at EL0. */
1732# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_NOT_IMPL 0
1733/** Mixed-endian support at EL0. */
1734# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SUPPORTED 1
1735/** Bit 20 - 23 - Indicates support for 16KiB memory translation granule size. */
1736#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1737#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20
1738/** 16KiB granule size not supported. */
1739# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_NOT_IMPL 0
1740/** 16KiB granule size is supported. */
1741# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED 1
1742/** 16KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1743# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_52BIT 2
1744/** Bit 24 - 27 - Indicates support for 64KiB memory translation granule size. */
1745#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1746#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24
1747/** 64KiB granule supported. */
1748# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED 0
1749/** 64KiB granule not supported. */
1750# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL 0xf
1751/** Bit 28 - 31 - Indicates support for 4KiB memory translation granule size. */
1752#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1753#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28
1754/** 4KiB granule supported. */
1755# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED 0
1756/** 4KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1757# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_52BIT 1
1758/** 4KiB granule not supported. */
1759# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL 0xf
1760/** Bit 32 - 35 - Indicates support for 16KiB granule size at stage 2. */
1761#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1762#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32
1763/** Support for 16KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran16 field. */
1764# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORT_BY_TGRAN16 0
1765/** 16KiB granule not supported at stage 2. */
1766# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_NOT_IMPL 1
1767/** 16KiB granule supported at stage 2. */
1768# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED 2
1769/** 16KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1770# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED_52BIT 3
1771/** Bit 36 - 39 - Indicates support for 64KiB granule size at stage 2. */
1772#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1773#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36
1774/** Support for 64KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran64 field. */
1775# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORT_BY_TGRAN64 0
1776/** 64KiB granule not supported at stage 2. */
1777# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_NOT_IMPL 1
1778/** 64KiB granule supported at stage 2. */
1779# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORTED 2
1780/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
1781#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1782#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40
1783/** Support for 4KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran4 field. */
1784# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORT_BY_TGRAN16 0
1785/** 4KiB granule not supported at stage 2. */
1786# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_NOT_IMPL 1
1787/** 4KiB granule supported at stage 2. */
1788# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED 2
1789/** 4KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1790# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED_52BIT 3
1791/** Bit 44 - 47 - Indicates support for disabling context synchronizing exception entry and exit. */
1792#define ARMV8_ID_AA64MMFR0_EL1_EXS_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1793#define ARMV8_ID_AA64MMFR0_EL1_EXS_SHIFT 44
1794/** All exception entries and exits are context synchronization events. */
1795# define ARMV8_ID_AA64MMFR0_EL1_EXS_NOT_IMPL 0
1796/** Non-context synchronizing exception entry and exit are supported (FEAT_ExS). */
1797# define ARMV8_ID_AA64MMFR0_EL1_EXS_SUPPORTED 1
1798/* Bit 48 - 55 - Reserved. */
1799/** Bit 56 - 59 - Indicates the presence of the Fine-Grained Trap controls. */
1800#define ARMV8_ID_AA64MMFR0_EL1_FGT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1801#define ARMV8_ID_AA64MMFR0_EL1_FGT_SHIFT 56
1802/** Fine-grained trap controls are not implemented. */
1803# define ARMV8_ID_AA64MMFR0_EL1_FGT_NOT_IMPL 0
1804/** Fine-grained trap controls are implemented (FEAT_FGT). */
1805# define ARMV8_ID_AA64MMFR0_EL1_FGT_SUPPORTED 1
1806/** Bit 60 - 63 - Indicates the presence of Enhanced Counter Virtualization. */
1807#define ARMV8_ID_AA64MMFR0_EL1_ECV_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1808#define ARMV8_ID_AA64MMFR0_EL1_ECV_SHIFT 60
1809/** Enhanced Counter Virtualization is not implemented. */
1810# define ARMV8_ID_AA64MMFR0_EL1_ECV_NOT_IMPL 0
1811/** Enhanced Counter Virtualization is implemented (FEAT_ECV). */
1812# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED 1
1813/** Enhanced Counter Virtualization is implemented and includes support for CNTHCTL_EL2.ECV and CNTPOFF_EL2 (FEAT_ECV). */
1814# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED_2 2
1815/** @} */
1816
1817
1818/** @name ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1.
1819 * @{ */
1820/** Bit 0 - 3 - Hardware updates to Access flag and Dirty state in translation tables. */
1821#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1822#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0
1823/** Hardware update of the Access flag and dirty state are not supported. */
1824# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_NOT_IMPL 0
1825/** Support for hardware update of the Access flag for Block and Page descriptors. */
1826# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SUPPORTED 1
1827/** Support for hardware update of the Access flag for Block and Page descriptors, hardware update of dirty state supported. */
1828# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_DIRTY_SUPPORTED 2
1829/** Bit 4 - 7 - EL1 Exception level handling. */
1830#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1831#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_SHIFT 4
1832/** VMID bits is 8. */
1833# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_8 0
1834/** VMID bits is 16 (FEAT_VMID16). */
1835# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_16 2
1836/** Bit 8 - 11 - Virtualization Host Extensions support. */
1837#define ARMV8_ID_AA64MMFR1_EL1_VHE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1838#define ARMV8_ID_AA64MMFR1_EL1_VHE_SHIFT 8
1839/** Virtualization Host Extensions are not supported. */
1840# define ARMV8_ID_AA64MMFR1_EL1_VHE_NOT_IMPL 0
1841/** Virtualization Host Extensions are supported. */
1842# define ARMV8_ID_AA64MMFR1_EL1_VHE_SUPPORTED 1
1843/** Bit 12 - 15 - Hierarchical Permission Disables. */
1844#define ARMV8_ID_AA64MMFR1_EL1_HPDS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1845#define ARMV8_ID_AA64MMFR1_EL1_HPDS_SHIFT 12
1846/** Disabling of hierarchical controls not supported. */
1847# define ARMV8_ID_AA64MMFR1_EL1_HPDS_NOT_IMPL 0
1848/** Disabling of hierarchical controls supported (FEAT_HPDS). */
1849# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED 1
1850/** FEAT_HPDS + possible hardware allocation of bits[62:59] of the translation table descriptors from the final lookup level (FEAT_HPDS2). */
1851# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED_2 2
1852/** Bit 16 - 19 - LORegions support. */
1853#define ARMV8_ID_AA64MMFR1_EL1_LO_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1854#define ARMV8_ID_AA64MMFR1_EL1_LO_SHIFT 16
1855/** LORegions not supported. */
1856# define ARMV8_ID_AA64MMFR1_EL1_LO_NOT_IMPL 0
1857/** LORegions supported. */
1858# define ARMV8_ID_AA64MMFR1_EL1_LO_SUPPORTED 1
1859/** Bit 20 - 23 - Privileged Access Never support. */
1860#define ARMV8_ID_AA64MMFR1_EL1_PAN_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1861#define ARMV8_ID_AA64MMFR1_EL1_PAN_SHIFT 20
1862/** PAN not supported. */
1863# define ARMV8_ID_AA64MMFR1_EL1_PAN_NOT_IMPL 0
1864/** PAN supported (FEAT_PAN). */
1865# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED 1
1866/** PAN supported and AT S1E1RP and AT S1E1WP instructions supported (FEAT_PAN2). */
1867# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_2 2
1868/** PAN supported and AT S1E1RP and AT S1E1WP instructions and SCTRL_EL1.EPAN and SCTRL_EL2.EPAN supported (FEAT_PAN3). */
1869# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_3 3
1870/** Bit 24 - 27 - Describes whether the PE can generate SError interrupt exceptions. */
1871#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1872#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SHIFT 24
1873/** The PE never generates an SError interrupt due to an External abort on a speculative read. */
1874# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_NOT_IMPL 0
1875/** The PE might generate an SError interrupt due to an External abort on a speculative read. */
1876# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SUPPORTED 1
1877/** Bit 28 - 31 - Indicates support for execute-never control distinction by Exception level at stage 2. */
1878#define ARMV8_ID_AA64MMFR1_EL1_XNX_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1879#define ARMV8_ID_AA64MMFR1_EL1_XNX_SHIFT 28
1880/** Distinction between EL0 and EL1 execute-never control at stage 2 not supported. */
1881# define ARMV8_ID_AA64MMFR1_EL1_XNX_NOT_IMPL 0
1882/** Distinction between EL0 and EL1 execute-never control at stage 2 supported (FEAT_XNX). */
1883# define ARMV8_ID_AA64MMFR1_EL1_XNX_SUPPORTED 1
1884/** Bit 32 - 35 - Indicates support for the configurable delayed trapping of WFE. */
1885#define ARMV8_ID_AA64MMFR1_EL1_TWED_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1886#define ARMV8_ID_AA64MMFR1_EL1_TWED_SHIFT 32
1887/** Configurable delayed trapping of WFE is not supported. */
1888# define ARMV8_ID_AA64MMFR1_EL1_TWED_NOT_IMPL 0
1889/** Configurable delayed trapping of WFE is supported (FEAT_TWED). */
1890# define ARMV8_ID_AA64MMFR1_EL1_TWED_SUPPORTED 1
1891/** Bit 36 - 39 - Indicates support for Enhanced Translation Synchronization. */
1892#define ARMV8_ID_AA64MMFR1_EL1_ETS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1893#define ARMV8_ID_AA64MMFR1_EL1_ETS_SHIFT 36
1894/** Enhanced Translation Synchronization is not supported. */
1895# define ARMV8_ID_AA64MMFR1_EL1_ETS_NOT_IMPL 0
1896/** Enhanced Translation Synchronization is implemented. */
1897# define ARMV8_ID_AA64MMFR1_EL1_ETS_SUPPORTED 1
1898/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
1899#define ARMV8_ID_AA64MMFR1_EL1_HCX_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1900#define ARMV8_ID_AA64MMFR1_EL1_HCX_SHIFT 40
1901/** HCRX_EL2 and its associated EL3 trap are not supported. */
1902# define ARMV8_ID_AA64MMFR1_EL1_HCX_NOT_IMPL 0
1903/** HCRX_EL2 and its associated EL3 trap are supported (FEAT_HCX). */
1904# define ARMV8_ID_AA64MMFR1_EL1_HCX_SUPPORTED 1
1905/** Bit 44 - 47 - Indicates support for FPCR.{AH,FIZ,NEP}. */
1906#define ARMV8_ID_AA64MMFR1_EL1_AFP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1907#define ARMV8_ID_AA64MMFR1_EL1_AFP_SHIFT 44
1908/** The FPCR.{AH,FIZ,NEP} fields are not supported. */
1909# define ARMV8_ID_AA64MMFR1_EL1_AFP_NOT_IMPL 0
1910/** The FPCR.{AH,FIZ,NEP} fields are supported (FEAT_AFP). */
1911# define ARMV8_ID_AA64MMFR1_EL1_AFP_SUPPORTED 1
1912/** Bit 48 - 51 - Indicates support for intermediate caching of translation table walks. */
1913#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1914#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_SHIFT 48
1915/** The intermediate caching of translation table walks might include non-coherent physical translation caches. */
1916# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_NON_COHERENT 0
1917/** The intermediate caching of translation table walks does not include non-coherent physical translation caches (FEAT_nTLBPA). */
1918# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_COHERENT_ONLY 1
1919/** Bit 52 - 55 - Indicates whether SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP are implemented in AArch64 state. */
1920#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1921#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SHIFT 52
1922/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are not implemented. */
1923# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_NOT_IMPL 0
1924/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are implemented (FEAT_TIDCP1). */
1925# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SUPPORTED 1
1926/** Bit 56 - 59 - Indicates support for cache maintenance instruction permission. */
1927#define ARMV8_ID_AA64MMFR1_EL1_CMOW_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1928#define ARMV8_ID_AA64MMFR1_EL1_CMOW_SHIFT 56
1929/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are not implemented. */
1930# define ARMV8_ID_AA64MMFR1_EL1_CMOW_NOT_IMPL 0
1931/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are implemented (FEAT_CMOW). */
1932# define ARMV8_ID_AA64MMFR1_EL1_CMOW_SUPPORTED 1
1933/* Bit 60 - 63 - Reserved. */
1934/** @} */
1935
1936
1937/** @} */
1938
1939#endif /* !IPRT_INCLUDED_armv8_h */
1940
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