VirtualBox

source: vbox/trunk/include/VBox/x86.mac@ 19559

Last change on this file since 19559 was 18842, checked in by vboxsync, 16 years ago

iprt/err.mac,VBox/err.mac,VBox/x86.mac: regenerated.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 24.3 KB
Line 
1%define ___VBox_x86_h
2%define X86_EFL_CF RT_BIT(0)
3%define X86_EFL_PF RT_BIT(2)
4%define X86_EFL_AF RT_BIT(4)
5%define X86_EFL_ZF RT_BIT(6)
6%define X86_EFL_SF RT_BIT(7)
7%define X86_EFL_TF RT_BIT(8)
8%define X86_EFL_IF RT_BIT(9)
9%define X86_EFL_DF RT_BIT(10)
10%define X86_EFL_OF RT_BIT(11)
11%define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
12%define X86_EFL_NT RT_BIT(14)
13%define X86_EFL_RF RT_BIT(16)
14%define X86_EFL_VM RT_BIT(17)
15%define X86_EFL_AC RT_BIT(18)
16%define X86_EFL_VIF RT_BIT(19)
17%define X86_EFL_VIP RT_BIT(20)
18%define X86_EFL_ID RT_BIT(21)
19%define X86_EFL_IOPL_SHIFT 12
20%define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
21%define X86_EFL_POPF_BITS (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID)
22%define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
23%define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
24%define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
25%define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
26%define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
27%define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
28%define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
29%define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
30%define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
31%define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
32%define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
33%define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
34%define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
35%define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
36%define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
37%define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
38%define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
39%define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
40%define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
41%define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
42%define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
43%define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
44%define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
45%define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
46%define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
47%define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
48%define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
49%define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
50%define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
51%define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
52%define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
53%define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
54%define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
55%define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
56%define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
57%define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
58%define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
59%define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
60%define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
61%define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
62%define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
63%define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
64%define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
65%define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
66%define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
67%define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
68%define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
69%define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
70%define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
71%define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
72%define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
73%define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
74%define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
75%define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
76%define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
77%define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
78%define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
79%define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
80%define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
81%define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
82%define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
83%define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
84%define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
85%define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
86%define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
87%define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
88%define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
89%define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
90%define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
91%define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
92%define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
93%define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
94%define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
95%define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
96%define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
97%define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
98%define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
99%define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
100%define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
101%define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
102%define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
103%define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
104%define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
105%define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
106%define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
107%define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
108%define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
109%define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
110%define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
111%define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
112%define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
113%define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
114%define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
115%define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
116%define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
117%define X86_CR0_PE RT_BIT(0)
118%define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
119%define X86_CR0_MP RT_BIT(1)
120%define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
121%define X86_CR0_EM RT_BIT(2)
122%define X86_CR0_EMULATE_FPU RT_BIT(2)
123%define X86_CR0_TS RT_BIT(3)
124%define X86_CR0_TASK_SWITCH RT_BIT(3)
125%define X86_CR0_ET RT_BIT(4)
126%define X86_CR0_EXTENSION_TYPE RT_BIT(4)
127%define X86_CR0_NE RT_BIT(5)
128%define X86_CR0_NUMERIC_ERROR RT_BIT(5)
129%define X86_CR0_WP RT_BIT(16)
130%define X86_CR0_WRITE_PROTECT RT_BIT(16)
131%define X86_CR0_AM RT_BIT(18)
132%define X86_CR0_ALIGMENT_MASK RT_BIT(18)
133%define X86_CR0_NW RT_BIT(29)
134%define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
135%define X86_CR0_CD RT_BIT(30)
136%define X86_CR0_CACHE_DISABLE RT_BIT(30)
137%define X86_CR0_PG RT_BIT(31)
138%define X86_CR0_PAGING RT_BIT(31)
139%define X86_CR3_PWT RT_BIT(3)
140%define X86_CR3_PCD RT_BIT(4)
141%define X86_CR3_PAGE_MASK (0xfffff000)
142%define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
143%define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
144%define X86_CR4_VME RT_BIT(0)
145%define X86_CR4_PVI RT_BIT(1)
146%define X86_CR4_TSD RT_BIT(2)
147%define X86_CR4_DE RT_BIT(3)
148%define X86_CR4_PSE RT_BIT(4)
149%define X86_CR4_PAE RT_BIT(5)
150%define X86_CR4_MCE RT_BIT(6)
151%define X86_CR4_PGE RT_BIT(7)
152%define X86_CR4_PCE RT_BIT(8)
153%define X86_CR4_OSFSXR RT_BIT(9)
154%define X86_CR4_OSXMMEEXCPT RT_BIT(10)
155%define X86_CR4_VMXE RT_BIT(13)
156%define X86_DR6_B0 RT_BIT(0)
157%define X86_DR6_B1 RT_BIT(1)
158%define X86_DR6_B2 RT_BIT(2)
159%define X86_DR6_B3 RT_BIT(3)
160%define X86_DR6_BD RT_BIT(13)
161%define X86_DR6_BS RT_BIT(14)
162%define X86_DR6_BT RT_BIT(15)
163%define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
164%define X86_DR7_L0 RT_BIT(0)
165%define X86_DR7_G0 RT_BIT(1)
166%define X86_DR7_L1 RT_BIT(2)
167%define X86_DR7_G1 RT_BIT(3)
168%define X86_DR7_L2 RT_BIT(4)
169%define X86_DR7_G2 RT_BIT(5)
170%define X86_DR7_L3 RT_BIT(6)
171%define X86_DR7_G3 RT_BIT(7)
172%define X86_DR7_LE RT_BIT(8)
173%define X86_DR7_GE RT_BIT(9)
174%define X86_DR7_GD RT_BIT(13)
175%define X86_DR7_RW0_MASK (3 << 16)
176%define X86_DR7_LEN0_MASK (3 << 18)
177%define X86_DR7_RW1_MASK (3 << 20)
178%define X86_DR7_LEN1_MASK (3 << 22)
179%define X86_DR7_RW2_MASK (3 << 24)
180%define X86_DR7_LEN2_MASK (3 << 26)
181%define X86_DR7_RW3_MASK (3 << 28)
182%define X86_DR7_LEN3_MASK (3 << 30)
183%define X86_DR7_MB1_MASK (RT_BIT(10))
184%define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
185%define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
186%define X86_DR7_RW_EO 0
187%define X86_DR7_RW_WO 1
188%define X86_DR7_RW_IO 2
189%define X86_DR7_RW_RW 3
190%define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
191%define X86_DR7_LEN_BYTE 0
192%define X86_DR7_LEN_WORD 1
193%define X86_DR7_LEN_QWORD 2
194%define X86_DR7_LEN_DWORD 3
195%define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
196%define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
197%define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7))
198%define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) | X86_DR7_RW(1, X86_DR7_RW_IO) | X86_DR7_RW(2, X86_DR7_RW_IO) | X86_DR7_RW(3, X86_DR7_RW_IO))
199%define X86_DR7_INIT_VAL 0x400
200%define MSR_IA32_TSC 0x10
201%define MSR_IA32_PLATFORM_ID 0x17
202%define MSR_IA32_APICBASE 0x1b
203%define MSR_IA32_FEATURE_CONTROL 0x3A
204%define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
205%define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
206%define MSR_IA32_BIOS_UPDT_TRIG 0x79
207%define MSR_IA32_BIOS_SIGN_ID 0x8B
208%define MSR_IA32_MTRR_CAP 0xFE
209%define MSR_IA32_SYSENTER_CS 0x174
210%define MSR_IA32_SYSENTER_ESP 0x175
211%define MSR_IA32_SYSENTER_EIP 0x176
212%define MSR_IA32_MCP_CAP 0x179
213%define MSR_IA32_MCP_STATUS 0x17A
214%define MSR_IA32_MCP_CTRL 0x17B
215%define MSR_IA32_CR_PAT 0x277
216%define MSR_IA32_PERFEVTSEL0 0x186
217%define MSR_IA32_PERFEVTSEL1 0x187
218%define MSR_IA32_PERF_STATUS 0x198
219%define MSR_IA32_PERF_CTL 0x199
220%define MSR_IA32_MTRR_DEF_TYPE 0x2FF
221%define MSR_IA32_MC0_CTL 0x400
222%define MSR_IA32_MC0_STATUS 0x401
223%define MSR_IA32_VMX_BASIC_INFO 0x480
224%define MSR_IA32_VMX_PINBASED_CTLS 0x481
225%define MSR_IA32_VMX_PROCBASED_CTLS 0x482
226%define MSR_IA32_VMX_EXIT_CTLS 0x483
227%define MSR_IA32_VMX_ENTRY_CTLS 0x484
228%define MSR_IA32_VMX_MISC 0x485
229%define MSR_IA32_VMX_CR0_FIXED0 0x486
230%define MSR_IA32_VMX_CR0_FIXED1 0x487
231%define MSR_IA32_VMX_CR4_FIXED0 0x488
232%define MSR_IA32_VMX_CR4_FIXED1 0x489
233%define MSR_IA32_VMX_VMCS_ENUM 0x48A
234%define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
235%define MSR_IA32_VMX_EPT_CAPS 0x48C
236%define MSR_IA32_APIC_START 0x800
237%define MSR_IA32_APIC_END 0x900
238%define MSR_K6_EFER 0xc0000080
239%define MSR_K6_EFER_SCE RT_BIT(0)
240%define MSR_K6_EFER_LME RT_BIT(8)
241%define MSR_K6_EFER_LMA RT_BIT(10)
242%define MSR_K6_EFER_NXE RT_BIT(11)
243%define MSR_K6_EFER_SVME RT_BIT(12)
244%define MSR_K6_EFER_LMSLE RT_BIT(13)
245%define MSR_K6_EFER_FFXSR RT_BIT(14)
246%define MSR_K6_STAR 0xc0000081
247%define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
248%define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
249%define MSR_K6_STAR_SEL_MASK 0xffff
250%define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
251%define MSR_K6_WHCR 0xc0000082
252%define MSR_K6_UWCCR 0xc0000085
253%define MSR_K6_PSOR 0xc0000087
254%define MSR_K6_PFIR 0xc0000088
255%define MSR_K7_EVNTSEL0 0xc0010000
256%define MSR_K7_EVNTSEL1 0xc0010001
257%define MSR_K7_EVNTSEL2 0xc0010002
258%define MSR_K7_EVNTSEL3 0xc0010003
259%define MSR_K7_PERFCTR0 0xc0010004
260%define MSR_K7_PERFCTR1 0xc0010005
261%define MSR_K7_PERFCTR2 0xc0010006
262%define MSR_K7_PERFCTR3 0xc0010007
263%define MSR_K8_LSTAR 0xc0000082
264%define MSR_K8_CSTAR 0xc0000083
265%define MSR_K8_SF_MASK 0xc0000084
266%define MSR_K8_FS_BASE 0xc0000100
267%define MSR_K8_GS_BASE 0xc0000101
268%define MSR_K8_KERNEL_GS_BASE 0xc0000102
269%define MSR_K8_TSC_AUX 0xc0000103
270%define MSR_K8_SYSCFG 0xc0010010
271%define MSR_K8_HWCR 0xc0010015
272%define MSR_K8_IORRBASE0 0xc0010016
273%define MSR_K8_IORRMASK0 0xc0010017
274%define MSR_K8_IORRBASE1 0xc0010018
275%define MSR_K8_IORRMASK1 0xc0010019
276%define MSR_K8_TOP_MEM1 0xc001001a
277%define MSR_K8_TOP_MEM2 0xc001001d
278%define MSR_K8_VM_CR 0xc0010114
279%define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
280%define MSR_K8_IGNNE 0xc0010115
281%define MSR_K8_SMM_CTL 0xc0010116
282%define MSR_K8_VM_HSAVE_PA 0xc0010117
283%define X86_PG_ENTRIES 1024
284%define X86_PG_PAE_ENTRIES 512
285%define X86_PG_PAE_PDPE_ENTRIES 4
286%define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
287%define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
288%define X86_PAGE_4K_SIZE _4K
289%define X86_PAGE_4K_SHIFT 12
290%define X86_PAGE_4K_OFFSET_MASK 0xfff
291%define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
292%define X86_PAGE_4K_BASE_MASK_32 0xfffff000
293%define X86_PAGE_2M_SIZE _2M
294%define X86_PAGE_2M_SHIFT 21
295%define X86_PAGE_2M_OFFSET_MASK 0x001fffff
296%define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
297%define X86_PAGE_2M_BASE_MASK_32 0xffe00000
298%define X86_PAGE_4M_SIZE _4M
299%define X86_PAGE_4M_SHIFT 22
300%define X86_PAGE_4M_OFFSET_MASK 0x003fffff
301%define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
302%define X86_PAGE_4M_BASE_MASK_32 0xffc00000
303%define X86_PTE_BIT_P 0
304%define X86_PTE_BIT_RW 1
305%define X86_PTE_BIT_US 2
306%define X86_PTE_BIT_PWT 3
307%define X86_PTE_BIT_PCD 4
308%define X86_PTE_BIT_A 5
309%define X86_PTE_BIT_D 6
310%define X86_PTE_BIT_PAT 7
311%define X86_PTE_BIT_G 8
312%define X86_PTE_P RT_BIT(0)
313%define X86_PTE_RW RT_BIT(1)
314%define X86_PTE_US RT_BIT(2)
315%define X86_PTE_PWT RT_BIT(3)
316%define X86_PTE_PCD RT_BIT(4)
317%define X86_PTE_A RT_BIT(5)
318%define X86_PTE_D RT_BIT(6)
319%define X86_PTE_PAT RT_BIT(7)
320%define X86_PTE_G RT_BIT(8)
321%define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
322%define X86_PTE_PG_MASK ( 0xfffff000 )
323%define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
324%define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
325%define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
326%define X86_PTE_PAE_NX RT_BIT_64(63)
327%define X86_PT_SHIFT 12
328%define X86_PT_MASK 0x3ff
329%define X86_PT_PAE_SHIFT 12
330%define X86_PT_PAE_MASK 0x1ff
331%define X86_PDE_P RT_BIT(0)
332%define X86_PDE_RW RT_BIT(1)
333%define X86_PDE_US RT_BIT(2)
334%define X86_PDE_PWT RT_BIT(3)
335%define X86_PDE_PCD RT_BIT(4)
336%define X86_PDE_A RT_BIT(5)
337%define X86_PDE_PS RT_BIT(7)
338%define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
339%define X86_PDE_PG_MASK ( 0xfffff000 )
340%define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
341%define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
342%define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
343%define X86_PDE_PAE_NX RT_BIT_64(63)
344%define X86_PDE4M_P RT_BIT(0)
345%define X86_PDE4M_RW RT_BIT(1)
346%define X86_PDE4M_US RT_BIT(2)
347%define X86_PDE4M_PWT RT_BIT(3)
348%define X86_PDE4M_PCD RT_BIT(4)
349%define X86_PDE4M_A RT_BIT(5)
350%define X86_PDE4M_D RT_BIT(6)
351%define X86_PDE4M_PS RT_BIT(7)
352%define X86_PDE4M_G RT_BIT(8)
353%define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
354%define X86_PDE4M_PAT RT_BIT(12)
355%define X86_PDE4M_PAT_SHIFT (12 - 7)
356%define X86_PDE4M_PG_MASK ( 0xffc00000 )
357%define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
358%define X86_PDE4M_PG_HIGH_SHIFT 19
359%define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
360%define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
361%define X86_PD_SHIFT 22
362%define X86_PD_MASK 0x3ff
363%define X86_PD_PAE_SHIFT 21
364%define X86_PD_PAE_MASK 0x1ff
365%define X86_PDPE_P RT_BIT(0)
366%define X86_PDPE_RW RT_BIT(1)
367%define X86_PDPE_US RT_BIT(2)
368%define X86_PDPE_PWT RT_BIT(3)
369%define X86_PDPE_PCD RT_BIT(4)
370%define X86_PDPE_A RT_BIT(5)
371%define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
372%define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
373%define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
374%define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
375%define X86_PDPE_NX RT_BIT_64(63)
376%define X86_PDPT_SHIFT 30
377%define X86_PDPT_MASK_PAE 0x3
378%define X86_PDPT_MASK_AMD64 0x1ff
379%define X86_PML4E_P RT_BIT(0)
380%define X86_PML4E_RW RT_BIT(1)
381%define X86_PML4E_US RT_BIT(2)
382%define X86_PML4E_PWT RT_BIT(3)
383%define X86_PML4E_PCD RT_BIT(4)
384%define X86_PML4E_A RT_BIT(5)
385%define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
386%define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
387%define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
388%define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
389%define X86_PML4E_NX RT_BIT_64(63)
390%define X86_PML4_SHIFT 39
391%define X86_PML4_MASK 0x1ff
392%define X86_SEL_TYPE_CODE 8
393%define X86_SEL_TYPE_MEMORY RT_BIT(4)
394%define X86_SEL_TYPE_ACCESSED 1
395%define X86_SEL_TYPE_DOWN 4
396%define X86_SEL_TYPE_CONF 4
397%define X86_SEL_TYPE_WRITE 2
398%define X86_SEL_TYPE_READ 2
399%define X86_SEL_TYPE_RO 0
400%define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
401%define X86_SEL_TYPE_RW 2
402%define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
403%define X86_SEL_TYPE_RO_DOWN 4
404%define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
405%define X86_SEL_TYPE_RW_DOWN 6
406%define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
407%define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
408%define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
409%define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
410%define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
411%define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
412%define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
413%define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
414%define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
415%define X86_SEL_TYPE_SYS_UNDEFINED 0
416%define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
417%define X86_SEL_TYPE_SYS_LDT 2
418%define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
419%define X86_SEL_TYPE_SYS_286_CALL_GATE 4
420%define X86_SEL_TYPE_SYS_TASK_GATE 5
421%define X86_SEL_TYPE_SYS_286_INT_GATE 6
422%define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
423%define X86_SEL_TYPE_SYS_UNDEFINED2 8
424%define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
425%define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
426%define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
427%define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
428%define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
429%define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
430%define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
431%define AMD64_SEL_TYPE_SYS_LDT 2
432%define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
433%define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
434%define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
435%define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
436%define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
437%define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
438%define X86_DESC_S RT_BIT(12)
439%define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
440%define X86_DESC_P RT_BIT(15)
441%define X86_DESC_AVL RT_BIT(20)
442%define X86_DESC_DB RT_BIT(22)
443%define X86_DESC_G RT_BIT(23)
444%define X86_SEL_SHIFT 3
445%define AMD64_SEL_SHIFT 4
446%define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
447%define X86_SEL_SHIFT_HC X86_SEL_SHIFT
448%define X86_SEL_MASK 0xfff8
449%define X86_SEL_LDT 0x0004
450%define X86_SEL_RPL 0x0003
451%define X86_TRAP_ERR_EXTERNAL 1
452%define X86_TRAP_ERR_IDT 2
453%define X86_TRAP_ERR_TI 4
454%define X86_TRAP_ERR_SEL_MASK 0xfff8
455%define X86_TRAP_ERR_SEL_SHIFT 3
456%define X86_TRAP_PF_P RT_BIT(0)
457%define X86_TRAP_PF_RW RT_BIT(1)
458%define X86_TRAP_PF_US RT_BIT(2)
459%define X86_TRAP_PF_RSVD RT_BIT(3)
460%define X86_TRAP_PF_ID RT_BIT(4)
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette