VirtualBox

source: vbox/trunk/include/VBox/x86.mac@ 1883

Last change on this file since 1883 was 1, checked in by vboxsync, 55 years ago

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1%define X86_EFL_CF BIT(0)
2%define X86_EFL_PF BIT(2)
3%define X86_EFL_AF BIT(4)
4%define X86_EFL_ZF BIT(6)
5%define X86_EFL_SF BIT(7)
6%define X86_EFL_TF BIT(8)
7%define X86_EFL_IF BIT(9)
8%define X86_EFL_DF BIT(10)
9%define X86_EFL_OF BIT(11)
10%define X86_EFL_IOPL (BIT(12) | BIT(13))
11%define X86_EFL_NT BIT(14)
12%define X86_EFL_RF BIT(16)
13%define X86_EFL_VM BIT(17)
14%define X86_EFL_AC BIT(18)
15%define X86_EFL_VIF BIT(19)
16%define X86_EFL_VIP BIT(20)
17%define X86_EFL_ID BIT(21)
18%define X86_EFL_IOPL_SHIFT 12
19%define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
20%define X86_CPUID_FEATURE_ECX_SSE3 BIT(0)
21%define X86_CPUID_FEATURE_ECX_MONITOR BIT(3)
22%define X86_CPUID_FEATURE_ECX_CPLDS BIT(4)
23%define X86_CPUID_FEATURE_ECX_VMX BIT(5)
24%define X86_CPUID_FEATURE_ECX_EST BIT(7)
25%define X86_CPUID_FEATURE_ECX_TM2 BIT(8)
26%define X86_CPUID_FEATURE_ECX_CNTXID BIT(10)
27%define X86_CPUID_FEATURE_ECX_CX16 BIT(13)
28%define X86_CPUID_FEATURE_EDX_FPU BIT(0)
29%define X86_CPUID_FEATURE_EDX_VME BIT(1)
30%define X86_CPUID_FEATURE_EDX_DE BIT(2)
31%define X86_CPUID_FEATURE_EDX_PSE BIT(3)
32%define X86_CPUID_FEATURE_EDX_TSC BIT(4)
33%define X86_CPUID_FEATURE_EDX_MSR BIT(5)
34%define X86_CPUID_FEATURE_EDX_PAE BIT(6)
35%define X86_CPUID_FEATURE_EDX_MCE BIT(7)
36%define X86_CPUID_FEATURE_EDX_CX8 BIT(8)
37%define X86_CPUID_FEATURE_EDX_APIC BIT(9)
38%define X86_CPUID_FEATURE_EDX_SEP BIT(11)
39%define X86_CPUID_FEATURE_EDX_MTRR BIT(12)
40%define X86_CPUID_FEATURE_EDX_PGE BIT(13)
41%define X86_CPUID_FEATURE_EDX_MCA BIT(14)
42%define X86_CPUID_FEATURE_EDX_CMOV BIT(15)
43%define X86_CPUID_FEATURE_EDX_PAT BIT(16)
44%define X86_CPUID_FEATURE_EDX_PSE36 BIT(17)
45%define X86_CPUID_FEATURE_EDX_PSN BIT(18)
46%define X86_CPUID_FEATURE_EDX_CLFSH BIT(19)
47%define X86_CPUID_FEATURE_EDX_DS BIT(21)
48%define X86_CPUID_FEATURE_EDX_ACPI BIT(22)
49%define X86_CPUID_FEATURE_EDX_MMX BIT(23)
50%define X86_CPUID_FEATURE_EDX_FXSR BIT(24)
51%define X86_CPUID_FEATURE_EDX_SSE BIT(25)
52%define X86_CPUID_FEATURE_EDX_SSE2 BIT(26)
53%define X86_CPUID_FEATURE_EDX_SS BIT(27)
54%define X86_CPUID_FEATURE_EDX_HTT BIT(28)
55%define X86_CPUID_FEATURE_EDX_TM BIT(29)
56%define X86_CPUID_FEATURE_EDX_PBE BIT(31)
57%define X86_CPUID_AMD_FEATURE_EDX_FPU BIT(0)
58%define X86_CPUID_AMD_FEATURE_EDX_VME BIT(1)
59%define X86_CPUID_AMD_FEATURE_EDX_DE BIT(2)
60%define X86_CPUID_AMD_FEATURE_EDX_PSE BIT(3)
61%define X86_CPUID_AMD_FEATURE_EDX_TSC BIT(4)
62%define X86_CPUID_AMD_FEATURE_EDX_MSR BIT(5)
63%define X86_CPUID_AMD_FEATURE_EDX_PAE BIT(6)
64%define X86_CPUID_AMD_FEATURE_EDX_MCE BIT(7)
65%define X86_CPUID_AMD_FEATURE_EDX_CX8 BIT(8)
66%define X86_CPUID_AMD_FEATURE_EDX_APIC BIT(9)
67%define X86_CPUID_AMD_FEATURE_EDX_SEP BIT(11)
68%define X86_CPUID_AMD_FEATURE_EDX_MTRR BIT(12)
69%define X86_CPUID_AMD_FEATURE_EDX_PGE BIT(13)
70%define X86_CPUID_AMD_FEATURE_EDX_MCA BIT(14)
71%define X86_CPUID_AMD_FEATURE_EDX_CMOV BIT(15)
72%define X86_CPUID_AMD_FEATURE_EDX_PAT BIT(16)
73%define X86_CPUID_AMD_FEATURE_EDX_PSE36 BIT(17)
74%define X86_CPUID_AMD_FEATURE_EDX_NX BIT(20)
75%define X86_CPUID_AMD_FEATURE_EDX_AXMMX BIT(22)
76%define X86_CPUID_AMD_FEATURE_EDX_MMX BIT(23)
77%define X86_CPUID_AMD_FEATURE_EDX_FXSR BIT(24)
78%define X86_CPUID_AMD_FEATURE_EDX_FFXSR BIT(25)
79%define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE BIT(29)
80%define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX BIT(30)
81%define X86_CPUID_AMD_FEATURE_EDX_3DNOW BIT(31)
82%define X86_CPUID_AMD_FEATURE_ECX_CMPL BIT(1)
83%define X86_CPUID_AMD_FEATURE_ECX_SVM BIT(2)
84%define X86_CPUID_AMD_FEATURE_ECX_CR8L BIT(4)
85%define X86_CR0_PE BIT(0)
86%define X86_CR0_PROTECTION_ENABLE BIT(0)
87%define X86_CR0_MP BIT(1)
88%define X86_CR0_MONITOR_COPROCESSOR BIT(1)
89%define X86_CR0_EM BIT(2)
90%define X86_CR0_EMULATE_FPU BIT(2)
91%define X86_CR0_TS BIT(3)
92%define X86_CR0_TASK_SWITCH BIT(3)
93%define X86_CR0_ET BIT(4)
94%define X86_CR0_EXTENSION_TYPE BIT(4)
95%define X86_CR0_NE BIT(5)
96%define X86_CR0_NUMERIC_ERROR BIT(5)
97%define X86_CR0_WP BIT(16)
98%define X86_CR0_WRITE_PROTECT BIT(16)
99%define X86_CR0_AM BIT(18)
100%define X86_CR0_ALIGMENT_MASK BIT(18)
101%define X86_CR0_NW BIT(29)
102%define X86_CR0_NOT_WRITE_THROUGH BIT(29)
103%define X86_CR0_CD BIT(30)
104%define X86_CR0_CACHE_DISABLE BIT(30)
105%define X86_CR0_PG BIT(31)
106%define X86_CR0_PAGING BIT(31)
107%define X86_CR3_PWT BIT(3)
108%define X86_CR3_PCD BIT(4)
109%define X86_CR3_PAGE_MASK (0xfffff000)
110%define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
111%define X86_CR4_VME BIT(0)
112%define X86_CR4_PVI BIT(1)
113%define X86_CR4_TSD BIT(2)
114%define X86_CR4_DE BIT(3)
115%define X86_CR4_PSE BIT(4)
116%define X86_CR4_PAE BIT(5)
117%define X86_CR4_MCE BIT(6)
118%define X86_CR4_PGE BIT(7)
119%define X86_CR4_PCE BIT(8)
120%define X86_CR4_OSFSXR BIT(9)
121%define X86_CR4_OSXMMEEXCPT BIT(10)
122%define X86_CR4_VMXE BIT(13)
123%define X86_DR6_B0 BIT(0)
124%define X86_DR6_B1 BIT(1)
125%define X86_DR6_B2 BIT(2)
126%define X86_DR6_B3 BIT(3)
127%define X86_DR6_BD BIT(13)
128%define X86_DR6_BS BIT(14)
129%define X86_DR6_BT BIT(15)
130%define X86_DR7_L0 BIT(0)
131%define X86_DR7_G0 BIT(1)
132%define X86_DR7_L1 BIT(2)
133%define X86_DR7_G1 BIT(3)
134%define X86_DR7_L2 BIT(4)
135%define X86_DR7_G2 BIT(5)
136%define X86_DR7_L3 BIT(6)
137%define X86_DR7_G3 BIT(7)
138%define X86_DR7_LE BIT(8)
139%define X86_DR7_GE BIT(9)
140%define X86_DR7_GD BIT(13)
141%define X86_DR7_RW0_MASK (3 << 16)
142%define X86_DR7_LEN0_MASK (3 << 18)
143%define X86_DR7_RW1_MASK (3 << 20)
144%define X86_DR7_LEN1_MASK (3 << 22)
145%define X86_DR7_RW2_MASK (3 << 24)
146%define X86_DR7_LEN2_MASK (3 << 26)
147%define X86_DR7_RW3_MASK (3 << 28)
148%define X86_DR7_LEN3_MASK (3 << 30)
149%define X86_DR7_MB1_MASK (BIT(10))
150%define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
151%define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
152%define X86_DR7_RW_EO 0
153%define X86_DR7_RW_WO 1
154%define X86_DR7_RW_IO 2
155%define X86_DR7_RW_RW 3
156%define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
157%define X86_DR7_LEN_BYTE 0
158%define X86_DR7_LEN_WORD 1
159%define X86_DR7_LEN_QWORD 2 /**< AMD64 long mode only. */
160%define X86_DR7_LEN_DWORD 3
161%define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
162%define X86_DR7_ENABLED_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(7))
163%define MSR_IA32_FEATURE_CONTROL 0x3A
164%define MSR_IA32_FEATURE_CONTROL_LOCK BIT(0)
165%define MSR_IA32_FEATURE_CONTROL_VMXON BIT(2)
166%define MSR_IA32_SYSENTER_CS 0x174
167%define MSR_IA32_SYSENTER_ESP 0x175
168%define MSR_IA32_SYSENTER_EIP 0x176
169%define MSR_IA32_VMX_BASIC_INFO 0x480
170%define MSR_IA32_VMX_PINBASED_CTLS 0x481
171%define MSR_IA32_VMX_PROCBASED_CTLS 0x482
172%define MSR_IA32_VMX_EXIT_CTLS 0x483
173%define MSR_IA32_VMX_ENTRY_CTLS 0x484
174%define MSR_IA32_VMX_MISC 0x485
175%define MSR_IA32_VMX_CR0_FIXED0 0x486
176%define MSR_IA32_VMX_CR0_FIXED1 0x487
177%define MSR_IA32_VMX_CR4_FIXED0 0x488
178%define MSR_IA32_VMX_CR4_FIXED1 0x489
179%define MSR_IA32_VMX_VMCS_ENUM 0x48A
180%define MSR_K6_EFER 0xc0000080
181%define MSR_K6_EFER_SCE BIT(0)
182%define MSR_K6_EFER_LME BIT(8)
183%define MSR_K6_EFER_LMA BIT(10)
184%define MSR_K6_EFER_NXE BIT(11)
185%define MSR_K6_EFER_SVME BIT(12)
186%define MSR_K6_EFER_LMSLE BIT(13)
187%define MSR_K6_EFER_FFXSR BIT(14)
188%define MSR_K6_STAR 0xc0000081
189%define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
190%define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
191%define MSR_K6_STAR_SEL_MASK 0xffff
192%define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
193%define MSR_K6_WHCR 0xc0000082
194%define MSR_K6_UWCCR 0xc0000085
195%define MSR_K6_PSOR 0xc0000087
196%define MSR_K6_PFIR 0xc0000088
197%define MSR_K7_EVNTSEL0 0xc0010000
198%define MSR_K7_EVNTSEL1 0xc0010001
199%define MSR_K7_EVNTSEL2 0xc0010002
200%define MSR_K7_EVNTSEL3 0xc0010003
201%define MSR_K7_PERFCTR0 0xc0010004
202%define MSR_K7_PERFCTR1 0xc0010005
203%define MSR_K7_PERFCTR2 0xc0010006
204%define MSR_K7_PERFCTR3 0xc0010007
205%define MSR_K8_LSTAR 0xc0000082
206%define MSR_K8_CSTAR 0xc0000083
207%define MSR_K8_SF_MASK 0xc0000084
208%define MSR_K8_FS_BASE 0xc0000100
209%define MSR_K8_GS_BASE 0xc0000101
210%define MSR_K8_KERNEL_GS_BASE 0xc0000102
211%define MSR_K8_TSC_AUX 0xc0000103
212%define MSR_K8_SYSCFG 0xc0010010
213%define MSR_K8_HWCR 0xc0010015
214%define MSR_K8_IORRBASE0 0xc0010016
215%define MSR_K8_IORRMASK0 0xc0010017
216%define MSR_K8_IORRBASE1 0xc0010018
217%define MSR_K8_IORRMASK1 0xc0010019
218%define MSR_K8_TOP_MEM1 0xc001001a
219%define MSR_K8_TOP_MEM2 0xc001001d
220%define MSR_K8_VM_CR 0xc0010114
221%define MSR_K8_IGNNE 0xc0010115
222%define MSR_K8_SMM_CTL 0xc0010116
223%define MSR_K8_VM_HSAVE_PA 0xc0010117
224%define X86_PG_ENTRIES 1024
225%define X86_PG_PAE_ENTRIES 512
226%define X86_PAGE_4K_SIZE _4K
227%define X86_PAGE_4K_SHIFT 12
228%define X86_PAGE_4K_OFFSET_MASK 0xfff
229%define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
230%define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
231%define X86_PAGE_2M_SIZE _2M
232%define X86_PAGE_2M_SHIFT 21
233%define X86_PAGE_2M_OFFSET_MASK 0x001fffff
234%define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
235%define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
236%define X86_PAGE_4M_SIZE _4M
237%define X86_PAGE_4M_SHIFT 22
238%define X86_PAGE_4M_OFFSET_MASK 0x003fffff
239%define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
240%define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
241%define X86_PTE_P BIT(0)
242%define X86_PTE_RW BIT(1)
243%define X86_PTE_US BIT(2)
244%define X86_PTE_PWT BIT(3)
245%define X86_PTE_PCD BIT(4)
246%define X86_PTE_A BIT(5)
247%define X86_PTE_D BIT(6)
248%define X86_PTE_PAT BIT(7)
249%define X86_PTE_G BIT(8)
250%define X86_PTE_AVL_MASK (BIT(9) | BIT(10) | BIT(11))
251%define X86_PTE_PG_MASK ( 0xfffff000 )
252%define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
253%define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
254%define X86_PTE_PAE_NX BIT64(63)
255%define X86_PT_SHIFT 12
256%define X86_PT_MASK 0x3ff
257%define X86_PT_PAE_SHIFT 12
258%define X86_PT_PAE_MASK 0x1ff
259%define X86_PDE_P BIT(0)
260%define X86_PDE_RW BIT(1)
261%define X86_PDE_US BIT(2)
262%define X86_PDE_PWT BIT(3)
263%define X86_PDE_PCD BIT(4)
264%define X86_PDE_A BIT(5)
265%define X86_PDE_PS BIT(7)
266%define X86_PDE_AVL_MASK (BIT(9) | BIT(10) | BIT(11))
267%define X86_PDE_PG_MASK ( 0xfffff000 )
268%define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
269%define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
270%define X86_PDE_PAE_NX BIT64(63)
271%define X86_PDE4M_P BIT(0)
272%define X86_PDE4M_RW BIT(1)
273%define X86_PDE4M_US BIT(2)
274%define X86_PDE4M_PWT BIT(3)
275%define X86_PDE4M_PCD BIT(4)
276%define X86_PDE4M_A BIT(5)
277%define X86_PDE4M_D BIT(6)
278%define X86_PDE4M_PS BIT(7)
279%define X86_PDE4M_G BIT(8)
280%define X86_PDE4M_AVL (BIT(9) | BIT(10) | BIT(11))
281%define X86_PDE4M_PAT BIT(12)
282%define X86_PDE4M_PAT_SHIFT (12 - 7)
283%define X86_PDE4M_PG_MASK ( 0xffc00000 )
284%define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
285%define X86_PDE4M_PG_HIGH_SHIFT 19
286%define X86_PDE4M_PAE_PG_MASK ( 0x000fffffffc00000ULL )
287%define X86_PDE4M_PAE_NX BIT64(63)
288%define X86_PD_SHIFT 22
289%define X86_PD_MASK 0x3ff
290%define X86_PD_PAE_SHIFT 21
291%define X86_PD_PAE_MASK 0x1ff
292%define X86_PDPE_P BIT(0)
293%define X86_PDPE_RW BIT(1)
294%define X86_PDPE_US BIT(2)
295%define X86_PDPE_PWT BIT(3)
296%define X86_PDPE_PCD BIT(4)
297%define X86_PDPE_A BIT(5)
298%define X86_PDPE_AVL_MASK (BIT(9) | BIT(10) | BIT(11))
299%define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
300%define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
301%define X86_PDPE_NX BIT64(63)
302%define X86_PDPTR_SHIFT 30
303%define X86_PDPTR_MASK_32 0x3
304%define X86_PDPTR_MASK 0x1ff
305%define X86_PML4E_P BIT(0)
306%define X86_PML4E_RW BIT(1)
307%define X86_PML4E_US BIT(2)
308%define X86_PML4E_PWT BIT(3)
309%define X86_PML4E_PCD BIT(4)
310%define X86_PML4E_A BIT(5)
311%define X86_PML4E_AVL_MASK (BIT(9) | BIT(10) | BIT(11))
312%define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
313%define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
314%define X86_PML4E_NX BIT64(63)
315%define X86_PML4_SHIFT 39
316%define X86_PML4_MASK 0x1ff
317%define X86_SEL_TYPE_CODE 8
318%define X86_SEL_TYPE_ACCESSED 1
319%define X86_SEL_TYPE_DOWN 4
320%define X86_SEL_TYPE_CONF 4
321%define X86_SEL_TYPE_WRITE 2
322%define X86_SEL_TYPE_READ 2
323%define X86_SEL_TYPE_RO 0
324%define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
325%define X86_SEL_TYPE_RW 2
326%define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
327%define X86_SEL_TYPE_RO_DOWN 4
328%define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
329%define X86_SEL_TYPE_RW_DOWN 6
330%define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
331%define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
332%define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
333%define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
334%define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
335%define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
336%define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
337%define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
338%define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
339%define X86_SEL_TYPE_SYS_UNDEFINED 0
340%define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
341%define X86_SEL_TYPE_SYS_LDT 2
342%define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
343%define X86_SEL_TYPE_SYS_286_CALL_GATE 4
344%define X86_SEL_TYPE_SYS_TASK_GATE 5
345%define X86_SEL_TYPE_SYS_286_INT_GATE 6
346%define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
347%define X86_SEL_TYPE_SYS_UNDEFINED2 8
348%define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
349%define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
350%define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
351%define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
352%define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
353%define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
354%define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
355%define X86_DESC_TYPE_MASK (BIT(8) | BIT(9) | BIT(10) | BIT(11))
356%define X86_DESC_S BIT(12)
357%define X86_DESC_DPL (BIT(13) | BIT(14))
358%define X86_DESC_P BIT(15)
359%define X86_DESC_AVL BIT(20)
360%define X86_DESC_DB BIT(22)
361%define X86_DESC_G BIT(23)
362%define X86_SEL_SHIFT 3
363%define X86_SEL_MASK 0xfff8
364%define X86_SEL_LDT 0x0004
365%define X86_SEL_RPL 0x0003
366%define X86_TRAP_ERR_EXTERNAL 1
367%define X86_TRAP_ERR_IDT 2
368%define X86_TRAP_ERR_TI 4
369%define X86_TRAP_ERR_SEL_MASK 0xfff8
370%define X86_TRAP_ERR_SEL_SHIFT 3
371%define X86_TRAP_PF_P BIT(0)
372%define X86_TRAP_PF_RW BIT(1)
373%define X86_TRAP_PF_US BIT(2)
374%define X86_TRAP_PF_RSVD BIT(3)
375%define X86_TRAP_PF_ID BIT(4)
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