VirtualBox

source: vbox/trunk/include/VBox/x86.mac@ 10647

Last change on this file since 10647 was 10647, checked in by vboxsync, 16 years ago

Manual saving of XMM registers.
Use new FPU/MMX/XMM state saving for VT-x and AMD-V.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 23.1 KB
Line 
1%define ___VBox_x86_h
2%define X86_EFL_CF RT_BIT(0)
3%define X86_EFL_PF RT_BIT(2)
4%define X86_EFL_AF RT_BIT(4)
5%define X86_EFL_ZF RT_BIT(6)
6%define X86_EFL_SF RT_BIT(7)
7%define X86_EFL_TF RT_BIT(8)
8%define X86_EFL_IF RT_BIT(9)
9%define X86_EFL_DF RT_BIT(10)
10%define X86_EFL_OF RT_BIT(11)
11%define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
12%define X86_EFL_NT RT_BIT(14)
13%define X86_EFL_RF RT_BIT(16)
14%define X86_EFL_VM RT_BIT(17)
15%define X86_EFL_AC RT_BIT(18)
16%define X86_EFL_VIF RT_BIT(19)
17%define X86_EFL_VIP RT_BIT(20)
18%define X86_EFL_ID RT_BIT(21)
19%define X86_EFL_IOPL_SHIFT 12
20%define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
21%define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
22%define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
23%define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
24%define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
25%define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
26%define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
27%define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
28%define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
29%define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
30%define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
31%define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
32%define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
33%define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
34%define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
35%define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
36%define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
37%define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
38%define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
39%define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
40%define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
41%define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
42%define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
43%define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
44%define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
45%define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
46%define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
47%define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
48%define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
49%define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
50%define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
51%define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
52%define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
53%define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
54%define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
55%define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
56%define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
57%define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
58%define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
59%define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
60%define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
61%define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
62%define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
63%define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
64%define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
65%define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
66%define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
67%define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
68%define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
69%define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
70%define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
71%define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
72%define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
73%define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
74%define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
75%define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
76%define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
77%define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
78%define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
79%define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
80%define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
81%define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
82%define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
83%define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
84%define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
85%define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
86%define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
87%define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
88%define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
89%define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
90%define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
91%define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
92%define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
93%define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
94%define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
95%define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
96%define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
97%define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
98%define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
99%define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
100%define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
101%define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
102%define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
103%define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
104%define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
105%define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
106%define X86_CR0_PE RT_BIT(0)
107%define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
108%define X86_CR0_MP RT_BIT(1)
109%define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
110%define X86_CR0_EM RT_BIT(2)
111%define X86_CR0_EMULATE_FPU RT_BIT(2)
112%define X86_CR0_TS RT_BIT(3)
113%define X86_CR0_TASK_SWITCH RT_BIT(3)
114%define X86_CR0_ET RT_BIT(4)
115%define X86_CR0_EXTENSION_TYPE RT_BIT(4)
116%define X86_CR0_NE RT_BIT(5)
117%define X86_CR0_NUMERIC_ERROR RT_BIT(5)
118%define X86_CR0_WP RT_BIT(16)
119%define X86_CR0_WRITE_PROTECT RT_BIT(16)
120%define X86_CR0_AM RT_BIT(18)
121%define X86_CR0_ALIGMENT_MASK RT_BIT(18)
122%define X86_CR0_NW RT_BIT(29)
123%define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
124%define X86_CR0_CD RT_BIT(30)
125%define X86_CR0_CACHE_DISABLE RT_BIT(30)
126%define X86_CR0_PG RT_BIT(31)
127%define X86_CR0_PAGING RT_BIT(31)
128%define X86_CR3_PWT RT_BIT(3)
129%define X86_CR3_PCD RT_BIT(4)
130%define X86_CR3_PAGE_MASK (0xfffff000)
131%define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
132%define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
133%define X86_CR4_VME RT_BIT(0)
134%define X86_CR4_PVI RT_BIT(1)
135%define X86_CR4_TSD RT_BIT(2)
136%define X86_CR4_DE RT_BIT(3)
137%define X86_CR4_PSE RT_BIT(4)
138%define X86_CR4_PAE RT_BIT(5)
139%define X86_CR4_MCE RT_BIT(6)
140%define X86_CR4_PGE RT_BIT(7)
141%define X86_CR4_PCE RT_BIT(8)
142%define X86_CR4_OSFSXR RT_BIT(9)
143%define X86_CR4_OSXMMEEXCPT RT_BIT(10)
144%define X86_CR4_VMXE RT_BIT(13)
145%define X86_DR6_B0 RT_BIT(0)
146%define X86_DR6_B1 RT_BIT(1)
147%define X86_DR6_B2 RT_BIT(2)
148%define X86_DR6_B3 RT_BIT(3)
149%define X86_DR6_BD RT_BIT(13)
150%define X86_DR6_BS RT_BIT(14)
151%define X86_DR6_BT RT_BIT(15)
152%define X86_DR7_L0 RT_BIT(0)
153%define X86_DR7_G0 RT_BIT(1)
154%define X86_DR7_L1 RT_BIT(2)
155%define X86_DR7_G1 RT_BIT(3)
156%define X86_DR7_L2 RT_BIT(4)
157%define X86_DR7_G2 RT_BIT(5)
158%define X86_DR7_L3 RT_BIT(6)
159%define X86_DR7_G3 RT_BIT(7)
160%define X86_DR7_LE RT_BIT(8)
161%define X86_DR7_GE RT_BIT(9)
162%define X86_DR7_GD RT_BIT(13)
163%define X86_DR7_RW0_MASK (3 << 16)
164%define X86_DR7_LEN0_MASK (3 << 18)
165%define X86_DR7_RW1_MASK (3 << 20)
166%define X86_DR7_LEN1_MASK (3 << 22)
167%define X86_DR7_RW2_MASK (3 << 24)
168%define X86_DR7_LEN2_MASK (3 << 26)
169%define X86_DR7_RW3_MASK (3 << 28)
170%define X86_DR7_LEN3_MASK (3 << 30)
171%define X86_DR7_MB1_MASK (RT_BIT(10))
172%define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
173%define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
174%define X86_DR7_RW_EO 0
175%define X86_DR7_RW_WO 1
176%define X86_DR7_RW_IO 2
177%define X86_DR7_RW_RW 3
178%define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
179%define X86_DR7_LEN_BYTE 0
180%define X86_DR7_LEN_WORD 1
181%define X86_DR7_LEN_QWORD 2 ;/**< AMD64 long mode only. */
182%define X86_DR7_LEN_DWORD 3
183%define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
184%define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(6) | RT_BIT(7))
185%define MSR_IA32_TSC 0x10
186%define MSR_IA32_APICBASE 0x1b
187%define MSR_IA32_FEATURE_CONTROL 0x3A
188%define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
189%define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
190%define MSR_IA32_MTRR_CAP 0xFE
191%define MSR_IA32_SYSENTER_CS 0x174
192%define MSR_IA32_SYSENTER_ESP 0x175
193%define MSR_IA32_SYSENTER_EIP 0x176
194%define MSR_IA32_MCP_CAP 0x179
195%define MSR_IA32_MCP_STATUS 0x17A
196%define MSR_IA32_MCP_CTRL 0x17B
197%define MSR_IA32_CR_PAT 0x277
198%define MSR_IA32_MTRR_DEF_TYPE 0x2FF
199%define MSR_IA32_VMX_BASIC_INFO 0x480
200%define MSR_IA32_VMX_PINBASED_CTLS 0x481
201%define MSR_IA32_VMX_PROCBASED_CTLS 0x482
202%define MSR_IA32_VMX_EXIT_CTLS 0x483
203%define MSR_IA32_VMX_ENTRY_CTLS 0x484
204%define MSR_IA32_VMX_MISC 0x485
205%define MSR_IA32_VMX_CR0_FIXED0 0x486
206%define MSR_IA32_VMX_CR0_FIXED1 0x487
207%define MSR_IA32_VMX_CR4_FIXED0 0x488
208%define MSR_IA32_VMX_CR4_FIXED1 0x489
209%define MSR_IA32_VMX_VMCS_ENUM 0x48A
210%define MSR_K6_EFER 0xc0000080
211%define MSR_K6_EFER_SCE RT_BIT(0)
212%define MSR_K6_EFER_LME RT_BIT(8)
213%define MSR_K6_EFER_LMA RT_BIT(10)
214%define MSR_K6_EFER_NXE RT_BIT(11)
215%define MSR_K6_EFER_SVME RT_BIT(12)
216%define MSR_K6_EFER_LMSLE RT_BIT(13)
217%define MSR_K6_EFER_FFXSR RT_BIT(14)
218%define MSR_K6_STAR 0xc0000081
219%define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
220%define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
221%define MSR_K6_STAR_SEL_MASK 0xffff
222%define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
223%define MSR_K6_WHCR 0xc0000082
224%define MSR_K6_UWCCR 0xc0000085
225%define MSR_K6_PSOR 0xc0000087
226%define MSR_K6_PFIR 0xc0000088
227%define MSR_K7_EVNTSEL0 0xc0010000
228%define MSR_K7_EVNTSEL1 0xc0010001
229%define MSR_K7_EVNTSEL2 0xc0010002
230%define MSR_K7_EVNTSEL3 0xc0010003
231%define MSR_K7_PERFCTR0 0xc0010004
232%define MSR_K7_PERFCTR1 0xc0010005
233%define MSR_K7_PERFCTR2 0xc0010006
234%define MSR_K7_PERFCTR3 0xc0010007
235%define MSR_K8_LSTAR 0xc0000082
236%define MSR_K8_CSTAR 0xc0000083
237%define MSR_K8_SF_MASK 0xc0000084
238%define MSR_K8_FS_BASE 0xc0000100
239%define MSR_K8_GS_BASE 0xc0000101
240%define MSR_K8_KERNEL_GS_BASE 0xc0000102
241%define MSR_K8_TSC_AUX 0xc0000103
242%define MSR_K8_SYSCFG 0xc0010010
243%define MSR_K8_HWCR 0xc0010015
244%define MSR_K8_IORRBASE0 0xc0010016
245%define MSR_K8_IORRMASK0 0xc0010017
246%define MSR_K8_IORRBASE1 0xc0010018
247%define MSR_K8_IORRMASK1 0xc0010019
248%define MSR_K8_TOP_MEM1 0xc001001a
249%define MSR_K8_TOP_MEM2 0xc001001d
250%define MSR_K8_VM_CR 0xc0010114
251%define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
252%define MSR_K8_IGNNE 0xc0010115
253%define MSR_K8_SMM_CTL 0xc0010116
254%define MSR_K8_VM_HSAVE_PA 0xc0010117
255%define X86_PG_ENTRIES 1024
256%define X86_PG_PAE_ENTRIES 512
257%define X86_PG_PAE_PDPE_ENTRIES 4
258%define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
259%define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
260%define X86_PAGE_4K_SIZE _4K
261%define X86_PAGE_4K_SHIFT 12
262%define X86_PAGE_4K_OFFSET_MASK 0xfff
263%define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
264%define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
265%define X86_PAGE_2M_SIZE _2M
266%define X86_PAGE_2M_SHIFT 21
267%define X86_PAGE_2M_OFFSET_MASK 0x001fffff
268%define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
269%define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
270%define X86_PAGE_4M_SIZE _4M
271%define X86_PAGE_4M_SHIFT 22
272%define X86_PAGE_4M_OFFSET_MASK 0x003fffff
273%define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
274%define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
275%define X86_PTE_P RT_BIT(0)
276%define X86_PTE_RW RT_BIT(1)
277%define X86_PTE_US RT_BIT(2)
278%define X86_PTE_PWT RT_BIT(3)
279%define X86_PTE_PCD RT_BIT(4)
280%define X86_PTE_A RT_BIT(5)
281%define X86_PTE_D RT_BIT(6)
282%define X86_PTE_PAT RT_BIT(7)
283%define X86_PTE_G RT_BIT(8)
284%define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
285%define X86_PTE_PG_MASK ( 0xfffff000 )
286%define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
287%define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
288%define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
289%define X86_PTE_PAE_NX RT_BIT_64(63)
290%define X86_PT_SHIFT 12
291%define X86_PT_MASK 0x3ff
292%define X86_PT_PAE_SHIFT 12
293%define X86_PT_PAE_MASK 0x1ff
294%define X86_PDE_P RT_BIT(0)
295%define X86_PDE_RW RT_BIT(1)
296%define X86_PDE_US RT_BIT(2)
297%define X86_PDE_PWT RT_BIT(3)
298%define X86_PDE_PCD RT_BIT(4)
299%define X86_PDE_A RT_BIT(5)
300%define X86_PDE_PS RT_BIT(7)
301%define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
302%define X86_PDE_PG_MASK ( 0xfffff000 )
303%define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
304%define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
305%define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
306%define X86_PDE_PAE_NX RT_BIT_64(63)
307%define X86_PDE4M_P RT_BIT(0)
308%define X86_PDE4M_RW RT_BIT(1)
309%define X86_PDE4M_US RT_BIT(2)
310%define X86_PDE4M_PWT RT_BIT(3)
311%define X86_PDE4M_PCD RT_BIT(4)
312%define X86_PDE4M_A RT_BIT(5)
313%define X86_PDE4M_D RT_BIT(6)
314%define X86_PDE4M_PS RT_BIT(7)
315%define X86_PDE4M_G RT_BIT(8)
316%define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
317%define X86_PDE4M_PAT RT_BIT(12)
318%define X86_PDE4M_PAT_SHIFT (12 - 7)
319%define X86_PDE4M_PG_MASK ( 0xffc00000 )
320%define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
321%define X86_PDE4M_PG_HIGH_SHIFT 19
322%define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
323%define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
324%define X86_PD_SHIFT 22
325%define X86_PD_MASK 0x3ff
326%define X86_PD_PAE_SHIFT 21
327%define X86_PD_PAE_MASK 0x1ff
328%define X86_PDPE_P RT_BIT(0)
329%define X86_PDPE_RW RT_BIT(1)
330%define X86_PDPE_US RT_BIT(2)
331%define X86_PDPE_PWT RT_BIT(3)
332%define X86_PDPE_PCD RT_BIT(4)
333%define X86_PDPE_A RT_BIT(5)
334%define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
335%define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
336%define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
337%define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
338%define X86_PDPE_NX RT_BIT_64(63)
339%define X86_PDPT_SHIFT 30
340%define X86_PDPT_MASK_PAE 0x3
341%define X86_PDPT_MASK_AMD64 0x1ff
342%define X86_PML4E_P RT_BIT(0)
343%define X86_PML4E_RW RT_BIT(1)
344%define X86_PML4E_US RT_BIT(2)
345%define X86_PML4E_PWT RT_BIT(3)
346%define X86_PML4E_PCD RT_BIT(4)
347%define X86_PML4E_A RT_BIT(5)
348%define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
349%define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
350%define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
351%define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
352%define X86_PML4E_NX RT_BIT_64(63)
353%define X86_PML4_SHIFT 39
354%define X86_PML4_MASK 0x1ff
355%define X86_SEL_TYPE_CODE 8
356%define X86_SEL_TYPE_MEMORY RT_BIT(4)
357%define X86_SEL_TYPE_ACCESSED 1
358%define X86_SEL_TYPE_DOWN 4
359%define X86_SEL_TYPE_CONF 4
360%define X86_SEL_TYPE_WRITE 2
361%define X86_SEL_TYPE_READ 2
362%define X86_SEL_TYPE_RO 0
363%define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
364%define X86_SEL_TYPE_RW 2
365%define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
366%define X86_SEL_TYPE_RO_DOWN 4
367%define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
368%define X86_SEL_TYPE_RW_DOWN 6
369%define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
370%define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
371%define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
372%define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
373%define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
374%define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
375%define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
376%define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
377%define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
378%define X86_SEL_TYPE_SYS_UNDEFINED 0
379%define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
380%define X86_SEL_TYPE_SYS_LDT 2
381%define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
382%define X86_SEL_TYPE_SYS_286_CALL_GATE 4
383%define X86_SEL_TYPE_SYS_TASK_GATE 5
384%define X86_SEL_TYPE_SYS_286_INT_GATE 6
385%define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
386%define X86_SEL_TYPE_SYS_UNDEFINED2 8
387%define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
388%define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
389%define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
390%define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
391%define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
392%define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
393%define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
394%define AMD64_SEL_TYPE_SYS_LDT 2
395%define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
396%define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
397%define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
398%define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
399%define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
400%define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
401%define X86_DESC_S RT_BIT(12)
402%define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
403%define X86_DESC_P RT_BIT(15)
404%define X86_DESC_AVL RT_BIT(20)
405%define X86_DESC_DB RT_BIT(22)
406%define X86_DESC_G RT_BIT(23)
407%define X86_SEL_SHIFT 3
408%define AMD64_SEL_SHIFT 4
409%define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
410%define X86_SEL_SHIFT_HC X86_SEL_SHIFT
411%define X86_SEL_MASK 0xfff8
412%define X86_SEL_LDT 0x0004
413%define X86_SEL_RPL 0x0003
414%define X86_TRAP_ERR_EXTERNAL 1
415%define X86_TRAP_ERR_IDT 2
416%define X86_TRAP_ERR_TI 4
417%define X86_TRAP_ERR_SEL_MASK 0xfff8
418%define X86_TRAP_ERR_SEL_SHIFT 3
419%define X86_TRAP_PF_P RT_BIT(0)
420%define X86_TRAP_PF_RW RT_BIT(1)
421%define X86_TRAP_PF_US RT_BIT(2)
422%define X86_TRAP_PF_RSVD RT_BIT(3)
423%define X86_TRAP_PF_ID RT_BIT(4)
424
425;;
426; FPU/XMM state
427;;
428struc X86FXSTATE
429 ;/** Control word. */
430 .FCW resw 1
431 ;/** Status word. */
432 .FSW resw 1
433 ;/** Tag word (it's a byte actually). */
434 .FTW resb 1
435 .huh1 resb 1
436 ;/** Opcode. */
437 .FOP resw 1
438 ;/** Instruction pointer. */
439 .FPUIP resd 1
440 ;/** Code selector. */
441 .CS resw 1
442 .Rsvrd1 resw 1
443 ;/* - offset 16 - */
444 ;/** Data pointer. */
445 .FPUDP resd 1
446 ;/** Data segment */
447 .DS resw 1
448 .Rsrvd2 resw 1
449 .MXCSR resd 1
450 .MXCSR_MASK resd 1
451 ;/* - offset 32 - */
452 ; FPU & MMX registers
453 .aRegs resq 8*2
454 ;/* - offset 160 - */
455 ;/* 8 XMM registers in 32 bits mode; 16 in long mode */
456 .aXMM resq 16*2
457 ;/* - offset 416 - */
458 .au32RsrvdRest resd (512 - 416) / 4
459endstruc
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