VirtualBox

source: vbox/trunk/include/VBox/x86.mac@ 10353

Last change on this file since 10353 was 9768, checked in by vboxsync, 17 years ago

Regenerate err.mac and x86.mac. Adjusted the rule for generting these as x86.h now include multiline macros.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 21.6 KB
Line 
1%define ___VBox_x86_h
2%define X86_EFL_CF RT_BIT(0)
3%define X86_EFL_PF RT_BIT(2)
4%define X86_EFL_AF RT_BIT(4)
5%define X86_EFL_ZF RT_BIT(6)
6%define X86_EFL_SF RT_BIT(7)
7%define X86_EFL_TF RT_BIT(8)
8%define X86_EFL_IF RT_BIT(9)
9%define X86_EFL_DF RT_BIT(10)
10%define X86_EFL_OF RT_BIT(11)
11%define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
12%define X86_EFL_NT RT_BIT(14)
13%define X86_EFL_RF RT_BIT(16)
14%define X86_EFL_VM RT_BIT(17)
15%define X86_EFL_AC RT_BIT(18)
16%define X86_EFL_VIF RT_BIT(19)
17%define X86_EFL_VIP RT_BIT(20)
18%define X86_EFL_ID RT_BIT(21)
19%define X86_EFL_IOPL_SHIFT 12
20%define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
21%define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
22%define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
23%define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
24%define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
25%define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
26%define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
27%define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
28%define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
29%define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
30%define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
31%define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
32%define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
33%define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
34%define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
35%define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
36%define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
37%define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
38%define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
39%define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
40%define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
41%define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
42%define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
43%define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
44%define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
45%define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
46%define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
47%define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
48%define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
49%define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
50%define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
51%define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
52%define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
53%define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
54%define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
55%define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
56%define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
57%define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
58%define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
59%define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
60%define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
61%define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
62%define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
63%define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
64%define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
65%define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
66%define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
67%define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
68%define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
69%define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
70%define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
71%define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
72%define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
73%define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
74%define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
75%define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
76%define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
77%define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
78%define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
79%define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
80%define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
81%define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
82%define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
83%define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
84%define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
85%define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
86%define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
87%define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
88%define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
89%define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
90%define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
91%define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
92%define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
93%define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
94%define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
95%define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
96%define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
97%define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
98%define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
99%define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
100%define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
101%define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
102%define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
103%define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
104%define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
105%define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
106%define X86_CR0_PE RT_BIT(0)
107%define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
108%define X86_CR0_MP RT_BIT(1)
109%define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
110%define X86_CR0_EM RT_BIT(2)
111%define X86_CR0_EMULATE_FPU RT_BIT(2)
112%define X86_CR0_TS RT_BIT(3)
113%define X86_CR0_TASK_SWITCH RT_BIT(3)
114%define X86_CR0_ET RT_BIT(4)
115%define X86_CR0_EXTENSION_TYPE RT_BIT(4)
116%define X86_CR0_NE RT_BIT(5)
117%define X86_CR0_NUMERIC_ERROR RT_BIT(5)
118%define X86_CR0_WP RT_BIT(16)
119%define X86_CR0_WRITE_PROTECT RT_BIT(16)
120%define X86_CR0_AM RT_BIT(18)
121%define X86_CR0_ALIGMENT_MASK RT_BIT(18)
122%define X86_CR0_NW RT_BIT(29)
123%define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
124%define X86_CR0_CD RT_BIT(30)
125%define X86_CR0_CACHE_DISABLE RT_BIT(30)
126%define X86_CR0_PG RT_BIT(31)
127%define X86_CR0_PAGING RT_BIT(31)
128%define X86_CR3_PWT RT_BIT(3)
129%define X86_CR3_PCD RT_BIT(4)
130%define X86_CR3_PAGE_MASK (0xfffff000)
131%define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
132%define X86_CR4_VME RT_BIT(0)
133%define X86_CR4_PVI RT_BIT(1)
134%define X86_CR4_TSD RT_BIT(2)
135%define X86_CR4_DE RT_BIT(3)
136%define X86_CR4_PSE RT_BIT(4)
137%define X86_CR4_PAE RT_BIT(5)
138%define X86_CR4_MCE RT_BIT(6)
139%define X86_CR4_PGE RT_BIT(7)
140%define X86_CR4_PCE RT_BIT(8)
141%define X86_CR4_OSFSXR RT_BIT(9)
142%define X86_CR4_OSXMMEEXCPT RT_BIT(10)
143%define X86_CR4_VMXE RT_BIT(13)
144%define X86_DR6_B0 RT_BIT(0)
145%define X86_DR6_B1 RT_BIT(1)
146%define X86_DR6_B2 RT_BIT(2)
147%define X86_DR6_B3 RT_BIT(3)
148%define X86_DR6_BD RT_BIT(13)
149%define X86_DR6_BS RT_BIT(14)
150%define X86_DR6_BT RT_BIT(15)
151%define X86_DR7_L0 RT_BIT(0)
152%define X86_DR7_G0 RT_BIT(1)
153%define X86_DR7_L1 RT_BIT(2)
154%define X86_DR7_G1 RT_BIT(3)
155%define X86_DR7_L2 RT_BIT(4)
156%define X86_DR7_G2 RT_BIT(5)
157%define X86_DR7_L3 RT_BIT(6)
158%define X86_DR7_G3 RT_BIT(7)
159%define X86_DR7_LE RT_BIT(8)
160%define X86_DR7_GE RT_BIT(9)
161%define X86_DR7_GD RT_BIT(13)
162%define X86_DR7_RW0_MASK (3 << 16)
163%define X86_DR7_LEN0_MASK (3 << 18)
164%define X86_DR7_RW1_MASK (3 << 20)
165%define X86_DR7_LEN1_MASK (3 << 22)
166%define X86_DR7_RW2_MASK (3 << 24)
167%define X86_DR7_LEN2_MASK (3 << 26)
168%define X86_DR7_RW3_MASK (3 << 28)
169%define X86_DR7_LEN3_MASK (3 << 30)
170%define X86_DR7_MB1_MASK (RT_BIT(10))
171%define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
172%define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
173%define X86_DR7_RW_EO 0
174%define X86_DR7_RW_WO 1
175%define X86_DR7_RW_IO 2
176%define X86_DR7_RW_RW 3
177%define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
178%define X86_DR7_LEN_BYTE 0
179%define X86_DR7_LEN_WORD 1
180%define X86_DR7_LEN_QWORD 2 /**< AMD64 long mode only. */
181%define X86_DR7_LEN_DWORD 3
182%define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
183%define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(6) | RT_BIT(7))
184%define MSR_IA32_APICBASE 0x1b
185%define MSR_IA32_FEATURE_CONTROL 0x3A
186%define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
187%define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
188%define MSR_IA32_SYSENTER_CS 0x174
189%define MSR_IA32_SYSENTER_ESP 0x175
190%define MSR_IA32_SYSENTER_EIP 0x176
191%define MSR_IA32_CR_PAT 0x277
192%define MSR_IA32_VMX_BASIC_INFO 0x480
193%define MSR_IA32_VMX_PINBASED_CTLS 0x481
194%define MSR_IA32_VMX_PROCBASED_CTLS 0x482
195%define MSR_IA32_VMX_EXIT_CTLS 0x483
196%define MSR_IA32_VMX_ENTRY_CTLS 0x484
197%define MSR_IA32_VMX_MISC 0x485
198%define MSR_IA32_VMX_CR0_FIXED0 0x486
199%define MSR_IA32_VMX_CR0_FIXED1 0x487
200%define MSR_IA32_VMX_CR4_FIXED0 0x488
201%define MSR_IA32_VMX_CR4_FIXED1 0x489
202%define MSR_IA32_VMX_VMCS_ENUM 0x48A
203%define MSR_K6_EFER 0xc0000080
204%define MSR_K6_EFER_SCE RT_BIT(0)
205%define MSR_K6_EFER_LME RT_BIT(8)
206%define MSR_K6_EFER_LMA RT_BIT(10)
207%define MSR_K6_EFER_NXE RT_BIT(11)
208%define MSR_K6_EFER_SVME RT_BIT(12)
209%define MSR_K6_EFER_LMSLE RT_BIT(13)
210%define MSR_K6_EFER_FFXSR RT_BIT(14)
211%define MSR_K6_STAR 0xc0000081
212%define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
213%define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
214%define MSR_K6_STAR_SEL_MASK 0xffff
215%define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
216%define MSR_K6_WHCR 0xc0000082
217%define MSR_K6_UWCCR 0xc0000085
218%define MSR_K6_PSOR 0xc0000087
219%define MSR_K6_PFIR 0xc0000088
220%define MSR_K7_EVNTSEL0 0xc0010000
221%define MSR_K7_EVNTSEL1 0xc0010001
222%define MSR_K7_EVNTSEL2 0xc0010002
223%define MSR_K7_EVNTSEL3 0xc0010003
224%define MSR_K7_PERFCTR0 0xc0010004
225%define MSR_K7_PERFCTR1 0xc0010005
226%define MSR_K7_PERFCTR2 0xc0010006
227%define MSR_K7_PERFCTR3 0xc0010007
228%define MSR_K8_LSTAR 0xc0000082
229%define MSR_K8_CSTAR 0xc0000083
230%define MSR_K8_SF_MASK 0xc0000084
231%define MSR_K8_FS_BASE 0xc0000100
232%define MSR_K8_GS_BASE 0xc0000101
233%define MSR_K8_KERNEL_GS_BASE 0xc0000102
234%define MSR_K8_TSC_AUX 0xc0000103
235%define MSR_K8_SYSCFG 0xc0010010
236%define MSR_K8_HWCR 0xc0010015
237%define MSR_K8_IORRBASE0 0xc0010016
238%define MSR_K8_IORRMASK0 0xc0010017
239%define MSR_K8_IORRBASE1 0xc0010018
240%define MSR_K8_IORRMASK1 0xc0010019
241%define MSR_K8_TOP_MEM1 0xc001001a
242%define MSR_K8_TOP_MEM2 0xc001001d
243%define MSR_K8_VM_CR 0xc0010114
244%define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
245%define MSR_K8_IGNNE 0xc0010115
246%define MSR_K8_SMM_CTL 0xc0010116
247%define MSR_K8_VM_HSAVE_PA 0xc0010117
248%define X86_PG_ENTRIES 1024
249%define X86_PG_PAE_ENTRIES 512
250%define X86_PG_PAE_PDPE_ENTRIES 4
251%define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
252%define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
253%define X86_PAGE_4K_SIZE _4K
254%define X86_PAGE_4K_SHIFT 12
255%define X86_PAGE_4K_OFFSET_MASK 0xfff
256%define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
257%define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
258%define X86_PAGE_2M_SIZE _2M
259%define X86_PAGE_2M_SHIFT 21
260%define X86_PAGE_2M_OFFSET_MASK 0x001fffff
261%define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
262%define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
263%define X86_PAGE_4M_SIZE _4M
264%define X86_PAGE_4M_SHIFT 22
265%define X86_PAGE_4M_OFFSET_MASK 0x003fffff
266%define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
267%define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
268%define X86_PTE_P RT_BIT(0)
269%define X86_PTE_RW RT_BIT(1)
270%define X86_PTE_US RT_BIT(2)
271%define X86_PTE_PWT RT_BIT(3)
272%define X86_PTE_PCD RT_BIT(4)
273%define X86_PTE_A RT_BIT(5)
274%define X86_PTE_D RT_BIT(6)
275%define X86_PTE_PAT RT_BIT(7)
276%define X86_PTE_G RT_BIT(8)
277%define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
278%define X86_PTE_PG_MASK ( 0xfffff000 )
279%define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
280%define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
281%define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
282%define X86_PTE_PAE_NX RT_BIT_64(63)
283%define X86_PT_SHIFT 12
284%define X86_PT_MASK 0x3ff
285%define X86_PT_PAE_SHIFT 12
286%define X86_PT_PAE_MASK 0x1ff
287%define X86_PDE_P RT_BIT(0)
288%define X86_PDE_RW RT_BIT(1)
289%define X86_PDE_US RT_BIT(2)
290%define X86_PDE_PWT RT_BIT(3)
291%define X86_PDE_PCD RT_BIT(4)
292%define X86_PDE_A RT_BIT(5)
293%define X86_PDE_PS RT_BIT(7)
294%define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
295%define X86_PDE_PG_MASK ( 0xfffff000 )
296%define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
297%define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
298%define X86_PDE_PAE_NX RT_BIT_64(63)
299%define X86_PDE4M_P RT_BIT(0)
300%define X86_PDE4M_RW RT_BIT(1)
301%define X86_PDE4M_US RT_BIT(2)
302%define X86_PDE4M_PWT RT_BIT(3)
303%define X86_PDE4M_PCD RT_BIT(4)
304%define X86_PDE4M_A RT_BIT(5)
305%define X86_PDE4M_D RT_BIT(6)
306%define X86_PDE4M_PS RT_BIT(7)
307%define X86_PDE4M_G RT_BIT(8)
308%define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
309%define X86_PDE4M_PAT RT_BIT(12)
310%define X86_PDE4M_PAT_SHIFT (12 - 7)
311%define X86_PDE4M_PG_MASK ( 0xffc00000 )
312%define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
313%define X86_PDE4M_PG_HIGH_SHIFT 19
314%define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
315%define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
316%define X86_PD_SHIFT 22
317%define X86_PD_MASK 0x3ff
318%define X86_PD_PAE_SHIFT 21
319%define X86_PD_PAE_MASK 0x1ff
320%define X86_PDPE_P RT_BIT(0)
321%define X86_PDPE_RW RT_BIT(1)
322%define X86_PDPE_US RT_BIT(2)
323%define X86_PDPE_PWT RT_BIT(3)
324%define X86_PDPE_PCD RT_BIT(4)
325%define X86_PDPE_A RT_BIT(5)
326%define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
327%define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
328%define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
329%define X86_PDPE_NX RT_BIT_64(63)
330%define X86_PDPT_SHIFT 30
331%define X86_PDPT_MASK_PAE 0x3
332%define X86_PDPT_MASK_AMD64 0x1ff
333%define X86_PML4E_P RT_BIT(0)
334%define X86_PML4E_RW RT_BIT(1)
335%define X86_PML4E_US RT_BIT(2)
336%define X86_PML4E_PWT RT_BIT(3)
337%define X86_PML4E_PCD RT_BIT(4)
338%define X86_PML4E_A RT_BIT(5)
339%define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
340%define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
341%define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
342%define X86_PML4E_NX RT_BIT_64(63)
343%define X86_PML4_SHIFT 39
344%define X86_PML4_MASK 0x1ff
345%define X86_SEL_TYPE_CODE 8
346%define X86_SEL_TYPE_MEMORY RT_BIT(4)
347%define X86_SEL_TYPE_ACCESSED 1
348%define X86_SEL_TYPE_DOWN 4
349%define X86_SEL_TYPE_CONF 4
350%define X86_SEL_TYPE_WRITE 2
351%define X86_SEL_TYPE_READ 2
352%define X86_SEL_TYPE_RO 0
353%define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
354%define X86_SEL_TYPE_RW 2
355%define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
356%define X86_SEL_TYPE_RO_DOWN 4
357%define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
358%define X86_SEL_TYPE_RW_DOWN 6
359%define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
360%define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
361%define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
362%define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
363%define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
364%define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
365%define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
366%define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
367%define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
368%define X86_SEL_TYPE_SYS_UNDEFINED 0
369%define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
370%define X86_SEL_TYPE_SYS_LDT 2
371%define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
372%define X86_SEL_TYPE_SYS_286_CALL_GATE 4
373%define X86_SEL_TYPE_SYS_TASK_GATE 5
374%define X86_SEL_TYPE_SYS_286_INT_GATE 6
375%define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
376%define X86_SEL_TYPE_SYS_UNDEFINED2 8
377%define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
378%define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
379%define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
380%define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
381%define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
382%define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
383%define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
384%define AMD64_SEL_TYPE_SYS_LDT 2
385%define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
386%define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
387%define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
388%define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
389%define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
390%define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
391%define X86_DESC_S RT_BIT(12)
392%define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
393%define X86_DESC_P RT_BIT(15)
394%define X86_DESC_AVL RT_BIT(20)
395%define X86_DESC_DB RT_BIT(22)
396%define X86_DESC_G RT_BIT(23)
397%define X86_SEL_SHIFT 3
398%define AMD64_SEL_SHIFT 4
399%define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
400%define X86_SEL_SHIFT_HC X86_SEL_SHIFT
401%define X86_SEL_MASK 0xfff8
402%define X86_SEL_LDT 0x0004
403%define X86_SEL_RPL 0x0003
404%define X86_TRAP_ERR_EXTERNAL 1
405%define X86_TRAP_ERR_IDT 2
406%define X86_TRAP_ERR_TI 4
407%define X86_TRAP_ERR_SEL_MASK 0xfff8
408%define X86_TRAP_ERR_SEL_SHIFT 3
409%define X86_TRAP_PF_P RT_BIT(0)
410%define X86_TRAP_PF_RW RT_BIT(1)
411%define X86_TRAP_PF_US RT_BIT(2)
412%define X86_TRAP_PF_RSVD RT_BIT(3)
413%define X86_TRAP_PF_ID RT_BIT(4)
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